diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/CHANGELOG dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/CHANGELOG --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/CHANGELOG 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/CHANGELOG 1970-01-01 00:00:00.000000000 +0000 @@ -1,112 +0,0 @@ -0.9.8 2013.05.05 - -- - -0.9.7 2013.04.15 - -- Octopus Net complete - -- changes for 3.8 kernels - - -0.9.6 2012.09.26 - -- basic Octopus Net support - - -0.9.5 2012.08.05 - -- cleanup - -0.9.4 2012.07.11 - -- support for new modulator bitstream 1.1 - -0.9.3 2012.06.13 - -- add hwid, remap attributes - -0.9.2 2012.06.08 - -- fix cxd2099 address writing optmization - -- add setting of TS output gap size through sysfs - gap_size = (gap_value*2)+4 - bit rate = 72 Mbps * 188 / gap_size - -0.9.1 2012.05.01 - -- support for reworked DVB-C modulator - -- support for multiple channels - -- move some funktions from tasklets back into - interrupt in those cases where it is more efficient - - -0.9.0 2012.03.05 - -- initial support of DVB-C modulator card - -- rework of redirect mechanism to support modulator - - -0.8.5 2012.01.30 - -- init DMA_BUFFER_CONTROL before starting input/output - in case it was not stopped properly before reboot - (can only happen on cards on PCIe extensions without reset line) - - -0.8.4 2012.01.04 - -- support for reading bridge serial number - -- test code for proper start/stop of redirected streams - - -0.8.3 2011.12.18 - -- add support for EEProms on 0x50 - -- make flashprog safer to use for end users - -- lost of kernel coding style adjustments - - -0.8.2 2011.10.14 - -- added some documentation in docs/ - -0.8.1 2011.10.13 - -- signal strength and SNR for STV0367/TDA18212 combo - -- serial number support via sysfs - - -0.8 2011.07.30 - -- Support for DVB-C/T cards with stv0367 demod and TDA18212 tuner - -- loopback TS for testing - -- support of octopus cards with fan, led and temperature sensors - via attributes. - -- redirect of TS to CI and back - - -0.7 2011.06.14 - -- Add IDs for new cards in ddbridge driver - -- Change dvb adapter allocation for ddbridge driver - Configurable with module parameter adapter_alloc: - - 0 = one adapter per io (old behavior) - 1 = one per tab with io present (tab connected to something) - 2 = one per tab regardless of something connected or not - 3 = one adapter for all devices of one card - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/Kbuild 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/Kbuild 1970-01-01 00:00:00.000000000 +0000 @@ -1,7 +0,0 @@ -# -# Makefile for the kernel multimedia device drivers. -# - -obj-y := dvb-core/ \ - ddbridge/ \ - frontends/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/Makefile 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,19 +0,0 @@ -KDIR ?= /lib/modules/$(shell uname -r)/build -PWD := $(shell pwd) - -MODDEFS := CONFIG_DVB_CORE=m CONFIG_DVB_DDBRIDGE=m CONFIG_DVB_DRXK=m CONFIG_DVB_TDA18271C2DD=m CONFIG_DVB_CXD2099=m CONFIG_DVB_LNBP21=m CONFIG_DVB_STV090x=m CONFIG_DVB_STV6110x=m CONFIG_DVB_STV0367=m CONFIG_DVB_TDA18212=m CONFIG_DVB_STV0367DD=m CONFIG_DVB_TDA18212DD=m CONFIG_DVB_OCTONET=m CONFIG_DVB_CXD2843=m - -all: - $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) $(MODDEFS) modules - $(MAKE) -C apps - -dep: - DIR=`pwd`; (cd $(TOPDIR); make SUBDIRS=$$DIR dep) - -install: all - $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules_install - -clean: - rm -rf */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules* - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/Makefile 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,16 +0,0 @@ -all: cit flashprog modt ddtest setmod - -cit: cit.c - gcc -o cit cit.c -lpthread - -modt: modt.c - gcc -o modt modt.c -lpthread - -setmod: setmod.c - gcc -o setmod setmod.c -I../include/ - -flashprog: flashprog.c - gcc -o flashprog flashprog.c - -ddtest: ddtest.c - gcc -o ddtest ddtest.c \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/cit.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/cit.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/cit.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/cit.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,138 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -uint8_t fill[188]={0x47, 0x1f, 0xff, 0x10, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff }; - -uint8_t ts[188]={0x47, 0x0a, 0xaa, 0x00, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff }; - -void proc_buf(uint8_t *buf, uint32_t *d) -{ - uint32_t c; - static uint32_t tc=0; - - - if (buf[1]==0x1f && buf[2]==0xff) { - //printf("fill\n"); - return; - } - if (buf[1]==0x9f && buf[2]==0xff) { - //printf("fill\n"); - return; - } - if (buf[1]==0x1a && buf[2]==0xbb) { - tc++; - if (!(tc&0xfff)) - printf("T %d\n", tc); - return; - } - printf("%02x %02x %02x %02x\n", buf[0], buf[1], buf [2], buf[3]); - if (buf[1]!=0x0a || buf[2]!=0xaa) - return; - c=(buf[4]<<24)|(buf[5]<<16)|(buf[6]<<8)|buf[7]; - if (c!=*d) { - printf("CONT ERROR: got %08x expected %08x\n", c, *d); - *d=c; - } else { - if (memcmp(ts+8, buf+8, 180)) - printf("error\n"); - if (!(c&0xffff)) - printf("R %d\n", c); - } - (*d)++; -} - -void *get_ts(void *a) -{ - uint8_t buf[188*1024]; - int len, off; - - int fdi=open("/dev/dvb/adapter0/ci0", O_RDONLY); - uint32_t d=0; - - while (1) { - len=read(fdi, buf, 188*1024); - if (len<0) - continue; - if (buf[0]!=0x47) { - read(fdi, buf, 1); - continue; - } - for (off=0; off>24); - cts[5]=(c>>16); - cts[6]=(c>>8); - cts[7]=c; - //write(fdo, fill, 188); - //printf("S %d\n", c); - c++; - //usleep(100000+0xffff&rand()); - //usleep(1000); - } - write(fdo, buf, 188*SNUM); - } -} - - -int main() -{ - pthread_t th; - - memset(ts+8, 180, 0x5a); - pthread_create(&th, NULL, get_ts, NULL); - usleep(10000); - send(); -} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/citin.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/citin.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/citin.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/citin.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,61 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void proc_ts(int i, uint8_t *buf) -{ - uint16_t pid=0x1fff&((buf[1]<<8)|buf[2]); - - if (buf[3]&0xc0) /* only descrambled packets */ - return; - /* only ORF */ - if (pid==160 || pid==161 || pid==1001||pid==13001 || pid==0) - write(1, buf, 188); -} - -#define TSBUFSIZE (100*188) - -void citest() -{ - uint8_t *buf; - uint8_t id; - int i, nts; - int len; - int ts=open("/dev/dvb/adapter4/sec0", O_RDONLY); - buf=(uint8_t *)malloc(TSBUFSIZE); - - - while(1) { - len=read(ts, buf, TSBUFSIZE); - if (len<0) { - continue; - } - if (buf[0]!=0x47) { - read(ts, buf, 1); - continue; - } - if (len%188) { /* should not happen */ - printf("blah\n"); - continue; - } - nts=len/188; - for (i=0; i -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TSBUFSIZE (100*188) - -void citest() -{ - uint8_t *buf; - uint8_t id; - int i, nts; - int len; - int ts0=open("/dev/dvb/adapter0/dvr0", O_RDONLY); - int ts1=open("/dev/dvb/adapter4/sec0", O_WRONLY); - int demux0=open("/dev/dvb/adapter0/demux0", O_RDWR); - - struct dmx_pes_filter_params pesFilterParams; - - pesFilterParams.input = DMX_IN_FRONTEND; - pesFilterParams.output = DMX_OUT_TS_TAP; - pesFilterParams.pes_type = DMX_PES_OTHER; - pesFilterParams.flags = DMX_IMMEDIATE_START; - - pesFilterParams.pid = 8192; - if (ioctl(demux0, DMX_SET_PES_FILTER, &pesFilterParams) < 0) { - printf("Could not set PES filter\n"); - return; - } - buf=(uint8_t *)malloc(TSBUFSIZE); - - while(1) { - len=read(ts0, buf, TSBUFSIZE); - if (len<=0) - break; - if (buf[0]!=0x47) - printf("oops\n"); - write(ts1, buf, len); - } -} - -int main() -{ - citest(); -} - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/ddtest.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/ddtest.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/ddtest.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/ddtest.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1137 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DDB_MAGIC 'd' - -struct ddb_id { - __u16 vendor; - __u16 device; - __u16 subvendor; - __u16 subdevice; - __u32 hw; - __u32 regmap; -}; - -struct ddb_flashio { - __u8 *write_buf; - __u32 write_len; - __u8 *read_buf; - __u32 read_len; -}; - -struct ddb_reg { - __u32 reg; - __u32 val; -}; - -struct ddb_mem { - __u32 off; - __u8 *buf; - __u32 len; -}; - -#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) -#define IOCTL_DDB_GPIO_IN _IOWR(DDB_MAGIC, 0x01, struct ddb_gpio) -#define IOCTL_DDB_GPIO_OUT _IOWR(DDB_MAGIC, 0x02, struct ddb_gpio) -#define IOCTL_DDB_ID _IOR(DDB_MAGIC, 0x03, struct ddb_id) -#define IOCTL_DDB_READ_REG _IOWR(DDB_MAGIC, 0x04, struct ddb_reg) -#define IOCTL_DDB_WRITE_REG _IOW(DDB_MAGIC, 0x05, struct ddb_reg) -#define IOCTL_DDB_READ_MEM _IOWR(DDB_MAGIC, 0x06, struct ddb_mem) -#define IOCTL_DDB_WRITE_MEM _IOR(DDB_MAGIC, 0x07, struct ddb_mem) - -typedef int (*COMMAND_FUNCTION)(int dev, int argc, char* argv[], uint32_t Flags); - -enum { - REPEAT_FLAG = 0x00000001, - SILENT_FLAG = 0x00000002, -}; - -enum { - UNKNOWN_FLASH = 0, - ATMEL_AT45DB642D = 1, - SSTI_SST25VF016B = 2, - SSTI_SST25VF032B = 3, -}; - -struct SCommand -{ - char* Name; - COMMAND_FUNCTION Function; - int Open; - char* Help; -}; - -// -------------------------------------------------------------------------------------------- - -void Dump(const uint8_t *b, uint32_t start, int l) -{ - int i, j; - - for (j = 0; j < l; j += 16, b += 16) { - printf("%04x: ", start + j); - for (i = 0; i < 16; i++) - if (i + j < l) - printf("%02x ", b[i]); - else - printf(" "); - printf(" |"); - for (i = 0; i < 16; i++) - if (i + j < l) - putchar((b[i] > 31 && b[i] < 127) ? b[i] : '.'); - printf("|\n"); - } -} - -int readreg(int dev, uint32_t RegAddress, uint32_t *pRegValue) -{ - struct ddb_reg reg = { .reg = RegAddress }; - int ret; - - ret = ioctl(dev, IOCTL_DDB_READ_REG, ®); - if (ret < 0) - return ret; - if (pRegValue) - *pRegValue = reg.val; - return 0; -} - -int writereg(int dev, uint32_t RegAddress, uint32_t RegValue) -{ - struct ddb_reg reg = { .reg = RegAddress, .val = RegValue}; - - return ioctl(dev, IOCTL_DDB_WRITE_REG, ®); -} - -int FlashIO(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen) -{ - struct ddb_flashio fio = { - .write_buf=wbuf, - .write_len=wlen, - .read_buf=rbuf, - .read_len=rlen, - }; - - return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio); -} - -int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len) -{ - int ret; - uint8_t cmd[4]; - uint32_t l; - - while (len) { - cmd[0] = 3; - cmd[1] = (addr >> 16) & 0xff; - cmd[2] = (addr >> 8) & 0xff; - cmd[3] = addr & 0xff; - - if (len > 1024) - l = 1024; - else - l = len; - ret = FlashIO(ddb, cmd, 4, buf, l); - if (ret < 0) - return ret; - addr += l; - buf += l; - len -= l; - } - return 0; -} - -int ReadFlash(int ddb, int argc, char *argv[], uint32_t Flags) -{ - uint32_t Start; - uint32_t Len; - uint8_t *Buffer; - - if (argc < 2 ) - return -1; - Start = strtoul(argv[0],NULL,16); - Len = strtoul(argv[1],NULL,16); - - Buffer = malloc(Len); - if (flashread(ddb, Buffer, Start, Len) < 0) { - printf("flashread error\n"); - free(Buffer); - return 0; - } - - Dump(Buffer,Start,Len); - - free(Buffer); - return 0; -} - - - -int FlashDetect(int dev) -{ - uint8_t Cmd = 0x9F; - uint8_t Id[3]; - - int r = FlashIO(dev, &Cmd, 1, Id, 3); - if (r < 0) - return r; - - if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x41) - r = SSTI_SST25VF016B; - else if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4A) - r = SSTI_SST25VF032B; - else if ( Id[0] == 0x1F && Id[1] == 0x28) - r = ATMEL_AT45DB642D; - else r = UNKNOWN_FLASH; - - switch(r) { - case UNKNOWN_FLASH : - printf("Unknown Flash Flash ID = %02x %02x %02x\n",Id[0],Id[1],Id[2]); - break; - case ATMEL_AT45DB642D : - printf("Flash: Atmel AT45DB642D 64 MBit\n"); - break; - case SSTI_SST25VF016B : - printf("Flash: SSTI SST25VF016B 16 MBit\n"); - break; - case SSTI_SST25VF032B : - printf("Flash: SSTI SST25VF032B 32 MBit\n"); - break; - } - return r; -} - -int FlashChipEraseAtmel(int dev) -{ - int err = 0; - // Note Sector 0 is in 2 parts - int i = 0; - while(i < 0x800000) - { - uint8_t Cmd[4]; - - printf(" Erase %08x\n",i); - Cmd[0] = 0x7C; // Sector Erase - Cmd[1] = ( (( i ) >> 16) & 0xFF ); - Cmd[2] = ( (( i ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - err = FlashIO(dev,Cmd,4,NULL,0); - if( err < 0 ) - break; - while (1) { - Cmd[0] = 0xD7; // Read Status register - err = FlashIO(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x80) == 0x80 ) break; - } - if( i == 0 ) i = 0x2000; - else if( i == 0x2000 ) i = 0x40000; - else i += 0x40000; - } - return 0; -} - -int FlashChipEraseSSTI(int dev) -{ - int err = 0; - uint8_t Cmd[4]; - - do - { - Cmd[0] = 0x50; // EWSR - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x01; // WRSR - Cmd[1] = 0x00; // BPx = 0, Unlock all blocks - err = FlashIO(dev,Cmd,2,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x06; // WREN - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x60; // CHIP Erase - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - while(1) - { - Cmd[0] = 0x05; // RDRS - err = FlashIO(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x01) == 0 ) break; - } - if( err < 0 ) break; - - Cmd[0] = 0x50; // EWSR - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x01; // WRSR - Cmd[1] = 0x1C; // BPx = 0, Lock all blocks - err = FlashIO(dev,Cmd,2,NULL,0); - } - while(0); - - if( err >= 0 ) printf("Flash erase succeeded\n"); - else printf("Flash erase failed\n"); - return 0; -} - - -int FlashWriteAtmel(int dev,uint32_t FlashOffset,uint8_t * Buffer,int BufferSize) -{ - int err = 0, i; - int BlockErase = BufferSize >= 8192; - uint8_t Cmd[4]; - - if( BlockErase ) { - for(i = 0; i < BufferSize; i += 8192 ) { - if( (i & 0xFFFF) == 0 ) - { - printf(" Erase %08x\n",FlashOffset + i); - } - Cmd[0] = 0x50; // Block Erase - Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - err = FlashIO(dev,Cmd,4,NULL,0); - if( err < 0 ) break; - - while(1) { - Cmd[0] = 0xD7; // Read Status register - err = FlashIO(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x80) == 0x80 ) break; - } - } - } - - for(i = 0; i < BufferSize; i += 1024 ) - { - if( (i & 0xFFFF) == 0 ) - { - printf(" Programm %08x\n",FlashOffset + i); - } - uint8_t Cmd[4 + 1024]; - Cmd[0] = 0x84; // Buffer 1 - Cmd[1] = 0x00; - Cmd[2] = 0x00; - Cmd[3] = 0x00; - memcpy(&Cmd[4],&Buffer[i],1024); - - err = FlashIO(dev,Cmd,4 + 1024,NULL,0); - if( err < 0 ) break; - - Cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase) - Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - - err = FlashIO(dev,Cmd,4,NULL,0); - if( err < 0 ) break; - - while(1) - { - Cmd[0] = 0xD7; // Read Status register - err = FlashIO(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x80) == 0x80 ) break; - } - if( err < 0 ) break; - } - return err; -} - -// ************************************************************************************** -// BUG: Erasing and writing an incomplete image will result in an failure to boot golden image. -// FIX: Write the new image from high to low addresses - -int FlashWriteSSTI(int dev,uint32_t FlashOffset,uint8_t * Buffer,int BufferSize) -{ - int err = 0, i, j; - uint8_t Cmd[6]; - - if( (BufferSize % 4096) != 0 ) return -1; // Must be multiple of sector size - - do - { - Cmd[0] = 0x50; // EWSR - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x01; // WRSR - Cmd[1] = 0x00; // BPx = 0, Unlock all blocks - err = FlashIO(dev,Cmd,2,NULL,0); - if( err < 0 ) break; - - for (i = 0; i < BufferSize; i += 4096 ) - { - if( (i & 0xFFFF) == 0 ) - { - printf(" Erase %08x\n",FlashOffset + i); - } - - Cmd[0] = 0x06; // WREN - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x20; // Sector erase ( 4Kb) - Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - err = FlashIO(dev,Cmd,4,NULL,0); - if( err < 0 ) break; - - while(1) - { - Cmd[0] = 0x05; // RDRS - err = FlashIO(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x01) == 0 ) break; - } - if( err < 0 ) break; - - } - if( err < 0 ) break; - - - for (j = BufferSize - 4096; j >= 0; j -= 4096 ) - { - if( (j & 0xFFFF) == 0 ) - { - printf(" Programm %08x\n",FlashOffset + j); - } - - for (i = 0; i < 4096; i += 2 ) - { - - if( i == 0 ) - { - Cmd[0] = 0x06; // WREN - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0xAD; // AAI - Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - Cmd[4] = Buffer[j+i]; - Cmd[5] = Buffer[j+i+1]; - err = FlashIO(dev,Cmd,6,NULL,0); - } - else - { - Cmd[0] = 0xAD; // AAI - Cmd[1] = Buffer[j+i]; - Cmd[2] = Buffer[j+i+1]; - err = FlashIO(dev,Cmd,3,NULL,0); - } - if( err < 0 ) break; - - while(1) - { - Cmd[0] = 0x05; // RDRS - err = FlashIO(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x01) == 0 ) break; - } - if( err < 0 ) break; - } - if( err < 0 ) break; - - Cmd[0] = 0x04; // WDIS - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - } - if( err < 0 ) break; - - - Cmd[0] = 0x50; // EWSR - err = FlashIO(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x01; // WRSR - Cmd[1] = 0x1C; // BPx = 0, Lock all blocks - err = FlashIO(dev,Cmd,2,NULL,0); - - } - while(0); - return err; -} - - - - - -// -------------------------------------------------------------------------------------------- - -int ReadDeviceMemory(int dev,int argc, char* argv[],uint32_t Flags) -{ - uint32_t Start; - uint32_t Len; - uint8_t * Buffer; - - if( argc < 2 ) return -1; - - Start = strtoul(argv[0],NULL,16); - Len = strtoul(argv[1],NULL,16); - if( Start > 0xFFFF || Start + Len > 0x10000 || Len == 0 ) return -1; - Buffer = malloc(Len); - - { - struct ddb_mem mem = {.off=Start, .len=Len, .buf=Buffer }; - ioctl(dev, IOCTL_DDB_READ_MEM, &mem); - } - Dump(Buffer,Start,Len); - free(Buffer); - return 0; -} - -int WriteDeviceMemory(int dev,int argc, char* argv[],uint32_t Flags) -{ - uint8_t * Buffer; - uint32_t Start, Len, i; - - if( argc < 2 ) return -1; - Start = strtoul(argv[0],NULL,16); - Len = argc - 1; - if( Start > 0xFFFF || Start + Len > 0x10000 || Len == 0 ) return -1; - Buffer = malloc(Len + sizeof(uint32_t)); - if( Buffer == NULL ) - return -2; - - *((uint32_t *)Buffer) = Start; - for (i = 0; i < Len; i += 1 ) - Buffer[i+sizeof(uint32_t)] = (uint8_t) strtoul(argv[i+1],NULL,16); - - - { - struct ddb_mem mem = {.off=Start, .len=Len, .buf=Buffer+4 }; - ioctl(dev, IOCTL_DDB_WRITE_MEM, &mem); - } - free(Buffer); - return 0; -} - -int FillDeviceMemory(int dev,int argc, char* argv[],uint32_t Flags) -{ - uint32_t Start, Len; - uint8_t * Buffer; - uint8_t Value = 0; - - if( argc < 2 ) return -1; - Start = strtoul(argv[0],NULL,16); - Len = strtoul(argv[1],NULL,16); - - if (Start > 0xFFFF || Start + Len > 0x10000 || Len == 0 ) - return -1; - - Buffer = malloc(Len); - if (Buffer == NULL) - return -2; - - if(argc > 2) - Value = (uint8_t) strtoul(argv[2],NULL,16); - memset(Buffer, Value, Len); - { - struct ddb_mem mem = {.off=Start, .len=Len, .buf=Buffer }; - ioctl(dev, IOCTL_DDB_WRITE_MEM, &mem); - } - free(Buffer); - return 0; -} - -int GetSetRegister(int dev,int argc, char* argv[],uint32_t Flags) -{ - uint32_t i; - - if( argc < 1 ) return -1; - - uint32_t Reg[2]; - char* p; - Reg[0] = strtoul(argv[0],&p,16) & 0xFFFC; - uint32_t LastReg = Reg[0]; - - if( Reg[0] >= 0x10000 ) return -1; - - if( argc == 1 ) - { - if( *p == '-' ) - { - LastReg = strtoul(&p[1],NULL,16) & 0xFFFC; - } - else if( *p == '+' ) - { - LastReg = Reg[0] + (strtoul(&p[1],NULL,16) - 1) * 4; - } - } - - uint32_t NumRegs = (LastReg - Reg[0]) / 4 + 1; - - if( LastReg >= 0x10000 || LastReg < Reg[0] ) return -1; - - if( argc > 1 ) - { - Reg[1] = strtoul(argv[1],NULL,0); - if( writereg(dev,Reg[0],Reg[1]) != 0 ) - { - return -2; - } - } - else - { - for(i = 0; i < NumRegs; i += 1 ) - { - if (readreg(dev,Reg[0],&Reg[1]) < 0 ) - { - return -2; - } - printf(" Register %02X = %08X (%d)\n",Reg[0],Reg[1],Reg[1]); - Reg[0] += 4; - } - } - - return 0; -} - - -// ----------------------------------------------------------------------------------------------------------- -// ----------------------------------------------------------------------------------------------------------- -// ----------------------------------------------------------------------------------------------------------- - -int FlashIOC(int dev,int argc, char* argv[],uint32_t Flags) -{ - uint8_t *Buffer; - uint32_t tmp = 0, i; - uint32_t WriteLen = (argc-1); - uint32_t BufferLength = WriteLen; - uint32_t ReadLen; - - if( argc < 2 ) return -1; - - ReadLen = strtoul(argv[argc-1],NULL,0); - if( ReadLen > BufferLength ) BufferLength = ReadLen ; - - Buffer = malloc(WriteLen); - - for(i = 0; i < (argc-1); i += 1 ) - { - tmp = strtoul(argv[i],NULL,16); - if( tmp > 255 ) - { - return -1; - } - Buffer[i] = (uint8_t) tmp; - } - - if( FlashIO(dev,Buffer,WriteLen,Buffer,ReadLen) < 0 ) - { - return 0; - } - - if( ReadLen > 0 ) - Dump(Buffer,0,ReadLen); - - return 0; - -} - -// ----------------------------------------------------------------------------------------------------------- -// ----------------------------------------------------------------------------------------------------------- -// ----------------------------------------------------------------------------------------------------------- - -// Searach and return FPGA ID from Buffer, buffer size must be 64 kByte or larger -uint32_t GetFPGA_ID(uint8_t * Buffer) -{ - uint32_t ID = 0xFFFFFF; - int Len = 0x10000 - 16; - while( Len > 0 ) - { - if( Buffer[0] == 0xBD && Buffer[1] == 0xB3 ) - { - ID = ((Buffer[6]) << 24) | ((Buffer[7]) << 16) | ((Buffer[8]) << 8) | ((Buffer[9])); - break; - } - if( Buffer[0] == 0xBC && Buffer[1] == 0xB3 ) - { - // Proteced bitstream. - ID = ((Buffer[2]^Buffer[6]^Buffer[10]^Buffer[14]) << 24) - | ((Buffer[3]^Buffer[7]^Buffer[11]^Buffer[15]) << 16) - | ((Buffer[4]^Buffer[8]^Buffer[12]^Buffer[16]) << 8) - | ((Buffer[5]^Buffer[9]^Buffer[13]^Buffer[17])); - break; - } - - Len -= 1; - Buffer += 1; - } - - return ID; -} - - -int FlashProg(int dev,int argc, char* argv[],uint32_t Flags) -{ - uint8_t * Buffer = NULL; - int BufferSize = 0; - int BlockErase = 0; - uint32_t FlashOffset = 0x10000; - int SectorSize = 0; - int FlashSize = 0; - int ValidateFPGAType = 1; - int Flash; - uint32_t Id1, Id2; - - if( argc < 1 ) - return -1; - Flash = FlashDetect(dev); - switch(Flash) - { - case ATMEL_AT45DB642D: SectorSize = 1024; FlashSize = 0x800000; break; - case SSTI_SST25VF016B: SectorSize = 4096; FlashSize = 0x200000; break; - case SSTI_SST25VF032B: SectorSize = 4096; FlashSize = 0x400000; break; - } - if (SectorSize == 0) - return 0; - - if( strncasecmp("-SubVendorID",argv[0],strlen(argv[0])) == 0 ) - { - if( argc < 2 ) return -1; - - uint32_t SubVendorID = strtoul(argv[1],NULL,16); - - BufferSize = SectorSize; - FlashOffset = 0; - - Buffer = malloc(BufferSize); - if( Buffer == NULL ) - { - printf("out of memory\n"); - return 0; - } - memset(Buffer,0xFF,BufferSize); - - Buffer[0] = ( ( SubVendorID >> 24 ) & 0xFF ); - Buffer[1] = ( ( SubVendorID >> 16 ) & 0xFF ); - Buffer[2] = ( ( SubVendorID >> 8 ) & 0xFF ); - Buffer[3] = ( ( SubVendorID ) & 0xFF ); - - } - else if( strncasecmp("-Jump",argv[0],strlen(argv[0])) == 0 ) - { - uint32_t Jump; - if( argc < 2 ) return -1; - - Jump = strtoul(argv[1],NULL,16); - - BufferSize = SectorSize; - FlashOffset = FlashSize - SectorSize; - - Buffer = malloc(BufferSize); - if( Buffer == NULL ) - { - printf("out of memory\n"); - return 0; - } - memset(Buffer,0xFF,BufferSize); - - memset(&Buffer[BufferSize - 256 + 0x10],0x00,16); - - Buffer[BufferSize - 256 + 0x10] = 0xbd; - Buffer[BufferSize - 256 + 0x11] = 0xb3; - Buffer[BufferSize - 256 + 0x12] = 0xc4; - Buffer[BufferSize - 256 + 0x1a] = 0xfe; - Buffer[BufferSize - 256 + 0x1e] = 0x03; - Buffer[BufferSize - 256 + 0x1f] = ( ( Jump >> 16 ) & 0xFF ); - Buffer[BufferSize - 256 + 0x20] = ( ( Jump >> 8 ) & 0xFF ); - Buffer[BufferSize - 256 + 0x21] = ( ( Jump ) & 0xFF ); - - } - else - { - if( argc > 1 ) - { - FlashOffset = strtoul(argv[1],NULL,16); - ValidateFPGAType = 0; // Don't validate if offset is given - } - - int fh = open(argv[0],O_RDONLY); - if( fh < 0 ) - { - printf("File not found \n"); - return 0; - } - - int fsize = lseek(fh,0,SEEK_END); - - if( fsize > 4000000 || fsize < SectorSize ) - { - close(fh); - printf("Invalid File Size \n"); - return 0; - } - - if( Flash == ATMEL_AT45DB642D ) - { - BlockErase = fsize >= 8192; - if( BlockErase ) - BufferSize = (fsize + 8191) & ~8191; - else - BufferSize = (fsize + 1023) & ~1023; - } - else - { - BufferSize = (fsize + SectorSize - 1 ) & ~(SectorSize - 1); - } - printf(" Size %08x\n",BufferSize); - - Buffer = malloc(BufferSize); - if( Buffer == NULL ) - { - close(fh); - printf("out of memory\n"); - return 0; - } - - memset(Buffer,0xFF,BufferSize); - lseek(fh,0,SEEK_SET); - read(fh,Buffer,fsize); - close(fh); - - if( BufferSize >= 0x10000 ) - { - int i; - // Clear header - for(i = 0; i < 0x200; i += 1 ) - { - if( *(uint16_t *)(&Buffer[i]) == 0xFFFF ) - break; - Buffer[i] = 0xFF; - } - // Place our own header - - if( ValidateFPGAType ) - { - uint8_t * CmpBuffer = malloc(0x10000); - if( CmpBuffer == NULL ) - { - free(Buffer); - printf("out of memory\n"); - return 0; - } - if (flashread(dev, CmpBuffer, FlashOffset, 0x10000)<0) { - printf("Ioctl returns error\n"); - free(Buffer); - free(CmpBuffer); - return 0; - } - - Id1 = GetFPGA_ID(Buffer); - Id2 = GetFPGA_ID(CmpBuffer); - - if (Id2 != 0xFFFFFFFF ) - { - if( Id1 == 0xFFFFFFFF || Id1 != Id2 ) - { - printf(" FPGA ID mismatch\n"); - free(Buffer); - free(CmpBuffer); - return 0; - } - } - } - - } - } - - int err = -1; - - switch(Flash) - { - case ATMEL_AT45DB642D: err = FlashWriteAtmel(dev,FlashOffset,Buffer,BufferSize); break; - case SSTI_SST25VF016B: - case SSTI_SST25VF032B: err = FlashWriteSSTI(dev,FlashOffset,Buffer,BufferSize); break; - } - - if( err < 0 ) printf(" Programm Error\n"); - else printf(" Programm Done\n"); - - free(Buffer); - return 0; -} - -// ----------------------------------------------------------------------------------------------------------- -// ----------------------------------------------------------------------------------------------------------- -// ----------------------------------------------------------------------------------------------------------- - -int FlashVerify(int dev,int argc, char* argv[],uint32_t Flags) -{ - if( argc < 1 ) return -1; - - uint8_t * Buffer = NULL; - uint8_t * Buffer2 = NULL; - int BufferSize = 0; - int BlockErase = 0; - uint32_t FlashOffset = 0x10000; - int fsize, fh; - int i; - int err = 0; - - if( argc > 1 ) - { - FlashOffset = strtoul(argv[1],NULL,16); - } - - fh = open(argv[0],O_RDONLY); - if( fh < 0 ) - { - printf("File not found \n"); - return 0; - } - - fsize = lseek(fh,0,SEEK_END); - - if( fsize > 4000000 || fsize < 1024 ) - { - close(fh); - printf("Invalid File Size \n"); - return 0; - } - BlockErase = fsize >= 8192; - - BufferSize = (fsize + 1023) & ~1023; - printf(" Size %08x\n",BufferSize); - - Buffer = malloc(BufferSize); - if( Buffer == NULL ) - { - close(fh); - printf("out of memory\n"); - return 0; - } - - Buffer2 = malloc(BufferSize); - if( Buffer2 == NULL ) - { - close(fh); - free(Buffer); - printf("out of memory\n"); - return 0; - } - memset(Buffer,0xFF,BufferSize); - memset(Buffer2,0xFF,BufferSize); - lseek(fh,0,SEEK_SET); - read(fh,Buffer,fsize); - close(fh); - - if( BufferSize >= 0x10000 ) - { - int i; - // Clear header - for(i = 0; i < 0x200; i += 1 ) - { - if( *(uint16_t *)(&Buffer[i]) == 0xFFFF ) break; - Buffer[i] = 0xFF; - } - // Place our own header - } - if (flashread(dev, Buffer2, FlashOffset, BufferSize)<0) { - printf("Ioctl returns error\n"); - free(Buffer); - free(Buffer2); - return 0; - } - for (i=0; i 2) { - val = strtoul(argv[2], NULL, 16); - writereg(dev, 0x2c, val); - writereg(dev, 0x20, 0x03); - do { - readreg(dev, 0x20, &val); - } while (val & 0x02); - } else { - writereg(dev, 0x20, 0x07); - do { - readreg(dev, 0x20, &val); - } while (val & 0x02); - readreg(dev, 0x2c, &val); - printf("%04x\n", val); - } - return 0; -} - -struct SCommand CommandTable[] = -{ - { "memread", ReadDeviceMemory, 1, "Read Device Memory : memread " }, - { "memfill", FillDeviceMemory, 1, "Fill Device Memory : memfill []" }, - { "memwrite", WriteDeviceMemory, 1, "Write Device Memory : memwrite .." }, - { "register", GetSetRegister, 1, "Get/Set Register : reg |<[0x]regnum> [[0x]value(32)]" }, - - { "flashread", ReadFlash, 1, "Read Flash : flashread " }, - { "flashio", FlashIO, 1, "Flash IO : flashio .. " }, - { "flashprog", FlashProg, 1, "Flash Programming : flashprog [
]" }, - { "flashprog", FlashProg, 1, "Flash Programming : flashprog -SubVendorID " }, - { "flashprog", FlashProg, 1, "Flash Programming : flashprog -Jump
" }, - { "flashverify", FlashVerify, 1, "Flash Verify : flashverify [
]" }, - { "flasherase", FlashErase, 1, "FlashErase : flasherase" }, - //{ "flashtest", FlashTest, 1, "FlashTest : flashtest" }, - - - { "mdio", mdio, 1, "mdio : mdio []" }, - { NULL,NULL,0 } -}; - -void Help() -{ - int i = 0; - while (CommandTable[i].Name != NULL) { - printf(" %s\n", CommandTable[i].Help); - i += 1; - } -} - - -int main(int argc, char **argv) -{ - int cmd = 0, status; - int i = 1; - int Device = 0; - uint32_t Flags = 0; - int CmdIndex = 0; - int dev; - char ddbname[80]; - - if( argc < 2 ) { - Help(); - return 1; - } - - - while( i < argc ) - { - if (*argv[i] != '-') - break; - if (strcmp(argv[i],"-r") == 0 || strcmp(argv[i],"--repeat") == 0 ) - Flags |= REPEAT_FLAG; - else if( strcmp(argv[i],"-s") == 0 || strcmp(argv[i],"--silent") == 0 ) - Flags |= SILENT_FLAG; - else if( strcmp(argv[i],"-d") == 0 || strcmp(argv[i],"--device") == 0 ) { - i += 1; - if( i < argc ) Device = strtoul(argv[i],NULL,0); - } else if( strcmp(argv[i],"-?") == 0 || strcmp(argv[i],"--help") == 0 ) { - Help(); - return 1; - } - i += 1; - } - - if (i >= argc || Device > 99) { - Help(); - return 1; - } - - sprintf(ddbname, "/dev/ddbridge/card%d", Device); - dev=open(ddbname, O_RDWR); - if (dev < 0) { - printf("Could not open device\n"); - return -1; - } - - CmdIndex = i; - - while( CommandTable[cmd].Name != NULL ) { - if (strncasecmp(CommandTable[cmd].Name,argv[CmdIndex],strlen(argv[CmdIndex])) == 0 ) - break; - cmd += 1; - } - - if (CommandTable[cmd].Name == NULL) { - Help(); - return 1; - } - - if( Flags != 0 ) printf(" Flags: %s %s\n",(Flags&REPEAT_FLAG)?"Repeat":"",(Flags&SILENT_FLAG)?"Silent":""); - status = (*CommandTable[cmd].Function)(dev,argc-CmdIndex-1,&argv[CmdIndex+1],Flags); - - if( status == -1 ) - { - printf(" %s\n",CommandTable[cmd].Help); - } - - - return 0; -} - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/flashprog.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/flashprog.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/flashprog.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/flashprog.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,574 +0,0 @@ -/* -/* flashprog - Programmer for flash on Digital Devices Octopus - * - * Copyright (C) 2010-2011 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DDB_MAGIC 'd' - -struct ddb_id { - __u16 vendor; - __u16 device; - __u16 subvendor; - __u16 subdevice; - __u32 hw; - __u32 regmap; -}; - -struct ddb_flashio { - __u8 *write_buf; - __u32 write_len; - __u8 *read_buf; - __u32 read_len; -}; - -#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) -#define IOCTL_DDB_ID _IOR(DDB_MAGIC, 0x03, struct ddb_id) - - -int flashio(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen) -{ - struct ddb_flashio fio = { - .write_buf=wbuf, - .write_len=wlen, - .read_buf=rbuf, - .read_len=rlen, - }; - - return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio); -} - -enum { - UNKNOWN_FLASH = 0, - ATMEL_AT45DB642D = 1, - SSTI_SST25VF016B = 2, - SSTI_SST25VF032B = 3, -}; - - -int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len) -{ - uint8_t cmd[4]= {0x03, (addr >> 16) & 0xff, - (addr >> 8) & 0xff, addr & 0xff}; - - return flashio(ddb, cmd, 4, buf, len); -} - -int flashdump(int ddb, uint32_t addr, uint32_t len) -{ - int i, j; - uint8_t buf[32]; - int bl = sizeof(buf); - - for (j=0; j= 8192; - int i; - - if (BlockErase) { - for(i = 0; i < BufferSize; i += 8192 ) { - uint8_t Cmd[4]; - if( (i & 0xFFFF) == 0 ) - printf(" Erase %08x\n",FlashOffset + i); - Cmd[0] = 0x50; // Block Erase - Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - err = flashio(dev,Cmd,4,NULL,0); - if( err < 0 ) break; - - while( 1 ) - { - Cmd[0] = 0xD7; // Read Status register - err = flashio(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x80) == 0x80 ) break; - } - } - } - - for(i = 0; i < BufferSize; i += 1024 ) - { - uint8_t Cmd[4 + 1024]; - if( (i & 0xFFFF) == 0 ) - { - printf(" Program %08x\n",FlashOffset + i); - } - Cmd[0] = 0x84; // Buffer 1 - Cmd[1] = 0x00; - Cmd[2] = 0x00; - Cmd[3] = 0x00; - memcpy(&Cmd[4],&Buffer[i],1024); - - err = flashio(dev,Cmd,4 + 1024,NULL,0); - if( err < 0 ) break; - - Cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase) - Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - - err = flashio(dev,Cmd,4,NULL,0); - if( err < 0 ) break; - - while( 1 ) - { - Cmd[0] = 0xD7; // Read Status register - err = flashio(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x80) == 0x80 ) break; - } - if( err < 0 ) break; - } - return err; -} - -int FlashWriteSSTI(int dev, uint32_t FlashOffset, uint8_t *Buffer, int BufferSize) -{ - int err = 0; - uint8_t Cmd[6]; - int i, j; - - // Must be multiple of sector size - if( (BufferSize % 4096) != 0 ) - return -1; - - do { - Cmd[0] = 0x50; // EWSR - err = flashio(dev,Cmd,1,NULL,0); - if( err < 0 ) - break; - - Cmd[0] = 0x01; // WRSR - Cmd[1] = 0x00; // BPx = 0, Unlock all blocks - err = flashio(dev,Cmd,2,NULL,0); - if( err < 0 ) - break; - - for(i = 0; i < BufferSize; i += 4096 ) { - if( (i & 0xFFFF) == 0 ) - printf(" Erase %08x\n",FlashOffset + i); - Cmd[0] = 0x06; // WREN - err = flashio(dev,Cmd,1,NULL,0); - if( err < 0 ) - break; - - Cmd[0] = 0x20; // Sector erase ( 4Kb) - Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - err = flashio(dev,Cmd,4,NULL,0); - if( err < 0 ) - break; - - while(1) { - Cmd[0] = 0x05; // RDRS - err = flashio(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x01) == 0 ) break; - } - if( err < 0 ) break; - } - if( err < 0 ) - break; - for(j = BufferSize - 4096; j >= 0; j -= 4096 ) { - if( (j & 0xFFFF) == 0 ) - printf(" Program %08x\n",FlashOffset + j); - - for(i = 0; i < 4096; i += 2 ) { - if( i == 0 ) { - Cmd[0] = 0x06; // WREN - err = flashio(dev,Cmd,1,NULL,0); - if( err < 0 ) - break; - - Cmd[0] = 0xAD; // AAI - Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF ); - Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF ); - Cmd[3] = 0x00; - Cmd[4] = Buffer[j+i]; - Cmd[5] = Buffer[j+i+1]; - err = flashio(dev,Cmd,6,NULL,0); - } else { - Cmd[0] = 0xAD; // AAI - Cmd[1] = Buffer[j+i]; - Cmd[2] = Buffer[j+i+1]; - err = flashio(dev,Cmd,3,NULL,0); - } - if( err < 0 ) - break; - - while(1) { - Cmd[0] = 0x05; // RDRS - err = flashio(dev,Cmd,1,&Cmd[0],1); - if( err < 0 ) break; - if( (Cmd[0] & 0x01) == 0 ) break; - } - if( err < 0 ) break; - } - if( err < 0 ) break; - - Cmd[0] = 0x04; // WDIS - err = flashio(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - } - if( err < 0 ) break; - - Cmd[0] = 0x50; // EWSR - err = flashio(dev,Cmd,1,NULL,0); - if( err < 0 ) break; - - Cmd[0] = 0x01; // WRSR - Cmd[1] = 0x1C; // BPx = 0, Lock all blocks - err = flashio(dev,Cmd,2,NULL,0); - } while(0); - return err; -} - -void get_id(int ddb, struct ddb_id *ddbid) { - uint8_t id[4]; - - if (ioctl(ddb, IOCTL_DDB_ID, ddbid)>=0) - return; - memset(ddbid, 0, sizeof(*ddbid)); - flashread(ddb, id, 0, 4); - printf("%02x %02x %02x %02x\n", - id[0], id[1], id[2], id[3]); - ddbid->subvendor=(id[0] << 8) | id[1]; - ddbid->subdevice=(id[2] << 8) | id[3]; -} - -int sure() -{ - char c; - - printf("\n\nWARNING! Flashing a new FPGA image might make your card unusable!\n"); - printf("\n\nWARNUNG! Das Flashen eines neuen FPGA-Images kann Ihre Karte unbrauchbar machen.\n"); - printf("\n\nAre you sure? y/n?"); - printf("\n\nSind Sie sicher? y/n?"); - fflush(0); - c = getchar(); - if (c!='y') { - printf("\nFlashing aborted.\n\n"); - return -1; - } - printf("\nStarting to flash\n\n"); - return 0; -} - - -int main(int argc, char **argv) -{ - char ddbname[80]; - int type = 0; - struct ddb_id ddbid; - uint8_t *buffer; - int BufferSize = 0; - int BlockErase = 0; - uint32_t FlashOffset = 0x10000; - int ddb; - int i, err; - int SectorSize=0; - int FlashSize=0; - int Flash; - - uint32_t svid=0, jump=0, dump=0; - int bin; - - int ddbnum = 0; - int force = 0; - - while (1) { - int option_index = 0; - int c; - static struct option long_options[] = { - {"svid", required_argument, NULL, 's'}, - {"help", no_argument , NULL, 'h'}, - {"force", no_argument , NULL, 'f'}, - {0, 0, 0, 0} - }; - c = getopt_long(argc, argv, - "d:n:s:o:l:dfhj", - long_options, &option_index); - if (c==-1) - break; - - switch (c) { - case 'd': - dump = strtoul(optarg, NULL, 16); - break; - case 's': - svid = strtoul(optarg, NULL, 16); - break; - case 'o': - FlashOffset = strtoul(optarg, NULL, 16); - break; - case 'n': - ddbnum = strtol(optarg, NULL, 0); - break; - case 'f': - force = 1; - break; - case 'j': - jump = 1; - break; - case 'h': - default: - break; - - } - } - if (optind> 24 ) & 0xFF); - buffer[1] = ((svid >> 16 ) & 0xFF); - buffer[2] = ((svid >> 8 ) & 0xFF); - buffer[3] = ((svid ) & 0xFF); - } else { - int fh, i; - int fsize; - char *fname; - - switch (type) { - default: - case 0: - fname="DVBBridgeV1B_DVBBridgeV1B.bit"; - printf("Octopus\n"); - break; - case 1: - fname="CIBridgeV1B_CIBridgeV1B.bit"; - printf("Octopus CI\n"); - break; - case 2: - fname="DVBModulatorV1B_DVBModulatorV1B.bit"; - printf("Modulator\n"); - break; - case 3: - fname="DVBBridgeV1A_DVBBridgeV1A.bit"; - printf("Octopus 35\n"); - break; - } - //fname="DVBNetPCIeV1A_DVBNetPCIeV1A.bit"; - //fname="DVBNetV1A_DVBNetV1A.bit"; - - fh = open(fname, O_RDONLY); - if (fh < 0 ) { - printf("File not found \n"); - return 0; - } - printf("Using bitstream %s\n", fname); - - fsize = lseek(fh,0,SEEK_END); - if( fsize > 4000000 || fsize < SectorSize ) - { - close(fh); - printf("Invalid File Size \n"); - return 0; - } - - if( Flash == ATMEL_AT45DB642D ) { - BlockErase = fsize >= 8192; - if( BlockErase ) - BufferSize = (fsize + 8191) & ~8191; - else - BufferSize = (fsize + 1023) & ~1023; - } else { - BufferSize = (fsize + SectorSize - 1 ) & ~(SectorSize - 1); - } - printf(" Size %08x, target %08x\n", BufferSize, FlashOffset); - - buffer = malloc(BufferSize); - - if( buffer == NULL ) { - close(fh); - printf("out of memory\n"); - return 0; - } - - memset(buffer, 0xFF, BufferSize); - lseek(fh, 0, SEEK_SET); - read(fh, buffer, fsize); - close(fh); - - if (BufferSize >= 0x10000) { - for(i = 0; i < 0x200; i += 1 ) { - if ( *(uint16_t *) (&buffer[i]) == 0xFFFF ) - break; - buffer[i] = 0xFF; - } - } - } - if (!force && sure()<0) - return 0; - switch(Flash) { - case ATMEL_AT45DB642D: - err = FlashWriteAtmel(ddb, FlashOffset, buffer, BufferSize); - break; - case SSTI_SST25VF016B: - case SSTI_SST25VF032B: - err = FlashWriteSSTI(ddb, FlashOffset, buffer, BufferSize); - break; - } - - if (err < 0) - printf("Programming Error\n"); - else - printf("Programming Done\n"); - - free(buffer); - return 0; -} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/modt.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/modt.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/modt.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/modt.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,36 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -#define SNUM 1000 -//671 -void send(void) -{ - uint8_t buf[188*SNUM], *cts; - int i; - uint32_t c=0; - int fdo; - - fdo=open("/dev/dvb/adapter0/mod0", O_WRONLY); - - - while (1) { - read(0, buf, sizeof(buf)); - write(fdo, buf, 188*SNUM); - } -} - - -int main() -{ - send(); -} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/setmod.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/setmod.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/apps/setmod.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/apps/setmod.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,31 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -int main() -{ - int fd; - struct dvb_mod_params mp; - struct dvb_mod_channel_params mc; - - fd = open("/dev/dvb/adapter1/mod0", O_RDONLY); - - mp.base_frequency = 730000000; - mp.attenuator = 0; - ioctl(fd, DVB_MOD_SET, &mp); - - mc.modulation = QAM_256; - ioctl(fd, DVB_MOD_CHANNEL_SET, &mc); - close(fd); -} - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Kbuild 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Kbuild 1970-01-01 00:00:00.000000000 +0000 @@ -1,8 +0,0 @@ -EXTRA_CFLAGS += -DCONFIG_DVB_LNBP21 -DCONFIG_DVB_STV090x -DCONFIG_DVB_STV6110x -g - -obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o -obj-$(CONFIG_DVB_OCTONET) += octonet.o - -EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -Idrivers/media/dvb-frontends -EXTRA_CFLAGS += -Idrivers/media/common/tuners -NOSTDINC_FLAGS += -I$(SUBDIRS)/frontends -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Makefile 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,19 +0,0 @@ -KDIR ?= /lib/modules/$(shell uname -r)/build -PWD := $(shell pwd) - -MODDEFS := CONFIG_DVB_DDBRIDGE=m - -all: - $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) $(MODDEFS) modules - $(MAKE) -C apps - -dep: - DIR=`pwd`; (cd $(TOPDIR); make SUBDIRS=$$DIR dep) - -install: all - $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules_install - -clean: - rm -rf */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules* - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-core.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-core.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-core.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-core.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,3337 +0,0 @@ -DEFINE_MUTEX(redirect_lock); - -static int ci_bitrate = 72000; -module_param(ci_bitrate, int, 0444); -MODULE_PARM_DESC(ci_bitrate, " Bitrate for output to CI."); - -static int ts_loop = -1; -module_param(ts_loop, int, 0444); -MODULE_PARM_DESC(ts_loop, "TS in/out test loop on port ts_loop"); - -static int vlan = 0; -module_param(vlan, int, 0444); -MODULE_PARM_DESC(vlan, "VLAN and QoS IDs enabled"); - -static int tt = 0; -module_param(tt, int, 0444); -MODULE_PARM_DESC(tt, ""); - -#define DDB_MAX_ADAPTER 32 -static struct ddb *ddbs[DDB_MAX_ADAPTER]; - -DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); - -#include "ddbridge-mod.c" -#include "ddbridge-i2c.c" -#include "ddbridge-ns.c" - - -static void ddb_set_dma_table(struct ddb *dev, struct ddb_dma *dma) -{ - u32 i, base; - u64 mem; - - if (!dma) - return; - base = DMA_BASE_ADDRESS_TABLE + dma->nr * 0x100; - for (i = 0; i < dma->num; i++) { - mem = dma->pbuf[i]; - ddbwritel(dev, mem & 0xffffffff, base + i * 8); - ddbwritel(dev, mem >> 32, base + i * 8 + 4); - } - dma->bufreg = (dma->div << 16) | - ((dma->num & 0x1f) << 11) | - ((dma->size >> 7) & 0x7ff); -} - -static void ddb_set_dma_tables(struct ddb *dev) -{ - u32 i; - - for (i = 0; i < dev->info->port_num * 2; i++) - ddb_set_dma_table(dev, dev->input[i].dma); - for (i = 0; i < dev->info->port_num; i++) - ddb_set_dma_table(dev, dev->output[i].dma); -} - - -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ - -static void ddb_redirect_dma(struct ddb *dev, - struct ddb_dma *sdma, - struct ddb_dma *ddma) -{ - u32 i, base; - u64 mem; - - sdma->bufreg = ddma->bufreg; - base = DMA_BASE_ADDRESS_TABLE + sdma->nr * 0x100; - for (i = 0; i < ddma->num; i++) { - mem = ddma->pbuf[i]; - ddbwritel(dev, mem & 0xffffffff, base + i * 8); - ddbwritel(dev, mem >> 32, base + i * 8 + 4); - } -} - -static int ddb_unredirect(struct ddb_port *port) -{ - struct ddb_input *oredi, *iredi = 0; - struct ddb_output *iredo = 0; - - //printk("unredirect %d.%d\n", port->dev->nr, port->nr); - mutex_lock(&redirect_lock); - if (port->output->dma->running) { - mutex_unlock(&redirect_lock); - return -EBUSY; - } - oredi = port->output->redi; - if (!oredi) - goto done; - if (port->input[0]) { - iredi = port->input[0]->redi; - iredo = port->input[0]->redo; - - if (iredo) { - iredo->port->output->redi = oredi; - if (iredo->port->input[0]) { - iredo->port->input[0]->redi = iredi; - ddb_redirect_dma(oredi->port->dev, - oredi->dma, iredo->dma); - } - port->input[0]->redo = 0; - ddb_set_dma_table(port->dev, port->input[0]->dma); - } - oredi->redi = iredi; - port->input[0]->redi = 0; - } - oredi->redo = 0; - port->output->redi = 0; - - ddb_set_dma_table(oredi->port->dev, oredi->dma); -done: - mutex_unlock(&redirect_lock); - return 0; -} - -static int ddb_redirect(u32 i, u32 p) -{ - struct ddb *idev = ddbs[(i >> 4) & 0x1f]; - struct ddb_input *input, *input2; - struct ddb *pdev = ddbs[(p >> 4) & 0x1f]; - struct ddb_port *port; - - if (!idev->has_dma || !pdev->has_dma) - return -EINVAL; - if (!idev || !pdev) - return -EINVAL; - - port = &pdev->port[p & 0x0f]; - if (!port->output) - return -EINVAL; - if (ddb_unredirect(port)) - return -EBUSY; - - if (i == 8) - return 0; - - input = &idev->input[i & 7]; - if (!input) - return -EINVAL; - - mutex_lock(&redirect_lock); - if (port->output->dma->running || input->dma->running) { - mutex_unlock(&redirect_lock); - return -EBUSY; - } - if ((input2 = port->input[0])) { - if (input->redi) { - input2->redi = input->redi; - input->redi = 0; - } else - input2->redi = input; - } - input->redo = port->output; - port->output->redi = input; - - ddb_redirect_dma(input->port->dev, input->dma, port->output->dma); - mutex_unlock(&redirect_lock); - return 0; -} - -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ - -#ifdef DDB_ALT_DMA -static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir) -{ - int i; - - if (!dma) - return; - for (i = 0; i < dma->num; i++) { - if (dma->vbuf[i]) { - dma_unmap_single(&pdev->dev, dma->pbuf[i], - dma->size, - dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE); - kfree(dma->vbuf[i]); - dma->vbuf[i] = 0; - } - } -} - -static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir) -{ - int i; - - if (!dma) - return 0; - for (i = 0; i < dma->num; i++) { - dma->vbuf[i] = kmalloc(dma->size, __GFP_REPEAT); - if (!dma->vbuf[i]) - return -ENOMEM; - dma->pbuf[i] = dma_map_single(&pdev->dev, dma->vbuf[i], - dma->size, - dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE); - if (dma_mapping_error(&pdev->dev, dma->pbuf[i])) { - kfree(dma->vbuf[i]); - return -ENOMEM; - } - } - return 0; -} -#else - -static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir) -{ - int i; - - if (!dma) - return; - for (i = 0; i < dma->num; i++) { - if (dma->vbuf[i]) { - pci_free_consistent(pdev, dma->size, - dma->vbuf[i], dma->pbuf[i]); - dma->vbuf[i] = 0; - } - } -} - -static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir) -{ - int i; - - if (!dma) - return 0; - for (i = 0; i < dma->num; i++) { - dma->vbuf[i] = pci_alloc_consistent(pdev, dma->size, - &dma->pbuf[i]); - if (!dma->vbuf[i]) - return -ENOMEM; - } - return 0; -} -#endif - -static int ddb_buffers_alloc(struct ddb *dev) -{ - int i; - struct ddb_port *port; - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - switch (port->class) { - case DDB_PORT_TUNER: - if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0) - return -1; - if (dma_alloc(dev->pdev, port->input[1]->dma, 0) < 0) - return -1; - break; - case DDB_PORT_CI: - case DDB_PORT_LOOP: - if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0) - return -1; - case DDB_PORT_MOD: - if (dma_alloc(dev->pdev, port->output->dma, 1) < 0) - return -1; - break; - default: - break; - } - } - ddb_set_dma_tables(dev); - return 0; -} - -static void ddb_buffers_free(struct ddb *dev) -{ - int i; - struct ddb_port *port; - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - - if (port->input[0]) - dma_free(dev->pdev, port->input[0]->dma, 0); - if (port->input[1]) - dma_free(dev->pdev, port->input[1]->dma, 0); - if (port->output) - dma_free(dev->pdev, port->output->dma, 1); - } -} - -static void ddb_output_start(struct ddb_output *output) -{ - struct ddb *dev = output->port->dev; - u32 con2; - - con2 = ((output->port->obr << 13) + 71999) / 72000; - con2 = (con2 << 16) | output->port->gap; - - if (output->dma) { - spin_lock_irq(&output->dma->lock); - output->dma->cbuf = 0; - output->dma->coff = 0; - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); - } - if (output->port->class == DDB_PORT_MOD) - ddbridge_mod_output_start(output); - else { - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, 2, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, 0x3c, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, con2, TS_OUTPUT_CONTROL2(output->nr)); - } - if (output->dma) { - ddbwritel(dev, output->dma->bufreg, DMA_BUFFER_SIZE(output->dma->nr)); - ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); - ddbwritel(dev, 1, DMA_BASE_READ); - ddbwritel(dev, 3, DMA_BUFFER_CONTROL(output->dma->nr)); - } - if (output->port->class != DDB_PORT_MOD) { - if (output->port->input[0]->port->class == DDB_PORT_LOOP) - //ddbwritel(dev, 0x15, TS_OUTPUT_CONTROL(output->nr)); - //ddbwritel(dev, 0x45, TS_OUTPUT_CONTROL(output->nr)); - ddbwritel(dev, (1 << 13) | 0x15, TS_OUTPUT_CONTROL(output->nr)); - else - ddbwritel(dev, 0x1d, TS_OUTPUT_CONTROL(output->nr)); - } - if (output->dma) { - output->dma->running = 1; - spin_unlock_irq(&output->dma->lock); - } -} - -static void ddb_output_stop(struct ddb_output *output) -{ - struct ddb *dev = output->port->dev; - - if (output->dma) - spin_lock_irq(&output->dma->lock); - if (output->port->class == DDB_PORT_MOD) - ddbridge_mod_output_stop(output); - else - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); - if (output->dma) { - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); - output->dma->running = 0; - spin_unlock_irq(&output->dma->lock); - } -} - -static void ddb_input_stop(struct ddb_input *input) -{ - struct ddb *dev = input->port->dev; - - if (input->dma) - spin_lock_irq(&input->dma->lock); - ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); - if (input->dma) { - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); - input->dma->running = 0; - spin_unlock_irq(&input->dma->lock); - } - //printk("input_stop %d.%d\n", dev->nr, input->nr); -} - -static void ddb_input_start(struct ddb_input *input) -{ - struct ddb *dev = input->port->dev; - - if (input->dma) { - spin_lock_irq(&input->dma->lock); - input->dma->cbuf = 0; - input->dma->coff = 0; - ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); - } - ddbwritel(dev, 0, TS_INPUT_CONTROL2(input->nr)); - ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); - ddbwritel(dev, 2, TS_INPUT_CONTROL(input->nr)); - ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); - - if (input->dma) { - ddbwritel(dev, input->dma->bufreg, DMA_BUFFER_SIZE(input->dma->nr)); - ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); - ddbwritel(dev, 1, DMA_BASE_WRITE); - ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma->nr)); - } - if (dev->info->type == DDB_OCTONET) - ddbwritel(dev, 0x01, TS_INPUT_CONTROL(input->nr)); - else - ddbwritel(dev, 0x09, TS_INPUT_CONTROL(input->nr)); - if (input->dma) { - input->dma->running = 1; - spin_unlock_irq(&input->dma->lock); - } - //printk("input_start %d.%d\n", dev->nr, input->nr); -} - - -static int ddb_dvb_input_start(struct ddb_input *input) -{ - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - - if (!dvb->users) - ddb_input_start(input); - - return ++dvb->users; -} - -static int ddb_dvb_input_stop(struct ddb_input *input) -{ - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - - if (--dvb->users) - return dvb->users; - - ddb_input_stop(input); - return 0; -} - -static void ddb_input_start_all(struct ddb_input *input) -{ - struct ddb_input *i = input; - struct ddb_output *o; - - mutex_lock(&redirect_lock); - while (i && (o = i->redo)) { - ddb_output_start(o); - if ((i = o->port->input[0])) - ddb_input_start(i); - } - ddb_input_start(input); - mutex_unlock(&redirect_lock); -} - -static void ddb_input_stop_all(struct ddb_input *input) -{ - struct ddb_input *i = input; - struct ddb_output *o; - - mutex_lock(&redirect_lock); - ddb_input_stop(input); - while (i && (o = i->redo)) { - ddb_output_stop(o); - if ((i = o->port->input[0])) - ddb_input_stop(i); - } - mutex_unlock(&redirect_lock); -} - -static u32 ddb_output_free(struct ddb_output *output) -{ - u32 idx, off, stat = output->dma->stat; - s32 diff; - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - if (output->dma->cbuf != idx) { - if ((((output->dma->cbuf + 1) % output->dma->num) == idx) && - (output->dma->size - output->dma->coff <= 188)) - return 0; - return 188; - } - diff = off - output->dma->coff; - if (diff <= 0 || diff > 188) - return 188; - return 0; -} - -static u32 ddb_dma_free(struct ddb_dma *dma) -{ - u32 idx, off, stat = dma->stat; - s32 p1, p2, diff; - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - p1 = idx * dma->size + off; - p2 = dma->cbuf * dma->size + dma->coff; - - diff = p1 - p2; - if (diff <= 0) - diff += dma->num * dma->size; - return diff; -} - -static ssize_t ddb_output_write(struct ddb_output *output, - const u8 *buf, size_t count) -{ - struct ddb *dev = output->port->dev; - u32 idx, off, stat = output->dma->stat; - u32 left = count, len; - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - while (left) { - len = output->dma->size - output->dma->coff; - if ((((output->dma->cbuf + 1) % output->dma->num) == idx) && - (off == 0)) { - if (len <= 188) - break; - len -= 188; - } - if (output->dma->cbuf == idx) { - if (off > output->dma->coff) { - len = off - output->dma->coff; - len -= (len % 188); - if (len <= 188) - break; - len -= 188; - } - } - if (len > left) - len = left; - if (copy_from_user(output->dma->vbuf[output->dma->cbuf] + - output->dma->coff, - buf, len)) - return -EIO; -#ifdef DDB_ALT_DMA - dma_sync_single_for_device(dev->dev, - output->dma->pbuf[output->dma->cbuf], - output->dma->size, DMA_TO_DEVICE); -#endif - left -= len; - buf += len; - output->dma->coff += len; - if (output->dma->coff == output->dma->size) { - output->dma->coff = 0; - output->dma->cbuf = ((output->dma->cbuf + 1) % - output->dma->num); - } - ddbwritel(dev, - (output->dma->cbuf << 11) | (output->dma->coff >> 7), - DMA_BUFFER_ACK(output->dma->nr)); - } - return count - left; -} - -static u32 ddb_input_free_bytes(struct ddb_input *input) -{ - struct ddb *dev = input->port->dev; - u32 idx, off, stat = input->dma->stat; - u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - if (ctrl & 4) - return 0; - if (input->dma->cbuf != idx) - return 1; - return 0; -} - -static s32 ddb_output_used_bufs(struct ddb_output *output) -{ - u32 idx, off, stat, ctrl; - s32 diff; - - spin_lock_irq(&output->dma->lock); - stat = output->dma->stat; - ctrl = output->dma->ctrl; - spin_unlock_irq(&output->dma->lock); - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - if (ctrl & 4) - return 0; - diff = output->dma->cbuf - idx; - if (diff == 0 && off < output->dma->coff) - return 0; - if (diff <= 0) - diff += output->dma->num; - return diff; -} - -static s32 ddb_input_free_bufs(struct ddb_input *input) -{ - u32 idx, off, stat, ctrl; - s32 free; - - spin_lock_irq(&input->dma->lock); - ctrl = input->dma->ctrl; - stat = input->dma->stat; - spin_unlock_irq(&input->dma->lock); - if (ctrl & 4) - return 0; - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - free = input->dma->cbuf - idx; - if (free == 0 && off < input->dma->coff) - return 0; - if (free <= 0) - free += input->dma->num; - return free - 1; -} - -static u32 ddb_output_ok(struct ddb_output *output) -{ - struct ddb_input *input = output->port->input[0]; - s32 diff; - - diff = ddb_input_free_bufs(input) - ddb_output_used_bufs(output); - if (diff > 0) - return 1; - return 0; -} - -static u32 ddb_input_avail(struct ddb_input *input) -{ - struct ddb *dev = input->port->dev; - u32 idx, off, stat = input->dma->stat; - u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - if (ctrl & 4) { - printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); - ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma->nr)); - return 0; - } - if (input->dma->cbuf != idx || off < input->dma->coff) - return 188; - return 0; -} - -static size_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count) -{ - struct ddb *dev = input->port->dev; - u32 left = count; - u32 idx, off, free, stat = input->dma->stat; - int ret; - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - while (left) { - if (input->dma->cbuf == idx) - return count - left; - free = input->dma->size - input->dma->coff; - if (free > left) - free = left; -#ifdef DDB_ALT_DMA - dma_sync_single_for_cpu(dev->dev, - input->dma->pbuf[input->dma->cbuf], - input->dma->size, DMA_FROM_DEVICE); -#endif - ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] + - input->dma->coff, free); - if (ret) - return -EFAULT; - input->dma->coff += free; - if (input->dma->coff == input->dma->size) { - input->dma->coff = 0; - input->dma->cbuf = (input->dma->cbuf + 1) % - input->dma->num; - } - left -= free; - ddbwritel(dev, - (input->dma->cbuf << 11) | (input->dma->coff >> 7), - DMA_BUFFER_ACK(input->dma->nr)); - } - return count; -} - -/****************************************************************************/ -/****************************************************************************/ - -static ssize_t ts_write(struct file *file, const char *buf, - size_t count, loff_t *ppos) -{ - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - struct ddb *dev = output->port->dev; - size_t left = count; - int stat; - - if (!dev->has_dma) - return -EINVAL; - while (left) { - if (ddb_output_free(output) < 188) { - if (file->f_flags & O_NONBLOCK) - break; - if (wait_event_interruptible( - output->dma->wq, - ddb_output_free(output) >= 188) < 0) - break; - } - stat = ddb_output_write(output, buf, left); - if (stat < 0) - return stat; - buf += stat; - left -= stat; - } - return (left == count) ? -EAGAIN : (count - left); -} - -static ssize_t ts_read(struct file *file, char *buf, - size_t count, loff_t *ppos) -{ - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - struct ddb_input *input = output->port->input[0]; - struct ddb *dev = output->port->dev; - int left, read; - - if (!dev->has_dma) - return -EINVAL; - count -= count % 188; - left = count; - while (left) { - if (ddb_input_avail(input) < 188) { - if (file->f_flags & O_NONBLOCK) - break; - if (wait_event_interruptible( - input->dma->wq, - ddb_input_avail(input) >= 188) < 0) - break; - } - read = ddb_input_read(input, buf, left); - left -= read; - buf += read; - } - return (left == count) ? -EAGAIN : (count - left); -} - -static unsigned int ts_poll(struct file *file, poll_table *wait) -{ - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - struct ddb_input *input = output->port->input[0]; - - unsigned int mask = 0; - - poll_wait(file, &input->dma->wq, wait); - poll_wait(file, &output->dma->wq, wait); - if (ddb_input_avail(input) >= 188) - mask |= POLLIN | POLLRDNORM; - if (ddb_output_free(output) >= 188) - mask |= POLLOUT | POLLWRNORM; - return mask; -} - -static int ts_release(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - struct ddb_input *input = output->port->input[0]; - - if ((file->f_flags & O_ACCMODE) == O_RDONLY) { - if (!input) - return -EINVAL; - ddb_input_stop(input); - } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) { - if (!output) - return -EINVAL; - ddb_output_stop(output); - } - return dvb_generic_release(inode, file); -} - -static int ts_open(struct inode *inode, struct file *file) -{ - int err; - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - struct ddb_input *input = output->port->input[0]; - - if ((file->f_flags & O_ACCMODE) == O_RDONLY) { - if (!input) - return -EINVAL; - if (input->redo || input->redi) - return -EBUSY; - } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) { - if (!output) - return -EINVAL; - } - if ((err = dvb_generic_open(inode, file)) < 0) - return err; - if ((file->f_flags & O_ACCMODE) == O_RDONLY) - ddb_input_start(input); - else if ((file->f_flags & O_ACCMODE) == O_WRONLY) - ddb_output_start(output); - return err; -} - -static int mod_release(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - struct ddb_input *input = output->port->input[0]; - - if ((file->f_flags & O_ACCMODE) == O_WRONLY) { - if (!output) - return -EINVAL; - ddb_output_stop(output); - } - return dvb_generic_release(inode, file); -} - -static int mod_open(struct inode *inode, struct file *file) -{ - int err; - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - - if ((file->f_flags & O_ACCMODE) == O_WRONLY) { - if (!output) - return -EINVAL; - } - if ((err = dvb_generic_open(inode, file)) < 0) - return err; - if ((file->f_flags & O_ACCMODE) == O_WRONLY) - ddb_output_start(output); - return err; -} -static const struct file_operations ci_fops = { - .owner = THIS_MODULE, - .read = ts_read, - .write = ts_write, - .open = ts_open, - .release = ts_release, - .poll = ts_poll, - .mmap = 0, -}; - -static struct dvb_device dvbdev_ci = { - .priv = 0, - .readers = 1, - .writers = 1, - .users = 2, - .fops = &ci_fops, -}; - - -/****************************************************************************/ -/****************************************************************************/ - -static long mod_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - return dvb_usercopy(file, cmd, arg, ddbridge_mod_do_ioctl); -} - -static const struct file_operations mod_fops = { - .owner = THIS_MODULE, - .read = ts_read, - .write = ts_write, - .open = mod_open, - .release = mod_release, - .poll = ts_poll, - .mmap = 0, - .unlocked_ioctl = mod_ioctl, -}; - -static struct dvb_device dvbdev_mod = { - .priv = 0, - .readers = 1, - .writers = 1, - .users = 2, - .fops = &mod_fops, -}; - - -#if 0 -static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) -{ - int i; - - for (i = 0; i < dev->info->port_num * 2; i++) { - if (dev->input[i].fe == fe) - return &dev->input[i]; - } - return NULL; -} -#endif - -static int locked_gate_ctrl(struct dvb_frontend *fe, int enable) -{ - struct ddb_input *input = fe->sec_priv; - struct ddb_port *port = input->port; - struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; - int status; - - if (enable) { - mutex_lock(&port->i2c_gate_lock); - status = dvb->gate_ctrl(fe, 1); - } else { - status = dvb->gate_ctrl(fe, 0); - mutex_unlock(&port->i2c_gate_lock); - } - return status; -} - -#ifdef CONFIG_DVB_DRXK -static int demod_attach_drxk(struct ddb_input *input) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; - - fe = dvb->fe = dvb_attach(drxk_attach, - i2c, 0x29 + (input->nr&1), - &dvb->fe2); - if (!fe) { - printk(KERN_ERR "No DRXK found!\n"); - return -ENODEV; - } - fe->sec_priv = input; - dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; - fe->ops.i2c_gate_ctrl = locked_gate_ctrl; - return 0; -} -#endif - -#if 0 -struct stv0367_config stv0367_0 = { - .demod_address = 0x1f, - .xtal = 27000000, - .if_khz = 5000, - .if_iq_mode = FE_TER_NORMAL_IF_TUNER, - .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, - .clk_pol = STV0367_RISINGEDGE_CLOCK, -}; - -struct stv0367_config stv0367_1 = { - .demod_address = 0x1e, - .xtal = 27000000, - .if_khz = 5000, - .if_iq_mode = FE_TER_NORMAL_IF_TUNER, - .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, - .clk_pol = STV0367_RISINGEDGE_CLOCK, -}; - - -static int demod_attach_stv0367(struct ddb_input *input) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; - - fe = dvb->fe = dvb_attach(stv0367ter_attach, - (input->nr & 1) ? &stv0367_1 : &stv0367_0, - i2c); - if (!dvb->fe) { - printk(KERN_ERR "No stv0367 found!\n"); - return -ENODEV; - } - fe->sec_priv = input; - dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; - fe->ops.i2c_gate_ctrl = locked_gate_ctrl; - return 0; -} -#endif - -struct cxd2843_cfg cxd2843_0 = { - .adr = 0x6c, -}; - -struct cxd2843_cfg cxd2843_1 = { - .adr = 0x6d, -}; - -static int demod_attach_cxd2843(struct ddb_input *input) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; - - fe = dvb->fe = dvb_attach(cxd2843_attach, i2c, - (input->nr & 1) ? &cxd2843_1 : &cxd2843_0); - if (!dvb->fe) { - printk(KERN_ERR "No cxd2843 found!\n"); - return -ENODEV; - } - fe->sec_priv = input; - dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; - fe->ops.i2c_gate_ctrl = locked_gate_ctrl; - return 0; -} - -struct stv0367_cfg stv0367dd_0 = { - .adr = 0x1f, - .xtal = 27000000, -}; - -struct stv0367_cfg stv0367dd_1 = { - .adr = 0x1e, - .xtal = 27000000, -}; - -static int demod_attach_stv0367dd(struct ddb_input *input) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; - - fe = dvb->fe = dvb_attach(stv0367_attach, i2c, - (input->nr & 1) ? &stv0367dd_1 : &stv0367dd_0, - &dvb->fe2); - if (!dvb->fe) { - printk(KERN_ERR "No stv0367 found!\n"); - return -ENODEV; - } - fe->sec_priv = input; - dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; - fe->ops.i2c_gate_ctrl = locked_gate_ctrl; - return 0; -} - -static int tuner_attach_tda18271(struct ddb_input *input) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; - - if (dvb->fe->ops.i2c_gate_ctrl) - dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 1); - fe = dvb_attach(tda18271c2dd_attach, dvb->fe, i2c, 0x60); - if (dvb->fe->ops.i2c_gate_ctrl) - dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0); - if (!fe) { - printk(KERN_ERR "No TDA18271 found!\n"); - return -ENODEV; - } - return 0; -} - -static int tuner_attach_tda18212dd(struct ddb_input *input) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; - - fe = dvb_attach(tda18212dd_attach, dvb->fe, i2c, - (input->nr & 1) ? 0x63 : 0x60); - if (!fe) { - printk(KERN_ERR "No TDA18212 found!\n"); - return -ENODEV; - } - return 0; -} - -#ifdef CONFIG_DVB_TDA18212 -struct tda18212_config tda18212_0 = { - .i2c_address = 0x60, -}; - -struct tda18212_config tda18212_1 = { - .i2c_address = 0x63, -}; - -static int tuner_attach_tda18212(struct ddb_input *input) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; - struct tda18212_config *cfg; - - cfg = (input->nr & 1) ? &tda18212_1 : &tda18212_0; - fe = dvb_attach(tda18212_attach, dvb->fe, i2c, cfg); - if (!fe) { - printk(KERN_ERR "No TDA18212 found!\n"); - return -ENODEV; - } - return 0; -} -#endif - -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ - -static struct stv090x_config stv0900 = { - .device = STV0900, - .demod_mode = STV090x_DUAL, - .clk_mode = STV090x_CLK_EXT, - - .xtal = 27000000, - .address = 0x69, - - .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, - .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, - - .repeater_level = STV090x_RPTLEVEL_16, - - .adc1_range = STV090x_ADC_1Vpp, - .adc2_range = STV090x_ADC_1Vpp, - - .diseqc_envelope_mode = true, -}; - -static struct stv090x_config stv0900_aa = { - .device = STV0900, - .demod_mode = STV090x_DUAL, - .clk_mode = STV090x_CLK_EXT, - - .xtal = 27000000, - .address = 0x68, - - .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, - .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, - - .repeater_level = STV090x_RPTLEVEL_16, - - .adc1_range = STV090x_ADC_1Vpp, - .adc2_range = STV090x_ADC_1Vpp, - - .diseqc_envelope_mode = true, -}; - -static struct stv6110x_config stv6110a = { - .addr = 0x60, - .refclk = 27000000, - .clk_div = 1, -}; - -static struct stv6110x_config stv6110b = { - .addr = 0x63, - .refclk = 27000000, - .clk_div = 1, -}; - -static int demod_attach_stv0900(struct ddb_input *input, int type) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - - dvb->fe = dvb_attach(stv090x_attach, feconf, i2c, - (input->nr & 1) ? STV090x_DEMODULATOR_1 - : STV090x_DEMODULATOR_0); - if (!dvb->fe) { - printk(KERN_ERR "No STV0900 found!\n"); - return -ENODEV; - } - if (!dvb_attach(lnbh24_attach, dvb->fe, i2c, 0, - 0, (input->nr & 1) ? - (0x09 - type) : (0x0b - type))) { - printk(KERN_ERR "No LNBH24 found!\n"); - return -ENODEV; - } - return 0; -} - -static int tuner_attach_stv6110(struct ddb_input *input, int type) -{ - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; - struct stv6110x_config *tunerconf = (input->nr & 1) ? - &stv6110b : &stv6110a; - struct stv6110x_devctl *ctl; - - ctl = dvb_attach(stv6110x_attach, dvb->fe, tunerconf, i2c); - if (!ctl) { - printk(KERN_ERR "No STV6110X found!\n"); - return -ENODEV; - } - printk(KERN_INFO "attach tuner input %d adr %02x\n", - input->nr, tunerconf->addr); - - feconf->tuner_init = ctl->tuner_init; - feconf->tuner_sleep = ctl->tuner_sleep; - feconf->tuner_set_mode = ctl->tuner_set_mode; - feconf->tuner_set_frequency = ctl->tuner_set_frequency; - feconf->tuner_get_frequency = ctl->tuner_get_frequency; - feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; - feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; - feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; - feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; - feconf->tuner_set_refclk = ctl->tuner_set_refclk; - feconf->tuner_get_status = ctl->tuner_get_status; - - return 0; -} - -static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, - int (*start_feed)(struct dvb_demux_feed *), - int (*stop_feed)(struct dvb_demux_feed *), - void *priv) -{ - dvbdemux->priv = priv; - - dvbdemux->filternum = 256; - dvbdemux->feednum = 256; - dvbdemux->start_feed = start_feed; - dvbdemux->stop_feed = stop_feed; - dvbdemux->write_to_decoder = NULL; - dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | - DMX_SECTION_FILTERING | - DMX_MEMORY_BASED_FILTERING); - return dvb_dmx_init(dvbdemux); -} - -static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, - struct dvb_demux *dvbdemux, - struct dmx_frontend *hw_frontend, - struct dmx_frontend *mem_frontend, - struct dvb_adapter *dvb_adapter) -{ - int ret; - - dmxdev->filternum = 256; - dmxdev->demux = &dvbdemux->dmx; - dmxdev->capabilities = 0; - ret = dvb_dmxdev_init(dmxdev, dvb_adapter); - if (ret < 0) - return ret; - - hw_frontend->source = DMX_FRONTEND_0; - dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); - mem_frontend->source = DMX_MEMORY_FE; - dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); - return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); -} - -static int start_input(struct ddb_input *input) -{ - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - - if (!dvb->users) - ddb_input_start_all(input); - - return ++dvb->users; -} - -static int stop_input(struct ddb_input *input) -{ - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - - if (--dvb->users) - return dvb->users; - - ddb_input_stop_all(input); - return 0; -} - -static int start_feed(struct dvb_demux_feed *dvbdmxfeed) -{ - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ddb_input *input = dvbdmx->priv; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - - if (!dvb->users) - ddb_input_start_all(input); - - return ++dvb->users; -} - -static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) -{ - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ddb_input *input = dvbdmx->priv; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - - if (--dvb->users) - return dvb->users; - - ddb_input_stop_all(input); - return 0; -} - -static void dvb_input_detach(struct ddb_input *input) -{ - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_demux *dvbdemux = &dvb->demux; - - switch (dvb->attached) { - case 0x31: - if (dvb->fe2) - dvb_unregister_frontend(dvb->fe2); - if (dvb->fe) - dvb_unregister_frontend(dvb->fe); - case 0x30: - dvb_frontend_detach(dvb->fe); - dvb->fe = dvb->fe2 = NULL; -#ifdef DVB_NETSTREAM - case 0x21: - dvb_netstream_release(&dvb->dvbns); -#endif - case 0x20: - dvb_net_release(&dvb->dvbnet); - case 0x11: - dvbdemux->dmx.close(&dvbdemux->dmx); - dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, - &dvb->hw_frontend); - dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, - &dvb->mem_frontend); - dvb_dmxdev_release(&dvb->dmxdev); - case 0x10: - dvb_dmx_release(&dvb->demux); - case 0x01: - break; - } - dvb->attached = 0x00; -} - -static int dvb_register_adapters(struct ddb *dev) -{ - int i, ret = 0; - struct ddb_port *port; - struct dvb_adapter *adap; - - if (adapter_alloc == 3 || dev->info->type == DDB_MOD) { - port = &dev->port[0]; - adap = port->dvb[0].adap; - ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, - port->dev->dev, - adapter_nr); - if (ret < 0) - return ret; - port->dvb[0].adap_registered = 1; - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - port->dvb[0].adap = adap; - port->dvb[1].adap = adap; - } - return 0; - } - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - switch (port->class) { - case DDB_PORT_TUNER: - adap = port->dvb[0].adap; - ret = dvb_register_adapter(adap, "DDBridge", - THIS_MODULE, - port->dev->dev, - adapter_nr); - if (ret < 0) - return ret; - port->dvb[0].adap_registered = 1; - - if (adapter_alloc > 0) { - port->dvb[1].adap = port->dvb[0].adap; - break; - } - adap = port->dvb[1].adap; - ret = dvb_register_adapter(adap, "DDBridge", - THIS_MODULE, - port->dev->dev, - adapter_nr); - if (ret < 0) - return ret; - port->dvb[1].adap_registered = 1; - break; - - case DDB_PORT_CI: - case DDB_PORT_LOOP: - adap = port->dvb[0].adap; - ret = dvb_register_adapter(adap, "DDBridge", - THIS_MODULE, - port->dev->dev, - adapter_nr); - if (ret < 0) - return ret; - port->dvb[0].adap_registered = 1; - break; - default: - if (adapter_alloc < 2) - break; - adap = port->dvb[0].adap; - ret = dvb_register_adapter(adap, "DDBridge", - THIS_MODULE, - port->dev->dev, - adapter_nr); - if (ret < 0) - return ret; - port->dvb[0].adap_registered = 1; - break; - } - } - return ret; -} - -static void dvb_unregister_adapters(struct ddb *dev) -{ - int i; - struct ddb_port *port; - struct ddb_dvb *dvb; - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - - dvb = &port->dvb[0]; - if (dvb->adap_registered) - dvb_unregister_adapter(dvb->adap); - dvb->adap_registered = 0; - - dvb = &port->dvb[1]; - if (dvb->adap_registered) - dvb_unregister_adapter(dvb->adap); - dvb->adap_registered = 0; - } -} - -static int dvb_input_attach(struct ddb_input *input) -{ - int ret = 0; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct ddb_port *port = input->port; - struct dvb_adapter *adap = dvb->adap; - struct dvb_demux *dvbdemux = &dvb->demux; - - dvb->attached = 0x01; - - ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", - start_feed, - stop_feed, input); - if (ret < 0) - return ret; - dvb->attached = 0x10; - - ret = my_dvb_dmxdev_ts_card_init(&dvb->dmxdev, - &dvb->demux, - &dvb->hw_frontend, - &dvb->mem_frontend, adap); - if (ret < 0) - return ret; - dvb->attached = 0x11; - - ret = dvb_net_init(adap, &dvb->dvbnet, dvb->dmxdev.demux); - if (ret < 0) - return ret; - dvb->attached = 0x20; - -#ifdef DVB_NETSTREAM - ret = netstream_init(input); - if (ret < 0) - return ret; - dvb->attached = 0x21; -#endif - dvb->fe = dvb->fe2 = 0; - switch (port->type) { - case DDB_TUNER_DVBS_ST: - if (demod_attach_stv0900(input, 0) < 0) - return -ENODEV; - if (tuner_attach_stv6110(input, 0) < 0) - return -ENODEV; - break; - case DDB_TUNER_DVBS_ST_AA: - if (demod_attach_stv0900(input, 1) < 0) - return -ENODEV; - if (tuner_attach_stv6110(input, 1) < 0) - return -ENODEV; - break; -#ifdef CONFIG_DVB_DRXK - case DDB_TUNER_DVBCT_TR: - if (demod_attach_drxk(input) < 0) - return -ENODEV; - if (tuner_attach_tda18271(input) < 0) - return -ENODEV; - break; -#endif - case DDB_TUNER_DVBCT_ST: - if (demod_attach_stv0367dd(input) < 0) - return -ENODEV; - if (tuner_attach_tda18212dd(input) < 0) - return -ENODEV; - break; - case DDB_TUNER_DVBCT2_SONY: - case DDB_TUNER_DVBC2T2_SONY: - case DDB_TUNER_ISDBT_SONY: - if (demod_attach_cxd2843(input) < 0) - return -ENODEV; - if (tuner_attach_tda18212dd(input) < 0) - return -ENODEV; - break; - default: - return 0; - } - dvb->attached = 0x30; - if (dvb->fe) { - if (dvb_register_frontend(adap, dvb->fe) < 0) - return -ENODEV; - } - if (dvb->fe2) { - if (dvb_register_frontend(adap, dvb->fe2) < 0) - return -ENODEV; - dvb->fe2->tuner_priv = dvb->fe->tuner_priv; - memcpy(&dvb->fe2->ops.tuner_ops, - &dvb->fe->ops.tuner_ops, - sizeof(struct dvb_tuner_ops)); - } - dvb->attached = 0x31; - return 0; -} - - -static int port_has_encti(struct ddb_port *port) -{ - u8 val; - int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val); - - if (!ret) - printk("[0x20]=0x%02x\n", val); - - return ret ? 0 : 1; -} - -static int port_has_cxd_old(struct ddb_port *port) -{ - u8 val; - return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; -} - -static int port_has_cxd(struct ddb_port *port) -{ - u8 val; - u8 probe[4] = { 0xe0, 0x00, 0x00, 0x00 }, data[4]; - struct i2c_msg msgs[2] = {{ .addr = 0x40, .flags = 0, - .buf = probe, .len = 4 }, - { .addr = 0x40, .flags = I2C_M_RD, - .buf = data, .len = 4 }}; - val = i2c_transfer(&port->i2c->adap, msgs, 2); - if (val != 2) - return 0; - - if (data[0] == 0x02 && data[1] == 0x2b && data[3] == 0x43) - return 2; - return 1; -} - -static int port_has_mach(struct ddb_port *port, u8 *id) -{ - u8 val; - u8 probe[1] = { 0x00 }, data[4]; - struct i2c_msg msgs[2] = {{ .addr = 0x10, .flags = 0, - .buf = probe, .len = 1 }, - { .addr = 0x10, .flags = I2C_M_RD, - .buf = data, .len = 4 }}; - val = i2c_transfer(&port->i2c->adap, msgs, 2); - if (val != 2) - return 0; - - if (data[0] != 'D' || data[1] != 'F') - return 0; - - *id = data[2]; - return 1; -} - -static int port_has_stv0900(struct ddb_port *port) -{ - u8 val; - if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) - return 0; - return 1; -} - -static int port_has_stv0900_aa(struct ddb_port *port) -{ - u8 val; - if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) - return 0; - return 1; -} - -static int port_has_drxks(struct ddb_port *port) -{ - u8 val; - if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) - return 0; - if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) - return 0; - return 1; -} - -static int port_has_stv0367(struct ddb_port *port) -{ - u8 val; - - if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0) - return 0; - if (val != 0x60) - return 0; - if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0) - return 0; - if (val != 0x60) - return 0; - return 1; -} - -static int init_xo2_old(struct ddb_port *port) -{ - struct i2c_adapter *i2c =&port->i2c->adap; - u8 val; - int res; - - res = i2c_read_reg(i2c, 0x10, 0x04, &val); - if (res < 0) - return res; - - if (val != 0x02) { - printk(KERN_INFO "Port %d: invalid XO2\n", port->nr); - return -1; - } - - /* Disable XO2 I2C master */ - i2c_write_reg(i2c, 0x10, 0xc0, 0x00); - - i2c_read_reg(i2c, 0x10, 0x08, &val); - if (val != 0) { - i2c_write_reg(i2c, 0x10, 0x08, 0x00); - msleep(100); - } - /* Enable tuner power, disable pll, reset demods */ - i2c_write_reg(i2c, 0x10, 0x08, 0x04); - msleep(2); - /* Release demod resets */ - i2c_write_reg(i2c, 0x10, 0x08, 0x07); - msleep(2); - /* Start XO2 PLL */ - i2c_write_reg(i2c, 0x10, 0x08, 0x87); - - return 0; -} - -static int init_xo2(struct ddb_port *port) -{ - struct i2c_adapter *i2c =&port->i2c->adap; - u8 val, data[2]; - int res; - - res = i2c_read_regs(i2c, 0x10, 0x04, data, 2); - if (res < 0) - return res; - - if (data[0] != 0x01) { - printk(KERN_INFO "Port %d: invalid XO2\n", port->nr); - return -1; - } - - i2c_read_reg(i2c, 0x10, 0x08, &val); - if (val != 0) { - i2c_write_reg(i2c, 0x10, 0x08, 0x00); - msleep(100); - } - /* Enable tuner power, disable pll, reset demods */ - i2c_write_reg(i2c, 0x10, 0x08, 0x04); - msleep(2); - /* Release demod resets */ - i2c_write_reg(i2c, 0x10, 0x08, 0x07); - msleep(2); - - /* Start XO2 PLL */ - i2c_write_reg(i2c, 0x10, 0x08, 0x87); - - return 0; -} - -static void ddb_port_probe(struct ddb_port *port) -{ - struct ddb *dev = port->dev; - char *modname = "NO MODULE"; - int val; - u8 id; - - port->class = DDB_PORT_NONE; - - if (dev->info->type == DDB_MOD) { - modname = "MOD"; - port->class = DDB_PORT_MOD; - printk(KERN_INFO "Port %d: MOD\n", port->nr); - return; - } - - if (port->nr > 1 && dev->info->type == DDB_OCTOPUS_CI) { - modname = "CI internal"; - port->class = DDB_PORT_CI; - port->type = DDB_CI_INTERNAL; - } else if ((val = port_has_cxd(port)) > 0) { - if (val == 1) { - modname = "CI"; - port->class = DDB_PORT_CI; - port->type = DDB_CI_EXTERNAL_SONY; - ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); - } else { - printk(KERN_INFO "Port %d: Uninitialized DuoFlex\n", port->nr); - return; - } - } else if (port_has_mach(port, &id)) { - char *xo2names[] = { "DUAL DVB-S2", "DUAL DVB-C/T/T2", "DUAL DVB-ISDBT", - "DUAL DVB-C/C2/T/T2", "DUAL ATSC", "DUAL DVB-C/C2/T/T2" }; - - ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); - id >>= 2; - if (id > 5) { - modname = "unknown XO2 DuoFlex"; - } else { - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_XO2 + id; - modname = xo2names[id]; - init_xo2(port); - } - } else if (port_has_stv0900(port)) { - modname = "DUAL DVB-S2"; - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_DVBS_ST; - ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); - } else if (port_has_stv0900_aa(port)) { - modname = "DUAL DVB-S2"; - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_DVBS_ST_AA; - ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); - } else if (port_has_drxks(port)) { - modname = "DUAL DVB-C/T"; - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_DVBCT_TR; - ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); - } else if (port_has_stv0367(port)) { - modname = "DUAL DVB-C/T"; - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_DVBCT_ST; - ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); - } else if (port_has_encti(port)) { - modname = "ENCTI"; - port->class = DDB_PORT_LOOP; - } else if (port->nr == ts_loop) { - modname = "TS LOOP"; - port->class = DDB_PORT_LOOP; - } - printk(KERN_INFO "Port %d (TAB %d): %s\n", port->nr, port->nr + 1, modname); -} - - -/****************************************************************************/ -/****************************************************************************/ -/****************************************************************************/ - -static int wait_ci_ready(struct ddb_ci *ci) -{ - u32 count = 10; - - ndelay(500); - do { - if (ddbreadl(ci->port->dev, - CI_CONTROL(ci->nr)) & CI_READY) - break; - usleep_range(1, 2); - if ((--count) == 0) - return -1; - } while (1); - return 0; -} - -static int read_attribute_mem(struct dvb_ca_en50221 *ca, - int slot, int address) -{ - struct ddb_ci *ci = ca->data; - u32 val, off = (address >> 1) & (CI_BUFFER_SIZE-1); - - if (address > CI_BUFFER_SIZE) - return -1; - ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address, - CI_DO_READ_ATTRIBUTES(ci->nr)); - wait_ci_ready(ci); - val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off); - return val; -} - -static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, - int address, u8 value) -{ - struct ddb_ci *ci = ca->data; - - ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address, - CI_DO_ATTRIBUTE_RW(ci->nr)); - wait_ci_ready(ci); - return 0; -} - -static int read_cam_control(struct dvb_ca_en50221 *ca, - int slot, u8 address) -{ - u32 count = 100; - struct ddb_ci *ci = ca->data; - u32 res; - - ddbwritel(ci->port->dev, CI_READ_CMD | address, - CI_DO_IO_RW(ci->nr)); - ndelay(500); - do { - res = ddbreadl(ci->port->dev, CI_READDATA(ci->nr)); - if (res & CI_READY) - break; - usleep_range(1, 2); - if ((--count) == 0) - return -1; - } while (1); - return (0xff & res); -} - -static int write_cam_control(struct dvb_ca_en50221 *ca, int slot, - u8 address, u8 value) -{ - struct ddb_ci *ci = ca->data; - - ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address, - CI_DO_IO_RW(ci->nr)); - wait_ci_ready(ci); - return 0; -} - -static int slot_reset(struct dvb_ca_en50221 *ca, int slot) -{ - struct ddb_ci *ci = ca->data; - - ddbwritel(ci->port->dev, CI_POWER_ON, - CI_CONTROL(ci->nr)); - msleep(100); - ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM, - CI_CONTROL(ci->nr)); - ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM, - CI_CONTROL(ci->nr)); - udelay(20); - ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON, - CI_CONTROL(ci->nr)); - return 0; -} - -static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) -{ - struct ddb_ci *ci = ca->data; - - ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr)); - msleep(300); - return 0; -} - -static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) -{ - struct ddb_ci *ci = ca->data; - u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); - - ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE, - CI_CONTROL(ci->nr)); - return 0; -} - -static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) -{ - struct ddb_ci *ci = ca->data; - u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); - int stat = 0; - - if (val & CI_CAM_DETECT) - stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; - if (val & CI_CAM_READY) - stat |= DVB_CA_EN50221_POLL_CAM_READY; - return stat; -} - -static struct dvb_ca_en50221 en_templ = { - .read_attribute_mem = read_attribute_mem, - .write_attribute_mem = write_attribute_mem, - .read_cam_control = read_cam_control, - .write_cam_control = write_cam_control, - .slot_reset = slot_reset, - .slot_shutdown = slot_shutdown, - .slot_ts_enable = slot_ts_enable, - .poll_slot_status = poll_slot_status, -}; - -static void ci_attach(struct ddb_port *port) -{ - struct ddb_ci *ci = 0; - - ci = kzalloc(sizeof(*ci), GFP_KERNEL); - if (!ci) - return; - memcpy(&ci->en, &en_templ, sizeof(en_templ)); - ci->en.data = ci; - port->en = &ci->en; - ci->port = port; - ci->nr = port->nr - 2; -} - -/****************************************************************************/ -/****************************************************************************/ -/****************************************************************************/ - - -struct cxd2099_cfg cxd_cfg = { - .bitrate = 72000, - .adr = 0x40, - .polarity = 1, - .clock_mode = 1, //2, -}; - -static int ddb_ci_attach(struct ddb_port *port) -{ - if (port->type == DDB_CI_EXTERNAL_SONY) { - cxd_cfg.bitrate = ci_bitrate; - port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); - if (!port->en) - return -ENODEV; - dvb_ca_en50221_init(port->dvb[0].adap, - port->en, 0, 1); - } - if (port->type == DDB_CI_INTERNAL) { - ci_attach(port); - if (!port->en) - return -ENODEV; - dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1); - } - return 0; -} - -static int ddb_port_attach(struct ddb_port *port) -{ - int ret = 0; - - switch (port->class) { - case DDB_PORT_TUNER: - ret = dvb_input_attach(port->input[0]); - if (ret < 0) - break; - ret = dvb_input_attach(port->input[1]); - if (ret < 0) - break; - port->input[0]->redi = port->input[0]; - port->input[1]->redi = port->input[1]; - break; - case DDB_PORT_CI: - ret = ddb_ci_attach(port); - if (ret < 0) - break; - case DDB_PORT_LOOP: - ret = dvb_register_device(port->dvb[0].adap, - &port->dvb[0].dev, - &dvbdev_ci, (void *) port->output, - DVB_DEVICE_CI); - break; - case DDB_PORT_MOD: - ret = dvb_register_device(port->dvb[0].adap, - &port->dvb[0].dev, - &dvbdev_mod, (void *) port->output, - DVB_DEVICE_MOD); - break; - default: - break; - } - if (ret < 0) - printk(KERN_ERR "port_attach on port %d failed\n", port->nr); - return ret; -} - -static int ddb_ports_attach(struct ddb *dev) -{ - int i, ret = 0; - struct ddb_port *port; - - if (dev->info->port_num) { - ret = dvb_register_adapters(dev); - if (ret < 0) - return ret; - } - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - ret = ddb_port_attach(port); - if (ret < 0) - break; - } - return ret; -} - -static void ddb_ports_detach(struct ddb *dev) -{ - int i; - struct ddb_port *port; - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - - switch (port->class) { - case DDB_PORT_TUNER: - dvb_input_detach(port->input[0]); - dvb_input_detach(port->input[1]); - break; - case DDB_PORT_CI: - case DDB_PORT_LOOP: - if (port->dvb[0].dev) - dvb_unregister_device(port->dvb[0].dev); - if (port->en) { - dvb_ca_en50221_release(port->en); - kfree(port->en); - port->en = 0; - } - break; - case DDB_PORT_MOD: - if (port->dvb[0].dev) - dvb_unregister_device(port->dvb[0].dev); - break; - } - } - dvb_unregister_adapters(dev); -} - - -/* Copy input DMA pointers to output DMA and ACK. */ - -static void input_write_output(struct ddb_input *input, - struct ddb_output *output) -{ - ddbwritel(output->port->dev, - input->dma->stat, DMA_BUFFER_ACK(output->dma->nr)); - output->dma->cbuf = (input->dma->stat >> 11) & 0x1f; - output->dma->coff = (input->dma->stat & 0x7ff) << 7; -} - -static void output_ack_input(struct ddb_output *output, - struct ddb_input *input) -{ - ddbwritel(input->port->dev, - output->dma->stat, DMA_BUFFER_ACK(input->dma->nr)); -} - -static void input_write_dvb(struct ddb_input *input, - struct ddb_input *input2) -{ - struct ddb_dvb *dvb = &input2->port->dvb[input2->nr & 1]; - struct ddb_dma *dma, *dma2; - struct ddb *dev = input->port->dev; - int noack = 0; - - dma = dma2 = input->dma; - /* if there also is an output connected, do not ACK. - input_write_output will ACK. */ - if (input->redo) { - dma2 = input->redo->dma; - noack = 1; - } - while (dma->cbuf != ((dma->stat >> 11) & 0x1f) - || (4 & dma->ctrl)) { - if (4 & dma->ctrl) { - //printk(KERN_ERR "Overflow dma %d\n", dma->nr); - if (noack) - noack = 0; - } -#ifdef DDB_ALT_DMA - dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf], - dma2->size, DMA_FROM_DEVICE); -#endif - dvb_dmx_swfilter_packets(&dvb->demux, - dma2->vbuf[dma->cbuf], - dma2->size / 188); - dma->cbuf = (dma->cbuf + 1) % dma2->num; - if (!noack) - ddbwritel(dev, (dma->cbuf << 11), - DMA_BUFFER_ACK(dma->nr)); - dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); - dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); - } -} - -#ifdef DDB_USE_WORK -static void input_work(struct work_struct *work) -{ - struct ddb_dma *dma = container_of(work, struct ddb_dma, work); - struct ddb_input *input = (struct ddb_input *) dma->io; -#else -static void input_tasklet(unsigned long data) -{ - struct ddb_input *input = (struct ddb_input *) data; - struct ddb_dma *dma = input->dma; -#endif - struct ddb *dev = input->port->dev; - - spin_lock(&dma->lock); - if (!dma->running) { - spin_unlock(&dma->lock); - return; - } - dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); - dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); - - //printk(KERN_ERR "IT %d.%d %08x\n", dev->nr, dma->nr, dma->ctrl); -#if 0 - if (4 & dma->ctrl) - printk(KERN_ERR "Overflow dma %d\n", dma->nr); -#endif - if (input->redi) - input_write_dvb(input, input->redi); - if (input->redo) - input_write_output(input, input->redo); - wake_up(&dma->wq); - spin_unlock(&dma->lock); -} - -static void input_handler(unsigned long data) -{ - struct ddb_input *input = (struct ddb_input *) data; - struct ddb_dma *dma = input->dma; - - - /* If there is no input connected, input_tasklet() will - just copy pointers and ACK. So, there is no need to go - through the tasklet scheduler. */ -#ifdef DDB_USE_WORK - if (input->redi) - queue_work(ddb_wq, &dma->work); - else - input_work(&dma->work); -#else - if (input->redi) - tasklet_schedule(&dma->tasklet); - else - input_tasklet(data); -#endif -} - -/* hmm, don't really need this anymore. - The output IRQ just copies some pointers, acks and wakes. */ - -static void output_work(struct work_struct *work) -{ -} - -static void output_tasklet(unsigned long data) -{ -} - -static void output_handler(unsigned long data) -{ - struct ddb_output *output = (struct ddb_output *) data; - struct ddb_dma *dma = output->dma; - struct ddb *dev = output->port->dev; - - spin_lock(&dma->lock); - if (!dma->running) { - spin_unlock(&dma->lock); - return; - } - dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); - dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); - if (output->redi) - output_ack_input(output, output->redi); - wake_up(&dma->wq); - spin_unlock(&dma->lock); -} - - -/****************************************************************************/ -/****************************************************************************/ - - -static void ddb_dma_init(struct ddb_dma *dma, int nr, void *io, int out) -{ -#ifndef DDB_USE_WORK - unsigned long priv = (unsigned long) io; -#endif - - dma->io = io; - dma->nr = nr; - spin_lock_init(&dma->lock); - init_waitqueue_head(&dma->wq); - if (out) { -#ifdef DDB_USE_WORK - INIT_WORK(&dma->work, output_work); -#else - tasklet_init(&dma->tasklet, output_tasklet, priv); -#endif - dma->num = OUTPUT_DMA_BUFS; - dma->size = OUTPUT_DMA_SIZE; - dma->div = OUTPUT_DMA_IRQ_DIV; - } else { -#ifdef DDB_USE_WORK - INIT_WORK(&dma->work, input_work); -#else - tasklet_init(&dma->tasklet, input_tasklet, priv); -#endif - dma->num = INPUT_DMA_BUFS; - dma->size = INPUT_DMA_SIZE; - dma->div = INPUT_DMA_IRQ_DIV; - } -} - -static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int dma_nr) -{ - struct ddb *dev = port->dev; - struct ddb_input *input = &dev->input[nr]; - - if (dev->has_dma) { - dev->handler[dma_nr + 8] = input_handler; - dev->handler_data[dma_nr + 8] = (unsigned long) input; - } - port->input[pnr] = input; - input->nr = nr; - input->port = port; - if (dev->has_dma) { - input->dma = &dev->dma[dma_nr]; - ddb_dma_init(input->dma, dma_nr, (void *) input, 0); - } - ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); - ddbwritel(dev, 2, TS_INPUT_CONTROL(nr)); - ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); - if (dev->has_dma) - ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); -} - -static void ddb_output_init(struct ddb_port *port, int nr, int dma_nr) -{ - struct ddb *dev = port->dev; - struct ddb_output *output = &dev->output[nr]; - - if (dev->has_dma) { - dev->handler[dma_nr + 8] = output_handler; - dev->handler_data[dma_nr + 8] = (unsigned long) output; - } - port->output = output; - output->nr = nr; - output->port = port; - if (dev->has_dma) { - output->dma = &dev->dma[dma_nr]; - ddb_dma_init(output->dma, dma_nr, (void *) output, 1); - } - if (output->port->class == DDB_PORT_MOD) { - //ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); - } else { - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); - ddbwritel(dev, 2, TS_OUTPUT_CONTROL(nr)); - ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); - } - if (dev->has_dma) - ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); -} - -static void ddb_ports_init(struct ddb *dev) -{ - int i; - struct ddb_port *port; - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - port->dev = dev; - port->nr = i; - port->i2c = &dev->i2c[i]; - port->gap = 4; - port->obr = ci_bitrate; - mutex_init(&port->i2c_gate_lock); - ddb_port_probe(port); - port->dvb[0].adap = &dev->adap[2 * i]; - port->dvb[1].adap = &dev->adap[2 * i + 1]; - - if ((dev->info->type == DDB_OCTOPUS_CI) || - (dev->info->type == DDB_OCTONET) || - (dev->info->type == DDB_OCTOPUS)) { - if (i >= 2 && dev->info->type == DDB_OCTOPUS_CI) { - ddb_input_init(port, 2 + i, 0, 2 + i); - ddb_input_init(port, 4 + i, 1, 4 + i); - } else { - ddb_input_init(port, 2 * i, 0, 2 * i); - ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1); - } - ddb_output_init(port, i, i + 8); - } - if (dev->info->type == DDB_MOD) { - ddb_output_init(port, i, i); - dev->handler[i + 18] = ddbridge_mod_rate_handler; - dev->handler_data[i + 18] = - (unsigned long) &dev->output[i]; - } - } -} - -static void ddb_ports_release(struct ddb *dev) -{ - int i; - struct ddb_port *port; - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; -#ifdef DDB_USE_WORK - if (port->input[0]) - cancel_work_sync(&port->input[0]->dma->work); - if (port->input[1]) - cancel_work_sync(&port->input[1]->dma->work); - if (port->output) - cancel_work_sync(&port->output->dma->work); -#else - if (port->input[0]) - tasklet_kill(&port->input[0]->dma->tasklet); - if (port->input[1]) - tasklet_kill(&port->input[1]->dma->tasklet); - if (port->output) - tasklet_kill(&port->output->dma->tasklet); -#endif - } -} - -/****************************************************************************/ -/****************************************************************************/ -/****************************************************************************/ - -#define IRQ_HANDLE(_nr) if ((s & (1UL << _nr)) && dev->handler[_nr]) \ - dev->handler[_nr](dev->handler_data[_nr]); - -static void irq_handle_msg(struct ddb *dev, u32 s) -{ - dev->i2c_irq++; - IRQ_HANDLE(0); - IRQ_HANDLE(1); - IRQ_HANDLE(2); - IRQ_HANDLE(3); -} - -static void irq_handle_io(struct ddb *dev, u32 s) -{ - dev->ts_irq++; - IRQ_HANDLE(8); - IRQ_HANDLE(9); - IRQ_HANDLE(10); - IRQ_HANDLE(11); - IRQ_HANDLE(12); - IRQ_HANDLE(13); - IRQ_HANDLE(14); - IRQ_HANDLE(15); - IRQ_HANDLE(16); - IRQ_HANDLE(17); - IRQ_HANDLE(18); - IRQ_HANDLE(19); - if (dev->info->type != DDB_MOD) - return; - IRQ_HANDLE(20); - IRQ_HANDLE(21); - IRQ_HANDLE(22); - IRQ_HANDLE(23); - IRQ_HANDLE(24); - IRQ_HANDLE(25); - IRQ_HANDLE(26); - IRQ_HANDLE(27); -} - -static irqreturn_t irq_handler0(int irq, void *dev_id) -{ - struct ddb *dev = (struct ddb *) dev_id; - u32 s = ddbreadl(dev, INTERRUPT_STATUS); - - do { - if (s & 0x80000000) - return IRQ_NONE; - if (!(s & 0xfff00)) - return IRQ_NONE; - ddbwritel(dev, s, INTERRUPT_ACK); - irq_handle_io(dev, s); - } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); - - return IRQ_HANDLED; -} - -static irqreturn_t irq_handler1(int irq, void *dev_id) -{ - struct ddb *dev = (struct ddb *) dev_id; - u32 s = ddbreadl(dev, INTERRUPT_STATUS); - - do { - if (s & 0x80000000) - return IRQ_NONE; - if (!(s & 0x0000f)) - return IRQ_NONE; - ddbwritel(dev, s, INTERRUPT_ACK); - irq_handle_msg(dev, s); - } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); - - return IRQ_HANDLED; -} - -static irqreturn_t irq_handler(int irq, void *dev_id) -{ - struct ddb *dev = (struct ddb *) dev_id; - u32 s = ddbreadl(dev, INTERRUPT_STATUS); - int ret = IRQ_HANDLED; - - if (!s) - return IRQ_NONE; - do { - if (s & 0x80000000) - return IRQ_NONE; - ddbwritel(dev, s, INTERRUPT_ACK); - - if (s & 0x0000000f) - irq_handle_msg(dev, s); - if (s & 0x0fffff00) { - irq_handle_io(dev, s); -#ifdef DDB_TEST_THREADED - ret = IRQ_WAKE_THREAD; -#endif - } - } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); - - return ret; -} - -static irqreturn_t irq_thread(int irq, void *dev_id) -{ - struct ddb *dev = (struct ddb *) dev_id; - - //printk("%s\n", __func__); - - return IRQ_HANDLED; -} - - -/****************************************************************************/ -/****************************************************************************/ -/****************************************************************************/ - -static ssize_t nsd_read(struct file *file, char *buf, - size_t count, loff_t *ppos) -{ - return 0; -} - -static unsigned int nsd_poll(struct file *file, poll_table *wait) -{ - return 0; -} - -static int nsd_release(struct inode *inode, struct file *file) -{ - return dvb_generic_release(inode, file); -} - -static int nsd_open(struct inode *inode, struct file *file) -{ - return dvb_generic_open(inode, file); -} - -static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct ddb *dev = dvbdev->priv; - - unsigned long arg = (unsigned long) parg; - int ret = 0; - - switch (cmd) { - case NSD_START_GET_TS: - { - struct dvb_nsd_ts *ts = parg; - u32 ctrl = ((ts->input & 7) << 8) | (ts->filter_mask << 2); - u32 to; - int i; - - if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) { - printk("ts capture busy\n"); - return -EBUSY; - } - ddb_dvb_input_start(&dev->input[ts->input & 7]); - - ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL); - ddbwritel(dev, ts->pid, TS_CAPTURE_PID); - ddbwritel(dev, (ts->section_id << 16) | (ts->table << 8) | ts->section, - TS_CAPTURE_TABLESECTION); - /* 1024 ms default timeout if timeout set to 0 */ - if (ts->timeout) - to = ts->timeout; - else - to = 1024; - /* 21 packets default if num set to 0 */ - if (ts->num) - to |= ((u32) ts->num << 16); - else - to |= (21 << 16); - ddbwritel(dev, to, TS_CAPTURE_TIMEOUT); - if (ts->mode) - ctrl |= 2; - ddbwritel(dev, ctrl | 1, TS_CAPTURE_CONTROL); - -#if 0 - for (i = 0; i < (ts->timeout / 100); i++) { - if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) - msleep(100); - else - break; - } - //printk("ts capture done %d\n", i); - if ((ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) || - (ddbreadl(dev, TS_CAPTURE_CONTROL) & (1 << 14))) { - //printk("ts capture timeout\n"); - ddb_dvb_input_stop(&dev->input[ts->input & 7]); - return -EAGAIN; - } - ddb_dvb_input_stop(&dev->input[ts->input & 7]); - ddbcpyfrom(dev, dev->tsbuf, TS_CAPTURE_MEMORY, TS_CAPTURE_LEN); - ts->len = ddbreadl(dev, TS_CAPTURE_RECEIVED) & 0xfff; - ret = copy_to_user(ts->ts, dev->tsbuf, ts->len); - if (ret < 0) - return ret; -#endif - break; - } - case NSD_POLL_GET_TS: - { - struct dvb_nsd_ts *ts = parg; - u32 ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL); - - if (ctrl & 1) { - return -EBUSY; - } - if (ctrl & (1 << 14)) { - //printk("ts capture timeout\n"); - return -EAGAIN; - } - ddbcpyfrom(dev, dev->tsbuf, TS_CAPTURE_MEMORY, TS_CAPTURE_LEN); - ts->len = ddbreadl(dev, TS_CAPTURE_RECEIVED) & 0xfff; - if (copy_to_user(ts->ts, dev->tsbuf, ts->len) < 0) - return -EIO; - break; - } - case NSD_CANCEL_GET_TS: - { - u32 ctrl = 0; - printk("cancel ts capture: 0x%x\n", ctrl); - ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL); - ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL); - //printk("control register is 0x%x\n", ctrl); - break; - } - case NSD_STOP_GET_TS: - { - struct dvb_nsd_ts *ts = parg; - if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) { - printk("cannot stop ts capture, while it was neither finished not canceled\n"); - return -EBUSY; - } - //printk("ts capture stopped\n"); - ddb_dvb_input_stop(&dev->input[ts->input & 7]); - break; - } - default: - ret = -EINVAL; - break; - } - return ret; -} - -static long nsd_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - return dvb_usercopy(file, cmd, arg, nsd_do_ioctl); -} - -static const struct file_operations nsd_fops = { - .owner = THIS_MODULE, - .read = nsd_read, - .open = nsd_open, - .release = nsd_release, - .poll = nsd_poll, - .unlocked_ioctl = nsd_ioctl, -}; - -static struct dvb_device dvbdev_nsd = { - .priv = 0, - .readers = 1, - .writers = 1, - .users = 1, - .fops = &nsd_fops, -}; - -static int ddb_nsd_attach(struct ddb *dev) -{ - int ret; - - ret = dvb_register_device(&dev->adap[0], - &dev->nsd_dev, - &dvbdev_nsd, (void *) dev, - DVB_DEVICE_NSD); - return ret; -} - -static void ddb_nsd_detach(struct ddb *dev) -{ - if (dev->nsd_dev->users > 2) { - wait_event(dev->nsd_dev->wait_queue, - dev->nsd_dev->users == 2); - } - dvb_unregister_device(dev->nsd_dev); -} - - -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ - -static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) -{ - u32 data, shift; - - if (wlen > 4) - ddbwritel(dev, 1, SPI_CONTROL); - while (wlen > 4) { - /* FIXME: check for big-endian */ - data = swab32(*(u32 *)wbuf); - wbuf += 4; - wlen -= 4; - ddbwritel(dev, data, SPI_DATA); - while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - } - - if (rlen) - ddbwritel(dev, 0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); - else - ddbwritel(dev, 0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); - - data = 0; - shift = ((4 - wlen) * 8); - while (wlen) { - data <<= 8; - data |= *wbuf; - wlen--; - wbuf++; - } - if (shift) - data <<= shift; - ddbwritel(dev, data, SPI_DATA); - while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - - if (!rlen) { - ddbwritel(dev, 0, SPI_CONTROL); - return 0; - } - if (rlen > 4) - ddbwritel(dev, 1, SPI_CONTROL); - - while (rlen > 4) { - ddbwritel(dev, 0xffffffff, SPI_DATA); - while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - data = ddbreadl(dev, SPI_DATA); - *(u32 *) rbuf = swab32(data); - rbuf += 4; - rlen -= 4; - } - ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); - ddbwritel(dev, 0xffffffff, SPI_DATA); - while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - - data = ddbreadl(dev, SPI_DATA); - ddbwritel(dev, 0, SPI_CONTROL); - - if (rlen < 4) - data <<= ((4 - rlen) * 8); - - while (rlen > 0) { - *rbuf = ((data >> 24) & 0xff); - data <<= 8; - rbuf++; - rlen--; - } - return 0; -} - -int ddbridge_flashread(struct ddb *dev, u8 *buf, u32 addr, u32 len) -{ - u8 cmd[4] = {0x03, (addr >> 16) & 0xff, - (addr >> 8) & 0xff, addr & 0xff}; - - return flashio(dev, cmd, 4, buf, len); -} - -static int mdio_write(struct ddb *dev, u8 adr, u8 reg, u16 val) -{ - ddbwritel(dev, adr, MDIO_ADR); - ddbwritel(dev, reg, MDIO_REG); - ddbwritel(dev, val, MDIO_VAL); - ddbwritel(dev, 0x03, MDIO_CTRL); - while (ddbreadl(dev, MDIO_CTRL) & 0x02); - return 0; -} - -static u16 mdio_read(struct ddb *dev, u8 adr, u8 reg) -{ - ddbwritel(dev, adr, MDIO_ADR); - ddbwritel(dev, reg, MDIO_REG); - ddbwritel(dev, 0x07, MDIO_CTRL); - while (ddbreadl(dev, MDIO_CTRL) & 0x02); - return ddbreadl(dev, MDIO_VAL); -} - -#define DDB_MAGIC 'd' - -struct ddb_flashio { - __u8 *write_buf; - __u32 write_len; - __u8 *read_buf; - __u32 read_len; -}; - -struct ddb_gpio { - __u32 mask; - __u32 data; -}; - -struct ddb_id { - __u16 vendor; - __u16 device; - __u16 subvendor; - __u16 subdevice; - __u32 hw; - __u32 regmap; -}; - -struct ddb_reg { - __u32 reg; - __u32 val; -}; - -struct ddb_mem { - __u32 off; - __u8 *buf; - __u32 len; -}; - -struct ddb_mdio { - __u8 adr; - __u8 reg; - __u16 val; -}; - -#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) -#define IOCTL_DDB_GPIO_IN _IOWR(DDB_MAGIC, 0x01, struct ddb_gpio) -#define IOCTL_DDB_GPIO_OUT _IOWR(DDB_MAGIC, 0x02, struct ddb_gpio) -#define IOCTL_DDB_ID _IOR(DDB_MAGIC, 0x03, struct ddb_id) -#define IOCTL_DDB_READ_REG _IOWR(DDB_MAGIC, 0x04, struct ddb_reg) -#define IOCTL_DDB_WRITE_REG _IOW(DDB_MAGIC, 0x05, struct ddb_reg) -#define IOCTL_DDB_READ_MEM _IOWR(DDB_MAGIC, 0x06, struct ddb_mem) -#define IOCTL_DDB_WRITE_MEM _IOR(DDB_MAGIC, 0x07, struct ddb_mem) -#define IOCTL_DDB_READ_MDIO _IOWR(DDB_MAGIC, 0x08, struct ddb_mdio) -#define IOCTL_DDB_WRITE_MDIO _IOR(DDB_MAGIC, 0x09, struct ddb_mdio) - -#define DDB_NAME "ddbridge" - -static u32 ddb_num; -static int ddb_major; -static DEFINE_MUTEX(ddb_mutex); - -static int ddb_release(struct inode *inode, struct file *file) -{ - struct ddb *dev = file->private_data; - - dev->ddb_dev_users--; - return 0; -} - -static int ddb_open(struct inode *inode, struct file *file) -{ - struct ddb *dev = ddbs[iminor(inode)]; - - if (dev->ddb_dev_users) - return -EBUSY; - dev->ddb_dev_users++; - file->private_data = dev; - return 0; -} - -static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - struct ddb *dev = file->private_data; - void *parg = (void *)arg; - int res; - - switch (cmd) { - case IOCTL_DDB_FLASHIO: - { - struct ddb_flashio fio; - u8 *rbuf, *wbuf; - - if (copy_from_user(&fio, parg, sizeof(fio))) - return -EFAULT; - - if (fio.write_len > 1028 || fio.read_len > 1028) - return -EINVAL; - if (fio.write_len + fio.read_len > 1028) - return -EINVAL; - - wbuf = &dev->iobuf[0]; - rbuf = wbuf + fio.write_len; - - if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) - return -EFAULT; - res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len); - if (res) - return res; - if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) - return -EFAULT; - break; - } - case IOCTL_DDB_GPIO_OUT: - { - struct ddb_gpio gpio; - if (copy_from_user(&gpio, parg, sizeof(gpio))) - return -EFAULT; - ddbwritel(dev, gpio.mask, GPIO_DIRECTION); - ddbwritel(dev, gpio.data, GPIO_OUTPUT); - break; - } - case IOCTL_DDB_ID: - { - struct ddb_id ddbid; - - ddbid.vendor = dev->id->vendor; - ddbid.device = dev->id->device; - ddbid.subvendor = dev->id->subvendor; - ddbid.subdevice = dev->id->subdevice; - ddbid.hw = ddbreadl(dev, 0); - ddbid.regmap = ddbreadl(dev, 4); - if (copy_to_user(parg, &ddbid, sizeof(ddbid))) - return -EFAULT; - break; - } - case IOCTL_DDB_READ_REG: - { - struct ddb_reg reg; - - if (copy_from_user(®, parg, sizeof(reg))) - return -EFAULT; - if (reg.reg >= dev->regs_len) - return -EINVAL; - reg.val = ddbreadl(dev, reg.reg); - if (copy_to_user(parg, ®, sizeof(reg))) - return -EFAULT; - break; - } - case IOCTL_DDB_WRITE_REG: - { - struct ddb_reg reg; - - if (copy_from_user(®, parg, sizeof(reg))) - return -EFAULT; - if (reg.reg >= dev->regs_len) - return -EINVAL; - ddbwritel(dev, reg.val, reg.reg); - break; - } - case IOCTL_DDB_READ_MDIO: - { - struct ddb_mdio mdio; - - if (copy_from_user(&mdio, parg, sizeof(mdio))) - return -EFAULT; - mdio.val = mdio_read(dev, mdio.adr, mdio.reg); - if (copy_to_user(parg, &mdio, sizeof(mdio))) - return -EFAULT; - break; - } - case IOCTL_DDB_WRITE_MDIO: - { - struct ddb_mdio mdio; - - if (copy_from_user(&mdio, parg, sizeof(mdio))) - return -EFAULT; - mdio_write(dev, mdio.adr, mdio.reg, mdio.val); - break; - } - case IOCTL_DDB_READ_MEM: - { - struct ddb_mem mem; - u8 *buf = &dev->iobuf[0]; - - if (copy_from_user(&mem, parg, sizeof(mem))) - return -EFAULT; - if ((mem.len + mem.off > dev->regs_len) || - mem.len > 1024) - return -EINVAL; - ddbcpyfrom(dev, buf, mem.off, mem.len); - if (copy_to_user(mem.buf, buf, mem.len)) - return -EFAULT; - break; - } - case IOCTL_DDB_WRITE_MEM: - { - struct ddb_mem mem; - u8 *buf = &dev->iobuf[0]; - - if (copy_from_user(&mem, parg, sizeof(mem))) - return -EFAULT; - if ((mem.len + mem.off > dev->regs_len) || - mem.len > 1024) - return -EINVAL; - if (copy_from_user(buf, mem.buf, mem.len)) - return -EFAULT; - ddbcpyto(dev, mem.off, buf, mem.len); - break; - } - default: - return -ENOTTY; - } - return 0; -} - -static const struct file_operations ddb_fops = { - .unlocked_ioctl = ddb_ioctl, - .open = ddb_open, - .release = ddb_release, -}; - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) -static char *ddb_devnode(struct device *device, mode_t *mode) -#else -static char *ddb_devnode(struct device *device, umode_t *mode) -#endif -{ - struct ddb *dev = dev_get_drvdata(device); - - return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); -} - -#define __ATTR_MRO(_name, _show) { \ - .attr = { .name = __stringify(_name), .mode = 0444 }, \ - .show = _show, \ -} - -#define __ATTR_MWO(_name, _store) { \ - .attr = { .name = __stringify(_name), .mode = 0222 }, \ - .store = _store, \ -} - -static ssize_t ports_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - - return sprintf(buf, "%d\n", dev->info->port_num); -} - -static ssize_t ts_irq_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - - return sprintf(buf, "%d\n", dev->ts_irq); -} - -static ssize_t i2c_irq_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - - return sprintf(buf, "%d\n", dev->i2c_irq); -} - -static char *class_name[] = { - "NONE", "CI", "TUNER", "LOOP" -}; - -static char *type_name[] = { - "NONE", "DVBS_ST", "DVBS_ST_AA", "DVBCT_TR", "DVBCT_ST", "INTERNAL", "CXD2099", -}; - -static ssize_t fan_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - u32 val; - - val = ddbreadl(dev, GPIO_OUTPUT) & 1; - return sprintf(buf, "%d\n", val); -} - -static ssize_t fan_store(struct device *device, struct device_attribute *d, - const char *buf, size_t count) -{ - struct ddb *dev = dev_get_drvdata(device); - unsigned val; - - if (sscanf(buf, "%u\n", &val) != 1) - return -EINVAL; - ddbwritel(dev, 1, GPIO_DIRECTION); - ddbwritel(dev, val & 1, GPIO_OUTPUT); - return count; -} - -static ssize_t temp_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - struct i2c_adapter *adap; - int temp, temp2; - u8 tmp[2]; - - if (dev->info->type == DDB_MOD) { - ddbwritel(dev, 1, TEMPMON_CONTROL); - msleep(5); - temp = ddbreadl(dev, TEMPMON_SENSOR1); - temp2 = ddbreadl(dev, TEMPMON_SENSOR2); - temp = (temp * 1000) >> 8; - temp2 = (temp2 * 1000) >> 8; - return sprintf(buf, "%d %d\n", temp, temp2); - } - if (!dev->info->temp_num) - return sprintf(buf, "no sensor\n"); - adap = &dev->i2c[dev->info->temp_bus].adap; - if (i2c_read_regs(adap, 0x48, 0, tmp, 2) < 0) - return sprintf(buf, "read_error\n"); - temp = (tmp[0] << 3) | (tmp[1] >> 5); - temp *= 125; - if (dev->info->temp_num == 2) { - if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0) - return sprintf(buf, "read_error\n"); - temp2 = (tmp[0] << 3) | (tmp[1] >> 5); - temp2 *= 125; - return sprintf(buf, "%d %d\n", temp, temp2); - } - return sprintf(buf, "%d\n", temp); -} - -static ssize_t qam_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - struct i2c_adapter *adap; - u8 tmp[4]; - s16 i, q; - - adap = &dev->i2c[1].adap; - if (i2c_read_regs16(adap, 0x1f, 0xf480, tmp, 4) < 0) - return sprintf(buf, "read_error\n"); - i = (s16) (((u16) tmp[1]) << 14) | (((u16) tmp[0]) << 6); - q = (s16) (((u16) tmp[3]) << 14) | (((u16) tmp[2]) << 6); - - return sprintf(buf, "%d %d\n", i, q); -} - -static ssize_t mod_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - int num = attr->attr.name[3] - 0x30; - - return sprintf(buf, "%s:%s\n", - class_name[dev->port[num].class], - type_name[dev->port[num].type]); -} - -static ssize_t led_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - int num = attr->attr.name[3] - 0x30; - - return sprintf(buf, "%d\n", dev->leds & (1 << num) ? 1 : 0); -} - - -static void ddb_set_led(struct ddb *dev, int num, int val) -{ - if (!dev->info->led_num) - return; - switch (dev->port[num].class) { - case DDB_PORT_TUNER: - switch (dev->port[num].type) { - case DDB_TUNER_DVBS_ST: - i2c_write_reg16(&dev->i2c[num].adap, - 0x69, 0xf14c, val ? 2 : 0); - break; - case DDB_TUNER_DVBCT_ST: - i2c_write_reg16(&dev->i2c[num].adap, - 0x1f, 0xf00e, 0); - i2c_write_reg16(&dev->i2c[num].adap, - 0x1f, 0xf00f, val ? 1 : 0); - break; - } - break; - default: - break; - } -} - -static ssize_t led_store(struct device *device, struct device_attribute *attr, - const char *buf, size_t count) -{ - struct ddb *dev = dev_get_drvdata(device); - int num = attr->attr.name[3] - 0x30; - unsigned val; - - if (sscanf(buf, "%u\n", &val) != 1) - return -EINVAL; - if (val) - dev->leds |= (1 << num); - else - dev->leds &= ~(1 << num); - ddb_set_led(dev, num, val); - return count; -} - -static ssize_t snr_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - char snr[32]; - int num = attr->attr.name[3] - 0x30; - - /* serial number at 0x100-0x11f */ - if (i2c_read_regs16(&dev->i2c[num].adap, 0x50, 0x100, snr, 32) < 0) - if (i2c_read_regs16(&dev->i2c[num].adap, 0x57, 0x100, snr, 32) < 0) - return sprintf(buf, "NO SNR\n"); - snr[31]=0; /* in case it is not terminated on EEPROM */ - return sprintf(buf, "%s\n", snr); -} - - -static ssize_t snr_store(struct device *device, struct device_attribute *attr, - const char *buf, size_t count) -{ - struct ddb *dev = dev_get_drvdata(device); - int num = attr->attr.name[3] - 0x30; - u8 snr[34] = { 0x01, 0x00 }; - - if (count > 31) - return -EINVAL; - memcpy(snr + 2, buf, count); - i2c_write(&dev->i2c[num].adap, 0x57, snr, 34); - i2c_write(&dev->i2c[num].adap, 0x50, snr, 34); - return count; -} - -static ssize_t bsnr_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - char snr[16]; - - ddbridge_flashread(dev, snr, 0x10, 15); - snr[15]=0; /* in case it is not terminated on EEPROM */ - return sprintf(buf, "%s\n", snr); -} - -static ssize_t redirect_show(struct device *device, struct device_attribute *attr, char *buf) -{ - return 0; -} - -static ssize_t redirect_store(struct device *device, struct device_attribute *attr, - const char *buf, size_t count) -{ - unsigned int i, p; - int res; - - if (sscanf(buf, "%x %x\n", &i, &p) != 2) - return -EINVAL; - res = ddb_redirect(i, p); - if (res < 0) - return res; - printk(KERN_INFO "redirect: %02x, %02x\n", i, p); - return count; -} - -static ssize_t gap_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - int num = attr->attr.name[3] - 0x30; - - return sprintf(buf, "%d\n", dev->port[num].gap); - -} -static ssize_t gap_store(struct device *device, struct device_attribute *attr, - const char *buf, size_t count) -{ - struct ddb *dev = dev_get_drvdata(device); - int num = attr->attr.name[3] - 0x30; - unsigned int val; - - if (sscanf(buf, "%u\n", &val) != 1) - return -EINVAL; - if (val > 20) - return -EINVAL; - dev->port[num].gap = val; - return count; -} - -static ssize_t version_show(struct device *device, struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - - return sprintf(buf, "%08x %08x\n", ddbreadl(dev, 0), ddbreadl(dev, 4)); -} - -static ssize_t hwid_show(struct device *device, - struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - - return sprintf(buf, "0x%08X\n", dev->hwid); -} - -static ssize_t regmap_show(struct device *device, - struct device_attribute *attr, char *buf) -{ - struct ddb *dev = dev_get_drvdata(device); - - return sprintf(buf, "0x%08X\n", dev->regmapid); -} - -static struct device_attribute ddb_attrs[] = { - __ATTR_RO(version), - __ATTR_RO(ports), - __ATTR_RO(ts_irq), - __ATTR_RO(i2c_irq), - __ATTR(gap0, 0666, gap_show, gap_store), - __ATTR(gap1, 0666, gap_show, gap_store), - __ATTR(gap2, 0666, gap_show, gap_store), - __ATTR(gap3, 0666, gap_show, gap_store), - __ATTR_RO(hwid), - __ATTR_RO(regmap), -#if 0 - __ATTR_RO(qam), -#endif - __ATTR(redirect, 0666, redirect_show, redirect_store), - __ATTR_MRO(snr, bsnr_show), - __ATTR_NULL, -}; - -static struct device_attribute ddb_attrs_temp[] = { - __ATTR_RO(temp), -}; - -static struct device_attribute ddb_attrs_mod[] = { - __ATTR_MRO(mod0, mod_show), - __ATTR_MRO(mod1, mod_show), - __ATTR_MRO(mod2, mod_show), - __ATTR_MRO(mod3, mod_show), -}; - -static struct device_attribute ddb_attrs_fan[] = { - __ATTR(fan, 0666, fan_show, fan_store), -}; - -static struct device_attribute ddb_attrs_snr[] = { - __ATTR(snr0, 0666, snr_show, snr_store), - __ATTR(snr1, 0666, snr_show, snr_store), - __ATTR(snr2, 0666, snr_show, snr_store), - __ATTR(snr3, 0666, snr_show, snr_store), -}; - -static struct device_attribute ddb_attrs_led[] = { - __ATTR(led0, 0666, led_show, led_store), - __ATTR(led1, 0666, led_show, led_store), - __ATTR(led2, 0666, led_show, led_store), - __ATTR(led3, 0666, led_show, led_store), -}; - -static struct class ddb_class = { - .name = "ddbridge", - .owner = THIS_MODULE, - .dev_attrs = ddb_attrs, - .devnode = ddb_devnode, -}; - -static int ddb_class_create(void) -{ - ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); - if (ddb_major < 0) - return ddb_major; - if (class_register(&ddb_class) < 0) - return -1; - return 0; -} - -static void ddb_class_destroy(void) -{ - class_unregister(&ddb_class); - unregister_chrdev(ddb_major, DDB_NAME); -} - -static void ddb_device_attrs_del(struct ddb *dev) -{ - int i; - - for (i = 0; i < dev->info->temp_num; i++) - device_remove_file(dev->ddb_dev, &ddb_attrs_temp[0]); - for (i = 0; i < dev->info->port_num; i++) - device_remove_file(dev->ddb_dev, &ddb_attrs_mod[i]); - for (i = 0; i < dev->info->fan_num; i++) - device_remove_file(dev->ddb_dev, &ddb_attrs_fan[0]); - for (i = 0; i < dev->info->i2c_num; i++) { - if (dev->info->led_num) - device_remove_file(dev->ddb_dev, &ddb_attrs_led[i]); - device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]); - } -} - -static int ddb_device_attrs_add(struct ddb *dev) -{ - int i, res = 0; - - for (i = 0; i < dev->info->temp_num; i++) - if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_temp[0]))) - goto fail; - for (i = 0; i < dev->info->port_num; i++) - if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_mod[i]))) - goto fail; - for (i = 0; i < dev->info->fan_num; i++) - if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_fan[0]))) - goto fail; - for (i = 0; i < dev->info->i2c_num; i++) { - if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_snr[i]))) - goto fail; - if (dev->info->led_num) - if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_led[i]))) - goto fail; - } -fail: - return res; -} - -static int ddb_device_create(struct ddb *dev) -{ - int res = 0; - - if (ddb_num == DDB_MAX_ADAPTER) - return -ENOMEM; - mutex_lock(&ddb_mutex); - dev->nr = ddb_num; - ddbs[dev->nr] = dev; - dev->ddb_dev = device_create(&ddb_class, dev->dev, - MKDEV(ddb_major, dev->nr), - dev, "ddbridge%d", dev->nr); - if (IS_ERR(dev->ddb_dev)) { - res = PTR_ERR(dev->ddb_dev); - printk(KERN_INFO "Could not create ddbridge%d\n", dev->nr); - goto fail; - } - res = ddb_device_attrs_add(dev); - if (res) { - ddb_device_attrs_del(dev); - device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); - ddbs[dev->nr] = 0; - dev->ddb_dev = ERR_PTR(-ENODEV); - } else - ddb_num++; -fail: - mutex_unlock(&ddb_mutex); - return res; -} - -static void ddb_device_destroy(struct ddb *dev) -{ - if (IS_ERR(dev->ddb_dev)) - return; - ddb_device_attrs_del(dev); - device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); -} - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,243 +0,0 @@ -/* - * ddbridge-i2c.c: Digital Devices bridge i2c driver - * - * Copyright (C) 2010-2013 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; - - return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; -} - -static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) -{ - struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -} - -static int i2c_read_regs(struct i2c_adapter *adapter, - u8 adr, u8 reg, u8 *val, u8 len) -{ - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = ®, .len = 1 }, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = len } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static int i2c_read_regs16(struct i2c_adapter *adapter, - u8 adr, u16 reg, u8 *val, u8 len) -{ - u8 reg16[2] = { reg >> 8, reg }; - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = reg16, .len = 2 }, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = len } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) -{ - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = ®, .len = 1}, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, - u16 reg, u8 *val) -{ - u8 msg[2] = {reg >> 8, reg & 0xff}; - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = msg, .len = 2}, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, - u16 reg, u8 val) -{ - u8 msg[3] = {reg >> 8, reg & 0xff, val}; - - return i2c_write(adap, adr, msg, 3); -} - -static int i2c_write_reg(struct i2c_adapter *adap, u8 adr, - u8 reg, u8 val) -{ - u8 msg[2] = {reg, val}; - - return i2c_write(adap, adr, msg, 2); -} - -static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) -{ - struct ddb *dev = i2c->dev; - int stat; - u32 val; - - //i2c->done = 0; - ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND); - //stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); - stat = wait_for_completion_timeout(&i2c->completion, HZ); - if (stat <= 0) { - printk(KERN_ERR "DDBridge I2C timeout, card %d, port %d\n", - dev->nr, i2c->nr); -#ifdef CONFIG_PCI_MSI - { /* MSI debugging*/ - u32 istat = ddbreadl(dev, INTERRUPT_STATUS); - printk(KERN_ERR "DDBridge IRS %08x\n", istat); - ddbwritel(dev, istat, INTERRUPT_ACK); - } -#endif - return -EIO; - } - val = ddbreadl(dev, i2c->regs + I2C_COMMAND); - if (val & 0x70000) - return -EIO; - return 0; -} - -static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, - struct i2c_msg msg[], int num) -{ - struct ddb_i2c *i2c = (struct ddb_i2c *) i2c_get_adapdata(adapter); - struct ddb *dev = i2c->dev; - u8 addr = 0; - - if (num) - addr = msg[0].addr; - if (num == 2 && msg[1].flags & I2C_M_RD && - !(msg[0].flags & I2C_M_RD)) { - memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, - msg[0].buf, msg[0].len); - ddbwritel(dev, msg[0].len|(msg[1].len << 16), - i2c->regs + I2C_TASKLENGTH); - if (!ddb_i2c_cmd(i2c, addr, 1)) { - memcpy_fromio(msg[1].buf, - dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, - msg[1].len); - return num; - } - } - if (num == 1 && !(msg[0].flags & I2C_M_RD)) { - ddbcpyto(dev, I2C_TASKMEM_BASE + i2c->wbuf, - msg[0].buf, msg[0].len); - ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH); - if (!ddb_i2c_cmd(i2c, addr, 2)) { - return num; - } - } - if (num == 1 && (msg[0].flags & I2C_M_RD)) { - ddbwritel(dev, msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); - if (!ddb_i2c_cmd(i2c, addr, 3)) { - ddbcpyfrom(dev, msg[0].buf, - I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); - return num; - } - } - return -EIO; -} - - -static u32 ddb_i2c_functionality(struct i2c_adapter *adap) -{ - return I2C_FUNC_SMBUS_EMUL; -} - -struct i2c_algorithm ddb_i2c_algo = { - .master_xfer = ddb_i2c_master_xfer, - .functionality = ddb_i2c_functionality, -}; - -static void ddb_i2c_release(struct ddb *dev) -{ - int i; - struct ddb_i2c *i2c; - struct i2c_adapter *adap; - - for (i = 0; i < dev->info->i2c_num; i++) { - i2c = &dev->i2c[i]; - adap = &i2c->adap; - i2c_del_adapter(adap); - } -} - -static void i2c_handler(unsigned long priv) -{ - struct ddb_i2c *i2c = (struct ddb_i2c *) priv; - - //i2c->done = 1; - //wake_up(&i2c->wq); - complete(&i2c->completion); -} - -static int ddb_i2c_init(struct ddb *dev) -{ - int i, j, stat = 0; - struct ddb_i2c *i2c; - struct i2c_adapter *adap; - - for (i = 0; i < dev->info->i2c_num; i++) { - i2c = &dev->i2c[i]; - dev->handler[i] = i2c_handler; - dev->handler_data[i] = (unsigned long) i2c; - i2c->dev = dev; - i2c->nr = i; - i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); - i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); - i2c->regs = 0x80 + i * 0x20; - ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING); - ddbwritel(dev, (i2c->rbuf << 16) | i2c->wbuf, - i2c->regs + I2C_TASKADDRESS); - //init_waitqueue_head(&i2c->wq); - init_completion(&i2c->completion); - - adap = &i2c->adap; - i2c_set_adapdata(adap, i2c); -#ifdef I2C_ADAP_CLASS_TV_DIGITAL - adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; -#else -#ifdef I2C_CLASS_TV_ANALOG - adap->class = I2C_CLASS_TV_ANALOG; -#endif -#endif - strcpy(adap->name, "ddbridge"); - adap->algo = &ddb_i2c_algo; - adap->algo_data = (void *)i2c; - adap->dev.parent = dev->dev; - stat = i2c_add_adapter(adap); - if (stat) - break; - } - if (stat) - for (j = 0; j < i; j++) { - i2c = &dev->i2c[j]; - adap = &i2c->adap; - i2c_del_adapter(adap); - } - return stat; -} - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-i2c.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,101 +0,0 @@ -/* - * ddbridge-i2c.h: Digital Devices bridge i2c driver - * - * Copyright (C) 2010-2013 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef _DDBRIDGE_I2C_H_ -#define _DDBRIDGE_I2C_H_ - -#include -#include - -static inline int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; - - return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; -} - -static inline int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) -{ - struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -} - -static inline int i2c_read_regs(struct i2c_adapter *adapter, - u8 adr, u8 reg, u8 *val, u8 len) -{ - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = ®, .len = 1 }, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = len } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static inline int i2c_read_regs16(struct i2c_adapter *adapter, - u8 adr, u16 reg, u8 *val, u8 len) -{ - u8 reg16[2] = { reg >> 8, reg }; - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = reg16, .len = 2 }, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = len } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static inline int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) -{ - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = ®, .len = 1}, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static inline int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, - u16 reg, u8 *val) -{ - u8 msg[2] = {reg >> 8, reg & 0xff}; - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = msg, .len = 2}, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -} - -static inline int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, - u16 reg, u8 val) -{ - u8 msg[3] = {reg >> 8, reg & 0xff, val}; - - return i2c_write(adap, adr, msg, 3); -} - -static inline int i2c_write_reg(struct i2c_adapter *adap, u8 adr, - u8 reg, u8 val) -{ - u8 msg[2] = {reg, val}; - - return i2c_write(adap, adr, msg, 2); -} - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-mod.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-mod.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-mod.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-mod.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1060 +0,0 @@ -#include "ddbridge.h" -#include "ddbridge-regs.h" - -#include - -inline s64 ConvertPCR(s64 a) -{ - s32 ext; - s64 b; - - b = div_s64_rem(a, 300 << 22, &ext); - - return (b << 31) | ext; - -} - -inline s64 NegConvertPCR(s64 a) -{ - s32 ext; - s64 b; - - b = -div_s64_rem(a, 300 << 22, &ext); - - if( ext != 0 ) { - ext = (300 << 22) - ext; - b -= 1; - } - return (b << 31) | ext; -} - -inline s64 RoundPCR(s64 a) -{ - s64 b = a + (HW_LSB_MASK>>1); - return b & ~(HW_LSB_MASK - 1); -} - -inline s64 RoundPCRUp(s64 a) -{ - s64 b = a + (HW_LSB_MASK - 1); - return b & ~(HW_LSB_MASK - 1); -} - -inline s64 RoundPCRDown(s64 a) -{ - return a & ~(HW_LSB_MASK - 1); -} - -static int mod_busy(struct ddb *dev, int chan) -{ - u32 creg; - - while (1) { - creg = ddbreadl(dev, CHANNEL_CONTROL(chan)); - if (creg == 0xffffffff) - return -EFAULT; - if ((creg & CHANNEL_CONTROL_BUSY) == 0) - break; - } - return 0; -} - -void ddbridge_mod_output_stop(struct ddb_output *output) -{ - struct ddb *dev = output->port->dev; - struct mod_state *mod= &dev->mod[output->nr]; - - mod->State = CM_IDLE; - mod->Control = 0; - ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); -#if 0 - udelay(10); - ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr)); - udelay(10); - ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); -#endif - mod_busy(dev, output->nr); - printk("mod_output_stop %d.%d\n", dev->nr, output->nr); -} - -static void mod_set_incs(struct ddb_output *output) -{ - s64 pcr; - struct ddb *dev = output->port->dev; - struct mod_state *mod= &dev->mod[output->nr]; - - pcr = ConvertPCR(mod->PCRIncrement); - ddbwritel(dev, pcr & 0xffffffff, - CHANNEL_PCR_ADJUST_OUTL(output->nr)); - ddbwritel(dev, (pcr >> 32) & 0xffffffff, - CHANNEL_PCR_ADJUST_OUTH(output->nr)); - mod_busy(dev, output->nr); - - pcr = NegConvertPCR(mod->PCRDecrement); - ddbwritel(dev, pcr & 0xffffffff, - CHANNEL_PCR_ADJUST_INL(output->nr)); - ddbwritel(dev, (pcr >> 32) & 0xffffffff, - CHANNEL_PCR_ADJUST_INH(output->nr)); - mod_busy(dev, output->nr); - -} - -static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 }; - -void ddbridge_mod_output_start(struct ddb_output *output) -{ - struct ddb *dev = output->port->dev; - struct mod_state *mod= &dev->mod[output->nr]; - - //PCRIncrement = RoundPCR(PCRIncrement); - //PCRDecrement = RoundPCR(PCRDecrement); - - mod->LastInPacketCount = 0; - mod->LastOutPacketCount = 0; - mod->InOverflowPacketCount = 0; - mod->OutOverflowPacketCount = 0; - mod->LastInPackets = 0; - mod->LastOutPackets = 0; - mod->LastPCRAdjust = 0; - mod->PCRRunningCorr = 0; - mod->MinInputPackets = 524288/2; // we interrupt every 0x80000=524288 packets - mod->PCRIncrement = 0;//PCRIncrement; - mod->PCRDecrement = 0;//PCRDecrement; - - mod->State = CM_STARTUP; - mod->StateCounter = CM_STARTUP_DELAY; - - ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); - udelay(10); - ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr)); - udelay(10); - ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); - - // QAM: 600 601 602 903 604 = 16 32 64 128 256 - //ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); - ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr)); - - ddbwritel(dev, mod->rate_inc, CHANNEL_RATE_INCR(output->nr)); - mod_busy(dev, output->nr); - - mod_set_incs(output); - - mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | - CHANNEL_CONTROL_ENABLE_DVB | - CHANNEL_CONTROL_ENABLE_SOURCE); - - ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr)); - printk("mod_output_start %d.%d\n", dev->nr, output->nr); -} - -/****************************************************************************/ -/****************************************************************************/ -/****************************************************************************/ - -static void mod_write_dac_register(struct ddb *dev, u8 Index, u8 Value) -{ - u32 RegValue = 0; - - ddbwritel(dev, Value, DAC_WRITE_DATA); - ddbwritel(dev, DAC_CONTROL_STARTIO | Index, DAC_CONTROL); - do { - RegValue = ddbreadl(dev, DAC_CONTROL); - } while ((RegValue & DAC_CONTROL_STARTIO) != 0 ); -} - -static void mod_write_dac_register2(struct ddb *dev, u8 Index, u16 Value) -{ - u32 RegValue = 0; - - ddbwritel(dev, Value, DAC_WRITE_DATA); - ddbwritel(dev, DAC_CONTROL_STARTIO | 0x20 | Index, DAC_CONTROL); - do { - RegValue = ddbreadl(dev, DAC_CONTROL); - } while ((RegValue & DAC_CONTROL_STARTIO) != 0 ); -} - -static int mod_read_dac_register(struct ddb *dev, u8 Index, u8 *pValue) -{ - u32 RegValue = 0; - - ddbwritel(dev, DAC_CONTROL_STARTIO | 0x80 | Index, DAC_CONTROL); - do { - RegValue = ddbreadl(dev, DAC_CONTROL); - } while( (RegValue & DAC_CONTROL_STARTIO) != 0 ); - - RegValue = ddbreadl(dev, DAC_READ_DATA); - *pValue = (u8) RegValue; - return 0; -} - -static void mod_set_up_converter_vco1(struct ddb *dev, u32 Value) -{ - u32 RegValue = 0; - - /* Extra delay before writing N divider */ - if ((Value & 0x03) == 0x02) - msleep(50); - do { - RegValue = ddbreadl(dev, VCO1_CONTROL); - } while( (RegValue & VCO1_CONTROL_WRITE) != 0 ); - - if ((RegValue & VCO1_CONTROL_CE) == 0) { - RegValue |= VCO1_CONTROL_CE; - ddbwritel(dev, RegValue, VCO1_CONTROL); - msleep(10); - } - - ddbwritel(dev, Value, VCO1_DATA); - ddbwritel(dev, RegValue | VCO1_CONTROL_WRITE, VCO1_CONTROL); -} - -static void mod_set_up_converter_vco2(struct ddb *dev, u32 Value) -{ - u32 RegValue = 0; - - /* Extra delay before writing N divider */ - if ((Value & 0x03) == 0x02) - msleep(50); - do { - RegValue = ddbreadl(dev, VCO2_CONTROL); - } while ((RegValue & VCO2_CONTROL_WRITE) != 0); - - if ((RegValue & VCO2_CONTROL_CE) == 0) { - RegValue |= VCO2_CONTROL_CE; - ddbwritel(dev, RegValue, VCO2_CONTROL); - msleep(10); - } - - ddbwritel(dev, Value, VCO2_DATA); - ddbwritel(dev, RegValue | VCO2_CONTROL_WRITE, VCO2_CONTROL); -} - -static void mod_set_down_converter_vco(struct ddb *dev, u32 Value) -{ - u32 RegValue = 0; - - do { - RegValue = ddbreadl(dev, VCO3_CONTROL); - } while( (RegValue & VCO3_CONTROL_WRITE) != 0 ); - - if ((RegValue & VCO3_CONTROL_CE) == 0) { - RegValue |= VCO3_CONTROL_CE; - ddbwritel(dev, RegValue, VCO3_CONTROL); - msleep(10); - } - ddbwritel(dev, Value, VCO3_DATA); - ddbwritel(dev, RegValue | VCO3_CONTROL_WRITE, VCO3_CONTROL); -} - -static int mod_set_attenuator(struct ddb *dev, u32 Value) -{ - if (Value > 31) - return -EINVAL; - ddbwritel(dev, Value, RF_ATTENUATOR); - return 0; -} - -static void mod_si598_readreg(struct ddb *dev, u8 index, u8 *val) -{ - ddbwritel(dev, index, CLOCKGEN_INDEX); - ddbwritel(dev, 1, CLOCKGEN_CONTROL); - msleep(5); - *val = ddbreadl(dev, CLOCKGEN_READDATA); -} - -static void mod_si598_writereg(struct ddb *dev, u8 index, u8 val) -{ - ddbwritel(dev, index, CLOCKGEN_INDEX); - ddbwritel(dev, val, CLOCKGEN_WRITEDATA); - ddbwritel(dev, 3, CLOCKGEN_CONTROL); - msleep(5); -} - -static int mod_set_si598(struct ddb *dev, u32 freq) -{ - u8 Data[6]; - u64 fDCO = 0; - u64 RFreq = 0; - u32 fOut = 10000000; - u64 m_fXtal = 0; - u32 N = 0; - u64 HSDiv = 0; - - u32 fxtal; - u64 MinDiv, MaxDiv, Div; - u64 RF; - - if (freq < 10000000 || freq > 525000000 ) - return -EINVAL; - mod_si598_writereg(dev, 137, 0x10); - - if (m_fXtal == 0) { - mod_si598_writereg(dev, 135, 0x01); - mod_si598_readreg(dev, 7, &Data[0]); - mod_si598_readreg(dev, 8, &Data[1]); - mod_si598_readreg(dev, 9, &Data[2]); - mod_si598_readreg(dev, 10, &Data[3]); - mod_si598_readreg(dev, 11, &Data[4]); - mod_si598_readreg(dev, 12, &Data[5]); - - printk(" Data = %02x %02x %02x %02x %02x %02x\n", - Data[0],Data[1],Data[2],Data[3],Data[4],Data[5]); - RFreq = (((u64)Data[1] & 0x3F) << 32) | ((u64)Data[2] << 24) | - ((u64)Data[3] << 16) | ((u64)Data[4] << 8) | ((u64)Data[5]); - if (RFreq == 0) - return -EINVAL; - HSDiv = ((Data[0] & 0xE0) >> 5) + 4; - if (HSDiv == 8 || HSDiv == 10 ) - return -EINVAL; - N = (((u32)(Data[0] & 0x1F) << 2) | ((u32)(Data[1] & 0xE0) >> 6)) + 1; - fDCO = fOut * (u64)(HSDiv * N); - m_fXtal = fDCO << 28; - printk("fxtal %016llx rfreq %016llx\n", m_fXtal, RFreq); - - m_fXtal += RFreq >> 1; - m_fXtal = div64_u64(m_fXtal, RFreq); - - printk(" fOut = %d fXtal = %d fDCO = %d HDIV = %2d, N = %3d \n", - (u32) fOut,(u32) m_fXtal,(u32) fDCO,HSDiv,N); - } - - fOut = freq; - MinDiv = 4850000000ULL; do_div(MinDiv, freq); MinDiv += 1; - MaxDiv = 5670000000ULL; do_div(MaxDiv, freq); - Div = 5260000000ULL; do_div(Div, freq); - - if( Div < MinDiv ) - Div = Div + 1; - printk(" fOut = %d MinDiv = %4d MaxDiv = %4d StartDiv = %d\n", fOut,MinDiv,MaxDiv,Div); - - if( Div <= 11 ) { - N = 1; - HSDiv = Div; - } else { - int retry = 100; - while (retry > 0) { - N = 0; - HSDiv = Div; - while( (HSDiv > 11) /*|| ((HSDiv * N) != Div)*/ ) { - N = N + 2; - HSDiv = Div; - do_div(HSDiv, N); - if (N > 128) - break; - } - printk(" %3d: %llu %u %u %u\n", retry, Div, HSDiv*N, HSDiv, N); - if (HSDiv * N < MinDiv) { - Div = Div + 2; - } else if (HSDiv * N > MaxDiv) { - Div = Div - 2; - } else - break; - retry = retry - 1; - } - if( retry == 0 ) { - printk(" FAIL \n"); - return -EINVAL; - } - } - - if (HSDiv == 8 || HSDiv == 10) { - HSDiv = HSDiv >> 1; - N = N * 2; - } - - if (HSDiv < 4) - return -EINVAL; - - - fDCO = (u64)fOut * (u64)N * (u64)HSDiv; - printk("fdco %16llx\n", fDCO); - RFreq = fDCO<<28; - printk("%16llx %16llx\n", fDCO, RFreq); - - fxtal = m_fXtal; - do_div(RFreq, fxtal); - printk("%16llx %d\n", RFreq, fxtal); - RF = RFreq; - - //printk("fOut = %d fXtal = %d fDCO = %d HDIV = %d, N = %d, RFreq = %d\n",fOut,m_fXtal,fDCO,HSDiv,N,RFreq); - //printk("%16llx\n", RF); - - Data[0] = (u8)( ((HSDiv - 4) << 5) | ((N - 1) >> 2) ); - Data[1] = (u8)( (((N - 1) & 0x03) << 6) | (( RF >> 32 ) & 0x3F ) ); - Data[2] = (u8)( (RF >> 24) & 0xFF ); - Data[3] = (u8)( (RF >> 16) & 0xFF ); - Data[4] = (u8)( (RF >> 8) & 0xFF ); - Data[5] = (u8)( (RF ) & 0xFF ); - - printk(" Data = %02x %02x %02x %02x %02x %02x\n", - Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]); - mod_si598_writereg(dev, 7, Data[0]); - mod_si598_writereg(dev, 8, Data[1]); - mod_si598_writereg(dev, 9, Data[2]); - mod_si598_writereg(dev, 10, Data[3]); - mod_si598_writereg(dev, 11, Data[4]); - mod_si598_writereg(dev, 12, Data[5]); - - mod_si598_writereg(dev, 137, 0x00); - mod_si598_writereg(dev, 135, 0x40); - return 0; -} - - -static void mod_bypass_equalizer(struct ddb *dev, int bypass) -{ - u32 RegValue; - - RegValue = ddbreadl(dev, IQOUTPUT_CONTROL); - RegValue &= ~IQOUTPUT_CONTROL_BYPASS_EQUALIZER; - RegValue |= (bypass ? IQOUTPUT_CONTROL_BYPASS_EQUALIZER : 0x00); - ddbwritel(dev, RegValue, IQOUTPUT_CONTROL); -} - -static int mod_set_equalizer(struct ddb *dev, u32 Num, s16 *cTable) -{ - u32 i, adr = IQOUTPUT_EQUALIZER_0; - - if (Num > 11) - return -EINVAL; - - for (i = 0; i < 11 - Num; i += 1) { - ddbwritel(dev, 0, adr); - adr += 4; - } - for (i = 0; i < Num; i += 1) { - ddbwritel(dev, (u32) cTable[i], adr); - adr += 4; - } - return 0; -} - -static void mod_peak(struct ddb *dev, u32 Time, s16 *pIPeak, s16 *pQPeak) -{ - u32 val; - - val = ddbreadl(dev, IQOUTPUT_CONTROL); - val &= ~(IQOUTPUT_CONTROL_ENABLE_PEAK | IQOUTPUT_CONTROL_RESET_PEAK); - ddbwritel(dev, val, IQOUTPUT_CONTROL); - ddbwritel(dev, val | IQOUTPUT_CONTROL_RESET_PEAK, IQOUTPUT_CONTROL); - msleep(10); - ddbwritel(dev, val, IQOUTPUT_CONTROL); - ddbwritel(dev, val | IQOUTPUT_CONTROL_ENABLE_PEAK, IQOUTPUT_CONTROL); - msleep(Time); - ddbwritel(dev, val, IQOUTPUT_CONTROL); - val = ddbreadl(dev, IQOUTPUT_PEAK_DETECTOR); - - *pIPeak = val & 0xffff; - *pQPeak = (val >> 16) & 0xffff; -} - -static int mod_init_dac_input(struct ddb *dev) -{ - u8 Set = 0; - u8 Hld = 0; - u8 Sample = 0; - - u8 Seek = 0; - u8 ReadSeek = 0; - - u8 SetTable[32]; - u8 HldTable[32]; - u8 SeekTable[32]; - - u8 Sample1 = 0xFF; - u8 Sample2 = 0xFF; - - u8 SelectSample = 0xFF; - u8 DiffMin = 0xFF; - - for (Sample = 0; Sample < 32; Sample++ ) { - Set = 0; - Hld = 0; - - mod_write_dac_register(dev, 0x04, Set << 4 | Hld); - mod_write_dac_register(dev, 0x05, Sample); - mod_read_dac_register(dev, 0x06, &ReadSeek); - Seek = ReadSeek & 0x01; - SeekTable[Sample] = Seek; - - HldTable[Sample] = 15; - - for (Hld = 1; Hld < 16; Hld += 1) { - mod_write_dac_register(dev, 0x04, Set << 4 | Hld); - mod_read_dac_register(dev, 0x06, &ReadSeek); - - if ((ReadSeek & 0x01) != Seek) - { - HldTable[Sample] = Hld; - break; - } - } - - Hld = 0; - SetTable[Sample] = 15; - for (Set = 1; Set < 16; Set += 1) { - mod_write_dac_register(dev, 0x04, Set << 4 | Hld); - mod_read_dac_register(dev, 0x06, &ReadSeek); - - if( (ReadSeek & 0x01) != Seek ) { - SetTable[Sample] = Set; - break; - } - } - } - - Seek = 1; - for (Sample = 0; Sample < 32; Sample += 1 ) { - //printk(" %2d: %d %2d %2d\n", Sample,SeekTable[Sample],SetTable[Sample],HldTable[Sample]); - - if (Sample1 == 0xFF && SeekTable[Sample] == 1 && Seek == 0 ) - Sample1 = Sample; - if (Sample1 != 0xFF && Sample2 == 0xFF && SeekTable[Sample] == 0 && Seek == 1 ) - Sample2 = Sample; - Seek = SeekTable[Sample]; - } - - if (Sample1 == 0xFF || Sample2 == 0xFF ) { - printk(" No valid window found\n"); - return -EINVAL; - } - - printk(" Window = %d - %d\n", Sample1, Sample2); - - for (Sample = Sample1; Sample < Sample2; Sample += 1) { - if (SetTable[Sample] < HldTable[Sample]) { - if (HldTable[Sample] - SetTable[Sample] < DiffMin) { - DiffMin = HldTable[Sample] - SetTable[Sample]; - SelectSample = Sample; - } - } - } - - printk("Select Sample %d\n", SelectSample); - - if (SelectSample == 0xFF) { - printk("No valid sample found\n"); - return -EINVAL; - } - - if (HldTable[SelectSample] + SetTable[SelectSample] < 8 ) { - printk("Too high jitter\n"); - return -EINVAL; - } - - mod_write_dac_register(dev, 0x04, 0x00); - mod_write_dac_register(dev, 0x05, (SelectSample - 1) & 0x1F); - mod_read_dac_register(dev, 0x06, &Seek); - mod_write_dac_register(dev, 0x05, (SelectSample + 1) & 0x1F); - mod_read_dac_register(dev, 0x06,&ReadSeek); - Seek &= ReadSeek; - - mod_write_dac_register(dev, 0x05, SelectSample); - mod_read_dac_register(dev, 0x06, &ReadSeek); - Seek &= ReadSeek; - if( (Seek & 0x01) == 0 ) { - printk("Insufficient timing margin\n"); - return -EINVAL; - } - printk("Done\n"); - return 0; -} - -static void mod_set_up1(struct ddb *dev, u32 Frequency, u32 Ref, u32 Ext) -{ - u32 RDiv = Ext / Ref; - - Frequency = Frequency / Ref; - mod_set_up_converter_vco1(dev, 0x360001 | (RDiv << 2)); - mod_set_up_converter_vco1(dev, 0x0ff128); - mod_set_up_converter_vco1(dev, 0x02 | (Frequency << 8)); -} - -static void mod_set_up2(struct ddb *dev, u32 Frequency, u32 Ref, u32 Ext) -{ - u32 Rdiv = Ext / Ref; - u32 PreScale = 8; - - Frequency = Frequency / Ref; - mod_set_up_converter_vco2(dev, 0x360001 | (Rdiv << 2)); - mod_set_up_converter_vco2(dev, 0x0fc128 | (((PreScale - 8) / 8) << 22)); - mod_set_up_converter_vco2(dev, 0x02 | ((Frequency / PreScale) << 8) - | (Frequency & (PreScale - 1)) << 2); -} - -static int mod_set_down(struct ddb *dev, u32 Frequency, u32 Ref, u32 Ext) -{ - u32 BandSelect = Ref * 8; - u32 RefMul = 1; - u32 RefDiv2 = 1; - u32 RefDiv = Ext * RefMul / (Ref * RefDiv2); - - if (Frequency < 2200 || Frequency > 4000) - return -EINVAL; - - Frequency = Frequency / Ref; - - mod_set_down_converter_vco(dev, 0x0080003C | ((BandSelect & 0xFF) << 12)); - mod_set_down_converter_vco(dev, 0x00000003); - mod_set_down_converter_vco(dev, 0x18001E42 | ((RefMul-1) << 25) | - ((RefDiv2-1) << 24) | (RefDiv << 14) ); - mod_set_down_converter_vco(dev, 0x08008021); - mod_set_down_converter_vco(dev, Frequency << 15); - return 0; -} - -static int mod_set_dac_clock(struct ddb *dev, u32 Frequency) -{ - int hr, i; - - if (Frequency) { - ddbwritel(dev, DAC_CONTROL_RESET, DAC_CONTROL); - msleep(10); - if (mod_set_si598(dev, Frequency)) { - printk("mod_set_si598 failed\n"); - return -1; - } - msleep(50); - ddbwritel(dev, 0x000, DAC_CONTROL); - msleep(10); - mod_write_dac_register(dev, 0, 0x02); - } - - for (i = 0; i < 10; i++) { - hr = mod_init_dac_input(dev); - if (hr == 0) - break; - msleep(100); - } - printk("mod_set_dac_clock OK\n"); - return hr; -} - -static void mod_set_dac_current(struct ddb *dev, u32 Current1, u32 Current2) -{ - mod_write_dac_register2(dev, 0x0b, Current1 & 0x3ff); - mod_write_dac_register2(dev, 0x0f, Current2 & 0x3ff); -} - -static void mod_output_enable(struct ddb *dev, int enable) -{ - - u32 RegValue; - - RegValue = ddbreadl(dev, IQOUTPUT_CONTROL); - RegValue &= ~(IQOUTPUT_CONTROL_ENABLE | IQOUTPUT_CONTROL_RESET); - ddbwritel(dev, RegValue, IQOUTPUT_CONTROL); - - if (enable) { - ddbwritel(dev, RegValue | IQOUTPUT_CONTROL_RESET, IQOUTPUT_CONTROL); - msleep(10); - ddbwritel(dev, RegValue, IQOUTPUT_CONTROL); - ddbwritel(dev, RegValue | IQOUTPUT_CONTROL_ENABLE, IQOUTPUT_CONTROL); - } -} - -static int mod_set_iq(struct ddb *dev, u32 steps, u32 chan, u32 freq) -{ - u32 i, j, k, fac = 8; - u32 s1 = 22, s2 = 33; - u64 amp = (1ULL << 17) - 1ULL; - u64 s = 0, c = (amp << s1), ss; - u64 frq = 0xC90FDAA22168C234ULL; - u32 *iqtab; - u32 iqtabadr; - u32 volatile regval; - - iqtab = kmalloc((steps + 1) * 4, GFP_KERNEL); - if (!iqtab) - return -ENOMEM; - frq = div64_u64(frq, steps * fac) >> (61 - s2); - - /* create sine table */ - for (i = 0; i <= steps * fac / 4; i++) { - if (!(i & (fac - 1))) { - j = i / fac; - ss = s >> s1; - //ss = ((s >> (s1 - 1)) + 1) >> 1; - - iqtab[j] = iqtab[steps / 2 - j] = ss; - iqtab[steps / 2 + j] = iqtab[steps - j] = -ss; - } - c -= ((s * frq) >> s2); - s += ((c * frq) >> s2); - } - - iqtabadr = chan << 16; - ddbwritel(dev, chan & 0x0f, MODULATOR_IQTABLE_INDEX); - for (i = j = 0, k = steps / 4; i < steps; i++) { - ddbwritel(dev, (iqtabadr + i) | MODULATOR_IQTABLE_INDEX_SEL_I, - MODULATOR_IQTABLE_INDEX); - ddbwritel(dev, iqtab[j], MODULATOR_IQTABLE_DATA); - regval = ddbreadl(dev, MODULATOR_CONTROL); - ddbwritel(dev, (iqtabadr + i) | MODULATOR_IQTABLE_INDEX_SEL_Q, - MODULATOR_IQTABLE_INDEX); - ddbwritel(dev, iqtab[k], MODULATOR_IQTABLE_DATA); - regval = ddbreadl(dev, MODULATOR_CONTROL); - j += freq; - j %= steps; - k += freq; - k %= steps; - } - ddbwritel(dev, steps - 1, MODULATOR_IQTABLE_END); - kfree(iqtab); - return 0; -} - -u32 eqtab[] = { - 0x0000FFDB, 0x00000121, 0x0000FF0A, 0x000003D7, - 0x000001C4, 0x000005A5, 0x000009CC, 0x0000F50D, - 0x00001B23, 0x0000EEB7, 0x00006A28 -}; - -static int mod_set_modulation(struct ddb *dev, int chan, int mod) -{ - static u32 setting[5] = { 0x600, 0x601, 0x602, 0x903, 0x604 }; - - if (mod > 4) - return -EINVAL; - ddbwritel(dev, setting[mod] , CHANNEL_SETTINGS(chan)); - return 0; -} - -static void mod_set_rateinc(struct ddb *dev, u32 chan, u32 inc) -{ - dev->mod[chan].rate_inc = inc; - ddbwritel(dev, inc, CHANNEL_RATE_INCR(chan)); - mod_busy(dev, chan); -} - -static void mod_set_channelsumshift(struct ddb *dev, u32 shift) -{ - ddbwritel(dev, (shift & 3) << 2, MODULATOR_CONTROL); -} - -static void mod_pre_eq_gain(struct ddb *dev, u16 gain) -{ - ddbwritel(dev, gain, IQOUTPUT_PRESCALER); -} - -static void mod_post_eq_gain(struct ddb *dev, u16 igain, u16 qgain) -{ - ddbwritel(dev, ((u32)qgain << 16) | igain, IQOUTPUT_POSTSCALER); -} - -static int set_base_frequency(struct ddb *dev, u32 freq) -{ - u32 Ext = 40; - u32 UP1Frequency = 290; - u32 UP2Frequency = 1896; - u32 down, freq10; - - printk("set base to %u\n", freq); - dev->mod_base.frequency = freq; - freq /= 1000000; - freq10 = dev->mod_base.flat_start + 4; - down = freq + 9 * 8 + freq10 + UP1Frequency + UP2Frequency; - - if ((freq10 + 9 * 8) > (dev->mod_base.flat_end - 4)) { - printk("Frequency out of range %d\n", freq10); - return -EINVAL; - } - if (down % 8) { - printk(" Invalid Frequency %d\n", down); - return -EINVAL; - } - return mod_set_down(dev, down, 8, Ext); -} - -static int mod_init(struct ddb *dev, u32 Frequency) -{ - int stat = 0; - u8 *buffer; - struct DDMOD_FLASH *flash; - u32 Ext = 40; - u32 UP1Frequency = 290; - u32 UP2Frequency = 1896; - u32 DownFrequency; - u32 FrequencyCH10; - u32 iqfreq, iqsteps, i; - - buffer = kmalloc(4096, GFP_KERNEL); - if (!buffer) - return -ENOMEM; - flash = (struct DDMOD_FLASH *) buffer; - - ddbridge_flashread(dev, buffer, DDMOD_FLASH_START, 4096); - - if (flash->Magic != DDMOD_FLASH_MAGIC && flash->Magic != 1) { - stat = -EINVAL; - goto fail; - } - printk("srate = %d\n", flash->DataSet[0].Symbolrate * 1000); - - mod_output_enable(dev, 0); - stat = mod_set_dac_clock(dev, flash->DataSet[0].DACFrequency * 1000); - if (stat < 0) { - printk("setting DAC clock failed\n"); - goto fail; - } - mod_set_dac_current(dev, 512, 512); - - ddbwritel(dev, flash->DataSet[0].Control2, IQOUTPUT_CONTROL2); - - mod_set_up1(dev, UP1Frequency, 5, Ext); - mod_set_up2(dev, UP2Frequency, 8, Ext); - - dev->mod_base.flat_start = flash->DataSet[0].FlatStart; - dev->mod_base.flat_end = flash->DataSet[0].FlatEnd; - - Frequency /= 1000000; - FrequencyCH10 = flash->DataSet[0].FlatStart + 4; - DownFrequency = Frequency + 9 * 8 + FrequencyCH10 + UP1Frequency + UP2Frequency; - printk("CH10 = %d, Down = %d\n", FrequencyCH10, DownFrequency); - - - if ((FrequencyCH10 + 9 * 8) > (flash->DataSet[0].FlatEnd - 4)) { - printk("Frequency out of range %d\n", FrequencyCH10); - stat = -EINVAL; - goto fail; - } - - if (DownFrequency % 8 != 0 ) { - printk(" Invalid Frequency %d\n", DownFrequency); - stat = -EINVAL; - goto fail; - } - - mod_set_down(dev, DownFrequency, 8, Ext); - - for (i = 0; i < 10; i++) { - ddbwritel(dev, 0, CHANNEL_CONTROL(i)); - - iqfreq = flash->DataSet[0].FrequencyFactor * (FrequencyCH10 + (9 - i) * 8); - iqsteps = flash->DataSet[0].IQTableLength; - mod_set_iq(dev, iqsteps, i, iqfreq); - - dev->mod[i].modulation = QAM_256; - } - - mod_bypass_equalizer(dev, 1); - mod_set_equalizer(dev, 11, flash->DataSet[0].EQTap); - mod_bypass_equalizer(dev, 0); - mod_post_eq_gain(dev, flash->DataSet[0].PostScaleI, flash->DataSet[0].PostScaleQ); - mod_pre_eq_gain(dev, flash->DataSet[0].PreScale); - //mod_pre_eq_gain(dev, 0x0680); - printk("prescaler %04x\n", flash->DataSet[0].PreScale); - mod_set_channelsumshift(dev, 2); - mod_output_enable(dev, 1); - - //mod_set_attenuator(dev, 10); -fail: - kfree(buffer); - return stat; -} - - -void ddbridge_mod_rate_handler(unsigned long data) -{ - struct ddb_output *output = (struct ddb_output *) data; - struct ddb_dma *dma = output->dma; - struct ddb *dev = output->port->dev; - struct mod_state *mod= &dev->mod[output->nr]; - - u32 chan = output->nr; - u32 OutPacketCount; - u32 InPacketCount; - u64 OutPackets, InPackets; - s64 PCRAdjust; - u32 PCRAdjustExt, PCRAdjustExtFrac, InPacketDiff, OutPacketDiff; - s32 PCRCorr; - - s64 pcr; - s64 PCRIncrementDiff; - s64 PCRIncrement; - u64 mul; - - if (!mod->do_handle) - return; - printk("rate_handler\n"); - - spin_lock(&dma->lock); - ddbwritel(dev, mod->Control | CHANNEL_CONTROL_FREEZE_STATUS, - CHANNEL_CONTROL(output->nr)); - - OutPacketCount = ddbreadl(dev, CHANNEL_PKT_COUNT_OUT(chan)); - if (OutPacketCount < mod->LastOutPacketCount ) - mod->OutOverflowPacketCount += 1; - mod->LastOutPacketCount = OutPacketCount; - - InPacketCount = ddbreadl(dev, CHANNEL_PKT_COUNT_IN(chan)); - if (InPacketCount < mod->LastInPacketCount ) - mod->InOverflowPacketCount += 1; - mod->LastInPacketCount = InPacketCount; - - OutPackets = ((u64) (mod->OutOverflowPacketCount) << 20) | OutPacketCount; - InPackets = ((u64) (mod->InOverflowPacketCount) << 20) | InPacketCount; - - PCRAdjust = (s64) ((u64) ddbreadl(dev, CHANNEL_PCR_ADJUST_ACCUL(chan)) | - (((u64) ddbreadl(dev, CHANNEL_PCR_ADJUST_ACCUH(chan)) << 32))); - PCRAdjustExt = (u32)((PCRAdjust & 0x7FFFFFFF) >> 22); - PCRAdjustExtFrac = (u32)((PCRAdjust & 0x003FFFFF) >> 12); - PCRAdjust >>= 31; - InPacketDiff = (u32) (InPackets - mod->LastInPackets); - OutPacketDiff = (u32) (OutPackets - mod->LastOutPackets); - PCRCorr = 0; - - switch (mod->State) { - case CM_STARTUP: - if (mod->StateCounter) { - if (mod->StateCounter == 1) { - mul = (0x1000000 * (u64) (OutPacketDiff - InPacketDiff - InPacketDiff/1000)); - if (OutPacketDiff) - mod->rate_inc = div_u64(mul, OutPacketDiff); - else - mod->rate_inc = 0; - printk("RI %08x\n", mod->rate_inc); - ddbwritel(dev, mod->rate_inc, CHANNEL_RATE_INCR(output->nr)); - mod_busy(dev, output->nr); -//#define PACKET_CLOCKS (27000000ULL*1504) -//#define FACTOR (1024<<12) -//double Increment = FACTOR*PACKET_CLOCKS/double(m_OutputBitrate); -//double Decrement = FACTOR*PACKET_CLOCKS/double(m_InputBitrate); - mod->PCRIncrement = 3348148758ULL; - if (InPacketDiff) - mod->PCRDecrement = div_u64(3348148758ULL * (u64) OutPacketDiff, - InPacketDiff); - else - mod->PCRDecrement = 0; - mod_set_incs(output); - } - mod->StateCounter--; - break; - } - if (InPacketDiff >= mod->MinInputPackets) { - mod->State = CM_ADJUST; - mod->Control |= CHANNEL_CONTROL_ENABLE_PCRADJUST; - mod->InPacketsSum = 0; - mod->OutPacketsSum = 0; - mod->PCRAdjustSum = 0; - mod->StateCounter = CM_AVERAGE; - } - break; - - case CM_ADJUST: - if (InPacketDiff < mod->MinInputPackets) { - printk("PCR Adjust reset IN: %u Min: %u\n", - InPacketDiff, mod->MinInputPackets); - mod->InPacketsSum = 0; - mod->OutPacketsSum = 0; - mod->PCRAdjustSum = 0; - mod->StateCounter = CM_AVERAGE; - ddbwritel(dev, - (mod->Control | CHANNEL_CONTROL_FREEZE_STATUS) & - ~CHANNEL_CONTROL_ENABLE_PCRADJUST, - CHANNEL_CONTROL(chan)); - break; - } - - mod->PCRAdjustSum += (s32) PCRAdjust; - mod->InPacketsSum += InPacketDiff; - mod->OutPacketsSum += OutPacketDiff; - if (mod->StateCounter--) - break; - - if (mod->OutPacketsSum) - PCRIncrement = div_s64((s64)mod->InPacketsSum * - (s64)mod->PCRDecrement + - (s64)(mod->OutPacketsSum >> 1) , - mod->OutPacketsSum); - else - PCRIncrement = 0; - - if( mod->PCRAdjustSum > 0 ) - PCRIncrement = RoundPCRDown(PCRIncrement); - else - PCRIncrement = RoundPCRUp(PCRIncrement); - - PCRIncrementDiff = PCRIncrement - mod->PCRIncrement; - if( PCRIncrementDiff > HW_LSB_MASK ) - PCRIncrementDiff = HW_LSB_MASK; - if( PCRIncrementDiff < -HW_LSB_MASK ) - PCRIncrementDiff = -HW_LSB_MASK; - - mod->PCRIncrement += PCRIncrementDiff; - pcr = ConvertPCR(mod->PCRIncrement); - printk("outl %016llx\n", pcr); - ddbwritel(dev, pcr & 0xffffffff, - CHANNEL_PCR_ADJUST_OUTL(output->nr)); - ddbwritel(dev, (pcr >> 32) & 0xffffffff, - CHANNEL_PCR_ADJUST_OUTH(output->nr)); - mod_busy(dev, chan); - - PCRCorr = (s32) (PCRIncrementDiff >> HW_LSB_SHIFT); - mod->PCRRunningCorr += PCRCorr; - - mod->InPacketsSum = 0; - mod->OutPacketsSum = 0; - mod->PCRAdjustSum = 0; - mod->StateCounter = CM_AVERAGE; - break; - - default: - break; - } - ddbwritel(dev, mod->Control, CHANNEL_CONTROL(chan)); - - mod->LastInPackets = InPackets; - mod->LastOutPackets = OutPackets; - mod->LastPCRAdjust = (s32) PCRAdjust; - - printk("chan %d out %016llx in %016llx indiff %08x\n", chan, OutPackets, InPackets, InPacketDiff); - printk("cnt %d pcra %016llx pcraext %08x pcraextfrac %08x pcrcorr %08x pcri %016llx\n", - mod->StateCounter, PCRAdjust, PCRAdjustExt, PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement); - //Channel,OutPackets,InPackets,InPacketDiff,PCRAdjust,PCRAdjustExt,PCRAdjustExtFrac,PCRCorr, mod->PCRRunningCorr,mod->StateCounter )); - spin_unlock(&dma->lock); -} - -int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct ddb_output *output = dvbdev->priv; - struct ddb *dev = output->port->dev; - - //unsigned long arg = (unsigned long) parg; - int ret = 0; - - switch (cmd) { - case DVB_MOD_SET: - { - struct dvb_mod_params *mp = parg; - - if (mp->base_frequency != dev->mod_base.frequency) - if (set_base_frequency(dev, mp->base_frequency)) - return -EINVAL; - mod_set_attenuator(dev, mp->attenuator); - break; - } - case DVB_MOD_CHANNEL_SET: - { - struct dvb_mod_channel_params *cp = parg; - - if (cp->modulation > QAM_256) - return -EINVAL; - dev->mod[output->nr].modulation = cp->modulation; - dev->mod[output->nr].rate_inc = cp->rate_increment; - ddbwritel(dev, dev->mod[output->nr].rate_inc, CHANNEL_RATE_INCR(output->nr)); - break; - } - default: - ret = -EINVAL; - break; - } - return ret; -} - -int ddbridge_mod_init(struct ddb *dev) -{ - return mod_init(dev, 722000000); -} - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-ns.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-ns.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-ns.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-ns.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,465 +0,0 @@ -static int ddb_dvb_input_start(struct ddb_input *input); -static int ddb_dvb_input_stop(struct ddb_input *input); - -static u16 calc_pcs(struct dvb_ns_params *p) -{ - u32 sum = 0; - u16 pcs; - - sum += (p->sip[0] << 8) | p->sip[1]; - sum += (p->sip[2] << 8) | p->sip[3]; - sum += (p->dip[0] << 8) | p->dip[1]; - sum += (p->dip[2] << 8) | p->dip[3]; - sum += 0x11; /* UDP proto */ - sum = (sum >> 16) + (sum & 0xffff); - pcs = sum; - //printk("PCS = %04x\n", pcs); - return pcs; -} - -static u16 calc_pcs16(struct dvb_ns_params *p, int ipv) -{ - u32 sum = 0, i; - u16 pcs; - - for (i = 0; i < ipv ? 16 : 4; i += 2) { - sum += (p->sip[i] << 8) | p->sip[i + 1]; - sum += (p->dip[i] << 8) | p->dip[i + 1]; - } - sum += 0x11; /* UDP proto */ - sum = (sum >> 16) + (sum & 0xffff); - pcs = sum; - return pcs; -} - -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ - -static void ns_free(struct dvbnss *nss) -{ - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - - mutex_lock(&dev->mutex); - dns->input = 0; - mutex_unlock(&dev->mutex); -} - -static int ns_alloc(struct dvbnss *nss) -{ - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - int i, ret = -EBUSY; - - mutex_lock(&dev->mutex); - for (i = 0; i < dev->ns_num; i++) { - if (dev->ns[i].input) - continue; - dev->ns[i].input = input; - dev->ns[i].fe = input->nr; - nss->priv = &dev->ns[i]; - ret = 0; - //printk("%s i=%d fe=%d\n", __func__, i, input->nr); - break; - } - ddbwritel(dev, 0x03, RTP_MASTER_CONTROL); - mutex_unlock(&dev->mutex); - return ret; -} - -static int ns_set_pids(struct dvbnss *nss) -{ - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - - //printk("ns_set_pids %02x %02x\n", nss->pids[0], nss->pids[1]); - if (dev->devid == 0x0301dd01) { - u32 sys = 0; - int pid, j = 1; - - sys |= nss->pids[0] & 3; - sys |= (nss->pids[2] & 0x1f) << 4; - ddbwritel(dev, sys, PID_FILTER_SYSTEM_PIDS(dns->nr)); - for (pid = 20; j < 5 && pid < 8192; pid++) - if (nss->pids[pid >> 3] & (1 << (pid & 7))) { - ddbwritel(dev, 0x8000 | pid, PID_FILTER_PID(dns->nr, j)); - j++; - } - /* disable unused pids */ - for (; j < 5; j++) - ddbwritel(dev, 0, PID_FILTER_PID(dns->nr, j)); - } else - ddbcpyto(dev, STREAM_PIDS(dns->nr), nss->pids, 0x400); - return 0; -} - -static int ns_set_pid(struct dvbnss *nss, u16 pid) -{ - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - u16 byte = (pid & 0x1fff) >> 3; - u8 bit = 1 << (pid & 7); - u32 off = STREAM_PIDS(dns->nr); - -#if 1 - if (dev->devid == 0x0301dd01) { - if (pid & 0x2000) { - if (pid & 0x8000) - memset(nss->pids, 0xff, 0x400); - else - memset(nss->pids, 0x00, 0x400); - } else { - if (pid & 0x8000) - nss->pids[byte] |= bit; - else - nss->pids[byte] &= ~bit; - } - ns_set_pids(nss); - } else { - if (pid & 0x2000) { - if (pid & 0x8000) - ddbmemset(dev, off, 0xff, 0x400); - else - ddbmemset(dev, off, 0x00, 0x400); - } else { - u8 val = ddbreadb(dev, off + byte); - if (pid & 0x8000) - ddbwriteb(dev, val | bit, off + byte); - else - ddbwriteb(dev, val & ~bit, off + byte); - } - } -#else - ddbcpyto(dev, STREAM_PIDS(dns->nr), nss->pids, 0x400); -#endif - return 0; -} - -static int citoport(struct ddb *dev, u8 ci) -{ - int i, j; - struct ddb_input *input; - - for (i = j = 0; i < dev->info->port_num; i++) { - if (dev->port[i].class == DDB_PORT_CI) { - if (j == ci) - return i; - j++; - } - } - return -1; -} - -static int ns_set_ci(struct dvbnss *nss, u8 ci) -{ - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - int ciport; - - if (ci == 255) { - dns->fe = input->nr; - return 0; - } - ciport = citoport(dev, ci); - if (ciport < 0) - return -EINVAL; - printk("input %d to ci %d at port %d\n", input->nr, ci, ciport); - ddbwritel(dev, (input->nr << 16) | 0x1c, TS_OUTPUT_CONTROL(ciport)); - usleep_range(1, 5); - ddbwritel(dev, (input->nr << 16) | 0x1d, TS_OUTPUT_CONTROL(ciport)); - dns->fe = ciport * 2; - return 0; -} - -static u8 rtp_head[] = { - 0x80, 0x21, - 0x00, 0x00, /* seq number */ - 0x00, 0x00, 0x00, 0x00, /* time stamp*/ - 0x91, 0x82, 0x73, 0x64, /* SSRC */ -}; - -static u8 rtcp_head[] = { - /* SR off 42:8 len 28*/ - 0x80, 0xc8, /* SR type */ - 0x00, 0x06, /* len */ - 0x91, 0x82, 0x73, 0x64, /* SSRC */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* NTP */ - 0x73, 0x64, 0x00, 0x00, /* RTP TS */ - 0x00, 0x00, 0x00, 0x00, /* packet count */ - 0x00, 0x00, 0x00, 0x00, /* octet count */ - /* SDES off 70:36 len 20 */ - 0x81, 0xca, /* SDES */ - 0x00, 0x03, /* len */ - 0x91, 0x82, 0x73, 0x64, /* SSRC */ - 0x01, 0x05, /* CNAME item */ - 0x53, 0x41, 0x54, 0x49, 0x50, /* "SATIP" */ - 0x00, /* item type 0 */ - /* APP off 86:52 len 16+string length */ - 0x80, 0xcc, /* APP */ - 0x00, 0x04, /* len */ - 0x91, 0x82, 0x73, 0x64, /* SSRC */ - 0x53, 0x45, 0x53, 0x31, /* "SES1" */ - 0x00, 0x00, /* identifier */ - 0x00, 0x00, /* string length */ - /* string off 102:68 */ -}; - -static int ns_set_rtcp_msg(struct dvbnss *nss, u8 *msg, u32 len) -{ - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - u32 off = STREAM_PACKET_ADR(dns->nr); - u32 coff = 96; - u16 wlen; - - //printk("%s len=%d\n", __func__, len); - - if (!len) { - ddbwritel(dev, ddbreadl(dev, STREAM_CONTROL(dns->nr)) & ~0x10, - STREAM_CONTROL(dns->nr)); - return 0; - } - if (copy_from_user(dns->p + coff + dns->rtcp_len, msg, len)) - return -EFAULT; - dns->p[coff + dns->rtcp_len - 2] = (len >> 8); - dns->p[coff + dns->rtcp_len - 1] = (len & 0xff); - if (len & 3) { - u32 pad = 4 - (len & 3); - memset(dns->p + coff + dns->rtcp_len + len, 0, pad); - len += pad; - } - wlen = len / 4; - wlen += 3; - dns->p[coff + dns->rtcp_len - 14] = (wlen >> 8); - dns->p[coff + dns->rtcp_len - 13] = (wlen & 0xff); - ddbcpyto(dev, off, dns->p, sizeof(dns->p)); - ddbwritel(dev, (dns->rtcp_udplen + len) | ((STREAM_PACKET_OFF(dns->nr) + coff) << 16), - STREAM_RTCP_PACKET(dns->nr)); - ddbwritel(dev, ddbreadl(dev, STREAM_CONTROL(dns->nr)) | 0x10, - STREAM_CONTROL(dns->nr)); - return 0; -} - -static u32 set_nsbuf(struct dvb_ns_params *p, u8 *buf, u32 *udplen, int rtcp) -{ - u32 c = 0; - u16 pcs; - u16 sport, dport; - - sport = rtcp ? p->sport2 : p->sport; - dport = rtcp ? p->dport2 : p->dport; - - /* MAC header */ - memcpy(buf + c, p->dmac, 6); - memcpy(buf + c + 6, p->smac, 6); - c += 12; - if (vlan) { - buf[c + 0] = 0x81; - buf[c + 1] = 0x00; - buf[c + 2] = ((p->qos & 7) << 5) | ((p->vlan & 0xf00) >> 8) ; - buf[c + 3] = p->vlan & 0xff; - c += 4; - } - buf[c + 0] = 0x08; - buf[c + 1] = 0x00; - c += 2; - - /* IP header */ - if (p->flags & DVB_NS_IPV6) { - u8 ip6head[8] = { 0x65, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x11, 0x00, }; - memcpy(buf + c, ip6head, sizeof(ip6head)); - buf[c + 7] = p->ttl; - memcpy(buf + c + 8, p->sip, 16); - memcpy(buf + c + 24, p->dip, 16); - c += 40; - - /* UDP */ - buf[c + 0] = sport >> 8; - buf[c + 1] = sport & 0xff; - buf[c + 2] = dport >> 8; - buf[c + 3] = dport & 0xff; - buf[c + 4] = 0; /* length */ - buf[c + 5] = 0; - pcs = calc_pcs16(p, p->flags & DVB_NS_IPV6); - buf[c + 6] = pcs >> 8; - buf[c + 7] = pcs & 0xff; - c += 8; - *udplen = 8; - - } else { - u8 ip4head[12] = { 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x40, 0x00, 0x40, 0x11, 0x00, 0x00 }; - - memcpy(buf + c, ip4head, sizeof(ip4head)); - buf[c + 8] = p->ttl; - memcpy(buf + c + 12, p->sip, 4); - memcpy(buf + c + 16, p->dip, 4); - c += 20; - - /* UDP */ - buf[c + 0] = sport >> 8; - buf[c + 1] = sport & 0xff; - buf[c + 2] = dport >> 8; - buf[c + 3] = dport & 0xff; - buf[c + 4] = 0; /* length */ - buf[c + 5] = 0; - pcs = calc_pcs(p); - buf[c + 6] = pcs >> 8; - buf[c + 7] = pcs & 0xff; - c += 8; - *udplen = 8; - } - - if (rtcp) { - memcpy(buf + c, rtcp_head, sizeof(rtcp_head)); - memcpy(buf + c + 4, p->ssrc, 4); - memcpy(buf + c + 32, p->ssrc, 4); - memcpy(buf + c + 48, p->ssrc, 4); - c += sizeof(rtcp_head); - *udplen += sizeof(rtcp_head); - } else if (p->flags & DVB_NS_RTP) { - memcpy(buf + c, rtp_head, sizeof(rtp_head)); - memcpy(buf + c + 8, p->ssrc, 4); - c += sizeof(rtp_head); - *udplen += sizeof(rtp_head); - } - return c; -} - -static int ns_set_ts_packets(struct dvbnss *nss, u8 *buf, u32 len) -{ - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - u32 off = STREAM_PACKET_ADR(dns->nr); - - if (nss->params.flags & DVB_NS_RTCP) - return -EINVAL; - - if (copy_from_user(dns->p + dns->ts_offset, buf, len)) - return -EFAULT; - ddbcpyto(dev, off, dns->p, sizeof(dns->p)); - return 0; -} - -static int ns_insert_ts_packets(struct dvbnss *nss, u8 count) -{ - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - u32 value = count; - - if (nss->params.flags & DVB_NS_RTCP) - return -EINVAL; - - if (count < 1 || count > 2) - return -EINVAL; - - ddbwritel(dev, value, STREAM_INSERT_PACKET(dns->nr)); - return 0; -} - -static int ns_set_net(struct dvbnss *nss) -{ - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - struct dvb_ns_params *p = &nss->params; - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - u32 off = STREAM_PACKET_ADR(dns->nr); - u32 coff = 96; - - dns->ts_offset = set_nsbuf(p, dns->p, &dns->udplen, 0); - if (nss->params.flags & DVB_NS_RTCP) - dns->rtcp_len = set_nsbuf(p, dns->p + coff, &dns->rtcp_udplen, 1); - ddbcpyto(dev, off, dns->p, sizeof(dns->p)); - ddbwritel(dev, dns->udplen | (STREAM_PACKET_OFF(dns->nr) << 16), - STREAM_RTP_PACKET(dns->nr)); - ddbwritel(dev, dns->rtcp_udplen | ((STREAM_PACKET_OFF(dns->nr) + coff) << 16), - STREAM_RTCP_PACKET(dns->nr)); - return 0; -} - -static int ns_start(struct dvbnss *nss) -{ - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - u32 reg = 0x8003; - - - if (nss->params.flags & DVB_NS_RTCP) - reg |= 0x10; - if (nss->params.flags & DVB_NS_RTP_TO) - reg |= 0x20; - if (nss->params.flags & DVB_NS_RTP) - reg |= 0x40; - if (nss->params.flags & DVB_NS_IPV6) - reg |= 0x80; - if (dns->fe != input->nr) - ddb_dvb_input_start(&dev->input[dns->fe]); - ddb_dvb_input_start(input); - ddbwritel(dev, reg | (dns->fe << 8), STREAM_CONTROL(dns->nr)); - return 0; -} - -static int ns_stop(struct dvbnss *nss) -{ - struct ddb_ns *dns = (struct ddb_ns *) nss->priv; - struct dvb_netstream *ns = nss->ns; - struct ddb_input *input = ns->priv; - struct ddb *dev = input->port->dev; - - ddbwritel(dev, 0x00, STREAM_CONTROL(dns->nr)); - ddb_dvb_input_stop(input); - if (dns->fe != input->nr) - ddb_dvb_input_stop(&dev->input[dns->fe]); - return 0; -} - -static int netstream_init(struct ddb_input *input) -{ - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_adapter *adap = dvb->adap; - struct dvb_netstream *ns = &dvb->dvbns; - struct ddb *dev = input->port->dev; - int i, res; - - ddbmemset(dev, STREAM_PIDS(input->nr), 0x00, 0x400); - if (dev->devid == 0x0301dd01) - dev->ns_num = 15; - else - dev->ns_num = 12; - for (i = 0; i < dev->ns_num; i++) - dev->ns[i].nr = i; - ns->priv = input; - ns->set_net = ns_set_net; - ns->set_rtcp_msg = ns_set_rtcp_msg; - ns->set_ts_packets = ns_set_ts_packets; - ns->insert_ts_packets = ns_insert_ts_packets; - ns->set_pid = ns_set_pid; - ns->set_pids = ns_set_pids; - ns->set_ci = ns_set_ci; - ns->start = ns_start; - ns->stop = ns_stop; - ns->alloc = ns_alloc; - ns->free = ns_free; - res = dvb_netstream_init(adap, ns); - return res; -} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-regs.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-regs.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-regs.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge-regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,399 +0,0 @@ -/* - * ddbridge-regs.h: Digital Devices PCIe bridge driver - * - * Copyright (C) 2010-2013 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -/* Register Definitions */ - -#define CUR_REGISTERMAP_VERSION 0x10003 -#define CUR_REGISTERMAP_VERSION_CI 0x10000 -#define CUR_REGISTERMAP_VERSION_MOD 0x10000 - -#define HARDWARE_VERSION 0x00 -#define REGISTERMAP_VERSION 0x04 - -/* ------------------------------------------------------------------------- */ -/* SPI Controller */ - -#define SPI_CONTROL 0x10 -#define SPI_DATA 0x14 - -/* ------------------------------------------------------------------------- */ -/* GPIO */ - -#define GPIO_OUTPUT 0x20 -#define GPIO_INPUT 0x24 -#define GPIO_DIRECTION 0x28 - -/* ------------------------------------------------------------------------- */ -/* MDIO */ - -#define MDIO_CTRL 0x20 -#define MDIO_ADR 0x24 -#define MDIO_REG 0x28 -#define MDIO_VAL 0x2C - -/* ------------------------------------------------------------------------- */ - -/* Interrupt controller -// How many MSI's are available depends on HW (Min 2 max 8) -// How many are usable also depends on Host platform -*/ - -#define INTERRUPT_BASE (0x40) - -#define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) -#define MSI0_ENABLE (INTERRUPT_BASE + 0x00) -#define MSI1_ENABLE (INTERRUPT_BASE + 0x04) -#define MSI2_ENABLE (INTERRUPT_BASE + 0x08) -#define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) -#define MSI4_ENABLE (INTERRUPT_BASE + 0x10) -#define MSI5_ENABLE (INTERRUPT_BASE + 0x14) -#define MSI6_ENABLE (INTERRUPT_BASE + 0x18) -#define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) - -#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) -#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) - -#define INTMASK_CLOCKGEN (0x00000001) -#define INTMASK_TEMPMON (0x00000002) - -#define INTMASK_I2C1 (0x00000001) -#define INTMASK_I2C2 (0x00000002) -#define INTMASK_I2C3 (0x00000004) -#define INTMASK_I2C4 (0x00000008) - -#define INTMASK_CIRQ1 (0x00000010) -#define INTMASK_CIRQ2 (0x00000020) -#define INTMASK_CIRQ3 (0x00000040) -#define INTMASK_CIRQ4 (0x00000080) - -#define INTMASK_TSINPUT1 (0x00000100) -#define INTMASK_TSINPUT2 (0x00000200) -#define INTMASK_TSINPUT3 (0x00000400) -#define INTMASK_TSINPUT4 (0x00000800) -#define INTMASK_TSINPUT5 (0x00001000) -#define INTMASK_TSINPUT6 (0x00002000) -#define INTMASK_TSINPUT7 (0x00004000) -#define INTMASK_TSINPUT8 (0x00008000) - -#define INTMASK_TSOUTPUT1 (0x00010000) -#define INTMASK_TSOUTPUT2 (0x00020000) -#define INTMASK_TSOUTPUT3 (0x00040000) -#define INTMASK_TSOUTPUT4 (0x00080000) - - -// Clock Generator ( Sil598 @ 0xAA I2c ) -#define CLOCKGEN_BASE (0x80) -#define CLOCKGEN_CONTROL (CLOCKGEN_BASE + 0x00) -#define CLOCKGEN_INDEX (CLOCKGEN_BASE + 0x04) -#define CLOCKGEN_WRITEDATA (CLOCKGEN_BASE + 0x08) -#define CLOCKGEN_READDATA (CLOCKGEN_BASE + 0x0C) - -// DAC ( AD9781/AD9783 SPI ) -#define DAC_BASE (0x090) -#define DAC_CONTROL (DAC_BASE) -#define DAC_WRITE_DATA (DAC_BASE+4) -#define DAC_READ_DATA (DAC_BASE+8) - -#define DAC_CONTROL_INSTRUCTION_REG (0xFF) -#define DAC_CONTROL_STARTIO (0x100) -#define DAC_CONTROL_RESET (0x200) - -// Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) -#define TEMPMON_BASE (0xA0) -#define TEMPMON_CONTROL (TEMPMON_BASE + 0x00) -#define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08) // SHORT Temperature in °C x 256 -#define TEMPMON_SENSOR2 (TEMPMON_BASE + 0x0C) // SHORT Temperature in °C x 256 - -// -// -------------------------------------------------------------------------- - - -/* ------------------------------------------------------------------------- */ -/* I2C Master Controller */ - -#define I2C_BASE (0x80) /* Byte offset */ - -#define I2C_COMMAND (0x00) -#define I2C_TIMING (0x04) -#define I2C_TASKLENGTH (0x08) /* High read, low write */ -#define I2C_TASKADDRESS (0x0C) /* High read, low write */ -#define I2C_MONITOR (0x1C) - -#define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) - -#define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ -#define I2C_TASKMEM_SIZE (0x0800) - -#define I2C_SPEED_400 (0x04030404) -#define I2C_SPEED_200 (0x09080909) -#define I2C_SPEED_154 (0x0C0B0C0C) -#define I2C_SPEED_100 (0x13121313) -#define I2C_SPEED_77 (0x19181919) -#define I2C_SPEED_50 (0x27262727) - - -/* ------------------------------------------------------------------------- */ -/* DMA Controller */ - -#define DMA_BASE_WRITE (0x100) -#define DMA_BASE_READ (0x140) - -#define DMA_CONTROL (0x00) -#define DMA_ERROR (0x04) - -#define DMA_DIAG_CONTROL (0x1C) -#define DMA_DIAG_PACKETCOUNTER_LOW (0x20) -#define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) -#define DMA_DIAG_TIMECOUNTER_LOW (0x28) -#define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) -#define DMA_DIAG_RECHECKCOUNTER (0x30) -#define DMA_DIAG_WAITTIMEOUTINIT (0x34) -#define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) -#define DMA_DIAG_WAITCOUNTER (0x3C) - -/* ------------------------------------------------------------------------- */ -/* DMA Buffer */ - -#define TS_INPUT_BASE (0x200) -#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 0x10 + 0x00) -#define TS_INPUT_CONTROL2(i) (TS_INPUT_BASE + (i) * 0x10 + 0x04) - -#define TS_OUTPUT_BASE (0x280) -#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x00) -#define TS_OUTPUT_CONTROL2(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x04) - -#define DMA_BUFFER_BASE (0x300) - -#define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x00) -#define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x04) -#define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x08) -#define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x0c) - -#define DMA_BASE_ADDRESS_TABLE (0x2000) -#define DMA_BASE_ADDRESS_TABLE_ENTRIES (512) - -/* ------------------------------------------------------------------------- */ -/* CI Interface (only CI-Bridge) */ - -#define CI_BASE (0x400) -#define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00) - -#define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04) -#define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08) -#define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c) -#define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10) - -#define CI_RESET_CAM (0x00000001) -#define CI_POWER_ON (0x00000002) -#define CI_ENABLE (0x00000004) -#define CI_BLOCKIO_ENABLE (0x00000008) -#define CI_BYPASS_DISABLE (0x00000010) -#define CI_DISABLE_AUTO_OFF (0x00000020) - -#define CI_CAM_READY (0x00010000) -#define CI_CAM_DETECT (0x00020000) -#define CI_READY (0x80000000) -#define CI_BLOCKIO_ACTIVE (0x40000000) -#define CI_BLOCKIO_RCVDATA (0x20000000) -#define CI_BLOCKIO_SEND_PENDING (0x10000000) -#define CI_BLOCKIO_SEND_COMPLETE (0x08000000) - -#define CI_READ_CMD (0x40000000) -#define CI_WRITE_CMD (0x80000000) - -#define CI_BLOCKIO_SEND(i) (CI_BASE + (i) * 32 + 0x14) -#define CI_BLOCKIO_RECEIVE(i) (CI_BASE + (i) * 32 + 0x18) - -#define CI_BLOCKIO_SEND_COMMAND (0x80000000) -#define CI_BLOCKIO_SEND_COMPLETE_ACK (0x40000000) -#define CI_BLOCKIO_RCVDATA_ACK (0x40000000) - -#define CI_BUFFER_BASE (0x3000) -#define CI_BUFFER_SIZE (0x0800) -#define CI_BLOCKIO_BUFFER_SIZE (CI_BUFFER_SIZE/2) - -#define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE ) -#define CI_BLOCKIO_RECEIVE_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE ) -#define CI_BLOCKIO_SEND_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE + CI_BLOCKIO_BUFFER_SIZE ) - -#define VCO1_BASE (0xC0) -#define VCO1_CONTROL (VCO1_BASE + 0x00) -#define VCO1_DATA (VCO1_BASE + 0x04) // 24 Bit -#define VCO1_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done -#define VCO1_CONTROL_CE (0x00000002) // 0 = Put VCO into power down -#define VCO1_CONTROL_MUXOUT (0x00000004) // Muxout from VCO (usually = Lock) - -#define VCO2_BASE (0xC8) -#define VCO2_CONTROL (VCO2_BASE + 0x00) -#define VCO2_DATA (VCO2_BASE + 0x04) // 24 Bit -#define VCO2_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done -#define VCO2_CONTROL_CE (0x00000002) // 0 = Put VCO into power down -#define VCO2_CONTROL_MUXOUT (0x00000004) // Muxout from VCO (usually = Lock) - -#define VCO3_BASE (0xD0) -#define VCO3_CONTROL (VCO3_BASE + 0x00) -#define VCO3_DATA (VCO3_BASE + 0x04) // 32 Bit -#define VCO3_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done -#define VCO3_CONTROL_CE (0x00000002) // 0 = Put VCO into power down -#define VCO3_CONTROL_MUXOUT (0x00000004) // Muxout from VCO (usually = Lock) - -#define RF_ATTENUATOR (0xD8) -// 0x00 = 0 dB -// 0x01 = 1 dB -// ... -// 0x1F = 31 dB - -#define RF_POWER (0xE0) -#define RF_POWER_BASE (0xE0) -#define RF_POWER_CONTROL (RF_POWER_BASE + 0x00) -#define RF_POWER_DATA (RF_POWER_BASE + 0x04) - -#define RF_POWER_CONTROL_START (0x00000001) -#define RF_POWER_CONTROL_DONE (0x00000002) -#define RF_POWER_CONTROL_VALIDMASK (0x00000700) -#define RF_POWER_CONTROL_VALID (0x00000500) - - -// -------------------------------------------------------------------------- -// Output control - -#define IQOUTPUT_BASE (0x240) -#define IQOUTPUT_CONTROL (IQOUTPUT_BASE + 0x00) -#define IQOUTPUT_CONTROL2 (IQOUTPUT_BASE + 0x04) -#define IQOUTPUT_PEAK_DETECTOR (IQOUTPUT_BASE + 0x08) -#define IQOUTPUT_POSTSCALER (IQOUTPUT_BASE + 0x0C) -#define IQOUTPUT_PRESCALER (IQOUTPUT_BASE + 0x10) - -#define IQOUTPUT_EQUALIZER_0 (IQOUTPUT_BASE + 0x14) -#define IQOUTPUT_EQUALIZER_1 (IQOUTPUT_BASE + 0x18) -#define IQOUTPUT_EQUALIZER_2 (IQOUTPUT_BASE + 0x1C) -#define IQOUTPUT_EQUALIZER_3 (IQOUTPUT_BASE + 0x20) -#define IQOUTPUT_EQUALIZER_4 (IQOUTPUT_BASE + 0x24) -#define IQOUTPUT_EQUALIZER_5 (IQOUTPUT_BASE + 0x28) -#define IQOUTPUT_EQUALIZER_6 (IQOUTPUT_BASE + 0x2C) -#define IQOUTPUT_EQUALIZER_7 (IQOUTPUT_BASE + 0x30) -#define IQOUTPUT_EQUALIZER_8 (IQOUTPUT_BASE + 0x34) -#define IQOUTPUT_EQUALIZER_9 (IQOUTPUT_BASE + 0x38) -#define IQOUTPUT_EQUALIZER_10 (IQOUTPUT_BASE + 0x3C) - -#define IQOUTPUT_EQUALIZER(i) (IQOUTPUT_EQUALIZER_0 + (i) * 4 ) - -#define IQOUTPUT_CONTROL_RESET (0x00000001) -#define IQOUTPUT_CONTROL_ENABLE (0x00000002) -#define IQOUTPUT_CONTROL_RESET_PEAK (0x00000004) -#define IQOUTPUT_CONTROL_ENABLE_PEAK (0x00000008) -#define IQOUTPUT_CONTROL_BYPASS_EQUALIZER (0x00000010) - - -// -------------------------------------------------------------------------- -// - -#define MODULATOR_BASE (0x200) -#define MODULATOR_CONTROL (MODULATOR_BASE) -#define MODULATOR_IQTABLE_END (MODULATOR_BASE+4) -#define MODULATOR_IQTABLE_INDEX (MODULATOR_BASE+8) -#define MODULATOR_IQTABLE_DATA (MODULATOR_BASE+12) - -#define MODULATOR_IQTABLE_INDEX_CHANNEL_MASK ( 0x000F0000 ) -#define MODULATOR_IQTABLE_INDEX_IQ_MASK ( 0x00008000 ) -#define MODULATOR_IQTABLE_INDEX_ADDRESS_MASK ( 0x000007FF ) -#define MODULATOR_IQTABLE_INDEX_SEL_I ( 0x00000000 ) -#define MODULATOR_IQTABLE_INDEX_SEL_Q ( MODULATOR_IQTABLE_INDEX_IQ_MASK ) -#define MODULATOR_IQTABLE_SIZE (2048) - - -// -------------------------------------------------------------------------- -// Modulator Channels - -#define CHANNEL_BASE (0x400) -#define CHANNEL_CONTROL(i) (CHANNEL_BASE + (i) * 64 + 0x00) -#define CHANNEL_SETTINGS(i) (CHANNEL_BASE + (i) * 64 + 0x04) -#define CHANNEL_RATE_INCR(i) (CHANNEL_BASE + (i) * 64 + 0x0C) -#define CHANNEL_PCR_ADJUST_OUTL(i) (CHANNEL_BASE + (i) * 64 + 0x10) -#define CHANNEL_PCR_ADJUST_OUTH(i) (CHANNEL_BASE + (i) * 64 + 0x14) -#define CHANNEL_PCR_ADJUST_INL(i) (CHANNEL_BASE + (i) * 64 + 0x18) -#define CHANNEL_PCR_ADJUST_INH(i) (CHANNEL_BASE + (i) * 64 + 0x1C) -#define CHANNEL_PCR_ADJUST_ACCUL(i) (CHANNEL_BASE + (i) * 64 + 0x20) -#define CHANNEL_PCR_ADJUST_ACCUH(i) (CHANNEL_BASE + (i) * 64 + 0x24) -#define CHANNEL_PKT_COUNT_OUT(i) (CHANNEL_BASE + (i) * 64 + 0x28) -#define CHANNEL_PKT_COUNT_IN(i) (CHANNEL_BASE + (i) * 64 + 0x2C) - -#define CHANNEL_CONTROL_RESET (0x00000001) -#define CHANNEL_CONTROL_ENABLE_DVB (0x00000002) -#define CHANNEL_CONTROL_ENABLE_IQ (0x00000004) -#define CHANNEL_CONTROL_ENABLE_SOURCE (0x00000008) -#define CHANNEL_CONTROL_ENABLE_PCRADJUST (0x00000010) -#define CHANNEL_CONTROL_FREEZE_STATUS (0x00000100) - -#define CHANNEL_CONTROL_RESET_ERROR (0x00010000) -#define CHANNEL_CONTROL_BUSY (0x01000000) -#define CHANNEL_CONTROL_ERROR_SYNC (0x20000000) -#define CHANNEL_CONTROL_ERROR_UNDERRUN (0x40000000) -#define CHANNEL_CONTROL_ERROR_FATAL (0x80000000) - -#define CHANNEL_SETTINGS_QAM_MASK (0x00000007) -#define CHANNEL_SETTINGS_QAM16 (0x00000000) -#define CHANNEL_SETTINGS_QAM32 (0x00000001) -#define CHANNEL_SETTINGS_QAM64 (0x00000002) -#define CHANNEL_SETTINGS_QAM128 (0x00000003) -#define CHANNEL_SETTINGS_QAM256 (0x00000004) - - -/* OCTONET */ - -#define ETHER_BASE (0x100) -#define ETHER_CONTROL (ETHER_BASE + 0x00) -#define ETHER_LENGTH (ETHER_BASE + 0x04) - -#define RTP_MASTER_BASE (0x120) -#define RTP_MASTER_CONTROL (RTP_MASTER_BASE + 0x00) -#define RTP_RTCP_INTERRUPT (RTP_MASTER_BASE + 0x04) -#define RTP_MASTER_RTCP_SETTINGS (RTP_MASTER_BASE + 0x0c) - -#define STREAM_BASE (0x400) -#define STREAM_CONTROL(i) (STREAM_BASE + (i) * 0x20 + 0x00) -#define STREAM_RTP_PACKET(i) (STREAM_BASE + (i) * 0x20 + 0x04) -#define STREAM_RTCP_PACKET(i) (STREAM_BASE + (i) * 0x20 + 0x08) -#define STREAM_RTP_SETTINGS(i) (STREAM_BASE + (i) * 0x20 + 0x0c) -#define STREAM_INSERT_PACKET(i) (STREAM_BASE + (i) * 0x20 + 0x10) - -#define STREAM_PACKET_OFF(i) ((i) * 0x200) -#define STREAM_PACKET_ADR(i) (0x2000 + (STREAM_PACKET_OFF(i))) - -#define STREAM_PIDS(i) (0x4000 + (i) * 0x400) - -#define TS_CAPTURE_BASE (0x0140) -#define TS_CAPTURE_CONTROL (TS_CAPTURE_BASE + 0x00) -#define TS_CAPTURE_PID (TS_CAPTURE_BASE + 0x04) -#define TS_CAPTURE_RECEIVED (TS_CAPTURE_BASE + 0x08) -#define TS_CAPTURE_TIMEOUT (TS_CAPTURE_BASE + 0x0c) -#define TS_CAPTURE_TABLESECTION (TS_CAPTURE_BASE + 0x10) - -#define TS_CAPTURE_MEMORY (0x7000) - -#define PID_FILTER_BASE (0x800) -#define PID_FILTER_SYSTEM_PIDS(i) (PID_FILTER_BASE + (i) * 0x20) -#define PID_FILTER_PID(i, j) (PID_FILTER_BASE + (i) * 0x20 + (j) * 4) - - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,432 +0,0 @@ -/* - * ddbridge.c: Digital Devices PCIe bridge driver - * - * Copyright (C) 2010-2013 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -//#define DDB_ALT_DMA -#define DDB_USE_WORK -//#define DDB_TEST_THREADED -#undef CONFIG_PCI_MSI - -#include "ddbridge.h" -#include "ddbridge-regs.h" - -#include "tda18271c2dd.h" -#include "stv6110x.h" -#include "stv090x.h" -#include "lnbh24.h" -#include "drxk.h" -#include "stv0367.h" -#include "stv0367dd.h" -#include "tda18212.h" -#include "tda18212dd.h" -#include "cxd2843.h" - -static struct workqueue_struct *ddb_wq; - -static int adapter_alloc; -module_param(adapter_alloc, int, 0444); -MODULE_PARM_DESC(adapter_alloc, "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); - -#include "ddbridge-core.c" - -/****************************************************************************/ -/****************************************************************************/ -/****************************************************************************/ - -static void ddb_unmap(struct ddb *dev) -{ - if (dev->regs) - iounmap(dev->regs); - vfree(dev); -} - - -static void __devexit ddb_remove(struct pci_dev *pdev) -{ - struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev); - - ddb_ports_detach(dev); - ddb_i2c_release(dev); - - ddbwritel(dev, 0, INTERRUPT_ENABLE); - ddbwritel(dev, 0, MSI1_ENABLE); - if (dev->msi == 2) - free_irq(dev->pdev->irq + 1, dev); - free_irq(dev->pdev->irq, dev); -#ifdef CONFIG_PCI_MSI - if (dev->msi) - pci_disable_msi(dev->pdev); -#endif - ddb_ports_release(dev); - ddb_buffers_free(dev); - ddb_device_destroy(dev); - - ddb_unmap(dev); - pci_set_drvdata(pdev, 0); - pci_disable_device(pdev); -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) -#define __devinit -#define __devinitdata -#endif - -static int __devinit ddb_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - struct ddb *dev; - int stat = 0; - int irq_flag = IRQF_SHARED; - - if (pci_enable_device(pdev) < 0) - return -ENODEV; - - dev = vzalloc(sizeof(struct ddb)); - if (dev == NULL) - return -ENOMEM; - - dev->has_dma = 1; - dev->pdev = pdev; - dev->dev = &pdev->dev; - pci_set_drvdata(pdev, dev); - dev->id = id; - dev->info = (struct ddb_info *) id->driver_data; - printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); - - dev->regs_len = pci_resource_len(dev->pdev, 0); - dev->regs = ioremap(pci_resource_start(dev->pdev, 0), - pci_resource_len(dev->pdev, 0)); - if (!dev->regs) { - printk("DDBridge: not enough memory for register map\n"); - stat = -ENOMEM; - goto fail; - } - if (ddbreadl(dev, 0) == 0xffffffff) { - printk("DDBridge: cannot read registers\n"); - stat = -ENODEV; - goto fail; - } - - dev->hwid = ddbreadl(dev, 0); - dev->regmapid = ddbreadl(dev, 4); - - printk(KERN_INFO "HW %08x REGMAP %08x\n", - dev->hwid, dev->regmapid); - - ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); - ddbwritel(dev, 0x00000000, MSI1_ENABLE); - ddbwritel(dev, 0x00000000, MSI2_ENABLE); - ddbwritel(dev, 0x00000000, MSI3_ENABLE); - ddbwritel(dev, 0x00000000, MSI4_ENABLE); - ddbwritel(dev, 0x00000000, MSI5_ENABLE); - ddbwritel(dev, 0x00000000, MSI6_ENABLE); - ddbwritel(dev, 0x00000000, MSI7_ENABLE); - -#ifdef CONFIG_PCI_MSI - if (pci_msi_enabled()) { - stat = pci_enable_msi_block(dev->pdev, 2); - if (stat == 0) { - dev->msi = 1; - printk("DDBrige using 2 MSI interrupts\n"); - } - if (stat == 1) - stat = pci_enable_msi(dev->pdev); - if (stat < 0) { - printk(KERN_INFO ": MSI not available.\n"); - } else { - irq_flag = 0; - dev->msi++; - } - } -#endif - if (dev->msi == 2) { - stat = request_irq(dev->pdev->irq, irq_handler0, - irq_flag, "ddbridge", (void *) dev); - if (stat < 0) - goto fail0; - stat = request_irq(dev->pdev->irq + 1, irq_handler1, - irq_flag, "ddbridge", (void *) dev); - if (stat < 0) { - free_irq(dev->pdev->irq, dev); - goto fail0; - } - } else { -#ifdef DDB_TEST_THREADED - stat = request_threaded_irq(dev->pdev->irq, irq_handler, - irq_thread, - irq_flag, - "ddbridge", (void *) dev); -#else - stat = request_irq(dev->pdev->irq, irq_handler, - irq_flag, "ddbridge", (void *) dev); -#endif - if (stat < 0) - goto fail0; - } - ddbwritel(dev, 0, DMA_BASE_READ); - if (dev->info->type != DDB_MOD) - ddbwritel(dev, 0, DMA_BASE_WRITE); - - //ddbwritel(dev, 0xffffffff, INTERRUPT_ACK); - if (dev->msi == 2) { - ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE); - ddbwritel(dev, 0x0000000f, MSI1_ENABLE); - } else { - ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); - ddbwritel(dev, 0x00000000, MSI1_ENABLE); - } - if (ddb_i2c_init(dev) < 0) - goto fail1; - ddb_ports_init(dev); - if (ddb_buffers_alloc(dev) < 0) { - printk(KERN_INFO ": Could not allocate buffer memory\n"); - goto fail2; - } - if (ddb_ports_attach(dev) < 0) - goto fail3; - - /* ignore if this fails */ - ddb_device_create(dev); - - if (dev->info->fan_num) { - ddbwritel(dev, 1, GPIO_DIRECTION); - ddbwritel(dev, 1, GPIO_OUTPUT); - } - if (dev->info->type == DDB_MOD) - ddbridge_mod_init(dev); - - return 0; - -fail3: - ddb_ports_detach(dev); - printk(KERN_ERR "fail3\n"); - ddb_ports_release(dev); -fail2: - printk(KERN_ERR "fail2\n"); - ddb_buffers_free(dev); - ddb_i2c_release(dev); -fail1: - printk(KERN_ERR "fail1\n"); - ddbwritel(dev, 0, INTERRUPT_ENABLE); - ddbwritel(dev, 0, MSI1_ENABLE); - free_irq(dev->pdev->irq, dev); - if (dev->msi == 2) - free_irq(dev->pdev->irq + 1, dev); -fail0: - printk(KERN_ERR "fail0\n"); - if (dev->msi) - pci_disable_msi(dev->pdev); -fail: - printk(KERN_ERR "fail\n"); - ddb_unmap(dev); - pci_set_drvdata(pdev, 0); - pci_disable_device(pdev); - return -1; -} - -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ - -struct ddb_regset octopus_i2c = { - .base = 0x80, - .num = 0x04, - .size = 0x20, -}; - -static struct ddb_regmap octopus_map = { -// .i2c = octopus_i2c, -}; - -static struct ddb_info ddb_none = { - .type = DDB_NONE, - .name = "unknown Digital Devices PCIe card, install newer driver", -// .regmap = octopus_map, -}; - -static struct ddb_info ddb_octopus = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus DVB adapter", - .port_num = 4, - .i2c_num = 4, -}; - -static struct ddb_info ddb_octopusv3 = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus V3 DVB adapter", - .port_num = 4, - .i2c_num = 4, -}; - -static struct ddb_info ddb_octopus_le = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus LE DVB adapter", - .port_num = 2, - .i2c_num = 2, -}; - -static struct ddb_info ddb_octopus_oem = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus OEM", - .port_num = 4, - .i2c_num = 4, - .led_num = 1, - .fan_num = 1, - .temp_num = 1, - .temp_bus = 0, -}; - -static struct ddb_info ddb_octopus_mini = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus Mini", - .port_num = 4, - .i2c_num = 4, -}; - -static struct ddb_info ddb_v6 = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Cine S2 V6 DVB adapter", - .port_num = 3, - .i2c_num = 3, -}; - -static struct ddb_info ddb_v6_5 = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Cine S2 V6.5 DVB adapter", - .port_num = 4, - .i2c_num = 4, -}; - -static struct ddb_info ddb_satixS2v3 = { - .type = DDB_OCTOPUS, - .name = "Mystique SaTiX-S2 V3 DVB adapter", - .port_num = 3, - .i2c_num = 3, -}; - -static struct ddb_info ddb_ci = { - .type = DDB_OCTOPUS_CI, - .name = "Digital Devices Octopus CI", - .port_num = 4, - .i2c_num = 2, -}; - -static struct ddb_info ddb_cis = { - .type = DDB_OCTOPUS_CI, - .name = "Digital Devices Octopus CI single", - .port_num = 3, - .i2c_num = 2, -}; - -static struct ddb_info ddb_dvbct = { - .type = DDB_OCTOPUS, - .name = "Digital Devices DVBCT V6.1 DVB adapter", - .port_num = 3, - .i2c_num = 3, -}; - -static struct ddb_info ddb_mod = { - .type = DDB_MOD, - .name = "Digital Devices DVB-C modulator", - .port_num = 10, - .temp_num = 1, -}; - -static struct ddb_info ddb_octonet = { - .type = DDB_OCTONET, - .name = "Digital Devices Octopus Net", - .port_num = 4, - .i2c_num = 4, -}; - -#define DDVID 0xdd01 /* Digital Devices Vendor ID */ - -#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ - .vendor = _vend, .device = _dev, \ - .subvendor = _subvend, .subdevice = _subdev, \ - .driver_data = (unsigned long)&_driverdata } - -static const struct pci_device_id ddb_id_tbl[] __devinitdata = { - DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), - DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), - DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3), - DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), - DDB_ID(DDVID, 0x0003, DDVID, 0x0003, ddb_octopus_oem), - DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), - DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), - DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), - DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), - DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), - DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci), - DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis), - DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod), - /* in case sub-ids got deleted in flash */ - DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), - DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none), - DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none), - {0} -}; -MODULE_DEVICE_TABLE(pci, ddb_id_tbl); - -static struct pci_driver ddb_pci_driver = { - .name = "ddbridge", - .id_table = ddb_id_tbl, - .probe = ddb_probe, - .remove = ddb_remove, -}; - -static __init int module_init_ddbridge(void) -{ - int stat = -1; - - printk(KERN_INFO "Digital Devices PCIE bridge driver 0.9.9, " - "Copyright (C) 2010-13 Digital Devices GmbH\n"); - if (ddb_class_create() < 0) - return -1; - ddb_wq = create_workqueue("ddbridge"); - if (ddb_wq == NULL) - goto exit1; - stat = pci_register_driver(&ddb_pci_driver); - if (stat < 0) - goto exit2; - return stat; -exit2: - destroy_workqueue(ddb_wq); -exit1: - ddb_class_destroy(); - return stat; -} - -static __exit void module_exit_ddbridge(void) -{ - pci_unregister_driver(&ddb_pci_driver); - destroy_workqueue(ddb_wq); - ddb_class_destroy(); -} - -module_init(module_init_ddbridge); -module_exit(module_exit_ddbridge); - -MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); -MODULE_AUTHOR("Ralph Metzler, Metzler Brothers Systementwicklung"); -MODULE_LICENSE("GPL"); -MODULE_VERSION("0.9.9"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/ddbridge.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,477 +0,0 @@ -/* - * ddbridge.h: Digital Devices PCIe bridge driver - * - * Copyright (C) 2010-2013 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef _DDBRIDGE_H_ -#define _DDBRIDGE_H_ - -#include - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) -#define __devexit -#define __devinit -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "dvb_netstream.h" -#include "dmxdev.h" -#include "dvbdev.h" -#include "dvb_demux.h" -#include "dvb_frontend.h" -#include "dvb_ringbuffer.h" -#include "dvb_ca_en50221.h" -#include "dvb_net.h" -#include "cxd2099.h" - -#define DDB_MAX_I2C 4 -#define DDB_MAX_PORT 10 -#define DDB_MAX_INPUT 8 -#define DDB_MAX_OUTPUT 10 - -struct ddb_regset { - uint32_t base; - uint32_t num; - uint32_t size; -}; - -struct ddb_regmap { - struct ddb_regset i2c; - struct ddb_regset i2c_buf; - struct ddb_regset dma; - struct ddb_regset dma_buf; - struct ddb_regset input; - struct ddb_regset output; - struct ddb_regset channel; - struct ddb_regset ci; - struct ddb_regset pid_filter; -}; - -struct ddb_info { - int type; -#define DDB_NONE 0 -#define DDB_OCTOPUS 1 -#define DDB_OCTOPUS_CI 2 -#define DDB_MOD 3 -#define DDB_OCTONET 4 - char *name; - int port_num; - int i2c_num; - int led_num; - int fan_num; - int temp_num; - int temp_bus; - struct ddb_regmap regmap; -}; - - -/* DMA_SIZE MUST be smaller than 256k and - MUST be divisible by 188 and 128 !!! */ - -#define DMA_MAX_BUFS 32 /* hardware table limit */ - -#define INPUT_DMA_BUFS 8 -#define INPUT_DMA_SIZE (128*47*21) -#define INPUT_DMA_IRQ_DIV 1 - -#define OUTPUT_DMA_BUFS 8 -#define OUTPUT_DMA_SIZE (128*47*21) -#define OUTPUT_DMA_IRQ_DIV 1 - -struct ddb; -struct ddb_port; - -struct ddb_dma { - void *io; - u32 nr; - dma_addr_t pbuf[DMA_MAX_BUFS]; - u8 *vbuf[DMA_MAX_BUFS]; - u32 num; - u32 size; - u32 div; - u32 bufreg; - -#ifdef DDB_USE_WORK - struct work_struct work; -#else - struct tasklet_struct tasklet; -#endif - spinlock_t lock; - wait_queue_head_t wq; - int running; - u32 stat; - u32 ctrl; - u32 cbuf; - u32 coff; -}; - -struct ddb_dvb { - struct dvb_adapter *adap; - int adap_registered; - struct dvb_device *dev; - struct dvb_frontend *fe; - struct dvb_frontend *fe2; - struct dmxdev dmxdev; - struct dvb_demux demux; - struct dvb_net dvbnet; - struct dvb_netstream dvbns; - struct dmx_frontend hw_frontend; - struct dmx_frontend mem_frontend; - int users; - int (*gate_ctrl)(struct dvb_frontend *, int); - int attached; -}; - -struct ddb_ci { - struct dvb_ca_en50221 en; - struct ddb_port *port; - u32 nr; - struct mutex lock; -}; - -struct ddb_io { - struct ddb_port *port; - u32 nr; - struct ddb_dma *dma; -// struct ddb_io *redirect; - struct ddb_io *redo; - struct ddb_io *redi; -}; - -#if 0 -struct ddb_input { - struct ddb_port *port; - u32 nr; - struct ddb_dma *dma; - struct ddb_output *redo; - struct ddb_input *redi; -}; - -struct ddb_output { - struct ddb_port *port; - u32 nr; - struct ddb_dma *dma; - struct ddb_output *redo; - struct ddb_input *redi; -}; -#else -#define ddb_output ddb_io -#define ddb_input ddb_io -#endif - -struct ddb_i2c { - struct ddb *dev; - u32 nr; - struct i2c_adapter adap; - u32 regs; - u32 rbuf; - u32 wbuf; -// int done; -// wait_queue_head_t wq; - struct completion completion; -}; - -struct ddb_port { - struct ddb *dev; - u32 nr; - struct ddb_i2c *i2c; - struct mutex i2c_gate_lock; - u32 class; -#define DDB_PORT_NONE 0 -#define DDB_PORT_CI 1 -#define DDB_PORT_TUNER 2 -#define DDB_PORT_LOOP 3 -#define DDB_PORT_MOD 4 - u32 type; -#define DDB_TUNER_NONE 0 -#define DDB_TUNER_DVBS_ST 1 -#define DDB_TUNER_DVBS_ST_AA 2 -#define DDB_TUNER_DVBCT_TR 3 -#define DDB_TUNER_DVBCT_ST 4 -#define DDB_CI_INTERNAL 5 -#define DDB_CI_EXTERNAL_SONY 6 -#define DDB_TUNER_XO2 16 -#define DDB_TUNER_DVBS 16 -#define DDB_TUNER_DVBCT2_SONY 17 -#define DDB_TUNER_ISDBT_SONY 18 -#define DDB_TUNER_DVBC2T2_SONY 19 -#define DDB_TUNER_ATSC_ST 20 -#define DDB_TUNER_DVBC2T2_ST 21 - - u32 adr; - - struct ddb_input *input[2]; - struct ddb_output *output; - struct dvb_ca_en50221 *en; - struct ddb_dvb dvb[2]; - u32 gap; - u32 obr; -}; - - -struct mod_base { - u32 frequency; - - u32 flat_start; - u32 flat_end; -}; - -struct mod_state { - u32 modulation; - - u32 do_handle; - - u32 rate_inc; - u32 Control; - u32 State; - u32 StateCounter; - s32 LastPCRAdjust; - s32 PCRAdjustSum; - s32 InPacketsSum; - s32 OutPacketsSum; - s64 PCRIncrement; - s64 PCRDecrement; - s32 PCRRunningCorr; - u32 OutOverflowPacketCount; - u32 InOverflowPacketCount; - u32 LastOutPacketCount; - u32 LastInPacketCount; - u64 LastOutPackets; - u64 LastInPackets; - u32 MinInputPackets; -}; - -#define CM_STARTUP_DELAY 2 -#define CM_AVERAGE 20 -#define CM_GAIN 10 - -#define HW_LSB_SHIFT 12 -#define HW_LSB_MASK 0x1000 - -#define CM_IDLE 0 -#define CM_STARTUP 1 -#define CM_ADJUST 2 - -#define TS_CAPTURE_LEN (21*188) - -/* net streaming hardware block */ - -#define DDB_NS_MAX 15 - -struct ddb_ns { - struct ddb_input *input; - int nr; - int fe; - u32 rtcp_udplen; - u32 rtcp_len; - u32 ts_offset; - u32 udplen; - u8 p[512]; -}; - -struct ddb { - struct pci_dev *pdev; - struct platform_device *pfdev; - struct device *dev; - const struct pci_device_id *id; - struct ddb_info *info; - int msi; - struct workqueue_struct *wq; - u32 has_dma; - u32 has_ns; - - struct ddb_regmap regmap; - unsigned char *regs; - u32 regs_len; - struct ddb_port port[DDB_MAX_PORT]; - struct ddb_i2c i2c[DDB_MAX_I2C]; - struct ddb_input input[DDB_MAX_INPUT]; - struct ddb_output output[DDB_MAX_OUTPUT]; - struct dvb_adapter adap[DDB_MAX_INPUT]; - struct ddb_dma dma[DDB_MAX_INPUT + DDB_MAX_OUTPUT]; - - void (*handler[32])(unsigned long); - unsigned long handler_data[32]; - - struct device *ddb_dev; - u32 ddb_dev_users; - u32 nr; - u8 iobuf[1028]; - - u8 leds; - u32 ts_irq; - u32 i2c_irq; - - u32 hwid; - u32 regmapid; - u32 mac; - u32 devid; - - int ns_num; - struct ddb_ns ns[DDB_NS_MAX]; - struct mutex mutex; - - struct dvb_device *nsd_dev; - u8 tsbuf[TS_CAPTURE_LEN]; - - struct mod_base mod_base; - struct mod_state mod[10]; -}; - - -/******************************************************************************/ - -static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr) -{ - writeb(val, (char *) (dev->regs+(adr))); -} - -static inline void ddbwritel(struct ddb *dev, u32 val, u32 adr) -{ - writel(val, (char *) (dev->regs+(adr))); -} - -static inline void ddbwritew(struct ddb *dev, u16 val, u32 adr) -{ - writew(val, (char *) (dev->regs+(adr))); -} - -static inline u32 ddbreadl(struct ddb *dev, u32 adr) -{ - return readl((char *) (dev->regs+(adr))); -} - -static inline u32 ddbreadb(struct ddb *dev, u32 adr) -{ - return readb((char *) (dev->regs+(adr))); -} - -#define ddbcpyto(_dev, _adr, _src, _count) \ - memcpy_toio((char *) (_dev->regs + (_adr)), (_src), (_count)) - -#define ddbcpyfrom(_dev, _dst, _adr, _count) \ - memcpy_fromio((_dst), (char *) (_dev->regs + (_adr)), (_count)) - -#define ddbmemset(_dev, _adr, _val, _count) \ - memset_io((char *) (_dev->regs + (_adr)), (_val), (_count)) - - -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ - -#define dd_uint8 u8 -#define dd_uint16 u16 -#define dd_int16 s16 -#define dd_uint32 u32 -#define dd_int32 s32 -#define dd_uint64 u64 -#define dd_int64 s64 - -#define DDMOD_FLASH_START 0x1000 - -struct DDMOD_FLASH_DS { - dd_uint32 Symbolrate; /* kSymbols/s */ - dd_uint32 DACFrequency; /* kHz */ - dd_uint16 FrequencyResolution; /* kHz */ - dd_uint16 IQTableLength; - dd_uint16 FrequencyFactor; - dd_int16 PhaseCorr; /* TBD */ - dd_uint32 Control2; - dd_uint16 PostScaleI; - dd_uint16 PostScaleQ; - dd_uint16 PreScale; - dd_int16 EQTap[11]; - dd_uint16 FlatStart; - dd_uint16 FlatEnd; - dd_uint32 FlashOffsetPrecalculatedIQTables; /* 0 = none */ - dd_uint8 Reserved[28]; - -}; - -struct DDMOD_FLASH { - dd_uint32 Magic; - dd_uint16 Version; - dd_uint16 DataSets; - - dd_uint16 VCORefFrequency; /* MHz */ - dd_uint16 VCO1Frequency; /* MHz */ - dd_uint16 VCO2Frequency; /* MHz */ - - dd_uint16 DACAux1; /* TBD */ - dd_uint16 DACAux2; /* TBD */ - - dd_uint8 Reserved1[238]; - - struct DDMOD_FLASH_DS DataSet[1]; -}; - -#define DDMOD_FLASH_MAGIC 0x5F564d5F - - -int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg); -int ddbridge_mod_init(struct ddb *dev); -void ddbridge_mod_output_stop(struct ddb_output *output); -void ddbridge_mod_output_start(struct ddb_output *output); -void ddbridge_mod_rate_handler(unsigned long data); - - -int ddbridge_flashread(struct ddb *dev, u8 *buf, u32 addr, u32 len); - - -#endif - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/octonet.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/octonet.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/octonet.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddbridge/octonet.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,176 +0,0 @@ -/* - * octonet.c: Digital Devices network tuner driver - * - * Copyright (C) 2012-13 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include "ddbridge.h" -#include "ddbridge-regs.h" - -#include "tda18271c2dd.h" -#include "stv6110x.h" -#include "stv090x.h" -#include "lnbh24.h" -#include "drxk.h" -#include "stv0367.h" -#include "stv0367dd.h" -#include "tda18212dd.h" -#include "cxd2843.h" - -#include - -static int adapter_alloc = 3; -module_param(adapter_alloc, int, 0444); -MODULE_PARM_DESC(adapter_alloc, "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); - -#define DVB_NETSTREAM - -#include "ddbridge-core.c" - -static struct ddb_info ddb_octonet = { - .type = DDB_OCTONET, - .name = "Digital Devices OctopusNet network DVB adapter", - .port_num = 4, - .i2c_num = 4, -}; - -static void octonet_unmap(struct ddb *dev) -{ - if (dev->regs) - iounmap(dev->regs); - vfree(dev); -} - -static int __exit octonet_remove(struct platform_device *pdev) -{ - struct ddb *dev; - - dev = platform_get_drvdata(pdev); - - ddb_nsd_detach(dev); - ddb_ports_detach(dev); - ddb_i2c_release(dev); - - ddbwritel(dev, 0, ETHER_CONTROL); - ddbwritel(dev, 0, INTERRUPT_ENABLE); - free_irq(platform_get_irq(dev->pfdev, 0), dev); - - ddb_device_destroy(dev); - octonet_unmap(dev); - platform_set_drvdata(pdev, 0); - return 0; -} - -static int __init octonet_probe(struct platform_device *pdev) -{ - struct ddb *dev; - struct resource *regs; - - dev = vzalloc(sizeof(struct ddb)); - if (!dev) - return -ENOMEM; - platform_set_drvdata(pdev, dev); - dev->dev = &pdev->dev; - dev->pfdev = pdev; - dev->info = &ddb_octonet; - mutex_init(&dev->mutex); - - regs = platform_get_resource(dev->pfdev, IORESOURCE_MEM, 0); - if (!regs) - return -ENXIO; - dev->regs_len = (regs->end - regs->start) + 1; - dev->regs = ioremap(regs->start, dev->regs_len); - if (!dev->regs) - return -ENOMEM; - - dev->hwid = ddbreadl(dev, 0); - dev->regmapid = ddbreadl(dev, 4); - dev->devid = ddbreadl(dev, 8); - dev->mac = ddbreadl(dev, 12); - - printk(KERN_INFO "HW %08x REGMAP %08x\n", dev->hwid, dev->regmapid); - printk(KERN_INFO "MAC %08x DEVID %08x\n", dev->mac, dev->devid); - - ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); - - if (request_irq(platform_get_irq(dev->pfdev, 0), irq_handler, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "octonet-dvb", (void *) dev) < 0) - goto fail; - ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); - ddbwritel(dev, 0x1, ETHER_CONTROL); - ddbwritel(dev, 14 + (vlan ? 4 : 0), ETHER_LENGTH); - - - if (ddb_i2c_init(dev) < 0) - goto fail1; - ddb_ports_init(dev); - if (ddb_ports_attach(dev) < 0) - goto fail3; - - ddb_nsd_attach(dev); - - ddb_device_create(dev); - - return 0; - -fail3: - ddb_ports_detach(dev); - printk(KERN_ERR "fail3\n"); -fail1: -fail: - ddbwritel(dev, 0, ETHER_CONTROL); - ddbwritel(dev, 0, INTERRUPT_ENABLE); - octonet_unmap(dev); - platform_set_drvdata(pdev, 0); - return 0; -} - -static struct platform_driver octonet_driver = { - .remove = __exit_p(octonet_remove), - .probe = octonet_probe, - .driver = { - .name = "octonet-dvb", - .owner = THIS_MODULE, - }, -}; - -static __init int init_octonet(void) -{ - printk(KERN_INFO "Digital Devices OctoNet driver, " - "Copyright (C) 2012-2013 Digital Devices GmbH\n"); - if (ddb_class_create()) - return -1; - return platform_driver_probe(&octonet_driver, octonet_probe); -} - -static __exit void exit_octonet(void) -{ - platform_driver_unregister(&octonet_driver); - ddb_class_destroy(); -} - -module_init(init_octonet); -module_exit(exit_octonet); - -MODULE_DESCRIPTION("GPL"); -MODULE_AUTHOR("Metzler Brothers Systementwicklung"); -MODULE_LICENSE("GPL"); -MODULE_VERSION("0.3"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddip/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddip/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddip/Kbuild 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddip/Kbuild 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -obj-$(CONFIG_DVB_DDBRIDGE) += ddip.o - -EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -Idrivers/media/dvb-frontends -EXTRA_CFLAGS += -Idrivers/media/common/tuners -NOSTDINC_FLAGS += -I$(SUBDIRS)/frontends -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddip/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddip/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddip/Makefile 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddip/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,18 +0,0 @@ -KDIR ?= /lib/modules/$(shell uname -r)/build -PWD := $(shell pwd) - -MODDEFS := CONFIG_DVB_DDIP=m - -all: - $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) $(MODDEFS) modules - -dep: - DIR=`pwd`; (cd $(TOPDIR); make SUBDIRS=$$DIR dep) - -install: all - $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules_install - -clean: - rm -rf */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules* - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddip/ddip.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddip/ddip.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/ddip/ddip.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/ddip/ddip.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,23 +0,0 @@ -#include -#include -#include - - -static __init int init_ddip(void) -{ - - return 0; -} - -static __exit void exit_ddip(void) -{ -} - -module_init(init_ddip); -module_exit(exit_ddip); - -MODULE_DESCRIPTION("GPL"); -MODULE_AUTHOR("Metzler Brothers Systementwicklung"); -MODULE_LICENSE("GPL"); -MODULE_VERSION("0.1"); - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dkms.conf dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dkms.conf --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dkms.conf 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dkms.conf 1970-01-01 00:00:00.000000000 +0000 @@ -1,45 +0,0 @@ -PACKAGE_NAME=dddvb -PACKAGE_VERSION=0.9.10.4yavdr0 -AUTOINSTALL=y -MAKE="make all" -CLEAN="make clean" -PATCH[0]=ddbridge.diff -PATCH[1]=drxk.diff -PATCH[2]=drxk_lockstatus_fix.diff -PATCH[3]=srcversion.diff -BUILT_MODULE_NAME[0]=dvb-core -BUILT_MODULE_LOCATION[0]=dvb-core/ -DEST_MODULE_LOCATION[0]=/updates/dkms -BUILT_MODULE_NAME[1]=octonet -BUILT_MODULE_LOCATION[1]=ddbridge/ -DEST_MODULE_LOCATION[1]=/updates/dkms -BUILT_MODULE_NAME[2]=ddbridge -BUILT_MODULE_LOCATION[2]=ddbridge/ -DEST_MODULE_LOCATION[2]=/updates/dkms -BUILT_MODULE_NAME[3]=drxk -BUILT_MODULE_LOCATION[3]=frontends/ -DEST_MODULE_LOCATION[3]=/updates/dkms -BUILT_MODULE_NAME[4]=tda18212dd -BUILT_MODULE_LOCATION[4]=frontends/ -DEST_MODULE_LOCATION[4]=/updates/dkms -BUILT_MODULE_NAME[5]=stv0367dd -BUILT_MODULE_LOCATION[5]=frontends/ -DEST_MODULE_LOCATION[5]=/updates/dkms -BUILT_MODULE_NAME[6]=lnbp21 -BUILT_MODULE_LOCATION[6]=frontends/ -DEST_MODULE_LOCATION[6]=/updates/dkms -BUILT_MODULE_NAME[7]=stv6110x -BUILT_MODULE_LOCATION[7]=frontends/ -DEST_MODULE_LOCATION[7]=/updates/dkms -BUILT_MODULE_NAME[8]=cxd2843 -BUILT_MODULE_LOCATION[8]=frontends/ -DEST_MODULE_LOCATION[8]=/updates/dkms -BUILT_MODULE_NAME[9]=stv090x -BUILT_MODULE_LOCATION[9]=frontends/ -DEST_MODULE_LOCATION[9]=/updates/dkms -BUILT_MODULE_NAME[10]=cxd2099 -BUILT_MODULE_LOCATION[10]=frontends/ -DEST_MODULE_LOCATION[10]=/updates/dkms -BUILT_MODULE_NAME[11]=tda18271c2dd -BUILT_MODULE_LOCATION[11]=frontends/ -DEST_MODULE_LOCATION[11]=/updates/dkms diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/adapter_alloc dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/adapter_alloc --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/adapter_alloc 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/adapter_alloc 1970-01-01 00:00:00.000000000 +0000 @@ -1,7 +0,0 @@ -The module parameter adapter_alloc lets you choose how adapter names are allocated. - -0 = one adapter per io if modules are present -1 = one adapter for each tab on which a module was detected -2 = one per tab even if no modules were detected -3 = one adapter for all devices of one card - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/ci dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/ci --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/ci 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/ci 1970-01-01 00:00:00.000000000 +0000 @@ -1,29 +0,0 @@ -The caX device associated with a CI device behaves just like any other -caX interface. You usually use it through a library like libdvben50221 -which is part of the dvb-apps package available at linuxtv.org. - -But contrary to other hardware where the CI module is physically placed -in the data path between the the demod and PCIe bridge, in the Digital -Devices cards the CI module is separate hardware. -So, you have to feed data to the CI module by writing to the secX -(in later kernel ci0) device and read it back from the same secX device. -The advantage is that the CI module can be used with any data coming from -any frontend or file. The disadvantage is that the user application has to -write/read the data to/from the module by itself. - -The sample application apps/cit.c shows how to pipe a stream through -the CI interface. In its ouput it will show discontinuities. Those should -only occur at the start of the program (due to old packets inside the CI -interface hardware and the CI module itself) and when a CI module is -inserted or removed. - -Since some users have problems using with standard software which cannot use -the CI interface in this way, there is now the redirect feature which allows -you to tell the driver to automatically pass the data coming from one -demod through a CI before offering it through the normal demux/dvr interface. -See docs/redirect for more info. - - - - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/modulator dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/modulator --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/modulator 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/modulator 1970-01-01 00:00:00.000000000 +0000 @@ -1,29 +0,0 @@ - -Modulator channels will automatically be enabled if you redirect data -from a demodulator to it. -E.g._: - -first demod on bridge 0 TAB1, modulator on bridge 1. - -echo "00 10" > /sys/class/ddbridge/ddbridge0/redirect - -Currently it is fixed to QAM256. Controls will be added later. -Rate control is experimental and PCR correction also not -implemented yet. So, depending on the reception device -there can be disturbances in playback. - -It is now also possible to chain redirects. -E.g., demod and modulator as above, CI on bridge 0 TAB 2: - -echo "00 01" > /sys/class/ddbridge/ddbridge0/redirect -echo "02 10" > /sys/class/ddbridge/ddbridge0/redirect - -The stream is also still available at the demux device -belonging to the demod devices. - -Now write and start an application (not provided) that -talks to the CI to decrypt the desired services. -For testing one can use a standard application that -supports decryption. Additionally to seeing the -decoded service on the PC it will then also be streamed -into cable by the modulator. \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/octopusnet dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/octopusnet --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/octopusnet 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/octopusnet 1970-01-01 00:00:00.000000000 +0000 @@ -1,69 +0,0 @@ -OctopusNet ----------- - -Hardware: - -- SoC Atmel SAM9G45 400MHz ARM 926 - 64 MB DRAM - 256 MB NAND flash - -- FPGA Lattice ECP3 17 - data flash - -- 5 port switch Marvell 88E6175R - - -The FPGA is connected to the memory bus of the G45 and maps control registers into the memory space -of the G45. This is mainly to control the data flow on the FPGA. Only minimal data can be transferred -(e.g. single sections). Transport streams cannot be transferred to the G45 this way! -The FPGA can receive up to 8 TS from up to 4 Duo-Flex cards. You can also can alternatively connect -CI modules to port 2 and 3 (TAP 3 and 4). - -The FPGA is also connected to one of the ports of the gigabit switch. -There are up to 12 channels. Each channel can select one input TS, which is then passed through -a PID filter (8192 bit array) and sent to the switch as a UDP/RTP stream. - -The G45 is connected to another port of the switch (but only with 100 MBit) - - -Booting: - -The G45 does not boot from the NAND flash but from the dataflash connected to the FPGA. The G45 -does not support error correction for the boot sector and NAND with zero error boot pages -is no longer easily available. -Newer Atmel SoCs support 4-bit error correction in boot ROM but not the G45. - -So, the G45 boot looks like this: - -- Run a minimal boot rom mapped by the FPGA. -- Boot rom loads a modified bootstrap via SPI (provided via FPGA ports) from the dataflash. -- Bootstrap loads u-boot via SPI from dataflash. -- u-boot boots Linux ... - -If you remove jumper XX, boot rom is disabled and the G45 will boot from NAND flash like this: - -- Internal G45 boot rom bootstrap from NAND flash. -- Bootstrap boots u-boot from NAND flash -- u-boot boots Linux ... - -This is just a fall-back since page 0 can contain errors which cannot be corrected by the G45 boot ROM -and the bootstrap code which loads u-boot also does not contain error correction. - - - - - - - - - - - - - - - - - - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/redirect dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/redirect --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/docs/redirect 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/docs/redirect 1970-01-01 00:00:00.000000000 +0000 @@ -1,24 +0,0 @@ -Redirection of TS streams through CI modules is now supported -through /sys/class/ddbridge/ddbridge0/redirect. -It only works with cards based on the ddbridge PCIe bridge, not -with nGene based cards. - -It is set up in such a way that you can write "AB CD" to -a "redirect" attribute and data from input B of card A is then piped through -port D (meaning TAB (D+1) which uses output D and input 2*D for CI io) -of card C and then shows up in the demux device belonging to -input B (input (B&1) of TAB (B/2+1)) of card A. - -E.g.: - -echo "00 01" > /sys/class/ddbridge/ddbridge0/redirect - -will pipe input 0 of card 0 through CI at port 1 (TAB 2) of card 0. - -Redirection should only be done right after loading the driver -(or booting if the driver is built-in) and before using the -devices in any way. - -adapter_alloc=3 is rcommended when using redirect -The ci device will then show up in the same adapter directory and most -software will then assume it belongs to the frontend in the same directory. diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/Makefile 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,12 +0,0 @@ -# -# Makefile for the kernel DVB device drivers. -# - -dvb-core-objs := dvbdev.o dmxdev.o dvb_demux.o dvb_filter.o \ - dvb_ca_en50221.o dvb_frontend.o \ - dvb_net.o dvb_ringbuffer.o dvb_math.o dvb_netstream.o - -obj-$(CONFIG_DVB_CORE) += dvb-core.o - -EXTRA_CFLAGS += -DCONFIG_DVB_DYNAMIC_MINORS -DCONFIG_DVB_NET -NOSTDINC_FLAGS += -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/demux.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/demux.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/demux.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/demux.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,241 +0,0 @@ -/* - * demux.h - * - * Copyright (c) 2002 Convergence GmbH - * - * based on code: - * Copyright (c) 2000 Nokia Research Center - * Tampere, FINLAND - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef __DEMUX_H -#define __DEMUX_H - -#include -#include -#include -#include -#include - -/*--------------------------------------------------------------------------*/ -/* Common definitions */ -/*--------------------------------------------------------------------------*/ - -/* - * DMX_MAX_FILTER_SIZE: Maximum length (in bytes) of a section/PES filter. - */ - -#ifndef DMX_MAX_FILTER_SIZE -#define DMX_MAX_FILTER_SIZE 18 -#endif - -/* - * DMX_MAX_SECFEED_SIZE: Maximum length (in bytes) of a private section feed filter. - */ - -#ifndef DMX_MAX_SECTION_SIZE -#define DMX_MAX_SECTION_SIZE 4096 -#endif -#ifndef DMX_MAX_SECFEED_SIZE -#define DMX_MAX_SECFEED_SIZE (DMX_MAX_SECTION_SIZE + 188) -#endif - - -/* - * enum dmx_success: Success codes for the Demux Callback API. - */ - -enum dmx_success { - DMX_OK = 0, /* Received Ok */ - DMX_LENGTH_ERROR, /* Incorrect length */ - DMX_OVERRUN_ERROR, /* Receiver ring buffer overrun */ - DMX_CRC_ERROR, /* Incorrect CRC */ - DMX_FRAME_ERROR, /* Frame alignment error */ - DMX_FIFO_ERROR, /* Receiver FIFO overrun */ - DMX_MISSED_ERROR /* Receiver missed packet */ -} ; - -/*--------------------------------------------------------------------------*/ -/* TS packet reception */ -/*--------------------------------------------------------------------------*/ - -/* TS filter type for set() */ - -#define TS_PACKET 1 /* send TS packets (188 bytes) to callback (default) */ -#define TS_PAYLOAD_ONLY 2 /* in case TS_PACKET is set, only send the TS - payload (<=184 bytes per packet) to callback */ -#define TS_DECODER 4 /* send stream to built-in decoder (if present) */ -#define TS_DEMUX 8 /* in case TS_PACKET is set, send the TS to - the demux device, not to the dvr device */ - -struct dmx_ts_feed { - int is_filtering; /* Set to non-zero when filtering in progress */ - struct dmx_demux *parent; /* Back-pointer */ - void *priv; /* Pointer to private data of the API client */ - int (*set) (struct dmx_ts_feed *feed, - u16 pid, - int type, - enum dmx_ts_pes pes_type, - size_t circular_buffer_size, - struct timespec timeout); - int (*start_filtering) (struct dmx_ts_feed* feed); - int (*stop_filtering) (struct dmx_ts_feed* feed); -}; - -/*--------------------------------------------------------------------------*/ -/* Section reception */ -/*--------------------------------------------------------------------------*/ - -struct dmx_section_filter { - u8 filter_value [DMX_MAX_FILTER_SIZE]; - u8 filter_mask [DMX_MAX_FILTER_SIZE]; - u8 filter_mode [DMX_MAX_FILTER_SIZE]; - struct dmx_section_feed* parent; /* Back-pointer */ - void* priv; /* Pointer to private data of the API client */ -}; - -struct dmx_section_feed { - int is_filtering; /* Set to non-zero when filtering in progress */ - struct dmx_demux* parent; /* Back-pointer */ - void* priv; /* Pointer to private data of the API client */ - - int check_crc; - u32 crc_val; - - u8 *secbuf; - u8 secbuf_base[DMX_MAX_SECFEED_SIZE]; - u16 secbufp, seclen, tsfeedp; - - int (*set) (struct dmx_section_feed* feed, - u16 pid, - size_t circular_buffer_size, - int check_crc); - int (*allocate_filter) (struct dmx_section_feed* feed, - struct dmx_section_filter** filter); - int (*release_filter) (struct dmx_section_feed* feed, - struct dmx_section_filter* filter); - int (*start_filtering) (struct dmx_section_feed* feed); - int (*stop_filtering) (struct dmx_section_feed* feed); -}; - -/*--------------------------------------------------------------------------*/ -/* Callback functions */ -/*--------------------------------------------------------------------------*/ - -typedef int (*dmx_ts_cb) ( const u8 * buffer1, - size_t buffer1_length, - const u8 * buffer2, - size_t buffer2_length, - struct dmx_ts_feed* source, - enum dmx_success success); - -typedef int (*dmx_section_cb) ( const u8 * buffer1, - size_t buffer1_len, - const u8 * buffer2, - size_t buffer2_len, - struct dmx_section_filter * source, - enum dmx_success success); - -/*--------------------------------------------------------------------------*/ -/* DVB Front-End */ -/*--------------------------------------------------------------------------*/ - -enum dmx_frontend_source { - DMX_MEMORY_FE, - DMX_FRONTEND_0, - DMX_FRONTEND_1, - DMX_FRONTEND_2, - DMX_FRONTEND_3, - DMX_STREAM_0, /* external stream input, e.g. LVDS */ - DMX_STREAM_1, - DMX_STREAM_2, - DMX_STREAM_3 -}; - -struct dmx_frontend { - struct list_head connectivity_list; /* List of front-ends that can - be connected to a particular - demux */ - enum dmx_frontend_source source; -}; - -/*--------------------------------------------------------------------------*/ -/* MPEG-2 TS Demux */ -/*--------------------------------------------------------------------------*/ - -/* - * Flags OR'ed in the capabilities field of struct dmx_demux. - */ - -#define DMX_TS_FILTERING 1 -#define DMX_PES_FILTERING 2 -#define DMX_SECTION_FILTERING 4 -#define DMX_MEMORY_BASED_FILTERING 8 /* write() available */ -#define DMX_CRC_CHECKING 16 -#define DMX_TS_DESCRAMBLING 32 - -/* - * Demux resource type identifier. -*/ - -/* - * DMX_FE_ENTRY(): Casts elements in the list of registered - * front-ends from the generic type struct list_head - * to the type * struct dmx_frontend - *. -*/ - -#define DMX_FE_ENTRY(list) list_entry(list, struct dmx_frontend, connectivity_list) - -struct dmx_demux { - u32 capabilities; /* Bitfield of capability flags */ - struct dmx_frontend* frontend; /* Front-end connected to the demux */ - void* priv; /* Pointer to private data of the API client */ - int (*open) (struct dmx_demux* demux); - int (*close) (struct dmx_demux* demux); - int (*write) (struct dmx_demux* demux, const char __user *buf, size_t count); - int (*allocate_ts_feed) (struct dmx_demux* demux, - struct dmx_ts_feed** feed, - dmx_ts_cb callback); - int (*release_ts_feed) (struct dmx_demux* demux, - struct dmx_ts_feed* feed); - int (*allocate_section_feed) (struct dmx_demux* demux, - struct dmx_section_feed** feed, - dmx_section_cb callback); - int (*release_section_feed) (struct dmx_demux* demux, - struct dmx_section_feed* feed); - int (*add_frontend) (struct dmx_demux* demux, - struct dmx_frontend* frontend); - int (*remove_frontend) (struct dmx_demux* demux, - struct dmx_frontend* frontend); - struct list_head* (*get_frontends) (struct dmx_demux* demux); - int (*connect_frontend) (struct dmx_demux* demux, - struct dmx_frontend* frontend); - int (*disconnect_frontend) (struct dmx_demux* demux); - - int (*get_pes_pids) (struct dmx_demux* demux, u16 *pids); - - int (*get_caps) (struct dmx_demux* demux, struct dmx_caps *caps); - - int (*set_source) (struct dmx_demux* demux, const dmx_source_t *src); - - int (*get_stc) (struct dmx_demux* demux, unsigned int num, - u64 *stc, unsigned int *base); -}; - -#endif /* #ifndef __DEMUX_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1272 +0,0 @@ -/* - * dmxdev.c - DVB demultiplexer device - * - * Copyright (C) 2000 Ralph Metzler & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dmxdev.h" - -static int debug; - -module_param(debug, int, 0644); -MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); - -#define dprintk if (debug) printk - -static int dvb_dmxdev_buffer_write(struct dvb_ringbuffer *buf, - const u8 *src, size_t len) -{ - ssize_t free; - - if (!len) - return 0; - if (!buf->data) - return 0; - - free = dvb_ringbuffer_free(buf); - if (len > free) { - dprintk("dmxdev: buffer overflow\n"); - return -EOVERFLOW; - } - - return dvb_ringbuffer_write(buf, src, len); -} - -static ssize_t dvb_dmxdev_buffer_read(struct dvb_ringbuffer *src, - int non_blocking, char __user *buf, - size_t count, loff_t *ppos) -{ - size_t todo; - ssize_t avail; - ssize_t ret = 0; - - if (!src->data) - return 0; - - if (src->error) { - ret = src->error; - dvb_ringbuffer_flush(src); - return ret; - } - - for (todo = count; todo > 0; todo -= ret) { - if (non_blocking && dvb_ringbuffer_empty(src)) { - ret = -EWOULDBLOCK; - break; - } - - ret = wait_event_interruptible(src->queue, - !dvb_ringbuffer_empty(src) || - (src->error != 0)); - if (ret < 0) - break; - - if (src->error) { - ret = src->error; - dvb_ringbuffer_flush(src); - break; - } - - avail = dvb_ringbuffer_avail(src); - if (avail > todo) - avail = todo; - - ret = dvb_ringbuffer_read_user(src, buf, avail); - if (ret < 0) - break; - - buf += ret; - } - - return (count - todo) ? (count - todo) : ret; -} - -static struct dmx_frontend *get_fe(struct dmx_demux *demux, int type) -{ - struct list_head *head, *pos; - - head = demux->get_frontends(demux); - if (!head) - return NULL; - list_for_each(pos, head) - if (DMX_FE_ENTRY(pos)->source == type) - return DMX_FE_ENTRY(pos); - - return NULL; -} - -static int dvb_dvr_open(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dmxdev *dmxdev = dvbdev->priv; - struct dmx_frontend *front; - - dprintk("function : %s\n", __func__); - - if (mutex_lock_interruptible(&dmxdev->mutex)) - return -ERESTARTSYS; - - if (dmxdev->exit) { - mutex_unlock(&dmxdev->mutex); - return -ENODEV; - } - - if ((file->f_flags & O_ACCMODE) == O_RDWR) { - if (!(dmxdev->capabilities & DMXDEV_CAP_DUPLEX)) { - mutex_unlock(&dmxdev->mutex); - return -EOPNOTSUPP; - } - } - - if ((file->f_flags & O_ACCMODE) == O_RDONLY) { - void *mem; - if (!dvbdev->readers) { - mutex_unlock(&dmxdev->mutex); - return -EBUSY; - } - mem = vmalloc(DVR_BUFFER_SIZE); - if (!mem) { - mutex_unlock(&dmxdev->mutex); - return -ENOMEM; - } - dvb_ringbuffer_init(&dmxdev->dvr_buffer, mem, DVR_BUFFER_SIZE); - dvbdev->readers--; - } - - if ((file->f_flags & O_ACCMODE) == O_WRONLY) { - dmxdev->dvr_orig_fe = dmxdev->demux->frontend; - - if (!dmxdev->demux->write) { - mutex_unlock(&dmxdev->mutex); - return -EOPNOTSUPP; - } - - front = get_fe(dmxdev->demux, DMX_MEMORY_FE); - - if (!front) { - mutex_unlock(&dmxdev->mutex); - return -EINVAL; - } - dmxdev->demux->disconnect_frontend(dmxdev->demux); - dmxdev->demux->connect_frontend(dmxdev->demux, front); - } - dvbdev->users++; - mutex_unlock(&dmxdev->mutex); - return 0; -} - -static int dvb_dvr_release(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dmxdev *dmxdev = dvbdev->priv; - - mutex_lock(&dmxdev->mutex); - - if ((file->f_flags & O_ACCMODE) == O_WRONLY) { - dmxdev->demux->disconnect_frontend(dmxdev->demux); - dmxdev->demux->connect_frontend(dmxdev->demux, - dmxdev->dvr_orig_fe); - } - if ((file->f_flags & O_ACCMODE) == O_RDONLY) { - dvbdev->readers++; - if (dmxdev->dvr_buffer.data) { - void *mem = dmxdev->dvr_buffer.data; - mb(); - spin_lock_irq(&dmxdev->lock); - dmxdev->dvr_buffer.data = NULL; - spin_unlock_irq(&dmxdev->lock); - vfree(mem); - } - } - /* TODO */ - dvbdev->users--; - if (dvbdev->users == 1 && dmxdev->exit == 1) { - fops_put(file->f_op); - file->f_op = NULL; - mutex_unlock(&dmxdev->mutex); - wake_up(&dvbdev->wait_queue); - } else - mutex_unlock(&dmxdev->mutex); - - return 0; -} - -static ssize_t dvb_dvr_write(struct file *file, const char __user *buf, - size_t count, loff_t *ppos) -{ - struct dvb_device *dvbdev = file->private_data; - struct dmxdev *dmxdev = dvbdev->priv; - int ret; - - if (!dmxdev->demux->write) - return -EOPNOTSUPP; - if ((file->f_flags & O_ACCMODE) != O_WRONLY) - return -EINVAL; - if (mutex_lock_interruptible(&dmxdev->mutex)) - return -ERESTARTSYS; - - if (dmxdev->exit) { - mutex_unlock(&dmxdev->mutex); - return -ENODEV; - } - ret = dmxdev->demux->write(dmxdev->demux, buf, count); - mutex_unlock(&dmxdev->mutex); - return ret; -} - -static ssize_t dvb_dvr_read(struct file *file, char __user *buf, size_t count, - loff_t *ppos) -{ - struct dvb_device *dvbdev = file->private_data; - struct dmxdev *dmxdev = dvbdev->priv; - - if (dmxdev->exit) - return -ENODEV; - - return dvb_dmxdev_buffer_read(&dmxdev->dvr_buffer, - file->f_flags & O_NONBLOCK, - buf, count, ppos); -} - -static int dvb_dvr_set_buffer_size(struct dmxdev *dmxdev, - unsigned long size) -{ - struct dvb_ringbuffer *buf = &dmxdev->dvr_buffer; - void *newmem; - void *oldmem; - - dprintk("function : %s\n", __func__); - - if (buf->size == size) - return 0; - if (!size) - return -EINVAL; - - newmem = vmalloc(size); - if (!newmem) - return -ENOMEM; - - oldmem = buf->data; - - spin_lock_irq(&dmxdev->lock); - buf->data = newmem; - buf->size = size; - - /* reset and not flush in case the buffer shrinks */ - dvb_ringbuffer_reset(buf); - spin_unlock_irq(&dmxdev->lock); - - vfree(oldmem); - - return 0; -} - -static inline void dvb_dmxdev_filter_state_set(struct dmxdev_filter - *dmxdevfilter, int state) -{ - spin_lock_irq(&dmxdevfilter->dev->lock); - dmxdevfilter->state = state; - spin_unlock_irq(&dmxdevfilter->dev->lock); -} - -static int dvb_dmxdev_set_buffer_size(struct dmxdev_filter *dmxdevfilter, - unsigned long size) -{ - struct dvb_ringbuffer *buf = &dmxdevfilter->buffer; - void *newmem; - void *oldmem; - - if (buf->size == size) - return 0; - if (!size) - return -EINVAL; - if (dmxdevfilter->state >= DMXDEV_STATE_GO) - return -EBUSY; - - newmem = vmalloc(size); - if (!newmem) - return -ENOMEM; - - oldmem = buf->data; - - spin_lock_irq(&dmxdevfilter->dev->lock); - buf->data = newmem; - buf->size = size; - - /* reset and not flush in case the buffer shrinks */ - dvb_ringbuffer_reset(buf); - spin_unlock_irq(&dmxdevfilter->dev->lock); - - vfree(oldmem); - - return 0; -} - -static void dvb_dmxdev_filter_timeout(unsigned long data) -{ - struct dmxdev_filter *dmxdevfilter = (struct dmxdev_filter *)data; - - dmxdevfilter->buffer.error = -ETIMEDOUT; - spin_lock_irq(&dmxdevfilter->dev->lock); - dmxdevfilter->state = DMXDEV_STATE_TIMEDOUT; - spin_unlock_irq(&dmxdevfilter->dev->lock); - wake_up(&dmxdevfilter->buffer.queue); -} - -static void dvb_dmxdev_filter_timer(struct dmxdev_filter *dmxdevfilter) -{ - struct dmx_sct_filter_params *para = &dmxdevfilter->params.sec; - - del_timer(&dmxdevfilter->timer); - if (para->timeout) { - dmxdevfilter->timer.function = dvb_dmxdev_filter_timeout; - dmxdevfilter->timer.data = (unsigned long)dmxdevfilter; - dmxdevfilter->timer.expires = - jiffies + 1 + (HZ / 2 + HZ * para->timeout) / 1000; - add_timer(&dmxdevfilter->timer); - } -} - -static int dvb_dmxdev_section_callback(const u8 *buffer1, size_t buffer1_len, - const u8 *buffer2, size_t buffer2_len, - struct dmx_section_filter *filter, - enum dmx_success success) -{ - struct dmxdev_filter *dmxdevfilter = filter->priv; - int ret; - - if (dmxdevfilter->buffer.error) { - wake_up(&dmxdevfilter->buffer.queue); - return 0; - } - spin_lock(&dmxdevfilter->dev->lock); - if (dmxdevfilter->state != DMXDEV_STATE_GO) { - spin_unlock(&dmxdevfilter->dev->lock); - return 0; - } - del_timer(&dmxdevfilter->timer); - dprintk("dmxdev: section callback %*ph\n", 6, buffer1); - ret = dvb_dmxdev_buffer_write(&dmxdevfilter->buffer, buffer1, - buffer1_len); - if (ret == buffer1_len) { - ret = dvb_dmxdev_buffer_write(&dmxdevfilter->buffer, buffer2, - buffer2_len); - } - if (ret < 0) - dmxdevfilter->buffer.error = ret; - if (dmxdevfilter->params.sec.flags & DMX_ONESHOT) - dmxdevfilter->state = DMXDEV_STATE_DONE; - spin_unlock(&dmxdevfilter->dev->lock); - wake_up(&dmxdevfilter->buffer.queue); - return 0; -} - -static int dvb_dmxdev_ts_callback(const u8 *buffer1, size_t buffer1_len, - const u8 *buffer2, size_t buffer2_len, - struct dmx_ts_feed *feed, - enum dmx_success success) -{ - struct dmxdev_filter *dmxdevfilter = feed->priv; - struct dvb_ringbuffer *buffer; - int ret; - - spin_lock(&dmxdevfilter->dev->lock); - if (dmxdevfilter->params.pes.output == DMX_OUT_DECODER) { - spin_unlock(&dmxdevfilter->dev->lock); - return 0; - } - - if (dmxdevfilter->params.pes.output == DMX_OUT_TAP - || dmxdevfilter->params.pes.output == DMX_OUT_TSDEMUX_TAP) - buffer = &dmxdevfilter->buffer; - else - buffer = &dmxdevfilter->dev->dvr_buffer; - if (buffer->error) { - spin_unlock(&dmxdevfilter->dev->lock); - wake_up(&buffer->queue); - return 0; - } - ret = dvb_dmxdev_buffer_write(buffer, buffer1, buffer1_len); - if (ret == buffer1_len) - ret = dvb_dmxdev_buffer_write(buffer, buffer2, buffer2_len); - if (ret < 0) - buffer->error = ret; - spin_unlock(&dmxdevfilter->dev->lock); - wake_up(&buffer->queue); - return 0; -} - -/* stop feed but only mark the specified filter as stopped (state set) */ -static int dvb_dmxdev_feed_stop(struct dmxdev_filter *dmxdevfilter) -{ - struct dmxdev_feed *feed; - - dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET); - - switch (dmxdevfilter->type) { - case DMXDEV_TYPE_SEC: - del_timer(&dmxdevfilter->timer); - dmxdevfilter->feed.sec->stop_filtering(dmxdevfilter->feed.sec); - break; - case DMXDEV_TYPE_PES: - list_for_each_entry(feed, &dmxdevfilter->feed.ts, next) - feed->ts->stop_filtering(feed->ts); - break; - default: - return -EINVAL; - } - return 0; -} - -/* start feed associated with the specified filter */ -static int dvb_dmxdev_feed_start(struct dmxdev_filter *filter) -{ - struct dmxdev_feed *feed; - int ret; - - dvb_dmxdev_filter_state_set(filter, DMXDEV_STATE_GO); - - switch (filter->type) { - case DMXDEV_TYPE_SEC: - return filter->feed.sec->start_filtering(filter->feed.sec); - case DMXDEV_TYPE_PES: - list_for_each_entry(feed, &filter->feed.ts, next) { - ret = feed->ts->start_filtering(feed->ts); - if (ret < 0) { - dvb_dmxdev_feed_stop(filter); - return ret; - } - } - break; - default: - return -EINVAL; - } - - return 0; -} - -/* restart section feed if it has filters left associated with it, - otherwise release the feed */ -static int dvb_dmxdev_feed_restart(struct dmxdev_filter *filter) -{ - int i; - struct dmxdev *dmxdev = filter->dev; - u16 pid = filter->params.sec.pid; - - for (i = 0; i < dmxdev->filternum; i++) - if (dmxdev->filter[i].state >= DMXDEV_STATE_GO && - dmxdev->filter[i].type == DMXDEV_TYPE_SEC && - dmxdev->filter[i].params.sec.pid == pid) { - dvb_dmxdev_feed_start(&dmxdev->filter[i]); - return 0; - } - - filter->dev->demux->release_section_feed(dmxdev->demux, - filter->feed.sec); - - return 0; -} - -static int dvb_dmxdev_filter_stop(struct dmxdev_filter *dmxdevfilter) -{ - struct dmxdev_feed *feed; - struct dmx_demux *demux; - - if (dmxdevfilter->state < DMXDEV_STATE_GO) - return 0; - - switch (dmxdevfilter->type) { - case DMXDEV_TYPE_SEC: - if (!dmxdevfilter->feed.sec) - break; - dvb_dmxdev_feed_stop(dmxdevfilter); - if (dmxdevfilter->filter.sec) - dmxdevfilter->feed.sec-> - release_filter(dmxdevfilter->feed.sec, - dmxdevfilter->filter.sec); - dvb_dmxdev_feed_restart(dmxdevfilter); - dmxdevfilter->feed.sec = NULL; - break; - case DMXDEV_TYPE_PES: - dvb_dmxdev_feed_stop(dmxdevfilter); - demux = dmxdevfilter->dev->demux; - list_for_each_entry(feed, &dmxdevfilter->feed.ts, next) { - demux->release_ts_feed(demux, feed->ts); - feed->ts = NULL; - } - break; - default: - if (dmxdevfilter->state == DMXDEV_STATE_ALLOCATED) - return 0; - return -EINVAL; - } - - dvb_ringbuffer_flush(&dmxdevfilter->buffer); - return 0; -} - -static void dvb_dmxdev_delete_pids(struct dmxdev_filter *dmxdevfilter) -{ - struct dmxdev_feed *feed, *tmp; - - /* delete all PIDs */ - list_for_each_entry_safe(feed, tmp, &dmxdevfilter->feed.ts, next) { - list_del(&feed->next); - kfree(feed); - } - - BUG_ON(!list_empty(&dmxdevfilter->feed.ts)); -} - -static inline int dvb_dmxdev_filter_reset(struct dmxdev_filter *dmxdevfilter) -{ - if (dmxdevfilter->state < DMXDEV_STATE_SET) - return 0; - - if (dmxdevfilter->type == DMXDEV_TYPE_PES) - dvb_dmxdev_delete_pids(dmxdevfilter); - - dmxdevfilter->type = DMXDEV_TYPE_NONE; - dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_ALLOCATED); - return 0; -} - -static int dvb_dmxdev_start_feed(struct dmxdev *dmxdev, - struct dmxdev_filter *filter, - struct dmxdev_feed *feed) -{ - struct timespec timeout = { 0 }; - struct dmx_pes_filter_params *para = &filter->params.pes; - dmx_output_t otype; - int ret; - int ts_type; - enum dmx_ts_pes ts_pes; - struct dmx_ts_feed *tsfeed; - - feed->ts = NULL; - otype = para->output; - - ts_pes = para->pes_type; - - if (ts_pes < DMX_PES_OTHER) - ts_type = TS_DECODER; - else - ts_type = 0; - - if (otype == DMX_OUT_TS_TAP) - ts_type |= TS_PACKET; - else if (otype == DMX_OUT_TSDEMUX_TAP) - ts_type |= TS_PACKET | TS_DEMUX; - else if (otype == DMX_OUT_TAP) - ts_type |= TS_PACKET | TS_DEMUX | TS_PAYLOAD_ONLY; - - ret = dmxdev->demux->allocate_ts_feed(dmxdev->demux, &feed->ts, - dvb_dmxdev_ts_callback); - if (ret < 0) - return ret; - - tsfeed = feed->ts; - tsfeed->priv = filter; - - ret = tsfeed->set(tsfeed, feed->pid, ts_type, ts_pes, 32768, timeout); - if (ret < 0) { - dmxdev->demux->release_ts_feed(dmxdev->demux, tsfeed); - return ret; - } - - ret = tsfeed->start_filtering(tsfeed); - if (ret < 0) { - dmxdev->demux->release_ts_feed(dmxdev->demux, tsfeed); - return ret; - } - - return 0; -} - -static int dvb_dmxdev_filter_start(struct dmxdev_filter *filter) -{ - struct dmxdev *dmxdev = filter->dev; - struct dmxdev_feed *feed; - void *mem; - int ret, i; - - if (filter->state < DMXDEV_STATE_SET) - return -EINVAL; - - if (filter->state >= DMXDEV_STATE_GO) - dvb_dmxdev_filter_stop(filter); - - if (!filter->buffer.data) { - mem = vmalloc(filter->buffer.size); - if (!mem) - return -ENOMEM; - spin_lock_irq(&filter->dev->lock); - filter->buffer.data = mem; - spin_unlock_irq(&filter->dev->lock); - } - - dvb_ringbuffer_flush(&filter->buffer); - - switch (filter->type) { - case DMXDEV_TYPE_SEC: - { - struct dmx_sct_filter_params *para = &filter->params.sec; - struct dmx_section_filter **secfilter = &filter->filter.sec; - struct dmx_section_feed **secfeed = &filter->feed.sec; - - *secfilter = NULL; - *secfeed = NULL; - - - /* find active filter/feed with same PID */ - for (i = 0; i < dmxdev->filternum; i++) { - if (dmxdev->filter[i].state >= DMXDEV_STATE_GO && - dmxdev->filter[i].type == DMXDEV_TYPE_SEC && - dmxdev->filter[i].params.sec.pid == para->pid) { - *secfeed = dmxdev->filter[i].feed.sec; - break; - } - } - - /* if no feed found, try to allocate new one */ - if (!*secfeed) { - ret = dmxdev->demux->allocate_section_feed(dmxdev->demux, - secfeed, - dvb_dmxdev_section_callback); - if (ret < 0) { - printk("DVB (%s): could not alloc feed\n", - __func__); - return ret; - } - - ret = (*secfeed)->set(*secfeed, para->pid, 32768, - (para->flags & DMX_CHECK_CRC) ? 1 : 0); - if (ret < 0) { - printk("DVB (%s): could not set feed\n", - __func__); - dvb_dmxdev_feed_restart(filter); - return ret; - } - } else { - dvb_dmxdev_feed_stop(filter); - } - - ret = (*secfeed)->allocate_filter(*secfeed, secfilter); - if (ret < 0) { - dvb_dmxdev_feed_restart(filter); - filter->feed.sec->start_filtering(*secfeed); - dprintk("could not get filter\n"); - return ret; - } - - (*secfilter)->priv = filter; - - memcpy(&((*secfilter)->filter_value[3]), - &(para->filter.filter[1]), DMX_FILTER_SIZE - 1); - memcpy(&(*secfilter)->filter_mask[3], - ¶->filter.mask[1], DMX_FILTER_SIZE - 1); - memcpy(&(*secfilter)->filter_mode[3], - ¶->filter.mode[1], DMX_FILTER_SIZE - 1); - - (*secfilter)->filter_value[0] = para->filter.filter[0]; - (*secfilter)->filter_mask[0] = para->filter.mask[0]; - (*secfilter)->filter_mode[0] = para->filter.mode[0]; - (*secfilter)->filter_mask[1] = 0; - (*secfilter)->filter_mask[2] = 0; - - filter->todo = 0; - - ret = filter->feed.sec->start_filtering(filter->feed.sec); - if (ret < 0) - return ret; - - dvb_dmxdev_filter_timer(filter); - break; - } - case DMXDEV_TYPE_PES: - list_for_each_entry(feed, &filter->feed.ts, next) { - ret = dvb_dmxdev_start_feed(dmxdev, filter, feed); - if (ret < 0) { - dvb_dmxdev_filter_stop(filter); - return ret; - } - } - break; - default: - return -EINVAL; - } - - dvb_dmxdev_filter_state_set(filter, DMXDEV_STATE_GO); - return 0; -} - -static int dvb_demux_open(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dmxdev *dmxdev = dvbdev->priv; - int i; - struct dmxdev_filter *dmxdevfilter; - - if (!dmxdev->filter) - return -EINVAL; - - if (mutex_lock_interruptible(&dmxdev->mutex)) - return -ERESTARTSYS; - - for (i = 0; i < dmxdev->filternum; i++) - if (dmxdev->filter[i].state == DMXDEV_STATE_FREE) - break; - - if (i == dmxdev->filternum) { - mutex_unlock(&dmxdev->mutex); - return -EMFILE; - } - - dmxdevfilter = &dmxdev->filter[i]; - mutex_init(&dmxdevfilter->mutex); - file->private_data = dmxdevfilter; - - dvb_ringbuffer_init(&dmxdevfilter->buffer, NULL, 8192); - dmxdevfilter->type = DMXDEV_TYPE_NONE; - dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_ALLOCATED); - init_timer(&dmxdevfilter->timer); - - dvbdev->users++; - - mutex_unlock(&dmxdev->mutex); - return 0; -} - -static int dvb_dmxdev_filter_free(struct dmxdev *dmxdev, - struct dmxdev_filter *dmxdevfilter) -{ - mutex_lock(&dmxdev->mutex); - mutex_lock(&dmxdevfilter->mutex); - - dvb_dmxdev_filter_stop(dmxdevfilter); - dvb_dmxdev_filter_reset(dmxdevfilter); - - if (dmxdevfilter->buffer.data) { - void *mem = dmxdevfilter->buffer.data; - - spin_lock_irq(&dmxdev->lock); - dmxdevfilter->buffer.data = NULL; - spin_unlock_irq(&dmxdev->lock); - vfree(mem); - } - - dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_FREE); - wake_up(&dmxdevfilter->buffer.queue); - mutex_unlock(&dmxdevfilter->mutex); - mutex_unlock(&dmxdev->mutex); - return 0; -} - -static inline void invert_mode(dmx_filter_t *filter) -{ - int i; - - for (i = 0; i < DMX_FILTER_SIZE; i++) - filter->mode[i] ^= 0xff; -} - -static int dvb_dmxdev_add_pid(struct dmxdev *dmxdev, - struct dmxdev_filter *filter, u16 pid) -{ - struct dmxdev_feed *feed; - - if ((filter->type != DMXDEV_TYPE_PES) || - (filter->state < DMXDEV_STATE_SET)) - return -EINVAL; - - /* only TS packet filters may have multiple PIDs */ - if ((filter->params.pes.output != DMX_OUT_TSDEMUX_TAP) && - (!list_empty(&filter->feed.ts))) - return -EINVAL; - - feed = kzalloc(sizeof(struct dmxdev_feed), GFP_KERNEL); - if (feed == NULL) - return -ENOMEM; - - feed->pid = pid; - list_add(&feed->next, &filter->feed.ts); - - if (filter->state >= DMXDEV_STATE_GO) - return dvb_dmxdev_start_feed(dmxdev, filter, feed); - - return 0; -} - -static int dvb_dmxdev_remove_pid(struct dmxdev *dmxdev, - struct dmxdev_filter *filter, u16 pid) -{ - struct dmxdev_feed *feed, *tmp; - - if ((filter->type != DMXDEV_TYPE_PES) || - (filter->state < DMXDEV_STATE_SET)) - return -EINVAL; - - list_for_each_entry_safe(feed, tmp, &filter->feed.ts, next) { - if ((feed->pid == pid) && (feed->ts != NULL)) { - feed->ts->stop_filtering(feed->ts); - filter->dev->demux->release_ts_feed(filter->dev->demux, - feed->ts); - list_del(&feed->next); - kfree(feed); - } - } - - return 0; -} - -static int dvb_dmxdev_filter_set(struct dmxdev *dmxdev, - struct dmxdev_filter *dmxdevfilter, - struct dmx_sct_filter_params *params) -{ - dprintk("function : %s, PID=0x%04x, flags=%02x, timeout=%d\n", - __func__, params->pid, params->flags, params->timeout); - - dvb_dmxdev_filter_stop(dmxdevfilter); - - dmxdevfilter->type = DMXDEV_TYPE_SEC; - memcpy(&dmxdevfilter->params.sec, - params, sizeof(struct dmx_sct_filter_params)); - invert_mode(&dmxdevfilter->params.sec.filter); - dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET); - - if (params->flags & DMX_IMMEDIATE_START) - return dvb_dmxdev_filter_start(dmxdevfilter); - - return 0; -} - -static int dvb_dmxdev_pes_filter_set(struct dmxdev *dmxdev, - struct dmxdev_filter *dmxdevfilter, - struct dmx_pes_filter_params *params) -{ - int ret; - - dvb_dmxdev_filter_stop(dmxdevfilter); - dvb_dmxdev_filter_reset(dmxdevfilter); - - if ((unsigned)params->pes_type > DMX_PES_OTHER) - return -EINVAL; - - dmxdevfilter->type = DMXDEV_TYPE_PES; - memcpy(&dmxdevfilter->params, params, - sizeof(struct dmx_pes_filter_params)); - INIT_LIST_HEAD(&dmxdevfilter->feed.ts); - - dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET); - - ret = dvb_dmxdev_add_pid(dmxdev, dmxdevfilter, - dmxdevfilter->params.pes.pid); - if (ret < 0) - return ret; - - if (params->flags & DMX_IMMEDIATE_START) - return dvb_dmxdev_filter_start(dmxdevfilter); - - return 0; -} - -static ssize_t dvb_dmxdev_read_sec(struct dmxdev_filter *dfil, - struct file *file, char __user *buf, - size_t count, loff_t *ppos) -{ - int result, hcount; - int done = 0; - - if (dfil->todo <= 0) { - hcount = 3 + dfil->todo; - if (hcount > count) - hcount = count; - result = dvb_dmxdev_buffer_read(&dfil->buffer, - file->f_flags & O_NONBLOCK, - buf, hcount, ppos); - if (result < 0) { - dfil->todo = 0; - return result; - } - if (copy_from_user(dfil->secheader - dfil->todo, buf, result)) - return -EFAULT; - buf += result; - done = result; - count -= result; - dfil->todo -= result; - if (dfil->todo > -3) - return done; - dfil->todo = ((dfil->secheader[1] << 8) | dfil->secheader[2]) & 0xfff; - if (!count) - return done; - } - if (count > dfil->todo) - count = dfil->todo; - result = dvb_dmxdev_buffer_read(&dfil->buffer, - file->f_flags & O_NONBLOCK, - buf, count, ppos); - if (result < 0) - return result; - dfil->todo -= result; - return (result + done); -} - -static ssize_t -dvb_demux_read(struct file *file, char __user *buf, size_t count, - loff_t *ppos) -{ - struct dmxdev_filter *dmxdevfilter = file->private_data; - int ret; - - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) - return -ERESTARTSYS; - - if (dmxdevfilter->type == DMXDEV_TYPE_SEC) - ret = dvb_dmxdev_read_sec(dmxdevfilter, file, buf, count, ppos); - else - ret = dvb_dmxdev_buffer_read(&dmxdevfilter->buffer, - file->f_flags & O_NONBLOCK, - buf, count, ppos); - - mutex_unlock(&dmxdevfilter->mutex); - return ret; -} - -static int dvb_demux_do_ioctl(struct file *file, - unsigned int cmd, void *parg) -{ - struct dmxdev_filter *dmxdevfilter = file->private_data; - struct dmxdev *dmxdev = dmxdevfilter->dev; - unsigned long arg = (unsigned long)parg; - int ret = 0; - - if (mutex_lock_interruptible(&dmxdev->mutex)) - return -ERESTARTSYS; - - switch (cmd) { - case DMX_START: - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { - mutex_unlock(&dmxdev->mutex); - return -ERESTARTSYS; - } - if (dmxdevfilter->state < DMXDEV_STATE_SET) - ret = -EINVAL; - else - ret = dvb_dmxdev_filter_start(dmxdevfilter); - mutex_unlock(&dmxdevfilter->mutex); - break; - - case DMX_STOP: - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { - mutex_unlock(&dmxdev->mutex); - return -ERESTARTSYS; - } - ret = dvb_dmxdev_filter_stop(dmxdevfilter); - mutex_unlock(&dmxdevfilter->mutex); - break; - - case DMX_SET_FILTER: - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { - mutex_unlock(&dmxdev->mutex); - return -ERESTARTSYS; - } - ret = dvb_dmxdev_filter_set(dmxdev, dmxdevfilter, parg); - mutex_unlock(&dmxdevfilter->mutex); - break; - - case DMX_SET_PES_FILTER: - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { - mutex_unlock(&dmxdev->mutex); - return -ERESTARTSYS; - } - ret = dvb_dmxdev_pes_filter_set(dmxdev, dmxdevfilter, parg); - mutex_unlock(&dmxdevfilter->mutex); - break; - - case DMX_SET_BUFFER_SIZE: - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { - mutex_unlock(&dmxdev->mutex); - return -ERESTARTSYS; - } - ret = dvb_dmxdev_set_buffer_size(dmxdevfilter, arg); - mutex_unlock(&dmxdevfilter->mutex); - break; - - case DMX_GET_PES_PIDS: - if (!dmxdev->demux->get_pes_pids) { - ret = -EINVAL; - break; - } - dmxdev->demux->get_pes_pids(dmxdev->demux, parg); - break; - - case DMX_GET_CAPS: - if (!dmxdev->demux->get_caps) { - ret = -EINVAL; - break; - } - ret = dmxdev->demux->get_caps(dmxdev->demux, parg); - break; - - case DMX_SET_SOURCE: - if (!dmxdev->demux->set_source) { - ret = -EINVAL; - break; - } - ret = dmxdev->demux->set_source(dmxdev->demux, parg); - break; - - case DMX_GET_STC: - if (!dmxdev->demux->get_stc) { - ret = -EINVAL; - break; - } - ret = dmxdev->demux->get_stc(dmxdev->demux, - ((struct dmx_stc *)parg)->num, - &((struct dmx_stc *)parg)->stc, - &((struct dmx_stc *)parg)->base); - break; - - case DMX_ADD_PID: - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { - ret = -ERESTARTSYS; - break; - } - ret = dvb_dmxdev_add_pid(dmxdev, dmxdevfilter, *(u16 *)parg); - mutex_unlock(&dmxdevfilter->mutex); - break; - - case DMX_REMOVE_PID: - if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { - ret = -ERESTARTSYS; - break; - } - ret = dvb_dmxdev_remove_pid(dmxdev, dmxdevfilter, *(u16 *)parg); - mutex_unlock(&dmxdevfilter->mutex); - break; - - default: - ret = -EINVAL; - break; - } - mutex_unlock(&dmxdev->mutex); - return ret; -} - -static long dvb_demux_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - return dvb_usercopy(file, cmd, arg, dvb_demux_do_ioctl); -} - -static unsigned int dvb_demux_poll(struct file *file, poll_table *wait) -{ - struct dmxdev_filter *dmxdevfilter = file->private_data; - unsigned int mask = 0; - - if (!dmxdevfilter) - return -EINVAL; - - poll_wait(file, &dmxdevfilter->buffer.queue, wait); - - if (dmxdevfilter->state != DMXDEV_STATE_GO && - dmxdevfilter->state != DMXDEV_STATE_DONE && - dmxdevfilter->state != DMXDEV_STATE_TIMEDOUT) - return 0; - - if (dmxdevfilter->buffer.error) - mask |= (POLLIN | POLLRDNORM | POLLPRI | POLLERR); - - if (!dvb_ringbuffer_empty(&dmxdevfilter->buffer)) - mask |= (POLLIN | POLLRDNORM | POLLPRI); - - return mask; -} - -static int dvb_demux_release(struct inode *inode, struct file *file) -{ - struct dmxdev_filter *dmxdevfilter = file->private_data; - struct dmxdev *dmxdev = dmxdevfilter->dev; - - int ret; - - ret = dvb_dmxdev_filter_free(dmxdev, dmxdevfilter); - - mutex_lock(&dmxdev->mutex); - dmxdev->dvbdev->users--; - if(dmxdev->dvbdev->users==1 && dmxdev->exit==1) { - fops_put(file->f_op); - file->f_op = NULL; - mutex_unlock(&dmxdev->mutex); - wake_up(&dmxdev->dvbdev->wait_queue); - } else - mutex_unlock(&dmxdev->mutex); - - return ret; -} - -static const struct file_operations dvb_demux_fops = { - .owner = THIS_MODULE, - .read = dvb_demux_read, - .unlocked_ioctl = dvb_demux_ioctl, - .open = dvb_demux_open, - .release = dvb_demux_release, - .poll = dvb_demux_poll, - .llseek = default_llseek, -}; - -static struct dvb_device dvbdev_demux = { - .priv = NULL, - .users = 1, - .writers = 1, - .fops = &dvb_demux_fops -}; - -static int dvb_dvr_do_ioctl(struct file *file, - unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct dmxdev *dmxdev = dvbdev->priv; - unsigned long arg = (unsigned long)parg; - int ret; - - if (mutex_lock_interruptible(&dmxdev->mutex)) - return -ERESTARTSYS; - - switch (cmd) { - case DMX_SET_BUFFER_SIZE: - ret = dvb_dvr_set_buffer_size(dmxdev, arg); - break; - - default: - ret = -EINVAL; - break; - } - mutex_unlock(&dmxdev->mutex); - return ret; -} - -static long dvb_dvr_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - return dvb_usercopy(file, cmd, arg, dvb_dvr_do_ioctl); -} - -static unsigned int dvb_dvr_poll(struct file *file, poll_table *wait) -{ - struct dvb_device *dvbdev = file->private_data; - struct dmxdev *dmxdev = dvbdev->priv; - unsigned int mask = 0; - - dprintk("function : %s\n", __func__); - - poll_wait(file, &dmxdev->dvr_buffer.queue, wait); - - if ((file->f_flags & O_ACCMODE) == O_RDONLY) { - if (dmxdev->dvr_buffer.error) - mask |= (POLLIN | POLLRDNORM | POLLPRI | POLLERR); - - if (!dvb_ringbuffer_empty(&dmxdev->dvr_buffer)) - mask |= (POLLIN | POLLRDNORM | POLLPRI); - } else - mask |= (POLLOUT | POLLWRNORM | POLLPRI); - - return mask; -} - -static const struct file_operations dvb_dvr_fops = { - .owner = THIS_MODULE, - .read = dvb_dvr_read, - .write = dvb_dvr_write, - .unlocked_ioctl = dvb_dvr_ioctl, - .open = dvb_dvr_open, - .release = dvb_dvr_release, - .poll = dvb_dvr_poll, - .llseek = default_llseek, -}; - -static struct dvb_device dvbdev_dvr = { - .priv = NULL, - .readers = 1, - .users = 1, - .fops = &dvb_dvr_fops -}; - -int dvb_dmxdev_init(struct dmxdev *dmxdev, struct dvb_adapter *dvb_adapter) -{ - int i; - - if (dmxdev->demux->open(dmxdev->demux) < 0) - return -EUSERS; - - dmxdev->filter = vmalloc(dmxdev->filternum * sizeof(struct dmxdev_filter)); - if (!dmxdev->filter) - return -ENOMEM; - - mutex_init(&dmxdev->mutex); - spin_lock_init(&dmxdev->lock); - for (i = 0; i < dmxdev->filternum; i++) { - dmxdev->filter[i].dev = dmxdev; - dmxdev->filter[i].buffer.data = NULL; - dvb_dmxdev_filter_state_set(&dmxdev->filter[i], - DMXDEV_STATE_FREE); - } - - dvb_register_device(dvb_adapter, &dmxdev->dvbdev, &dvbdev_demux, dmxdev, - DVB_DEVICE_DEMUX); - dvb_register_device(dvb_adapter, &dmxdev->dvr_dvbdev, &dvbdev_dvr, - dmxdev, DVB_DEVICE_DVR); - - dvb_ringbuffer_init(&dmxdev->dvr_buffer, NULL, 8192); - - return 0; -} - -EXPORT_SYMBOL(dvb_dmxdev_init); - -void dvb_dmxdev_release(struct dmxdev *dmxdev) -{ - dmxdev->exit=1; - if (dmxdev->dvbdev->users > 1) { - wait_event(dmxdev->dvbdev->wait_queue, - dmxdev->dvbdev->users==1); - } - if (dmxdev->dvr_dvbdev->users > 1) { - wait_event(dmxdev->dvr_dvbdev->wait_queue, - dmxdev->dvr_dvbdev->users==1); - } - - dvb_unregister_device(dmxdev->dvbdev); - dvb_unregister_device(dmxdev->dvr_dvbdev); - - vfree(dmxdev->filter); - dmxdev->filter = NULL; - dmxdev->demux->close(dmxdev->demux); -} - -EXPORT_SYMBOL(dvb_dmxdev_release); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dmxdev.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,119 +0,0 @@ -/* - * dmxdev.h - * - * Copyright (C) 2000 Ralph Metzler & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DMXDEV_H_ -#define _DMXDEV_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "dvbdev.h" -#include "demux.h" -#include "dvb_ringbuffer.h" - -enum dmxdev_type { - DMXDEV_TYPE_NONE, - DMXDEV_TYPE_SEC, - DMXDEV_TYPE_PES, -}; - -enum dmxdev_state { - DMXDEV_STATE_FREE, - DMXDEV_STATE_ALLOCATED, - DMXDEV_STATE_SET, - DMXDEV_STATE_GO, - DMXDEV_STATE_DONE, - DMXDEV_STATE_TIMEDOUT -}; - -struct dmxdev_feed { - u16 pid; - struct dmx_ts_feed *ts; - struct list_head next; -}; - -struct dmxdev_filter { - union { - struct dmx_section_filter *sec; - } filter; - - union { - /* list of TS and PES feeds (struct dmxdev_feed) */ - struct list_head ts; - struct dmx_section_feed *sec; - } feed; - - union { - struct dmx_sct_filter_params sec; - struct dmx_pes_filter_params pes; - } params; - - enum dmxdev_type type; - enum dmxdev_state state; - struct dmxdev *dev; - struct dvb_ringbuffer buffer; - - struct mutex mutex; - - /* only for sections */ - struct timer_list timer; - int todo; - u8 secheader[3]; -}; - - -struct dmxdev { - struct dvb_device *dvbdev; - struct dvb_device *dvr_dvbdev; - - struct dmxdev_filter *filter; - struct dmx_demux *demux; - - int filternum; - int capabilities; - - unsigned int exit:1; -#define DMXDEV_CAP_DUPLEX 1 - struct dmx_frontend *dvr_orig_fe; - - struct dvb_ringbuffer dvr_buffer; -#define DVR_BUFFER_SIZE (10*188*1024) - - struct mutex mutex; - spinlock_t lock; -}; - - -int dvb_dmxdev_init(struct dmxdev *dmxdev, struct dvb_adapter *); -void dvb_dmxdev_release(struct dmxdev *dmxdev); - -#endif /* _DMXDEV_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1803 +0,0 @@ -/* - * dvb_ca.c: generic DVB functions for EN50221 CAM interfaces - * - * Copyright (C) 2004 Andrew de Quincey - * - * Parts of this file were based on sources as follows: - * - * Copyright (C) 2003 Ralph Metzler - * - * based on code: - * - * Copyright (C) 1999-2002 Ralph Metzler - * & Marcus Metzler for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_ca_en50221.h" -#include "dvb_ringbuffer.h" - -static int dvb_ca_en50221_debug; - -module_param_named(cam_debug, dvb_ca_en50221_debug, int, 0644); -MODULE_PARM_DESC(cam_debug, "enable verbose debug messages"); - -#define dprintk if (dvb_ca_en50221_debug) printk - -#define INIT_TIMEOUT_SECS 10 - -#define HOST_LINK_BUF_SIZE 0x200 - -#define RX_BUFFER_SIZE 65535 - -#define MAX_RX_PACKETS_PER_ITERATION 10 - -#define CTRLIF_DATA 0 -#define CTRLIF_COMMAND 1 -#define CTRLIF_STATUS 1 -#define CTRLIF_SIZE_LOW 2 -#define CTRLIF_SIZE_HIGH 3 - -#define CMDREG_HC 1 /* Host control */ -#define CMDREG_SW 2 /* Size write */ -#define CMDREG_SR 4 /* Size read */ -#define CMDREG_RS 8 /* Reset interface */ -#define CMDREG_FRIE 0x40 /* Enable FR interrupt */ -#define CMDREG_DAIE 0x80 /* Enable DA interrupt */ -#define IRQEN (CMDREG_DAIE) - -#define STATUSREG_RE 1 /* read error */ -#define STATUSREG_WE 2 /* write error */ -#define STATUSREG_FR 0x40 /* module free */ -#define STATUSREG_DA 0x80 /* data available */ -#define STATUSREG_TXERR (STATUSREG_RE|STATUSREG_WE) /* general transfer error */ - - -#define DVB_CA_SLOTSTATE_NONE 0 -#define DVB_CA_SLOTSTATE_UNINITIALISED 1 -#define DVB_CA_SLOTSTATE_RUNNING 2 -#define DVB_CA_SLOTSTATE_INVALID 3 -#define DVB_CA_SLOTSTATE_WAITREADY 4 -#define DVB_CA_SLOTSTATE_VALIDATE 5 -#define DVB_CA_SLOTSTATE_WAITFR 6 -#define DVB_CA_SLOTSTATE_LINKINIT 7 - - -/* Information on a CA slot */ -struct dvb_ca_slot { - - /* current state of the CAM */ - int slot_state; - - /* mutex used for serializing access to one CI slot */ - struct mutex slot_lock; - - /* Number of CAMCHANGES that have occurred since last processing */ - atomic_t camchange_count; - - /* Type of last CAMCHANGE */ - int camchange_type; - - /* base address of CAM config */ - u32 config_base; - - /* value to write into Config Control register */ - u8 config_option; - - /* if 1, the CAM supports DA IRQs */ - u8 da_irq_supported:1; - - /* size of the buffer to use when talking to the CAM */ - int link_buf_size; - - /* buffer for incoming packets */ - struct dvb_ringbuffer rx_buffer; - - /* timer used during various states of the slot */ - unsigned long timeout; -}; - -/* Private CA-interface information */ -struct dvb_ca_private { - - /* pointer back to the public data structure */ - struct dvb_ca_en50221 *pub; - - /* the DVB device */ - struct dvb_device *dvbdev; - - /* Flags describing the interface (DVB_CA_FLAG_*) */ - u32 flags; - - /* number of slots supported by this CA interface */ - unsigned int slot_count; - - /* information on each slot */ - struct dvb_ca_slot *slot_info; - - /* wait queues for read() and write() operations */ - wait_queue_head_t wait_queue; - - /* PID of the monitoring thread */ - struct task_struct *thread; - - /* Flag indicating if the CA device is open */ - unsigned int open:1; - - /* Flag indicating the thread should wake up now */ - unsigned int wakeup:1; - - /* Delay the main thread should use */ - unsigned long delay; - - /* Slot to start looking for data to read from in the next user-space read operation */ - int next_read_slot; - - /* mutex serializing ioctls */ - struct mutex ioctl_mutex; -}; - -static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca); -static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 * ebuf, int ecount); -static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * ebuf, int ecount); - - -/** - * Safely find needle in haystack. - * - * @param haystack Buffer to look in. - * @param hlen Number of bytes in haystack. - * @param needle Buffer to find. - * @param nlen Number of bytes in needle. - * @return Pointer into haystack needle was found at, or NULL if not found. - */ -static char *findstr(char * haystack, int hlen, char * needle, int nlen) -{ - int i; - - if (hlen < nlen) - return NULL; - - for (i = 0; i <= hlen - nlen; i++) { - if (!strncmp(haystack + i, needle, nlen)) - return haystack + i; - } - - return NULL; -} - - - -/* ******************************************************************************** */ -/* EN50221 physical interface functions */ - - -/** - * Check CAM status. - */ -static int dvb_ca_en50221_check_camstatus(struct dvb_ca_private *ca, int slot) -{ - int slot_status; - int cam_present_now; - int cam_changed; - - /* IRQ mode */ - if (ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE) { - return (atomic_read(&ca->slot_info[slot].camchange_count) != 0); - } - - /* poll mode */ - slot_status = ca->pub->poll_slot_status(ca->pub, slot, ca->open); - - cam_present_now = (slot_status & DVB_CA_EN50221_POLL_CAM_PRESENT) ? 1 : 0; - cam_changed = (slot_status & DVB_CA_EN50221_POLL_CAM_CHANGED) ? 1 : 0; - if (!cam_changed) { - int cam_present_old = (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_NONE); - cam_changed = (cam_present_now != cam_present_old); - } - - if (cam_changed) { - if (!cam_present_now) { - ca->slot_info[slot].camchange_type = DVB_CA_EN50221_CAMCHANGE_REMOVED; - } else { - ca->slot_info[slot].camchange_type = DVB_CA_EN50221_CAMCHANGE_INSERTED; - } - atomic_set(&ca->slot_info[slot].camchange_count, 1); - } else { - if ((ca->slot_info[slot].slot_state == DVB_CA_SLOTSTATE_WAITREADY) && - (slot_status & DVB_CA_EN50221_POLL_CAM_READY)) { - // move to validate state if reset is completed - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_VALIDATE; - } - } - - return cam_changed; -} - - -/** - * Wait for flags to become set on the STATUS register on a CAM interface, - * checking for errors and timeout. - * - * @param ca CA instance. - * @param slot Slot on interface. - * @param waitfor Flags to wait for. - * @param timeout_ms Timeout in milliseconds. - * - * @return 0 on success, nonzero on error. - */ -static int dvb_ca_en50221_wait_if_status(struct dvb_ca_private *ca, int slot, - u8 waitfor, int timeout_hz) -{ - unsigned long timeout; - unsigned long start; - - dprintk("%s\n", __func__); - - /* loop until timeout elapsed */ - start = jiffies; - timeout = jiffies + timeout_hz; - while (1) { - /* read the status and check for error */ - int res = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS); - if (res < 0) - return -EIO; - - /* if we got the flags, it was successful! */ - if (res & waitfor) { - dprintk("%s succeeded timeout:%lu\n", __func__, jiffies - start); - return 0; - } - - /* check for timeout */ - if (time_after(jiffies, timeout)) { - break; - } - - /* wait for a bit */ - msleep(1); - } - - dprintk("%s failed timeout:%lu\n", __func__, jiffies - start); - - /* if we get here, we've timed out */ - return -ETIMEDOUT; -} - - -/** - * Initialise the link layer connection to a CAM. - * - * @param ca CA instance. - * @param slot Slot id. - * - * @return 0 on success, nonzero on failure. - */ -static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot) -{ - int ret; - int buf_size; - u8 buf[2]; - - dprintk("%s\n", __func__); - - /* we'll be determining these during this function */ - ca->slot_info[slot].da_irq_supported = 0; - - /* set the host link buffer size temporarily. it will be overwritten with the - * real negotiated size later. */ - ca->slot_info[slot].link_buf_size = 2; - - /* read the buffer size from the CAM */ - if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN | CMDREG_SR)) != 0) - return ret; - if ((ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_DA, HZ / 10)) != 0) - return ret; - if ((ret = dvb_ca_en50221_read_data(ca, slot, buf, 2)) != 2) - return -EIO; - if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN)) != 0) - return ret; - - /* store it, and choose the minimum of our buffer and the CAM's buffer size */ - buf_size = (buf[0] << 8) | buf[1]; - if (buf_size > HOST_LINK_BUF_SIZE) - buf_size = HOST_LINK_BUF_SIZE; - ca->slot_info[slot].link_buf_size = buf_size; - buf[0] = buf_size >> 8; - buf[1] = buf_size & 0xff; - dprintk("Chosen link buffer size of %i\n", buf_size); - - /* write the buffer size to the CAM */ - if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN | CMDREG_SW)) != 0) - return ret; - if ((ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_FR, HZ / 10)) != 0) - return ret; - if ((ret = dvb_ca_en50221_write_data(ca, slot, buf, 2)) != 2) - return -EIO; - if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN)) != 0) - return ret; - - /* success */ - return 0; -} - -/** - * Read a tuple from attribute memory. - * - * @param ca CA instance. - * @param slot Slot id. - * @param address Address to read from. Updated. - * @param tupleType Tuple id byte. Updated. - * @param tupleLength Tuple length. Updated. - * @param tuple Dest buffer for tuple (must be 256 bytes). Updated. - * - * @return 0 on success, nonzero on error. - */ -static int dvb_ca_en50221_read_tuple(struct dvb_ca_private *ca, int slot, - int *address, int *tupleType, int *tupleLength, u8 * tuple) -{ - int i; - int _tupleType; - int _tupleLength; - int _address = *address; - - /* grab the next tuple length and type */ - if ((_tupleType = ca->pub->read_attribute_mem(ca->pub, slot, _address)) < 0) - return _tupleType; - if (_tupleType == 0xff) { - dprintk("END OF CHAIN TUPLE type:0x%x\n", _tupleType); - *address += 2; - *tupleType = _tupleType; - *tupleLength = 0; - return 0; - } - if ((_tupleLength = ca->pub->read_attribute_mem(ca->pub, slot, _address + 2)) < 0) - return _tupleLength; - _address += 4; - - dprintk("TUPLE type:0x%x length:%i\n", _tupleType, _tupleLength); - - /* read in the whole tuple */ - for (i = 0; i < _tupleLength; i++) { - tuple[i] = ca->pub->read_attribute_mem(ca->pub, slot, _address + (i * 2)); - dprintk(" 0x%02x: 0x%02x %c\n", - i, tuple[i] & 0xff, - ((tuple[i] > 31) && (tuple[i] < 127)) ? tuple[i] : '.'); - } - _address += (_tupleLength * 2); - - // success - *tupleType = _tupleType; - *tupleLength = _tupleLength; - *address = _address; - return 0; -} - - -/** - * Parse attribute memory of a CAM module, extracting Config register, and checking - * it is a DVB CAM module. - * - * @param ca CA instance. - * @param slot Slot id. - * - * @return 0 on success, <0 on failure. - */ -static int dvb_ca_en50221_parse_attributes(struct dvb_ca_private *ca, int slot) -{ - int address = 0; - int tupleLength; - int tupleType; - u8 tuple[257]; - char *dvb_str; - int rasz; - int status; - int got_cftableentry = 0; - int end_chain = 0; - int i; - u16 manfid = 0; - u16 devid = 0; - - - // CISTPL_DEVICE_0A - if ((status = - dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, &tupleLength, tuple)) < 0) - return status; - if (tupleType != 0x1D) - return -EINVAL; - - - - // CISTPL_DEVICE_0C - if ((status = - dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, &tupleLength, tuple)) < 0) - return status; - if (tupleType != 0x1C) - return -EINVAL; - - - - // CISTPL_VERS_1 - if ((status = - dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, &tupleLength, tuple)) < 0) - return status; - if (tupleType != 0x15) - return -EINVAL; - - - - // CISTPL_MANFID - if ((status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, - &tupleLength, tuple)) < 0) - return status; - if (tupleType != 0x20) - return -EINVAL; - if (tupleLength != 4) - return -EINVAL; - manfid = (tuple[1] << 8) | tuple[0]; - devid = (tuple[3] << 8) | tuple[2]; - - - - // CISTPL_CONFIG - if ((status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, - &tupleLength, tuple)) < 0) - return status; - if (tupleType != 0x1A) - return -EINVAL; - if (tupleLength < 3) - return -EINVAL; - - /* extract the configbase */ - rasz = tuple[0] & 3; - if (tupleLength < (3 + rasz + 14)) - return -EINVAL; - ca->slot_info[slot].config_base = 0; - for (i = 0; i < rasz + 1; i++) { - ca->slot_info[slot].config_base |= (tuple[2 + i] << (8 * i)); - } - - /* check it contains the correct DVB string */ - dvb_str = findstr((char *)tuple, tupleLength, "DVB_CI_V", 8); - if (dvb_str == NULL) - return -EINVAL; - if (tupleLength < ((dvb_str - (char *) tuple) + 12)) - return -EINVAL; - - /* is it a version we support? */ - if (strncmp(dvb_str + 8, "1.00", 4)) { - printk("dvb_ca adapter %d: Unsupported DVB CAM module version %c%c%c%c\n", - ca->dvbdev->adapter->num, dvb_str[8], dvb_str[9], dvb_str[10], dvb_str[11]); - return -EINVAL; - } - - /* process the CFTABLE_ENTRY tuples, and any after those */ - while ((!end_chain) && (address < 0x1000)) { - if ((status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, - &tupleLength, tuple)) < 0) - return status; - switch (tupleType) { - case 0x1B: // CISTPL_CFTABLE_ENTRY - if (tupleLength < (2 + 11 + 17)) - break; - - /* if we've already parsed one, just use it */ - if (got_cftableentry) - break; - - /* get the config option */ - ca->slot_info[slot].config_option = tuple[0] & 0x3f; - - /* OK, check it contains the correct strings */ - if ((findstr((char *)tuple, tupleLength, "DVB_HOST", 8) == NULL) || - (findstr((char *)tuple, tupleLength, "DVB_CI_MODULE", 13) == NULL)) - break; - - got_cftableentry = 1; - break; - - case 0x14: // CISTPL_NO_LINK - break; - - case 0xFF: // CISTPL_END - end_chain = 1; - break; - - default: /* Unknown tuple type - just skip this tuple and move to the next one */ - dprintk("dvb_ca: Skipping unknown tuple type:0x%x length:0x%x\n", tupleType, - tupleLength); - break; - } - } - - if ((address > 0x1000) || (!got_cftableentry)) - return -EINVAL; - - dprintk("Valid DVB CAM detected MANID:%x DEVID:%x CONFIGBASE:0x%x CONFIGOPTION:0x%x\n", - manfid, devid, ca->slot_info[slot].config_base, ca->slot_info[slot].config_option); - - // success! - return 0; -} - - -/** - * Set CAM's configoption correctly. - * - * @param ca CA instance. - * @param slot Slot containing the CAM. - */ -static int dvb_ca_en50221_set_configoption(struct dvb_ca_private *ca, int slot) -{ - int configoption; - - dprintk("%s\n", __func__); - - /* set the config option */ - ca->pub->write_attribute_mem(ca->pub, slot, - ca->slot_info[slot].config_base, - ca->slot_info[slot].config_option); - - /* check it */ - configoption = ca->pub->read_attribute_mem(ca->pub, slot, ca->slot_info[slot].config_base); - dprintk("Set configoption 0x%x, read configoption 0x%x\n", - ca->slot_info[slot].config_option, configoption & 0x3f); - - /* fine! */ - return 0; - -} - - -/** - * This function talks to an EN50221 CAM control interface. It reads a buffer of - * data from the CAM. The data can either be stored in a supplied buffer, or - * automatically be added to the slot's rx_buffer. - * - * @param ca CA instance. - * @param slot Slot to read from. - * @param ebuf If non-NULL, the data will be written to this buffer. If NULL, - * the data will be added into the buffering system as a normal fragment. - * @param ecount Size of ebuf. Ignored if ebuf is NULL. - * - * @return Number of bytes read, or < 0 on error - */ -static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 * ebuf, int ecount) -{ - int bytes_read; - int status; - u8 buf[HOST_LINK_BUF_SIZE]; - int i; - - dprintk("%s\n", __func__); - - /* check if we have space for a link buf in the rx_buffer */ - if (ebuf == NULL) { - int buf_free; - - if (ca->slot_info[slot].rx_buffer.data == NULL) { - status = -EIO; - goto exit; - } - buf_free = dvb_ringbuffer_free(&ca->slot_info[slot].rx_buffer); - - if (buf_free < (ca->slot_info[slot].link_buf_size + DVB_RINGBUFFER_PKTHDRSIZE)) { - status = -EAGAIN; - goto exit; - } - } - - if (ca->pub->read_data && (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_LINKINIT)) { - if (ebuf == NULL) - status = ca->pub->read_data(ca->pub, slot, buf, sizeof(buf)); - else - status = ca->pub->read_data(ca->pub, slot, buf, ecount); - if (status < 0) - return status; - bytes_read = status; - if (status == 0) - goto exit; - } else { - - /* check if there is data available */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) - goto exit; - if (!(status & STATUSREG_DA)) { - /* no data */ - status = 0; - goto exit; - } - - /* read the amount of data */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH)) < 0) - goto exit; - bytes_read = status << 8; - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_LOW)) < 0) - goto exit; - bytes_read |= status; - - /* check it will fit */ - if (ebuf == NULL) { - if (bytes_read > ca->slot_info[slot].link_buf_size) { - printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the link buffer size (%i > %i)!\n", - ca->dvbdev->adapter->num, bytes_read, ca->slot_info[slot].link_buf_size); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; - status = -EIO; - goto exit; - } - if (bytes_read < 2) { - printk("dvb_ca adapter %d: CAM sent a buffer that was less than 2 bytes!\n", - ca->dvbdev->adapter->num); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; - status = -EIO; - goto exit; - } - } else { - if (bytes_read > ecount) { - printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the ecount size!\n", - ca->dvbdev->adapter->num); - status = -EIO; - goto exit; - } - } - - /* fill the buffer */ - for (i = 0; i < bytes_read; i++) { - /* read byte and check */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_DATA)) < 0) - goto exit; - - /* OK, store it in the buffer */ - buf[i] = status; - } - - /* check for read error (RE should now be 0) */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) - goto exit; - if (status & STATUSREG_RE) { - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; - status = -EIO; - goto exit; - } - } - /* OK, add it to the receive buffer, or copy into external buffer if supplied */ - if (ebuf == NULL) { - if (ca->slot_info[slot].rx_buffer.data == NULL) { - status = -EIO; - goto exit; - } - dvb_ringbuffer_pkt_write(&ca->slot_info[slot].rx_buffer, buf, bytes_read); - } else { - memcpy(ebuf, buf, bytes_read); - } - - dprintk("Received CA packet for slot %i connection id 0x%x last_frag:%i size:0x%x\n", slot, - buf[0], (buf[1] & 0x80) == 0, bytes_read); - - /* wake up readers when a last_fragment is received */ - if ((buf[1] & 0x80) == 0x00) { - wake_up_interruptible(&ca->wait_queue); - } - status = bytes_read; - -exit: - return status; -} - - -/** - * This function talks to an EN50221 CAM control interface. It writes a buffer of data - * to a CAM. - * - * @param ca CA instance. - * @param slot Slot to write to. - * @param ebuf The data in this buffer is treated as a complete link-level packet to - * be written. - * @param count Size of ebuf. - * - * @return Number of bytes written, or < 0 on error. - */ -static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * buf, int bytes_write) -{ - int status; - int i; - - dprintk("%s\n", __func__); - - - /* sanity check */ - if (bytes_write > ca->slot_info[slot].link_buf_size) - return -EINVAL; - - if (ca->pub->write_data && (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_LINKINIT)) - return ca->pub->write_data(ca->pub, slot, buf, bytes_write); - - /* it is possible we are dealing with a single buffer implementation, - thus if there is data available for read or if there is even a read - already in progress, we do nothing but awake the kernel thread to - process the data if necessary. */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) - goto exitnowrite; - if (status & (STATUSREG_DA | STATUSREG_RE)) { - if (status & STATUSREG_DA) - dvb_ca_en50221_thread_wakeup(ca); - - status = -EAGAIN; - goto exitnowrite; - } - - /* OK, set HC bit */ - if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, - IRQEN | CMDREG_HC)) != 0) - goto exit; - - /* check if interface is still free */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) - goto exit; - if (!(status & STATUSREG_FR)) { - /* it wasn't free => try again later */ - status = -EAGAIN; - goto exit; - } - - /* It may need some time for the CAM to settle down, or there might be a - race condition between the CAM, writing HC and our last check for DA. - This happens, if the CAM asserts DA, just after checking DA before we - are setting HC. In this case it might be a bug in the CAM to keep the - FR bit, the lower layer/HW communication requires a longer timeout or - the CAM needs more time internally. But this happens in reality! - We need to read the status from the HW again and do the same we did - for the previous check for DA */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) - goto exit; - if (status & (STATUSREG_DA | STATUSREG_RE)) { - if (status & STATUSREG_DA) - dvb_ca_en50221_thread_wakeup(ca); - - status = -EAGAIN; - goto exit; - } - - /* send the amount of data */ - if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH, bytes_write >> 8)) != 0) - goto exit; - if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_LOW, - bytes_write & 0xff)) != 0) - goto exit; - - /* send the buffer */ - for (i = 0; i < bytes_write; i++) { - if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_DATA, buf[i])) != 0) - goto exit; - } - - /* check for write error (WE should now be 0) */ - if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) - goto exit; - if (status & STATUSREG_WE) { - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; - status = -EIO; - goto exit; - } - status = bytes_write; - - dprintk("Wrote CA packet for slot %i, connection id 0x%x last_frag:%i size:0x%x\n", slot, - buf[0], (buf[1] & 0x80) == 0, bytes_write); - -exit: - ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN); - -exitnowrite: - return status; -} -EXPORT_SYMBOL(dvb_ca_en50221_camchange_irq); - - - -/* ******************************************************************************** */ -/* EN50221 higher level functions */ - - -/** - * A CAM has been removed => shut it down. - * - * @param ca CA instance. - * @param slot Slot to shut down. - */ -static int dvb_ca_en50221_slot_shutdown(struct dvb_ca_private *ca, int slot) -{ - dprintk("%s\n", __func__); - - ca->pub->slot_shutdown(ca->pub, slot); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE; - - /* need to wake up all processes to check if they're now - trying to write to a defunct CAM */ - wake_up_interruptible(&ca->wait_queue); - - dprintk("Slot %i shutdown\n", slot); - - /* success */ - return 0; -} -EXPORT_SYMBOL(dvb_ca_en50221_camready_irq); - - -/** - * A CAMCHANGE IRQ has occurred. - * - * @param ca CA instance. - * @param slot Slot concerned. - * @param change_type One of the DVB_CA_CAMCHANGE_* values. - */ -void dvb_ca_en50221_camchange_irq(struct dvb_ca_en50221 *pubca, int slot, int change_type) -{ - struct dvb_ca_private *ca = pubca->private; - - dprintk("CAMCHANGE IRQ slot:%i change_type:%i\n", slot, change_type); - - switch (change_type) { - case DVB_CA_EN50221_CAMCHANGE_REMOVED: - case DVB_CA_EN50221_CAMCHANGE_INSERTED: - break; - - default: - return; - } - - ca->slot_info[slot].camchange_type = change_type; - atomic_inc(&ca->slot_info[slot].camchange_count); - dvb_ca_en50221_thread_wakeup(ca); -} -EXPORT_SYMBOL(dvb_ca_en50221_frda_irq); - - -/** - * A CAMREADY IRQ has occurred. - * - * @param ca CA instance. - * @param slot Slot concerned. - */ -void dvb_ca_en50221_camready_irq(struct dvb_ca_en50221 *pubca, int slot) -{ - struct dvb_ca_private *ca = pubca->private; - - dprintk("CAMREADY IRQ slot:%i\n", slot); - - if (ca->slot_info[slot].slot_state == DVB_CA_SLOTSTATE_WAITREADY) { - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_VALIDATE; - dvb_ca_en50221_thread_wakeup(ca); - } -} - - -/** - * An FR or DA IRQ has occurred. - * - * @param ca CA instance. - * @param slot Slot concerned. - */ -void dvb_ca_en50221_frda_irq(struct dvb_ca_en50221 *pubca, int slot) -{ - struct dvb_ca_private *ca = pubca->private; - int flags; - - dprintk("FR/DA IRQ slot:%i\n", slot); - - switch (ca->slot_info[slot].slot_state) { - case DVB_CA_SLOTSTATE_LINKINIT: - flags = ca->pub->read_cam_control(pubca, slot, CTRLIF_STATUS); - if (flags & STATUSREG_DA) { - dprintk("CAM supports DA IRQ\n"); - ca->slot_info[slot].da_irq_supported = 1; - } - break; - - case DVB_CA_SLOTSTATE_RUNNING: - if (ca->open) - dvb_ca_en50221_thread_wakeup(ca); - break; - } -} - - - -/* ******************************************************************************** */ -/* EN50221 thread functions */ - -/** - * Wake up the DVB CA thread - * - * @param ca CA instance. - */ -static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca) -{ - - dprintk("%s\n", __func__); - - ca->wakeup = 1; - mb(); - wake_up_process(ca->thread); -} - -/** - * Update the delay used by the thread. - * - * @param ca CA instance. - */ -static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca) -{ - int delay; - int curdelay = 100000000; - int slot; - - /* Beware of too high polling frequency, because one polling - * call might take several hundred milliseconds until timeout! - */ - for (slot = 0; slot < ca->slot_count; slot++) { - switch (ca->slot_info[slot].slot_state) { - default: - case DVB_CA_SLOTSTATE_NONE: - delay = HZ * 60; /* 60s */ - if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) - delay = HZ * 5; /* 5s */ - break; - case DVB_CA_SLOTSTATE_INVALID: - delay = HZ * 60; /* 60s */ - if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) - delay = HZ / 10; /* 100ms */ - break; - - case DVB_CA_SLOTSTATE_UNINITIALISED: - case DVB_CA_SLOTSTATE_WAITREADY: - case DVB_CA_SLOTSTATE_VALIDATE: - case DVB_CA_SLOTSTATE_WAITFR: - case DVB_CA_SLOTSTATE_LINKINIT: - delay = HZ / 10; /* 100ms */ - break; - - case DVB_CA_SLOTSTATE_RUNNING: - delay = HZ * 60; /* 60s */ - if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) - delay = HZ / 10; /* 100ms */ - if (ca->open) { - if ((!ca->slot_info[slot].da_irq_supported) || - (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_DA))) - delay = HZ / 10; /* 100ms */ - } - break; - } - - if (delay < curdelay) - curdelay = delay; - } - - ca->delay = curdelay; -} - - - -/** - * Kernel thread which monitors CA slots for CAM changes, and performs data transfers. - */ -static int dvb_ca_en50221_thread(void *data) -{ - struct dvb_ca_private *ca = data; - int slot; - int flags; - int status; - int pktcount; - void *rxbuf; - - dprintk("%s\n", __func__); - - /* choose the correct initial delay */ - dvb_ca_en50221_thread_update_delay(ca); - - /* main loop */ - while (!kthread_should_stop()) { - /* sleep for a bit */ - if (!ca->wakeup) { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(ca->delay); - if (kthread_should_stop()) - return 0; - } - ca->wakeup = 0; - - /* go through all the slots processing them */ - for (slot = 0; slot < ca->slot_count; slot++) { - - mutex_lock(&ca->slot_info[slot].slot_lock); - - // check the cam status + deal with CAMCHANGEs - while (dvb_ca_en50221_check_camstatus(ca, slot)) { - /* clear down an old CI slot if necessary */ - if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_NONE) - dvb_ca_en50221_slot_shutdown(ca, slot); - - /* if a CAM is NOW present, initialise it */ - if (ca->slot_info[slot].camchange_type == DVB_CA_EN50221_CAMCHANGE_INSERTED) { - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_UNINITIALISED; - } - - /* we've handled one CAMCHANGE */ - dvb_ca_en50221_thread_update_delay(ca); - atomic_dec(&ca->slot_info[slot].camchange_count); - } - - // CAM state machine - switch (ca->slot_info[slot].slot_state) { - case DVB_CA_SLOTSTATE_NONE: - case DVB_CA_SLOTSTATE_INVALID: - // no action needed - break; - - case DVB_CA_SLOTSTATE_UNINITIALISED: - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_WAITREADY; - ca->pub->slot_reset(ca->pub, slot); - ca->slot_info[slot].timeout = jiffies + (INIT_TIMEOUT_SECS * HZ); - break; - - case DVB_CA_SLOTSTATE_WAITREADY: - if (time_after(jiffies, ca->slot_info[slot].timeout)) { - printk("dvb_ca adaptor %d: PC card did not respond :(\n", - ca->dvbdev->adapter->num); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - // no other action needed; will automatically change state when ready - break; - - case DVB_CA_SLOTSTATE_VALIDATE: - if (dvb_ca_en50221_parse_attributes(ca, slot) != 0) { - /* we need this extra check for annoying interfaces like the budget-av */ - if ((!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) && - (ca->pub->poll_slot_status)) { - status = ca->pub->poll_slot_status(ca->pub, slot, 0); - if (!(status & DVB_CA_EN50221_POLL_CAM_PRESENT)) { - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - } - - printk("dvb_ca adapter %d: Invalid PC card inserted :(\n", - ca->dvbdev->adapter->num); - //ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - if (dvb_ca_en50221_set_configoption(ca, slot) != 0) { - printk("dvb_ca adapter %d: Unable to initialise CAM :(\n", - ca->dvbdev->adapter->num); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - if (ca->pub->write_cam_control(ca->pub, slot, - CTRLIF_COMMAND, CMDREG_RS) != 0) { - printk("dvb_ca adapter %d: Unable to reset CAM IF\n", - ca->dvbdev->adapter->num); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - dprintk("DVB CAM validated successfully\n"); - - ca->slot_info[slot].timeout = jiffies + (INIT_TIMEOUT_SECS * HZ); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_WAITFR; - ca->wakeup = 1; - break; - - case DVB_CA_SLOTSTATE_WAITFR: - if (time_after(jiffies, ca->slot_info[slot].timeout)) { - printk("dvb_ca adapter %d: DVB CAM did not respond :(\n", - ca->dvbdev->adapter->num); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - - flags = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS); - if (flags & STATUSREG_FR) { - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; - ca->wakeup = 1; - } - break; - - case DVB_CA_SLOTSTATE_LINKINIT: - if (dvb_ca_en50221_link_init(ca, slot) != 0) { - /* we need this extra check for annoying interfaces like the budget-av */ - if ((!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) && - (ca->pub->poll_slot_status)) { - status = ca->pub->poll_slot_status(ca->pub, slot, 0); - if (!(status & DVB_CA_EN50221_POLL_CAM_PRESENT)) { - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - } - - printk("dvb_ca adapter %d: DVB CAM link initialisation failed :(\n", ca->dvbdev->adapter->num); -#if 1 - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; - dvb_ca_en50221_thread_update_delay(ca); -#else - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_UNINITIALISED; - dvb_ca_en50221_thread_update_delay(ca); -#endif - break; - } - - if (ca->slot_info[slot].rx_buffer.data == NULL) { - rxbuf = vmalloc(RX_BUFFER_SIZE); - if (rxbuf == NULL) { - printk("dvb_ca adapter %d: Unable to allocate CAM rx buffer :(\n", ca->dvbdev->adapter->num); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; - dvb_ca_en50221_thread_update_delay(ca); - break; - } - dvb_ringbuffer_init(&ca->slot_info[slot].rx_buffer, rxbuf, RX_BUFFER_SIZE); - } - - ca->pub->slot_ts_enable(ca->pub, slot); - ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_RUNNING; - dvb_ca_en50221_thread_update_delay(ca); - printk("dvb_ca adapter %d: DVB CAM detected and initialised successfully\n", ca->dvbdev->adapter->num); - break; - - case DVB_CA_SLOTSTATE_RUNNING: - if (!ca->open) - break; - - // poll slots for data - pktcount = 0; - while ((status = dvb_ca_en50221_read_data(ca, slot, NULL, 0)) > 0) { - if (!ca->open) - break; - - /* if a CAMCHANGE occurred at some point, do not do any more processing of this slot */ - if (dvb_ca_en50221_check_camstatus(ca, slot)) { - // we dont want to sleep on the next iteration so we can handle the cam change - ca->wakeup = 1; - break; - } - - /* check if we've hit our limit this time */ - if (++pktcount >= MAX_RX_PACKETS_PER_ITERATION) { - // dont sleep; there is likely to be more data to read - ca->wakeup = 1; - break; - } - } - break; - } - - mutex_unlock(&ca->slot_info[slot].slot_lock); - } - } - - return 0; -} - - - -/* ******************************************************************************** */ -/* EN50221 IO interface functions */ - -/** - * Real ioctl implementation. - * NOTE: CA_SEND_MSG/CA_GET_MSG ioctls have userspace buffers passed to them. - * - * @param inode Inode concerned. - * @param file File concerned. - * @param cmd IOCTL command. - * @param arg Associated argument. - * - * @return 0 on success, <0 on error. - */ -static int dvb_ca_en50221_io_do_ioctl(struct file *file, - unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_ca_private *ca = dvbdev->priv; - int err = 0; - int slot; - - dprintk("%s\n", __func__); - - if (mutex_lock_interruptible(&ca->ioctl_mutex)) - return -ERESTARTSYS; - - switch (cmd) { - case CA_RESET: - for (slot = 0; slot < ca->slot_count; slot++) { - mutex_lock(&ca->slot_info[slot].slot_lock); - if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_NONE) { - dvb_ca_en50221_slot_shutdown(ca, slot); - if (ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE) - dvb_ca_en50221_camchange_irq(ca->pub, - slot, - DVB_CA_EN50221_CAMCHANGE_INSERTED); - } - mutex_unlock(&ca->slot_info[slot].slot_lock); - } - ca->next_read_slot = 0; - dvb_ca_en50221_thread_wakeup(ca); - break; - - case CA_GET_CAP: { - struct ca_caps *caps = parg; - - caps->slot_num = ca->slot_count; - caps->slot_type = CA_CI_LINK; - caps->descr_num = 0; - caps->descr_type = 0; - break; - } - - case CA_GET_SLOT_INFO: { - struct ca_slot_info *info = parg; - - if ((info->num > ca->slot_count) || (info->num < 0)) { - err = -EINVAL; - goto out_unlock; - } - - info->type = CA_CI_LINK; - info->flags = 0; - if ((ca->slot_info[info->num].slot_state != DVB_CA_SLOTSTATE_NONE) - && (ca->slot_info[info->num].slot_state != DVB_CA_SLOTSTATE_INVALID)) { - info->flags = CA_CI_MODULE_PRESENT; - } - if (ca->slot_info[info->num].slot_state == DVB_CA_SLOTSTATE_RUNNING) { - info->flags |= CA_CI_MODULE_READY; - } - break; - } - - default: - err = -EINVAL; - break; - } - -out_unlock: - mutex_unlock(&ca->ioctl_mutex); - return err; -} - - -/** - * Wrapper for ioctl implementation. - * - * @param inode Inode concerned. - * @param file File concerned. - * @param cmd IOCTL command. - * @param arg Associated argument. - * - * @return 0 on success, <0 on error. - */ -static long dvb_ca_en50221_io_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - return dvb_usercopy(file, cmd, arg, dvb_ca_en50221_io_do_ioctl); -} - - -/** - * Implementation of write() syscall. - * - * @param file File structure. - * @param buf Source buffer. - * @param count Size of source buffer. - * @param ppos Position in file (ignored). - * - * @return Number of bytes read, or <0 on error. - */ -static ssize_t dvb_ca_en50221_io_write(struct file *file, - const char __user * buf, size_t count, loff_t * ppos) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_ca_private *ca = dvbdev->priv; - u8 slot, connection_id; - int status; - u8 fragbuf[HOST_LINK_BUF_SIZE]; - int fragpos = 0; - int fraglen; - unsigned long timeout; - int written; - - dprintk("%s\n", __func__); - - /* Incoming packet has a 2 byte header. hdr[0] = slot_id, hdr[1] = connection_id */ - if (count < 2) - return -EINVAL; - - /* extract slot & connection id */ - if (copy_from_user(&slot, buf, 1)) - return -EFAULT; - if (copy_from_user(&connection_id, buf + 1, 1)) - return -EFAULT; - buf += 2; - count -= 2; - - /* check if the slot is actually running */ - if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_RUNNING) - return -EINVAL; - - /* fragment the packets & store in the buffer */ - while (fragpos < count) { - fraglen = ca->slot_info[slot].link_buf_size - 2; - if (fraglen < 0) - break; - if (fraglen > HOST_LINK_BUF_SIZE - 2) - fraglen = HOST_LINK_BUF_SIZE - 2; - if ((count - fragpos) < fraglen) - fraglen = count - fragpos; - - fragbuf[0] = connection_id; - fragbuf[1] = ((fragpos + fraglen) < count) ? 0x80 : 0x00; - status = copy_from_user(fragbuf + 2, buf + fragpos, fraglen); - if (status) { - status = -EFAULT; - goto exit; - } - - timeout = jiffies + HZ / 2; - written = 0; - while (!time_after(jiffies, timeout)) { - /* check the CAM hasn't been removed/reset in the meantime */ - if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_RUNNING) { - status = -EIO; - goto exit; - } - - mutex_lock(&ca->slot_info[slot].slot_lock); - status = dvb_ca_en50221_write_data(ca, slot, fragbuf, fraglen + 2); - mutex_unlock(&ca->slot_info[slot].slot_lock); - if (status == (fraglen + 2)) { - written = 1; - break; - } - if (status != -EAGAIN) - goto exit; - - msleep(1); - } - if (!written) { - status = -EIO; - goto exit; - } - - fragpos += fraglen; - } - status = count + 2; - -exit: - return status; -} - - -/** - * Condition for waking up in dvb_ca_en50221_io_read_condition - */ -static int dvb_ca_en50221_io_read_condition(struct dvb_ca_private *ca, - int *result, int *_slot) -{ - int slot; - int slot_count = 0; - int idx; - size_t fraglen; - int connection_id = -1; - int found = 0; - u8 hdr[2]; - - slot = ca->next_read_slot; - while ((slot_count < ca->slot_count) && (!found)) { - if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_RUNNING) - goto nextslot; - - if (ca->slot_info[slot].rx_buffer.data == NULL) { - return 0; - } - - idx = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, -1, &fraglen); - while (idx != -1) { - dvb_ringbuffer_pkt_read(&ca->slot_info[slot].rx_buffer, idx, 0, hdr, 2); - if (connection_id == -1) - connection_id = hdr[0]; - if ((hdr[0] == connection_id) && ((hdr[1] & 0x80) == 0)) { - *_slot = slot; - found = 1; - break; - } - - idx = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, idx, &fraglen); - } - -nextslot: - slot = (slot + 1) % ca->slot_count; - slot_count++; - } - - ca->next_read_slot = slot; - return found; -} - - -/** - * Implementation of read() syscall. - * - * @param file File structure. - * @param buf Destination buffer. - * @param count Size of destination buffer. - * @param ppos Position in file (ignored). - * - * @return Number of bytes read, or <0 on error. - */ -static ssize_t dvb_ca_en50221_io_read(struct file *file, char __user * buf, - size_t count, loff_t * ppos) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_ca_private *ca = dvbdev->priv; - int status; - int result = 0; - u8 hdr[2]; - int slot; - int connection_id = -1; - size_t idx, idx2; - int last_fragment = 0; - size_t fraglen; - int pktlen; - int dispose = 0; - - dprintk("%s\n", __func__); - - /* Outgoing packet has a 2 byte header. hdr[0] = slot_id, hdr[1] = connection_id */ - if (count < 2) - return -EINVAL; - - /* wait for some data */ - if ((status = dvb_ca_en50221_io_read_condition(ca, &result, &slot)) == 0) { - - /* if we're in nonblocking mode, exit immediately */ - if (file->f_flags & O_NONBLOCK) - return -EWOULDBLOCK; - - /* wait for some data */ - status = wait_event_interruptible(ca->wait_queue, - dvb_ca_en50221_io_read_condition - (ca, &result, &slot)); - } - if ((status < 0) || (result < 0)) { - if (result) - return result; - return status; - } - - idx = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, -1, &fraglen); - pktlen = 2; - do { - if (idx == -1) { - printk("dvb_ca adapter %d: BUG: read packet ended before last_fragment encountered\n", ca->dvbdev->adapter->num); - status = -EIO; - goto exit; - } - - dvb_ringbuffer_pkt_read(&ca->slot_info[slot].rx_buffer, idx, 0, hdr, 2); - if (connection_id == -1) - connection_id = hdr[0]; - if (hdr[0] == connection_id) { - if (pktlen < count) { - if ((pktlen + fraglen - 2) > count) { - fraglen = count - pktlen; - } else { - fraglen -= 2; - } - - if ((status = dvb_ringbuffer_pkt_read_user(&ca->slot_info[slot].rx_buffer, idx, 2, - buf + pktlen, fraglen)) < 0) { - goto exit; - } - pktlen += fraglen; - } - - if ((hdr[1] & 0x80) == 0) - last_fragment = 1; - dispose = 1; - } - - idx2 = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, idx, &fraglen); - if (dispose) - dvb_ringbuffer_pkt_dispose(&ca->slot_info[slot].rx_buffer, idx); - idx = idx2; - dispose = 0; - } while (!last_fragment); - - hdr[0] = slot; - hdr[1] = connection_id; - status = copy_to_user(buf, hdr, 2); - if (status) { - status = -EFAULT; - goto exit; - } - status = pktlen; - -exit: - return status; -} - - -/** - * Implementation of file open syscall. - * - * @param inode Inode concerned. - * @param file File concerned. - * - * @return 0 on success, <0 on failure. - */ -static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_ca_private *ca = dvbdev->priv; - int err; - int i; - - dprintk("%s\n", __func__); - - if (!try_module_get(ca->pub->owner)) - return -EIO; - - err = dvb_generic_open(inode, file); - if (err < 0) { - module_put(ca->pub->owner); - return err; - } - - for (i = 0; i < ca->slot_count; i++) { - - if (ca->slot_info[i].slot_state == DVB_CA_SLOTSTATE_RUNNING) { - if (ca->slot_info[i].rx_buffer.data != NULL) { - /* it is safe to call this here without locks because - * ca->open == 0. Data is not read in this case */ - dvb_ringbuffer_flush(&ca->slot_info[i].rx_buffer); - } - } - } - - ca->open = 1; - dvb_ca_en50221_thread_update_delay(ca); - dvb_ca_en50221_thread_wakeup(ca); - - return 0; -} - - -/** - * Implementation of file close syscall. - * - * @param inode Inode concerned. - * @param file File concerned. - * - * @return 0 on success, <0 on failure. - */ -static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_ca_private *ca = dvbdev->priv; - int err; - - dprintk("%s\n", __func__); - - /* mark the CA device as closed */ - ca->open = 0; - dvb_ca_en50221_thread_update_delay(ca); - - err = dvb_generic_release(inode, file); - - module_put(ca->pub->owner); - - return err; -} - - -/** - * Implementation of poll() syscall. - * - * @param file File concerned. - * @param wait poll wait table. - * - * @return Standard poll mask. - */ -static unsigned int dvb_ca_en50221_io_poll(struct file *file, poll_table * wait) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_ca_private *ca = dvbdev->priv; - unsigned int mask = 0; - int slot; - int result = 0; - - dprintk("%s\n", __func__); - - if (dvb_ca_en50221_io_read_condition(ca, &result, &slot) == 1) { - mask |= POLLIN; - } - - /* if there is something, return now */ - if (mask) - return mask; - - /* wait for something to happen */ - poll_wait(file, &ca->wait_queue, wait); - - if (dvb_ca_en50221_io_read_condition(ca, &result, &slot) == 1) { - mask |= POLLIN; - } - - return mask; -} -EXPORT_SYMBOL(dvb_ca_en50221_init); - - -static const struct file_operations dvb_ca_fops = { - .owner = THIS_MODULE, - .read = dvb_ca_en50221_io_read, - .write = dvb_ca_en50221_io_write, - .unlocked_ioctl = dvb_ca_en50221_io_ioctl, - .open = dvb_ca_en50221_io_open, - .release = dvb_ca_en50221_io_release, - .poll = dvb_ca_en50221_io_poll, - .llseek = noop_llseek, -}; - -static struct dvb_device dvbdev_ca = { - .priv = NULL, - .users = 1, - .readers = 1, - .writers = 1, - .fops = &dvb_ca_fops, -}; - - -/* ******************************************************************************** */ -/* Initialisation/shutdown functions */ - - -/** - * Initialise a new DVB CA EN50221 interface device. - * - * @param dvb_adapter DVB adapter to attach the new CA device to. - * @param ca The dvb_ca instance. - * @param flags Flags describing the CA device (DVB_CA_FLAG_*). - * @param slot_count Number of slots supported. - * - * @return 0 on success, nonzero on failure - */ -int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter, - struct dvb_ca_en50221 *pubca, int flags, int slot_count) -{ - int ret; - struct dvb_ca_private *ca = NULL; - int i; - - dprintk("%s\n", __func__); - - if (slot_count < 1) - return -EINVAL; - - /* initialise the system data */ - if ((ca = kzalloc(sizeof(struct dvb_ca_private), GFP_KERNEL)) == NULL) { - ret = -ENOMEM; - goto error; - } - ca->pub = pubca; - ca->flags = flags; - ca->slot_count = slot_count; - if ((ca->slot_info = kcalloc(slot_count, sizeof(struct dvb_ca_slot), GFP_KERNEL)) == NULL) { - ret = -ENOMEM; - goto error; - } - init_waitqueue_head(&ca->wait_queue); - ca->open = 0; - ca->wakeup = 0; - ca->next_read_slot = 0; - pubca->private = ca; - - /* register the DVB device */ - ret = dvb_register_device(dvb_adapter, &ca->dvbdev, &dvbdev_ca, ca, DVB_DEVICE_CA); - if (ret) - goto error; - - /* now initialise each slot */ - for (i = 0; i < slot_count; i++) { - memset(&ca->slot_info[i], 0, sizeof(struct dvb_ca_slot)); - ca->slot_info[i].slot_state = DVB_CA_SLOTSTATE_NONE; - atomic_set(&ca->slot_info[i].camchange_count, 0); - ca->slot_info[i].camchange_type = DVB_CA_EN50221_CAMCHANGE_REMOVED; - mutex_init(&ca->slot_info[i].slot_lock); - } - - mutex_init(&ca->ioctl_mutex); - - if (signal_pending(current)) { - ret = -EINTR; - goto error; - } - mb(); - - /* create a kthread for monitoring this CA device */ - ca->thread = kthread_run(dvb_ca_en50221_thread, ca, "kdvb-ca-%i:%i", - ca->dvbdev->adapter->num, ca->dvbdev->id); - if (IS_ERR(ca->thread)) { - ret = PTR_ERR(ca->thread); - printk("dvb_ca_init: failed to start kernel_thread (%d)\n", - ret); - goto error; - } - return 0; - -error: - if (ca != NULL) { - if (ca->dvbdev != NULL) - dvb_unregister_device(ca->dvbdev); - kfree(ca->slot_info); - kfree(ca); - } - pubca->private = NULL; - return ret; -} -EXPORT_SYMBOL(dvb_ca_en50221_release); - - - -/** - * Release a DVB CA EN50221 interface device. - * - * @param ca_dev The dvb_device_t instance for the CA device. - * @param ca The associated dvb_ca instance. - */ -void dvb_ca_en50221_release(struct dvb_ca_en50221 *pubca) -{ - struct dvb_ca_private *ca = pubca->private; - int i; - - dprintk("%s\n", __func__); - - /* shutdown the thread if there was one */ - kthread_stop(ca->thread); - - for (i = 0; i < ca->slot_count; i++) { - dvb_ca_en50221_slot_shutdown(ca, i); - vfree(ca->slot_info[i].rx_buffer.data); - } - kfree(ca->slot_info); - dvb_unregister_device(ca->dvbdev); - kfree(ca); - pubca->private = NULL; -} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ca_en50221.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,140 +0,0 @@ -/* - * dvb_ca.h: generic DVB functions for EN50221 CA interfaces - * - * Copyright (C) 2004 Andrew de Quincey - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _DVB_CA_EN50221_H_ -#define _DVB_CA_EN50221_H_ - -#include -#include - -#include "dvbdev.h" - -#define DVB_CA_EN50221_POLL_CAM_PRESENT 1 -#define DVB_CA_EN50221_POLL_CAM_CHANGED 2 -#define DVB_CA_EN50221_POLL_CAM_READY 4 - -#define DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE 1 -#define DVB_CA_EN50221_FLAG_IRQ_FR 2 -#define DVB_CA_EN50221_FLAG_IRQ_DA 4 - -#define DVB_CA_EN50221_CAMCHANGE_REMOVED 0 -#define DVB_CA_EN50221_CAMCHANGE_INSERTED 1 - - - -/* Structure describing a CA interface */ -struct dvb_ca_en50221 { - - /* the module owning this structure */ - struct module* owner; - - /* NOTE: the read_*, write_* and poll_slot_status functions will be - * called for different slots concurrently and need to use locks where - * and if appropriate. There will be no concurrent access to one slot. - */ - - /* functions for accessing attribute memory on the CAM */ - int (*read_attribute_mem)(struct dvb_ca_en50221* ca, int slot, int address); - int (*write_attribute_mem)(struct dvb_ca_en50221* ca, int slot, int address, u8 value); - - /* functions for accessing the control interface on the CAM */ - int (*read_cam_control)(struct dvb_ca_en50221* ca, int slot, u8 address); - int (*write_cam_control)(struct dvb_ca_en50221* ca, int slot, u8 address, u8 value); - - /* functions for readin/writing data */ - int (*read_data)(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount); - int (*write_data)(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount); - - /* Functions for controlling slots */ - int (*slot_reset)(struct dvb_ca_en50221* ca, int slot); - int (*slot_shutdown)(struct dvb_ca_en50221* ca, int slot); - int (*slot_ts_enable)(struct dvb_ca_en50221* ca, int slot); - - /* - * Poll slot status. - * Only necessary if DVB_CA_FLAG_EN50221_IRQ_CAMCHANGE is not set - */ - int (*poll_slot_status)(struct dvb_ca_en50221* ca, int slot, int open); - - /* private data, used by caller */ - void* data; - - /* Opaque data used by the dvb_ca core. Do not modify! */ - void* private; -}; - - - - -/* ******************************************************************************** */ -/* Functions for reporting IRQ events */ - -/** - * A CAMCHANGE IRQ has occurred. - * - * @param ca CA instance. - * @param slot Slot concerned. - * @param change_type One of the DVB_CA_CAMCHANGE_* values - */ -void dvb_ca_en50221_camchange_irq(struct dvb_ca_en50221* pubca, int slot, int change_type); - -/** - * A CAMREADY IRQ has occurred. - * - * @param ca CA instance. - * @param slot Slot concerned. - */ -void dvb_ca_en50221_camready_irq(struct dvb_ca_en50221* pubca, int slot); - -/** - * An FR or a DA IRQ has occurred. - * - * @param ca CA instance. - * @param slot Slot concerned. - */ -void dvb_ca_en50221_frda_irq(struct dvb_ca_en50221* ca, int slot); - - - -/* ******************************************************************************** */ -/* Initialisation/shutdown functions */ - -/** - * Initialise a new DVB CA device. - * - * @param dvb_adapter DVB adapter to attach the new CA device to. - * @param ca The dvb_ca instance. - * @param flags Flags describing the CA device (DVB_CA_EN50221_FLAG_*). - * @param slot_count Number of slots supported. - * - * @return 0 on success, nonzero on failure - */ -extern int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter, struct dvb_ca_en50221* ca, int flags, int slot_count); - -/** - * Release a DVB CA device. - * - * @param ca The associated dvb_ca instance. - */ -extern void dvb_ca_en50221_release(struct dvb_ca_en50221* ca); - - - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1320 +0,0 @@ -/* - * dvb_demux.c - DVB kernel demux API - * - * Copyright (C) 2000-2001 Ralph Metzler - * & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_demux.h" - -#define NOBUFS -/* -** #define DVB_DEMUX_SECTION_LOSS_LOG to monitor payload loss in the syslog -*/ -// #define DVB_DEMUX_SECTION_LOSS_LOG - -static int dvb_demux_tscheck; -module_param(dvb_demux_tscheck, int, 0644); -MODULE_PARM_DESC(dvb_demux_tscheck, - "enable transport stream continuity and TEI check"); - -static int dvb_demux_speedcheck; -module_param(dvb_demux_speedcheck, int, 0644); -MODULE_PARM_DESC(dvb_demux_speedcheck, - "enable transport stream speed check"); - -static int dvb_demux_feed_err_pkts = 1; -module_param(dvb_demux_feed_err_pkts, int, 0644); -MODULE_PARM_DESC(dvb_demux_feed_err_pkts, - "when set to 0, drop packets with the TEI bit set (1 by default)"); - -#define dprintk_tscheck(x...) do { \ - if (dvb_demux_tscheck && printk_ratelimit()) \ - printk(x); \ - } while (0) - -/****************************************************************************** - * static inlined helper functions - ******************************************************************************/ - -static inline u16 section_length(const u8 *buf) -{ - return 3 + ((buf[1] & 0x0f) << 8) + buf[2]; -} - -static inline u16 ts_pid(const u8 *buf) -{ - return ((buf[1] & 0x1f) << 8) + buf[2]; -} - -static inline u8 payload(const u8 *tsp) -{ - if (!(tsp[3] & 0x10)) // no payload? - return 0; - - if (tsp[3] & 0x20) { // adaptation field? - if (tsp[4] > 183) // corrupted data? - return 0; - else - return 184 - 1 - tsp[4]; - } - - return 184; -} - -static u32 dvb_dmx_crc32(struct dvb_demux_feed *f, const u8 *src, size_t len) -{ - return (f->feed.sec.crc_val = crc32_be(f->feed.sec.crc_val, src, len)); -} - -static void dvb_dmx_memcopy(struct dvb_demux_feed *f, u8 *d, const u8 *s, - size_t len) -{ - memcpy(d, s, len); -} - -/****************************************************************************** - * Software filter functions - ******************************************************************************/ - -static inline int dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed, - const u8 *buf) -{ - int count = payload(buf); - int p; - //int ccok; - //u8 cc; - - if (count == 0) - return -1; - - p = 188 - count; - - /* - cc = buf[3] & 0x0f; - ccok = ((feed->cc + 1) & 0x0f) == cc; - feed->cc = cc; - if (!ccok) - printk("missed packet!\n"); - */ - - if (buf[1] & 0x40) // PUSI ? - feed->peslen = 0xfffa; - - feed->peslen += count; - - return feed->cb.ts(&buf[p], count, NULL, 0, &feed->feed.ts, DMX_OK); -} - -static int dvb_dmx_swfilter_sectionfilter(struct dvb_demux_feed *feed, - struct dvb_demux_filter *f) -{ - u8 neq = 0; - int i; - - for (i = 0; i < DVB_DEMUX_MASK_MAX; i++) { - u8 xor = f->filter.filter_value[i] ^ feed->feed.sec.secbuf[i]; - - if (f->maskandmode[i] & xor) - return 0; - - neq |= f->maskandnotmode[i] & xor; - } - - if (f->doneq && !neq) - return 0; - - return feed->cb.sec(feed->feed.sec.secbuf, feed->feed.sec.seclen, - NULL, 0, &f->filter, DMX_OK); -} - -static inline int dvb_dmx_swfilter_section_feed(struct dvb_demux_feed *feed) -{ - struct dvb_demux *demux = feed->demux; - struct dvb_demux_filter *f = feed->filter; - struct dmx_section_feed *sec = &feed->feed.sec; - int section_syntax_indicator; - - if (!sec->is_filtering) - return 0; - - if (!f) - return 0; - - if (sec->check_crc) { - section_syntax_indicator = ((sec->secbuf[1] & 0x80) != 0); - if (section_syntax_indicator && - demux->check_crc32(feed, sec->secbuf, sec->seclen)) - return -1; - } - - do { - if (dvb_dmx_swfilter_sectionfilter(feed, f) < 0) - return -1; - } while ((f = f->next) && sec->is_filtering); - - sec->seclen = 0; - - return 0; -} - -static void dvb_dmx_swfilter_section_new(struct dvb_demux_feed *feed) -{ - struct dmx_section_feed *sec = &feed->feed.sec; - -#ifdef DVB_DEMUX_SECTION_LOSS_LOG - if (sec->secbufp < sec->tsfeedp) { - int i, n = sec->tsfeedp - sec->secbufp; - - /* - * Section padding is done with 0xff bytes entirely. - * Due to speed reasons, we won't check all of them - * but just first and last. - */ - if (sec->secbuf[0] != 0xff || sec->secbuf[n - 1] != 0xff) { - printk("dvb_demux.c section ts padding loss: %d/%d\n", - n, sec->tsfeedp); - printk("dvb_demux.c pad data:"); - for (i = 0; i < n; i++) - printk(" %02x", sec->secbuf[i]); - printk("\n"); - } - } -#endif - - sec->tsfeedp = sec->secbufp = sec->seclen = 0; - sec->secbuf = sec->secbuf_base; -} - -/* - * Losless Section Demux 1.4.1 by Emard - * Valsecchi Patrick: - * - middle of section A (no PUSI) - * - end of section A and start of section B - * (with PUSI pointing to the start of the second section) - * - * In this case, without feed->pusi_seen you'll receive a garbage section - * consisting of the end of section A. Basically because tsfeedp - * is incemented and the use=0 condition is not raised - * when the second packet arrives. - * - * Fix: - * when demux is started, let feed->pusi_seen = 0 to - * prevent initial feeding of garbage from the end of - * previous section. When you for the first time see PUSI=1 - * then set feed->pusi_seen = 1 - */ -static int dvb_dmx_swfilter_section_copy_dump(struct dvb_demux_feed *feed, - const u8 *buf, u8 len) -{ - struct dvb_demux *demux = feed->demux; - struct dmx_section_feed *sec = &feed->feed.sec; - u16 limit, seclen, n; - - if (sec->tsfeedp >= DMX_MAX_SECFEED_SIZE) - return 0; - - if (sec->tsfeedp + len > DMX_MAX_SECFEED_SIZE) { -#ifdef DVB_DEMUX_SECTION_LOSS_LOG - printk("dvb_demux.c section buffer full loss: %d/%d\n", - sec->tsfeedp + len - DMX_MAX_SECFEED_SIZE, - DMX_MAX_SECFEED_SIZE); -#endif - len = DMX_MAX_SECFEED_SIZE - sec->tsfeedp; - } - - if (len <= 0) - return 0; - - demux->memcopy(feed, sec->secbuf_base + sec->tsfeedp, buf, len); - sec->tsfeedp += len; - - /* - * Dump all the sections we can find in the data (Emard) - */ - limit = sec->tsfeedp; - if (limit > DMX_MAX_SECFEED_SIZE) - return -1; /* internal error should never happen */ - - /* to be sure always set secbuf */ - sec->secbuf = sec->secbuf_base + sec->secbufp; - - for (n = 0; sec->secbufp + 2 < limit; n++) { - seclen = section_length(sec->secbuf); - if (seclen <= 0 || seclen > DMX_MAX_SECTION_SIZE - || seclen + sec->secbufp > limit) - return 0; - sec->seclen = seclen; - sec->crc_val = ~0; - /* dump [secbuf .. secbuf+seclen) */ - if (feed->pusi_seen) - dvb_dmx_swfilter_section_feed(feed); -#ifdef DVB_DEMUX_SECTION_LOSS_LOG - else - printk("dvb_demux.c pusi not seen, discarding section data\n"); -#endif - sec->secbufp += seclen; /* secbufp and secbuf moving together is */ - sec->secbuf += seclen; /* redundant but saves pointer arithmetic */ - } - - return 0; -} - -static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed, - const u8 *buf) -{ - u8 p, count; - int ccok, dc_i = 0; - u8 cc; - - count = payload(buf); - - if (count == 0) /* count == 0 if no payload or out of range */ - return -1; - - p = 188 - count; /* payload start */ - - cc = buf[3] & 0x0f; - ccok = ((feed->cc + 1) & 0x0f) == cc; - feed->cc = cc; - - if (buf[3] & 0x20) { - /* adaption field present, check for discontinuity_indicator */ - if ((buf[4] > 0) && (buf[5] & 0x80)) - dc_i = 1; - } - - if (!ccok || dc_i) { -#ifdef DVB_DEMUX_SECTION_LOSS_LOG - printk("dvb_demux.c discontinuity detected %d bytes lost\n", - count); - /* - * those bytes under sume circumstances will again be reported - * in the following dvb_dmx_swfilter_section_new - */ -#endif - /* - * Discontinuity detected. Reset pusi_seen = 0 to - * stop feeding of suspicious data until next PUSI=1 arrives - */ - feed->pusi_seen = 0; - dvb_dmx_swfilter_section_new(feed); - } - - if (buf[1] & 0x40) { - /* PUSI=1 (is set), section boundary is here */ - if (count > 1 && buf[p] < count) { - const u8 *before = &buf[p + 1]; - u8 before_len = buf[p]; - const u8 *after = &before[before_len]; - u8 after_len = count - 1 - before_len; - - dvb_dmx_swfilter_section_copy_dump(feed, before, - before_len); - /* before start of new section, set pusi_seen = 1 */ - feed->pusi_seen = 1; - dvb_dmx_swfilter_section_new(feed); - dvb_dmx_swfilter_section_copy_dump(feed, after, - after_len); - } -#ifdef DVB_DEMUX_SECTION_LOSS_LOG - else if (count > 0) - printk("dvb_demux.c PUSI=1 but %d bytes lost\n", count); -#endif - } else { - /* PUSI=0 (is not set), no section boundary */ - dvb_dmx_swfilter_section_copy_dump(feed, &buf[p], count); - } - - return 0; -} - -static inline void dvb_dmx_swfilter_packet_type(struct dvb_demux_feed *feed, - const u8 *buf) -{ - switch (feed->type) { - case DMX_TYPE_TS: - if (!feed->feed.ts.is_filtering) - break; - if (feed->ts_type & TS_PACKET) { - if (feed->ts_type & TS_PAYLOAD_ONLY) - dvb_dmx_swfilter_payload(feed, buf); - else - feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts, - DMX_OK); - } - if (feed->ts_type & TS_DECODER) - if (feed->demux->write_to_decoder) - feed->demux->write_to_decoder(feed, buf, 188); - break; - - case DMX_TYPE_SEC: - if (!feed->feed.sec.is_filtering) - break; - if (dvb_dmx_swfilter_section_packet(feed, buf) < 0) - feed->feed.sec.seclen = feed->feed.sec.secbufp = 0; - break; - - default: - break; - } -} - -#define DVR_FEED(f) \ - (((f)->type == DMX_TYPE_TS) && \ - ((f)->feed.ts.is_filtering) && \ - (((f)->ts_type & (TS_PACKET | TS_DEMUX)) == TS_PACKET)) - -static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf) -{ - struct dvb_demux_feed *feed; - u16 pid = ts_pid(buf); - int dvr_done = 0; - - if (dvb_demux_speedcheck) { - struct timespec cur_time, delta_time; - u64 speed_bytes, speed_timedelta; - - demux->speed_pkts_cnt++; - - /* show speed every SPEED_PKTS_INTERVAL packets */ - if (!(demux->speed_pkts_cnt % SPEED_PKTS_INTERVAL)) { - cur_time = current_kernel_time(); - - if (demux->speed_last_time.tv_sec != 0 && - demux->speed_last_time.tv_nsec != 0) { - delta_time = timespec_sub(cur_time, - demux->speed_last_time); - speed_bytes = (u64)demux->speed_pkts_cnt - * 188 * 8; - /* convert to 1024 basis */ - speed_bytes = 1000 * div64_u64(speed_bytes, - 1024); - speed_timedelta = - (u64)timespec_to_ns(&delta_time); - speed_timedelta = div64_u64(speed_timedelta, - 1000000); /* nsec -> usec */ - printk(KERN_INFO "TS speed %llu Kbits/sec \n", - div64_u64(speed_bytes, - speed_timedelta)); - } - - demux->speed_last_time = cur_time; - demux->speed_pkts_cnt = 0; - } - } - - if (buf[1] & 0x80) { - dprintk_tscheck("TEI detected. " - "PID=0x%x data1=0x%x\n", - pid, buf[1]); - /* data in this packet cant be trusted - drop it unless - * module option dvb_demux_feed_err_pkts is set */ - if (!dvb_demux_feed_err_pkts) - return; - } else /* if TEI bit is set, pid may be wrong- skip pkt counter */ - if (demux->cnt_storage && dvb_demux_tscheck) { - /* check pkt counter */ - if (pid < MAX_PID) { - if (buf[3] & 0x10) - demux->cnt_storage[pid] = - (demux->cnt_storage[pid] + 1) & 0xf; - - if ((buf[3] & 0xf) != demux->cnt_storage[pid]) { - dprintk_tscheck("TS packet counter mismatch. PID=0x%x expected 0x%x got 0x%x\n", - pid, demux->cnt_storage[pid], - buf[3] & 0xf); - demux->cnt_storage[pid] = buf[3] & 0xf; - } - } - /* end check */ - } - - list_for_each_entry(feed, &demux->feed_list, list_head) { - if ((feed->pid != pid) && (feed->pid != 0x2000)) - continue; - - /* copy each packet only once to the dvr device, even - * if a PID is in multiple filters (e.g. video + PCR) */ - if ((DVR_FEED(feed)) && (dvr_done++)) - continue; - - if (feed->pid == pid) - dvb_dmx_swfilter_packet_type(feed, buf); - else if (feed->pid == 0x2000) - feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts, DMX_OK); - } -} - -void dvb_dmx_swfilter_packets(struct dvb_demux *demux, const u8 *buf, - size_t count) -{ - spin_lock(&demux->lock); - - while (count--) { - if (buf[0] == 0x47) - dvb_dmx_swfilter_packet(demux, buf); - buf += 188; - } - - spin_unlock(&demux->lock); -} - -EXPORT_SYMBOL(dvb_dmx_swfilter_packets); - -static inline int find_next_packet(const u8 *buf, int pos, size_t count, - const int pktsize) -{ - int start = pos, lost; - - while (pos < count) { - if (buf[pos] == 0x47 || - (pktsize == 204 && buf[pos] == 0xB8)) - break; - pos++; - } - - lost = pos - start; - if (lost) { - /* This garbage is part of a valid packet? */ - int backtrack = pos - pktsize; - if (backtrack >= 0 && (buf[backtrack] == 0x47 || - (pktsize == 204 && buf[backtrack] == 0xB8))) - return backtrack; - } - - return pos; -} - -/* Filter all pktsize= 188 or 204 sized packets and skip garbage. */ -static inline void _dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, - size_t count, const int pktsize) -{ - int p = 0, i, j; - const u8 *q; - - spin_lock(&demux->lock); - - if (demux->tsbufp) { /* tsbuf[0] is now 0x47. */ - i = demux->tsbufp; - j = pktsize - i; - if (count < j) { - memcpy(&demux->tsbuf[i], buf, count); - demux->tsbufp += count; - goto bailout; - } - memcpy(&demux->tsbuf[i], buf, j); - if (demux->tsbuf[0] == 0x47) /* double check */ - dvb_dmx_swfilter_packet(demux, demux->tsbuf); - demux->tsbufp = 0; - p += j; - } - - while (1) { - p = find_next_packet(buf, p, count, pktsize); - if (p >= count) - break; - if (count - p < pktsize) - break; - - q = &buf[p]; - - if (pktsize == 204 && (*q == 0xB8)) { - memcpy(demux->tsbuf, q, 188); - demux->tsbuf[0] = 0x47; - q = demux->tsbuf; - } - dvb_dmx_swfilter_packet(demux, q); - p += pktsize; - } - - i = count - p; - if (i) { - memcpy(demux->tsbuf, &buf[p], i); - demux->tsbufp = i; - if (pktsize == 204 && demux->tsbuf[0] == 0xB8) - demux->tsbuf[0] = 0x47; - } - -bailout: - spin_unlock(&demux->lock); -} - -void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count) -{ - _dvb_dmx_swfilter(demux, buf, count, 188); -} -EXPORT_SYMBOL(dvb_dmx_swfilter); - -void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, size_t count) -{ - _dvb_dmx_swfilter(demux, buf, count, 204); -} -EXPORT_SYMBOL(dvb_dmx_swfilter_204); - -void dvb_dmx_swfilter_raw(struct dvb_demux *demux, const u8 *buf, size_t count) -{ - spin_lock(&demux->lock); - - demux->feed->cb.ts(buf, count, NULL, 0, &demux->feed->feed.ts, DMX_OK); - - spin_unlock(&demux->lock); -} -EXPORT_SYMBOL(dvb_dmx_swfilter_raw); - -static struct dvb_demux_filter *dvb_dmx_filter_alloc(struct dvb_demux *demux) -{ - int i; - - for (i = 0; i < demux->filternum; i++) - if (demux->filter[i].state == DMX_STATE_FREE) - break; - - if (i == demux->filternum) - return NULL; - - demux->filter[i].state = DMX_STATE_ALLOCATED; - - return &demux->filter[i]; -} - -static struct dvb_demux_feed *dvb_dmx_feed_alloc(struct dvb_demux *demux) -{ - int i; - - for (i = 0; i < demux->feednum; i++) - if (demux->feed[i].state == DMX_STATE_FREE) - break; - - if (i == demux->feednum) - return NULL; - - demux->feed[i].state = DMX_STATE_ALLOCATED; - - return &demux->feed[i]; -} - -static int dvb_demux_feed_find(struct dvb_demux_feed *feed) -{ - struct dvb_demux_feed *entry; - - list_for_each_entry(entry, &feed->demux->feed_list, list_head) - if (entry == feed) - return 1; - - return 0; -} - -static void dvb_demux_feed_add(struct dvb_demux_feed *feed) -{ - spin_lock_irq(&feed->demux->lock); - if (dvb_demux_feed_find(feed)) { - printk(KERN_ERR "%s: feed already in list (type=%x state=%x pid=%x)\n", - __func__, feed->type, feed->state, feed->pid); - goto out; - } - - list_add(&feed->list_head, &feed->demux->feed_list); -out: - spin_unlock_irq(&feed->demux->lock); -} - -static void dvb_demux_feed_del(struct dvb_demux_feed *feed) -{ - spin_lock_irq(&feed->demux->lock); - if (!(dvb_demux_feed_find(feed))) { - printk(KERN_ERR "%s: feed not in list (type=%x state=%x pid=%x)\n", - __func__, feed->type, feed->state, feed->pid); - goto out; - } - - list_del(&feed->list_head); -out: - spin_unlock_irq(&feed->demux->lock); -} - -static int dmx_ts_feed_set(struct dmx_ts_feed *ts_feed, u16 pid, int ts_type, - enum dmx_ts_pes pes_type, - size_t circular_buffer_size, struct timespec timeout) -{ - struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; - struct dvb_demux *demux = feed->demux; - - if (pid > DMX_MAX_PID) - return -EINVAL; - - if (mutex_lock_interruptible(&demux->mutex)) - return -ERESTARTSYS; - - if (ts_type & TS_DECODER) { - if (pes_type >= DMX_PES_OTHER) { - mutex_unlock(&demux->mutex); - return -EINVAL; - } - - if (demux->pesfilter[pes_type] && - demux->pesfilter[pes_type] != feed) { - mutex_unlock(&demux->mutex); - return -EINVAL; - } - - demux->pesfilter[pes_type] = feed; - demux->pids[pes_type] = pid; - } - - dvb_demux_feed_add(feed); - - feed->pid = pid; - feed->buffer_size = circular_buffer_size; - feed->timeout = timeout; - feed->ts_type = ts_type; - feed->pes_type = pes_type; - - if (feed->buffer_size) { -#ifdef NOBUFS - feed->buffer = NULL; -#else - feed->buffer = vmalloc(feed->buffer_size); - if (!feed->buffer) { - mutex_unlock(&demux->mutex); - return -ENOMEM; - } -#endif - } - - feed->state = DMX_STATE_READY; - mutex_unlock(&demux->mutex); - - return 0; -} - -static int dmx_ts_feed_start_filtering(struct dmx_ts_feed *ts_feed) -{ - struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; - struct dvb_demux *demux = feed->demux; - int ret; - - if (mutex_lock_interruptible(&demux->mutex)) - return -ERESTARTSYS; - - if (feed->state != DMX_STATE_READY || feed->type != DMX_TYPE_TS) { - mutex_unlock(&demux->mutex); - return -EINVAL; - } - - if (!demux->start_feed) { - mutex_unlock(&demux->mutex); - return -ENODEV; - } - - if ((ret = demux->start_feed(feed)) < 0) { - mutex_unlock(&demux->mutex); - return ret; - } - - spin_lock_irq(&demux->lock); - ts_feed->is_filtering = 1; - feed->state = DMX_STATE_GO; - spin_unlock_irq(&demux->lock); - mutex_unlock(&demux->mutex); - - return 0; -} - -static int dmx_ts_feed_stop_filtering(struct dmx_ts_feed *ts_feed) -{ - struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; - struct dvb_demux *demux = feed->demux; - int ret; - - mutex_lock(&demux->mutex); - - if (feed->state < DMX_STATE_GO) { - mutex_unlock(&demux->mutex); - return -EINVAL; - } - - if (!demux->stop_feed) { - mutex_unlock(&demux->mutex); - return -ENODEV; - } - - ret = demux->stop_feed(feed); - - spin_lock_irq(&demux->lock); - ts_feed->is_filtering = 0; - feed->state = DMX_STATE_ALLOCATED; - spin_unlock_irq(&demux->lock); - mutex_unlock(&demux->mutex); - - return ret; -} - -static int dvbdmx_allocate_ts_feed(struct dmx_demux *dmx, - struct dmx_ts_feed **ts_feed, - dmx_ts_cb callback) -{ - struct dvb_demux *demux = (struct dvb_demux *)dmx; - struct dvb_demux_feed *feed; - - if (mutex_lock_interruptible(&demux->mutex)) - return -ERESTARTSYS; - - if (!(feed = dvb_dmx_feed_alloc(demux))) { - mutex_unlock(&demux->mutex); - return -EBUSY; - } - - feed->type = DMX_TYPE_TS; - feed->cb.ts = callback; - feed->demux = demux; - feed->pid = 0xffff; - feed->peslen = 0xfffa; - feed->buffer = NULL; - - (*ts_feed) = &feed->feed.ts; - (*ts_feed)->parent = dmx; - (*ts_feed)->priv = NULL; - (*ts_feed)->is_filtering = 0; - (*ts_feed)->start_filtering = dmx_ts_feed_start_filtering; - (*ts_feed)->stop_filtering = dmx_ts_feed_stop_filtering; - (*ts_feed)->set = dmx_ts_feed_set; - - if (!(feed->filter = dvb_dmx_filter_alloc(demux))) { - feed->state = DMX_STATE_FREE; - mutex_unlock(&demux->mutex); - return -EBUSY; - } - - feed->filter->type = DMX_TYPE_TS; - feed->filter->feed = feed; - feed->filter->state = DMX_STATE_READY; - - mutex_unlock(&demux->mutex); - - return 0; -} - -static int dvbdmx_release_ts_feed(struct dmx_demux *dmx, - struct dmx_ts_feed *ts_feed) -{ - struct dvb_demux *demux = (struct dvb_demux *)dmx; - struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; - - mutex_lock(&demux->mutex); - - if (feed->state == DMX_STATE_FREE) { - mutex_unlock(&demux->mutex); - return -EINVAL; - } -#ifndef NOBUFS - vfree(feed->buffer); - feed->buffer = NULL; -#endif - - feed->state = DMX_STATE_FREE; - feed->filter->state = DMX_STATE_FREE; - - dvb_demux_feed_del(feed); - - feed->pid = 0xffff; - - if (feed->ts_type & TS_DECODER && feed->pes_type < DMX_PES_OTHER) - demux->pesfilter[feed->pes_type] = NULL; - - mutex_unlock(&demux->mutex); - return 0; -} - -/****************************************************************************** - * dmx_section_feed API calls - ******************************************************************************/ - -static int dmx_section_feed_allocate_filter(struct dmx_section_feed *feed, - struct dmx_section_filter **filter) -{ - struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; - struct dvb_demux *dvbdemux = dvbdmxfeed->demux; - struct dvb_demux_filter *dvbdmxfilter; - - if (mutex_lock_interruptible(&dvbdemux->mutex)) - return -ERESTARTSYS; - - dvbdmxfilter = dvb_dmx_filter_alloc(dvbdemux); - if (!dvbdmxfilter) { - mutex_unlock(&dvbdemux->mutex); - return -EBUSY; - } - - spin_lock_irq(&dvbdemux->lock); - *filter = &dvbdmxfilter->filter; - (*filter)->parent = feed; - (*filter)->priv = NULL; - dvbdmxfilter->feed = dvbdmxfeed; - dvbdmxfilter->type = DMX_TYPE_SEC; - dvbdmxfilter->state = DMX_STATE_READY; - dvbdmxfilter->next = dvbdmxfeed->filter; - dvbdmxfeed->filter = dvbdmxfilter; - spin_unlock_irq(&dvbdemux->lock); - - mutex_unlock(&dvbdemux->mutex); - return 0; -} - -static int dmx_section_feed_set(struct dmx_section_feed *feed, - u16 pid, size_t circular_buffer_size, - int check_crc) -{ - struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - - if (pid > 0x1fff) - return -EINVAL; - - if (mutex_lock_interruptible(&dvbdmx->mutex)) - return -ERESTARTSYS; - - dvb_demux_feed_add(dvbdmxfeed); - - dvbdmxfeed->pid = pid; - dvbdmxfeed->buffer_size = circular_buffer_size; - dvbdmxfeed->feed.sec.check_crc = check_crc; - -#ifdef NOBUFS - dvbdmxfeed->buffer = NULL; -#else - dvbdmxfeed->buffer = vmalloc(dvbdmxfeed->buffer_size); - if (!dvbdmxfeed->buffer) { - mutex_unlock(&dvbdmx->mutex); - return -ENOMEM; - } -#endif - - dvbdmxfeed->state = DMX_STATE_READY; - mutex_unlock(&dvbdmx->mutex); - return 0; -} - -static void prepare_secfilters(struct dvb_demux_feed *dvbdmxfeed) -{ - int i; - struct dvb_demux_filter *f; - struct dmx_section_filter *sf; - u8 mask, mode, doneq; - - if (!(f = dvbdmxfeed->filter)) - return; - do { - sf = &f->filter; - doneq = 0; - for (i = 0; i < DVB_DEMUX_MASK_MAX; i++) { - mode = sf->filter_mode[i]; - mask = sf->filter_mask[i]; - f->maskandmode[i] = mask & mode; - doneq |= f->maskandnotmode[i] = mask & ~mode; - } - f->doneq = doneq ? 1 : 0; - } while ((f = f->next)); -} - -static int dmx_section_feed_start_filtering(struct dmx_section_feed *feed) -{ - struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - int ret; - - if (mutex_lock_interruptible(&dvbdmx->mutex)) - return -ERESTARTSYS; - - if (feed->is_filtering) { - mutex_unlock(&dvbdmx->mutex); - return -EBUSY; - } - - if (!dvbdmxfeed->filter) { - mutex_unlock(&dvbdmx->mutex); - return -EINVAL; - } - - dvbdmxfeed->feed.sec.tsfeedp = 0; - dvbdmxfeed->feed.sec.secbuf = dvbdmxfeed->feed.sec.secbuf_base; - dvbdmxfeed->feed.sec.secbufp = 0; - dvbdmxfeed->feed.sec.seclen = 0; - - if (!dvbdmx->start_feed) { - mutex_unlock(&dvbdmx->mutex); - return -ENODEV; - } - - prepare_secfilters(dvbdmxfeed); - - if ((ret = dvbdmx->start_feed(dvbdmxfeed)) < 0) { - mutex_unlock(&dvbdmx->mutex); - return ret; - } - - spin_lock_irq(&dvbdmx->lock); - feed->is_filtering = 1; - dvbdmxfeed->state = DMX_STATE_GO; - spin_unlock_irq(&dvbdmx->lock); - - mutex_unlock(&dvbdmx->mutex); - return 0; -} - -static int dmx_section_feed_stop_filtering(struct dmx_section_feed *feed) -{ - struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - int ret; - - mutex_lock(&dvbdmx->mutex); - - if (!dvbdmx->stop_feed) { - mutex_unlock(&dvbdmx->mutex); - return -ENODEV; - } - - ret = dvbdmx->stop_feed(dvbdmxfeed); - - spin_lock_irq(&dvbdmx->lock); - dvbdmxfeed->state = DMX_STATE_READY; - feed->is_filtering = 0; - spin_unlock_irq(&dvbdmx->lock); - - mutex_unlock(&dvbdmx->mutex); - return ret; -} - -static int dmx_section_feed_release_filter(struct dmx_section_feed *feed, - struct dmx_section_filter *filter) -{ - struct dvb_demux_filter *dvbdmxfilter = (struct dvb_demux_filter *)filter, *f; - struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - - mutex_lock(&dvbdmx->mutex); - - if (dvbdmxfilter->feed != dvbdmxfeed) { - mutex_unlock(&dvbdmx->mutex); - return -EINVAL; - } - - if (feed->is_filtering) - feed->stop_filtering(feed); - - spin_lock_irq(&dvbdmx->lock); - f = dvbdmxfeed->filter; - - if (f == dvbdmxfilter) { - dvbdmxfeed->filter = dvbdmxfilter->next; - } else { - while (f->next != dvbdmxfilter) - f = f->next; - f->next = f->next->next; - } - - dvbdmxfilter->state = DMX_STATE_FREE; - spin_unlock_irq(&dvbdmx->lock); - mutex_unlock(&dvbdmx->mutex); - return 0; -} - -static int dvbdmx_allocate_section_feed(struct dmx_demux *demux, - struct dmx_section_feed **feed, - dmx_section_cb callback) -{ - struct dvb_demux *dvbdmx = (struct dvb_demux *)demux; - struct dvb_demux_feed *dvbdmxfeed; - - if (mutex_lock_interruptible(&dvbdmx->mutex)) - return -ERESTARTSYS; - - if (!(dvbdmxfeed = dvb_dmx_feed_alloc(dvbdmx))) { - mutex_unlock(&dvbdmx->mutex); - return -EBUSY; - } - - dvbdmxfeed->type = DMX_TYPE_SEC; - dvbdmxfeed->cb.sec = callback; - dvbdmxfeed->demux = dvbdmx; - dvbdmxfeed->pid = 0xffff; - dvbdmxfeed->feed.sec.secbuf = dvbdmxfeed->feed.sec.secbuf_base; - dvbdmxfeed->feed.sec.secbufp = dvbdmxfeed->feed.sec.seclen = 0; - dvbdmxfeed->feed.sec.tsfeedp = 0; - dvbdmxfeed->filter = NULL; - dvbdmxfeed->buffer = NULL; - - (*feed) = &dvbdmxfeed->feed.sec; - (*feed)->is_filtering = 0; - (*feed)->parent = demux; - (*feed)->priv = NULL; - - (*feed)->set = dmx_section_feed_set; - (*feed)->allocate_filter = dmx_section_feed_allocate_filter; - (*feed)->start_filtering = dmx_section_feed_start_filtering; - (*feed)->stop_filtering = dmx_section_feed_stop_filtering; - (*feed)->release_filter = dmx_section_feed_release_filter; - - mutex_unlock(&dvbdmx->mutex); - return 0; -} - -static int dvbdmx_release_section_feed(struct dmx_demux *demux, - struct dmx_section_feed *feed) -{ - struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; - struct dvb_demux *dvbdmx = (struct dvb_demux *)demux; - - mutex_lock(&dvbdmx->mutex); - - if (dvbdmxfeed->state == DMX_STATE_FREE) { - mutex_unlock(&dvbdmx->mutex); - return -EINVAL; - } -#ifndef NOBUFS - vfree(dvbdmxfeed->buffer); - dvbdmxfeed->buffer = NULL; -#endif - dvbdmxfeed->state = DMX_STATE_FREE; - - dvb_demux_feed_del(dvbdmxfeed); - - dvbdmxfeed->pid = 0xffff; - - mutex_unlock(&dvbdmx->mutex); - return 0; -} - -/****************************************************************************** - * dvb_demux kernel data API calls - ******************************************************************************/ - -static int dvbdmx_open(struct dmx_demux *demux) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - - if (dvbdemux->users >= MAX_DVB_DEMUX_USERS) - return -EUSERS; - - dvbdemux->users++; - return 0; -} - -static int dvbdmx_close(struct dmx_demux *demux) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - - if (dvbdemux->users == 0) - return -ENODEV; - - dvbdemux->users--; - //FIXME: release any unneeded resources if users==0 - return 0; -} - -static int dvbdmx_write(struct dmx_demux *demux, const char __user *buf, size_t count) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - void *p; - - if ((!demux->frontend) || (demux->frontend->source != DMX_MEMORY_FE)) - return -EINVAL; - - p = memdup_user(buf, count); - if (IS_ERR(p)) - return PTR_ERR(p); - if (mutex_lock_interruptible(&dvbdemux->mutex)) { - kfree(p); - return -ERESTARTSYS; - } - dvb_dmx_swfilter(dvbdemux, p, count); - kfree(p); - mutex_unlock(&dvbdemux->mutex); - - if (signal_pending(current)) - return -EINTR; - return count; -} - -static int dvbdmx_add_frontend(struct dmx_demux *demux, - struct dmx_frontend *frontend) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - struct list_head *head = &dvbdemux->frontend_list; - - list_add(&(frontend->connectivity_list), head); - - return 0; -} - -static int dvbdmx_remove_frontend(struct dmx_demux *demux, - struct dmx_frontend *frontend) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - struct list_head *pos, *n, *head = &dvbdemux->frontend_list; - - list_for_each_safe(pos, n, head) { - if (DMX_FE_ENTRY(pos) == frontend) { - list_del(pos); - return 0; - } - } - - return -ENODEV; -} - -static struct list_head *dvbdmx_get_frontends(struct dmx_demux *demux) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - - if (list_empty(&dvbdemux->frontend_list)) - return NULL; - - return &dvbdemux->frontend_list; -} - -static int dvbdmx_connect_frontend(struct dmx_demux *demux, - struct dmx_frontend *frontend) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - - if (demux->frontend) - return -EINVAL; - - mutex_lock(&dvbdemux->mutex); - - demux->frontend = frontend; - mutex_unlock(&dvbdemux->mutex); - return 0; -} - -static int dvbdmx_disconnect_frontend(struct dmx_demux *demux) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - - mutex_lock(&dvbdemux->mutex); - - demux->frontend = NULL; - mutex_unlock(&dvbdemux->mutex); - return 0; -} - -static int dvbdmx_get_pes_pids(struct dmx_demux *demux, u16 * pids) -{ - struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; - - memcpy(pids, dvbdemux->pids, 5 * sizeof(u16)); - return 0; -} - -int dvb_dmx_init(struct dvb_demux *dvbdemux) -{ - int i; - struct dmx_demux *dmx = &dvbdemux->dmx; - - dvbdemux->cnt_storage = NULL; - dvbdemux->users = 0; - dvbdemux->filter = vmalloc(dvbdemux->filternum * sizeof(struct dvb_demux_filter)); - - if (!dvbdemux->filter) - return -ENOMEM; - - dvbdemux->feed = vmalloc(dvbdemux->feednum * sizeof(struct dvb_demux_feed)); - if (!dvbdemux->feed) { - vfree(dvbdemux->filter); - dvbdemux->filter = NULL; - return -ENOMEM; - } - for (i = 0; i < dvbdemux->filternum; i++) { - dvbdemux->filter[i].state = DMX_STATE_FREE; - dvbdemux->filter[i].index = i; - } - for (i = 0; i < dvbdemux->feednum; i++) { - dvbdemux->feed[i].state = DMX_STATE_FREE; - dvbdemux->feed[i].index = i; - } - - dvbdemux->cnt_storage = vmalloc(MAX_PID + 1); - if (!dvbdemux->cnt_storage) - printk(KERN_WARNING "Couldn't allocate memory for TS/TEI check. Disabling it\n"); - - INIT_LIST_HEAD(&dvbdemux->frontend_list); - - for (i = 0; i < DMX_PES_OTHER; i++) { - dvbdemux->pesfilter[i] = NULL; - dvbdemux->pids[i] = 0xffff; - } - - INIT_LIST_HEAD(&dvbdemux->feed_list); - - dvbdemux->playing = 0; - dvbdemux->recording = 0; - dvbdemux->tsbufp = 0; - - if (!dvbdemux->check_crc32) - dvbdemux->check_crc32 = dvb_dmx_crc32; - - if (!dvbdemux->memcopy) - dvbdemux->memcopy = dvb_dmx_memcopy; - - dmx->frontend = NULL; - dmx->priv = dvbdemux; - dmx->open = dvbdmx_open; - dmx->close = dvbdmx_close; - dmx->write = dvbdmx_write; - dmx->allocate_ts_feed = dvbdmx_allocate_ts_feed; - dmx->release_ts_feed = dvbdmx_release_ts_feed; - dmx->allocate_section_feed = dvbdmx_allocate_section_feed; - dmx->release_section_feed = dvbdmx_release_section_feed; - - dmx->add_frontend = dvbdmx_add_frontend; - dmx->remove_frontend = dvbdmx_remove_frontend; - dmx->get_frontends = dvbdmx_get_frontends; - dmx->connect_frontend = dvbdmx_connect_frontend; - dmx->disconnect_frontend = dvbdmx_disconnect_frontend; - dmx->get_pes_pids = dvbdmx_get_pes_pids; - - mutex_init(&dvbdemux->mutex); - spin_lock_init(&dvbdemux->lock); - - return 0; -} - -EXPORT_SYMBOL(dvb_dmx_init); - -void dvb_dmx_release(struct dvb_demux *dvbdemux) -{ - vfree(dvbdemux->cnt_storage); - vfree(dvbdemux->filter); - vfree(dvbdemux->feed); -} - -EXPORT_SYMBOL(dvb_dmx_release); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_demux.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,151 +0,0 @@ -/* - * dvb_demux.h: DVB kernel demux API - * - * Copyright (C) 2000-2001 Marcus Metzler & Ralph Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVB_DEMUX_H_ -#define _DVB_DEMUX_H_ - -#include -#include -#include -#include - -#include "demux.h" - -#define DMX_TYPE_TS 0 -#define DMX_TYPE_SEC 1 -#define DMX_TYPE_PES 2 - -#define DMX_STATE_FREE 0 -#define DMX_STATE_ALLOCATED 1 -#define DMX_STATE_SET 2 -#define DMX_STATE_READY 3 -#define DMX_STATE_GO 4 - -#define DVB_DEMUX_MASK_MAX 18 - -#define MAX_PID 0x1fff - -#define SPEED_PKTS_INTERVAL 50000 - -struct dvb_demux_filter { - struct dmx_section_filter filter; - u8 maskandmode[DMX_MAX_FILTER_SIZE]; - u8 maskandnotmode[DMX_MAX_FILTER_SIZE]; - int doneq; - - struct dvb_demux_filter *next; - struct dvb_demux_feed *feed; - int index; - int state; - int type; - - u16 hw_handle; - struct timer_list timer; -}; - -#define DMX_FEED_ENTRY(pos) list_entry(pos, struct dvb_demux_feed, list_head) - -struct dvb_demux_feed { - union { - struct dmx_ts_feed ts; - struct dmx_section_feed sec; - } feed; - - union { - dmx_ts_cb ts; - dmx_section_cb sec; - } cb; - - struct dvb_demux *demux; - void *priv; - int type; - int state; - u16 pid; - u8 *buffer; - int buffer_size; - - struct timespec timeout; - struct dvb_demux_filter *filter; - - int ts_type; - enum dmx_ts_pes pes_type; - - int cc; - int pusi_seen; /* prevents feeding of garbage from previous section */ - - u16 peslen; - - struct list_head list_head; - unsigned int index; /* a unique index for each feed (can be used as hardware pid filter index) */ -}; - -struct dvb_demux { - struct dmx_demux dmx; - void *priv; - int filternum; - int feednum; - int (*start_feed)(struct dvb_demux_feed *feed); - int (*stop_feed)(struct dvb_demux_feed *feed); - int (*write_to_decoder)(struct dvb_demux_feed *feed, - const u8 *buf, size_t len); - u32 (*check_crc32)(struct dvb_demux_feed *feed, - const u8 *buf, size_t len); - void (*memcopy)(struct dvb_demux_feed *feed, u8 *dst, - const u8 *src, size_t len); - - int users; -#define MAX_DVB_DEMUX_USERS 10 - struct dvb_demux_filter *filter; - struct dvb_demux_feed *feed; - - struct list_head frontend_list; - - struct dvb_demux_feed *pesfilter[DMX_PES_OTHER]; - u16 pids[DMX_PES_OTHER]; - int playing; - int recording; - -#define DMX_MAX_PID 0x2000 - struct list_head feed_list; - u8 tsbuf[204]; - int tsbufp; - - struct mutex mutex; - spinlock_t lock; - - uint8_t *cnt_storage; /* for TS continuity check */ - - struct timespec speed_last_time; /* for TS speed check */ - uint32_t speed_pkts_cnt; /* for TS speed check */ -}; - -int dvb_dmx_init(struct dvb_demux *dvbdemux); -void dvb_dmx_release(struct dvb_demux *dvbdemux); -void dvb_dmx_swfilter_packets(struct dvb_demux *dvbdmx, const u8 *buf, - size_t count); -void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count); -void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, - size_t count); -void dvb_dmx_swfilter_raw(struct dvb_demux *demux, const u8 *buf, - size_t count); - -#endif /* _DVB_DEMUX_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,603 +0,0 @@ -#include -#include -#include -#include "dvb_filter.h" - -#if 0 -static unsigned int bitrates[3][16] = -{{0,32,64,96,128,160,192,224,256,288,320,352,384,416,448,0}, - {0,32,48,56,64,80,96,112,128,160,192,224,256,320,384,0}, - {0,32,40,48,56,64,80,96,112,128,160,192,224,256,320,0}}; -#endif - -static u32 freq[4] = {480, 441, 320, 0}; - -static unsigned int ac3_bitrates[32] = - {32,40,48,56,64,80,96,112,128,160,192,224,256,320,384,448,512,576,640, - 0,0,0,0,0,0,0,0,0,0,0,0,0}; - -static u32 ac3_frames[3][32] = - {{64,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024, - 1152,1280,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {69,87,104,121,139,174,208,243,278,348,417,487,557,696,835,975,1114, - 1253,1393,0,0,0,0,0,0,0,0,0,0,0,0,0}, - {96,120,144,168,192,240,288,336,384,480,576,672,768,960,1152,1344, - 1536,1728,1920,0,0,0,0,0,0,0,0,0,0,0,0,0}}; - - - -#if 0 -static void setup_ts2pes(ipack *pa, ipack *pv, u16 *pida, u16 *pidv, - void (*pes_write)(u8 *buf, int count, void *data), - void *priv) -{ - dvb_filter_ipack_init(pa, IPACKS, pes_write); - dvb_filter_ipack_init(pv, IPACKS, pes_write); - pa->pid = pida; - pv->pid = pidv; - pa->data = priv; - pv->data = priv; -} -#endif - -#if 0 -static void ts_to_pes(ipack *p, u8 *buf) // don't need count (=188) -{ - u8 off = 0; - - if (!buf || !p ){ - printk("NULL POINTER IDIOT\n"); - return; - } - if (buf[1]&PAY_START) { - if (p->plength == MMAX_PLENGTH-6 && p->found>6){ - p->plength = p->found-6; - p->found = 0; - send_ipack(p); - dvb_filter_ipack_reset(p); - } - } - if (buf[3] & ADAPT_FIELD) { // adaptation field? - off = buf[4] + 1; - if (off+4 > 187) return; - } - dvb_filter_instant_repack(buf+4+off, TS_SIZE-4-off, p); -} -#endif - -#if 0 -/* needs 5 byte input, returns picture coding type*/ -static int read_picture_header(u8 *headr, struct mpg_picture *pic, int field, int pr) -{ - u8 pct; - - if (pr) printk( "Pic header: "); - pic->temporal_reference[field] = (( headr[0] << 2 ) | - (headr[1] & 0x03) )& 0x03ff; - if (pr) printk( " temp ref: 0x%04x", pic->temporal_reference[field]); - - pct = ( headr[1] >> 2 ) & 0x07; - pic->picture_coding_type[field] = pct; - if (pr) { - switch(pct){ - case I_FRAME: - printk( " I-FRAME"); - break; - case B_FRAME: - printk( " B-FRAME"); - break; - case P_FRAME: - printk( " P-FRAME"); - break; - } - } - - - pic->vinfo.vbv_delay = (( headr[1] >> 5 ) | ( headr[2] << 3) | - ( (headr[3] & 0x1F) << 11) ) & 0xffff; - - if (pr) printk( " vbv delay: 0x%04x", pic->vinfo.vbv_delay); - - pic->picture_header_parameter = ( headr[3] & 0xe0 ) | - ((headr[4] & 0x80) >> 3); - - if ( pct == B_FRAME ){ - pic->picture_header_parameter |= ( headr[4] >> 3 ) & 0x0f; - } - if (pr) printk( " pic head param: 0x%x", - pic->picture_header_parameter); - - return pct; -} -#endif - -#if 0 -/* needs 4 byte input */ -static int read_gop_header(u8 *headr, struct mpg_picture *pic, int pr) -{ - if (pr) printk("GOP header: "); - - pic->time_code = (( headr[0] << 17 ) | ( headr[1] << 9) | - ( headr[2] << 1 ) | (headr[3] &0x01)) & 0x1ffffff; - - if (pr) printk(" time: %d:%d.%d ", (headr[0]>>2)& 0x1F, - ((headr[0]<<4)& 0x30)| ((headr[1]>>4)& 0x0F), - ((headr[1]<<3)& 0x38)| ((headr[2]>>5)& 0x0F)); - - if ( ( headr[3] & 0x40 ) != 0 ){ - pic->closed_gop = 1; - } else { - pic->closed_gop = 0; - } - if (pr) printk("closed: %d", pic->closed_gop); - - if ( ( headr[3] & 0x20 ) != 0 ){ - pic->broken_link = 1; - } else { - pic->broken_link = 0; - } - if (pr) printk(" broken: %d\n", pic->broken_link); - - return 0; -} -#endif - -#if 0 -/* needs 8 byte input */ -static int read_sequence_header(u8 *headr, struct dvb_video_info *vi, int pr) -{ - int sw; - int form = -1; - - if (pr) printk("Reading sequence header\n"); - - vi->horizontal_size = ((headr[1] &0xF0) >> 4) | (headr[0] << 4); - vi->vertical_size = ((headr[1] &0x0F) << 8) | (headr[2]); - - sw = (int)((headr[3]&0xF0) >> 4) ; - - switch( sw ){ - case 1: - if (pr) - printk("Videostream: ASPECT: 1:1"); - vi->aspect_ratio = 100; - break; - case 2: - if (pr) - printk("Videostream: ASPECT: 4:3"); - vi->aspect_ratio = 133; - break; - case 3: - if (pr) - printk("Videostream: ASPECT: 16:9"); - vi->aspect_ratio = 177; - break; - case 4: - if (pr) - printk("Videostream: ASPECT: 2.21:1"); - vi->aspect_ratio = 221; - break; - - case 5 ... 15: - if (pr) - printk("Videostream: ASPECT: reserved"); - vi->aspect_ratio = 0; - break; - - default: - vi->aspect_ratio = 0; - return -1; - } - - if (pr) - printk(" Size = %dx%d",vi->horizontal_size,vi->vertical_size); - - sw = (int)(headr[3]&0x0F); - - switch ( sw ) { - case 1: - if (pr) - printk(" FRate: 23.976 fps"); - vi->framerate = 23976; - form = -1; - break; - case 2: - if (pr) - printk(" FRate: 24 fps"); - vi->framerate = 24000; - form = -1; - break; - case 3: - if (pr) - printk(" FRate: 25 fps"); - vi->framerate = 25000; - form = VIDEO_MODE_PAL; - break; - case 4: - if (pr) - printk(" FRate: 29.97 fps"); - vi->framerate = 29970; - form = VIDEO_MODE_NTSC; - break; - case 5: - if (pr) - printk(" FRate: 30 fps"); - vi->framerate = 30000; - form = VIDEO_MODE_NTSC; - break; - case 6: - if (pr) - printk(" FRate: 50 fps"); - vi->framerate = 50000; - form = VIDEO_MODE_PAL; - break; - case 7: - if (pr) - printk(" FRate: 60 fps"); - vi->framerate = 60000; - form = VIDEO_MODE_NTSC; - break; - } - - vi->bit_rate = (headr[4] << 10) | (headr[5] << 2) | (headr[6] & 0x03); - - vi->vbv_buffer_size - = (( headr[6] & 0xF8) >> 3 ) | (( headr[7] & 0x1F )<< 5); - - if (pr){ - printk(" BRate: %d Mbit/s",4*(vi->bit_rate)/10000); - printk(" vbvbuffer %d",16*1024*(vi->vbv_buffer_size)); - printk("\n"); - } - - vi->video_format = form; - - return 0; -} -#endif - - -#if 0 -static int get_vinfo(u8 *mbuf, int count, struct dvb_video_info *vi, int pr) -{ - u8 *headr; - int found = 0; - int c = 0; - - while (found < 4 && c+4 < count){ - u8 *b; - - b = mbuf+c; - if ( b[0] == 0x00 && b[1] == 0x00 && b[2] == 0x01 - && b[3] == 0xb3) found = 4; - else { - c++; - } - } - - if (! found) return -1; - c += 4; - if (c+12 >= count) return -1; - headr = mbuf+c; - if (read_sequence_header(headr, vi, pr) < 0) return -1; - vi->off = c-4; - return 0; -} -#endif - - -#if 0 -static int get_ainfo(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr) -{ - u8 *headr; - int found = 0; - int c = 0; - int fr = 0; - - while (found < 2 && c < count){ - u8 b[2]; - memcpy( b, mbuf+c, 2); - - if ( b[0] == 0xff && (b[1] & 0xf8) == 0xf8) - found = 2; - else { - c++; - } - } - - if (!found) return -1; - - if (c+3 >= count) return -1; - headr = mbuf+c; - - ai->layer = (headr[1] & 0x06) >> 1; - - if (pr) - printk("Audiostream: Layer: %d", 4-ai->layer); - - - ai->bit_rate = bitrates[(3-ai->layer)][(headr[2] >> 4 )]*1000; - - if (pr){ - if (ai->bit_rate == 0) - printk(" Bit rate: free"); - else if (ai->bit_rate == 0xf) - printk(" BRate: reserved"); - else - printk(" BRate: %d kb/s", ai->bit_rate/1000); - } - - fr = (headr[2] & 0x0c ) >> 2; - ai->frequency = freq[fr]*100; - if (pr){ - if (ai->frequency == 3) - printk(" Freq: reserved\n"); - else - printk(" Freq: %d kHz\n",ai->frequency); - - } - ai->off = c; - return 0; -} -#endif - - -int dvb_filter_get_ac3info(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr) -{ - u8 *headr; - int found = 0; - int c = 0; - u8 frame = 0; - int fr = 0; - - while ( !found && c < count){ - u8 *b = mbuf+c; - - if ( b[0] == 0x0b && b[1] == 0x77 ) - found = 1; - else { - c++; - } - } - - if (!found) return -1; - if (pr) - printk("Audiostream: AC3"); - - ai->off = c; - if (c+5 >= count) return -1; - - ai->layer = 0; // 0 for AC3 - headr = mbuf+c+2; - - frame = (headr[2]&0x3f); - ai->bit_rate = ac3_bitrates[frame >> 1]*1000; - - if (pr) - printk(" BRate: %d kb/s", (int) ai->bit_rate/1000); - - ai->frequency = (headr[2] & 0xc0 ) >> 6; - fr = (headr[2] & 0xc0 ) >> 6; - ai->frequency = freq[fr]*100; - if (pr) printk (" Freq: %d Hz\n", (int) ai->frequency); - - - ai->framesize = ac3_frames[fr][frame >> 1]; - if ((frame & 1) && (fr == 1)) ai->framesize++; - ai->framesize = ai->framesize << 1; - if (pr) printk (" Framesize %d\n",(int) ai->framesize); - - - return 0; -} -EXPORT_SYMBOL(dvb_filter_get_ac3info); - - -#if 0 -static u8 *skip_pes_header(u8 **bufp) -{ - u8 *inbuf = *bufp; - u8 *buf = inbuf; - u8 *pts = NULL; - int skip = 0; - - static const int mpeg1_skip_table[16] = { - 1, 0xffff, 5, 10, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff - }; - - - if ((inbuf[6] & 0xc0) == 0x80){ /* mpeg2 */ - if (buf[7] & PTS_ONLY) - pts = buf+9; - else pts = NULL; - buf = inbuf + 9 + inbuf[8]; - } else { /* mpeg1 */ - for (buf = inbuf + 6; *buf == 0xff; buf++) - if (buf == inbuf + 6 + 16) { - break; - } - if ((*buf & 0xc0) == 0x40) - buf += 2; - skip = mpeg1_skip_table [*buf >> 4]; - if (skip == 5 || skip == 10) pts = buf; - else pts = NULL; - - buf += mpeg1_skip_table [*buf >> 4]; - } - - *bufp = buf; - return pts; -} -#endif - -#if 0 -static void initialize_quant_matrix( u32 *matrix ) -{ - int i; - - matrix[0] = 0x08101013; - matrix[1] = 0x10131616; - matrix[2] = 0x16161616; - matrix[3] = 0x1a181a1b; - matrix[4] = 0x1b1b1a1a; - matrix[5] = 0x1a1a1b1b; - matrix[6] = 0x1b1d1d1d; - matrix[7] = 0x2222221d; - matrix[8] = 0x1d1d1b1b; - matrix[9] = 0x1d1d2020; - matrix[10] = 0x22222526; - matrix[11] = 0x25232322; - matrix[12] = 0x23262628; - matrix[13] = 0x28283030; - matrix[14] = 0x2e2e3838; - matrix[15] = 0x3a454553; - - for ( i = 16 ; i < 32 ; i++ ) - matrix[i] = 0x10101010; -} -#endif - -#if 0 -static void initialize_mpg_picture(struct mpg_picture *pic) -{ - int i; - - /* set MPEG1 */ - pic->mpeg1_flag = 1; - pic->profile_and_level = 0x4A ; /* MP@LL */ - pic->progressive_sequence = 1; - pic->low_delay = 0; - - pic->sequence_display_extension_flag = 0; - for ( i = 0 ; i < 4 ; i++ ){ - pic->frame_centre_horizontal_offset[i] = 0; - pic->frame_centre_vertical_offset[i] = 0; - } - pic->last_frame_centre_horizontal_offset = 0; - pic->last_frame_centre_vertical_offset = 0; - - pic->picture_display_extension_flag[0] = 0; - pic->picture_display_extension_flag[1] = 0; - pic->sequence_header_flag = 0; - pic->gop_flag = 0; - pic->sequence_end_flag = 0; -} -#endif - -#if 0 -static void mpg_set_picture_parameter( int32_t field_type, struct mpg_picture *pic ) -{ - int16_t last_h_offset; - int16_t last_v_offset; - - int16_t *p_h_offset; - int16_t *p_v_offset; - - if ( pic->mpeg1_flag ){ - pic->picture_structure[field_type] = VIDEO_FRAME_PICTURE; - pic->top_field_first = 0; - pic->repeat_first_field = 0; - pic->progressive_frame = 1; - pic->picture_coding_parameter = 0x000010; - } - - /* Reset flag */ - pic->picture_display_extension_flag[field_type] = 0; - - last_h_offset = pic->last_frame_centre_horizontal_offset; - last_v_offset = pic->last_frame_centre_vertical_offset; - if ( field_type == FIRST_FIELD ){ - p_h_offset = pic->frame_centre_horizontal_offset; - p_v_offset = pic->frame_centre_vertical_offset; - *p_h_offset = last_h_offset; - *(p_h_offset + 1) = last_h_offset; - *(p_h_offset + 2) = last_h_offset; - *p_v_offset = last_v_offset; - *(p_v_offset + 1) = last_v_offset; - *(p_v_offset + 2) = last_v_offset; - } else { - pic->frame_centre_horizontal_offset[3] = last_h_offset; - pic->frame_centre_vertical_offset[3] = last_v_offset; - } -} -#endif - -#if 0 -static void init_mpg_picture( struct mpg_picture *pic, int chan, int32_t field_type) -{ - pic->picture_header = 0; - pic->sequence_header_data - = ( INIT_HORIZONTAL_SIZE << 20 ) - | ( INIT_VERTICAL_SIZE << 8 ) - | ( INIT_ASPECT_RATIO << 4 ) - | ( INIT_FRAME_RATE ); - pic->mpeg1_flag = 0; - pic->vinfo.horizontal_size - = INIT_DISP_HORIZONTAL_SIZE; - pic->vinfo.vertical_size - = INIT_DISP_VERTICAL_SIZE; - pic->picture_display_extension_flag[field_type] - = 0; - pic->pts_flag[field_type] = 0; - - pic->sequence_gop_header = 0; - pic->picture_header = 0; - pic->sequence_header_flag = 0; - pic->gop_flag = 0; - pic->sequence_end_flag = 0; - pic->sequence_display_extension_flag = 0; - pic->last_frame_centre_horizontal_offset = 0; - pic->last_frame_centre_vertical_offset = 0; - pic->channel = chan; -} -#endif - -void dvb_filter_pes2ts_init(struct dvb_filter_pes2ts *p2ts, unsigned short pid, - dvb_filter_pes2ts_cb_t *cb, void *priv) -{ - unsigned char *buf=p2ts->buf; - - buf[0]=0x47; - buf[1]=(pid>>8); - buf[2]=pid&0xff; - p2ts->cc=0; - p2ts->cb=cb; - p2ts->priv=priv; -} -EXPORT_SYMBOL(dvb_filter_pes2ts_init); - -int dvb_filter_pes2ts(struct dvb_filter_pes2ts *p2ts, unsigned char *pes, - int len, int payload_start) -{ - unsigned char *buf=p2ts->buf; - int ret=0, rest; - - //len=6+((pes[4]<<8)|pes[5]); - - if (payload_start) - buf[1]|=0x40; - else - buf[1]&=~0x40; - while (len>=184) { - buf[3]=0x10|((p2ts->cc++)&0x0f); - memcpy(buf+4, pes, 184); - if ((ret=p2ts->cb(p2ts->priv, buf))) - return ret; - len-=184; pes+=184; - buf[1]&=~0x40; - } - if (!len) - return 0; - buf[3]=0x30|((p2ts->cc++)&0x0f); - rest=183-len; - if (rest) { - buf[5]=0x00; - if (rest-1) - memset(buf+6, 0xff, rest-1); - } - buf[4]=rest; - memcpy(buf+5+rest, pes, len); - return p2ts->cb(p2ts->priv, buf); -} -EXPORT_SYMBOL(dvb_filter_pes2ts); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_filter.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,246 +0,0 @@ -/* - * dvb_filter.h - * - * Copyright (C) 2003 Convergence GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _DVB_FILTER_H_ -#define _DVB_FILTER_H_ - -#include - -#include "demux.h" - -typedef int (dvb_filter_pes2ts_cb_t) (void *, unsigned char *); - -struct dvb_filter_pes2ts { - unsigned char buf[188]; - unsigned char cc; - dvb_filter_pes2ts_cb_t *cb; - void *priv; -}; - -void dvb_filter_pes2ts_init(struct dvb_filter_pes2ts *p2ts, unsigned short pid, - dvb_filter_pes2ts_cb_t *cb, void *priv); - -int dvb_filter_pes2ts(struct dvb_filter_pes2ts *p2ts, unsigned char *pes, - int len, int payload_start); - - -#define PROG_STREAM_MAP 0xBC -#define PRIVATE_STREAM1 0xBD -#define PADDING_STREAM 0xBE -#define PRIVATE_STREAM2 0xBF -#define AUDIO_STREAM_S 0xC0 -#define AUDIO_STREAM_E 0xDF -#define VIDEO_STREAM_S 0xE0 -#define VIDEO_STREAM_E 0xEF -#define ECM_STREAM 0xF0 -#define EMM_STREAM 0xF1 -#define DSM_CC_STREAM 0xF2 -#define ISO13522_STREAM 0xF3 -#define PROG_STREAM_DIR 0xFF - -#define DVB_PICTURE_START 0x00 -#define DVB_USER_START 0xb2 -#define DVB_SEQUENCE_HEADER 0xb3 -#define DVB_SEQUENCE_ERROR 0xb4 -#define DVB_EXTENSION_START 0xb5 -#define DVB_SEQUENCE_END 0xb7 -#define DVB_GOP_START 0xb8 -#define DVB_EXCEPT_SLICE 0xb0 - -#define SEQUENCE_EXTENSION 0x01 -#define SEQUENCE_DISPLAY_EXTENSION 0x02 -#define PICTURE_CODING_EXTENSION 0x08 -#define QUANT_MATRIX_EXTENSION 0x03 -#define PICTURE_DISPLAY_EXTENSION 0x07 - -#define I_FRAME 0x01 -#define B_FRAME 0x02 -#define P_FRAME 0x03 - -/* Initialize sequence_data */ -#define INIT_HORIZONTAL_SIZE 720 -#define INIT_VERTICAL_SIZE 576 -#define INIT_ASPECT_RATIO 0x02 -#define INIT_FRAME_RATE 0x03 -#define INIT_DISP_HORIZONTAL_SIZE 540 -#define INIT_DISP_VERTICAL_SIZE 576 - - -//flags2 -#define PTS_DTS_FLAGS 0xC0 -#define ESCR_FLAG 0x20 -#define ES_RATE_FLAG 0x10 -#define DSM_TRICK_FLAG 0x08 -#define ADD_CPY_FLAG 0x04 -#define PES_CRC_FLAG 0x02 -#define PES_EXT_FLAG 0x01 - -//pts_dts flags -#define PTS_ONLY 0x80 -#define PTS_DTS 0xC0 - -#define TS_SIZE 188 -#define TRANS_ERROR 0x80 -#define PAY_START 0x40 -#define TRANS_PRIO 0x20 -#define PID_MASK_HI 0x1F -//flags -#define TRANS_SCRMBL1 0x80 -#define TRANS_SCRMBL2 0x40 -#define ADAPT_FIELD 0x20 -#define PAYLOAD 0x10 -#define COUNT_MASK 0x0F - -// adaptation flags -#define DISCON_IND 0x80 -#define RAND_ACC_IND 0x40 -#define ES_PRI_IND 0x20 -#define PCR_FLAG 0x10 -#define OPCR_FLAG 0x08 -#define SPLICE_FLAG 0x04 -#define TRANS_PRIV 0x02 -#define ADAP_EXT_FLAG 0x01 - -// adaptation extension flags -#define LTW_FLAG 0x80 -#define PIECE_RATE 0x40 -#define SEAM_SPLICE 0x20 - - -#define MAX_PLENGTH 0xFFFF -#define MMAX_PLENGTH (256*MAX_PLENGTH) - -#ifndef IPACKS -#define IPACKS 2048 -#endif - -struct ipack { - int size; - int found; - u8 *buf; - u8 cid; - u32 plength; - u8 plen[2]; - u8 flag1; - u8 flag2; - u8 hlength; - u8 pts[5]; - u16 *pid; - int mpeg; - u8 check; - int which; - int done; - void *data; - void (*func)(u8 *buf, int size, void *priv); - int count; - int repack_subids; -}; - -struct dvb_video_info { - u32 horizontal_size; - u32 vertical_size; - u32 aspect_ratio; - u32 framerate; - u32 video_format; - u32 bit_rate; - u32 comp_bit_rate; - u32 vbv_buffer_size; - s16 vbv_delay; - u32 CSPF; - u32 off; -}; - -#define OFF_SIZE 4 -#define FIRST_FIELD 0 -#define SECOND_FIELD 1 -#define VIDEO_FRAME_PICTURE 0x03 - -struct mpg_picture { - int channel; - struct dvb_video_info vinfo; - u32 *sequence_gop_header; - u32 *picture_header; - s32 time_code; - int low_delay; - int closed_gop; - int broken_link; - int sequence_header_flag; - int gop_flag; - int sequence_end_flag; - - u8 profile_and_level; - s32 picture_coding_parameter; - u32 matrix[32]; - s8 matrix_change_flag; - - u8 picture_header_parameter; - /* bit 0 - 2: bwd f code - bit 3 : fpb vector - bit 4 - 6: fwd f code - bit 7 : fpf vector */ - - int mpeg1_flag; - int progressive_sequence; - int sequence_display_extension_flag; - u32 sequence_header_data; - s16 last_frame_centre_horizontal_offset; - s16 last_frame_centre_vertical_offset; - - u32 pts[2]; /* [0] 1st field, [1] 2nd field */ - int top_field_first; - int repeat_first_field; - int progressive_frame; - int bank; - int forward_bank; - int backward_bank; - int compress; - s16 frame_centre_horizontal_offset[OFF_SIZE]; - /* [0-2] 1st field, [3] 2nd field */ - s16 frame_centre_vertical_offset[OFF_SIZE]; - /* [0-2] 1st field, [3] 2nd field */ - s16 temporal_reference[2]; - /* [0] 1st field, [1] 2nd field */ - - s8 picture_coding_type[2]; - /* [0] 1st field, [1] 2nd field */ - s8 picture_structure[2]; - /* [0] 1st field, [1] 2nd field */ - s8 picture_display_extension_flag[2]; - /* [0] 1st field, [1] 2nd field */ - /* picture_display_extenion() 0:no 1:exit*/ - s8 pts_flag[2]; - /* [0] 1st field, [1] 2nd field */ -}; - -struct dvb_audio_info { - int layer; - u32 bit_rate; - u32 frequency; - u32 mode; - u32 mode_extension ; - u32 emphasis; - u32 framesize; - u32 off; -}; - -int dvb_filter_get_ac3info(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr); - - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,2696 +0,0 @@ -/* - * dvb_frontend.c: DVB frontend tuning interface/thread - * - * - * Copyright (C) 1999-2001 Ralph Metzler - * Marcus Metzler - * Holger Waechtler - * for convergence integrated media GmbH - * - * Copyright (C) 2004 Andrew de Quincey (tuning thread cleanup) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -/* Enables DVBv3 compatibility bits at the headers */ -#define __DVB_CORE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "dvbdev.h" -#include - -static int dvb_frontend_debug; -static int dvb_shutdown_timeout; -static int dvb_force_auto_inversion; -static int dvb_override_tune_delay; -static int dvb_powerdown_on_sleep = 1; -static int dvb_mfe_wait_time = 5; - -module_param_named(frontend_debug, dvb_frontend_debug, int, 0644); -MODULE_PARM_DESC(frontend_debug, "Turn on/off frontend core debugging (default:off)."); -module_param(dvb_shutdown_timeout, int, 0644); -MODULE_PARM_DESC(dvb_shutdown_timeout, "wait seconds after close() before suspending hardware"); -module_param(dvb_force_auto_inversion, int, 0644); -MODULE_PARM_DESC(dvb_force_auto_inversion, "0: normal (default), 1: INVERSION_AUTO forced always"); -module_param(dvb_override_tune_delay, int, 0644); -MODULE_PARM_DESC(dvb_override_tune_delay, "0: normal (default), >0 => delay in milliseconds to wait for lock after a tune attempt"); -module_param(dvb_powerdown_on_sleep, int, 0644); -MODULE_PARM_DESC(dvb_powerdown_on_sleep, "0: do not power down, 1: turn LNB voltage off on sleep (default)"); -module_param(dvb_mfe_wait_time, int, 0644); -MODULE_PARM_DESC(dvb_mfe_wait_time, "Wait up to seconds on open() for multi-frontend to become available (default:5 seconds)"); - -#define FESTATE_IDLE 1 -#define FESTATE_RETUNE 2 -#define FESTATE_TUNING_FAST 4 -#define FESTATE_TUNING_SLOW 8 -#define FESTATE_TUNED 16 -#define FESTATE_ZIGZAG_FAST 32 -#define FESTATE_ZIGZAG_SLOW 64 -#define FESTATE_DISEQC 128 -#define FESTATE_ERROR 256 -#define FESTATE_WAITFORLOCK (FESTATE_TUNING_FAST | FESTATE_TUNING_SLOW | FESTATE_ZIGZAG_FAST | FESTATE_ZIGZAG_SLOW | FESTATE_DISEQC) -#define FESTATE_SEARCHING_FAST (FESTATE_TUNING_FAST | FESTATE_ZIGZAG_FAST) -#define FESTATE_SEARCHING_SLOW (FESTATE_TUNING_SLOW | FESTATE_ZIGZAG_SLOW) -#define FESTATE_LOSTLOCK (FESTATE_ZIGZAG_FAST | FESTATE_ZIGZAG_SLOW) - -#define FE_ALGO_HW 1 -/* - * FESTATE_IDLE. No tuning parameters have been supplied and the loop is idling. - * FESTATE_RETUNE. Parameters have been supplied, but we have not yet performed the first tune. - * FESTATE_TUNING_FAST. Tuning parameters have been supplied and fast zigzag scan is in progress. - * FESTATE_TUNING_SLOW. Tuning parameters have been supplied. Fast zigzag failed, so we're trying again, but slower. - * FESTATE_TUNED. The frontend has successfully locked on. - * FESTATE_ZIGZAG_FAST. The lock has been lost, and a fast zigzag has been initiated to try and regain it. - * FESTATE_ZIGZAG_SLOW. The lock has been lost. Fast zigzag has been failed, so we're trying again, but slower. - * FESTATE_DISEQC. A DISEQC command has just been issued. - * FESTATE_WAITFORLOCK. When we're waiting for a lock. - * FESTATE_SEARCHING_FAST. When we're searching for a signal using a fast zigzag scan. - * FESTATE_SEARCHING_SLOW. When we're searching for a signal using a slow zigzag scan. - * FESTATE_LOSTLOCK. When the lock has been lost, and we're searching it again. - */ - -#define DVB_FE_NO_EXIT 0 -#define DVB_FE_NORMAL_EXIT 1 -#define DVB_FE_DEVICE_REMOVED 2 - -static DEFINE_MUTEX(frontend_mutex); - -struct dvb_frontend_private { - - /* thread/frontend values */ - struct dvb_device *dvbdev; - struct dvb_frontend_parameters parameters_out; - struct dvb_fe_events events; - struct semaphore sem; - struct list_head list_head; - wait_queue_head_t wait_queue; - struct task_struct *thread; - unsigned long release_jiffies; - unsigned int exit; - unsigned int wakeup; - fe_status_t status; - unsigned long tune_mode_flags; - unsigned int delay; - unsigned int reinitialise; - int tone; - int voltage; - - /* swzigzag values */ - unsigned int state; - unsigned int bending; - int lnb_drift; - unsigned int inversion; - unsigned int auto_step; - unsigned int auto_sub_step; - unsigned int started_auto_step; - unsigned int min_delay; - unsigned int max_drift; - unsigned int step_size; - int quality; - unsigned int check_wrapped; - enum dvbfe_search algo_status; -}; - -static void dvb_frontend_wakeup(struct dvb_frontend *fe); -static int dtv_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p_out); -static int dtv_property_legacy_params_sync(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p); - -static bool has_get_frontend(struct dvb_frontend *fe) -{ - return fe->ops.get_frontend != NULL; -} - -/* - * Due to DVBv3 API calls, a delivery system should be mapped into one of - * the 4 DVBv3 delivery systems (FE_QPSK, FE_QAM, FE_OFDM or FE_ATSC), - * otherwise, a DVBv3 call will fail. - */ -enum dvbv3_emulation_type { - DVBV3_UNKNOWN, - DVBV3_QPSK, - DVBV3_QAM, - DVBV3_OFDM, - DVBV3_ATSC, -}; - -static enum dvbv3_emulation_type dvbv3_type(u32 delivery_system) -{ - switch (delivery_system) { - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: - return DVBV3_QAM; - case SYS_DVBS: - case SYS_DVBS2: - case SYS_TURBO: - case SYS_ISDBS: - case SYS_DSS: - return DVBV3_QPSK; - case SYS_DVBT: - case SYS_DVBT2: - case SYS_ISDBT: - case SYS_DTMB: - return DVBV3_OFDM; - case SYS_ATSC: - case SYS_ATSCMH: - case SYS_DVBC_ANNEX_B: - return DVBV3_ATSC; - case SYS_UNDEFINED: - case SYS_ISDBC: - case SYS_DVBH: - case SYS_DAB: - default: - /* - * Doesn't know how to emulate those types and/or - * there's no frontend driver from this type yet - * with some emulation code, so, we're not sure yet how - * to handle them, or they're not compatible with a DVBv3 call. - */ - return DVBV3_UNKNOWN; - } -} - -static void dvb_frontend_add_event(struct dvb_frontend *fe, fe_status_t status) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dvb_fe_events *events = &fepriv->events; - struct dvb_frontend_event *e; - int wp; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - if ((status & FE_HAS_LOCK) && has_get_frontend(fe)) - dtv_get_frontend(fe, &fepriv->parameters_out); - - mutex_lock(&events->mtx); - - wp = (events->eventw + 1) % MAX_EVENT; - if (wp == events->eventr) { - events->overflow = 1; - events->eventr = (events->eventr + 1) % MAX_EVENT; - } - - e = &events->events[events->eventw]; - e->status = status; - e->parameters = fepriv->parameters_out; - - events->eventw = wp; - - mutex_unlock(&events->mtx); - - wake_up_interruptible (&events->wait_queue); -} - -static int dvb_frontend_get_event(struct dvb_frontend *fe, - struct dvb_frontend_event *event, int flags) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dvb_fe_events *events = &fepriv->events; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - if (events->overflow) { - events->overflow = 0; - return -EOVERFLOW; - } - - if (events->eventw == events->eventr) { - int ret; - - if (flags & O_NONBLOCK) - return -EWOULDBLOCK; - - up(&fepriv->sem); - - ret = wait_event_interruptible (events->wait_queue, - events->eventw != events->eventr); - - if (down_interruptible (&fepriv->sem)) - return -ERESTARTSYS; - - if (ret < 0) - return ret; - } - - mutex_lock(&events->mtx); - *event = events->events[events->eventr]; - events->eventr = (events->eventr + 1) % MAX_EVENT; - mutex_unlock(&events->mtx); - - return 0; -} - -static void dvb_frontend_clear_events(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dvb_fe_events *events = &fepriv->events; - - mutex_lock(&events->mtx); - events->eventr = events->eventw; - mutex_unlock(&events->mtx); -} - -static void dvb_frontend_init(struct dvb_frontend *fe) -{ - dev_dbg(fe->dvb->device, - "%s: initialising adapter %i frontend %i (%s)...\n", - __func__, fe->dvb->num, fe->id, fe->ops.info.name); - - if (fe->ops.init) - fe->ops.init(fe); - if (fe->ops.tuner_ops.init) { - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - fe->ops.tuner_ops.init(fe); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - } -} - -void dvb_frontend_reinitialise(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - - fepriv->reinitialise = 1; - dvb_frontend_wakeup(fe); -} -EXPORT_SYMBOL(dvb_frontend_reinitialise); - -static void dvb_frontend_swzigzag_update_delay(struct dvb_frontend_private *fepriv, int locked) -{ - int q2; - struct dvb_frontend *fe = fepriv->dvbdev->priv; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - if (locked) - (fepriv->quality) = (fepriv->quality * 220 + 36*256) / 256; - else - (fepriv->quality) = (fepriv->quality * 220 + 0) / 256; - - q2 = fepriv->quality - 128; - q2 *= q2; - - fepriv->delay = fepriv->min_delay + q2 * HZ / (128*128); -} - -/** - * Performs automatic twiddling of frontend parameters. - * - * @param fe The frontend concerned. - * @param check_wrapped Checks if an iteration has completed. DO NOT SET ON THE FIRST ATTEMPT - * @returns Number of complete iterations that have been performed. - */ -static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wrapped) -{ - int autoinversion; - int ready = 0; - int fe_set_err = 0; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dtv_frontend_properties *c = &fe->dtv_property_cache, tmp; - int original_inversion = c->inversion; - u32 original_frequency = c->frequency; - - /* are we using autoinversion? */ - autoinversion = ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) && - (c->inversion == INVERSION_AUTO)); - - /* setup parameters correctly */ - while(!ready) { - /* calculate the lnb_drift */ - fepriv->lnb_drift = fepriv->auto_step * fepriv->step_size; - - /* wrap the auto_step if we've exceeded the maximum drift */ - if (fepriv->lnb_drift > fepriv->max_drift) { - fepriv->auto_step = 0; - fepriv->auto_sub_step = 0; - fepriv->lnb_drift = 0; - } - - /* perform inversion and +/- zigzag */ - switch(fepriv->auto_sub_step) { - case 0: - /* try with the current inversion and current drift setting */ - ready = 1; - break; - - case 1: - if (!autoinversion) break; - - fepriv->inversion = (fepriv->inversion == INVERSION_OFF) ? INVERSION_ON : INVERSION_OFF; - ready = 1; - break; - - case 2: - if (fepriv->lnb_drift == 0) break; - - fepriv->lnb_drift = -fepriv->lnb_drift; - ready = 1; - break; - - case 3: - if (fepriv->lnb_drift == 0) break; - if (!autoinversion) break; - - fepriv->inversion = (fepriv->inversion == INVERSION_OFF) ? INVERSION_ON : INVERSION_OFF; - fepriv->lnb_drift = -fepriv->lnb_drift; - ready = 1; - break; - - default: - fepriv->auto_step++; - fepriv->auto_sub_step = -1; /* it'll be incremented to 0 in a moment */ - break; - } - - if (!ready) fepriv->auto_sub_step++; - } - - /* if this attempt would hit where we started, indicate a complete - * iteration has occurred */ - if ((fepriv->auto_step == fepriv->started_auto_step) && - (fepriv->auto_sub_step == 0) && check_wrapped) { - return 1; - } - - dev_dbg(fe->dvb->device, "%s: drift:%i inversion:%i auto_step:%i " \ - "auto_sub_step:%i started_auto_step:%i\n", - __func__, fepriv->lnb_drift, fepriv->inversion, - fepriv->auto_step, fepriv->auto_sub_step, - fepriv->started_auto_step); - - /* set the frontend itself */ - c->frequency += fepriv->lnb_drift; - if (autoinversion) - c->inversion = fepriv->inversion; - tmp = *c; - if (fe->ops.set_frontend) - fe_set_err = fe->ops.set_frontend(fe); - *c = tmp; - if (fe_set_err < 0) { - fepriv->state = FESTATE_ERROR; - return fe_set_err; - } - - c->frequency = original_frequency; - c->inversion = original_inversion; - - fepriv->auto_sub_step++; - return 0; -} - -static void dvb_frontend_swzigzag(struct dvb_frontend *fe) -{ - fe_status_t s = 0; - int retval = 0; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dtv_frontend_properties *c = &fe->dtv_property_cache, tmp; - - /* if we've got no parameters, just keep idling */ - if (fepriv->state & FESTATE_IDLE) { - fepriv->delay = 3*HZ; - fepriv->quality = 0; - return; - } - - /* in SCAN mode, we just set the frontend when asked and leave it alone */ - if (fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT) { - if (fepriv->state & FESTATE_RETUNE) { - tmp = *c; - if (fe->ops.set_frontend) - retval = fe->ops.set_frontend(fe); - *c = tmp; - if (retval < 0) - fepriv->state = FESTATE_ERROR; - else - fepriv->state = FESTATE_TUNED; - } - fepriv->delay = 3*HZ; - fepriv->quality = 0; - return; - } - - /* get the frontend status */ - if (fepriv->state & FESTATE_RETUNE) { - s = 0; - } else { - if (fe->ops.read_status) - fe->ops.read_status(fe, &s); - if (s != fepriv->status) { - dvb_frontend_add_event(fe, s); - fepriv->status = s; - } - } - - /* if we're not tuned, and we have a lock, move to the TUNED state */ - if ((fepriv->state & FESTATE_WAITFORLOCK) && (s & FE_HAS_LOCK)) { - dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); - fepriv->state = FESTATE_TUNED; - - /* if we're tuned, then we have determined the correct inversion */ - if ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) && - (c->inversion == INVERSION_AUTO)) { - c->inversion = fepriv->inversion; - } - return; - } - - /* if we are tuned already, check we're still locked */ - if (fepriv->state & FESTATE_TUNED) { - dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); - - /* we're tuned, and the lock is still good... */ - if (s & FE_HAS_LOCK) { - return; - } else { /* if we _WERE_ tuned, but now don't have a lock */ - fepriv->state = FESTATE_ZIGZAG_FAST; - fepriv->started_auto_step = fepriv->auto_step; - fepriv->check_wrapped = 0; - } - } - - /* don't actually do anything if we're in the LOSTLOCK state, - * the frontend is set to FE_CAN_RECOVER, and the max_drift is 0 */ - if ((fepriv->state & FESTATE_LOSTLOCK) && - (fe->ops.info.caps & FE_CAN_RECOVER) && (fepriv->max_drift == 0)) { - dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); - return; - } - - /* don't do anything if we're in the DISEQC state, since this - * might be someone with a motorized dish controlled by DISEQC. - * If its actually a re-tune, there will be a SET_FRONTEND soon enough. */ - if (fepriv->state & FESTATE_DISEQC) { - dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); - return; - } - - /* if we're in the RETUNE state, set everything up for a brand - * new scan, keeping the current inversion setting, as the next - * tune is _very_ likely to require the same */ - if (fepriv->state & FESTATE_RETUNE) { - fepriv->lnb_drift = 0; - fepriv->auto_step = 0; - fepriv->auto_sub_step = 0; - fepriv->started_auto_step = 0; - fepriv->check_wrapped = 0; - } - - /* fast zigzag. */ - if ((fepriv->state & FESTATE_SEARCHING_FAST) || (fepriv->state & FESTATE_RETUNE)) { - fepriv->delay = fepriv->min_delay; - - /* perform a tune */ - retval = dvb_frontend_swzigzag_autotune(fe, - fepriv->check_wrapped); - if (retval < 0) { - return; - } else if (retval) { - /* OK, if we've run out of trials at the fast speed. - * Drop back to slow for the _next_ attempt */ - fepriv->state = FESTATE_SEARCHING_SLOW; - fepriv->started_auto_step = fepriv->auto_step; - return; - } - fepriv->check_wrapped = 1; - - /* if we've just retuned, enter the ZIGZAG_FAST state. - * This ensures we cannot return from an - * FE_SET_FRONTEND ioctl before the first frontend tune - * occurs */ - if (fepriv->state & FESTATE_RETUNE) { - fepriv->state = FESTATE_TUNING_FAST; - } - } - - /* slow zigzag */ - if (fepriv->state & FESTATE_SEARCHING_SLOW) { - dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); - - /* Note: don't bother checking for wrapping; we stay in this - * state until we get a lock */ - dvb_frontend_swzigzag_autotune(fe, 0); - } -} - -static int dvb_frontend_is_exiting(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - - if (fepriv->exit != DVB_FE_NO_EXIT) - return 1; - - if (fepriv->dvbdev->writers == 1) - if (time_after_eq(jiffies, fepriv->release_jiffies + - dvb_shutdown_timeout * HZ)) - return 1; - - return 0; -} - -static int dvb_frontend_should_wakeup(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - - if (fepriv->wakeup) { - fepriv->wakeup = 0; - return 1; - } - return dvb_frontend_is_exiting(fe); -} - -static void dvb_frontend_wakeup(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - - fepriv->wakeup = 1; - wake_up_interruptible(&fepriv->wait_queue); -} - -static int dvb_frontend_thread(void *data) -{ - struct dvb_frontend *fe = data; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - fe_status_t s; - enum dvbfe_algo algo; - - bool re_tune = false; - bool semheld = false; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - fepriv->check_wrapped = 0; - fepriv->quality = 0; - fepriv->delay = 3*HZ; - fepriv->status = 0; - fepriv->wakeup = 0; - fepriv->reinitialise = 0; - - dvb_frontend_init(fe); - - set_freezable(); - while (1) { - up(&fepriv->sem); /* is locked when we enter the thread... */ -restart: - wait_event_interruptible_timeout(fepriv->wait_queue, - dvb_frontend_should_wakeup(fe) || kthread_should_stop() - || freezing(current), - fepriv->delay); - - if (kthread_should_stop() || dvb_frontend_is_exiting(fe)) { - /* got signal or quitting */ - if (!down_interruptible(&fepriv->sem)) - semheld = true; - fepriv->exit = DVB_FE_NORMAL_EXIT; - break; - } - - if (try_to_freeze()) - goto restart; - - if (down_interruptible(&fepriv->sem)) - break; - - if (fepriv->reinitialise) { - dvb_frontend_init(fe); - if (fe->ops.set_tone && fepriv->tone != -1) - fe->ops.set_tone(fe, fepriv->tone); - if (fe->ops.set_voltage && fepriv->voltage != -1) - fe->ops.set_voltage(fe, fepriv->voltage); - fepriv->reinitialise = 0; - } - - /* do an iteration of the tuning loop */ - if (fe->ops.get_frontend_algo) { - algo = fe->ops.get_frontend_algo(fe); - switch (algo) { - case DVBFE_ALGO_HW: - dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_HW\n", __func__); - - if (fepriv->state & FESTATE_RETUNE) { - dev_dbg(fe->dvb->device, "%s: Retune requested, FESTATE_RETUNE\n", __func__); - re_tune = true; - fepriv->state = FESTATE_TUNED; - } else { - re_tune = false; - } - - if (fe->ops.tune) - fe->ops.tune(fe, re_tune, fepriv->tune_mode_flags, &fepriv->delay, &s); - - if (s != fepriv->status && !(fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT)) { - dev_dbg(fe->dvb->device, "%s: state changed, adding current state\n", __func__); - dvb_frontend_add_event(fe, s); - fepriv->status = s; - } - break; - case DVBFE_ALGO_SW: - dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_SW\n", __func__); - dvb_frontend_swzigzag(fe); - break; - case DVBFE_ALGO_CUSTOM: - dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_CUSTOM, state=%d\n", __func__, fepriv->state); - if (fepriv->state & FESTATE_RETUNE) { - dev_dbg(fe->dvb->device, "%s: Retune requested, FESTAT_RETUNE\n", __func__); - fepriv->state = FESTATE_TUNED; - } - /* Case where we are going to search for a carrier - * User asked us to retune again for some reason, possibly - * requesting a search with a new set of parameters - */ - if (fepriv->algo_status & DVBFE_ALGO_SEARCH_AGAIN) { - if (fe->ops.search) { - fepriv->algo_status = fe->ops.search(fe); - /* We did do a search as was requested, the flags are - * now unset as well and has the flags wrt to search. - */ - } else { - fepriv->algo_status &= ~DVBFE_ALGO_SEARCH_AGAIN; - } - } - /* Track the carrier if the search was successful */ - if (fepriv->algo_status != DVBFE_ALGO_SEARCH_SUCCESS) { - fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; - fepriv->delay = HZ / 2; - } - dtv_property_legacy_params_sync(fe, &fepriv->parameters_out); - fe->ops.read_status(fe, &s); - if (s != fepriv->status) { - dvb_frontend_add_event(fe, s); /* update event list */ - fepriv->status = s; - if (!(s & FE_HAS_LOCK)) { - fepriv->delay = HZ / 10; - fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; - } else { - fepriv->delay = 60 * HZ; - } - } - break; - default: - dev_dbg(fe->dvb->device, "%s: UNDEFINED ALGO !\n", __func__); - break; - } - } else { - dvb_frontend_swzigzag(fe); - } - } - - if (dvb_powerdown_on_sleep) { - if (fe->ops.set_voltage) - fe->ops.set_voltage(fe, SEC_VOLTAGE_OFF); - if (fe->ops.tuner_ops.sleep) { - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - fe->ops.tuner_ops.sleep(fe); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - } - if (fe->ops.sleep) - fe->ops.sleep(fe); - } - - fepriv->thread = NULL; - if (kthread_should_stop()) - fepriv->exit = DVB_FE_DEVICE_REMOVED; - else - fepriv->exit = DVB_FE_NO_EXIT; - mb(); - - if (semheld) - up(&fepriv->sem); - dvb_frontend_wakeup(fe); - return 0; -} - -static void dvb_frontend_stop(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - fepriv->exit = DVB_FE_NORMAL_EXIT; - mb(); - - if (!fepriv->thread) - return; - - kthread_stop(fepriv->thread); - - sema_init(&fepriv->sem, 1); - fepriv->state = FESTATE_IDLE; - - /* paranoia check in case a signal arrived */ - if (fepriv->thread) - dev_warn(fe->dvb->device, - "dvb_frontend_stop: warning: thread %p won't exit\n", - fepriv->thread); -} - -s32 timeval_usec_diff(struct timeval lasttime, struct timeval curtime) -{ - return ((curtime.tv_usec < lasttime.tv_usec) ? - 1000000 - lasttime.tv_usec + curtime.tv_usec : - curtime.tv_usec - lasttime.tv_usec); -} -EXPORT_SYMBOL(timeval_usec_diff); - -static inline void timeval_usec_add(struct timeval *curtime, u32 add_usec) -{ - curtime->tv_usec += add_usec; - if (curtime->tv_usec >= 1000000) { - curtime->tv_usec -= 1000000; - curtime->tv_sec++; - } -} - -/* - * Sleep until gettimeofday() > waketime + add_usec - * This needs to be as precise as possible, but as the delay is - * usually between 2ms and 32ms, it is done using a scheduled msleep - * followed by usleep (normally a busy-wait loop) for the remainder - */ -void dvb_frontend_sleep_until(struct timeval *waketime, u32 add_usec) -{ - struct timeval lasttime; - s32 delta, newdelta; - - timeval_usec_add(waketime, add_usec); - - do_gettimeofday(&lasttime); - delta = timeval_usec_diff(lasttime, *waketime); - if (delta > 2500) { - msleep((delta - 1500) / 1000); - do_gettimeofday(&lasttime); - newdelta = timeval_usec_diff(lasttime, *waketime); - delta = (newdelta > delta) ? 0 : newdelta; - } - if (delta > 0) - udelay(delta); -} -EXPORT_SYMBOL(dvb_frontend_sleep_until); - -static int dvb_frontend_start(struct dvb_frontend *fe) -{ - int ret; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct task_struct *fe_thread; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - if (fepriv->thread) { - if (fepriv->exit == DVB_FE_NO_EXIT) - return 0; - else - dvb_frontend_stop (fe); - } - - if (signal_pending(current)) - return -EINTR; - if (down_interruptible (&fepriv->sem)) - return -EINTR; - - fepriv->state = FESTATE_IDLE; - fepriv->exit = DVB_FE_NO_EXIT; - fepriv->thread = NULL; - mb(); - - fe_thread = kthread_run(dvb_frontend_thread, fe, - "kdvb-ad-%i-fe-%i", fe->dvb->num,fe->id); - if (IS_ERR(fe_thread)) { - ret = PTR_ERR(fe_thread); - dev_warn(fe->dvb->device, - "dvb_frontend_start: failed to start kthread (%d)\n", - ret); - up(&fepriv->sem); - return ret; - } - fepriv->thread = fe_thread; - return 0; -} - -static void dvb_frontend_get_frequency_limits(struct dvb_frontend *fe, - u32 *freq_min, u32 *freq_max) -{ - *freq_min = max(fe->ops.info.frequency_min, fe->ops.tuner_ops.info.frequency_min); - - if (fe->ops.info.frequency_max == 0) - *freq_max = fe->ops.tuner_ops.info.frequency_max; - else if (fe->ops.tuner_ops.info.frequency_max == 0) - *freq_max = fe->ops.info.frequency_max; - else - *freq_max = min(fe->ops.info.frequency_max, fe->ops.tuner_ops.info.frequency_max); - - if (*freq_min == 0 || *freq_max == 0) - dev_warn(fe->dvb->device, "DVB: adapter %i frontend %u frequency limits undefined - fix the driver\n", - fe->dvb->num, fe->id); -} - -static int dvb_frontend_check_parameters(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - u32 freq_min; - u32 freq_max; - - /* range check: frequency */ - dvb_frontend_get_frequency_limits(fe, &freq_min, &freq_max); - if ((freq_min && c->frequency < freq_min) || - (freq_max && c->frequency > freq_max)) { - dev_warn(fe->dvb->device, "DVB: adapter %i frontend %i frequency %u out of range (%u..%u)\n", - fe->dvb->num, fe->id, c->frequency, - freq_min, freq_max); - return -EINVAL; - } - - /* range check: symbol rate */ - switch (c->delivery_system) { - case SYS_DVBS: - case SYS_DVBS2: - case SYS_TURBO: - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: - if ((fe->ops.info.symbol_rate_min && - c->symbol_rate < fe->ops.info.symbol_rate_min) || - (fe->ops.info.symbol_rate_max && - c->symbol_rate > fe->ops.info.symbol_rate_max)) { - dev_warn(fe->dvb->device, "DVB: adapter %i frontend %i symbol rate %u out of range (%u..%u)\n", - fe->dvb->num, fe->id, c->symbol_rate, - fe->ops.info.symbol_rate_min, - fe->ops.info.symbol_rate_max); - return -EINVAL; - } - default: - break; - } - - return 0; -} - -static int dvb_frontend_clear_cache(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - int i; - u32 delsys; - - delsys = c->delivery_system; - memset(c, 0, offsetof(struct dtv_frontend_properties, strength)); - c->delivery_system = delsys; - - c->state = DTV_CLEAR; - - dev_dbg(fe->dvb->device, "%s: Clearing cache for delivery system %d\n", - __func__, c->delivery_system); - - c->transmission_mode = TRANSMISSION_MODE_AUTO; - c->bandwidth_hz = 0; /* AUTO */ - c->guard_interval = GUARD_INTERVAL_AUTO; - c->hierarchy = HIERARCHY_AUTO; - c->symbol_rate = 0; - c->code_rate_HP = FEC_AUTO; - c->code_rate_LP = FEC_AUTO; - c->fec_inner = FEC_AUTO; - c->rolloff = ROLLOFF_AUTO; - c->voltage = SEC_VOLTAGE_OFF; - c->sectone = SEC_TONE_OFF; - c->pilot = PILOT_AUTO; - - c->isdbt_partial_reception = 0; - c->isdbt_sb_mode = 0; - c->isdbt_sb_subchannel = 0; - c->isdbt_sb_segment_idx = 0; - c->isdbt_sb_segment_count = 0; - c->isdbt_layer_enabled = 0; - for (i = 0; i < 3; i++) { - c->layer[i].fec = FEC_AUTO; - c->layer[i].modulation = QAM_AUTO; - c->layer[i].interleaving = 0; - c->layer[i].segment_count = 0; - } - - c->stream_id = NO_STREAM_ID_FILTER; - - switch (c->delivery_system) { - case SYS_DVBS: - case SYS_DVBS2: - case SYS_TURBO: - c->modulation = QPSK; /* implied for DVB-S in legacy API */ - c->rolloff = ROLLOFF_35;/* implied for DVB-S */ - break; - case SYS_ATSC: - c->modulation = VSB_8; - break; - default: - c->modulation = QAM_AUTO; - break; - } - - c->lna = LNA_AUTO; - - return 0; -} - -#define _DTV_CMD(n, s, b) \ -[n] = { \ - .name = #n, \ - .cmd = n, \ - .set = s,\ - .buffer = b \ -} - -static struct dtv_cmds_h dtv_cmds[DTV_MAX_COMMAND + 1] = { - _DTV_CMD(DTV_TUNE, 1, 0), - _DTV_CMD(DTV_CLEAR, 1, 0), - - /* Set */ - _DTV_CMD(DTV_FREQUENCY, 1, 0), - _DTV_CMD(DTV_BANDWIDTH_HZ, 1, 0), - _DTV_CMD(DTV_MODULATION, 1, 0), - _DTV_CMD(DTV_INVERSION, 1, 0), - _DTV_CMD(DTV_DISEQC_MASTER, 1, 1), - _DTV_CMD(DTV_SYMBOL_RATE, 1, 0), - _DTV_CMD(DTV_INNER_FEC, 1, 0), - _DTV_CMD(DTV_VOLTAGE, 1, 0), - _DTV_CMD(DTV_TONE, 1, 0), - _DTV_CMD(DTV_PILOT, 1, 0), - _DTV_CMD(DTV_ROLLOFF, 1, 0), - _DTV_CMD(DTV_DELIVERY_SYSTEM, 1, 0), - _DTV_CMD(DTV_HIERARCHY, 1, 0), - _DTV_CMD(DTV_CODE_RATE_HP, 1, 0), - _DTV_CMD(DTV_CODE_RATE_LP, 1, 0), - _DTV_CMD(DTV_GUARD_INTERVAL, 1, 0), - _DTV_CMD(DTV_TRANSMISSION_MODE, 1, 0), - _DTV_CMD(DTV_INTERLEAVING, 1, 0), - - _DTV_CMD(DTV_ISDBT_PARTIAL_RECEPTION, 1, 0), - _DTV_CMD(DTV_ISDBT_SOUND_BROADCASTING, 1, 0), - _DTV_CMD(DTV_ISDBT_SB_SUBCHANNEL_ID, 1, 0), - _DTV_CMD(DTV_ISDBT_SB_SEGMENT_IDX, 1, 0), - _DTV_CMD(DTV_ISDBT_SB_SEGMENT_COUNT, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYER_ENABLED, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERA_FEC, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERA_MODULATION, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERA_SEGMENT_COUNT, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERA_TIME_INTERLEAVING, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERB_FEC, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERB_MODULATION, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERB_SEGMENT_COUNT, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERB_TIME_INTERLEAVING, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERC_FEC, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERC_MODULATION, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERC_SEGMENT_COUNT, 1, 0), - _DTV_CMD(DTV_ISDBT_LAYERC_TIME_INTERLEAVING, 1, 0), - - _DTV_CMD(DTV_STREAM_ID, 1, 0), - _DTV_CMD(DTV_DVBT2_PLP_ID_LEGACY, 1, 0), - _DTV_CMD(DTV_LNA, 1, 0), - - /* Get */ - _DTV_CMD(DTV_DISEQC_SLAVE_REPLY, 0, 1), - _DTV_CMD(DTV_API_VERSION, 0, 0), - - _DTV_CMD(DTV_ENUM_DELSYS, 0, 0), - - _DTV_CMD(DTV_ATSCMH_PARADE_ID, 1, 0), - _DTV_CMD(DTV_ATSCMH_RS_FRAME_ENSEMBLE, 1, 0), - - _DTV_CMD(DTV_ATSCMH_FIC_VER, 0, 0), - _DTV_CMD(DTV_ATSCMH_NOG, 0, 0), - _DTV_CMD(DTV_ATSCMH_TNOG, 0, 0), - _DTV_CMD(DTV_ATSCMH_SGN, 0, 0), - _DTV_CMD(DTV_ATSCMH_PRC, 0, 0), - _DTV_CMD(DTV_ATSCMH_RS_FRAME_MODE, 0, 0), - _DTV_CMD(DTV_ATSCMH_RS_CODE_MODE_PRI, 0, 0), - _DTV_CMD(DTV_ATSCMH_RS_CODE_MODE_SEC, 0, 0), - _DTV_CMD(DTV_ATSCMH_SCCC_BLOCK_MODE, 0, 0), - _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_A, 0, 0), - _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_B, 0, 0), - _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_C, 0, 0), - _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_D, 0, 0), - - /* Statistics API */ - _DTV_CMD(DTV_STAT_SIGNAL_STRENGTH, 0, 0), - _DTV_CMD(DTV_STAT_CNR, 0, 0), - _DTV_CMD(DTV_STAT_PRE_ERROR_BIT_COUNT, 0, 0), - _DTV_CMD(DTV_STAT_PRE_TOTAL_BIT_COUNT, 0, 0), - _DTV_CMD(DTV_STAT_POST_ERROR_BIT_COUNT, 0, 0), - _DTV_CMD(DTV_STAT_POST_TOTAL_BIT_COUNT, 0, 0), - _DTV_CMD(DTV_STAT_ERROR_BLOCK_COUNT, 0, 0), - _DTV_CMD(DTV_STAT_TOTAL_BLOCK_COUNT, 0, 0), -}; - -static void dtv_property_dump(struct dvb_frontend *fe, struct dtv_property *tvp) -{ - int i; - - if (tvp->cmd <= 0 || tvp->cmd > DTV_MAX_COMMAND) { - dev_warn(fe->dvb->device, "%s: tvp.cmd = 0x%08x undefined\n", - __func__, tvp->cmd); - return; - } - - dev_dbg(fe->dvb->device, "%s: tvp.cmd = 0x%08x (%s)\n", __func__, - tvp->cmd, dtv_cmds[tvp->cmd].name); - - if (dtv_cmds[tvp->cmd].buffer) { - dev_dbg(fe->dvb->device, "%s: tvp.u.buffer.len = 0x%02x\n", - __func__, tvp->u.buffer.len); - - for(i = 0; i < tvp->u.buffer.len; i++) - dev_dbg(fe->dvb->device, - "%s: tvp.u.buffer.data[0x%02x] = 0x%02x\n", - __func__, i, tvp->u.buffer.data[i]); - } else { - dev_dbg(fe->dvb->device, "%s: tvp.u.data = 0x%08x\n", __func__, - tvp->u.data); - } -} - -/* Synchronise the legacy tuning parameters into the cache, so that demodulator - * drivers can use a single set_frontend tuning function, regardless of whether - * it's being used for the legacy or new API, reducing code and complexity. - */ -static int dtv_property_cache_sync(struct dvb_frontend *fe, - struct dtv_frontend_properties *c, - const struct dvb_frontend_parameters *p) -{ - c->frequency = p->frequency; - c->inversion = p->inversion; - - switch (dvbv3_type(c->delivery_system)) { - case DVBV3_QPSK: - dev_dbg(fe->dvb->device, "%s: Preparing QPSK req\n", __func__); - c->symbol_rate = p->u.qpsk.symbol_rate; - c->fec_inner = p->u.qpsk.fec_inner; - break; - case DVBV3_QAM: - dev_dbg(fe->dvb->device, "%s: Preparing QAM req\n", __func__); - c->symbol_rate = p->u.qam.symbol_rate; - c->fec_inner = p->u.qam.fec_inner; - c->modulation = p->u.qam.modulation; - break; - case DVBV3_OFDM: - dev_dbg(fe->dvb->device, "%s: Preparing OFDM req\n", __func__); - - switch (p->u.ofdm.bandwidth) { - case BANDWIDTH_10_MHZ: - c->bandwidth_hz = 10000000; - break; - case BANDWIDTH_8_MHZ: - c->bandwidth_hz = 8000000; - break; - case BANDWIDTH_7_MHZ: - c->bandwidth_hz = 7000000; - break; - case BANDWIDTH_6_MHZ: - c->bandwidth_hz = 6000000; - break; - case BANDWIDTH_5_MHZ: - c->bandwidth_hz = 5000000; - break; - case BANDWIDTH_1_712_MHZ: - c->bandwidth_hz = 1712000; - break; - case BANDWIDTH_AUTO: - c->bandwidth_hz = 0; - } - - c->code_rate_HP = p->u.ofdm.code_rate_HP; - c->code_rate_LP = p->u.ofdm.code_rate_LP; - c->modulation = p->u.ofdm.constellation; - c->transmission_mode = p->u.ofdm.transmission_mode; - c->guard_interval = p->u.ofdm.guard_interval; - c->hierarchy = p->u.ofdm.hierarchy_information; - break; - case DVBV3_ATSC: - dev_dbg(fe->dvb->device, "%s: Preparing ATSC req\n", __func__); - c->modulation = p->u.vsb.modulation; - if (c->delivery_system == SYS_ATSCMH) - break; - if ((c->modulation == VSB_8) || (c->modulation == VSB_16)) - c->delivery_system = SYS_ATSC; - else - c->delivery_system = SYS_DVBC_ANNEX_B; - break; - case DVBV3_UNKNOWN: - dev_err(fe->dvb->device, - "%s: doesn't know how to handle a DVBv3 call to delivery system %i\n", - __func__, c->delivery_system); - return -EINVAL; - } - - return 0; -} - -/* Ensure the cached values are set correctly in the frontend - * legacy tuning structures, for the advanced tuning API. - */ -static int dtv_property_legacy_params_sync(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) -{ - const struct dtv_frontend_properties *c = &fe->dtv_property_cache; - - p->frequency = c->frequency; - p->inversion = c->inversion; - - switch (dvbv3_type(c->delivery_system)) { - case DVBV3_UNKNOWN: - dev_err(fe->dvb->device, - "%s: doesn't know how to handle a DVBv3 call to delivery system %i\n", - __func__, c->delivery_system); - return -EINVAL; - case DVBV3_QPSK: - dev_dbg(fe->dvb->device, "%s: Preparing QPSK req\n", __func__); - p->u.qpsk.symbol_rate = c->symbol_rate; - p->u.qpsk.fec_inner = c->fec_inner; - break; - case DVBV3_QAM: - dev_dbg(fe->dvb->device, "%s: Preparing QAM req\n", __func__); - p->u.qam.symbol_rate = c->symbol_rate; - p->u.qam.fec_inner = c->fec_inner; - p->u.qam.modulation = c->modulation; - break; - case DVBV3_OFDM: - dev_dbg(fe->dvb->device, "%s: Preparing OFDM req\n", __func__); - switch (c->bandwidth_hz) { - case 10000000: - p->u.ofdm.bandwidth = BANDWIDTH_10_MHZ; - break; - case 8000000: - p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; - break; - case 7000000: - p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; - break; - case 6000000: - p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; - break; - case 5000000: - p->u.ofdm.bandwidth = BANDWIDTH_5_MHZ; - break; - case 1712000: - p->u.ofdm.bandwidth = BANDWIDTH_1_712_MHZ; - break; - case 0: - default: - p->u.ofdm.bandwidth = BANDWIDTH_AUTO; - } - p->u.ofdm.code_rate_HP = c->code_rate_HP; - p->u.ofdm.code_rate_LP = c->code_rate_LP; - p->u.ofdm.constellation = c->modulation; - p->u.ofdm.transmission_mode = c->transmission_mode; - p->u.ofdm.guard_interval = c->guard_interval; - p->u.ofdm.hierarchy_information = c->hierarchy; - break; - case DVBV3_ATSC: - dev_dbg(fe->dvb->device, "%s: Preparing VSB req\n", __func__); - p->u.vsb.modulation = c->modulation; - break; - } - return 0; -} - -/** - * dtv_get_frontend - calls a callback for retrieving DTV parameters - * @fe: struct dvb_frontend pointer - * @c: struct dtv_frontend_properties pointer (DVBv5 cache) - * @p_out struct dvb_frontend_parameters pointer (DVBv3 FE struct) - * - * This routine calls either the DVBv3 or DVBv5 get_frontend call. - * If c is not null, it will update the DVBv5 cache struct pointed by it. - * If p_out is not null, it will update the DVBv3 params pointed by it. - */ -static int dtv_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p_out) -{ - int r; - - if (fe->ops.get_frontend) { - r = fe->ops.get_frontend(fe); - if (unlikely(r < 0)) - return r; - if (p_out) - dtv_property_legacy_params_sync(fe, p_out); - return 0; - } - - /* As everything is in cache, get_frontend fops are always supported */ - return 0; -} - -static int dvb_frontend_ioctl_legacy(struct file *file, - unsigned int cmd, void *parg); -static int dvb_frontend_ioctl_properties(struct file *file, - unsigned int cmd, void *parg); - -static int dtv_property_process_get(struct dvb_frontend *fe, - const struct dtv_frontend_properties *c, - struct dtv_property *tvp, - struct file *file) -{ - int r, ncaps; - - switch(tvp->cmd) { - case DTV_ENUM_DELSYS: - ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { - tvp->u.buffer.data[ncaps] = fe->ops.delsys[ncaps]; - ncaps++; - } - tvp->u.buffer.len = ncaps; - break; - case DTV_FREQUENCY: - tvp->u.data = c->frequency; - break; - case DTV_MODULATION: - tvp->u.data = c->modulation; - break; - case DTV_BANDWIDTH_HZ: - tvp->u.data = c->bandwidth_hz; - break; - case DTV_INVERSION: - tvp->u.data = c->inversion; - break; - case DTV_SYMBOL_RATE: - tvp->u.data = c->symbol_rate; - break; - case DTV_INNER_FEC: - tvp->u.data = c->fec_inner; - break; - case DTV_PILOT: - tvp->u.data = c->pilot; - break; - case DTV_ROLLOFF: - tvp->u.data = c->rolloff; - break; - case DTV_DELIVERY_SYSTEM: - tvp->u.data = c->delivery_system; - break; - case DTV_VOLTAGE: - tvp->u.data = c->voltage; - break; - case DTV_TONE: - tvp->u.data = c->sectone; - break; - case DTV_API_VERSION: - tvp->u.data = (DVB_API_VERSION << 8) | DVB_API_VERSION_MINOR; - break; - case DTV_CODE_RATE_HP: - tvp->u.data = c->code_rate_HP; - break; - case DTV_CODE_RATE_LP: - tvp->u.data = c->code_rate_LP; - break; - case DTV_GUARD_INTERVAL: - tvp->u.data = c->guard_interval; - break; - case DTV_TRANSMISSION_MODE: - tvp->u.data = c->transmission_mode; - break; - case DTV_HIERARCHY: - tvp->u.data = c->hierarchy; - break; - case DTV_INTERLEAVING: - tvp->u.data = c->interleaving; - break; - - /* ISDB-T Support here */ - case DTV_ISDBT_PARTIAL_RECEPTION: - tvp->u.data = c->isdbt_partial_reception; - break; - case DTV_ISDBT_SOUND_BROADCASTING: - tvp->u.data = c->isdbt_sb_mode; - break; - case DTV_ISDBT_SB_SUBCHANNEL_ID: - tvp->u.data = c->isdbt_sb_subchannel; - break; - case DTV_ISDBT_SB_SEGMENT_IDX: - tvp->u.data = c->isdbt_sb_segment_idx; - break; - case DTV_ISDBT_SB_SEGMENT_COUNT: - tvp->u.data = c->isdbt_sb_segment_count; - break; - case DTV_ISDBT_LAYER_ENABLED: - tvp->u.data = c->isdbt_layer_enabled; - break; - case DTV_ISDBT_LAYERA_FEC: - tvp->u.data = c->layer[0].fec; - break; - case DTV_ISDBT_LAYERA_MODULATION: - tvp->u.data = c->layer[0].modulation; - break; - case DTV_ISDBT_LAYERA_SEGMENT_COUNT: - tvp->u.data = c->layer[0].segment_count; - break; - case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: - tvp->u.data = c->layer[0].interleaving; - break; - case DTV_ISDBT_LAYERB_FEC: - tvp->u.data = c->layer[1].fec; - break; - case DTV_ISDBT_LAYERB_MODULATION: - tvp->u.data = c->layer[1].modulation; - break; - case DTV_ISDBT_LAYERB_SEGMENT_COUNT: - tvp->u.data = c->layer[1].segment_count; - break; - case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: - tvp->u.data = c->layer[1].interleaving; - break; - case DTV_ISDBT_LAYERC_FEC: - tvp->u.data = c->layer[2].fec; - break; - case DTV_ISDBT_LAYERC_MODULATION: - tvp->u.data = c->layer[2].modulation; - break; - case DTV_ISDBT_LAYERC_SEGMENT_COUNT: - tvp->u.data = c->layer[2].segment_count; - break; - case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: - tvp->u.data = c->layer[2].interleaving; - break; - - /* Multistream support */ - case DTV_STREAM_ID: - case DTV_DVBT2_PLP_ID_LEGACY: - tvp->u.data = c->stream_id; - break; - - /* ATSC-MH */ - case DTV_ATSCMH_FIC_VER: - tvp->u.data = fe->dtv_property_cache.atscmh_fic_ver; - break; - case DTV_ATSCMH_PARADE_ID: - tvp->u.data = fe->dtv_property_cache.atscmh_parade_id; - break; - case DTV_ATSCMH_NOG: - tvp->u.data = fe->dtv_property_cache.atscmh_nog; - break; - case DTV_ATSCMH_TNOG: - tvp->u.data = fe->dtv_property_cache.atscmh_tnog; - break; - case DTV_ATSCMH_SGN: - tvp->u.data = fe->dtv_property_cache.atscmh_sgn; - break; - case DTV_ATSCMH_PRC: - tvp->u.data = fe->dtv_property_cache.atscmh_prc; - break; - case DTV_ATSCMH_RS_FRAME_MODE: - tvp->u.data = fe->dtv_property_cache.atscmh_rs_frame_mode; - break; - case DTV_ATSCMH_RS_FRAME_ENSEMBLE: - tvp->u.data = fe->dtv_property_cache.atscmh_rs_frame_ensemble; - break; - case DTV_ATSCMH_RS_CODE_MODE_PRI: - tvp->u.data = fe->dtv_property_cache.atscmh_rs_code_mode_pri; - break; - case DTV_ATSCMH_RS_CODE_MODE_SEC: - tvp->u.data = fe->dtv_property_cache.atscmh_rs_code_mode_sec; - break; - case DTV_ATSCMH_SCCC_BLOCK_MODE: - tvp->u.data = fe->dtv_property_cache.atscmh_sccc_block_mode; - break; - case DTV_ATSCMH_SCCC_CODE_MODE_A: - tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_a; - break; - case DTV_ATSCMH_SCCC_CODE_MODE_B: - tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_b; - break; - case DTV_ATSCMH_SCCC_CODE_MODE_C: - tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_c; - break; - case DTV_ATSCMH_SCCC_CODE_MODE_D: - tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_d; - break; - - case DTV_LNA: - tvp->u.data = c->lna; - break; - - /* Fill quality measures */ - case DTV_STAT_SIGNAL_STRENGTH: - tvp->u.st = c->strength; - break; - case DTV_STAT_CNR: - tvp->u.st = c->cnr; - break; - case DTV_STAT_PRE_ERROR_BIT_COUNT: - tvp->u.st = c->pre_bit_error; - break; - case DTV_STAT_PRE_TOTAL_BIT_COUNT: - tvp->u.st = c->pre_bit_count; - break; - case DTV_STAT_POST_ERROR_BIT_COUNT: - tvp->u.st = c->post_bit_error; - break; - case DTV_STAT_POST_TOTAL_BIT_COUNT: - tvp->u.st = c->post_bit_count; - break; - case DTV_STAT_ERROR_BLOCK_COUNT: - tvp->u.st = c->block_error; - break; - case DTV_STAT_TOTAL_BLOCK_COUNT: - tvp->u.st = c->block_count; - break; - default: - dev_dbg(fe->dvb->device, - "%s: FE property %d doesn't exist\n", - __func__, tvp->cmd); - return -EINVAL; - } - - /* Allow the frontend to override outgoing properties */ - if (fe->ops.get_property) { - r = fe->ops.get_property(fe, tvp); - if (r < 0) - return r; - } - - dtv_property_dump(fe, tvp); - - return 0; -} - -static int dtv_set_frontend(struct dvb_frontend *fe); - -static bool is_dvbv3_delsys(u32 delsys) -{ - bool status; - - status = (delsys == SYS_DVBT) || (delsys == SYS_DVBC_ANNEX_A) || - (delsys == SYS_DVBS) || (delsys == SYS_ATSC); - - return status; -} - -/** - * emulate_delivery_system - emulate a DVBv5 delivery system with a DVBv3 type - * @fe: struct frontend; - * @delsys: DVBv5 type that will be used for emulation - * - * Provides emulation for delivery systems that are compatible with the old - * DVBv3 call. Among its usages, it provices support for ISDB-T, and allows - * using a DVB-S2 only frontend just like it were a DVB-S, if the frontent - * parameters are compatible with DVB-S spec. - */ -static int emulate_delivery_system(struct dvb_frontend *fe, u32 delsys) -{ - int i; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - - c->delivery_system = delsys; - - /* - * If the call is for ISDB-T, put it into full-seg, auto mode, TV - */ - if (c->delivery_system == SYS_ISDBT) { - dev_dbg(fe->dvb->device, - "%s: Using defaults for SYS_ISDBT\n", - __func__); - - if (!c->bandwidth_hz) - c->bandwidth_hz = 6000000; - - c->isdbt_partial_reception = 0; - c->isdbt_sb_mode = 0; - c->isdbt_sb_subchannel = 0; - c->isdbt_sb_segment_idx = 0; - c->isdbt_sb_segment_count = 0; - c->isdbt_layer_enabled = 7; - for (i = 0; i < 3; i++) { - c->layer[i].fec = FEC_AUTO; - c->layer[i].modulation = QAM_AUTO; - c->layer[i].interleaving = 0; - c->layer[i].segment_count = 0; - } - } - dev_dbg(fe->dvb->device, "%s: change delivery system on cache to %d\n", - __func__, c->delivery_system); - - return 0; -} - -/** - * dvbv5_set_delivery_system - Sets the delivery system for a DVBv5 API call - * @fe: frontend struct - * @desired_system: delivery system requested by the user - * - * A DVBv5 call know what's the desired system it wants. So, set it. - * - * There are, however, a few known issues with early DVBv5 applications that - * are also handled by this logic: - * - * 1) Some early apps use SYS_UNDEFINED as the desired delivery system. - * This is an API violation, but, as we don't want to break userspace, - * convert it to the first supported delivery system. - * 2) Some apps might be using a DVBv5 call in a wrong way, passing, for - * example, SYS_DVBT instead of SYS_ISDBT. This is because early usage of - * ISDB-T provided backward compat with DVB-T. - */ -static int dvbv5_set_delivery_system(struct dvb_frontend *fe, - u32 desired_system) -{ - int ncaps; - u32 delsys = SYS_UNDEFINED; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - enum dvbv3_emulation_type type; - - /* - * It was reported that some old DVBv5 applications were - * filling delivery_system with SYS_UNDEFINED. If this happens, - * assume that the application wants to use the first supported - * delivery system. - */ - if (desired_system == SYS_UNDEFINED) - desired_system = fe->ops.delsys[0]; - - /* - * This is a DVBv5 call. So, it likely knows the supported - * delivery systems. So, check if the desired delivery system is - * supported - */ - ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { - if (fe->ops.delsys[ncaps] == desired_system) { - c->delivery_system = desired_system; - dev_dbg(fe->dvb->device, - "%s: Changing delivery system to %d\n", - __func__, desired_system); - return 0; - } - ncaps++; - } - - /* - * The requested delivery system isn't supported. Maybe userspace - * is requesting a DVBv3 compatible delivery system. - * - * The emulation only works if the desired system is one of the - * delivery systems supported by DVBv3 API - */ - if (!is_dvbv3_delsys(desired_system)) { - dev_dbg(fe->dvb->device, - "%s: Delivery system %d not supported.\n", - __func__, desired_system); - return -EINVAL; - } - - type = dvbv3_type(desired_system); - - /* - * Get the last non-DVBv3 delivery system that has the same type - * of the desired system - */ - ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { - if (dvbv3_type(fe->ops.delsys[ncaps]) == type) - delsys = fe->ops.delsys[ncaps]; - ncaps++; - } - - /* There's nothing compatible with the desired delivery system */ - if (delsys == SYS_UNDEFINED) { - dev_dbg(fe->dvb->device, - "%s: Delivery system %d not supported on emulation mode.\n", - __func__, desired_system); - return -EINVAL; - } - - dev_dbg(fe->dvb->device, - "%s: Using delivery system %d emulated as if it were %d\n", - __func__, delsys, desired_system); - - return emulate_delivery_system(fe, desired_system); -} - -/** - * dvbv3_set_delivery_system - Sets the delivery system for a DVBv3 API call - * @fe: frontend struct - * - * A DVBv3 call doesn't know what's the desired system it wants. It also - * doesn't allow to switch between different types. Due to that, userspace - * should use DVBv5 instead. - * However, in order to avoid breaking userspace API, limited backward - * compatibility support is provided. - * - * There are some delivery systems that are incompatible with DVBv3 calls. - * - * This routine should work fine for frontends that support just one delivery - * system. - * - * For frontends that support multiple frontends: - * 1) It defaults to use the first supported delivery system. There's an - * userspace application that allows changing it at runtime; - * - * 2) If the current delivery system is not compatible with DVBv3, it gets - * the first one that it is compatible. - * - * NOTE: in order for this to work with applications like Kaffeine that - * uses a DVBv5 call for DVB-S2 and a DVBv3 call to go back to - * DVB-S, drivers that support both DVB-S and DVB-S2 should have the - * SYS_DVBS entry before the SYS_DVBS2, otherwise it won't switch back - * to DVB-S. - */ -static int dvbv3_set_delivery_system(struct dvb_frontend *fe) -{ - int ncaps; - u32 delsys = SYS_UNDEFINED; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - - /* If not set yet, defaults to the first supported delivery system */ - if (c->delivery_system == SYS_UNDEFINED) - c->delivery_system = fe->ops.delsys[0]; - - /* - * Trivial case: just use the current one, if it already a DVBv3 - * delivery system - */ - if (is_dvbv3_delsys(c->delivery_system)) { - dev_dbg(fe->dvb->device, - "%s: Using delivery system to %d\n", - __func__, c->delivery_system); - return 0; - } - - /* - * Seek for the first delivery system that it is compatible with a - * DVBv3 standard - */ - ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { - if (dvbv3_type(fe->ops.delsys[ncaps]) != DVBV3_UNKNOWN) { - delsys = fe->ops.delsys[ncaps]; - break; - } - ncaps++; - } - if (delsys == SYS_UNDEFINED) { - dev_dbg(fe->dvb->device, - "%s: Couldn't find a delivery system that works with FE_SET_FRONTEND\n", - __func__); - return -EINVAL; - } - return emulate_delivery_system(fe, delsys); -} - -static int dtv_property_process_set(struct dvb_frontend *fe, - struct dtv_property *tvp, - struct file *file) -{ - int r = 0; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - - /* Allow the frontend to validate incoming properties */ - if (fe->ops.set_property) { - r = fe->ops.set_property(fe, tvp); - if (r < 0) - return r; - } - - switch(tvp->cmd) { - case DTV_CLEAR: - /* - * Reset a cache of data specific to the frontend here. This does - * not effect hardware. - */ - dvb_frontend_clear_cache(fe); - break; - case DTV_TUNE: - /* interpret the cache of data, build either a traditional frontend - * tunerequest so we can pass validation in the FE_SET_FRONTEND - * ioctl. - */ - c->state = tvp->cmd; - dev_dbg(fe->dvb->device, "%s: Finalised property cache\n", - __func__); - - r = dtv_set_frontend(fe); - break; - case DTV_FREQUENCY: - c->frequency = tvp->u.data; - break; - case DTV_MODULATION: - c->modulation = tvp->u.data; - break; - case DTV_BANDWIDTH_HZ: - c->bandwidth_hz = tvp->u.data; - break; - case DTV_INVERSION: - c->inversion = tvp->u.data; - break; - case DTV_SYMBOL_RATE: - c->symbol_rate = tvp->u.data; - break; - case DTV_INNER_FEC: - c->fec_inner = tvp->u.data; - break; - case DTV_PILOT: - c->pilot = tvp->u.data; - break; - case DTV_ROLLOFF: - c->rolloff = tvp->u.data; - break; - case DTV_DELIVERY_SYSTEM: - r = dvbv5_set_delivery_system(fe, tvp->u.data); - break; - case DTV_VOLTAGE: - c->voltage = tvp->u.data; - r = dvb_frontend_ioctl_legacy(file, FE_SET_VOLTAGE, - (void *)c->voltage); - break; - case DTV_TONE: - c->sectone = tvp->u.data; - r = dvb_frontend_ioctl_legacy(file, FE_SET_TONE, - (void *)c->sectone); - break; - case DTV_CODE_RATE_HP: - c->code_rate_HP = tvp->u.data; - break; - case DTV_CODE_RATE_LP: - c->code_rate_LP = tvp->u.data; - break; - case DTV_GUARD_INTERVAL: - c->guard_interval = tvp->u.data; - break; - case DTV_TRANSMISSION_MODE: - c->transmission_mode = tvp->u.data; - break; - case DTV_HIERARCHY: - c->hierarchy = tvp->u.data; - break; - case DTV_INTERLEAVING: - c->interleaving = tvp->u.data; - break; - - /* ISDB-T Support here */ - case DTV_ISDBT_PARTIAL_RECEPTION: - c->isdbt_partial_reception = tvp->u.data; - break; - case DTV_ISDBT_SOUND_BROADCASTING: - c->isdbt_sb_mode = tvp->u.data; - break; - case DTV_ISDBT_SB_SUBCHANNEL_ID: - c->isdbt_sb_subchannel = tvp->u.data; - break; - case DTV_ISDBT_SB_SEGMENT_IDX: - c->isdbt_sb_segment_idx = tvp->u.data; - break; - case DTV_ISDBT_SB_SEGMENT_COUNT: - c->isdbt_sb_segment_count = tvp->u.data; - break; - case DTV_ISDBT_LAYER_ENABLED: - c->isdbt_layer_enabled = tvp->u.data; - break; - case DTV_ISDBT_LAYERA_FEC: - c->layer[0].fec = tvp->u.data; - break; - case DTV_ISDBT_LAYERA_MODULATION: - c->layer[0].modulation = tvp->u.data; - break; - case DTV_ISDBT_LAYERA_SEGMENT_COUNT: - c->layer[0].segment_count = tvp->u.data; - break; - case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: - c->layer[0].interleaving = tvp->u.data; - break; - case DTV_ISDBT_LAYERB_FEC: - c->layer[1].fec = tvp->u.data; - break; - case DTV_ISDBT_LAYERB_MODULATION: - c->layer[1].modulation = tvp->u.data; - break; - case DTV_ISDBT_LAYERB_SEGMENT_COUNT: - c->layer[1].segment_count = tvp->u.data; - break; - case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: - c->layer[1].interleaving = tvp->u.data; - break; - case DTV_ISDBT_LAYERC_FEC: - c->layer[2].fec = tvp->u.data; - break; - case DTV_ISDBT_LAYERC_MODULATION: - c->layer[2].modulation = tvp->u.data; - break; - case DTV_ISDBT_LAYERC_SEGMENT_COUNT: - c->layer[2].segment_count = tvp->u.data; - break; - case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: - c->layer[2].interleaving = tvp->u.data; - break; - - /* Multistream support */ - case DTV_STREAM_ID: - case DTV_DVBT2_PLP_ID_LEGACY: - c->stream_id = tvp->u.data; - break; - - /* ATSC-MH */ - case DTV_ATSCMH_PARADE_ID: - fe->dtv_property_cache.atscmh_parade_id = tvp->u.data; - break; - case DTV_ATSCMH_RS_FRAME_ENSEMBLE: - fe->dtv_property_cache.atscmh_rs_frame_ensemble = tvp->u.data; - break; - - case DTV_LNA: - c->lna = tvp->u.data; - if (fe->ops.set_lna) - r = fe->ops.set_lna(fe); - break; - - default: - return -EINVAL; - } - - return r; -} - -static int dvb_frontend_ioctl(struct file *file, - unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_frontend *fe = dvbdev->priv; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - int err = -EOPNOTSUPP; - - dev_dbg(fe->dvb->device, "%s: (%d)\n", __func__, _IOC_NR(cmd)); - if (down_interruptible(&fepriv->sem)) - return -ERESTARTSYS; - - if (fepriv->exit != DVB_FE_NO_EXIT) { - up(&fepriv->sem); - return -ENODEV; - } - - if ((file->f_flags & O_ACCMODE) == O_RDONLY && - (_IOC_DIR(cmd) != _IOC_READ || cmd == FE_GET_EVENT || - cmd == FE_DISEQC_RECV_SLAVE_REPLY)) { - up(&fepriv->sem); - return -EPERM; - } - - if ((cmd == FE_SET_PROPERTY) || (cmd == FE_GET_PROPERTY)) - err = dvb_frontend_ioctl_properties(file, cmd, parg); - else { - c->state = DTV_UNDEFINED; - err = dvb_frontend_ioctl_legacy(file, cmd, parg); - } - - up(&fepriv->sem); - return err; -} - -static int dvb_frontend_ioctl_properties(struct file *file, - unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_frontend *fe = dvbdev->priv; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - int err = 0; - - struct dtv_properties *tvps = NULL; - struct dtv_property *tvp = NULL; - int i; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - if(cmd == FE_SET_PROPERTY) { - tvps = (struct dtv_properties __user *)parg; - - dev_dbg(fe->dvb->device, "%s: properties.num = %d\n", __func__, tvps->num); - dev_dbg(fe->dvb->device, "%s: properties.props = %p\n", __func__, tvps->props); - - /* Put an arbitrary limit on the number of messages that can - * be sent at once */ - if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS)) - return -EINVAL; - - tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL); - if (!tvp) { - err = -ENOMEM; - goto out; - } - - if (copy_from_user(tvp, tvps->props, tvps->num * sizeof(struct dtv_property))) { - err = -EFAULT; - goto out; - } - - for (i = 0; i < tvps->num; i++) { - err = dtv_property_process_set(fe, tvp + i, file); - if (err < 0) - goto out; - (tvp + i)->result = err; - } - - if (c->state == DTV_TUNE) - dev_dbg(fe->dvb->device, "%s: Property cache is full, tuning\n", __func__); - - } else - if(cmd == FE_GET_PROPERTY) { - tvps = (struct dtv_properties __user *)parg; - - dev_dbg(fe->dvb->device, "%s: properties.num = %d\n", __func__, tvps->num); - dev_dbg(fe->dvb->device, "%s: properties.props = %p\n", __func__, tvps->props); - - /* Put an arbitrary limit on the number of messages that can - * be sent at once */ - if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS)) - return -EINVAL; - - tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL); - if (!tvp) { - err = -ENOMEM; - goto out; - } - - if (copy_from_user(tvp, tvps->props, tvps->num * sizeof(struct dtv_property))) { - err = -EFAULT; - goto out; - } - - /* - * Fills the cache out struct with the cache contents, plus - * the data retrieved from get_frontend, if the frontend - * is not idle. Otherwise, returns the cached content - */ - if (fepriv->state != FESTATE_IDLE) { - err = dtv_get_frontend(fe, NULL); - if (err < 0) - goto out; - } - for (i = 0; i < tvps->num; i++) { - err = dtv_property_process_get(fe, c, tvp + i, file); - if (err < 0) - goto out; - (tvp + i)->result = err; - } - - if (copy_to_user(tvps->props, tvp, tvps->num * sizeof(struct dtv_property))) { - err = -EFAULT; - goto out; - } - - } else - err = -EOPNOTSUPP; - -out: - kfree(tvp); - return err; -} - -static int dtv_set_frontend(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - struct dvb_frontend_tune_settings fetunesettings; - u32 rolloff = 0; - - if (dvb_frontend_check_parameters(fe) < 0) - return -EINVAL; - - /* - * Initialize output parameters to match the values given by - * the user. FE_SET_FRONTEND triggers an initial frontend event - * with status = 0, which copies output parameters to userspace. - */ - dtv_property_legacy_params_sync(fe, &fepriv->parameters_out); - - /* - * Be sure that the bandwidth will be filled for all - * non-satellite systems, as tuners need to know what - * low pass/Nyquist half filter should be applied, in - * order to avoid inter-channel noise. - * - * ISDB-T and DVB-T/T2 already sets bandwidth. - * ATSC and DVB-C don't set, so, the core should fill it. - * - * On DVB-C Annex A and C, the bandwidth is a function of - * the roll-off and symbol rate. Annex B defines different - * roll-off factors depending on the modulation. Fortunately, - * Annex B is only used with 6MHz, so there's no need to - * calculate it. - * - * While not officially supported, a side effect of handling it at - * the cache level is that a program could retrieve the bandwidth - * via DTV_BANDWIDTH_HZ, which may be useful for test programs. - */ - switch (c->delivery_system) { - case SYS_ATSC: - case SYS_DVBC_ANNEX_B: - c->bandwidth_hz = 6000000; - break; - case SYS_DVBC_ANNEX_A: - rolloff = 115; - break; - case SYS_DVBC_ANNEX_C: - rolloff = 113; - break; - default: - break; - } - if (rolloff) - c->bandwidth_hz = (c->symbol_rate * rolloff) / 100; - - /* force auto frequency inversion if requested */ - if (dvb_force_auto_inversion) - c->inversion = INVERSION_AUTO; - - /* - * without hierarchical coding code_rate_LP is irrelevant, - * so we tolerate the otherwise invalid FEC_NONE setting - */ - if (c->hierarchy == HIERARCHY_NONE && c->code_rate_LP == FEC_NONE) - c->code_rate_LP = FEC_AUTO; - - /* get frontend-specific tuning settings */ - memset(&fetunesettings, 0, sizeof(struct dvb_frontend_tune_settings)); - if (fe->ops.get_tune_settings && (fe->ops.get_tune_settings(fe, &fetunesettings) == 0)) { - fepriv->min_delay = (fetunesettings.min_delay_ms * HZ) / 1000; - fepriv->max_drift = fetunesettings.max_drift; - fepriv->step_size = fetunesettings.step_size; - } else { - /* default values */ - switch (c->delivery_system) { - case SYS_DVBS: - case SYS_DVBS2: - case SYS_ISDBS: - case SYS_TURBO: - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: - fepriv->min_delay = HZ / 20; - fepriv->step_size = c->symbol_rate / 16000; - fepriv->max_drift = c->symbol_rate / 2000; - break; - case SYS_DVBT: - case SYS_DVBT2: - case SYS_ISDBT: - case SYS_DTMB: - fepriv->min_delay = HZ / 20; - fepriv->step_size = fe->ops.info.frequency_stepsize * 2; - fepriv->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1; - break; - default: - /* - * FIXME: This sounds wrong! if freqency_stepsize is - * defined by the frontend, why not use it??? - */ - fepriv->min_delay = HZ / 20; - fepriv->step_size = 0; /* no zigzag */ - fepriv->max_drift = 0; - break; - } - } - if (dvb_override_tune_delay > 0) - fepriv->min_delay = (dvb_override_tune_delay * HZ) / 1000; - - fepriv->state = FESTATE_RETUNE; - - /* Request the search algorithm to search */ - fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; - - dvb_frontend_clear_events(fe); - dvb_frontend_add_event(fe, 0); - dvb_frontend_wakeup(fe); - fepriv->status = 0; - - return 0; -} - - -static int dvb_frontend_ioctl_legacy(struct file *file, - unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_frontend *fe = dvbdev->priv; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - int err = -EOPNOTSUPP; - - switch (cmd) { - case FE_GET_INFO: { - struct dvb_frontend_info* info = parg; - - memcpy(info, &fe->ops.info, sizeof(struct dvb_frontend_info)); - dvb_frontend_get_frequency_limits(fe, &info->frequency_min, &info->frequency_max); - - /* - * Associate the 4 delivery systems supported by DVBv3 - * API with their DVBv5 counterpart. For the other standards, - * use the closest type, assuming that it would hopefully - * work with a DVBv3 application. - * It should be noticed that, on multi-frontend devices with - * different types (terrestrial and cable, for example), - * a pure DVBv3 application won't be able to use all delivery - * systems. Yet, changing the DVBv5 cache to the other delivery - * system should be enough for making it work. - */ - switch (dvbv3_type(c->delivery_system)) { - case DVBV3_QPSK: - info->type = FE_QPSK; - break; - case DVBV3_ATSC: - info->type = FE_ATSC; - break; - case DVBV3_QAM: - info->type = FE_QAM; - break; - case DVBV3_OFDM: - info->type = FE_OFDM; - break; - default: - dev_err(fe->dvb->device, - "%s: doesn't know how to handle a DVBv3 call to delivery system %i\n", - __func__, c->delivery_system); - fe->ops.info.type = FE_OFDM; - } - dev_dbg(fe->dvb->device, "%s: current delivery system on cache: %d, V3 type: %d\n", - __func__, c->delivery_system, fe->ops.info.type); - - /* Force the CAN_INVERSION_AUTO bit on. If the frontend doesn't - * do it, it is done for it. */ - info->caps |= FE_CAN_INVERSION_AUTO; - err = 0; - break; - } - - case FE_READ_STATUS: { - fe_status_t* status = parg; - - /* if retune was requested but hasn't occurred yet, prevent - * that user get signal state from previous tuning */ - if (fepriv->state == FESTATE_RETUNE || - fepriv->state == FESTATE_ERROR) { - err=0; - *status = 0; - break; - } - - if (fe->ops.read_status) - err = fe->ops.read_status(fe, status); - break; - } - - case FE_READ_BER: - if (fe->ops.read_ber) { - if (fepriv->thread) - err = fe->ops.read_ber(fe, (__u32 *) parg); - else - err = -EAGAIN; - } - break; - - case FE_READ_SIGNAL_STRENGTH: - if (fe->ops.read_signal_strength) { - if (fepriv->thread) - err = fe->ops.read_signal_strength(fe, (__u16 *) parg); - else - err = -EAGAIN; - } - break; - - case FE_READ_SNR: - if (fe->ops.read_snr) { - if (fepriv->thread) - err = fe->ops.read_snr(fe, (__u16 *) parg); - else - err = -EAGAIN; - } - break; - - case FE_READ_UNCORRECTED_BLOCKS: - if (fe->ops.read_ucblocks) { - if (fepriv->thread) - err = fe->ops.read_ucblocks(fe, (__u32 *) parg); - else - err = -EAGAIN; - } - break; - - case FE_DISEQC_RESET_OVERLOAD: - if (fe->ops.diseqc_reset_overload) { - err = fe->ops.diseqc_reset_overload(fe); - fepriv->state = FESTATE_DISEQC; - fepriv->status = 0; - } - break; - - case FE_DISEQC_SEND_MASTER_CMD: - if (fe->ops.diseqc_send_master_cmd) { - err = fe->ops.diseqc_send_master_cmd(fe, (struct dvb_diseqc_master_cmd*) parg); - fepriv->state = FESTATE_DISEQC; - fepriv->status = 0; - } - break; - - case FE_DISEQC_SEND_BURST: - if (fe->ops.diseqc_send_burst) { - err = fe->ops.diseqc_send_burst(fe, (fe_sec_mini_cmd_t) parg); - fepriv->state = FESTATE_DISEQC; - fepriv->status = 0; - } - break; - - case FE_SET_TONE: - if (fe->ops.set_tone) { - err = fe->ops.set_tone(fe, (fe_sec_tone_mode_t) parg); - fepriv->tone = (fe_sec_tone_mode_t) parg; - fepriv->state = FESTATE_DISEQC; - fepriv->status = 0; - } - break; - - case FE_SET_VOLTAGE: - if (fe->ops.set_voltage) { - err = fe->ops.set_voltage(fe, (fe_sec_voltage_t) parg); - fepriv->voltage = (fe_sec_voltage_t) parg; - fepriv->state = FESTATE_DISEQC; - fepriv->status = 0; - } - break; - - case FE_DISHNETWORK_SEND_LEGACY_CMD: - if (fe->ops.dishnetwork_send_legacy_command) { - err = fe->ops.dishnetwork_send_legacy_command(fe, (unsigned long) parg); - fepriv->state = FESTATE_DISEQC; - fepriv->status = 0; - } else if (fe->ops.set_voltage) { - /* - * NOTE: This is a fallback condition. Some frontends - * (stv0299 for instance) take longer than 8msec to - * respond to a set_voltage command. Those switches - * need custom routines to switch properly. For all - * other frontends, the following should work ok. - * Dish network legacy switches (as used by Dish500) - * are controlled by sending 9-bit command words - * spaced 8msec apart. - * the actual command word is switch/port dependent - * so it is up to the userspace application to send - * the right command. - * The command must always start with a '0' after - * initialization, so parg is 8 bits and does not - * include the initialization or start bit - */ - unsigned long swcmd = ((unsigned long) parg) << 1; - struct timeval nexttime; - struct timeval tv[10]; - int i; - u8 last = 1; - if (dvb_frontend_debug) - printk("%s switch command: 0x%04lx\n", __func__, swcmd); - do_gettimeofday(&nexttime); - if (dvb_frontend_debug) - tv[0] = nexttime; - /* before sending a command, initialize by sending - * a 32ms 18V to the switch - */ - fe->ops.set_voltage(fe, SEC_VOLTAGE_18); - dvb_frontend_sleep_until(&nexttime, 32000); - - for (i = 0; i < 9; i++) { - if (dvb_frontend_debug) - do_gettimeofday(&tv[i + 1]); - if ((swcmd & 0x01) != last) { - /* set voltage to (last ? 13V : 18V) */ - fe->ops.set_voltage(fe, (last) ? SEC_VOLTAGE_13 : SEC_VOLTAGE_18); - last = (last) ? 0 : 1; - } - swcmd = swcmd >> 1; - if (i != 8) - dvb_frontend_sleep_until(&nexttime, 8000); - } - if (dvb_frontend_debug) { - printk("%s(%d): switch delay (should be 32k followed by all 8k\n", - __func__, fe->dvb->num); - for (i = 1; i < 10; i++) - printk("%d: %d\n", i, timeval_usec_diff(tv[i-1] , tv[i])); - } - err = 0; - fepriv->state = FESTATE_DISEQC; - fepriv->status = 0; - } - break; - - case FE_DISEQC_RECV_SLAVE_REPLY: - if (fe->ops.diseqc_recv_slave_reply) - err = fe->ops.diseqc_recv_slave_reply(fe, (struct dvb_diseqc_slave_reply*) parg); - break; - - case FE_ENABLE_HIGH_LNB_VOLTAGE: - if (fe->ops.enable_high_lnb_voltage) - err = fe->ops.enable_high_lnb_voltage(fe, (long) parg); - break; - - case FE_SET_FRONTEND: - err = dvbv3_set_delivery_system(fe); - if (err) - break; - - err = dtv_property_cache_sync(fe, c, parg); - if (err) - break; - err = dtv_set_frontend(fe); - break; - case FE_GET_EVENT: - err = dvb_frontend_get_event (fe, parg, file->f_flags); - break; - - case FE_GET_FRONTEND: - err = dtv_get_frontend(fe, parg); - break; - - case FE_SET_FRONTEND_TUNE_MODE: - fepriv->tune_mode_flags = (unsigned long) parg; - err = 0; - break; - } - - return err; -} - - -static unsigned int dvb_frontend_poll(struct file *file, struct poll_table_struct *wait) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_frontend *fe = dvbdev->priv; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - - //dev_dbg_ratelimited(fe->dvb->device, "%s:\n", __func__); - - poll_wait (file, &fepriv->events.wait_queue, wait); - - if (fepriv->events.eventw != fepriv->events.eventr) - return (POLLIN | POLLRDNORM | POLLPRI); - - return 0; -} - -static int dvb_frontend_open(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_frontend *fe = dvbdev->priv; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dvb_adapter *adapter = fe->dvb; - int ret; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - if (fepriv->exit == DVB_FE_DEVICE_REMOVED) - return -ENODEV; - - if (adapter->mfe_shared) { - mutex_lock (&adapter->mfe_lock); - - if (adapter->mfe_dvbdev == NULL) - adapter->mfe_dvbdev = dvbdev; - - else if (adapter->mfe_dvbdev != dvbdev) { - struct dvb_device - *mfedev = adapter->mfe_dvbdev; - struct dvb_frontend - *mfe = mfedev->priv; - struct dvb_frontend_private - *mfepriv = mfe->frontend_priv; - int mferetry = (dvb_mfe_wait_time << 1); - - mutex_unlock (&adapter->mfe_lock); - while (mferetry-- && (mfedev->users != -1 || - mfepriv->thread != NULL)) { - if(msleep_interruptible(500)) { - if(signal_pending(current)) - return -EINTR; - } - } - - mutex_lock (&adapter->mfe_lock); - if(adapter->mfe_dvbdev != dvbdev) { - mfedev = adapter->mfe_dvbdev; - mfe = mfedev->priv; - mfepriv = mfe->frontend_priv; - if (mfedev->users != -1 || - mfepriv->thread != NULL) { - mutex_unlock (&adapter->mfe_lock); - return -EBUSY; - } - adapter->mfe_dvbdev = dvbdev; - } - } - } - - if (dvbdev->users == -1 && fe->ops.ts_bus_ctrl) { - if ((ret = fe->ops.ts_bus_ctrl(fe, 1)) < 0) - goto err0; - - /* If we took control of the bus, we need to force - reinitialization. This is because many ts_bus_ctrl() - functions strobe the RESET pin on the demod, and if the - frontend thread already exists then the dvb_init() routine - won't get called (which is what usually does initial - register configuration). */ - fepriv->reinitialise = 1; - } - - if ((ret = dvb_generic_open (inode, file)) < 0) - goto err1; - - if ((file->f_flags & O_ACCMODE) != O_RDONLY) { - /* normal tune mode when opened R/W */ - fepriv->tune_mode_flags &= ~FE_TUNE_MODE_ONESHOT; - fepriv->tone = -1; - fepriv->voltage = -1; - - ret = dvb_frontend_start (fe); - if (ret) - goto err2; - - /* empty event queue */ - fepriv->events.eventr = fepriv->events.eventw = 0; - } - - if (adapter->mfe_shared) - mutex_unlock (&adapter->mfe_lock); - return ret; - -err2: - dvb_generic_release(inode, file); -err1: - if (dvbdev->users == -1 && fe->ops.ts_bus_ctrl) - fe->ops.ts_bus_ctrl(fe, 0); -err0: - if (adapter->mfe_shared) - mutex_unlock (&adapter->mfe_lock); - return ret; -} - -static int dvb_frontend_release(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_frontend *fe = dvbdev->priv; - struct dvb_frontend_private *fepriv = fe->frontend_priv; - int ret; - - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - if ((file->f_flags & O_ACCMODE) != O_RDONLY) { - fepriv->release_jiffies = jiffies; - mb(); - } - - ret = dvb_generic_release (inode, file); - - if (dvbdev->users == -1) { - wake_up(&fepriv->wait_queue); - if (fepriv->exit != DVB_FE_NO_EXIT) - wake_up(&dvbdev->wait_queue); - if (fe->ops.ts_bus_ctrl) - fe->ops.ts_bus_ctrl(fe, 0); - } - - return ret; -} - -static const struct file_operations dvb_frontend_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = dvb_generic_ioctl, - .poll = dvb_frontend_poll, - .open = dvb_frontend_open, - .release = dvb_frontend_release, - .llseek = noop_llseek, -}; - -int dvb_frontend_suspend(struct dvb_frontend *fe) -{ - int ret = 0; - - dev_dbg(fe->dvb->device, "%s: adap=%d fe=%d\n", __func__, fe->dvb->num, - fe->id); - - if (fe->ops.tuner_ops.sleep) - ret = fe->ops.tuner_ops.sleep(fe); - - if (fe->ops.sleep) - ret = fe->ops.sleep(fe); - - return ret; -} -EXPORT_SYMBOL(dvb_frontend_suspend); - -int dvb_frontend_resume(struct dvb_frontend *fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - int ret = 0; - - dev_dbg(fe->dvb->device, "%s: adap=%d fe=%d\n", __func__, fe->dvb->num, - fe->id); - - if (fe->ops.init) - ret = fe->ops.init(fe); - - if (fe->ops.tuner_ops.init) - ret = fe->ops.tuner_ops.init(fe); - - fepriv->state = FESTATE_RETUNE; - dvb_frontend_wakeup(fe); - - return ret; -} -EXPORT_SYMBOL(dvb_frontend_resume); - -int dvb_register_frontend(struct dvb_adapter* dvb, - struct dvb_frontend* fe) -{ - struct dvb_frontend_private *fepriv; - static const struct dvb_device dvbdev_template = { - .users = ~0, - .writers = 1, - .readers = (~0)-1, - .fops = &dvb_frontend_fops, - .kernel_ioctl = dvb_frontend_ioctl - }; - - dev_dbg(dvb->device, "%s:\n", __func__); - - if (mutex_lock_interruptible(&frontend_mutex)) - return -ERESTARTSYS; - - fe->frontend_priv = kzalloc(sizeof(struct dvb_frontend_private), GFP_KERNEL); - if (fe->frontend_priv == NULL) { - mutex_unlock(&frontend_mutex); - return -ENOMEM; - } - fepriv = fe->frontend_priv; - - sema_init(&fepriv->sem, 1); - init_waitqueue_head (&fepriv->wait_queue); - init_waitqueue_head (&fepriv->events.wait_queue); - mutex_init(&fepriv->events.mtx); - fe->dvb = dvb; - fepriv->inversion = INVERSION_OFF; - - dvb_register_device (fe->dvb, &fepriv->dvbdev, &dvbdev_template, - fe, DVB_DEVICE_FRONTEND); - - dev_info(fe->dvb->device, - "DVB: registering adapter %i frontend %i (%s)...\n", - fe->dvb->num, fepriv->dvbdev->id, fe->ops.info.name); - - /* - * Initialize the cache to the proper values according with the - * first supported delivery system (ops->delsys[0]) - */ - - fe->dtv_property_cache.delivery_system = fe->ops.delsys[0]; - dvb_frontend_clear_cache(fe); - - mutex_unlock(&frontend_mutex); - return 0; -} -EXPORT_SYMBOL(dvb_register_frontend); - -int dvb_unregister_frontend(struct dvb_frontend* fe) -{ - struct dvb_frontend_private *fepriv = fe->frontend_priv; - dev_dbg(fe->dvb->device, "%s:\n", __func__); - - mutex_lock(&frontend_mutex); - dvb_frontend_stop (fe); - mutex_unlock(&frontend_mutex); - - if (fepriv->dvbdev->users < -1) - wait_event(fepriv->dvbdev->wait_queue, - fepriv->dvbdev->users==-1); - - mutex_lock(&frontend_mutex); - dvb_unregister_device (fepriv->dvbdev); - - /* fe is invalid now */ - kfree(fepriv); - mutex_unlock(&frontend_mutex); - return 0; -} -EXPORT_SYMBOL(dvb_unregister_frontend); - -#ifdef CONFIG_MEDIA_ATTACH -void dvb_frontend_detach(struct dvb_frontend* fe) -{ - void *ptr; - - if (fe->ops.release_sec) { - fe->ops.release_sec(fe); - symbol_put_addr(fe->ops.release_sec); - } - if (fe->ops.tuner_ops.release) { - fe->ops.tuner_ops.release(fe); - symbol_put_addr(fe->ops.tuner_ops.release); - } - if (fe->ops.analog_ops.release) { - fe->ops.analog_ops.release(fe); - symbol_put_addr(fe->ops.analog_ops.release); - } - ptr = (void*)fe->ops.release; - if (ptr) { - fe->ops.release(fe); - symbol_put_addr(ptr); - } -} -#else -void dvb_frontend_detach(struct dvb_frontend* fe) -{ - if (fe->ops.release_sec) - fe->ops.release_sec(fe); - if (fe->ops.tuner_ops.release) - fe->ops.tuner_ops.release(fe); - if (fe->ops.analog_ops.release) - fe->ops.analog_ops.release(fe); - if (fe->ops.release) - fe->ops.release(fe); -} -#endif -EXPORT_SYMBOL(dvb_frontend_detach); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_frontend.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,437 +0,0 @@ -/* - * dvb_frontend.h - * - * Copyright (C) 2001 convergence integrated media GmbH - * Copyright (C) 2004 convergence GmbH - * - * Written by Ralph Metzler - * Overhauled by Holger Waechtler - * Kernel I2C stuff by Michael Hunold - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVB_FRONTEND_H_ -#define _DVB_FRONTEND_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "dvbdev.h" - -/* - * Maximum number of Delivery systems per frontend. It - * should be smaller or equal to 32 - */ -#define MAX_DELSYS 8 - -struct dvb_frontend_tune_settings { - int min_delay_ms; - int step_size; - int max_drift; -}; - -struct dvb_frontend; - -struct dvb_tuner_info { - char name[128]; - - u32 frequency_min; - u32 frequency_max; - u32 frequency_step; - - u32 bandwidth_min; - u32 bandwidth_max; - u32 bandwidth_step; -}; - -struct analog_parameters { - unsigned int frequency; - unsigned int mode; - unsigned int audmode; - u64 std; -}; - -enum dvbfe_modcod { - DVBFE_MODCOD_DUMMY_PLFRAME = 0, - DVBFE_MODCOD_QPSK_1_4, - DVBFE_MODCOD_QPSK_1_3, - DVBFE_MODCOD_QPSK_2_5, - DVBFE_MODCOD_QPSK_1_2, - DVBFE_MODCOD_QPSK_3_5, - DVBFE_MODCOD_QPSK_2_3, - DVBFE_MODCOD_QPSK_3_4, - DVBFE_MODCOD_QPSK_4_5, - DVBFE_MODCOD_QPSK_5_6, - DVBFE_MODCOD_QPSK_8_9, - DVBFE_MODCOD_QPSK_9_10, - DVBFE_MODCOD_8PSK_3_5, - DVBFE_MODCOD_8PSK_2_3, - DVBFE_MODCOD_8PSK_3_4, - DVBFE_MODCOD_8PSK_5_6, - DVBFE_MODCOD_8PSK_8_9, - DVBFE_MODCOD_8PSK_9_10, - DVBFE_MODCOD_16APSK_2_3, - DVBFE_MODCOD_16APSK_3_4, - DVBFE_MODCOD_16APSK_4_5, - DVBFE_MODCOD_16APSK_5_6, - DVBFE_MODCOD_16APSK_8_9, - DVBFE_MODCOD_16APSK_9_10, - DVBFE_MODCOD_32APSK_3_4, - DVBFE_MODCOD_32APSK_4_5, - DVBFE_MODCOD_32APSK_5_6, - DVBFE_MODCOD_32APSK_8_9, - DVBFE_MODCOD_32APSK_9_10, - DVBFE_MODCOD_RESERVED_1, - DVBFE_MODCOD_BPSK_1_3, - DVBFE_MODCOD_BPSK_1_4, - DVBFE_MODCOD_RESERVED_2 -}; - -enum tuner_param { - DVBFE_TUNER_FREQUENCY = (1 << 0), - DVBFE_TUNER_TUNERSTEP = (1 << 1), - DVBFE_TUNER_IFFREQ = (1 << 2), - DVBFE_TUNER_BANDWIDTH = (1 << 3), - DVBFE_TUNER_REFCLOCK = (1 << 4), - DVBFE_TUNER_IQSENSE = (1 << 5), - DVBFE_TUNER_DUMMY = (1 << 31) -}; - -/* - * ALGO_HW: (Hardware Algorithm) - * ---------------------------------------------------------------- - * Devices that support this algorithm do everything in hardware - * and no software support is needed to handle them. - * Requesting these devices to LOCK is the only thing required, - * device is supposed to do everything in the hardware. - * - * ALGO_SW: (Software Algorithm) - * ---------------------------------------------------------------- - * These are dumb devices, that require software to do everything - * - * ALGO_CUSTOM: (Customizable Agorithm) - * ---------------------------------------------------------------- - * Devices having this algorithm can be customized to have specific - * algorithms in the frontend driver, rather than simply doing a - * software zig-zag. In this case the zigzag maybe hardware assisted - * or it maybe completely done in hardware. In all cases, usage of - * this algorithm, in conjunction with the search and track - * callbacks, utilizes the driver specific algorithm. - * - * ALGO_RECOVERY: (Recovery Algorithm) - * ---------------------------------------------------------------- - * These devices have AUTO recovery capabilities from LOCK failure - */ -enum dvbfe_algo { - DVBFE_ALGO_HW = (1 << 0), - DVBFE_ALGO_SW = (1 << 1), - DVBFE_ALGO_CUSTOM = (1 << 2), - DVBFE_ALGO_RECOVERY = (1 << 31) -}; - -struct tuner_state { - u32 frequency; - u32 tunerstep; - u32 ifreq; - u32 bandwidth; - u32 iqsense; - u32 refclock; -}; - -/* - * search callback possible return status - * - * DVBFE_ALGO_SEARCH_SUCCESS - * The frontend search algorithm completed and returned successfully - * - * DVBFE_ALGO_SEARCH_ASLEEP - * The frontend search algorithm is sleeping - * - * DVBFE_ALGO_SEARCH_FAILED - * The frontend search for a signal failed - * - * DVBFE_ALGO_SEARCH_INVALID - * The frontend search algorith was probably supplied with invalid - * parameters and the search is an invalid one - * - * DVBFE_ALGO_SEARCH_ERROR - * The frontend search algorithm failed due to some error - * - * DVBFE_ALGO_SEARCH_AGAIN - * The frontend search algorithm was requested to search again - */ -enum dvbfe_search { - DVBFE_ALGO_SEARCH_SUCCESS = (1 << 0), - DVBFE_ALGO_SEARCH_ASLEEP = (1 << 1), - DVBFE_ALGO_SEARCH_FAILED = (1 << 2), - DVBFE_ALGO_SEARCH_INVALID = (1 << 3), - DVBFE_ALGO_SEARCH_AGAIN = (1 << 4), - DVBFE_ALGO_SEARCH_ERROR = (1 << 31), -}; - - -struct dvb_tuner_ops { - - struct dvb_tuner_info info; - - int (*release)(struct dvb_frontend *fe); - int (*init)(struct dvb_frontend *fe); - int (*sleep)(struct dvb_frontend *fe); - - /** This is for simple PLLs - set all parameters in one go. */ - int (*set_params)(struct dvb_frontend *fe); - int (*set_analog_params)(struct dvb_frontend *fe, struct analog_parameters *p); - - /** This is support for demods like the mt352 - fills out the supplied buffer with what to write. */ - int (*calc_regs)(struct dvb_frontend *fe, u8 *buf, int buf_len); - - /** This is to allow setting tuner-specific configs */ - int (*set_config)(struct dvb_frontend *fe, void *priv_cfg); - - int (*get_frequency)(struct dvb_frontend *fe, u32 *frequency); - int (*get_bandwidth)(struct dvb_frontend *fe, u32 *bandwidth); - int (*get_if_frequency)(struct dvb_frontend *fe, u32 *frequency); - -#define TUNER_STATUS_LOCKED 1 -#define TUNER_STATUS_STEREO 2 - int (*get_status)(struct dvb_frontend *fe, u32 *status); - int (*get_rf_strength)(struct dvb_frontend *fe, u16 *strength); - int (*get_afc)(struct dvb_frontend *fe, s32 *afc); - - /** These are provided separately from set_params in order to facilitate silicon - * tuners which require sophisticated tuning loops, controlling each parameter separately. */ - int (*set_frequency)(struct dvb_frontend *fe, u32 frequency); - int (*set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth); - - /* - * These are provided separately from set_params in order to facilitate silicon - * tuners which require sophisticated tuning loops, controlling each parameter separately. - */ - int (*set_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); - int (*get_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); -}; - -struct analog_demod_info { - char *name; -}; - -struct analog_demod_ops { - - struct analog_demod_info info; - - void (*set_params)(struct dvb_frontend *fe, - struct analog_parameters *params); - int (*has_signal)(struct dvb_frontend *fe, u16 *signal); - int (*get_afc)(struct dvb_frontend *fe, s32 *afc); - void (*tuner_status)(struct dvb_frontend *fe); - void (*standby)(struct dvb_frontend *fe); - void (*release)(struct dvb_frontend *fe); - int (*i2c_gate_ctrl)(struct dvb_frontend *fe, int enable); - - /** This is to allow setting tuner-specific configuration */ - int (*set_config)(struct dvb_frontend *fe, void *priv_cfg); -}; - -struct dtv_frontend_properties; - -struct dvb_frontend_ops { - - struct dvb_frontend_info info; - - u8 delsys[MAX_DELSYS]; - - void (*release)(struct dvb_frontend* fe); - void (*release_sec)(struct dvb_frontend* fe); - - int (*init)(struct dvb_frontend* fe); - int (*sleep)(struct dvb_frontend* fe); - - int (*write)(struct dvb_frontend* fe, const u8 buf[], int len); - - /* if this is set, it overrides the default swzigzag */ - int (*tune)(struct dvb_frontend* fe, - bool re_tune, - unsigned int mode_flags, - unsigned int *delay, - fe_status_t *status); - /* get frontend tuning algorithm from the module */ - enum dvbfe_algo (*get_frontend_algo)(struct dvb_frontend *fe); - - /* these two are only used for the swzigzag code */ - int (*set_frontend)(struct dvb_frontend *fe); - int (*get_tune_settings)(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* settings); - - int (*get_frontend)(struct dvb_frontend *fe); - - int (*read_status)(struct dvb_frontend* fe, fe_status_t* status); - int (*read_ber)(struct dvb_frontend* fe, u32* ber); - int (*read_signal_strength)(struct dvb_frontend* fe, u16* strength); - int (*read_snr)(struct dvb_frontend* fe, u16* snr); - int (*read_ucblocks)(struct dvb_frontend* fe, u32* ucblocks); - - int (*diseqc_reset_overload)(struct dvb_frontend* fe); - int (*diseqc_send_master_cmd)(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd); - int (*diseqc_recv_slave_reply)(struct dvb_frontend* fe, struct dvb_diseqc_slave_reply* reply); - int (*diseqc_send_burst)(struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd); - int (*set_tone)(struct dvb_frontend* fe, fe_sec_tone_mode_t tone); - int (*set_voltage)(struct dvb_frontend* fe, fe_sec_voltage_t voltage); - int (*enable_high_lnb_voltage)(struct dvb_frontend* fe, long arg); - int (*dishnetwork_send_legacy_command)(struct dvb_frontend* fe, unsigned long cmd); - int (*i2c_gate_ctrl)(struct dvb_frontend* fe, int enable); - int (*ts_bus_ctrl)(struct dvb_frontend* fe, int acquire); - int (*set_lna)(struct dvb_frontend *); - - /* These callbacks are for devices that implement their own - * tuning algorithms, rather than a simple swzigzag - */ - enum dvbfe_search (*search)(struct dvb_frontend *fe); - - struct dvb_tuner_ops tuner_ops; - struct analog_demod_ops analog_ops; - - int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); - int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -}; - -#ifdef __DVB_CORE__ -#define MAX_EVENT 8 - -struct dvb_fe_events { - struct dvb_frontend_event events[MAX_EVENT]; - int eventw; - int eventr; - int overflow; - wait_queue_head_t wait_queue; - struct mutex mtx; -}; -#endif - -struct dtv_frontend_properties { - - /* Cache State */ - u32 state; - - u32 frequency; - fe_modulation_t modulation; - - fe_sec_voltage_t voltage; - fe_sec_tone_mode_t sectone; - fe_spectral_inversion_t inversion; - fe_code_rate_t fec_inner; - fe_transmit_mode_t transmission_mode; - u32 bandwidth_hz; /* 0 = AUTO */ - fe_guard_interval_t guard_interval; - fe_hierarchy_t hierarchy; - u32 symbol_rate; - fe_code_rate_t code_rate_HP; - fe_code_rate_t code_rate_LP; - - fe_pilot_t pilot; - fe_rolloff_t rolloff; - - fe_delivery_system_t delivery_system; - - enum fe_interleaving interleaving; - - /* ISDB-T specifics */ - u8 isdbt_partial_reception; - u8 isdbt_sb_mode; - u8 isdbt_sb_subchannel; - u32 isdbt_sb_segment_idx; - u32 isdbt_sb_segment_count; - u8 isdbt_layer_enabled; - struct { - u8 segment_count; - fe_code_rate_t fec; - fe_modulation_t modulation; - u8 interleaving; - } layer[3]; - - /* Multistream specifics */ - u32 stream_id; - - /* ATSC-MH specifics */ - u8 atscmh_fic_ver; - u8 atscmh_parade_id; - u8 atscmh_nog; - u8 atscmh_tnog; - u8 atscmh_sgn; - u8 atscmh_prc; - - u8 atscmh_rs_frame_mode; - u8 atscmh_rs_frame_ensemble; - u8 atscmh_rs_code_mode_pri; - u8 atscmh_rs_code_mode_sec; - u8 atscmh_sccc_block_mode; - u8 atscmh_sccc_code_mode_a; - u8 atscmh_sccc_code_mode_b; - u8 atscmh_sccc_code_mode_c; - u8 atscmh_sccc_code_mode_d; - - u32 lna; - - /* statistics data */ - struct dtv_fe_stats strength; - struct dtv_fe_stats cnr; - struct dtv_fe_stats pre_bit_error; - struct dtv_fe_stats pre_bit_count; - struct dtv_fe_stats post_bit_error; - struct dtv_fe_stats post_bit_count; - struct dtv_fe_stats block_error; - struct dtv_fe_stats block_count; -}; - -struct dvb_frontend { - struct dvb_frontend_ops ops; - struct dvb_adapter *dvb; - void *demodulator_priv; - void *tuner_priv; - void *frontend_priv; - void *sec_priv; - void *analog_demod_priv; - struct dtv_frontend_properties dtv_property_cache; -#define DVB_FRONTEND_COMPONENT_TUNER 0 -#define DVB_FRONTEND_COMPONENT_DEMOD 1 - int (*callback)(void *adapter_priv, int component, int cmd, int arg); - int id; -}; - -extern int dvb_register_frontend(struct dvb_adapter *dvb, - struct dvb_frontend *fe); - -extern int dvb_unregister_frontend(struct dvb_frontend *fe); - -extern void dvb_frontend_detach(struct dvb_frontend *fe); - -extern void dvb_frontend_reinitialise(struct dvb_frontend *fe); -extern int dvb_frontend_suspend(struct dvb_frontend *fe); -extern int dvb_frontend_resume(struct dvb_frontend *fe); - -extern void dvb_frontend_sleep_until(struct timeval *waketime, u32 add_usec); -extern s32 timeval_usec_diff(struct timeval lasttime, struct timeval curtime); - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,145 +0,0 @@ -/* - * dvb-math provides some complex fixed-point math - * operations shared between the dvb related stuff - * - * Copyright (C) 2006 Christoph Pfister (christophpfister@gmail.com) - * - * This library is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include "dvb_math.h" - -static const unsigned short logtable[256] = { - 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7, - 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508, - 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6, - 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37, - 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f, - 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41, - 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1, - 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142, - 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68, - 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355, - 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c, - 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490, - 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3, - 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507, - 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe, - 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca, - 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c, - 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7, - 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c, - 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c, - 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a, - 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065, - 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730, - 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc, - 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469, - 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9, - 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c, - 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765, - 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83, - 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387, - 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973, - 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47 -}; - -unsigned int intlog2(u32 value) -{ - /** - * returns: log2(value) * 2^24 - * wrong result if value = 0 (log2(0) is undefined) - */ - unsigned int msb; - unsigned int logentry; - unsigned int significand; - unsigned int interpolation; - - if (unlikely(value == 0)) { - WARN_ON(1); - return 0; - } - - /* first detect the msb (count begins at 0) */ - msb = fls(value) - 1; - - /** - * now we use a logtable after the following method: - * - * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24 - * where x = msb and therefore 1 <= y < 2 - * first y is determined by shifting the value left - * so that msb is bit 31 - * 0x00231f56 -> 0x8C7D5800 - * the result is y * 2^31 -> "significand" - * then the highest 9 bits are used for a table lookup - * the highest bit is discarded because it's always set - * the highest nine bits in our example are 100011000 - * so we would use the entry 0x18 - */ - significand = value << (31 - msb); - logentry = (significand >> 23) & 0xff; - - /** - * last step we do is interpolation because of the - * limitations of the log table the error is that part of - * the significand which isn't used for lookup then we - * compute the ratio between the error and the next table entry - * and interpolate it between the log table entry used and the - * next one the biggest error possible is 0x7fffff - * (in our example it's 0x7D5800) - * needed value for next table entry is 0x800000 - * so the interpolation is - * (error / 0x800000) * (logtable_next - logtable_current) - * in the implementation the division is moved to the end for - * better accuracy there is also an overflow correction if - * logtable_next is 256 - */ - interpolation = ((significand & 0x7fffff) * - ((logtable[(logentry + 1) & 0xff] - - logtable[logentry]) & 0xffff)) >> 15; - - /* now we return the result */ - return ((msb << 24) + (logtable[logentry] << 8) + interpolation); -} -EXPORT_SYMBOL(intlog2); - -unsigned int intlog10(u32 value) -{ - /** - * returns: log10(value) * 2^24 - * wrong result if value = 0 (log10(0) is undefined) - */ - u64 log; - - if (unlikely(value == 0)) { - WARN_ON(1); - return 0; - } - - log = intlog2(value); - - /** - * we use the following method: - * log10(x) = log2(x) * log10(2) - */ - - return (log * 646456993) >> 31; -} -EXPORT_SYMBOL(intlog10); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_math.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,58 +0,0 @@ -/* - * dvb-math provides some complex fixed-point math - * operations shared between the dvb related stuff - * - * Copyright (C) 2006 Christoph Pfister (christophpfister@gmail.com) - * - * This library is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __DVB_MATH_H -#define __DVB_MATH_H - -#include - -/** - * computes log2 of a value; the result is shifted left by 24 bits - * - * to use rational values you can use the following method: - * intlog2(value) = intlog2(value * 2^x) - x * 2^24 - * - * example: intlog2(8) will give 3 << 24 = 3 * 2^24 - * example: intlog2(9) will give 3 << 24 + ... = 3.16... * 2^24 - * example: intlog2(1.5) = intlog2(3) - 2^24 = 0.584... * 2^24 - * - * @param value The value (must be != 0) - * @return log2(value) * 2^24 - */ -extern unsigned int intlog2(u32 value); - -/** - * computes log10 of a value; the result is shifted left by 24 bits - * - * to use rational values you can use the following method: - * intlog10(value) = intlog10(value * 10^x) - x * 2^24 - * - * example: intlog10(1000) will give 3 << 24 = 3 * 2^24 - * due to the implementation intlog10(1000) might be not exactly 3 * 2^24 - * - * look at intlog2 for similar examples - * - * @param value The value (must be != 0) - * @return log10(value) * 2^24 - */ -extern unsigned int intlog10(u32 value); - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1542 +0,0 @@ -/* - * dvb_net.c - * - * Copyright (C) 2001 Convergence integrated media GmbH - * Ralph Metzler - * Copyright (C) 2002 Ralph Metzler - * - * ULE Decapsulation code: - * Copyright (C) 2003, 2004 gcs - Global Communication & Services GmbH. - * and Department of Scientific Computing - * Paris Lodron University of Salzburg. - * Hilmar Linder - * and Wolfram Stering - * - * ULE Decaps according to RFC 4326. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -/* - * ULE ChangeLog: - * Feb 2004: hl/ws v1: Implementing draft-fair-ipdvb-ule-01.txt - * - * Dec 2004: hl/ws v2: Implementing draft-ietf-ipdvb-ule-03.txt: - * ULE Extension header handling. - * Bugreports by Moritz Vieth and Hanno Tersteegen, - * Fraunhofer Institute for Open Communication Systems - * Competence Center for Advanced Satellite Communications. - * Bugfixes and robustness improvements. - * Filtering on dest MAC addresses, if present (D-Bit = 0) - * ULE_DEBUG compile-time option. - * Apr 2006: cp v3: Bugfixes and compliency with RFC 4326 (ULE) by - * Christian Praehauser , - * Paris Lodron University of Salzburg. - */ - -/* - * FIXME / TODO (dvb_net.c): - * - * Unloading does not work for 2.6.9 kernels: a refcount doesn't go to zero. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_demux.h" -#include "dvb_net.h" - -#ifndef ETH_P_802_3_MIN -#define ETH_P_802_3_MIN 1536 -#endif - -static int dvb_net_debug; -module_param(dvb_net_debug, int, 0444); -MODULE_PARM_DESC(dvb_net_debug, "enable debug messages"); - -#define dprintk(x...) do { if (dvb_net_debug) printk(x); } while (0) - - -static inline __u32 iov_crc32( __u32 c, struct kvec *iov, unsigned int cnt ) -{ - unsigned int j; - for (j = 0; j < cnt; j++) - c = crc32_be( c, iov[j].iov_base, iov[j].iov_len ); - return c; -} - - -#define DVB_NET_MULTICAST_MAX 10 - -#undef ULE_DEBUG - -#ifdef ULE_DEBUG - -#define MAC_ADDR_PRINTFMT "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x" -#define MAX_ADDR_PRINTFMT_ARGS(macap) (macap)[0],(macap)[1],(macap)[2],(macap)[3],(macap)[4],(macap)[5] - -#define isprint(c) ((c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || (c >= '0' && c <= '9')) - -static void hexdump( const unsigned char *buf, unsigned short len ) -{ - char str[80], octet[10]; - int ofs, i, l; - - for (ofs = 0; ofs < len; ofs += 16) { - sprintf( str, "%03d: ", ofs ); - - for (i = 0; i < 16; i++) { - if ((i + ofs) < len) - sprintf( octet, "%02x ", buf[ofs + i] ); - else - strcpy( octet, " " ); - - strcat( str, octet ); - } - strcat( str, " " ); - l = strlen( str ); - - for (i = 0; (i < 16) && ((i + ofs) < len); i++) - str[l++] = isprint( buf[ofs + i] ) ? buf[ofs + i] : '.'; - - str[l] = '\0'; - printk( KERN_WARNING "%s\n", str ); - } -} - -#endif - -struct dvb_net_priv { - int in_use; - u16 pid; - struct net_device *net; - struct dvb_net *host; - struct dmx_demux *demux; - struct dmx_section_feed *secfeed; - struct dmx_section_filter *secfilter; - struct dmx_ts_feed *tsfeed; - int multi_num; - struct dmx_section_filter *multi_secfilter[DVB_NET_MULTICAST_MAX]; - unsigned char multi_macs[DVB_NET_MULTICAST_MAX][6]; - int rx_mode; -#define RX_MODE_UNI 0 -#define RX_MODE_MULTI 1 -#define RX_MODE_ALL_MULTI 2 -#define RX_MODE_PROMISC 3 - struct work_struct set_multicast_list_wq; - struct work_struct restart_net_feed_wq; - unsigned char feedtype; /* Either FEED_TYPE_ or FEED_TYPE_ULE */ - int need_pusi; /* Set to 1, if synchronization on PUSI required. */ - unsigned char tscc; /* TS continuity counter after sync on PUSI. */ - struct sk_buff *ule_skb; /* ULE SNDU decodes into this buffer. */ - unsigned char *ule_next_hdr; /* Pointer into skb to next ULE extension header. */ - unsigned short ule_sndu_len; /* ULE SNDU length in bytes, w/o D-Bit. */ - unsigned short ule_sndu_type; /* ULE SNDU type field, complete. */ - unsigned char ule_sndu_type_1; /* ULE SNDU type field, if split across 2 TS cells. */ - unsigned char ule_dbit; /* Whether the DestMAC address present - * or not (bit is set). */ - unsigned char ule_bridged; /* Whether the ULE_BRIDGED extension header was found. */ - int ule_sndu_remain; /* Nr. of bytes still required for current ULE SNDU. */ - unsigned long ts_count; /* Current ts cell counter. */ - struct mutex mutex; -}; - - -/** - * Determine the packet's protocol ID. The rule here is that we - * assume 802.3 if the type field is short enough to be a length. - * This is normal practice and works for any 'now in use' protocol. - * - * stolen from eth.c out of the linux kernel, hacked for dvb-device - * by Michael Holzt - */ -static __be16 dvb_net_eth_type_trans(struct sk_buff *skb, - struct net_device *dev) -{ - struct ethhdr *eth; - unsigned char *rawp; - - skb_reset_mac_header(skb); - skb_pull(skb,dev->hard_header_len); - eth = eth_hdr(skb); - - if (*eth->h_dest & 1) { - if(memcmp(eth->h_dest,dev->broadcast, ETH_ALEN)==0) - skb->pkt_type=PACKET_BROADCAST; - else - skb->pkt_type=PACKET_MULTICAST; - } - - if (ntohs(eth->h_proto) >= ETH_P_802_3_MIN) - return eth->h_proto; - - rawp = skb->data; - - /** - * This is a magic hack to spot IPX packets. Older Novell breaks - * the protocol design and runs IPX over 802.3 without an 802.2 LLC - * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This - * won't work for fault tolerant netware but does for the rest. - */ - if (*(unsigned short *)rawp == 0xFFFF) - return htons(ETH_P_802_3); - - /** - * Real 802.2 LLC - */ - return htons(ETH_P_802_2); -} - -#define TS_SZ 188 -#define TS_SYNC 0x47 -#define TS_TEI 0x80 -#define TS_SC 0xC0 -#define TS_PUSI 0x40 -#define TS_AF_A 0x20 -#define TS_AF_D 0x10 - -/* ULE Extension Header handlers. */ - -#define ULE_TEST 0 -#define ULE_BRIDGED 1 - -#define ULE_OPTEXTHDR_PADDING 0 - -static int ule_test_sndu( struct dvb_net_priv *p ) -{ - return -1; -} - -static int ule_bridged_sndu( struct dvb_net_priv *p ) -{ - struct ethhdr *hdr = (struct ethhdr*) p->ule_next_hdr; - if(ntohs(hdr->h_proto) < ETH_P_802_3_MIN) { - int framelen = p->ule_sndu_len - ((p->ule_next_hdr+sizeof(struct ethhdr)) - p->ule_skb->data); - /* A frame Type < ETH_P_802_3_MIN for a bridged frame, introduces a LLC Length field. */ - if(framelen != ntohs(hdr->h_proto)) { - return -1; - } - } - /* Note: - * From RFC4326: - * "A bridged SNDU is a Mandatory Extension Header of Type 1. - * It must be the final (or only) extension header specified in the header chain of a SNDU." - * The 'ule_bridged' flag will cause the extension header processing loop to terminate. - */ - p->ule_bridged = 1; - return 0; -} - -static int ule_exthdr_padding(struct dvb_net_priv *p) -{ - return 0; -} - -/** Handle ULE extension headers. - * Function is called after a successful CRC32 verification of an ULE SNDU to complete its decoding. - * Returns: >= 0: nr. of bytes consumed by next extension header - * -1: Mandatory extension header that is not recognized or TEST SNDU; discard. - */ -static int handle_one_ule_extension( struct dvb_net_priv *p ) -{ - /* Table of mandatory extension header handlers. The header type is the index. */ - static int (*ule_mandatory_ext_handlers[255])( struct dvb_net_priv *p ) = - { [0] = ule_test_sndu, [1] = ule_bridged_sndu, [2] = NULL, }; - - /* Table of optional extension header handlers. The header type is the index. */ - static int (*ule_optional_ext_handlers[255])( struct dvb_net_priv *p ) = - { [0] = ule_exthdr_padding, [1] = NULL, }; - - int ext_len = 0; - unsigned char hlen = (p->ule_sndu_type & 0x0700) >> 8; - unsigned char htype = p->ule_sndu_type & 0x00FF; - - /* Discriminate mandatory and optional extension headers. */ - if (hlen == 0) { - /* Mandatory extension header */ - if (ule_mandatory_ext_handlers[htype]) { - ext_len = ule_mandatory_ext_handlers[htype]( p ); - if(ext_len >= 0) { - p->ule_next_hdr += ext_len; - if (!p->ule_bridged) { - p->ule_sndu_type = ntohs(*(__be16 *)p->ule_next_hdr); - p->ule_next_hdr += 2; - } else { - p->ule_sndu_type = ntohs(*(__be16 *)(p->ule_next_hdr + ((p->ule_dbit ? 2 : 3) * ETH_ALEN))); - /* This assures the extension handling loop will terminate. */ - } - } - // else: extension handler failed or SNDU should be discarded - } else - ext_len = -1; /* SNDU has to be discarded. */ - } else { - /* Optional extension header. Calculate the length. */ - ext_len = hlen << 1; - /* Process the optional extension header according to its type. */ - if (ule_optional_ext_handlers[htype]) - (void)ule_optional_ext_handlers[htype]( p ); - p->ule_next_hdr += ext_len; - p->ule_sndu_type = ntohs( *(__be16 *)(p->ule_next_hdr-2) ); - /* - * note: the length of the next header type is included in the - * length of THIS optional extension header - */ - } - - return ext_len; -} - -static int handle_ule_extensions( struct dvb_net_priv *p ) -{ - int total_ext_len = 0, l; - - p->ule_next_hdr = p->ule_skb->data; - do { - l = handle_one_ule_extension( p ); - if (l < 0) - return l; /* Stop extension header processing and discard SNDU. */ - total_ext_len += l; -#ifdef ULE_DEBUG - dprintk("handle_ule_extensions: ule_next_hdr=%p, ule_sndu_type=%i, " - "l=%i, total_ext_len=%i\n", p->ule_next_hdr, - (int) p->ule_sndu_type, l, total_ext_len); -#endif - - } while (p->ule_sndu_type < ETH_P_802_3_MIN); - - return total_ext_len; -} - - -/** Prepare for a new ULE SNDU: reset the decoder state. */ -static inline void reset_ule( struct dvb_net_priv *p ) -{ - p->ule_skb = NULL; - p->ule_next_hdr = NULL; - p->ule_sndu_len = 0; - p->ule_sndu_type = 0; - p->ule_sndu_type_1 = 0; - p->ule_sndu_remain = 0; - p->ule_dbit = 0xFF; - p->ule_bridged = 0; -} - -/** - * Decode ULE SNDUs according to draft-ietf-ipdvb-ule-03.txt from a sequence of - * TS cells of a single PID. - */ -static void dvb_net_ule( struct net_device *dev, const u8 *buf, size_t buf_len ) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - unsigned long skipped = 0L; - const u8 *ts, *ts_end, *from_where = NULL; - u8 ts_remain = 0, how_much = 0, new_ts = 1; - struct ethhdr *ethh = NULL; - bool error = false; - -#ifdef ULE_DEBUG - /* The code inside ULE_DEBUG keeps a history of the last 100 TS cells processed. */ - static unsigned char ule_hist[100*TS_SZ]; - static unsigned char *ule_where = ule_hist, ule_dump; -#endif - - /* For all TS cells in current buffer. - * Appearently, we are called for every single TS cell. - */ - for (ts = buf, ts_end = buf + buf_len; ts < ts_end; /* no default incr. */ ) { - - if (new_ts) { - /* We are about to process a new TS cell. */ - -#ifdef ULE_DEBUG - if (ule_where >= &ule_hist[100*TS_SZ]) ule_where = ule_hist; - memcpy( ule_where, ts, TS_SZ ); - if (ule_dump) { - hexdump( ule_where, TS_SZ ); - ule_dump = 0; - } - ule_where += TS_SZ; -#endif - - /* Check TS error conditions: sync_byte, transport_error_indicator, scrambling_control . */ - if ((ts[0] != TS_SYNC) || (ts[1] & TS_TEI) || ((ts[3] & TS_SC) != 0)) { - printk(KERN_WARNING "%lu: Invalid TS cell: SYNC %#x, TEI %u, SC %#x.\n", - priv->ts_count, ts[0], ts[1] & TS_TEI >> 7, ts[3] & 0xC0 >> 6); - - /* Drop partly decoded SNDU, reset state, resync on PUSI. */ - if (priv->ule_skb) { - dev_kfree_skb( priv->ule_skb ); - /* Prepare for next SNDU. */ - dev->stats.rx_errors++; - dev->stats.rx_frame_errors++; - } - reset_ule(priv); - priv->need_pusi = 1; - - /* Continue with next TS cell. */ - ts += TS_SZ; - priv->ts_count++; - continue; - } - - ts_remain = 184; - from_where = ts + 4; - } - /* Synchronize on PUSI, if required. */ - if (priv->need_pusi) { - if (ts[1] & TS_PUSI) { - /* Find beginning of first ULE SNDU in current TS cell. */ - /* Synchronize continuity counter. */ - priv->tscc = ts[3] & 0x0F; - /* There is a pointer field here. */ - if (ts[4] > ts_remain) { - printk(KERN_ERR "%lu: Invalid ULE packet " - "(pointer field %d)\n", priv->ts_count, ts[4]); - ts += TS_SZ; - priv->ts_count++; - continue; - } - /* Skip to destination of pointer field. */ - from_where = &ts[5] + ts[4]; - ts_remain -= 1 + ts[4]; - skipped = 0; - } else { - skipped++; - ts += TS_SZ; - priv->ts_count++; - continue; - } - } - - if (new_ts) { - /* Check continuity counter. */ - if ((ts[3] & 0x0F) == priv->tscc) - priv->tscc = (priv->tscc + 1) & 0x0F; - else { - /* TS discontinuity handling: */ - printk(KERN_WARNING "%lu: TS discontinuity: got %#x, " - "expected %#x.\n", priv->ts_count, ts[3] & 0x0F, priv->tscc); - /* Drop partly decoded SNDU, reset state, resync on PUSI. */ - if (priv->ule_skb) { - dev_kfree_skb( priv->ule_skb ); - /* Prepare for next SNDU. */ - // reset_ule(priv); moved to below. - dev->stats.rx_errors++; - dev->stats.rx_frame_errors++; - } - reset_ule(priv); - /* skip to next PUSI. */ - priv->need_pusi = 1; - continue; - } - /* If we still have an incomplete payload, but PUSI is - * set; some TS cells are missing. - * This is only possible here, if we missed exactly 16 TS - * cells (continuity counter wrap). */ - if (ts[1] & TS_PUSI) { - if (! priv->need_pusi) { - if (!(*from_where < (ts_remain-1)) || *from_where != priv->ule_sndu_remain) { - /* Pointer field is invalid. Drop this TS cell and any started ULE SNDU. */ - printk(KERN_WARNING "%lu: Invalid pointer " - "field: %u.\n", priv->ts_count, *from_where); - - /* Drop partly decoded SNDU, reset state, resync on PUSI. */ - if (priv->ule_skb) { - error = true; - dev_kfree_skb(priv->ule_skb); - } - - if (error || priv->ule_sndu_remain) { - dev->stats.rx_errors++; - dev->stats.rx_frame_errors++; - error = false; - } - - reset_ule(priv); - priv->need_pusi = 1; - continue; - } - /* Skip pointer field (we're processing a - * packed payload). */ - from_where += 1; - ts_remain -= 1; - } else - priv->need_pusi = 0; - - if (priv->ule_sndu_remain > 183) { - /* Current SNDU lacks more data than there could be available in the - * current TS cell. */ - dev->stats.rx_errors++; - dev->stats.rx_length_errors++; - printk(KERN_WARNING "%lu: Expected %d more SNDU bytes, but " - "got PUSI (pf %d, ts_remain %d). Flushing incomplete payload.\n", - priv->ts_count, priv->ule_sndu_remain, ts[4], ts_remain); - dev_kfree_skb(priv->ule_skb); - /* Prepare for next SNDU. */ - reset_ule(priv); - /* Resync: go to where pointer field points to: start of next ULE SNDU. */ - from_where += ts[4]; - ts_remain -= ts[4]; - } - } - } - - /* Check if new payload needs to be started. */ - if (priv->ule_skb == NULL) { - /* Start a new payload with skb. - * Find ULE header. It is only guaranteed that the - * length field (2 bytes) is contained in the current - * TS. - * Check ts_remain has to be >= 2 here. */ - if (ts_remain < 2) { - printk(KERN_WARNING "Invalid payload packing: only %d " - "bytes left in TS. Resyncing.\n", ts_remain); - priv->ule_sndu_len = 0; - priv->need_pusi = 1; - ts += TS_SZ; - continue; - } - - if (! priv->ule_sndu_len) { - /* Got at least two bytes, thus extrace the SNDU length. */ - priv->ule_sndu_len = from_where[0] << 8 | from_where[1]; - if (priv->ule_sndu_len & 0x8000) { - /* D-Bit is set: no dest mac present. */ - priv->ule_sndu_len &= 0x7FFF; - priv->ule_dbit = 1; - } else - priv->ule_dbit = 0; - - if (priv->ule_sndu_len < 5) { - printk(KERN_WARNING "%lu: Invalid ULE SNDU length %u. " - "Resyncing.\n", priv->ts_count, priv->ule_sndu_len); - dev->stats.rx_errors++; - dev->stats.rx_length_errors++; - priv->ule_sndu_len = 0; - priv->need_pusi = 1; - new_ts = 1; - ts += TS_SZ; - priv->ts_count++; - continue; - } - ts_remain -= 2; /* consume the 2 bytes SNDU length. */ - from_where += 2; - } - - priv->ule_sndu_remain = priv->ule_sndu_len + 2; - /* - * State of current TS: - * ts_remain (remaining bytes in the current TS cell) - * 0 ule_type is not available now, we need the next TS cell - * 1 the first byte of the ule_type is present - * >=2 full ULE header present, maybe some payload data as well. - */ - switch (ts_remain) { - case 1: - priv->ule_sndu_remain--; - priv->ule_sndu_type = from_where[0] << 8; - priv->ule_sndu_type_1 = 1; /* first byte of ule_type is set. */ - ts_remain -= 1; from_where += 1; - /* Continue w/ next TS. */ - case 0: - new_ts = 1; - ts += TS_SZ; - priv->ts_count++; - continue; - - default: /* complete ULE header is present in current TS. */ - /* Extract ULE type field. */ - if (priv->ule_sndu_type_1) { - priv->ule_sndu_type_1 = 0; - priv->ule_sndu_type |= from_where[0]; - from_where += 1; /* points to payload start. */ - ts_remain -= 1; - } else { - /* Complete type is present in new TS. */ - priv->ule_sndu_type = from_where[0] << 8 | from_where[1]; - from_where += 2; /* points to payload start. */ - ts_remain -= 2; - } - break; - } - - /* Allocate the skb (decoder target buffer) with the correct size, as follows: - * prepare for the largest case: bridged SNDU with MAC address (dbit = 0). */ - priv->ule_skb = dev_alloc_skb( priv->ule_sndu_len + ETH_HLEN + ETH_ALEN ); - if (priv->ule_skb == NULL) { - printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", - dev->name); - dev->stats.rx_dropped++; - return; - } - - /* This includes the CRC32 _and_ dest mac, if !dbit. */ - priv->ule_sndu_remain = priv->ule_sndu_len; - priv->ule_skb->dev = dev; - /* Leave space for Ethernet or bridged SNDU header (eth hdr plus one MAC addr). */ - skb_reserve( priv->ule_skb, ETH_HLEN + ETH_ALEN ); - } - - /* Copy data into our current skb. */ - how_much = min(priv->ule_sndu_remain, (int)ts_remain); - memcpy(skb_put(priv->ule_skb, how_much), from_where, how_much); - priv->ule_sndu_remain -= how_much; - ts_remain -= how_much; - from_where += how_much; - - /* Check for complete payload. */ - if (priv->ule_sndu_remain <= 0) { - /* Check CRC32, we've got it in our skb already. */ - __be16 ulen = htons(priv->ule_sndu_len); - __be16 utype = htons(priv->ule_sndu_type); - const u8 *tail; - struct kvec iov[3] = { - { &ulen, sizeof ulen }, - { &utype, sizeof utype }, - { priv->ule_skb->data, priv->ule_skb->len - 4 } - }; - u32 ule_crc = ~0L, expected_crc; - if (priv->ule_dbit) { - /* Set D-bit for CRC32 verification, - * if it was set originally. */ - ulen |= htons(0x8000); - } - - ule_crc = iov_crc32(ule_crc, iov, 3); - tail = skb_tail_pointer(priv->ule_skb); - expected_crc = *(tail - 4) << 24 | - *(tail - 3) << 16 | - *(tail - 2) << 8 | - *(tail - 1); - if (ule_crc != expected_crc) { - printk(KERN_WARNING "%lu: CRC32 check FAILED: %08x / %08x, SNDU len %d type %#x, ts_remain %d, next 2: %x.\n", - priv->ts_count, ule_crc, expected_crc, priv->ule_sndu_len, priv->ule_sndu_type, ts_remain, ts_remain > 2 ? *(unsigned short *)from_where : 0); - -#ifdef ULE_DEBUG - hexdump( iov[0].iov_base, iov[0].iov_len ); - hexdump( iov[1].iov_base, iov[1].iov_len ); - hexdump( iov[2].iov_base, iov[2].iov_len ); - - if (ule_where == ule_hist) { - hexdump( &ule_hist[98*TS_SZ], TS_SZ ); - hexdump( &ule_hist[99*TS_SZ], TS_SZ ); - } else if (ule_where == &ule_hist[TS_SZ]) { - hexdump( &ule_hist[99*TS_SZ], TS_SZ ); - hexdump( ule_hist, TS_SZ ); - } else { - hexdump( ule_where - TS_SZ - TS_SZ, TS_SZ ); - hexdump( ule_where - TS_SZ, TS_SZ ); - } - ule_dump = 1; -#endif - - dev->stats.rx_errors++; - dev->stats.rx_crc_errors++; - dev_kfree_skb(priv->ule_skb); - } else { - /* CRC32 verified OK. */ - u8 dest_addr[ETH_ALEN]; - static const u8 bc_addr[ETH_ALEN] = - { [ 0 ... ETH_ALEN-1] = 0xff }; - - /* CRC32 was OK. Remove it from skb. */ - priv->ule_skb->tail -= 4; - priv->ule_skb->len -= 4; - - if (!priv->ule_dbit) { - /* - * The destination MAC address is the - * next data in the skb. It comes - * before any extension headers. - * - * Check if the payload of this SNDU - * should be passed up the stack. - */ - register int drop = 0; - if (priv->rx_mode != RX_MODE_PROMISC) { - if (priv->ule_skb->data[0] & 0x01) { - /* multicast or broadcast */ - if (memcmp(priv->ule_skb->data, bc_addr, ETH_ALEN)) { - /* multicast */ - if (priv->rx_mode == RX_MODE_MULTI) { - int i; - for(i = 0; i < priv->multi_num && memcmp(priv->ule_skb->data, priv->multi_macs[i], ETH_ALEN); i++) - ; - if (i == priv->multi_num) - drop = 1; - } else if (priv->rx_mode != RX_MODE_ALL_MULTI) - drop = 1; /* no broadcast; */ - /* else: all multicast mode: accept all multicast packets */ - } - /* else: broadcast */ - } - else if (memcmp(priv->ule_skb->data, dev->dev_addr, ETH_ALEN)) - drop = 1; - /* else: destination address matches the MAC address of our receiver device */ - } - /* else: promiscuous mode; pass everything up the stack */ - - if (drop) { -#ifdef ULE_DEBUG - dprintk("Dropping SNDU: MAC destination address does not match: dest addr: "MAC_ADDR_PRINTFMT", dev addr: "MAC_ADDR_PRINTFMT"\n", - MAX_ADDR_PRINTFMT_ARGS(priv->ule_skb->data), MAX_ADDR_PRINTFMT_ARGS(dev->dev_addr)); -#endif - dev_kfree_skb(priv->ule_skb); - goto sndu_done; - } - else - { - skb_copy_from_linear_data(priv->ule_skb, - dest_addr, - ETH_ALEN); - skb_pull(priv->ule_skb, ETH_ALEN); - } - } - - /* Handle ULE Extension Headers. */ - if (priv->ule_sndu_type < ETH_P_802_3_MIN) { - /* There is an extension header. Handle it accordingly. */ - int l = handle_ule_extensions(priv); - if (l < 0) { - /* Mandatory extension header unknown or TEST SNDU. Drop it. */ - // printk( KERN_WARNING "Dropping SNDU, extension headers.\n" ); - dev_kfree_skb(priv->ule_skb); - goto sndu_done; - } - skb_pull(priv->ule_skb, l); - } - - /* - * Construct/assure correct ethernet header. - * Note: in bridged mode (priv->ule_bridged != - * 0) we already have the (original) ethernet - * header at the start of the payload (after - * optional dest. address and any extension - * headers). - */ - - if (!priv->ule_bridged) { - skb_push(priv->ule_skb, ETH_HLEN); - ethh = (struct ethhdr *)priv->ule_skb->data; - if (!priv->ule_dbit) { - /* dest_addr buffer is only valid if priv->ule_dbit == 0 */ - memcpy(ethh->h_dest, dest_addr, ETH_ALEN); - memset(ethh->h_source, 0, ETH_ALEN); - } - else /* zeroize source and dest */ - memset( ethh, 0, ETH_ALEN*2 ); - - ethh->h_proto = htons(priv->ule_sndu_type); - } - /* else: skb is in correct state; nothing to do. */ - priv->ule_bridged = 0; - - /* Stuff into kernel's protocol stack. */ - priv->ule_skb->protocol = dvb_net_eth_type_trans(priv->ule_skb, dev); - /* If D-bit is set (i.e. destination MAC address not present), - * receive the packet anyhow. */ - /* if (priv->ule_dbit && skb->pkt_type == PACKET_OTHERHOST) - priv->ule_skb->pkt_type = PACKET_HOST; */ - dev->stats.rx_packets++; - dev->stats.rx_bytes += priv->ule_skb->len; - netif_rx(priv->ule_skb); - } - sndu_done: - /* Prepare for next SNDU. */ - reset_ule(priv); - } - - /* More data in current TS (look at the bytes following the CRC32)? */ - if (ts_remain >= 2 && *((unsigned short *)from_where) != 0xFFFF) { - /* Next ULE SNDU starts right there. */ - new_ts = 0; - priv->ule_skb = NULL; - priv->ule_sndu_type_1 = 0; - priv->ule_sndu_len = 0; - // printk(KERN_WARNING "More data in current TS: [%#x %#x %#x %#x]\n", - // *(from_where + 0), *(from_where + 1), - // *(from_where + 2), *(from_where + 3)); - // printk(KERN_WARNING "ts @ %p, stopped @ %p:\n", ts, from_where + 0); - // hexdump(ts, 188); - } else { - new_ts = 1; - ts += TS_SZ; - priv->ts_count++; - if (priv->ule_skb == NULL) { - priv->need_pusi = 1; - priv->ule_sndu_type_1 = 0; - priv->ule_sndu_len = 0; - } - } - } /* for all available TS cells */ -} - -static int dvb_net_ts_callback(const u8 *buffer1, size_t buffer1_len, - const u8 *buffer2, size_t buffer2_len, - struct dmx_ts_feed *feed, enum dmx_success success) -{ - struct net_device *dev = feed->priv; - - if (buffer2) - printk(KERN_WARNING "buffer2 not NULL: %p.\n", buffer2); - if (buffer1_len > 32768) - printk(KERN_WARNING "length > 32k: %zu.\n", buffer1_len); - /* printk("TS callback: %u bytes, %u TS cells @ %p.\n", - buffer1_len, buffer1_len / TS_SZ, buffer1); */ - dvb_net_ule(dev, buffer1, buffer1_len); - return 0; -} - - -static void dvb_net_sec(struct net_device *dev, - const u8 *pkt, int pkt_len) -{ - u8 *eth; - struct sk_buff *skb; - struct net_device_stats *stats = &dev->stats; - int snap = 0; - - /* note: pkt_len includes a 32bit checksum */ - if (pkt_len < 16) { - printk("%s: IP/MPE packet length = %d too small.\n", - dev->name, pkt_len); - stats->rx_errors++; - stats->rx_length_errors++; - return; - } -/* it seems some ISPs manage to screw up here, so we have to - * relax the error checks... */ -#if 0 - if ((pkt[5] & 0xfd) != 0xc1) { - /* drop scrambled or broken packets */ -#else - if ((pkt[5] & 0x3c) != 0x00) { - /* drop scrambled */ -#endif - stats->rx_errors++; - stats->rx_crc_errors++; - return; - } - if (pkt[5] & 0x02) { - /* handle LLC/SNAP, see rfc-1042 */ - if (pkt_len < 24 || memcmp(&pkt[12], "\xaa\xaa\x03\0\0\0", 6)) { - stats->rx_dropped++; - return; - } - snap = 8; - } - if (pkt[7]) { - /* FIXME: assemble datagram from multiple sections */ - stats->rx_errors++; - stats->rx_frame_errors++; - return; - } - - /* we have 14 byte ethernet header (ip header follows); - * 12 byte MPE header; 4 byte checksum; + 2 byte alignment, 8 byte LLC/SNAP - */ - if (!(skb = dev_alloc_skb(pkt_len - 4 - 12 + 14 + 2 - snap))) { - //printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); - stats->rx_dropped++; - return; - } - skb_reserve(skb, 2); /* longword align L3 header */ - skb->dev = dev; - - /* copy L3 payload */ - eth = (u8 *) skb_put(skb, pkt_len - 12 - 4 + 14 - snap); - memcpy(eth + 14, pkt + 12 + snap, pkt_len - 12 - 4 - snap); - - /* create ethernet header: */ - eth[0]=pkt[0x0b]; - eth[1]=pkt[0x0a]; - eth[2]=pkt[0x09]; - eth[3]=pkt[0x08]; - eth[4]=pkt[0x04]; - eth[5]=pkt[0x03]; - - eth[6]=eth[7]=eth[8]=eth[9]=eth[10]=eth[11]=0; - - if (snap) { - eth[12] = pkt[18]; - eth[13] = pkt[19]; - } else { - /* protocol numbers are from rfc-1700 or - * http://www.iana.org/assignments/ethernet-numbers - */ - if (pkt[12] >> 4 == 6) { /* version field from IP header */ - eth[12] = 0x86; /* IPv6 */ - eth[13] = 0xdd; - } else { - eth[12] = 0x08; /* IPv4 */ - eth[13] = 0x00; - } - } - - skb->protocol = dvb_net_eth_type_trans(skb, dev); - - stats->rx_packets++; - stats->rx_bytes+=skb->len; - netif_rx(skb); -} - -static int dvb_net_sec_callback(const u8 *buffer1, size_t buffer1_len, - const u8 *buffer2, size_t buffer2_len, - struct dmx_section_filter *filter, - enum dmx_success success) -{ - struct net_device *dev = filter->priv; - - /** - * we rely on the DVB API definition where exactly one complete - * section is delivered in buffer1 - */ - dvb_net_sec (dev, buffer1, buffer1_len); - return 0; -} - -static int dvb_net_tx(struct sk_buff *skb, struct net_device *dev) -{ - dev_kfree_skb(skb); - return NETDEV_TX_OK; -} - -static u8 mask_normal[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; -static u8 mask_allmulti[6]={0xff, 0xff, 0xff, 0x00, 0x00, 0x00}; -static u8 mac_allmulti[6]={0x01, 0x00, 0x5e, 0x00, 0x00, 0x00}; -static u8 mask_promisc[6]={0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - -static int dvb_net_filter_sec_set(struct net_device *dev, - struct dmx_section_filter **secfilter, - u8 *mac, u8 *mac_mask) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - int ret; - - *secfilter=NULL; - ret = priv->secfeed->allocate_filter(priv->secfeed, secfilter); - if (ret<0) { - printk("%s: could not get filter\n", dev->name); - return ret; - } - - (*secfilter)->priv=(void *) dev; - - memset((*secfilter)->filter_value, 0x00, DMX_MAX_FILTER_SIZE); - memset((*secfilter)->filter_mask, 0x00, DMX_MAX_FILTER_SIZE); - memset((*secfilter)->filter_mode, 0xff, DMX_MAX_FILTER_SIZE); - - (*secfilter)->filter_value[0]=0x3e; - (*secfilter)->filter_value[3]=mac[5]; - (*secfilter)->filter_value[4]=mac[4]; - (*secfilter)->filter_value[8]=mac[3]; - (*secfilter)->filter_value[9]=mac[2]; - (*secfilter)->filter_value[10]=mac[1]; - (*secfilter)->filter_value[11]=mac[0]; - - (*secfilter)->filter_mask[0] = 0xff; - (*secfilter)->filter_mask[3] = mac_mask[5]; - (*secfilter)->filter_mask[4] = mac_mask[4]; - (*secfilter)->filter_mask[8] = mac_mask[3]; - (*secfilter)->filter_mask[9] = mac_mask[2]; - (*secfilter)->filter_mask[10] = mac_mask[1]; - (*secfilter)->filter_mask[11]=mac_mask[0]; - - dprintk("%s: filter mac=%pM\n", dev->name, mac); - dprintk("%s: filter mask=%pM\n", dev->name, mac_mask); - - return 0; -} - -static int dvb_net_feed_start(struct net_device *dev) -{ - int ret = 0, i; - struct dvb_net_priv *priv = netdev_priv(dev); - struct dmx_demux *demux = priv->demux; - unsigned char *mac = (unsigned char *) dev->dev_addr; - - dprintk("%s: rx_mode %i\n", __func__, priv->rx_mode); - mutex_lock(&priv->mutex); - if (priv->tsfeed || priv->secfeed || priv->secfilter || priv->multi_secfilter[0]) - printk("%s: BUG %d\n", __func__, __LINE__); - - priv->secfeed=NULL; - priv->secfilter=NULL; - priv->tsfeed = NULL; - - if (priv->feedtype == DVB_NET_FEEDTYPE_MPE) { - dprintk("%s: alloc secfeed\n", __func__); - ret=demux->allocate_section_feed(demux, &priv->secfeed, - dvb_net_sec_callback); - if (ret<0) { - printk("%s: could not allocate section feed\n", dev->name); - goto error; - } - - ret = priv->secfeed->set(priv->secfeed, priv->pid, 32768, 1); - - if (ret<0) { - printk("%s: could not set section feed\n", dev->name); - priv->demux->release_section_feed(priv->demux, priv->secfeed); - priv->secfeed=NULL; - goto error; - } - - if (priv->rx_mode != RX_MODE_PROMISC) { - dprintk("%s: set secfilter\n", __func__); - dvb_net_filter_sec_set(dev, &priv->secfilter, mac, mask_normal); - } - - switch (priv->rx_mode) { - case RX_MODE_MULTI: - for (i = 0; i < priv->multi_num; i++) { - dprintk("%s: set multi_secfilter[%d]\n", __func__, i); - dvb_net_filter_sec_set(dev, &priv->multi_secfilter[i], - priv->multi_macs[i], mask_normal); - } - break; - case RX_MODE_ALL_MULTI: - priv->multi_num=1; - dprintk("%s: set multi_secfilter[0]\n", __func__); - dvb_net_filter_sec_set(dev, &priv->multi_secfilter[0], - mac_allmulti, mask_allmulti); - break; - case RX_MODE_PROMISC: - priv->multi_num=0; - dprintk("%s: set secfilter\n", __func__); - dvb_net_filter_sec_set(dev, &priv->secfilter, mac, mask_promisc); - break; - } - - dprintk("%s: start filtering\n", __func__); - priv->secfeed->start_filtering(priv->secfeed); - } else if (priv->feedtype == DVB_NET_FEEDTYPE_ULE) { - struct timespec timeout = { 0, 10000000 }; // 10 msec - - /* we have payloads encapsulated in TS */ - dprintk("%s: alloc tsfeed\n", __func__); - ret = demux->allocate_ts_feed(demux, &priv->tsfeed, dvb_net_ts_callback); - if (ret < 0) { - printk("%s: could not allocate ts feed\n", dev->name); - goto error; - } - - /* Set netdevice pointer for ts decaps callback. */ - priv->tsfeed->priv = (void *)dev; - ret = priv->tsfeed->set(priv->tsfeed, - priv->pid, /* pid */ - TS_PACKET, /* type */ - DMX_PES_OTHER, /* pes type */ - 32768, /* circular buffer size */ - timeout /* timeout */ - ); - - if (ret < 0) { - printk("%s: could not set ts feed\n", dev->name); - priv->demux->release_ts_feed(priv->demux, priv->tsfeed); - priv->tsfeed = NULL; - goto error; - } - - dprintk("%s: start filtering\n", __func__); - priv->tsfeed->start_filtering(priv->tsfeed); - } else - ret = -EINVAL; - -error: - mutex_unlock(&priv->mutex); - return ret; -} - -static int dvb_net_feed_stop(struct net_device *dev) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - int i, ret = 0; - - dprintk("%s\n", __func__); - mutex_lock(&priv->mutex); - if (priv->feedtype == DVB_NET_FEEDTYPE_MPE) { - if (priv->secfeed) { - if (priv->secfeed->is_filtering) { - dprintk("%s: stop secfeed\n", __func__); - priv->secfeed->stop_filtering(priv->secfeed); - } - - if (priv->secfilter) { - dprintk("%s: release secfilter\n", __func__); - priv->secfeed->release_filter(priv->secfeed, - priv->secfilter); - priv->secfilter=NULL; - } - - for (i=0; imulti_num; i++) { - if (priv->multi_secfilter[i]) { - dprintk("%s: release multi_filter[%d]\n", - __func__, i); - priv->secfeed->release_filter(priv->secfeed, - priv->multi_secfilter[i]); - priv->multi_secfilter[i] = NULL; - } - } - - priv->demux->release_section_feed(priv->demux, priv->secfeed); - priv->secfeed = NULL; - } else - printk("%s: no feed to stop\n", dev->name); - } else if (priv->feedtype == DVB_NET_FEEDTYPE_ULE) { - if (priv->tsfeed) { - if (priv->tsfeed->is_filtering) { - dprintk("%s: stop tsfeed\n", __func__); - priv->tsfeed->stop_filtering(priv->tsfeed); - } - priv->demux->release_ts_feed(priv->demux, priv->tsfeed); - priv->tsfeed = NULL; - } - else - printk("%s: no ts feed to stop\n", dev->name); - } else - ret = -EINVAL; - mutex_unlock(&priv->mutex); - return ret; -} - - -static int dvb_set_mc_filter(struct net_device *dev, unsigned char *addr) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - - if (priv->multi_num == DVB_NET_MULTICAST_MAX) - return -ENOMEM; - - memcpy(priv->multi_macs[priv->multi_num], addr, ETH_ALEN); - - priv->multi_num++; - return 0; -} - - -static void wq_set_multicast_list (struct work_struct *work) -{ - struct dvb_net_priv *priv = - container_of(work, struct dvb_net_priv, set_multicast_list_wq); - struct net_device *dev = priv->net; - - dvb_net_feed_stop(dev); - priv->rx_mode = RX_MODE_UNI; - netif_addr_lock_bh(dev); - - if (dev->flags & IFF_PROMISC) { - dprintk("%s: promiscuous mode\n", dev->name); - priv->rx_mode = RX_MODE_PROMISC; - } else if ((dev->flags & IFF_ALLMULTI)) { - dprintk("%s: allmulti mode\n", dev->name); - priv->rx_mode = RX_MODE_ALL_MULTI; - } else if (!netdev_mc_empty(dev)) { - struct netdev_hw_addr *ha; - - dprintk("%s: set_mc_list, %d entries\n", - dev->name, netdev_mc_count(dev)); - - priv->rx_mode = RX_MODE_MULTI; - priv->multi_num = 0; - - netdev_for_each_mc_addr(ha, dev) - dvb_set_mc_filter(dev, ha->addr); - } - - netif_addr_unlock_bh(dev); - dvb_net_feed_start(dev); -} - - -static void dvb_net_set_multicast_list (struct net_device *dev) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - schedule_work(&priv->set_multicast_list_wq); -} - - -static void wq_restart_net_feed (struct work_struct *work) -{ - struct dvb_net_priv *priv = - container_of(work, struct dvb_net_priv, restart_net_feed_wq); - struct net_device *dev = priv->net; - - if (netif_running(dev)) { - dvb_net_feed_stop(dev); - dvb_net_feed_start(dev); - } -} - - -static int dvb_net_set_mac (struct net_device *dev, void *p) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - struct sockaddr *addr=p; - - memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); - - if (netif_running(dev)) - schedule_work(&priv->restart_net_feed_wq); - - return 0; -} - - -static int dvb_net_open(struct net_device *dev) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - - priv->in_use++; - dvb_net_feed_start(dev); - return 0; -} - - -static int dvb_net_stop(struct net_device *dev) -{ - struct dvb_net_priv *priv = netdev_priv(dev); - - priv->in_use--; - return dvb_net_feed_stop(dev); -} - -static const struct header_ops dvb_header_ops = { - .create = eth_header, - .parse = eth_header_parse, - .rebuild = eth_rebuild_header, -}; - - -static const struct net_device_ops dvb_netdev_ops = { - .ndo_open = dvb_net_open, - .ndo_stop = dvb_net_stop, - .ndo_start_xmit = dvb_net_tx, - .ndo_set_rx_mode = dvb_net_set_multicast_list, - .ndo_set_mac_address = dvb_net_set_mac, - .ndo_change_mtu = eth_change_mtu, - .ndo_validate_addr = eth_validate_addr, -}; - -static void dvb_net_setup(struct net_device *dev) -{ - ether_setup(dev); - - dev->header_ops = &dvb_header_ops; - dev->netdev_ops = &dvb_netdev_ops; - dev->mtu = 4096; - - dev->flags |= IFF_NOARP; -} - -static int get_if(struct dvb_net *dvbnet) -{ - int i; - - for (i=0; istate[i]) - break; - - if (i == DVB_NET_DEVICES_MAX) - return -1; - - dvbnet->state[i]=1; - return i; -} - -static int dvb_net_add_if(struct dvb_net *dvbnet, u16 pid, u8 feedtype) -{ - struct net_device *net; - struct dvb_net_priv *priv; - int result; - int if_num; - - if (feedtype != DVB_NET_FEEDTYPE_MPE && feedtype != DVB_NET_FEEDTYPE_ULE) - return -EINVAL; - if ((if_num = get_if(dvbnet)) < 0) - return -EINVAL; - - net = alloc_netdev(sizeof(struct dvb_net_priv), "dvb", dvb_net_setup); - if (!net) - return -ENOMEM; - - if (dvbnet->dvbdev->id) - snprintf(net->name, IFNAMSIZ, "dvb%d%u%d", - dvbnet->dvbdev->adapter->num, dvbnet->dvbdev->id, if_num); - else - /* compatibility fix to keep dvb0_0 format */ - snprintf(net->name, IFNAMSIZ, "dvb%d_%d", - dvbnet->dvbdev->adapter->num, if_num); - - net->addr_len = 6; - memcpy(net->dev_addr, dvbnet->dvbdev->adapter->proposed_mac, 6); - - dvbnet->device[if_num] = net; - - priv = netdev_priv(net); - priv->net = net; - priv->demux = dvbnet->demux; - priv->pid = pid; - priv->rx_mode = RX_MODE_UNI; - priv->need_pusi = 1; - priv->tscc = 0; - priv->feedtype = feedtype; - reset_ule(priv); - - INIT_WORK(&priv->set_multicast_list_wq, wq_set_multicast_list); - INIT_WORK(&priv->restart_net_feed_wq, wq_restart_net_feed); - mutex_init(&priv->mutex); - - net->base_addr = pid; - - if ((result = register_netdev(net)) < 0) { - dvbnet->device[if_num] = NULL; - free_netdev(net); - return result; - } - printk("dvb_net: created network interface %s\n", net->name); - - return if_num; -} - -static int dvb_net_remove_if(struct dvb_net *dvbnet, unsigned long num) -{ - struct net_device *net = dvbnet->device[num]; - struct dvb_net_priv *priv; - - if (!dvbnet->state[num]) - return -EINVAL; - priv = netdev_priv(net); - if (priv->in_use) - return -EBUSY; - - dvb_net_stop(net); - flush_work(&priv->set_multicast_list_wq); - flush_work(&priv->restart_net_feed_wq); - printk("dvb_net: removed network interface %s\n", net->name); - unregister_netdev(net); - dvbnet->state[num]=0; - dvbnet->device[num] = NULL; - free_netdev(net); - - return 0; -} - -static int dvb_net_do_ioctl(struct file *file, - unsigned int cmd, void *parg) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_net *dvbnet = dvbdev->priv; - int ret = 0; - - if (((file->f_flags&O_ACCMODE)==O_RDONLY)) - return -EPERM; - - if (mutex_lock_interruptible(&dvbnet->ioctl_mutex)) - return -ERESTARTSYS; - - switch (cmd) { - case NET_ADD_IF: - { - struct dvb_net_if *dvbnetif = parg; - int result; - - if (!capable(CAP_SYS_ADMIN)) { - ret = -EPERM; - goto ioctl_error; - } - - if (!try_module_get(dvbdev->adapter->module)) { - ret = -EPERM; - goto ioctl_error; - } - - result=dvb_net_add_if(dvbnet, dvbnetif->pid, dvbnetif->feedtype); - if (result<0) { - module_put(dvbdev->adapter->module); - ret = result; - goto ioctl_error; - } - dvbnetif->if_num=result; - break; - } - case NET_GET_IF: - { - struct net_device *netdev; - struct dvb_net_priv *priv_data; - struct dvb_net_if *dvbnetif = parg; - - if (dvbnetif->if_num >= DVB_NET_DEVICES_MAX || - !dvbnet->state[dvbnetif->if_num]) { - ret = -EINVAL; - goto ioctl_error; - } - - netdev = dvbnet->device[dvbnetif->if_num]; - - priv_data = netdev_priv(netdev); - dvbnetif->pid=priv_data->pid; - dvbnetif->feedtype=priv_data->feedtype; - break; - } - case NET_REMOVE_IF: - { - if (!capable(CAP_SYS_ADMIN)) { - ret = -EPERM; - goto ioctl_error; - } - if ((unsigned long) parg >= DVB_NET_DEVICES_MAX) { - ret = -EINVAL; - goto ioctl_error; - } - ret = dvb_net_remove_if(dvbnet, (unsigned long) parg); - if (!ret) - module_put(dvbdev->adapter->module); - break; - } - - /* binary compatibility cruft */ - case __NET_ADD_IF_OLD: - { - struct __dvb_net_if_old *dvbnetif = parg; - int result; - - if (!capable(CAP_SYS_ADMIN)) { - ret = -EPERM; - goto ioctl_error; - } - - if (!try_module_get(dvbdev->adapter->module)) { - ret = -EPERM; - goto ioctl_error; - } - - result=dvb_net_add_if(dvbnet, dvbnetif->pid, DVB_NET_FEEDTYPE_MPE); - if (result<0) { - module_put(dvbdev->adapter->module); - ret = result; - goto ioctl_error; - } - dvbnetif->if_num=result; - break; - } - case __NET_GET_IF_OLD: - { - struct net_device *netdev; - struct dvb_net_priv *priv_data; - struct __dvb_net_if_old *dvbnetif = parg; - - if (dvbnetif->if_num >= DVB_NET_DEVICES_MAX || - !dvbnet->state[dvbnetif->if_num]) { - ret = -EINVAL; - goto ioctl_error; - } - - netdev = dvbnet->device[dvbnetif->if_num]; - - priv_data = netdev_priv(netdev); - dvbnetif->pid=priv_data->pid; - break; - } - default: - ret = -ENOTTY; - break; - } - -ioctl_error: - mutex_unlock(&dvbnet->ioctl_mutex); - return ret; -} - -static long dvb_net_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - return dvb_usercopy(file, cmd, arg, dvb_net_do_ioctl); -} - -static int dvb_net_close(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_net *dvbnet = dvbdev->priv; - - dvb_generic_release(inode, file); - - if(dvbdev->users == 1 && dvbnet->exit == 1) - wake_up(&dvbdev->wait_queue); - return 0; -} - - -static const struct file_operations dvb_net_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = dvb_net_ioctl, - .open = dvb_generic_open, - .release = dvb_net_close, - .llseek = noop_llseek, -}; - -static struct dvb_device dvbdev_net = { - .priv = NULL, - .users = 1, - .writers = 1, - .fops = &dvb_net_fops, -}; - - -void dvb_net_release (struct dvb_net *dvbnet) -{ - int i; - - dvbnet->exit = 1; - if (dvbnet->dvbdev->users < 1) - wait_event(dvbnet->dvbdev->wait_queue, - dvbnet->dvbdev->users==1); - - dvb_unregister_device(dvbnet->dvbdev); - - for (i=0; istate[i]) - continue; - dvb_net_remove_if(dvbnet, i); - } -} -EXPORT_SYMBOL(dvb_net_release); - - -int dvb_net_init (struct dvb_adapter *adap, struct dvb_net *dvbnet, - struct dmx_demux *dmx) -{ - int i; - - mutex_init(&dvbnet->ioctl_mutex); - dvbnet->demux = dmx; - - for (i=0; istate[i] = 0; - - return dvb_register_device(adap, &dvbnet->dvbdev, &dvbdev_net, - dvbnet, DVB_DEVICE_NET); -} -EXPORT_SYMBOL(dvb_net_init); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_net.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,67 +0,0 @@ -/* - * dvb_net.h - * - * Copyright (C) 2001 Ralph Metzler for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVB_NET_H_ -#define _DVB_NET_H_ - -#include -#include -#include -#include -#include - -#include "dvbdev.h" - -#define DVB_NET_DEVICES_MAX 10 - -#ifdef CONFIG_DVB_NET - -struct dvb_net { - struct dvb_device *dvbdev; - struct net_device *device[DVB_NET_DEVICES_MAX]; - int state[DVB_NET_DEVICES_MAX]; - unsigned int exit:1; - struct dmx_demux *demux; - struct mutex ioctl_mutex; -}; - -void dvb_net_release(struct dvb_net *); -int dvb_net_init(struct dvb_adapter *, struct dvb_net *, struct dmx_demux *); - -#else - -struct dvb_net { - struct dvb_device *dvbdev; -}; - -static inline void dvb_net_release(struct dvb_net *dvbnet) -{ -} - -static inline int dvb_net_init(struct dvb_adapter *adap, - struct dvb_net *dvbnet, struct dmx_demux *dmx) -{ - return 0; -} - -#endif /* ifdef CONFIG_DVB_NET */ - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,235 +0,0 @@ -#include -#include "dvb_netstream.h" - -static ssize_t ns_write(struct file *file, const char *buf, - size_t count, loff_t *ppos) -{ - printk("%s\n", __func__); - return 0; -} - -static ssize_t ns_read(struct file *file, char *buf, - size_t count, loff_t *ppos) -{ - printk("%s\n", __func__); - return 0; -} - -static unsigned int ns_poll(struct file *file, poll_table *wait) -{ - printk("%s\n", __func__); - return 0; -} - -static int ns_stop(struct dvbnss *nss) -{ - struct dvb_netstream *ns = nss->ns; - - mutex_lock(&ns->mutex); - if (nss->running && ns->stop) { - ns->stop(nss); - nss->running = 0; - } - mutex_unlock(&ns->mutex); - return 0; -} - -static int ns_release(struct inode *inode, struct file *file) -{ - struct dvbnss *nss = file->private_data; - struct dvb_netstream *ns = nss->ns; - - ns_stop(nss); - if (ns->free) - ns->free(nss); - mutex_lock(&ns->mutex); - list_del(&nss->nssl); - mutex_unlock(&ns->mutex); - vfree(nss); - return 0; -} - -static int ns_open(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - struct dvb_netstream *ns = dvbdev->priv; - struct dvbnss *nss; - - nss = vmalloc(sizeof(*nss)); - if (!nss) - return -ENOMEM; - nss->ns = ns; - if (ns->alloc && ns->alloc(nss) < 0) { - vfree(nss); - return -EBUSY; - } - file->private_data = nss; - nss->running = 0; - mutex_lock(&ns->mutex); - list_add(&nss->nssl, &ns->nssl); - mutex_unlock(&ns->mutex); - return 0; -} - -static int set_net(struct dvbnss *nss, struct dvb_ns_params *p) -{ - return 0; -} - -static int do_ioctl(struct file *file, unsigned int cmd, void *parg) -{ - struct dvbnss *nss = file->private_data; - struct dvb_netstream *ns = nss->ns; - //unsigned long arg = (unsigned long) parg; - int ret = 0; - - switch (cmd) { - case NS_SET_RTCP_MSG: - { - struct dvb_ns_rtcp *rtcpm = parg; - - if (ns->set_rtcp_msg) { - //printk("%s calling NS_SET_RTCP_MSG\n", __func__); - ret = ns->set_rtcp_msg(nss, rtcpm->msg, rtcpm->len); - } - break; - } - - case NS_SET_NET: - memcpy(&nss->params, parg, sizeof(nss->params)); - if (ns->set_net) { - ret = ns->set_net(nss); - } else - ret = set_net(nss, (struct dvb_ns_params *) parg); - break; - - case NS_START: - mutex_lock(&ns->mutex); - if (nss->running) { - ret = -EBUSY; - } else if (ns->start) { - ret = ns->start(nss); - nss->running = 1; - } - mutex_unlock(&ns->mutex); - break; - - case NS_STOP: - ns_stop(nss); - break; - - case NS_SET_PACKETS: - { - struct dvb_ns_packet *packet = parg; - if (ns->set_ts_packets) { - ret = ns->set_ts_packets(nss, packet->buf, packet->count * 188); - } - break; - } - - case NS_INSERT_PACKETS: - { - u8 count = *(u8 *) parg; - if (ns->insert_ts_packets) - ret = ns->insert_ts_packets(nss, count); - break; - } - - case NS_SET_PID: - { - u16 pid = *(u16 *) parg; - u16 byte = (pid & 0x1fff) >> 3; - u8 bit = 1 << (pid & 7); - - if (pid & 0x2000) { - if (pid & 0x8000) - memset(nss->pids, 0xff, 0x400); - else - memset(nss->pids, 0x00, 0x400); - } else { - if (pid & 0x8000) - nss->pids[byte] |= bit; - else - nss->pids[byte] &= ~bit; - } - if (ns->set_pid) - ret = ns->set_pid(nss, pid); - break; - } - - case NS_SET_PIDS: - ret = copy_from_user(nss->pids, *(u8 **) parg, 0x400); - if (ret < 0) - return ret; - if (ns->set_pids) - ret = ns->set_pids(nss); - break; - - case NS_SET_CI: - { - u8 ci = *(u8 *) parg; - - if (nss->running) - ret = -EBUSY; - else if (ns->set_ci) - ret = ns->set_ci(nss, ci); - break; - } - - default: - ret = -EINVAL; - break; - } - return ret; -} - -static long ns_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - return dvb_usercopy(file, cmd, arg, do_ioctl); -} - -static const struct file_operations ns_fops = { - .owner = THIS_MODULE, - .read = ns_read, - .write = ns_write, - .open = ns_open, - .release = ns_release, - .poll = ns_poll, - .mmap = 0, - .unlocked_ioctl = ns_ioctl, -}; - -static struct dvb_device ns_dev = { - .priv = 0, - .readers = 1, - .writers = 1, - .users = 1, - .fops = &ns_fops, -}; - - -int dvb_netstream_init(struct dvb_adapter *dvb_adapter, struct dvb_netstream *ns) -{ - mutex_init(&ns->mutex); - spin_lock_init(&ns->lock); - ns->exit = 0; - dvb_register_device(dvb_adapter, &ns->dvbdev, &ns_dev, ns, - DVB_DEVICE_NS); - INIT_LIST_HEAD(&ns->nssl); - return 0; -} - -EXPORT_SYMBOL(dvb_netstream_init); - -void dvb_netstream_release(struct dvb_netstream *ns) -{ - ns->exit=1; - if (ns->dvbdev->users > 1) { - wait_event(ns->dvbdev->wait_queue, - ns->dvbdev->users == 1); - } - dvb_unregister_device(ns->dvbdev); -} - -EXPORT_SYMBOL(dvb_netstream_release); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_netstream.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,70 +0,0 @@ -#ifndef _DVB_NETSTREAM_H_ -#define _DVB_NETSTREAM_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvbdev.h" - -#define DVBNS_MAXPIDS 32 - -struct dvbnss { - struct dvb_netstream *ns; - void *priv; - - u8 pids[1024]; - u8 packet[1328]; - u32 pp; - - struct socket *sock; - struct sockaddr_in sadr; - u32 sn; - - struct dvb_ns_params params; - - struct list_head nssl; - int running; -}; - -#define MAX_DVBNSS 32 - -struct dvb_netstream { - void *priv; - - struct mutex mutex; - spinlock_t lock; - struct dvb_device *dvbdev; - int exit; - - struct list_head nssl; - - int (*set_net) (struct dvbnss *); - int (*set_pid) (struct dvbnss *, u16); - int (*set_pids) (struct dvbnss *); - int (*set_ci) (struct dvbnss *, u8); - int (*set_rtcp_msg) (struct dvbnss *, u8 *, u32); - int (*set_ts_packets) (struct dvbnss *, u8 *, u32); - int (*insert_ts_packets) (struct dvbnss *, u8); - int (*start) (struct dvbnss *); - int (*stop) (struct dvbnss *); - int (*alloc) (struct dvbnss *); - void (*free) (struct dvbnss *); - -}; - - -void dvb_netstream_release(struct dvb_netstream *); -int dvb_netstream_init(struct dvb_adapter *, struct dvb_netstream *); - - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,299 +0,0 @@ -/* - * - * dvb_ringbuffer.c: ring buffer implementation for the dvb driver - * - * Copyright (C) 2003 Oliver Endriss - * Copyright (C) 2004 Andrew de Quincey - * - * based on code originally found in av7110.c & dvb_ci.c: - * Copyright (C) 1999-2003 Ralph Metzler - * & Marcus Metzler for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - - - -#include -#include -#include -#include -#include -#include - -#include "dvb_ringbuffer.h" - -#define PKT_READY 0 -#define PKT_DISPOSED 1 - - -void dvb_ringbuffer_init(struct dvb_ringbuffer *rbuf, void *data, size_t len) -{ - rbuf->pread=rbuf->pwrite=0; - rbuf->data=data; - rbuf->size=len; - rbuf->error=0; - - init_waitqueue_head(&rbuf->queue); - - spin_lock_init(&(rbuf->lock)); -} - - - -int dvb_ringbuffer_empty(struct dvb_ringbuffer *rbuf) -{ - return (rbuf->pread==rbuf->pwrite); -} - - - -ssize_t dvb_ringbuffer_free(struct dvb_ringbuffer *rbuf) -{ - ssize_t free; - - free = rbuf->pread - rbuf->pwrite; - if (free <= 0) - free += rbuf->size; - return free-1; -} - - - -ssize_t dvb_ringbuffer_avail(struct dvb_ringbuffer *rbuf) -{ - ssize_t avail; - - avail = rbuf->pwrite - rbuf->pread; - if (avail < 0) - avail += rbuf->size; - return avail; -} - - - -void dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf) -{ - rbuf->pread = rbuf->pwrite; - rbuf->error = 0; -} -EXPORT_SYMBOL(dvb_ringbuffer_flush); - -void dvb_ringbuffer_reset(struct dvb_ringbuffer *rbuf) -{ - rbuf->pread = rbuf->pwrite = 0; - rbuf->error = 0; -} - -void dvb_ringbuffer_flush_spinlock_wakeup(struct dvb_ringbuffer *rbuf) -{ - unsigned long flags; - - spin_lock_irqsave(&rbuf->lock, flags); - dvb_ringbuffer_flush(rbuf); - spin_unlock_irqrestore(&rbuf->lock, flags); - - wake_up(&rbuf->queue); -} - -ssize_t dvb_ringbuffer_read_user(struct dvb_ringbuffer *rbuf, u8 __user *buf, size_t len) -{ - size_t todo = len; - size_t split; - - split = (rbuf->pread + len > rbuf->size) ? rbuf->size - rbuf->pread : 0; - if (split > 0) { - if (copy_to_user(buf, rbuf->data+rbuf->pread, split)) - return -EFAULT; - buf += split; - todo -= split; - rbuf->pread = 0; - } - if (copy_to_user(buf, rbuf->data+rbuf->pread, todo)) - return -EFAULT; - - rbuf->pread = (rbuf->pread + todo) % rbuf->size; - - return len; -} - -void dvb_ringbuffer_read(struct dvb_ringbuffer *rbuf, u8 *buf, size_t len) -{ - size_t todo = len; - size_t split; - - split = (rbuf->pread + len > rbuf->size) ? rbuf->size - rbuf->pread : 0; - if (split > 0) { - memcpy(buf, rbuf->data+rbuf->pread, split); - buf += split; - todo -= split; - rbuf->pread = 0; - } - memcpy(buf, rbuf->data+rbuf->pread, todo); - - rbuf->pread = (rbuf->pread + todo) % rbuf->size; -} - - -ssize_t dvb_ringbuffer_write(struct dvb_ringbuffer *rbuf, const u8 *buf, size_t len) -{ - size_t todo = len; - size_t split; - - split = (rbuf->pwrite + len > rbuf->size) ? rbuf->size - rbuf->pwrite : 0; - - if (split > 0) { - memcpy(rbuf->data+rbuf->pwrite, buf, split); - buf += split; - todo -= split; - rbuf->pwrite = 0; - } - memcpy(rbuf->data+rbuf->pwrite, buf, todo); - rbuf->pwrite = (rbuf->pwrite + todo) % rbuf->size; - - return len; -} - -ssize_t dvb_ringbuffer_pkt_write(struct dvb_ringbuffer *rbuf, u8* buf, size_t len) -{ - int status; - ssize_t oldpwrite = rbuf->pwrite; - - DVB_RINGBUFFER_WRITE_BYTE(rbuf, len >> 8); - DVB_RINGBUFFER_WRITE_BYTE(rbuf, len & 0xff); - DVB_RINGBUFFER_WRITE_BYTE(rbuf, PKT_READY); - status = dvb_ringbuffer_write(rbuf, buf, len); - - if (status < 0) rbuf->pwrite = oldpwrite; - return status; -} - -ssize_t dvb_ringbuffer_pkt_read_user(struct dvb_ringbuffer *rbuf, size_t idx, - int offset, u8 __user *buf, size_t len) -{ - size_t todo; - size_t split; - size_t pktlen; - - pktlen = rbuf->data[idx] << 8; - pktlen |= rbuf->data[(idx + 1) % rbuf->size]; - if (offset > pktlen) return -EINVAL; - if ((offset + len) > pktlen) len = pktlen - offset; - - idx = (idx + DVB_RINGBUFFER_PKTHDRSIZE + offset) % rbuf->size; - todo = len; - split = ((idx + len) > rbuf->size) ? rbuf->size - idx : 0; - if (split > 0) { - if (copy_to_user(buf, rbuf->data+idx, split)) - return -EFAULT; - buf += split; - todo -= split; - idx = 0; - } - if (copy_to_user(buf, rbuf->data+idx, todo)) - return -EFAULT; - - return len; -} - -ssize_t dvb_ringbuffer_pkt_read(struct dvb_ringbuffer *rbuf, size_t idx, - int offset, u8* buf, size_t len) -{ - size_t todo; - size_t split; - size_t pktlen; - - pktlen = rbuf->data[idx] << 8; - pktlen |= rbuf->data[(idx + 1) % rbuf->size]; - if (offset > pktlen) return -EINVAL; - if ((offset + len) > pktlen) len = pktlen - offset; - - idx = (idx + DVB_RINGBUFFER_PKTHDRSIZE + offset) % rbuf->size; - todo = len; - split = ((idx + len) > rbuf->size) ? rbuf->size - idx : 0; - if (split > 0) { - memcpy(buf, rbuf->data+idx, split); - buf += split; - todo -= split; - idx = 0; - } - memcpy(buf, rbuf->data+idx, todo); - return len; -} - -void dvb_ringbuffer_pkt_dispose(struct dvb_ringbuffer *rbuf, size_t idx) -{ - size_t pktlen; - - rbuf->data[(idx + 2) % rbuf->size] = PKT_DISPOSED; - - // clean up disposed packets - while(dvb_ringbuffer_avail(rbuf) > DVB_RINGBUFFER_PKTHDRSIZE) { - if (DVB_RINGBUFFER_PEEK(rbuf, 2) == PKT_DISPOSED) { - pktlen = DVB_RINGBUFFER_PEEK(rbuf, 0) << 8; - pktlen |= DVB_RINGBUFFER_PEEK(rbuf, 1); - DVB_RINGBUFFER_SKIP(rbuf, pktlen + DVB_RINGBUFFER_PKTHDRSIZE); - } else { - // first packet is not disposed, so we stop cleaning now - break; - } - } -} - -ssize_t dvb_ringbuffer_pkt_next(struct dvb_ringbuffer *rbuf, size_t idx, size_t* pktlen) -{ - int consumed; - int curpktlen; - int curpktstatus; - - if (idx == -1) { - idx = rbuf->pread; - } else { - curpktlen = rbuf->data[idx] << 8; - curpktlen |= rbuf->data[(idx + 1) % rbuf->size]; - idx = (idx + curpktlen + DVB_RINGBUFFER_PKTHDRSIZE) % rbuf->size; - } - - consumed = (idx - rbuf->pread) % rbuf->size; - - while((dvb_ringbuffer_avail(rbuf) - consumed) > DVB_RINGBUFFER_PKTHDRSIZE) { - - curpktlen = rbuf->data[idx] << 8; - curpktlen |= rbuf->data[(idx + 1) % rbuf->size]; - curpktstatus = rbuf->data[(idx + 2) % rbuf->size]; - - if (curpktstatus == PKT_READY) { - *pktlen = curpktlen; - return idx; - } - - consumed += curpktlen + DVB_RINGBUFFER_PKTHDRSIZE; - idx = (idx + curpktlen + DVB_RINGBUFFER_PKTHDRSIZE) % rbuf->size; - } - - // no packets available - return -1; -} - - - -EXPORT_SYMBOL(dvb_ringbuffer_init); -EXPORT_SYMBOL(dvb_ringbuffer_empty); -EXPORT_SYMBOL(dvb_ringbuffer_free); -EXPORT_SYMBOL(dvb_ringbuffer_avail); -EXPORT_SYMBOL(dvb_ringbuffer_flush_spinlock_wakeup); -EXPORT_SYMBOL(dvb_ringbuffer_read_user); -EXPORT_SYMBOL(dvb_ringbuffer_read); -EXPORT_SYMBOL(dvb_ringbuffer_write); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvb_ringbuffer.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,186 +0,0 @@ -/* - * - * dvb_ringbuffer.h: ring buffer implementation for the dvb driver - * - * Copyright (C) 2003 Oliver Endriss - * Copyright (C) 2004 Andrew de Quincey - * - * based on code originally found in av7110.c & dvb_ci.c: - * Copyright (C) 1999-2003 Ralph Metzler & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _DVB_RINGBUFFER_H_ -#define _DVB_RINGBUFFER_H_ - -#include -#include - -struct dvb_ringbuffer { - u8 *data; - ssize_t size; - ssize_t pread; - ssize_t pwrite; - int error; - - wait_queue_head_t queue; - spinlock_t lock; -}; - -#define DVB_RINGBUFFER_PKTHDRSIZE 3 - - -/* -** Notes: -** ------ -** (1) For performance reasons read and write routines don't check buffer sizes -** and/or number of bytes free/available. This has to be done before these -** routines are called. For example: -** -** *** write bytes *** -** free = dvb_ringbuffer_free(rbuf); -** if (free >= buflen) -** count = dvb_ringbuffer_write(rbuf, buffer, buflen); -** else -** ... -** -** *** read min. 1000, max. bytes *** -** avail = dvb_ringbuffer_avail(rbuf); -** if (avail >= 1000) -** count = dvb_ringbuffer_read(rbuf, buffer, min(avail, bufsize)); -** else -** ... -** -** (2) If there is exactly one reader and one writer, there is no need -** to lock read or write operations. -** Two or more readers must be locked against each other. -** Flushing the buffer counts as a read operation. -** Resetting the buffer counts as a read and write operation. -** Two or more writers must be locked against each other. -*/ - -/* initialize ring buffer, lock and queue */ -extern void dvb_ringbuffer_init(struct dvb_ringbuffer *rbuf, void *data, size_t len); - -/* test whether buffer is empty */ -extern int dvb_ringbuffer_empty(struct dvb_ringbuffer *rbuf); - -/* return the number of free bytes in the buffer */ -extern ssize_t dvb_ringbuffer_free(struct dvb_ringbuffer *rbuf); - -/* return the number of bytes waiting in the buffer */ -extern ssize_t dvb_ringbuffer_avail(struct dvb_ringbuffer *rbuf); - - -/* -** Reset the read and write pointers to zero and flush the buffer -** This counts as a read and write operation -*/ -extern void dvb_ringbuffer_reset(struct dvb_ringbuffer *rbuf); - - -/* read routines & macros */ -/* ---------------------- */ -/* flush buffer */ -extern void dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf); - -/* flush buffer protected by spinlock and wake-up waiting task(s) */ -extern void dvb_ringbuffer_flush_spinlock_wakeup(struct dvb_ringbuffer *rbuf); - -/* peek at byte in the buffer */ -#define DVB_RINGBUFFER_PEEK(rbuf,offs) \ - (rbuf)->data[((rbuf)->pread+(offs))%(rbuf)->size] - -/* advance read ptr by bytes */ -#define DVB_RINGBUFFER_SKIP(rbuf,num) \ - (rbuf)->pread=((rbuf)->pread+(num))%(rbuf)->size - -/* -** read bytes from ring buffer into -** specifies whether resides in user space -** returns number of bytes transferred or -EFAULT -*/ -extern ssize_t dvb_ringbuffer_read_user(struct dvb_ringbuffer *rbuf, - u8 __user *buf, size_t len); -extern void dvb_ringbuffer_read(struct dvb_ringbuffer *rbuf, - u8 *buf, size_t len); - - -/* write routines & macros */ -/* ----------------------- */ -/* write single byte to ring buffer */ -#define DVB_RINGBUFFER_WRITE_BYTE(rbuf,byte) \ - { (rbuf)->data[(rbuf)->pwrite]=(byte); \ - (rbuf)->pwrite=((rbuf)->pwrite+1)%(rbuf)->size; } -/* -** write bytes to ring buffer -** specifies whether resides in user space -** returns number of bytes transferred or -EFAULT -*/ -extern ssize_t dvb_ringbuffer_write(struct dvb_ringbuffer *rbuf, const u8 *buf, - size_t len); - - -/** - * Write a packet into the ringbuffer. - * - * Ringbuffer to write to. - * Buffer to write. - * Length of buffer (currently limited to 65535 bytes max). - * returns Number of bytes written, or -EFAULT, -ENOMEM, -EVINAL. - */ -extern ssize_t dvb_ringbuffer_pkt_write(struct dvb_ringbuffer *rbuf, u8* buf, - size_t len); - -/** - * Read from a packet in the ringbuffer. Note: unlike dvb_ringbuffer_read(), this - * does NOT update the read pointer in the ringbuffer. You must use - * dvb_ringbuffer_pkt_dispose() to mark a packet as no longer required. - * - * Ringbuffer concerned. - * Packet index as returned by dvb_ringbuffer_pkt_next(). - * Offset into packet to read from. - * Destination buffer for data. - * Size of destination buffer. - * Set to 1 if is in userspace. - * returns Number of bytes read, or -EFAULT. - */ -extern ssize_t dvb_ringbuffer_pkt_read_user(struct dvb_ringbuffer *rbuf, size_t idx, - int offset, u8 __user *buf, size_t len); -extern ssize_t dvb_ringbuffer_pkt_read(struct dvb_ringbuffer *rbuf, size_t idx, - int offset, u8 *buf, size_t len); - -/** - * Dispose of a packet in the ring buffer. - * - * Ring buffer concerned. - * Packet index as returned by dvb_ringbuffer_pkt_next(). - */ -extern void dvb_ringbuffer_pkt_dispose(struct dvb_ringbuffer *rbuf, size_t idx); - -/** - * Get the index of the next packet in a ringbuffer. - * - * Ringbuffer concerned. - * Previous packet index, or -1 to return the first packet index. - * On success, will be updated to contain the length of the packet in bytes. - * returns Packet index (if >=0), or -1 if no packets available. - */ -extern ssize_t dvb_ringbuffer_pkt_next(struct dvb_ringbuffer *rbuf, size_t idx, size_t* pktlen); - - -#endif /* _DVB_RINGBUFFER_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,513 +0,0 @@ -/* - * dvbdev.c - * - * Copyright (C) 2000 Ralph Metzler - * & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dvbdev.h" - -static DEFINE_MUTEX(dvbdev_mutex); -static int dvbdev_debug; - -module_param(dvbdev_debug, int, 0644); -MODULE_PARM_DESC(dvbdev_debug, "Turn on/off device debugging (default:off)."); - -#define dprintk if (dvbdev_debug) printk - -static LIST_HEAD(dvb_adapter_list); -static DEFINE_MUTEX(dvbdev_register_lock); - -static const char * const dnames[] = { - "video", "audio", "sec", "frontend", "demux", "dvr", "ca", - "net", "osd", "ci", "mod", "ns", "nsd" -}; - -#ifdef CONFIG_DVB_DYNAMIC_MINORS -#define MAX_DVB_MINORS 256 -#define DVB_MAX_IDS MAX_DVB_MINORS -#else -#define DVB_MAX_IDS 4 -#define nums2minor(num,type,id) ((num << 6) | (id << 4) | type) -#define MAX_DVB_MINORS (DVB_MAX_ADAPTERS*64) -#endif - -static struct class *dvb_class; - -static struct dvb_device *dvb_minors[MAX_DVB_MINORS]; -static DECLARE_RWSEM(minor_rwsem); - -static int dvb_device_open(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev; - - //mutex_lock(&dvbdev_mutex); - down_read(&minor_rwsem); - dvbdev = dvb_minors[iminor(inode)]; - - if (dvbdev && dvbdev->fops) { - int err = 0; - const struct file_operations *old_fops; - - file->private_data = dvbdev; - old_fops = file->f_op; - file->f_op = fops_get(dvbdev->fops); - if (file->f_op == NULL) { - file->f_op = old_fops; - goto fail; - } - if(file->f_op->open) - err = file->f_op->open(inode,file); - if (err) { - fops_put(file->f_op); - file->f_op = fops_get(old_fops); - } - fops_put(old_fops); - up_read(&minor_rwsem); - //mutex_unlock(&dvbdev_mutex); - return err; - } -fail: - up_read(&minor_rwsem); - //mutex_unlock(&dvbdev_mutex); - return -ENODEV; -} - - -static const struct file_operations dvb_device_fops = -{ - .owner = THIS_MODULE, - .open = dvb_device_open, - .llseek = noop_llseek, -}; - -static struct cdev dvb_device_cdev; - -int dvb_generic_open(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - - if (!dvbdev) - return -ENODEV; - - if (!dvbdev->users) - return -EBUSY; - - if ((file->f_flags & O_ACCMODE) == O_RDONLY) { - if (!dvbdev->readers) - return -EBUSY; - dvbdev->readers--; - } else { - if (!dvbdev->writers) - return -EBUSY; - dvbdev->writers--; - } - - dvbdev->users--; - return 0; -} -EXPORT_SYMBOL(dvb_generic_open); - - -int dvb_generic_release(struct inode *inode, struct file *file) -{ - struct dvb_device *dvbdev = file->private_data; - - if (!dvbdev) - return -ENODEV; - - if ((file->f_flags & O_ACCMODE) == O_RDONLY) { - dvbdev->readers++; - } else { - dvbdev->writers++; - } - - dvbdev->users++; - return 0; -} -EXPORT_SYMBOL(dvb_generic_release); - - -long dvb_generic_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - struct dvb_device *dvbdev = file->private_data; - - if (!dvbdev) - return -ENODEV; - - if (!dvbdev->kernel_ioctl) - return -EINVAL; - - return dvb_usercopy(file, cmd, arg, dvbdev->kernel_ioctl); -} -EXPORT_SYMBOL(dvb_generic_ioctl); - - -static int dvbdev_get_free_id (struct dvb_adapter *adap, int type) -{ - u32 id = 0; - - while (id < DVB_MAX_IDS) { - struct dvb_device *dev; - list_for_each_entry(dev, &adap->device_list, list_head) - if (dev->type == type && dev->id == id) - goto skip; - return id; -skip: - id++; - } - return -ENFILE; -} - - -int dvb_register_device(struct dvb_adapter *adap, struct dvb_device **pdvbdev, - const struct dvb_device *template, void *priv, int type) -{ - struct dvb_device *dvbdev; - struct file_operations *dvbdevfops; - struct device *clsdev; - int minor; - int id; - - mutex_lock(&dvbdev_register_lock); - - if ((id = dvbdev_get_free_id (adap, type)) < 0){ - mutex_unlock(&dvbdev_register_lock); - *pdvbdev = NULL; - printk(KERN_ERR "%s: couldn't find free device id\n", __func__); - return -ENFILE; - } - - *pdvbdev = dvbdev = kmalloc(sizeof(struct dvb_device), GFP_KERNEL); - - if (!dvbdev){ - mutex_unlock(&dvbdev_register_lock); - return -ENOMEM; - } - - dvbdevfops = kzalloc(sizeof(struct file_operations), GFP_KERNEL); - - if (!dvbdevfops){ - kfree (dvbdev); - mutex_unlock(&dvbdev_register_lock); - return -ENOMEM; - } - - memcpy(dvbdev, template, sizeof(struct dvb_device)); - dvbdev->type = type; - dvbdev->id = id; - dvbdev->adapter = adap; - dvbdev->priv = priv; - dvbdev->fops = dvbdevfops; - init_waitqueue_head (&dvbdev->wait_queue); - - memcpy(dvbdevfops, template->fops, sizeof(struct file_operations)); - dvbdevfops->owner = adap->module; - - list_add_tail (&dvbdev->list_head, &adap->device_list); - - down_write(&minor_rwsem); -#ifdef CONFIG_DVB_DYNAMIC_MINORS - for (minor = 0; minor < MAX_DVB_MINORS; minor++) - if (dvb_minors[minor] == NULL) - break; - - if (minor == MAX_DVB_MINORS) { - kfree(dvbdevfops); - kfree(dvbdev); - up_write(&minor_rwsem); - mutex_unlock(&dvbdev_register_lock); - return -EINVAL; - } -#else - minor = nums2minor(adap->num, type, id); -#endif - - dvbdev->minor = minor; - dvb_minors[minor] = dvbdev; - up_write(&minor_rwsem); - - mutex_unlock(&dvbdev_register_lock); - - clsdev = device_create(dvb_class, adap->device, - MKDEV(DVB_MAJOR, minor), - dvbdev, "dvb%d.%s%d", adap->num, dnames[type], id); - if (IS_ERR(clsdev)) { - printk(KERN_ERR "%s: failed to create device dvb%d.%s%d (%ld)\n", - __func__, adap->num, dnames[type], id, PTR_ERR(clsdev)); - return PTR_ERR(clsdev); - } - - dprintk(KERN_DEBUG "DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n", - adap->num, dnames[type], id, minor, minor); - - return 0; -} -EXPORT_SYMBOL(dvb_register_device); - - -void dvb_unregister_device(struct dvb_device *dvbdev) -{ - if (!dvbdev) - return; - - down_write(&minor_rwsem); - dvb_minors[dvbdev->minor] = NULL; - up_write(&minor_rwsem); - - device_destroy(dvb_class, MKDEV(DVB_MAJOR, dvbdev->minor)); - - list_del (&dvbdev->list_head); - kfree (dvbdev->fops); - kfree (dvbdev); -} -EXPORT_SYMBOL(dvb_unregister_device); - -static int dvbdev_check_free_adapter_num(int num) -{ - struct list_head *entry; - list_for_each(entry, &dvb_adapter_list) { - struct dvb_adapter *adap; - adap = list_entry(entry, struct dvb_adapter, list_head); - if (adap->num == num) - return 0; - } - return 1; -} - -static int dvbdev_get_free_adapter_num (void) -{ - int num = 0; - - while (num < DVB_MAX_ADAPTERS) { - if (dvbdev_check_free_adapter_num(num)) - return num; - num++; - } - - return -ENFILE; -} - - -int dvb_register_adapter(struct dvb_adapter *adap, const char *name, - struct module *module, struct device *device, - short *adapter_nums) -{ - int i, num; - - mutex_lock(&dvbdev_register_lock); - - for (i = 0; i < DVB_MAX_ADAPTERS; ++i) { - num = adapter_nums[i]; - if (num >= 0 && num < DVB_MAX_ADAPTERS) { - /* use the one the driver asked for */ - if (dvbdev_check_free_adapter_num(num)) - break; - } else { - num = dvbdev_get_free_adapter_num(); - break; - } - num = -1; - } - - if (num < 0) { - mutex_unlock(&dvbdev_register_lock); - return -ENFILE; - } - - memset (adap, 0, sizeof(struct dvb_adapter)); - INIT_LIST_HEAD (&adap->device_list); - - printk(KERN_INFO "DVB: registering new adapter (%s)\n", name); - - adap->num = num; - adap->name = name; - adap->module = module; - adap->device = device; - adap->mfe_shared = 0; - adap->mfe_dvbdev = NULL; - mutex_init (&adap->mfe_lock); - - list_add_tail (&adap->list_head, &dvb_adapter_list); - - mutex_unlock(&dvbdev_register_lock); - - return num; -} -EXPORT_SYMBOL(dvb_register_adapter); - - -int dvb_unregister_adapter(struct dvb_adapter *adap) -{ - mutex_lock(&dvbdev_register_lock); - list_del (&adap->list_head); - mutex_unlock(&dvbdev_register_lock); - return 0; -} -EXPORT_SYMBOL(dvb_unregister_adapter); - -/* if the miracle happens and "generic_usercopy()" is included into - the kernel, then this can vanish. please don't make the mistake and - define this as video_usercopy(). this will introduce a dependecy - to the v4l "videodev.o" module, which is unnecessary for some - cards (ie. the budget dvb-cards don't need the v4l module...) */ -int dvb_usercopy(struct file *file, - unsigned int cmd, unsigned long arg, - int (*func)(struct file *file, - unsigned int cmd, void *arg)) -{ - char sbuf[128]; - void *mbuf = NULL; - void *parg = NULL; - int err = -EINVAL; - - /* Copy arguments into temp kernel buffer */ - switch (_IOC_DIR(cmd)) { - case _IOC_NONE: - /* - * For this command, the pointer is actually an integer - * argument. - */ - parg = (void *) arg; - break; - case _IOC_READ: /* some v4l ioctls are marked wrong ... */ - case _IOC_WRITE: - case (_IOC_WRITE | _IOC_READ): - if (_IOC_SIZE(cmd) <= sizeof(sbuf)) { - parg = sbuf; - } else { - /* too big to allocate from stack */ - mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL); - if (NULL == mbuf) - return -ENOMEM; - parg = mbuf; - } - - err = -EFAULT; - if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) - goto out; - break; - } - - /* call driver */ - //mutex_lock(&dvbdev_mutex); - if ((err = func(file, cmd, parg)) == -ENOIOCTLCMD) - err = -ENOTTY; - //mutex_unlock(&dvbdev_mutex); - - if (err < 0) - goto out; - - /* Copy results into user buffer */ - switch (_IOC_DIR(cmd)) - { - case _IOC_READ: - case (_IOC_WRITE | _IOC_READ): - if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) - err = -EFAULT; - break; - } - -out: - kfree(mbuf); - return err; -} -EXPORT_SYMBOL(dvb_usercopy); - -static int dvb_uevent(struct device *dev, struct kobj_uevent_env *env) -{ - struct dvb_device *dvbdev = dev_get_drvdata(dev); - - add_uevent_var(env, "DVB_ADAPTER_NUM=%d", dvbdev->adapter->num); - add_uevent_var(env, "DVB_DEVICE_TYPE=%s", dnames[dvbdev->type]); - add_uevent_var(env, "DVB_DEVICE_NUM=%d", dvbdev->id); - return 0; -} - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) -static char *dvb_devnode(struct device *dev, mode_t *mode) -#else -static char *dvb_devnode(struct device *dev, umode_t *mode) -#endif -{ - struct dvb_device *dvbdev = dev_get_drvdata(dev); - - return kasprintf(GFP_KERNEL, "dvb/adapter%d/%s%d", - dvbdev->adapter->num, dnames[dvbdev->type], dvbdev->id); -} - - -static int __init init_dvbdev(void) -{ - int retval; - dev_t dev = MKDEV(DVB_MAJOR, 0); - - if ((retval = register_chrdev_region(dev, MAX_DVB_MINORS, "DVB")) != 0) { - printk(KERN_ERR "dvb-core: unable to get major %d\n", DVB_MAJOR); - return retval; - } - - cdev_init(&dvb_device_cdev, &dvb_device_fops); - if ((retval = cdev_add(&dvb_device_cdev, dev, MAX_DVB_MINORS)) != 0) { - printk(KERN_ERR "dvb-core: unable register character device\n"); - goto error; - } - - dvb_class = class_create(THIS_MODULE, "dvb"); - if (IS_ERR(dvb_class)) { - retval = PTR_ERR(dvb_class); - goto error; - } - dvb_class->dev_uevent = dvb_uevent; - dvb_class->devnode = dvb_devnode; - return 0; - -error: - cdev_del(&dvb_device_cdev); - unregister_chrdev_region(dev, MAX_DVB_MINORS); - return retval; -} - - -static void __exit exit_dvbdev(void) -{ - class_destroy(dvb_class); - cdev_del(&dvb_device_cdev); - unregister_chrdev_region(MKDEV(DVB_MAJOR, 0), MAX_DVB_MINORS); -} - -subsys_initcall(init_dvbdev); -module_exit(exit_dvbdev); - -MODULE_DESCRIPTION("DVB Core Driver"); -MODULE_AUTHOR("Marcus Metzler, Ralph Metzler, Holger Waechtler"); -MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/dvb-core/dvbdev.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,150 +0,0 @@ -/* - * dvbdev.h - * - * Copyright (C) 2000 Ralph Metzler & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Lesser Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVBDEV_H_ -#define _DVBDEV_H_ - -#include -#include -#include -#include - -#define DVB_MAJOR 212 - -#if defined(CONFIG_DVB_MAX_ADAPTERS) && CONFIG_DVB_MAX_ADAPTERS > 0 - #define DVB_MAX_ADAPTERS CONFIG_DVB_MAX_ADAPTERS -#else - #define DVB_MAX_ADAPTERS 8 -#endif - -#define DVB_UNSET (-1) - -#define DVB_DEVICE_VIDEO 0 -#define DVB_DEVICE_AUDIO 1 -#define DVB_DEVICE_SEC 2 -#define DVB_DEVICE_FRONTEND 3 -#define DVB_DEVICE_DEMUX 4 -#define DVB_DEVICE_DVR 5 -#define DVB_DEVICE_CA 6 -#define DVB_DEVICE_NET 7 -#define DVB_DEVICE_OSD 8 -#define DVB_DEVICE_CI 9 -#define DVB_DEVICE_MOD 10 -#define DVB_DEVICE_NS 11 -#define DVB_DEVICE_NSD 12 - -#define DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr) \ - static short adapter_nr[] = \ - {[0 ... (DVB_MAX_ADAPTERS - 1)] = DVB_UNSET }; \ - module_param_array(adapter_nr, short, NULL, 0444); \ - MODULE_PARM_DESC(adapter_nr, "DVB adapter numbers") - -struct dvb_frontend; - -struct dvb_adapter { - int num; - struct list_head list_head; - struct list_head device_list; - const char *name; - u8 proposed_mac [6]; - void* priv; - - struct device *device; - - struct module *module; - - int mfe_shared; /* indicates mutually exclusive frontends */ - struct dvb_device *mfe_dvbdev; /* frontend device in use */ - struct mutex mfe_lock; /* access lock for thread creation */ -}; - - -struct dvb_device { - struct list_head list_head; - const struct file_operations *fops; - struct dvb_adapter *adapter; - int type; - int minor; - u32 id; - - /* in theory, 'users' can vanish now, - but I don't want to change too much now... */ - int readers; - int writers; - int users; - - wait_queue_head_t wait_queue; - /* don't really need those !? -- FIXME: use video_usercopy */ - int (*kernel_ioctl)(struct file *file, unsigned int cmd, void *arg); - - void *priv; -}; - - -extern int dvb_register_adapter(struct dvb_adapter *adap, const char *name, - struct module *module, struct device *device, - short *adapter_nums); -extern int dvb_unregister_adapter (struct dvb_adapter *adap); - -extern int dvb_register_device (struct dvb_adapter *adap, - struct dvb_device **pdvbdev, - const struct dvb_device *template, - void *priv, - int type); - -extern void dvb_unregister_device (struct dvb_device *dvbdev); - -extern int dvb_generic_open (struct inode *inode, struct file *file); -extern int dvb_generic_release (struct inode *inode, struct file *file); -extern long dvb_generic_ioctl (struct file *file, - unsigned int cmd, unsigned long arg); - -/* we don't mess with video_usercopy() any more, -we simply define out own dvb_usercopy(), which will hopefully become -generic_usercopy() someday... */ - -extern int dvb_usercopy(struct file *file, unsigned int cmd, unsigned long arg, - int (*func)(struct file *file, unsigned int cmd, void *arg)); - -/** generic DVB attach function. */ -#ifdef CONFIG_MEDIA_ATTACH -#define dvb_attach(FUNCTION, ARGS...) ({ \ - void *__r = NULL; \ - typeof(&FUNCTION) __a = symbol_request(FUNCTION); \ - if (__a) { \ - __r = (void *) __a(ARGS); \ - if (__r == NULL) \ - symbol_put(FUNCTION); \ - } else { \ - printk(KERN_ERR "DVB: Unable to find symbol "#FUNCTION"()\n"); \ - } \ - __r; \ -}) - -#else -#define dvb_attach(FUNCTION, ARGS...) ({ \ - FUNCTION(ARGS); \ -}) - -#endif - -#endif /* #ifndef _DVBDEV_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/Makefile 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/Makefile 1970-01-01 00:00:00.000000000 +0000 @@ -1,28 +0,0 @@ -# -# Makefile for the kernel DVB frontend device drivers. -# - -EXTRA_CFLAGS += -DCONFIG_DVB_LNBP21 -EXTRA_CFLAGS += -DCONFIG_DVB_STV090x -EXTRA_CFLAGS += -DCONFIG_DVB_STV6110x -#EXTRA_CFLAGS += -DCONFIG_DVB_STV0367 -EXTRA_CFLAGS += -DCONFIG_DVB_STV0367DD -#EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212 -EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212DD -EXTRA_CFLAGS += -DCONFIG_DVB_CXD2843 -EXTRA_CFLAGS += -DDBVALS -NOSTDINC_FLAGS += -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core - -drxk-objs := drxk_hard.o -obj-$(CONFIG_DVB_DRXK) += drxk.o - -obj-$(CONFIG_DVB_LNBP21) += lnbp21.o -obj-$(CONFIG_DVB_STV090x) += stv090x.o -obj-$(CONFIG_DVB_STV6110x) += stv6110x.o -obj-$(CONFIG_DVB_CXD2099) += cxd2099.o -obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o -#obj-$(CONFIG_DVB_STV0367) += stv0367.o -obj-$(CONFIG_DVB_STV0367DD) += stv0367dd.o -#obj-$(CONFIG_DVB_TDA18212) += tda18212.o -obj-$(CONFIG_DVB_TDA18212DD) += tda18212dd.o -obj-$(CONFIG_DVB_CXD2843) += cxd2843.o diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,703 +0,0 @@ -/* - * cxd2099.c: Driver for the CXD2099AR Common Interface Controller - * - * Copyright (C) 2010-2013 Digital Devices GmbH - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cxd2099.h" - -//#define BUFFER_MODE 1 - -#define MAX_BUFFER_SIZE 248 - -static int read_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount); - -struct cxd { - struct dvb_ca_en50221 en; - - struct i2c_adapter *i2c; - struct cxd2099_cfg cfg; - - u8 regs[0x23]; - u8 lastaddress; - u8 clk_reg_f; - u8 clk_reg_b; - int mode; - int ready; - int dr; - int write_busy; - int slot_stat; - - u8 amem[1024]; - int amem_read; - - int cammode; - struct mutex lock; - - u8 rbuf[1028]; - u8 wbuf[1028]; -}; - -static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr, - u8 reg, u8 data) -{ - u8 m[2] = {reg, data}; - struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2}; - - if (i2c_transfer(adapter, &msg, 1) != 1) { - printk(KERN_ERR "Failed to write to I2C register %02x@%02x!\n", - reg, adr); - return -1; - } - return 0; -} - -static int i2c_write(struct i2c_adapter *adapter, u8 adr, - u8 *data, u8 len) -{ - struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; - - if (i2c_transfer(adapter, &msg, 1) != 1) { - printk(KERN_ERR "Failed to write to I2C!\n"); - return -1; - } - return 0; -} - -static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, - u8 reg, u8 *val) -{ - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = ®, .len = 1}, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1} }; - - if (i2c_transfer(adapter, msgs, 2) != 2) { - printk(KERN_ERR "error in i2c_read_reg\n"); - return -1; - } - return 0; -} - -static int i2c_read(struct i2c_adapter *adapter, u8 adr, - u8 reg, u8 *data, u8 n) -{ - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = ®, .len = 1}, - {.addr = adr, .flags = I2C_M_RD, - .buf = data, .len = n} }; - - if (i2c_transfer(adapter, msgs, 2) != 2) { - printk(KERN_ERR "error in i2c_read\n"); - return -1; - } - return 0; -} - -static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n) -{ - int status = 0; - - if (ci->lastaddress != adr) - status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); - if (!status) { - ci->lastaddress = adr; - status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n); - } - return status; -} - -static int read_reg(struct cxd *ci, u8 reg, u8 *val) -{ - return read_block(ci, reg, val, 1); -} - - -static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) -{ - int status; - u8 addr[3] = {2, address & 0xff, address >> 8}; - - status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); - if (!status) - status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n); - return status; -} - -static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) -{ - int status; - u8 addr[3] = {2, address & 0xff, address >> 8}; - - status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); - if (!status) { - u8 buf[256] = {3}; - memcpy(buf+1, data, n); - status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1); - } - return status; -} - -static int read_io(struct cxd *ci, u16 address, u8 *val) -{ - int status; - u8 addr[3] = {2, address & 0xff, address >> 8}; - - status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); - if (!status) - status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1); - return status; -} - -static int write_io(struct cxd *ci, u16 address, u8 val) -{ - int status; - u8 addr[3] = {2, address & 0xff, address >> 8}; - u8 buf[2] = {3, val}; - - status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); - if (!status) - status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2); - return status; -} - -#if 0 -static int read_io_data(struct cxd *ci, u8 *data, u8 n) -{ - int status; - u8 addr[3] = { 2, 0, 0 }; - - status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); - if (!status) - status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n); - return 0; -} - -static int write_io_data(struct cxd *ci, u8 *data, u8 n) -{ - int status; - u8 addr[3] = {2, 0, 0}; - - status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); - if (!status) { - u8 buf[256] = {3}; - memcpy(buf+1, data, n); - status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); - } - return 0; - -} -#endif - -static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) -{ - int status = 0; - - if (ci->lastaddress != reg) - status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg); - if (!status && reg >= 6 && reg <=8 && mask != 0xff) - status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]); - ci->lastaddress = reg; - ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; - if (!status) { - status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]); - } - if (reg == 0x20) - ci->regs[reg] &= 0x7f; - return status; -} - -static int write_reg(struct cxd *ci, u8 reg, u8 val) -{ - return write_regm(ci, reg, val, 0xff); -} - -static int write_block(struct cxd *ci, u8 adr, u8 *data, int n) -{ - int status = 0; - u8 *buf = ci->wbuf; - - if (ci->lastaddress != adr) - status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); - if (!status) { - ci->lastaddress = adr; - buf[0] = 1; - memcpy(buf + 1, data, n); - status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); - } - return status; -} - -static void set_mode(struct cxd *ci, int mode) -{ - if (mode == ci->mode) - return; - - switch (mode) { - case 0x00: /* IO mem */ - write_regm(ci, 0x06, 0x00, 0x07); - break; - case 0x01: /* ATT mem */ - write_regm(ci, 0x06, 0x02, 0x07); - break; - default: - break; - } - ci->mode = mode; -} - -static void cam_mode(struct cxd *ci, int mode) -{ - u8 dummy; - - if (mode == ci->cammode) - return; - - switch (mode) { - case 0x00: - write_regm(ci, 0x20, 0x80, 0x80); - break; - case 0x01: - if (!ci->en.read_data) - return; - ci->write_busy = 0; - printk(KERN_INFO "enable cam buffer mode\n"); - write_reg(ci, 0x0d, 0x00); - write_reg(ci, 0x0e, 0x01); - write_regm(ci, 0x08, 0x40, 0x40); - read_reg(ci, 0x12, &dummy); - write_regm(ci, 0x08, 0x80, 0x80); - break; - default: - break; - } - ci->cammode = mode; -} - - - -#define CHK_ERROR(s) if( (status = s) ) break - -static int init(struct cxd *ci) -{ - int status; - - mutex_lock(&ci->lock); - ci->mode=-1; - do { - CHK_ERROR(write_reg(ci, 0x00, 0x00)); - CHK_ERROR(write_reg(ci, 0x01, 0x00)); - CHK_ERROR(write_reg(ci, 0x02, 0x10)); - CHK_ERROR(write_reg(ci, 0x03, 0x00)); - CHK_ERROR(write_reg(ci, 0x05, 0xFF)); - CHK_ERROR(write_reg(ci, 0x06, 0x1F)); - CHK_ERROR(write_reg(ci, 0x07, 0x1F)); - CHK_ERROR(write_reg(ci, 0x08, 0x28)); - CHK_ERROR(write_reg(ci, 0x14, 0x20)); - - CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */ - - CHK_ERROR(write_reg(ci, 0x0B, 0x33)); - CHK_ERROR(write_reg(ci, 0x0C, 0x33)); - - CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F)); - CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b)); - CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F)); - CHK_ERROR(write_reg(ci, 0x17,ci->clk_reg_f)); - - if (ci->cfg.clock_mode == 2) { - u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000; // bitrate*2^13/ 72000 - - if (ci->cfg.polarity) { - CHK_ERROR(write_reg(ci, 0x09, 0x6f)); /* mode D */ - } else { - CHK_ERROR(write_reg(ci, 0x09, 0x6d)); - } - CHK_ERROR(write_reg(ci, 0x20, 0x08)); - CHK_ERROR(write_reg(ci, 0x21, (reg >> 8) & 0xff)); - CHK_ERROR(write_reg(ci, 0x22, reg & 0xff)); - } else if (ci->cfg.clock_mode == 1) { - if (ci->cfg.polarity) { - CHK_ERROR(write_reg(ci, 0x09, 0x6f)); /* mode D */ - } else { - CHK_ERROR(write_reg(ci, 0x09, 0x6d)); - } - CHK_ERROR(write_reg(ci, 0x20, 0x68)); - CHK_ERROR(write_reg(ci, 0x21, 0x00)); - CHK_ERROR(write_reg(ci, 0x22, 0x02)); - } else { - if (ci->cfg.polarity) { - CHK_ERROR(write_reg(ci, 0x09, 0x4f)); /* mode C */ - } else { - CHK_ERROR(write_reg(ci, 0x09, 0x4d)); - } - - CHK_ERROR(write_reg(ci, 0x20, 0x28)); - CHK_ERROR(write_reg(ci, 0x21, 0x00)); - CHK_ERROR(write_reg(ci, 0x22, 0x07)); - } - - CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80)); - CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02)); - CHK_ERROR(write_reg(ci, 0x01, 0x04)); - CHK_ERROR(write_reg(ci, 0x00, 0x31)); - - /* Put TS in bypass */ - CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08)); - ci->cammode=-1; - cam_mode(ci, 0); - } while(0); - mutex_unlock(&ci->lock); - - return 0; -} - -static int read_attribute_mem(struct dvb_ca_en50221 *ca, - int slot, int address) -{ - struct cxd *ci = ca->data; -#if 0 - if (ci->amem_read) { - if (address <=0 || address>1024) - return -EIO; - return ci->amem[address]; - } - - mutex_lock(&ci->lock); - write_regm(ci, 0x06, 0x00, 0x05); - read_pccard(ci, 0, &ci->amem[0], 128); - read_pccard(ci, 128, &ci->amem[0], 128); - read_pccard(ci, 256, &ci->amem[0], 128); - read_pccard(ci, 384, &ci->amem[0], 128); - write_regm(ci, 0x06, 0x05, 0x05); - mutex_unlock(&ci->lock); - return ci->amem[address]; -#else - u8 val; - mutex_lock(&ci->lock); - set_mode(ci, 1); - read_pccard(ci, address, &val, 1); - mutex_unlock(&ci->lock); - //printk("%02x:%02x\n", address,val); - return val; -#endif -} - -static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, - int address, u8 value) -{ - struct cxd *ci = ca->data; - - mutex_lock(&ci->lock); - set_mode(ci, 1); - write_pccard(ci, address, &value, 1); - mutex_unlock(&ci->lock); - return 0; -} - -static int read_cam_control(struct dvb_ca_en50221 *ca, - int slot, u8 address) -{ - struct cxd *ci = ca->data; - u8 val; - - mutex_lock(&ci->lock); - set_mode(ci, 0); - read_io(ci, address, &val); - mutex_unlock(&ci->lock); - return val; -} - -static int write_cam_control(struct dvb_ca_en50221 *ca, int slot, - u8 address, u8 value) -{ - struct cxd *ci = ca->data; - - mutex_lock(&ci->lock); - set_mode(ci, 0); - write_io(ci, address, value); - mutex_unlock(&ci->lock); - return 0; -} - -static int slot_reset(struct dvb_ca_en50221 *ca, int slot) -{ - struct cxd *ci = ca->data; - - if (ci->cammode) - read_data(ca, slot, ci->rbuf, 0); - - mutex_lock(&ci->lock); - printk("slot_reset\n"); -#if 0 - write_reg(ci, 0x00, 0x21); - write_reg(ci, 0x06, 0x1F); - write_reg(ci, 0x00, 0x31); -#else -#if 0 - write_reg(ci, 0x06, 0x1F); - write_reg(ci, 0x06, 0x2F); -#else - cam_mode(ci, 0); - write_reg(ci, 0x00, 0x21); - write_reg(ci, 0x06, 0x1F); - //msleep(300); - write_reg(ci, 0x00, 0x31); - write_regm(ci, 0x20, 0x80, 0x80); - write_reg(ci, 0x03, 0x02); - ci->ready=0; -#endif -#endif - ci->mode=-1; - { - int i; -#if 0 - u8 val; -#endif - for (i=0; i<100;i++) { - msleep(10); -#if 0 - read_reg(ci, 0x06,&val); - printk(KERN_INFO "%d:%02x\n", i, val); - if (!(val&0x10)) - break; -#else - if (ci->ready) - break; -#endif - } - } - mutex_unlock(&ci->lock); - /* msleep(500); */ - return 0; -} - -static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) -{ - struct cxd *ci = ca->data; - - printk(KERN_INFO "slot_shutdown\n"); - if (ci->cammode) - read_data(ca, slot, ci->rbuf, 0); - mutex_lock(&ci->lock); - write_reg(ci, 0x00, 0x21); - write_reg(ci, 0x06, 0x1F); - msleep(300); - - write_regm(ci, 0x09, 0x08, 0x08); - write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */ - write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */ - - ci->mode = -1; - ci->write_busy = 0; - mutex_unlock(&ci->lock); - return 0; -} - -static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) -{ - struct cxd *ci = ca->data; - - mutex_lock(&ci->lock); - write_regm(ci, 0x09, 0x00, 0x08); - set_mode(ci, 0); - cam_mode(ci, 1); - mutex_unlock(&ci->lock); - return 0; -} - - -static int campoll(struct cxd *ci) -{ - u8 istat; - - read_reg(ci, 0x04, &istat); - if (!istat) - return 0; - write_reg(ci, 0x05, istat); - - if (istat & 0x40) { - ci->dr = 1; - //printk(KERN_INFO "DR\n"); - } - if (istat & 0x20) { - //printk(KERN_INFO "WC\n"); - ci->write_busy = 0; - } - - if (istat & 2) { - u8 slotstat; - - read_reg(ci, 0x01, &slotstat); - if (!(2 & slotstat)) { - if (!ci->slot_stat) { - ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; - write_regm(ci, 0x03, 0x08, 0x08); - } - - } else { - if (ci->slot_stat) { - ci->slot_stat = 0; - write_regm(ci, 0x03, 0x00, 0x08); - printk(KERN_INFO "NO CAM\n"); - ci->ready = 0; - } - } - if (istat&8 && ci->slot_stat==DVB_CA_EN50221_POLL_CAM_PRESENT) { - ci->ready=1; - ci->slot_stat|=DVB_CA_EN50221_POLL_CAM_READY; - } - } - return 0; -} - - -static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) -{ - struct cxd *ci = ca->data; - u8 slotstat; - - mutex_lock(&ci->lock); - campoll(ci); - read_reg(ci, 0x01, &slotstat); - mutex_unlock(&ci->lock); - - return ci->slot_stat; -} - -static int read_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount) -{ - struct cxd *ci = ca->data; - u8 msb, lsb; - u16 len; - - mutex_lock(&ci->lock); - campoll(ci); - mutex_unlock(&ci->lock); - - if (!ci->dr) - return 0; - - mutex_lock(&ci->lock); - read_reg(ci, 0x0f, &msb); - read_reg(ci, 0x10, &lsb); - len = ((u16)msb<<8)|lsb; - if (len > ecount || len < 2) { - /* read it anyway or cxd may hang */ - read_block(ci, 0x12, ci->rbuf, len); - mutex_unlock(&ci->lock); - return -EIO; - } - read_block(ci, 0x12, ebuf, len); - ci->dr = 0; - mutex_unlock(&ci->lock); -#if 0 - printk(KERN_INFO "read_data %d\n", len); - { - int i; - - for (i=0; i< len; i++) - printk("%02x ", ebuf[i]); - printk("\n"); - } -#endif - return len; -} - -static int write_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount) -{ - struct cxd *ci = ca->data; - - if (ci->write_busy) - return -EAGAIN; - mutex_lock(&ci->lock); - printk("write_data %d\n", ecount); - write_reg(ci, 0x0d, ecount >> 8); - write_reg(ci, 0x0e, ecount & 0xff); - write_block(ci, 0x11, ebuf, ecount); - ci->write_busy = 1; - mutex_unlock(&ci->lock); - return ecount; -} - -static struct dvb_ca_en50221 en_templ = { - .read_attribute_mem = read_attribute_mem, - .write_attribute_mem = write_attribute_mem, - .read_cam_control = read_cam_control, - .write_cam_control = write_cam_control, - .slot_reset = slot_reset, - .slot_shutdown = slot_shutdown, - .slot_ts_enable = slot_ts_enable, - .poll_slot_status = poll_slot_status, -#ifdef BUFFER_MODE - .read_data = read_data, - .write_data = write_data, -#endif - -}; - -struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, - void *priv, - struct i2c_adapter *i2c) -{ - struct cxd *ci = 0; - u8 val; - - if (i2c_read_reg(i2c, cfg->adr, 0, &val)<0) { - printk("No CXD2099 detected at %02x\n", cfg->adr); - return 0; - } - - ci = kzalloc(sizeof(struct cxd), GFP_KERNEL); - if (!ci) - return 0; - - mutex_init(&ci->lock); - memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg)); - ci->i2c = i2c; - ci->lastaddress = 0xff; - ci->clk_reg_b = 0x4a; - ci->clk_reg_f = 0x1b; - - memcpy(&ci->en, &en_templ, sizeof(en_templ)); - ci->en.data = ci; - init(ci); - printk(KERN_INFO "Attached CXD2099AR at %02x\n", ci->cfg.adr); - return &ci->en; -} - -EXPORT_SYMBOL(cxd2099_attach); - -MODULE_DESCRIPTION("cxd2099"); -MODULE_AUTHOR("Ralph Metzler"); -MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2099.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,41 +0,0 @@ -/* - * cxd2099.h: Driver for the CXD2099AR Common Interface Controller - * - * Copyright (C) 2010-2011 Digital Devices GmbH - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef _CXD2099_H_ -#define _CXD2099_H_ - -#include - -struct cxd2099_cfg { - u32 bitrate; - u8 adr; - u8 polarity; - u8 clock_mode; -}; - -struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, - void *priv, struct i2c_adapter *i2c); - - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1649 +0,0 @@ -/* - * Driver for the Sony CXD2843ER DVB-T/T2/C/C2 demodulator. - * Also supports the CXD2837ER DVB-T/T2/C and the - * CXD2838ER ISDB-T demodulator. - * - * Copyright (C) 2013 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "cxd2843.h" - - -enum EDemodType { CXD2843, CXD2837, CXD2838 }; -enum EDemodState { Unknown, Shutdown, Sleep, ActiveT, ActiveT2, ActiveC, ActiveC2, ActiveIT }; -enum omode { OM_NONE, OM_DVBT, OM_DVBT2, OM_DVBC, OM_QAM_ITU_C, OM_DVBC2, OM_ISDBT }; - -struct cxd_state { - struct dvb_frontend frontend; - struct i2c_adapter *i2c; - struct mutex mutex; - - u8 adrt; - u8 curbankt; - - u8 adrx; - u8 curbankx; - - enum EDemodType type; - enum EDemodState state; - enum omode omode; - - u8 IF_FS; - int ContinuousClock; - int SerialMode; - u8 SerialClockFrequency; - - u32 LockTimeout; - u32 TSLockTimeout; - u32 L1PostTimeout; - u32 DataSliceID; - int FirstTimeLock; - u32 PLPNumber; - u32 last_status; - - u32 bandwidth; - u32 bw; -}; - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = - {.addr = adr, .flags = 0, .buf = data, .len = len}; - - if (i2c_transfer(adap, &msg, 1) != 1) { - printk("cxd2843: i2c_write error\n"); - return -1; - } - return 0; -} - -static int writeregs(struct cxd_state *state, u8 adr, u8 reg, u8 *regd, u16 len) -{ - u8 data[len + 1]; - - data[0] = reg; - memcpy(data + 1, regd, len); - return i2c_write(state->i2c, adr, data, len + 1); -} - -static int writereg(struct cxd_state *state, u8 adr, u8 reg, u8 dat) -{ - u8 mm[2] = {reg, dat}; - - return i2c_write(state->i2c, adr, mm, 2); -} - -static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) -{ - struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, - .buf = msg, .len = len}, - { .addr = adr, .flags = I2C_M_RD, - .buf = answ, .len = alen } }; - if (i2c_transfer(adap, msgs, 2) != 2) { - printk("cxd2843: i2c_read error\n"); - return -1; - } - return 0; -} - -static int readregs(struct cxd_state *state, u8 adr, u8 reg, u8 *val, int count) -{ - return i2c_read(state->i2c, adr, ®, 1, val, count); -} - -static int readregst_unlocked(struct cxd_state *cxd, u8 bank, u8 Address, u8 *pValue, u16 count) -{ - int status = 0; - - if (bank != 0xFF && cxd->curbankt != bank) { - status = writereg(cxd, cxd->adrt, 0, bank); - if (status < 0) { - cxd->curbankt = 0xFF; - return status; - } - cxd->curbankt = bank; - } - status = readregs(cxd, cxd->adrt, Address, pValue, count); - return status; -} - -static int readregst(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) -{ - int status; - - mutex_lock(&cxd->mutex); - status = readregst_unlocked(cxd, Bank, Address, pValue, count); - mutex_unlock(&cxd->mutex); - return status; -} - -static int readregsx_unlocked(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) -{ - int status = 0; - - if (Bank != 0xFF && cxd->curbankx != Bank) { - status = writereg(cxd, cxd->adrx, 0, Bank); - if (status < 0) { - cxd->curbankx = 0xFF; - return status; - } - cxd->curbankx = Bank; - } - status = readregs(cxd, cxd->adrx, Address, pValue, count); - return status; -} - -static int readregsx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) -{ - int status; - - mutex_lock(&cxd->mutex); - status = readregsx_unlocked(cxd, Bank, Address, pValue, count); - mutex_unlock(&cxd->mutex); - return status; -} - -static int writeregsx_unlocked(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) -{ - int status = 0; - - if (Bank != 0xFF && cxd->curbankx != Bank) { - status = writereg(cxd, cxd->adrx, 0, Bank); - if (status < 0) { - cxd->curbankx = 0xFF; - return status; - } - cxd->curbankx = Bank; - } - status = writeregs(cxd, cxd->adrx, Address, pValue, count); - return status; -} - -static int writeregsx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) -{ - int status; - - mutex_lock(&cxd->mutex); - status = writeregsx_unlocked(cxd, Bank, Address, pValue, count); - mutex_unlock(&cxd->mutex); - return status; -} - -static int writeregx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 val) -{ - return writeregsx(cxd, Bank, Address, &val, 1); -} - -static int writeregst_unlocked(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) -{ - int status = 0; - - if (Bank != 0xFF && cxd->curbankt != Bank) { - status = writereg(cxd, cxd->adrt, 0, Bank); - if (status < 0) { - cxd->curbankt = 0xFF; - return status; - } - cxd->curbankt = Bank; - } - status = writeregs(cxd, cxd->adrt, Address, pValue, count); - return status; -} - -static int writeregst(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) -{ - int status; - - mutex_lock(&cxd->mutex); - status = writeregst_unlocked(cxd, Bank, Address, pValue, count); - mutex_unlock(&cxd->mutex); - return status; -} - -static int writeregt(struct cxd_state *cxd, u8 Bank, u8 Address, u8 val) -{ - return writeregst(cxd, Bank, Address, &val, 1); -} - -static int writebitsx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 Value, u8 Mask) -{ - int status = 0; - u8 tmp; - - mutex_lock(&cxd->mutex); - status = readregsx_unlocked(cxd, Bank, Address, &tmp, 1); - if (status < 0) - return status; - tmp = (tmp & ~Mask) | Value; - status = writeregsx_unlocked(cxd, Bank, Address, &tmp, 1); - mutex_unlock(&cxd->mutex); - return status; -} - -static int writebitst(struct cxd_state *cxd, u8 Bank, u8 Address, u8 Value, u8 Mask) -{ - int status = 0; - u8 Tmp = 0x00; - - mutex_lock(&cxd->mutex); - status = readregst_unlocked(cxd, Bank, Address, &Tmp, 1); - if (status < 0) - return status; - Tmp = (Tmp & ~Mask) | Value; - status = writeregst_unlocked(cxd, Bank, Address, &Tmp, 1); - mutex_unlock(&cxd->mutex); - return status; -} - -static int FreezeRegsT(struct cxd_state *cxd) -{ - mutex_lock(&cxd->mutex); - return writereg(cxd, cxd->adrt, 1, 1); -} - -static int UnFreezeRegsT(struct cxd_state *cxd) -{ - int status = 0; - - status = writereg(cxd, cxd->adrt, 1, 0); - mutex_unlock(&cxd->mutex); - return status; -} - -static inline u32 MulDiv32(u32 a, u32 b, u32 c) -{ - u64 tmp64; - - tmp64 = (u64)a * (u64)b; - do_div(tmp64, c); - - return (u32) tmp64; -} - -static void Active_to_Sleep(struct cxd_state *state) -{ - if (state->state <= Sleep ) - return; - - writeregt(state, 0x00,0xC3,0x01); // Disable TS - writeregt(state, 0x00,0x80,0x3F); // Enable HighZ 1 - writeregt(state, 0x00,0x81,0xFF); // Enable HighZ 2 - writeregx(state, 0x00,0x18,0x01); // Disable ADC 4 - writeregt(state, 0x00,0x43,0x0A); // Disable ADC 2 // This looks broken (see enable) - writeregt(state, 0x00,0x41,0x0A); // Disable ADC 1 - writeregt(state, 0x00,0x30,0x00); // Disable ADC Clock - writeregt(state, 0x00,0x2F,0x00); // Disable RF level Monitor - writeregt(state, 0x00,0x2C,0x00); // Disable Demod Clock - state->state = Sleep; -} - -static void ActiveT2_to_Sleep(struct cxd_state *state) -{ - if (state->state <= Sleep ) - return; - - writeregt(state, 0x00,0xC3,0x01); // Disable TS - writeregt(state, 0x00,0x80,0x3F); // Enable HighZ 1 - writeregt(state, 0x00,0x81,0xFF); // Enable HighZ 2 - - writeregt(state, 0x13,0x83,0x40); // - writeregt(state, 0x13,0x86,0x21); // - writebitst(state, 0x13,0x9E,0x09,0x0F); // ... - writeregt(state, 0x13,0x9F,0xFB); // - - writeregx(state, 0x00,0x18,0x01); // Disable ADC 4 - writeregt(state, 0x00,0x43,0x0A); // Disable ADC 2 // This looks broken (see enable) - writeregt(state, 0x00,0x41,0x0A); // Disable ADC 1 - writeregt(state, 0x00,0x30,0x00); // Disable ADC Clock - writeregt(state, 0x00,0x2F,0x00); // Disable RF level Monitor - writeregt(state, 0x00,0x2C,0x00); // Disable Demod Clock - state->state = Sleep; -} - -static void ActiveC2_to_Sleep(struct cxd_state *state) -{ - if (state->state <= Sleep ) - return; - - writeregt(state, 0x00,0xC3,0x01); // Disable TS - writeregt(state, 0x00,0x80,0x3F); // Enable HighZ 1 - writeregt(state, 0x00,0x81,0xFF); // Enable HighZ 2 - - writeregt(state, 0x20,0xC2,0x11); // - writebitst(state, 0x25,0x6A,0x02,0x03); // - { - static u8 data[3] = { 0x07, 0x61, 0x36 }; - writeregst(state, 0x25,0x89,data,sizeof(data)); // - } - writebitst(state, 0x25,0xCB,0x05,0x07); // - { - static u8 data[4] = { 0x2E, 0xE0, 0x2E, 0xE0 }; - writeregst(state, 0x25,0xDC,data,sizeof(data)); // - } - writeregt(state, 0x25,0xE2,0x2F); // - writeregt(state, 0x25,0xE5,0x2F); // - writebitst(state, 0x27,0x20,0x00,0x01); // - writebitst(state, 0x27,0x35,0x00,0x01); // - writebitst(state, 0x27,0xD9,0x19,0x3F); // - writebitst(state, 0x2A,0x78,0x01,0x07); // - writeregt(state, 0x2A,0x86,0x08); // - writeregt(state, 0x2A,0x88,0x14); // - writebitst(state, 0x2B,0x2B,0x00,0x1F); // - { - u8 data[2] = { 0x75, 0x75 }; - writeregst(state, 0x2D,0x24,data,sizeof(data)); - } - - writeregx(state, 0x00,0x18,0x01); // Disable ADC 4 - writeregt(state, 0x00,0x43,0x0A); // Disable ADC 2 // This looks broken (see enable) - writeregt(state, 0x00,0x41,0x0A); // Disable ADC 1 - writeregt(state, 0x00,0x30,0x00); // Disable ADC Clock - writeregt(state, 0x00,0x2F,0x00); // Disable RF level Monitor - writeregt(state, 0x00,0x2C,0x00); // Disable Demod Clock - state->state = Sleep; -} - -static int ConfigureTS(struct cxd_state *state, enum EDemodState newDemodState) -{ - int status = 0; - - ///* OSERCKMODE OSERDUTYMODE OTSCKPERIOD OREG_CKSEL_TSIF */ - // { 1, 1, 8, 0 }, /* High Freq, full rate */ - // { 1, 1, 8, 1 }, /* Mid Freq, full rate */ - // { 1, 1, 8, 2 }, /* Low Freq, full rate */ - // { 2, 2, 16, 0 }, /* High Freq, half rate */ - // { 2, 2, 16, 1 }, /* Mid Freq, half rate */ - // { 2, 2, 16, 2 } /* Low Freq, half rate */ - - u8 OSERCKMODE = 1; - u8 OSERDUTYMODE = 1; - u8 OTSCKPERIOD = 8; - u8 OREG_CKSEL_TSIF = state->SerialClockFrequency; - - if (state->SerialClockFrequency >= 3 ) { - OSERCKMODE = 2; - OSERDUTYMODE = 2; - OTSCKPERIOD = 16; - OREG_CKSEL_TSIF = state->SerialClockFrequency - 3; - } - writebitst(state, 0x00, 0xC4, OSERCKMODE, 0x03); // OSERCKMODE - writebitst(state, 0x00, 0xD1, OSERDUTYMODE, 0x03); // OSERDUTYMODE - writeregt(state, 0x00, 0xD9, OTSCKPERIOD); // OTSCKPERIOD - writebitst(state, 0x00, 0x32, 0x00, 0x01); // Disable TS IF - writebitst(state, 0x00, 0x33, OREG_CKSEL_TSIF, 0x03); // OREG_CKSEL_TSIF - writebitst(state, 0x00, 0x32, 0x01, 0x01); // Enable TS IF - - if (newDemodState == ActiveT) - writebitst(state, 0x10, 0x66, 0x01, 0x01); - if (newDemodState == ActiveC) - writebitst(state, 0x40, 0x66, 0x01, 0x01); - - return status; -} - -static void BandSettingT(struct cxd_state *state, u32 iffreq) -{ - u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; - - switch (state->bw) { - case 8: - { - static u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; - static u8 CL_data[] = { 0x01, 0xE0 }; - static u8 NF_data[] = { 0x01, 0x02 }; - - writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x00,0x07); // System Bandwidth - writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency - writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter - break; - } - case 7: - { - static u8 TR_data[] = { 0x14, 0x80, 0x00, 0x00, 0x00 }; - static u8 CL_data[] = { 0x12, 0xF8 }; - static u8 NF_data[] = { 0x00, 0x03 }; - - writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x02,0x07); // System Bandwidth - writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency - writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter - break; - } - case 6: - { - static u8 TR_data[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA }; - static u8 CL_data[] = { 0x1F, 0xDC }; - static u8 NF_data[] = { 0x00, 0x03 }; - - writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x04,0x07); // System Bandwidth - writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency - writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter - break; - } - case 5: - { - static u8 TR_data[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 }; - static u8 CL_data[] = { 0x26, 0x3C }; - static u8 NF_data[] = { 0x00, 0x03 }; - - writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - - writebitst(state, 0x10,0xD7,0x06,0x07); // System Bandwidth - writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency - writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter - break; - } - } -} - -static void Sleep_to_ActiveT(struct cxd_state *state, u32 iffreq) -{ - printk("%s\n", __FUNCTION__); - - ConfigureTS(state, ActiveT); - - writeregx(state, 0x00,0x17,0x01); // Mode - writeregt(state, 0x00,0x2C,0x01); // Demod Clock - writeregt(state, 0x00,0x2F,0x00); // Disable RF Monitor - writeregt(state, 0x00,0x30,0x00); // Enable ADC Clock - writeregt(state, 0x00,0x41,0x1A); // Enable ADC1 - - { - u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz - //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz - writeregst(state, 0x00,0x43,data,2); // Enable ADC 2+3 - } - writeregx(state, 0x00,0x18,0x00); // Enable ADC 4 - - // -- till here identical to DVB-C (apart from mode) - - writebitst(state, 0x10,0xD2,0x0C,0x1F); // IF AGC Gain - writeregt(state, 0x11,0x6A,0x48); // BB AGC Target Level - - writebitst(state, 0x10,0xA5,0x00,0x01); // ASCOT Off - - writebitst(state, 0x18,0x36,0x40,0x07); // Pre RS Monitoring - writebitst(state, 0x18,0x30,0x01,0x01); // FEC Autorecover - writebitst(state, 0x18,0x31,0x01,0x01); // FEC Autorecover - - writebitst(state, 0x00,0xCE,0x01,0x01); // TSIF ONOPARITY - writebitst(state, 0x00,0xCF,0x01,0x01); // TSIF ONOPARITY_MANUAL_ON - - BandSettingT(state, iffreq); - - writeregt(state, 0x00,0x80,0x28); // Disable HiZ Setting 1 - writeregt(state, 0x00,0x81,0x00); // Disable HiZ Setting 2 -} - -static void BandSettingT2(struct cxd_state *state, u32 iffreq) -{ - u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; - - switch (state->bw) { - default: - case 8: - { - static u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; - writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x00,0x07); // System Bandwidth - } - break; - case 7: - { - static u8 TR_data[] = { 0x14, 0x80, 0x00, 0x00, 0x00 }; - writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x02,0x07); // System Bandwidth - } - break; - case 6: - { - static u8 TR_data[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA }; - writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x04,0x07); // System Bandwidth - } - break; - case 5: - { - static u8 TR_data[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 }; - writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x06,0x07); // System Bandwidth - } - break; - case 1: // 1.7 MHz - { - static u8 TR_data[] = { 0x58, 0xE2, 0xAF, 0xE0, 0xBC }; - writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - - writebitst(state, 0x10,0xD7,0x03,0x07); // System Bandwidth - } - break; - } -} - - -static void Sleep_to_ActiveT2(struct cxd_state *state, u32 iffreq) -{ - ConfigureTS(state, ActiveT2); - - writeregx(state, 0x00, 0x17, 0x02); // Mode - writeregt(state, 0x00, 0x2C, 0x01); // Demod Clock - writeregt(state, 0x00, 0x2F, 0x00); // Disable RF Monitor - writeregt(state, 0x00, 0x30, 0x00); // Enable ADC Clock - writeregt(state, 0x00, 0x41, 0x1A); // Enable ADC1 - - { - u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz - //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz - writeregst(state, 0x00, 0x43,data,2); // Enable ADC 2+3 - } - writeregx(state, 0x00, 0x18, 0x00); // Enable ADC 4 - - writebitst(state, 0x10, 0xD2, 0x0C, 0x1F); //IFAGC coarse gain - writeregt(state, 0x11, 0x6A, 0x50); // BB AGC Target Level - writebitst(state, 0x10, 0xA5, 0x00, 0x01); // ASCOT Off - - writeregt(state, 0x20, 0x8B, 0x3C); // SNR Good count - writebitst(state, 0x2B, 0x76, 0x20, 0x70); // Noise Gain ACQ - - writebitst(state, 0x00, 0xCE, 0x01, 0x01); // TSIF ONOPARITY - writebitst(state, 0x00, 0xCF, 0x01, 0x01); // TSIF ONOPARITY_MANUAL_ON - - writeregt(state, 0x13, 0x83, 0x10); // T2 Inital settings - writeregt(state, 0x13, 0x86, 0x34); // ... - writebitst(state, 0x13, 0x9E, 0x09, 0x0F); // ... - writeregt(state, 0x13, 0x9F, 0xD8); // ... - - BandSettingT2(state, iffreq); - - writeregt(state, 0x00, 0x80, 0x28); // Disable HiZ Setting 1 - writeregt(state, 0x00, 0x81, 0x00); // Disable HiZ Setting 2 -} - - -static void BandSettingC(struct cxd_state *state, u32 iffreq) -{ - u8 data[3]; - data[0] = (iffreq >> 16) & 0xFF; - data[1] = (iffreq >> 8) & 0xFF; - data[2] = (iffreq ) & 0xFF; - writeregst(state, 0x10, 0xB6, data, 3); // iffreq -} - -static void Sleep_to_ActiveC(struct cxd_state *state, u32 iffreq) -{ - ConfigureTS(state, ActiveC); - - writeregx(state, 0x00, 0x17, 0x04); // Mode - writeregt(state, 0x00, 0x2C, 0x01); // Demod Clock - writeregt(state, 0x00, 0x2F, 0x00); // Disable RF Monitor - writeregt(state, 0x00, 0x30, 0x00); // Enable ADC Clock - writeregt(state, 0x00, 0x41, 0x1A); // Enable ADC1 - - { - u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz - //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz - writeregst(state, 0x00, 0x43,data,2); // Enable ADC 2+3 - } - writeregx(state, 0x00, 0x18, 0x00); // Enable ADC 4 - - writebitst(state, 0x10, 0xD2, 0x09, 0x1F); // IF AGC Gain - writeregt(state, 0x11, 0x6A, 0x48); // BB AGC Target Level - writebitst(state, 0x10, 0xA5, 0x00, 0x01); // ASCOT Off - - writebitst(state, 0x40, 0xC3, 0x00, 0x04); // OREG_BNDET_EN_64 - - writebitst(state, 0x00, 0xCE, 0x01, 0x01); // TSIF ONOPARITY - writebitst(state, 0x00, 0xCF, 0x01, 0x01); // TSIF ONOPARITY_MANUAL_ON - - BandSettingC(state, iffreq); - - writeregt(state, 0x00, 0x80, 0x28); // Disable HiZ Setting 1 - writeregt(state, 0x00, 0x81, 0x00); // Disable HiZ Setting 2 -} - -static void BandSettingC2(struct cxd_state *state, u32 iffreq) -{ - u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; - - switch (state->bw) { - case 8: - { - static u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; - static u8 data[2] = { 0x11, 0x9E }; - - writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - - writebitst(state, 0x10,0xD7,0x00,0x07); // System Bandwidth - - writeregst(state, 0x50,0xEC,data,sizeof(data)); // timeout - writeregt(state, 0x50,0xEF,0x11); - writeregt(state, 0x50,0xF1,0x9E); - } - break; - case 6: - { - static u8 TR_data[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA }; - static u8 data[2] = { 0x17, 0x70 }; - - writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - writebitst(state, 0x10,0xD7,0x04,0x07); // System Bandwidth - - writeregst(state, 0x50,0xEC,data,sizeof(data)); // timeout - writeregt(state, 0x50,0xEF,0x17); - writeregt(state, 0x50,0xF1,0x70); - } - break; - } -} - -static void Sleep_to_ActiveC2(struct cxd_state *state, u32 iffreq) -{ - ConfigureTS(state, ActiveC2); - - writeregx(state, 0x00,0x17,0x05); // Mode - writeregt(state, 0x00,0x2C,0x01); // Demod Clock - writeregt(state, 0x00,0x2F,0x00); // Disable RF Monitor - writeregt(state, 0x00,0x30,0x00); // Enable ADC Clock - writeregt(state, 0x00,0x41,0x1A); // Enable ADC1 - - { - u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz - //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz - writeregst(state, 0x00,0x43,data,sizeof(data)); // Enable ADC 2+3 - } - writeregx(state, 0x00,0x18,0x00); // Enable ADC 4 - - writebitst(state, 0x10,0xD2,0x0C,0x1F); //IFAGC coarse gain - writeregt(state, 0x11,0x6A,0x50); // BB AGC Target Level - writebitst(state, 0x10,0xA5,0x00,0x01); // ASCOT Off - - writebitst(state, 0x00,0xCE,0x01,0x01); // TSIF ONOPARITY - writebitst(state, 0x00,0xCF,0x01,0x01); // TSIF ONOPARITY_MANUAL_ON - - writeregt(state, 0x20,0xC2,0x00); // - writebitst(state, 0x25,0x6A,0x00,0x03); // - { - u8 data[3] = { 0x0C, 0xD1, 0x40 }; - writeregst(state, 0x25,0x89,data,sizeof(data)); - } - writebitst(state, 0x25,0xCB,0x01,0x07); // - { - u8 data[4] = { 0x7B, 0x00, 0x7B, 0x00 }; - writeregst(state, 0x25,0xDC,data,sizeof(data)); - } - writeregt(state, 0x25,0xE2,0x30); // - writeregt(state, 0x25,0xE5,0x30); // - writebitst(state, 0x27,0x20,0x01,0x01); // - writebitst(state, 0x27,0x35,0x01,0x01); // - writebitst(state, 0x27,0xD9,0x18,0x3F); // - writebitst(state, 0x2A,0x78,0x00,0x07); // - writeregt(state, 0x2A,0x86,0x20); // - writeregt(state, 0x2A,0x88,0x32); // - writebitst(state, 0x2B,0x2B,0x10,0x1F); // - { - u8 data[2] = { 0x01, 0x01 }; - writeregst(state, 0x2D,0x24,data,sizeof(data)); - } - - BandSettingC2(state, iffreq); - - writeregt(state, 0x00,0x80,0x28); // Disable HiZ Setting 1 - writeregt(state, 0x00,0x81,0x00); // Disable HiZ Setting 2 -} - - -static void BandSettingIT(struct cxd_state *state, u32 iffreq) -{ - u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; - - switch (state->bw) { - default: - case 8: - { - static u8 TR_data[] = { 0x0F, 0x22, 0x80, 0x00, 0x00 }; // 20.5/41 - static u8 CL_data[] = { 0x15, 0xA8 }; - - // static u8 TR_data[] = { 0x11, 0xB8, 0x00, 0x00, 0x00 }; // 24 - writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - - writeregt(state, 0x10,0xD7,0x00); // System Bandwidth - //static u8 CL_data[] = { 0x13, 0xFC }; - writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency - } - break; - case 7: - { - static u8 TR_data[] = { 0x11, 0x4c, 0x00, 0x00, 0x00 }; - static u8 CL_data[] = { 0x1B, 0x5D }; - - //static u8 TR_data[] = { 0x14, 0x40, 0x00, 0x00, 0x00 }; - writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - - writeregt(state, 0x10,0xD7,0x02); // System Bandwidth - //static u8 CL_data[] = { 0x1A, 0xFA }; - writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency - } - break; - case 6: - { - static u8 TR_data[] = { 0x14, 0x2E, 0x00, 0x00, 0x00 }; - static u8 CL_data[] = { 0x1F, 0xEC }; - //static u8 TR_data[] = { 0x17, 0xA0, 0x00, 0x00, 0x00 }; - //static u8 CL_data[] = { 0x1F, 0x79 }; - - writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery - // Add EQ Optimisation for tuner here - writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq - - writeregt(state, 0x10,0xD7,0x04); // System Bandwidth - writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data)); // core latency - } - break; - } -} - -static void Sleep_to_ActiveIT(struct cxd_state *state, u32 iffreq) -{ - static u8 data2[3] = { 0xB9,0xBA,0x63 }; // 20.5/41 MHz - //static u8 data2[3] = { 0xB7,0x1B,0x00 }; // 24 MHz - static u8 TSIF_data[2] = { 0x61,0x60 } ; // 20.5/41 MHz - //static u8 TSIF_data[2] = { 0x60,0x00 } ; // 24 MHz - - printk("%s\n", __FUNCTION__); - - ConfigureTS(state, ActiveIT); - - // writeregx(state, 0x00,0x17,0x01); // 2838 has only one Mode - writeregt(state, 0x00,0x2C,0x01); // Demod Clock - writeregt(state, 0x00,0x2F,0x00); // Disable RF Monitor - writeregt(state, 0x00,0x30,0x00); // Enable ADC Clock - writeregt(state, 0x00,0x41,0x1A); // Enable ADC1 - - { - u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz, 24 MHz - //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz - writeregst(state, 0x00,0x43,data,2); // Enable ADC 2+3 - } - writeregx(state, 0x00,0x18,0x00); // Enable ADC 4 - - writeregst(state, 0x60,0xA8,data2,sizeof(data2)); - - writeregst(state, 0x10,0xBF,TSIF_data,sizeof(TSIF_data)); - - writeregt(state, 0x10,0xE2,0xCE); // OREG_PNC_DISABLE - writebitst(state, 0x10,0xA5,0x00,0x01); // ASCOT Off - - BandSettingIT(state, iffreq); - - writeregt(state, 0x00,0x80,0x28); // Disable HiZ Setting 1 - writeregt(state, 0x00,0x81,0x00); // Disable HiZ Setting 2 -} - -static void T2_SetParameters(struct cxd_state *state) -{ - u8 Profile = 0x01; // Profile Base - u8 notT2time = 12; // early unlock detection time - - //u8 Profile = 0x05; // Lite - //u8 notT2time = 40; - - //u8 Profile = 0x00; // Any - //u8 notT2time = 40; - - - if (state->PLPNumber != 0xffffffff) { - writeregt(state, 0x23, 0xAF, state->PLPNumber); - writeregt(state, 0x23, 0xAD, 0x01); - } else { - writeregt(state, 0x23, 0xAD, 0x00); - } - - writebitst(state, 0x2E, 0x10, Profile, 0x07); - writeregt(state, 0x2B, 0x19, notT2time); -} - -static void C2_ReleasePreset(struct cxd_state *state) -{ - { - static u8 data[2] = { 0x02, 0x80}; - writeregst(state, 0x27,0xF4,data,sizeof(data)); - } - writebitst(state, 0x27,0x51,0x40,0xF0); - writebitst(state, 0x27,0x73,0x07,0x0F); - writebitst(state, 0x27,0x74,0x19,0x3F); - writebitst(state, 0x27,0x75,0x19,0x3F); - writebitst(state, 0x27,0x76,0x19,0x3F); - if (state->bw == 6 ) { - static u8 data[5] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA}; - writeregst(state, 0x20,0x9F,data,sizeof(data)); - } else { - static u8 data[5] = { 0x11, 0xF0, 0x00, 0x00, 0x00}; - writeregst(state, 0x20,0x9F,data,sizeof(data)); - } - writebitst(state, 0x27,0xC9,0x07,0x07); - writebitst(state, 0x20,0xC2,0x11,0x33); - { - static u8 data[10] = { 0x16, 0xF0, 0x2B, 0xD8, 0x16, 0x16, 0xF0, 0x2C, 0xD8, 0x16 }; - writeregst(state, 0x2A,0x20,data,sizeof(data)); - } - { - static u8 data[4] = { 0x00, 0x00, 0x00, 0x00 }; - writeregst(state, 0x50,0x6B,data,sizeof(data)); - } - writebitst(state, 0x50,0x6F,0x00,0x40); // Disable Preset -} - -static void C2_DemodSetting2(struct cxd_state *state) -{ - u8 data[6]; - u32 TunePosition = state->frontend.dtv_property_cache.frequency / 1000; - - if (state->bw == 6) { - TunePosition = ((TunePosition * 1792) / 3) / 1000; - } else { - TunePosition = (TunePosition * 448) / 1000; - } - TunePosition = ((TunePosition + 6) / 12) * 12; - - printk("TunePosition = %u\n", TunePosition); - - data[0] = ( (TunePosition >> 16) & 0xFF ); - data[1] = ( (TunePosition >> 8) & 0xFF ); - data[2] = ( (TunePosition ) & 0xFF ); - data[3] = 0x02; - data[4] = (state->DataSliceID & 0xFF); - data[5] = (state->PLPNumber & 0xFF); - writeregst(state, 0x50, 0x7A, data, sizeof(data)); - writebitst(state, 0x50, 0x87, 0x01, 0x01); /* Preset Clear */ -} - -static void Stop(struct cxd_state *state) -{ - writeregt(state, 0x00,0xC3,0x01); /* Disable TS */ -} - -static void ShutDown(struct cxd_state *state) -{ - switch (state->state) { - case ActiveT2: - ActiveT2_to_Sleep(state); - break; - case ActiveC2: - ActiveC2_to_Sleep(state); - break; - default: - Active_to_Sleep(state); - break; - } -} - -static int gate_ctrl(struct dvb_frontend *fe, int enable) -{ - struct cxd_state *state = fe->demodulator_priv; - - return writebitsx(state, 0xFF, 0x08, enable ? 0x01 : 0x00, 0x01); -} - -static void release(struct dvb_frontend* fe) -{ - struct cxd_state *state = fe->demodulator_priv; - - Stop(state); - ShutDown(state); - kfree(state); -} - -static int Start(struct cxd_state *state, u32 IntermediateFrequency) -{ - enum EDemodState newDemodState = Unknown; - u32 iffreq; - - if (state->state < Sleep ) { - return -EINVAL; - } - - iffreq = MulDiv32(IntermediateFrequency, 16777216, 41000000); - - switch(state->omode) { - case OM_DVBT: - if (state->type == CXD2838 ) - return -EINVAL; - newDemodState = ActiveT; - break; - case OM_DVBT2: - if (state->type == CXD2838 ) - return -EINVAL; - newDemodState = ActiveT2; - break; - case OM_DVBC: - case OM_QAM_ITU_C: - if (state->type == CXD2838 ) - return -EINVAL; - newDemodState = ActiveC; - break; - case OM_DVBC2: - if (state->type != CXD2843 ) - return -EINVAL; - newDemodState = ActiveC2; - break; - case OM_ISDBT: - if (state->type != CXD2838 ) - return -EINVAL; - newDemodState = ActiveIT; - break; - default: - return -EINVAL; - } - - state->LockTimeout = 0; - state->TSLockTimeout = 0; - state->L1PostTimeout = 0; - state->FirstTimeLock = 1; - - if (state->state == newDemodState ) { - writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS Output */ - switch (newDemodState) { - case ActiveT: - writeregt(state, 0x10,0x67, 0x00); /* Stick with HP ( 0x01 = LP ) */ - BandSettingT(state, iffreq); - break; - case ActiveT2: - T2_SetParameters(state); - BandSettingT2(state, iffreq); - break; - case ActiveC: - BandSettingC(state, iffreq); - break; - case ActiveC2: - BandSettingC2(state, iffreq); - C2_ReleasePreset(state); - C2_DemodSetting2(state); - break; - case ActiveIT: - BandSettingIT(state, iffreq); - break; - default: - break; - } - } else { - if (state->state > Sleep ) { - switch (state->state) { - case ActiveT2: - ActiveT2_to_Sleep(state); - break; - case ActiveC2: - ActiveC2_to_Sleep(state); - break; - default: - Active_to_Sleep(state); - break; - } - } - switch (newDemodState) { - case ActiveT: - writeregt(state, 0x10,0x67, 0x00); // Stick with HP ( 0x01 = LP ) - Sleep_to_ActiveT(state, iffreq); - break; - case ActiveT2: - T2_SetParameters(state); - Sleep_to_ActiveT2(state, iffreq); - break; - case ActiveC: - Sleep_to_ActiveC(state, iffreq); - break; - case ActiveC2: - Sleep_to_ActiveC2(state, iffreq); - C2_ReleasePreset(state); - C2_DemodSetting2(state); - break; - case ActiveIT: - Sleep_to_ActiveIT(state, iffreq); - break; - default: - break; - } - } - state->state = newDemodState; - writeregt(state, 0x00, 0xFE, 0x01); // SW Reset - writeregt(state, 0x00, 0xC3, 0x00); // Enable TS Output - - return 0; -} - -static int set_parameters(struct dvb_frontend *fe) -{ - int stat; - struct cxd_state *state = fe->demodulator_priv; - u32 IF; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBC_ANNEX_A: - state->omode = OM_DVBC; - break; - case SYS_DVBC2: - state->omode = OM_DVBC2; - break; - case SYS_DVBT: - state->omode = OM_DVBT; - break; - case SYS_DVBT2: - state->omode = OM_DVBT2; - break; - case SYS_ISDBT: - state->omode = OM_ISDBT; - break; - default: - return -EINVAL; - } - if (fe->ops.tuner_ops.set_params) - fe->ops.tuner_ops.set_params(fe); - state->bandwidth = fe->dtv_property_cache.bandwidth_hz; - state->bw = (fe->dtv_property_cache.bandwidth_hz + 999999) / 1000000; - state->DataSliceID = 0;//fe->dtv_property_cache.slice_id; - state->PLPNumber = fe->dtv_property_cache.stream_id; - fe->ops.tuner_ops.get_if_frequency(fe, &IF); - stat = Start(state, IF); - return stat; -} - - -static void init(struct cxd_state *state) -{ - u8 data[2] = {0x00, 0x00}; // 20.5 MHz - - state->omode = OM_NONE; - state->state = Unknown; - - writeregx(state, 0xFF, 0x02, 0x00); - msleep(4); - writeregx(state, 0x00, 0x10, 0x01); - - writeregsx(state, 0x00, 0x13, data, 2); - writeregx(state, 0x00, 0x10, 0x00); - msleep(2); - state->curbankx = 0xFF; - state->curbankt = 0xFF; - - writeregt(state, 0x00, 0x43, 0x0A); - writeregt(state, 0x00, 0x41, 0x0A); - if (state->type == CXD2838) - writeregt(state, 0x60, 0x5A, 0x00); - - writebitst(state, 0x10, 0xCB, 0x00, 0x40); - writeregt(state, 0x10, 0xCD, state->IF_FS); - - writebitst(state, 0x00, 0xC4, 0x80, 0x98); - writebitst(state, 0x00, 0xC5, 0x00, 0x07); - writebitst(state, 0x00, 0xCB, 0x00, 0x01); - writebitst(state, 0x00, 0xC6, 0x00, 0x1D); - writebitst(state, 0x00, 0xC8, 0x00, 0x1D); - writebitst(state, 0x00, 0xC9, 0x00, 0x1D); - writebitst(state, 0x00, 0x83, 0x00, 0x07); - writeregt(state, 0x00, 0x84, 0x00); - writebitst(state, 0x00, 0xD3, (state->type == CXD2838) ? 0x01 : 0x00, 0x01); - writebitst(state, 0x00, 0xDE, 0x00, 0x01); - - state->state = Sleep; -} - - -static void init_state(struct cxd_state *state, struct cxd2843_cfg *cfg) -{ - state->adrt = cfg->adr; - state->adrx = cfg->adr + 0x02; - state->curbankt = 0xff; - state->curbankx = 0xff; - - mutex_init(&state->mutex); - - state->SerialMode = 1; - state->ContinuousClock = 1; - state->SerialClockFrequency = - (cfg->ts_clock >= 1 && cfg->ts_clock <= 5) ? cfg->ts_clock : 1; // 1 = fastest (82 MBit/s), 5 = slowest - state->SerialClockFrequency = 1; - state->IF_FS = 0x50; // IF Fullscale 0x50 = 1.4V, 0x39 = 1V, 0x28 = 0.7V -} - -static int get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) -{ - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: - //return c_get_tune_settings(fe, sets); - default: - /* DVB-T: Use info.frequency_stepsize. */ - return -EINVAL; - } -} - -static int read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct cxd_state *state = fe->demodulator_priv; - u8 rdata; - - *status=0; - switch (state->state) { - case ActiveC: - readregst(state, 0x40, 0x88, &rdata, 1); - if (rdata & 0x02) - break; - if (rdata & 0x01) { - *status |= 0x07; - readregst(state, 0x40, 0x10, &rdata, 1); - if (rdata & 0x20) - *status |= 0x1f; - } - break; - case ActiveT: - readregst(state, 0x10, 0x10, &rdata, 1) ; - if (rdata & 0x10) - break; - if ((rdata & 0x07) == 0x06) { - *status |= 0x07; - if (rdata & 0x20) - *status |= 0x1f; - } - break; - case ActiveT2: - readregst(state, 0x20, 0x10, &rdata, 1); - if (rdata & 0x10) - break; - if ((rdata & 0x07) == 0x06) { - *status |= 0x07; - if (rdata & 0x20) - *status |= 0x08; - } - if (*status & 0x08) { - readregst(state, 0x22, 0x12, &rdata, 1); - if (rdata & 0x01) - *status |= 0x10; - } - break; - case ActiveC2: - readregst(state, 0x20, 0x10, &rdata, 1); - if (rdata & 0x10) - break; - if ((rdata & 0x07) == 0x06) { - *status |= 0x07; - if (rdata & 0x20) - *status |= 0x18; - } - if ((*status & 0x10) && state->FirstTimeLock) { - u8 data; - - // Change1stTrial - readregst(state, 0x28, 0xE6, &rdata, 1); - data = rdata & 1; - readregst(state, 0x50, 0x15, &rdata, 1); - data |= ((rdata & 0x18) >> 2); - //writebitst(state, 0x50,0x6F,rdata,0x07); - state->FirstTimeLock = 0; - } - break; - case ActiveIT: - readregst(state, 0x60, 0x10, &rdata, 1); - if (rdata & 0x10) - break; - if (rdata & 0x02) { - *status |= 0x07; - if (rdata & 0x01) - *status |= 0x18; - } - break; - default: - break; - } - state->last_status = *status; - return 0; -} - -static int read_ber(struct dvb_frontend *fe, u32 *ber) -{ - //struct cxd_state *state = fe->demodulator_priv; - - *ber = 0; - return 0; -} - -static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - if (fe->ops.tuner_ops.get_rf_strength) - fe->ops.tuner_ops.get_rf_strength(fe, strength); - else - *strength = 0; - return 0; -} - -static s32 Log10x100(u32 x) -{ - static u32 LookupTable[100] = { - 101157945, 103514217, 105925373, 108392691, 110917482, - 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 - 127350308, 130316678, 133352143, 136458314, 139636836, - 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 - 160324539, 164058977, 167880402, 171790839, 175792361, - 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 - 201836636, 206538016, 211348904, 216271852, 221309471, - 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 - 254097271, 260015956, 266072506, 272270131, 278612117, - 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 - 319889511, 327340695, 334965439, 342767787, 350751874, - 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 - 402717034, 412097519, 421696503, 431519077, 441570447, - 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 - 506990708, 518800039, 530884444, 543250331, 555904257, - 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 - 638263486, 653130553, 668343918, 683911647, 699841996, - 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 - 803526122, 822242650, 841395142, 860993752, 881048873, - 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 - }; - s32 y; - int i; - - if (x == 0) - return 0; - y = 800; - if (x >= 1000000000) { - x /= 10; - y += 100; - } - - while (x < 100000000) { - x *= 10; - y -= 100; - } - i = 0; - while (i < 100 && x > LookupTable[i]) - i += 1; - y += i; - return y; -} - -#if 0 -static void GetPLPIds(struct cxd_state *state, u32 nValues, u8 *Values, u32 *Returned) -{ - u8 nPids = 0; - - *Returned = 0; - if (state->state != ActiveT2 ) - return; - if (state->last_status != 0x1f) - return; - - FreezeRegsT(state); - readregst_unlocked(state, 0x22, 0x7F, &nPids, 1); - - Values[0] = nPids; - if( nPids >= nValues ) - nPids = nValues - 1; - - readregst_unlocked(state, 0x22, 0x80, &Values[1], nPids > 128 ? 128 : nPids); - - if( nPids > 128 ) - readregst_unlocked(state, 0x23, 0x10, &Values[129], nPids - 128); - - *Returned = nPids + 1; - - UnFreezeRegsT(state); -} -#endif - -static void GetSignalToNoiseIT(struct cxd_state *state, u32 *SignalToNoise) -{ - u8 Data[2]; - u32 reg; - - FreezeRegsT(state); - readregst_unlocked(state, 0x60, 0x28, Data, sizeof(Data)); - UnFreezeRegsT(state); - - reg = (Data[0] << 8) | Data[1]; - if (reg > 51441) - reg = 51441; - - if (state->bw == 8) { - if (reg > 1143) - reg = 1143; - *SignalToNoise = (Log10x100(reg) - Log10x100(1200 - reg)) + 220; - } else - *SignalToNoise = Log10x100(reg) - 90; -} - -static void GetSignalToNoiseC2(struct cxd_state *state, u32 *SignalToNoise) -{ - u8 Data[2]; - u32 reg; - - FreezeRegsT(state); - readregst_unlocked(state, 0x20, 0x28, Data, sizeof(Data)); - UnFreezeRegsT(state); - - reg = (Data[0] << 8) | Data[1]; - if (reg > 51441) - reg = 51441; - - *SignalToNoise = (Log10x100(reg) - Log10x100(55000 - reg)) + 384; -} - - -static void GetSignalToNoiseT2(struct cxd_state *state, u32 *SignalToNoise) -{ - u8 Data[2]; - u32 reg; - - FreezeRegsT(state); - readregst_unlocked(state, 0x20, 0x28, Data, sizeof(Data)); - UnFreezeRegsT(state); - - reg = (Data[0] << 8) | Data[1]; - if (reg > 10876) - reg = 10876; - - *SignalToNoise = (Log10x100(reg) - Log10x100(12600 - reg)) + 320; -} - -static void GetSignalToNoiseT(struct cxd_state *state, u32 *SignalToNoise) -{ - u8 Data[2]; - u32 reg; - - FreezeRegsT(state); - readregst_unlocked(state, 0x10, 0x28, Data, sizeof(Data)); - UnFreezeRegsT(state); - - reg = (Data[0] << 8) | Data[1]; - if (reg > 4996) - reg = 4996; - - *SignalToNoise = (Log10x100(reg) - Log10x100(5350 - reg)) + 285; -} - -static void GetSignalToNoiseC(struct cxd_state *state, u32 *SignalToNoise) -{ - u8 Data[2]; - u8 Constellation = 0; - u32 reg; - - *SignalToNoise = 0; - - FreezeRegsT(state); - readregst_unlocked(state, 0x40, 0x19, &Constellation, 1); - readregst_unlocked(state, 0x40, 0x4C, Data, sizeof(Data)); - UnFreezeRegsT(state); - - reg = ((u32)(Data[0] & 0x1F) << 8) | (Data[1]); - if (reg == 0) - return; - - switch (Constellation & 0x07) { - case 0: // QAM 16 - case 2: // QAM 64 - case 4: // QAM 256 - if (reg < 126) - reg = 126; - *SignalToNoise = ((439 - Log10x100(reg)) * 2134 + 500) / 1000; - break; - case 1: // QAM 32 - case 3: // QAM 128 - if (reg < 69) - reg = 69; - *SignalToNoise = ((432 - Log10x100(reg)) * 2015 + 500) / 1000; - break; - } -} - -static int read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct cxd_state *state = fe->demodulator_priv; - u32 SNR = 0; - - *snr = 0; - if (state->last_status != 0x1f) - return 0; - - switch (state->state) { - case ActiveC: - GetSignalToNoiseC(state, &SNR); - break; - case ActiveC2: - GetSignalToNoiseC2(state, &SNR); - break; - case ActiveT: - GetSignalToNoiseT(state, &SNR); - break; - case ActiveT2: - GetSignalToNoiseT2(state, &SNR); - break; - case ActiveIT: - GetSignalToNoiseIT(state, &SNR); - break; - default: - break; - } - *snr = SNR; - return 0; -} - -static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - *ucblocks = 0; - return 0; -} - -static struct dvb_frontend_ops common_ops_2843 = { - .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2, SYS_DVBC2 }, - .info = { - .name = "CXD2843 DVB-C/C2 DVB-T/T2", - .frequency_stepsize = 166667, /* DVB-T only */ - .frequency_min = 47000000, /* DVB-T: 47125000 */ - .frequency_max = 865000000, /* DVB-C: 862000000 */ - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = /* DVB-C */ - FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | - FE_CAN_FEC_AUTO | - /* DVB-T */ - FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | - FE_CAN_RECOVER | FE_CAN_MUTE_TS - }, - .release = release, - .i2c_gate_ctrl = gate_ctrl, - .set_frontend = set_parameters, - - .get_tune_settings = get_tune_settings, - .read_status = read_status, - .read_ber = read_ber, - .read_signal_strength = read_signal_strength, - .read_snr = read_snr, - .read_ucblocks = read_ucblocks, -}; - -static struct dvb_frontend_ops common_ops_2837 = { - .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2}, - .info = { - .name = "CXD2837 DVB-C DVB-T/T2", - .frequency_stepsize = 166667, /* DVB-T only */ - .frequency_min = 47000000, /* DVB-T: 47125000 */ - .frequency_max = 865000000, /* DVB-C: 862000000 */ - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = /* DVB-C */ - FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | - FE_CAN_FEC_AUTO | - /* DVB-T */ - FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | - FE_CAN_RECOVER | FE_CAN_MUTE_TS - }, - .release = release, - .i2c_gate_ctrl = gate_ctrl, - .set_frontend = set_parameters, - - .get_tune_settings = get_tune_settings, - .read_status = read_status, - .read_ber = read_ber, - .read_signal_strength = read_signal_strength, - .read_snr = read_snr, - .read_ucblocks = read_ucblocks, -}; - -static struct dvb_frontend_ops common_ops_2838 = { - .delsys = { SYS_ISDBT }, - .info = { - .name = "CXD2838 ISDB-T", - .frequency_stepsize = 166667, - .frequency_min = 47000000, - .frequency_max = 865000000, - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | - FE_CAN_RECOVER | FE_CAN_MUTE_TS - }, - .release = release, - .i2c_gate_ctrl = gate_ctrl, - .set_frontend = set_parameters, - - .get_tune_settings = get_tune_settings, - .read_status = read_status, - .read_ber = read_ber, - .read_signal_strength = read_signal_strength, - .read_snr = read_snr, - .read_ucblocks = read_ucblocks, -}; - -static int probe(struct cxd_state *state) -{ - u8 ChipID = 0x00; - int status; - - status = readregst(state, 0x00, 0xFD, &ChipID, 1); - - if (status) { - status = readregsx(state, 0x00, 0xFD, &ChipID, 1); - } - if (status) - return status; - - //printk("ChipID = %02X\n", ChipID); - switch (ChipID) { - case 0xa4: - state->type = CXD2843; - memcpy(&state->frontend.ops, &common_ops_2843, sizeof(struct dvb_frontend_ops)); - break; - case 0xb1: - state->type = CXD2837; - memcpy(&state->frontend.ops, &common_ops_2837, sizeof(struct dvb_frontend_ops)); - break; - case 0xb0: - state->type = CXD2838; - memcpy(&state->frontend.ops, &common_ops_2838, sizeof(struct dvb_frontend_ops)); - break; - default: - return -1; - } - state->frontend.demodulator_priv = state; - return 0; -} - -struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, struct cxd2843_cfg *cfg) -{ - struct cxd_state *state = NULL; - - state = kzalloc(sizeof(struct cxd_state), GFP_KERNEL); - if (!state) - return NULL; - - state->i2c = i2c; - init_state(state, cfg); - if (probe(state) == 0) { - init(state); - return &state->frontend; - } - printk("cxd2843: not found\n"); - kfree(state); - return NULL; -} - -MODULE_DESCRIPTION("CXD2843/37/38 driver"); -MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(cxd2843_attach); - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/cxd2843.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,14 +0,0 @@ -#ifndef _CXD2843_H_ -#define _CXD2843_H_ - -#include -#include - -struct cxd2843_cfg { - u8 adr; - u32 ts_clock; -}; - -extern struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, struct cxd2843_cfg *cfg); - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,10 +0,0 @@ -#ifndef _DRXK_H_ -#define _DRXK_H_ - -#include -#include - -extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, - u8 adr, - struct dvb_frontend **fe_t); -#endif Binary files /tmp/E8GjFYYGeu/dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_a3.mc and /tmp/G28E6P4D0c/dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_a3.mc differ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,5097 +0,0 @@ -/* - * drxk_hard: DRX-K DVB-C/T demodulator driver - * - * Copyright (C) 2010-2011 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "drxk.h" -#include "drxk_hard.h" - -static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); -static int PowerDownQAM(struct drxk_state *state); -static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); -static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode); -static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, - s32 tunerFreqOffset); -static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); -static int DVBTStart(struct drxk_state *state); -static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, - s32 tunerFreqOffset); -static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); -static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); -static int SwitchAntennaToQAM(struct drxk_state *state); -static int SwitchAntennaToDVBT(struct drxk_state *state); - -static bool IsDVBT(struct drxk_state *state) -{ - return state->m_OperationMode == OM_DVBT; -} - -static bool IsQAM(struct drxk_state *state) -{ - return state->m_OperationMode == OM_QAM_ITU_A || - state->m_OperationMode == OM_QAM_ITU_B || - state->m_OperationMode == OM_QAM_ITU_C; -} - -bool IsA1WithPatchCode(struct drxk_state *state) -{ - return state->m_DRXK_A1_PATCH_CODE; -} - -bool IsA1WithRomCode(struct drxk_state *state) -{ - return state->m_DRXK_A1_ROM_CODE; -} - -#define NOA1ROM 0 - -#ifndef CHK_ERROR - #define CHK_ERROR(s) if ((status = s) < 0) break -#endif - -#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) -#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) - -#define DEFAULT_MER_83 165 -#define DEFAULT_MER_93 250 - -#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH -#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) -#endif - -#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH -#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) -#endif - -#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH -#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06) -#endif - -#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 -#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 - -#ifndef DRXK_KI_RAGC_ATV -#define DRXK_KI_RAGC_ATV 4 -#endif -#ifndef DRXK_KI_IAGC_ATV -#define DRXK_KI_IAGC_ATV 6 -#endif -#ifndef DRXK_KI_DAGC_ATV -#define DRXK_KI_DAGC_ATV 7 -#endif - -#ifndef DRXK_KI_RAGC_QAM -#define DRXK_KI_RAGC_QAM 3 -#endif -#ifndef DRXK_KI_IAGC_QAM -#define DRXK_KI_IAGC_QAM 4 -#endif -#ifndef DRXK_KI_DAGC_QAM -#define DRXK_KI_DAGC_QAM 7 -#endif -#ifndef DRXK_KI_RAGC_DVBT -#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) -#endif -#ifndef DRXK_KI_IAGC_DVBT -#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) -#endif -#ifndef DRXK_KI_DAGC_DVBT -#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) -#endif - -#ifndef DRXK_AGC_DAC_OFFSET -#define DRXK_AGC_DAC_OFFSET (0x800) -#endif - -#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ -#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) -#endif - -#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ -#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) -#endif - -#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ -#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) -#endif - -#ifndef DRXK_QAM_SYMBOLRATE_MAX -#define DRXK_QAM_SYMBOLRATE_MAX (7233000) -#endif - -#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 -#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 -#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 -#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 -#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 -#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 -#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 -#define DRXK_BL_ROM_OFFSET_UCODE 0 - -#define DRXK_BLC_TIMEOUT 100 - -#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 -#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 - -#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 - -#ifndef DRXK_OFDM_NE_NOTCH_WIDTH -#define DRXK_OFDM_NE_NOTCH_WIDTH (4) -#endif - -#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) -#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) -#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) -#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) -#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) - -static inline u32 MulDiv32(u32 a, u32 b, u32 c) -{ - u64 tmp64; - - tmp64 = (u64)a * (u64)b; - do_div(tmp64, c); - - return (u32) tmp64; -} - -inline u32 Frac28a(u32 a, u32 c) -{ - int i = 0; - u32 Q1 = 0; - u32 R0 = 0; - - R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ - Q1 = a / c; /* integer part, only the 4 least significant bits - will be visible in the result */ - - /* division using radix 16, 7 nibbles in the result */ - for (i = 0; i < 7; i++) { - Q1 = (Q1 << 4) | (R0 / c); - R0 = (R0 % c) << 4; - } - /* rounding */ - if ((R0 >> 3) >= c) - Q1++; - - return Q1; -} - -static u32 Log10Times100(u32 x) -{ - static const u8 scale = 15; - static const u8 indexWidth = 5; - u8 i = 0; - u32 y = 0; - u32 d = 0; - u32 k = 0; - u32 r = 0; - /* - log2lut[n] = (1< 0; k--) { - if (x & (((u32)1) << scale)) - break; - x <<= 1; - } - } else { - for (k = scale; k < 31 ; k++) { - if ((x & (((u32)(-1)) << (scale+1))) == 0) - break; - x >>= 1; - } - } - /* - Now x has binary point between bit[scale] and bit[scale-1] - and 1.0 <= x < 2.0 */ - - /* correction for divison: log(x) = log(x/y)+log(y) */ - y = k * ((((u32)1) << scale) * 200); - - /* remove integer part */ - x &= ((((u32)1) << scale)-1); - /* get index */ - i = (u8) (x >> (scale - indexWidth)); - /* compute delta (x - a) */ - d = x & ((((u32)1) << (scale - indexWidth)) - 1); - /* compute log, multiplication (d* (..)) must be within range ! */ - y += log2lut[i] + - ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); - /* Conver to log10() */ - y /= 108853; /* (log2(10) << scale) */ - r = (y >> 1); - /* rounding */ - if (y & ((u32)1)) - r++; - return (r); -} - -/****************************************************************************/ -/* I2C **********************************************************************/ -/****************************************************************************/ - -static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) -{ - struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 }}; - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -} - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = - {.addr = adr, .flags = 0, .buf = data, .len = len}; - - if (i2c_transfer(adap, &msg, 1) != 1) { - printk("i2c_write error\n"); - return -1; - } - return 0; -} - -static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) -{ - struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, - .buf = msg, .len = len}, - { .addr = adr, .flags = I2C_M_RD, - .buf = answ, .len = alen } }; - if (i2c_transfer(adap, msgs, 2) != 2) { - printk("i2c_read error\n"); - return -1; - } - return 0; -} - -static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) -{ - u8 adr=state->demod_address, mm1[4], mm2[2], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm1[0] = (((reg << 1) & 0xFF) | 0x01); - mm1[1] = ((reg >> 16) & 0xFF); - mm1[2] = ((reg >> 24) & 0xFF) | flags; - mm1[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm1[0] = ((reg << 1) & 0xFF); - mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) - return -1; - if (data) - *data = mm2[0] | (mm2[1] << 8); - return 0; -} - -static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) -{ - return Read16(state, reg, data, 0); -} - -static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) -{ - u8 adr = state->demod_address, mm1[4], mm2[4], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm1[0] = (((reg << 1) & 0xFF) | 0x01); - mm1[1] = ((reg >> 16) & 0xFF); - mm1[2] = ((reg >> 24) & 0xFF) | flags; - mm1[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm1[0] = ((reg << 1) & 0xFF); - mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) - return -1; - if (data) - *data = mm2[0] | (mm2[1] << 8) | - (mm2[2] << 16) | (mm2[3] << 24); - return 0; -} - -static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) -{ - u8 adr = state->demod_address, mm[6], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm[0] = (((reg << 1) & 0xFF) | 0x01); - mm[1] = ((reg >> 16) & 0xFF); - mm[2] = ((reg >> 24) & 0xFF) | flags; - mm[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm[0] = ((reg << 1) & 0xFF); - mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - mm[len] = data & 0xff; - mm[len+1] = (data >>8) & 0xff; - if (i2c_write(state->i2c, adr, mm, len + 2) < 0) - return -1; - return 0; -} - -static int Write16_0(struct drxk_state *state, u32 reg, u16 data) -{ - return Write16(state, reg, data, 0); -} - -static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) -{ - u8 adr = state->demod_address, mm[8], len; -#ifdef I2C_LONG_ADR - flags |= 0xC0; -#endif - if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { - mm[0] = (((reg << 1) & 0xFF) | 0x01); - mm[1] = ((reg >> 16) & 0xFF); - mm[2] = ((reg >> 24) & 0xFF) | flags; - mm[3] = ((reg >> 7) & 0xFF); - len = 4; - } else { - mm[0] = ((reg << 1) & 0xFF); - mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); - len = 2; - } - mm[len] = data & 0xff; - mm[len+1] = (data >> 8) & 0xff; - mm[len+2] = (data >> 16) & 0xff; - mm[len+3] = (data >> 24) & 0xff; - if (i2c_write(state->i2c, adr, mm, len+4) < 0) - return -1; - return 0; -} - -static int WriteBlock(struct drxk_state *state, u32 Address, - const int BlockSize, const u8 pBlock[], u8 Flags) -{ - int status = 0, BlkSize = BlockSize; -#ifdef I2C_LONG_ADR - Flags |= 0xC0; -#endif - while (BlkSize > 0) { - int Chunk = BlkSize > state->m_ChunkSize ? - state->m_ChunkSize : BlkSize ; - u8 *AdrBuf = &state->Chunk[0]; - u32 AdrLength = 0; - - if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { - AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); - AdrBuf[1] = ((Address >> 16) & 0xFF); - AdrBuf[2] = ((Address >> 24) & 0xFF); - AdrBuf[3] = ((Address >> 7) & 0xFF); - AdrBuf[2] |= Flags; - AdrLength = 4; - if (Chunk == state->m_ChunkSize) - Chunk -= 2; - } else { - AdrBuf[0] = ((Address << 1) & 0xFF); - AdrBuf[1] = (((Address >> 16) & 0x0F) | - ((Address >> 18) & 0xF0)); - AdrLength = 2; - } - memcpy(&state->Chunk[AdrLength], pBlock, Chunk); - status = i2c_write(state->i2c, state->demod_address, - &state->Chunk[0], Chunk+AdrLength); - if (status<0) { - printk("I2C Write error\n"); - break; - } - pBlock += Chunk; - Address += (Chunk >> 1); - BlkSize -= Chunk; - } - return status; -} - -#ifndef DRXK_MAX_RETRIES_POWERUP -#define DRXK_MAX_RETRIES_POWERUP 20 -#endif - -int PowerUpDevice(struct drxk_state *state) -{ - int status; - u8 data = 0; - u16 retryCount = 0; - - status = i2c_read1(state->i2c, state->demod_address, &data); - if (status<0) - do { - data = 0; - if (i2c_write(state->i2c, - state->demod_address, &data, 1) < 0) - printk("powerup failed\n"); - msleep(10); - retryCount++ ; - } while (i2c_read1(state->i2c, - state->demod_address, &data) < 0 && - (retryCount < DRXK_MAX_RETRIES_POWERUP)); - if (retryCount >= DRXK_MAX_RETRIES_POWERUP) - return -1; - do { - /* Make sure all clk domains are active */ - CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, - SIO_CC_PWD_MODE_LEVEL_NONE)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, - SIO_CC_UPDATE_KEY)); - /* Enable pll lock tests */ - CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); - state->m_currentPowerMode = DRX_POWER_UP; - } while (0); - return status; -} - - -static int init_state(struct drxk_state *state) -{ - u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; - u32 ulVSBIfAgcOutputLevel = 0; - u32 ulVSBIfAgcMinLevel = 0; - u32 ulVSBIfAgcMaxLevel = 0x7FFF; - u32 ulVSBIfAgcSpeed = 3; - - u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; - u32 ulVSBRfAgcOutputLevel = 0; - u32 ulVSBRfAgcMinLevel = 0; - u32 ulVSBRfAgcMaxLevel = 0x7FFF; - u32 ulVSBRfAgcSpeed = 3; - u32 ulVSBRfAgcTop = 9500; - u32 ulVSBRfAgcCutOffCurrent = 4000; - - u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; - u32 ulATVIfAgcOutputLevel = 0; - u32 ulATVIfAgcMinLevel = 0; - u32 ulATVIfAgcMaxLevel = 0; - u32 ulATVIfAgcSpeed = 3; - - u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; - u32 ulATVRfAgcOutputLevel = 0; - u32 ulATVRfAgcMinLevel = 0; - u32 ulATVRfAgcMaxLevel = 0; - u32 ulATVRfAgcTop = 9500; - u32 ulATVRfAgcCutOffCurrent = 4000; - u32 ulATVRfAgcSpeed = 3; - - u32 ulQual83 = DEFAULT_MER_83; - u32 ulQual93 = DEFAULT_MER_93; - - u32 ulDVBTStaticTSClock = 1; - u32 ulDVBCStaticTSClock = 1; - - u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; - u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; - - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ - u32 ulGPIOCfg = 0x0113; - u32 ulGPIO = 0; - u32 ulSerialMode = 1; - u32 ulInvertTSClock = 0; - u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; - u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; - u32 ulDVBTBitrate = 50000000; - u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; - - u32 ulInsertRSByte = 0; - - u32 ulRfMirror = 1; - u32 ulPowerDown = 0; - - u32 ulAntennaDVBT = 1; - u32 ulAntennaDVBC = 0; - u32 ulAntennaSwitchDVBTDVBC = 0; - - state->m_hasLNA = false; - state->m_hasDVBT= false; - state->m_hasDVBC= false; - state->m_hasATV= false; - state->m_hasOOB = false; - state->m_hasAudio = false; - - state->m_ChunkSize = 124; - - state->m_oscClockFreq = 0; - state->m_smartAntInverted = false; - state->m_bPDownOpenBridge = false; - - /* real system clock frequency in kHz */ - state->m_sysClockFreq = 151875; - /* Timing div, 250ns/Psys */ - /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ - state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * - HI_I2C_DELAY) / 1000; - /* Clipping */ - if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) - state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; - state->m_HICfgWakeUpKey = (state->demod_address << 1); - /* port/bridge/power down ctrl */ - state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; - - state->m_bPowerDown = (ulPowerDown != 0); - - state->m_DRXK_A1_PATCH_CODE = false; - state->m_DRXK_A1_ROM_CODE = false; - state->m_DRXK_A2_ROM_CODE = false; - state->m_DRXK_A3_ROM_CODE = false; - state->m_DRXK_A2_PATCH_CODE = false; - state->m_DRXK_A3_PATCH_CODE = false; - - /* Init AGC and PGA parameters */ - /* VSB IF */ - state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); - state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); - state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); - state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); - state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); - state->m_vsbPgaCfg = 140; - - /* VSB RF */ - state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); - state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); - state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); - state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); - state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); - state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); - state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); - state->m_vsbPreSawCfg.reference = 0x07; - state->m_vsbPreSawCfg.usePreSaw = true; - - state->m_Quality83percent = DEFAULT_MER_83; - state->m_Quality93percent = DEFAULT_MER_93; - if (ulQual93 <= 500 && ulQual83 < ulQual93) { - state->m_Quality83percent = ulQual83; - state->m_Quality93percent = ulQual93; - } - - /* ATV IF */ - state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); - state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); - state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); - state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); - state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); - - /* ATV RF */ - state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); - state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); - state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); - state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); - state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); - state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); - state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); - state->m_atvPreSawCfg.reference = 0x04; - state->m_atvPreSawCfg.usePreSaw = true; - - - /* DVBT RF */ - state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; - state->m_dvbtRfAgcCfg.outputLevel = 0; - state->m_dvbtRfAgcCfg.minOutputLevel = 0; - state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; - state->m_dvbtRfAgcCfg.top = 0x2100; - state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; - state->m_dvbtRfAgcCfg.speed = 1; - - - /* DVBT IF */ - state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; - state->m_dvbtIfAgcCfg.outputLevel = 0; - state->m_dvbtIfAgcCfg.minOutputLevel = 0; - state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; - state->m_dvbtIfAgcCfg.top = 13424; - state->m_dvbtIfAgcCfg.cutOffCurrent = 0; - state->m_dvbtIfAgcCfg.speed = 3; - state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; - state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; - // state->m_dvbtPgaCfg = 140; - - state->m_dvbtPreSawCfg.reference = 4; - state->m_dvbtPreSawCfg.usePreSaw = false; - - /* QAM RF */ - state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; - state->m_qamRfAgcCfg.outputLevel = 0; - state->m_qamRfAgcCfg.minOutputLevel = 6023; - state->m_qamRfAgcCfg.maxOutputLevel = 27000; - state->m_qamRfAgcCfg.top = 0x2380; - state->m_qamRfAgcCfg.cutOffCurrent = 4000; - state->m_qamRfAgcCfg.speed = 3; - - /* QAM IF */ - state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; - state->m_qamIfAgcCfg.outputLevel = 0; - state->m_qamIfAgcCfg.minOutputLevel = 0; - state->m_qamIfAgcCfg.maxOutputLevel = 9000; - state->m_qamIfAgcCfg.top = 0x0511; - state->m_qamIfAgcCfg.cutOffCurrent = 0; - state->m_qamIfAgcCfg.speed = 3; - state->m_qamIfAgcCfg.IngainTgtMax = 5119; - state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; - - state->m_qamPgaCfg = 140; - state->m_qamPreSawCfg.reference = 4; - state->m_qamPreSawCfg.usePreSaw = false; - - state->m_OperationMode = OM_NONE; - state->m_DrxkState = DRXK_UNINITIALIZED; - - /* MPEG output configuration */ - state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ - state->m_insertRSByte = false; /* If TRUE; insert RS byte */ - state->m_enableParallel = true; /* If TRUE; - parallel out otherwise serial */ - state->m_invertDATA = false; /* If TRUE; invert DATA signals */ - state->m_invertERR = false; /* If TRUE; invert ERR signal */ - state->m_invertSTR = false; /* If TRUE; invert STR signals */ - state->m_invertVAL = false; /* If TRUE; invert VAL signals */ - state->m_invertCLK = - (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ - state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); - state->m_DVBCStaticCLK = - (ulDVBCStaticTSClock != 0); - /* If TRUE; static MPEG clockrate will be used; - otherwise clockrate will adapt to the bitrate of the TS */ - - state->m_DVBTBitrate = ulDVBTBitrate; - state->m_DVBCBitrate = ulDVBCBitrate; - - state->m_TSDataStrength = (ulTSDataStrength & 0x07); - state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); - - /* Maximum bitrate in b/s in case static clockrate is selected */ - state->m_mpegTsStaticBitrate = 19392658; - state->m_disableTEIhandling = false; - - if (ulInsertRSByte) - state->m_insertRSByte = true; - - state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; - if (ulMpegLockTimeOut < 10000) - state->m_MpegLockTimeOut = ulMpegLockTimeOut; - state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; - if (ulDemodLockTimeOut < 10000) - state->m_DemodLockTimeOut = ulDemodLockTimeOut; - - // QAM defaults - state->m_Constellation = DRX_CONSTELLATION_AUTO; - state->m_qamInterleaveMode = DRXK_QAM_I12_J17; - state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/ - state->m_fecRsPrescale = 1; - - state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; - state->m_agcFastClipCtrlDelay = 0; - - state->m_GPIOCfg = (ulGPIOCfg); - state->m_GPIO = (ulGPIO == 0 ? 0 : 1); - - state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1); - state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1); - state->m_AntennaSwitchDVBTDVBC = - (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1); - - state->m_bPowerDown = false; - state->m_currentPowerMode = DRX_POWER_DOWN; - - state->m_enableParallel = (ulSerialMode == 0); - - state->m_rfmirror = (ulRfMirror == 0); - state->m_IfAgcPol = false; - return 0; -} - -static int DRXX_Open(struct drxk_state *state) -{ - int status = 0; - u32 jtag = 0; - u16 bid = 0; - u16 key = 0; - - do { - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - /* Check device id */ - CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, - SIO_TOP_COMM_KEY_KEY)); - CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); - CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); - } while(0); - return status; -} - -static int GetDeviceCapabilities(struct drxk_state *state) -{ - u16 sioPdrOhwCfg = 0; - u32 sioTopJtagidLo = 0; - int status; - - do { - /* driver 0.9.0 */ - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); - CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); - - switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { - case 0: - /* ignore (bypass ?) */ - break; - case 1: - /* 27 MHz */ - state->m_oscClockFreq = 27000; - break; - case 2: - /* 20.25 MHz */ - state->m_oscClockFreq = 20250; - break; - case 3: - /* 4 MHz */ - state->m_oscClockFreq = 20250; - break; - default: - return -1; - } - /* - Determine device capabilities - Based on pinning v14 - */ - CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, - &sioTopJtagidLo, 0)); - /* driver 0.9.0 */ - switch((sioTopJtagidLo >> 29) & 0xF) { - case 0: - state->m_deviceSpin = DRXK_SPIN_A1; - break; - case 2: - state->m_deviceSpin = DRXK_SPIN_A2; - break; - case 3: - state->m_deviceSpin = DRXK_SPIN_A3; - break; - default: - state->m_deviceSpin = DRXK_SPIN_UNKNOWN; - status = -1; - break; - } - switch ((sioTopJtagidLo>>12)&0xFF) { - case 0x13: - /* typeId = DRX3913K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = false; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = false; - state->m_hasGPIO1 = false; - state->m_hasIRQN = false; - break; - case 0x15: - /* typeId = DRX3915K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x16: - /* typeId = DRX3916K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x18: - /* typeId = DRX3918K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x21: - /* typeId = DRX3921K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x23: - /* typeId = DRX3923K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x25: - /* typeId = DRX3925K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - case 0x26: - /* typeId = DRX3926K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; - break; - default: - printk("DeviceID not supported = %02x\n", - ((sioTopJtagidLo>>12)&0xFF)); - status = -1; - break; - } - } while(0); - return status; -} - -static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) -{ - int status; - bool powerdown_cmd; - - //printk("%s\n", __FUNCTION__); - - /* Write command */ - status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); - if (status < 0) - return status; - if (cmd == SIO_HI_RA_RAM_CMD_RESET) - msleep(1); - - powerdown_cmd = - (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && - ((state->m_HICfgCtrl) & - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); - if (powerdown_cmd == false) { - /* Wait until command rdy */ - u32 retryCount = 0; - u16 waitCmd; - - do { - msleep(1); - retryCount += 1; - status = Read16(state, SIO_HI_RA_RAM_CMD__A, - &waitCmd, 0); - } while ((status < 0) && - (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0)); - - if (status == 0) - status = Read16(state, SIO_HI_RA_RAM_RES__A, - pResult, 0); - } - return status; -} - -static int HI_CfgCommand(struct drxk_state *state) -{ - int status; - - mutex_lock(&state->mutex); - do { - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A, - state->m_HICfgTimeout)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A, - state->m_HICfgCtrl)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A, - state->m_HICfgWakeUpKey)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A, - state->m_HICfgBridgeDelay)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A, - state->m_HICfgTimingDiv)); - CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A, - SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); - CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); - - state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - } while(0); - mutex_unlock(&state->mutex); - return status; -} - -static int InitHI(struct drxk_state *state) -{ - state->m_HICfgWakeUpKey = (state->demod_address<<1); - state->m_HICfgTimeout = 0x96FF; - /* port/bridge/power down ctrl */ - state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; - return HI_CfgCommand(state); -} - -static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) -{ - int status = -1; - u16 sioPdrMclkCfg = 0; - u16 sioPdrMdxCfg = 0; - - do { - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - /* MPEG TS pad configuration */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); - - if (mpegEnable == false) { - /* Set MPEG TS pads to inputmode */ - CHK_ERROR(Write16_0(state, - SIO_PDR_MSTRT_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, - SIO_PDR_MERR_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, - SIO_PDR_MCLK_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, - SIO_PDR_MVAL_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000)); - } else { - /* Enable MPEG output */ - sioPdrMdxCfg = - ((state->m_TSDataStrength << - SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); - sioPdrMclkCfg = ((state->m_TSClockkStrength << - SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); - - CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, - 0x0000)); // Disable - CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, - 0x0000)); // Disable - if (state->m_enableParallel == true) { - /* paralel -> enable MD1 to MD7 */ - CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, - sioPdrMdxCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, - sioPdrMdxCfg)); - } else { - sioPdrMdxCfg = ((state->m_TSDataStrength << - SIO_PDR_MD0_CFG_DRIVE__B) | - 0x0003); - /* serial -> disable MD1 to MD7 */ - CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, - 0x0000)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, - 0x0000)); - } - CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, - sioPdrMclkCfg)); - CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, - sioPdrMdxCfg)); - } - /* Enable MB output over MPEG pads and ctl input */ - CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); - /* Write nomagic word to enable pdr reg write */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); - } while(0); - return status; -} - -static int MPEGTSDisable(struct drxk_state *state) -{ - return MPEGTSConfigurePins(state, false); -} - -static int BLChainCmd(struct drxk_state *state, - u16 romOffset, u16 nrOfElements, u32 timeOut) -{ - u16 blStatus = 0; - int status; - unsigned long end; - - mutex_lock(&state->mutex); - do { - CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, - SIO_BL_MODE_CHAIN)); - CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, - romOffset)); - CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, - nrOfElements)); - CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, - SIO_BL_ENABLE_ON)); - end=jiffies+msecs_to_jiffies(timeOut); - - do { - msleep(1); - CHK_ERROR(Read16(state, SIO_BL_STATUS__A, - &blStatus, 0)); - } while ((blStatus == 0x1) && - ((time_is_after_jiffies(end)))); - if (blStatus == 0x1) { - printk("SIO not ready\n"); - mutex_unlock(&state->mutex); - return -1; - } - } while(0); - mutex_unlock(&state->mutex); - return status; -} - - -static int DownloadMicrocode(struct drxk_state *state, - const u8 pMCImage[], - u32 Length) -{ - const u8 *pSrc = pMCImage; - u16 Flags; - u16 Drain; - u32 Address; - u16 nBlocks; - u16 BlockSize; - u16 BlockCRC; - u32 offset = 0; - u32 i; - int status; - - /* down the drain (we don care about MAGIC_WORD) */ - Drain = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - nBlocks = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - - for (i = 0; i < nBlocks; i += 1) { - Address = (pSrc[0] << 24) | (pSrc[1] << 16) | - (pSrc[2] << 8) | pSrc[3]; - pSrc += sizeof(u32); offset += sizeof(u32); - - BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); - pSrc += sizeof(u16); offset += sizeof(u16); - - Flags = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - - BlockCRC = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); - status = WriteBlock(state, Address, BlockSize, pSrc, 0); - if (status<0) - break; - pSrc += BlockSize; - offset += BlockSize; - } - return status; -} - -static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) -{ - int status; - u16 data = 0; - u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; - u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; - unsigned long end; - - if (enable == false) { - desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; - desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; - } - - status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); - - if (data == desiredStatus) { - /* tokenring already has correct status */ - return status; - } - /* Disable/enable dvbt tokenring bridge */ - status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); - - end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); - do - CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); - while ((data != desiredStatus) && - ((time_is_after_jiffies(end)))); - if (data != desiredStatus) { - printk("SIO not ready\n"); - return -1; - } - return status; -} - -static int MPEGTSStop(struct drxk_state *state) -{ - int status = 0; - u16 fecOcSncMode = 0; - u16 fecOcIprMode = 0; - - do { - /* Gracefull shutdown (byte boundaries) */ - CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); - fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; - CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); - - /* Suppress MCLK during absence of data */ - CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); - fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; - CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode)); - } while (0); - return status; -} - -static int scu_command(struct drxk_state *state, - u16 cmd, u8 parameterLen, - u16 * parameter, u8 resultLen, u16 * result) -{ -#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 -#error DRXK register mapping no longer compatible with this routine! -#endif - u16 curCmd = 0; - int status; - unsigned long end; - - if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || - ((resultLen > 0) && (result == NULL))) - return -1; - - mutex_lock(&state->mutex); - do { - /* assume that the command register is ready - since it is checked afterwards */ - u8 buffer[34]; - int cnt = 0, ii; - - for (ii=parameterLen-1; ii >= 0; ii -= 1) { - buffer[cnt++] = (parameter[ii] & 0xFF); - buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); - } - buffer[cnt++] = (cmd & 0xFF); - buffer[cnt++] = ((cmd >> 8) & 0xFF); - - WriteBlock(state, SCU_RAM_PARAM_0__A - - (parameterLen-1), cnt, buffer, 0x00); - /* Wait until SCU has processed command */ - end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME); - do { - msleep(1); - CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd)); - } while (! (curCmd == DRX_SCU_READY) && - (time_is_after_jiffies(end))); - if (curCmd != DRX_SCU_READY) { - printk("SCU not ready\n"); - mutex_unlock(&state->mutex); - return -1; - } - /* read results */ - if ((resultLen > 0) && (result != NULL)) { - s16 err; - int ii; - - for(ii=resultLen-1; ii >= 0; ii -= 1) { - CHK_ERROR(Read16_0(state, - SCU_RAM_PARAM_0__A - ii, - &result[ii])); - } - - /* Check if an error was reported by SCU */ - err = (s16)result[0]; - - /* check a few fixed error codes */ - if (err == SCU_RESULT_UNKSTD) { - printk("SCU_RESULT_UNKSTD\n"); - mutex_unlock(&state->mutex); - return -1; - } else if (err == SCU_RESULT_UNKCMD) { - printk("SCU_RESULT_UNKCMD\n"); - mutex_unlock(&state->mutex); - return -1; - } - /* here it is assumed that negative means error, - and positive no error */ - else if (err < 0) { - printk("%s ERROR\n", __FUNCTION__); - mutex_unlock(&state->mutex); - return -1; - } - } - } while(0); - mutex_unlock(&state->mutex); - if (status<0) - { - printk("%s: status = %d\n", __FUNCTION__, status); - } - - return status; -} - -static int SetIqmAf(struct drxk_state *state, bool active) -{ - u16 data = 0; - int status; - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active)); - //printk("%s\n", __FUNCTION__); - - do - { - /* Configure IQM */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));; - if (!active) { - data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY - | IQM_AF_STDBY_STDBY_AMP_STANDBY - | IQM_AF_STDBY_STDBY_PD_STANDBY - | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY - | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY - ); - // break; - //default: - // break; - //} - } else /* active */ { - data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) - & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) - & (~IQM_AF_STDBY_STDBY_PD_STANDBY) - & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) - & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) - ); - // break; - //default: - // break; - //} - } - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - }while(0); - return status; -} - -static int CtrlPowerMode(struct drxk_state *state, - pDRXPowerMode_t mode) -{ - int status = 0; - u16 sioCcPwdMode = 0; - - //printk("%s\n", __FUNCTION__); - /* Check arguments */ - if (mode == NULL) - return -1; - - switch (*mode) { - case DRX_POWER_UP: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; - break; - case DRXK_POWER_DOWN_OFDM: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; - break; - case DRXK_POWER_DOWN_CORE: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; - break; - case DRXK_POWER_DOWN_PLL: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; - break; - case DRX_POWER_DOWN: - sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; - break; - default: - /* Unknow sleep mode */ - return -1; - break; - } - - /* If already in requested power mode, do nothing */ - if (state->m_currentPowerMode == *mode) - return 0; - - /* For next steps make sure to start from DRX_POWER_UP mode */ - if (state->m_currentPowerMode != DRX_POWER_UP) - { - do { - CHK_ERROR(PowerUpDevice(state)); - CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); - } while(0); - } - - if (*mode == DRX_POWER_UP) { - /* Restore analog & pin configuartion */ - } else { - /* Power down to requested mode */ - /* Backup some register settings */ - /* Set pins with possible pull-ups connected - to them in input mode */ - /* Analog power down */ - /* ADC power down */ - /* Power down device */ - /* stop all comm_exec */ - /* Stop and power down previous standard */ - do { - switch (state->m_OperationMode) { - case OM_DVBT: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownDVBT(state, false)); - break; - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownQAM(state)); - break; - default: - break; - } - CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); - CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, - sioCcPwdMode)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, - SIO_CC_UPDATE_KEY)); - - if (*mode != DRXK_POWER_DOWN_OFDM) { - state->m_HICfgCtrl |= - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - CHK_ERROR(HI_CfgCommand(state)); - } - } while(0); - } - state->m_currentPowerMode = *mode; - return (status); -} - -static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) -{ - DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; - u16 cmdResult = 0; - u16 data = 0; - int status; - - do { - CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); - if (data == SCU_COMM_EXEC_ACTIVE) { - /* Send OFDM stop command */ - CHK_ERROR(scu_command(state, - SCU_RAM_COMMAND_STANDARD_OFDM | - SCU_RAM_COMMAND_CMD_DEMOD_STOP, - 0, NULL, 1, &cmdResult)); - /* Send OFDM reset command */ - CHK_ERROR(scu_command(state, - SCU_RAM_COMMAND_STANDARD_OFDM | - SCU_RAM_COMMAND_CMD_DEMOD_RESET, - 0, NULL, 1, &cmdResult)); - } - - /* Reset datapath for OFDM, processors first */ - CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, - OFDM_SC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, - OFDM_LC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, - IQM_COMM_EXEC_B_STOP)); - - /* powerdown AFE */ - CHK_ERROR(SetIqmAf(state,false)); - - /* powerdown to OFDM mode */ - if (setPowerMode) { - CHK_ERROR(CtrlPowerMode(state,&powerMode)); - } - } while(0); - return status; -} - -static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode) -{ - int status = 0; - - /* - Stop and power down previous standard - TODO investigate total power down instead of partial - power down depending on "previous" standard. - */ - do { - /* disable HW lock indicator */ - CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - if (state->m_OperationMode != oMode) { - switch (state->m_OperationMode) { - // OM_NONE was added for start up - case OM_NONE: - break; - case OM_DVBT: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownDVBT(state,true)); - state->m_OperationMode = OM_NONE; - break; - case OM_QAM_ITU_B: - status = -1; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(PowerDownQAM(state)); - state->m_OperationMode = OM_NONE; - break; - default: - status = -1; - } - CHK_ERROR(status); - - /* - Power up new standard - */ - switch (oMode) - { - case OM_DVBT: - state->m_OperationMode = oMode; - CHK_ERROR(SetDVBTStandard(state, oMode)); - break; - case OM_QAM_ITU_B: - status = -1; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: - state->m_OperationMode = oMode; - CHK_ERROR(SetQAMStandard(state,oMode)); - break; - default: - status = -1; - } - } - CHK_ERROR(status); - } while(0); - return 0; -} - -static int Start(struct drxk_state *state, s32 offsetFreq, - s32 IntermediateFrequency) -{ - int status; - - do { - u16 IFreqkHz; - s32 OffsetkHz = offsetFreq / 1000; - - if (state->m_DrxkState != DRXK_STOPPED && - state->m_DrxkState != DRXK_DTV_STARTED) { - status = -1; - break; - } - state->m_bMirrorFreqSpect = -#ifndef USE_API3 - (state->props.inversion == INVERSION_ON); -#else - (state->param.inversion == INVERSION_ON); -#endif - if (IntermediateFrequency < 0) { - state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; - IntermediateFrequency = -IntermediateFrequency; - } - - switch(state->m_OperationMode) { - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: - IFreqkHz = (IntermediateFrequency / 1000); - CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz)); - state->m_DrxkState = DRXK_DTV_STARTED; - break; - case OM_DVBT: - IFreqkHz = (IntermediateFrequency / 1000); - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz)); - CHK_ERROR(DVBTStart(state)); - state->m_DrxkState = DRXK_DTV_STARTED; - break; - default: - break; - } - } while(0); - return status; -} - -static int ShutDown(struct drxk_state *state) -{ - MPEGTSStop(state); - return 0; -} - -static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time) -{ - int status; - - if (pLockStatus == NULL) - return -1; - - *pLockStatus = NOT_LOCKED; - - /* define the SCU command code */ - switch (state->m_OperationMode) { - case OM_QAM_ITU_A: - case OM_QAM_ITU_B: - case OM_QAM_ITU_C: - status = GetQAMLockStatus(state, pLockStatus); - break; - case OM_DVBT: - status = GetDVBTLockStatus(state, pLockStatus); - break; - default: - break; - } - return status; -} - -static int MPEGTSStart(struct drxk_state *state) -{ - int status = 0; - - u16 fecOcSncMode = 0; - - do { - /* Allow OC to sync again */ - CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); - fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; - CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); - } while (0); - return status; -} - -static int MPEGTSDtoInit(struct drxk_state *state) -{ - int status = -1; - - do { - /* Rate integration settings */ - CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); - CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); - CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); - CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); - CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); - - /* Additional configuration */ - CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); - } while (0); - return status; -} - -static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode) -{ - int status = -1; - - u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ - u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ - u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ - u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ - u16 fecOcTmdMode = 0; - u16 fecOcTmdIntUpdRate = 0; - u32 maxBitRate = 0; - bool staticCLK = false; - - do { - /* Check insertion of the Reed-Solomon parity bytes */ - CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); - CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, - &fecOcRegIprMode)); - fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); - fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); - if (state->m_insertRSByte == true) { - /* enable parity symbol forward */ - fecOcRegMode |= FEC_OC_MODE_PARITY__M; - /* MVAL disable during parity bytes */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; - /* TS burst length to 204 */ - fecOcDtoBurstLen = 204 ; - } - - /* Check serial or parrallel output */ - fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); - if (state->m_enableParallel == false) { - /* MPEG data output is serial -> set ipr_mode[0] */ - fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; - } - - switch (oMode) { - case OM_DVBT: - maxBitRate = state->m_DVBTBitrate; - fecOcTmdMode = 3; - fecOcRcnCtlRate = 0xC00000; - staticCLK = state->m_DVBTStaticCLK; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: - fecOcTmdMode = 0x0004; - fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ - maxBitRate = state->m_DVBCBitrate; - staticCLK = state->m_DVBCStaticCLK; - break; - default: - status = -1; - } /* switch (standard) */ - CHK_ERROR(status); - - /* Configure DTO's */ - if (staticCLK ) { - u32 bitRate = 0; - - /* Rational DTO for MCLK source (static MCLK rate), - Dynamic DTO for optimal grouping - (avoid intra-packet gaps), - DTO offset enable to sync TS burst with MSTRT */ - fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | - FEC_OC_DTO_MODE_OFFSET_ENABLE__M); - fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | - FEC_OC_FCT_MODE_VIRT_ENA__M); - - /* Check user defined bitrate */ - bitRate = maxBitRate; - if (bitRate > 75900000UL) - { /* max is 75.9 Mb/s */ - bitRate = 75900000UL; - } - /* Rational DTO period: - dto_period = (Fsys / bitrate) - 2 - - Result should be floored, - to make sure >= requested bitrate - */ - fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) - * 1000) / bitRate); - if (fecOcDtoPeriod <= 2) - fecOcDtoPeriod = 0; - else - fecOcDtoPeriod -= 2; - fecOcTmdIntUpdRate = 8; - } else { - /* (commonAttr->staticCLK == false) => dynamic mode */ - fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; - fecOcFctMode = FEC_OC_FCT_MODE__PRE; - fecOcTmdIntUpdRate = 5; - } - - /* Write appropriate registers with requested configuration */ - CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, - fecOcDtoBurstLen)); - CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, - fecOcDtoPeriod)); - CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, - fecOcDtoMode)); - CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, - fecOcFctMode)); - CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, - fecOcRegMode)); - CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, - fecOcRegIprMode)); - - /* Rate integration settings */ - CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, - fecOcRcnCtlRate ,0)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, - fecOcTmdIntUpdRate)); - CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, - fecOcTmdMode)); - } while (0); - return status; -} - -static int MPEGTSConfigurePolarity(struct drxk_state *state) -{ - int status; - u16 fecOcRegIprInvert = 0; - - /* Data mask for the output data byte */ - u16 InvertDataMask = - FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | - FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | - FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | - FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; - - /* Control selective inversion of output bits */ - fecOcRegIprInvert &= (~(InvertDataMask)); - if (state->m_invertDATA == true) - fecOcRegIprInvert |= InvertDataMask; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); - if (state->m_invertERR == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); - if (state->m_invertSTR == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); - if (state->m_invertVAL == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; - fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); - if (state->m_invertCLK == true) - fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; - status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); - return status; -} - -#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 - -static int SetAgcRf(struct drxk_state *state, - struct SCfgAgc *pAgcCfg, bool isDTV) -{ - int status = 0; - struct SCfgAgc *pIfAgcSettings; - - if (pAgcCfg == NULL) - return -1; - - do { - u16 data = 0; - - switch (pAgcCfg->ctrlMode) { - case DRXK_AGC_CTRL_AUTO: - - /* Enable RF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); - - CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, - &data, 0)); - - /* Enable SCU RF AGC loop */ - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; - - /* Polarity */ - if (state->m_RfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - - /* Set speed (using complementary reduction value) */ - CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, - &data, 0)); - - data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; - data |= (~(pAgcCfg->speed << - SCU_RAM_AGC_KI_RED_RAGC_RED__B) - & SCU_RAM_AGC_KI_RED_RAGC_RED__M); - - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_KI_RED__A, data)); - - if (IsDVBT(state)) - pIfAgcSettings = &state->m_dvbtIfAgcCfg; - else if (IsQAM(state)) - pIfAgcSettings = &state->m_qamIfAgcCfg; - else - pIfAgcSettings = &state->m_atvIfAgcCfg; - if (pIfAgcSettings == NULL) - return -1; - - /* Set TOP, only if IF-AGC is in AUTO mode */ - if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pAgcCfg->top)); - - /* Cut-Off current */ - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_RF_IACCU_HI_CO__A, - pAgcCfg->cutOffCurrent)); - - /* Max. output level */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, - pAgcCfg->maxOutputLevel)); - - break; - - case DRXK_AGC_CTRL_USER: - /* Enable RF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); - - /* Disable SCU RF AGC loop */ - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; - if (state->m_RfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, - data)); - - /* SCU c.o.c. to 0, enabling full control range */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, - 0)); - - /* Write value to output pin */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, - pAgcCfg->outputLevel)); - break; - - case DRXK_AGC_CTRL_OFF: - /* Disable RF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - /* Disable SCU RF AGC loop */ - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - break; - - default: - return -1; - - } /* switch (agcsettings->ctrlMode) */ - } while(0); - return status; -} - -#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 - -static int SetAgcIf (struct drxk_state *state, - struct SCfgAgc *pAgcCfg, bool isDTV) -{ - u16 data = 0; - int status = 0; - struct SCfgAgc *pRfAgcSettings; - - do { - switch (pAgcCfg->ctrlMode) { - case DRXK_AGC_CTRL_AUTO: - - /* Enable IF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, - &data)); - - /* Enable SCU IF AGC loop */ - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - - /* Polarity */ - if (state->m_IfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - - /* Set speed (using complementary reduction value) */ - CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, - &data)); - data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; - data |= (~(pAgcCfg->speed << - SCU_RAM_AGC_KI_RED_IAGC_RED__B) - & SCU_RAM_AGC_KI_RED_IAGC_RED__M); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A , - data)); - - if (IsQAM(state)) - pRfAgcSettings = &state->m_qamRfAgcCfg; - else - pRfAgcSettings = &state->m_atvRfAgcCfg; - if (pRfAgcSettings == NULL) - return -1; - /* Restore TOP */ - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pRfAgcSettings->top)); - break; - - case DRXK_AGC_CTRL_USER: - - /* Enable IF AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - - /* Disable SCU IF AGC loop */ - data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - - /* Polarity */ - if (state->m_IfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - - /* Write value to output pin */ - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - pAgcCfg->outputLevel)); - break; - - case DRXK_AGC_CTRL_OFF: - - /* Disable If AGC DAC */ - CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); - data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; - CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); - - /* Disable SCU IF AGC loop */ - CHK_ERROR(Read16_0(state, - SCU_RAM_AGC_CONFIG__A, &data)); - data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - CHK_ERROR(Write16_0(state, - SCU_RAM_AGC_CONFIG__A, data)); - break; - } /* switch (agcSettingsIf->ctrlMode) */ - - /* always set the top to support - configurations without if-loop */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, - pAgcCfg->top)); - - - } while(0); - return status; -} - -static int ReadIFAgc(struct drxk_state *state, u32 *pValue) -{ - u16 agcDacLvl; - int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); - - *pValue = 0; - - if (status==0) { - u16 Level = 0; - if (agcDacLvl > DRXK_AGC_DAC_OFFSET) - Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; - if (Level < 14000) - *pValue = (14000 - Level) / 4 ; - else - *pValue = 0; - } - return status; -} - -static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) -{ - int status = 0; - - do { - /* MER calculation */ - u16 qamSlErrPower = 0; /* accum. error between - raw and sliced symbols */ - u32 qamSlSigPower = 0; /* used for MER, depends of - QAM constellation */ - u32 qamSlMer = 0; /* QAM MER */ - - /* get the register value needed for MER */ - CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower)); - -#ifndef USE_API3 - switch(state->props.modulation) { -#else - switch(state->param.u.qam.modulation) { -#endif - case QAM_16: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; - break; - case QAM_32: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; - break; - case QAM_64: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; - break; - case QAM_128: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; - break; - default: - case QAM_256: - qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; - break; - } - - if (qamSlErrPower > 0) { - qamSlMer = Log10Times100(qamSlSigPower) - - Log10Times100((u32) qamSlErrPower); - } - *pSignalToNoise = qamSlMer; - } while(0); - return status; -} - -static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) -{ - int status = 0; - - u16 regData = 0; - u32 EqRegTdSqrErrI = 0; - u32 EqRegTdSqrErrQ = 0; - u16 EqRegTdSqrErrExp = 0; - u16 EqRegTdTpsPwrOfs = 0; - u16 EqRegTdReqSmbCnt = 0; - u32 tpsCnt = 0; - u32 SqrErrIQ = 0; - u32 a = 0; - u32 b = 0; - u32 c = 0; - u32 iMER = 0; - u16 transmissionParams = 0; - - do { - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, - &EqRegTdTpsPwrOfs)); - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, - &EqRegTdReqSmbCnt)); - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, - &EqRegTdSqrErrExp)); - CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, - ®Data)); - /* Extend SQR_ERR_I operational range */ - EqRegTdSqrErrI = (u32) regData; - if ((EqRegTdSqrErrExp > 11) && - (EqRegTdSqrErrI < 0x00000FFFUL)) { - EqRegTdSqrErrI += 0x00010000UL; - } - CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A, - ®Data)); - /* Extend SQR_ERR_Q operational range */ - EqRegTdSqrErrQ = (u32)regData; - if ((EqRegTdSqrErrExp > 11) && - (EqRegTdSqrErrQ < 0x00000FFFUL)) - EqRegTdSqrErrQ += 0x00010000UL; - - CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A, - &transmissionParams)); - - /* Check input data for MER */ - - /* MER calculation (in 0.1 dB) without math.h */ - if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) - iMER = 0; - else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { - /* No error at all, this must be the HW reset value - * Apparently no first measurement yet - * Set MER to 0.0 */ - iMER = 0; - } else { - SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << - EqRegTdSqrErrExp; - if ((transmissionParams & - OFDM_SC_RA_RAM_OP_PARAM_MODE__M) - == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) - tpsCnt = 17; - else - tpsCnt = 68; - - /* IMER = 100 * log10 (x) - where x = (EqRegTdTpsPwrOfs^2 * - EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ - - => IMER = a + b -c - where a = 100 * log10 (EqRegTdTpsPwrOfs^2) - b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) - c = 100 * log10 (SqrErrIQ) - */ - - /* log(x) x = 9bits * 9bits->18 bits */ - a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs); - /* log(x) x = 16bits * 7bits->23 bits */ - b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt); - /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ - c = Log10Times100(SqrErrIQ); - - iMER = a + b; - /* No negative MER, clip to zero */ - if (iMER > c) - iMER -= c; - else - iMER = 0; - } - *pSignalToNoise = iMER; - } while(0); - - return status; -} - -static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) -{ - *pSignalToNoise = 0; - switch(state->m_OperationMode) { - case OM_DVBT: - return GetDVBTSignalToNoise(state, pSignalToNoise); - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: - return GetQAMSignalToNoise(state, pSignalToNoise); - default: - break; - } - return 0; -} - -#if 0 -static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) -{ - /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ - int status = 0; - - static s32 QE_SN[] = - { - 51, // QPSK 1/2 - 69, // QPSK 2/3 - 79, // QPSK 3/4 - 89, // QPSK 5/6 - 97, // QPSK 7/8 - 108, // 16-QAM 1/2 - 131, // 16-QAM 2/3 - 146, // 16-QAM 3/4 - 156, // 16-QAM 5/6 - 160, // 16-QAM 7/8 - 165, // 64-QAM 1/2 - 187, // 64-QAM 2/3 - 202, // 64-QAM 3/4 - 216, // 64-QAM 5/6 - 225, // 64-QAM 7/8 - }; - - *pQuality = 0; - - do { - s32 SignalToNoise = 0; - u16 Constellation = 0; - u16 CodeRate = 0; - u32 SignalToNoiseRel; - u32 BERQuality; - - CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise)); - CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A, - &Constellation)); - Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; - - CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A, - &CodeRate)); - CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; - - if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || - CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) - break; - SignalToNoiseRel = SignalToNoise - - QE_SN[Constellation * 5 + CodeRate]; - BERQuality = 100; - - if (SignalToNoiseRel < -70) *pQuality = 0; - else if (SignalToNoiseRel < 30) - *pQuality = ((SignalToNoiseRel + 70) * - BERQuality) / 100; - else - *pQuality = BERQuality; - } while(0); - return 0; -}; - -static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) -{ - int status = 0; - *pQuality = 0; - - do { - u32 SignalToNoise = 0; - u32 BERQuality = 100; - u32 SignalToNoiseRel = 0; - - CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); - -#ifndef USE_API3 - switch(state->props.modulation) { -#else - switch(state->param.u.qam.modulation) { -#endif - case QAM_16: - SignalToNoiseRel = SignalToNoise - 200; - break; - case QAM_32: - SignalToNoiseRel = SignalToNoise - 230; - break; /* Not in NorDig */ - case QAM_64: - SignalToNoiseRel = SignalToNoise - 260; - break; - case QAM_128: - SignalToNoiseRel = SignalToNoise - 290; - break; - default: - case QAM_256: - SignalToNoiseRel = SignalToNoise - 320; - break; - } - - if (SignalToNoiseRel < -70) - *pQuality = 0; - else if (SignalToNoiseRel < 30) - *pQuality = ((SignalToNoiseRel + 70) * - BERQuality) / 100; - else - *pQuality = BERQuality; - } while(0); - - return status; -} - -static int GetQuality(struct drxk_state *state, s32 *pQuality) -{ - switch(state->m_OperationMode) { - case OM_DVBT: - return GetDVBTQuality(state, pQuality); - case OM_QAM_ITU_A: - return GetDVBCQuality(state, pQuality); - default: - break; - } - - return 0; -} -#endif - -/* Free data ram in SIO HI */ -#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 -#define SIO_HI_RA_RAM_USR_END__A 0x420060 - -#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) -#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) -#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ -#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE - -#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) -#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) -#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) - -static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) -{ - int status; - - if (state->m_DrxkState == DRXK_UNINITIALIZED) - return -1; - if (state->m_DrxkState == DRXK_POWERED_DOWN) - return -1; - - do { - CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, - SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); - if (bEnableBridge) { - CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, - SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); - } else { - CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, - SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); - } - - CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0)); - } while(0); - return status; -} - -static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg) -{ - int status; - - if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M)) - return -1; - - status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); - return status; -} - -static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, - u16 romOffset, u16 nrOfElements, u32 timeOut) -{ - u16 blStatus = 0; - u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF); - u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF); - int status ; - unsigned long end; - - mutex_lock(&state->mutex); - do { - CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); - CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); - CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); - CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); - CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements)); - CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); - - end=jiffies+msecs_to_jiffies(timeOut); - do { - CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus)); - } while ((blStatus == 0x1) && - time_is_after_jiffies(end)); - if (blStatus == 0x1) { - printk("SIO not ready\n"); - mutex_unlock(&state->mutex); - return -1; - } - } while(0); - mutex_unlock(&state->mutex); - return status; - -} - -static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) -{ - u16 data = 0; - int status; - - do { - /* Start measurement */ - CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, - IQM_AF_COMM_EXEC_ACTIVE)); - CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1)); - - *count = 0; - CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data)); - if (data == 127) - *count = *count+1; - CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data)); - if (data == 127) - *count = *count+1; - CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data)); - if (data == 127) - *count = *count+1; - } while(0); - return status; -} - -static int ADCSynchronization(struct drxk_state *state) -{ - u16 count = 0; - int status; - - do { - CHK_ERROR(ADCSyncMeasurement(state, &count)); - - if (count==1) { - /* Try sampling on a diffrent edge */ - u16 clkNeg = 0; - - CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg)); - if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { - clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); - clkNeg |= - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; - } else { - clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); - clkNeg |= - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; - } - CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg)); - CHK_ERROR(ADCSyncMeasurement(state, &count)); - } - - if (count < 2) - status = -1; - } while (0); - return status; -} - -static int SetFrequencyShifter(struct drxk_state *state, - u16 intermediateFreqkHz, - s32 tunerFreqOffset, - bool isDTV) -{ - bool selectPosImage = false; - u32 rfFreqResidual = tunerFreqOffset; - u32 fmFrequencyShift = 0; - bool tunerMirror = !state->m_bMirrorFreqSpect; - u32 adcFreq; - bool adcFlip; - int status; - u32 ifFreqActual; - u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3); - u32 frequencyShift; - bool imageToSelect; - - /* - Program frequency shifter - No need to account for mirroring on RF - */ - if (isDTV) { - if ((state->m_OperationMode == OM_QAM_ITU_A) || - (state->m_OperationMode == OM_QAM_ITU_C) || - (state->m_OperationMode == OM_DVBT)) - selectPosImage = true; - else - selectPosImage = false; - } - if (tunerMirror) - /* tuner doesn't mirror */ - ifFreqActual = intermediateFreqkHz + - rfFreqResidual + fmFrequencyShift; - else - /* tuner mirrors */ - ifFreqActual = intermediateFreqkHz - - rfFreqResidual - fmFrequencyShift; - if (ifFreqActual > samplingFrequency / 2) { - /* adc mirrors */ - adcFreq = samplingFrequency - ifFreqActual; - adcFlip = true; - } else { - /* adc doesn't mirror */ - adcFreq = ifFreqActual; - adcFlip = false; - } - - frequencyShift = adcFreq; - imageToSelect = state->m_rfmirror ^ tunerMirror ^ - adcFlip ^ selectPosImage; - state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency); - - if (imageToSelect) - state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; - - /* Program frequency shifter with tuner offset compensation */ - /* frequencyShift += tunerFreqOffset; TODO */ - status = Write32(state, IQM_FS_RATE_OFS_LO__A , - state->m_IqmFsRateOfs, 0); - return status; -} - -static int InitAGC(struct drxk_state *state, bool isDTV) -{ - u16 ingainTgt = 0; - u16 ingainTgtMin = 0; - u16 ingainTgtMax = 0; - u16 clpCyclen = 0; - u16 clpSumMin = 0; - u16 clpDirTo = 0; - u16 snsSumMin = 0; - u16 snsSumMax = 0; - u16 clpSumMax = 0; - u16 snsDirTo = 0; - u16 kiInnergainMin = 0; - u16 ifIaccuHiTgt = 0; - u16 ifIaccuHiTgtMin = 0; - u16 ifIaccuHiTgtMax = 0; - u16 data = 0; - u16 fastClpCtrlDelay = 0; - u16 clpCtrlMode = 0; - int status = 0; - - do { - /* Common settings */ - snsSumMax = 1023; - ifIaccuHiTgtMin = 2047; - clpCyclen = 500; - clpSumMax = 1023; - - if (IsQAM(state)) { - /* Standard specific settings */ - clpSumMin = 8; - clpDirTo = (u16) - 9; - clpCtrlMode = 0; - snsSumMin = 8; - snsDirTo = (u16) - 9; - kiInnergainMin = (u16) - 1030; - } else - status = -1; - CHK_ERROR((status)); - if (IsQAM(state)) { - ifIaccuHiTgtMax = 0x2380; - ifIaccuHiTgt = 0x2380; - ingainTgtMin = 0x0511; - ingainTgt = 0x0511; - ingainTgtMax = 5119; - fastClpCtrlDelay = - state->m_qamIfAgcCfg.FastClipCtrlDelay; - } else { - ifIaccuHiTgtMax = 0x1200; - ifIaccuHiTgt = 0x1200; - ingainTgtMin = 13424; - ingainTgt = 13424; - ingainTgtMax = 30000; - fastClpCtrlDelay = - state->m_dvbtIfAgcCfg.FastClipCtrlDelay; - } - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, - fastClpCtrlDelay)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, - clpCtrlMode)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, - ingainTgt)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, - ingainTgtMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, - ingainTgtMax)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, - ifIaccuHiTgtMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, - ifIaccuHiTgtMax)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, - clpSumMax)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, - snsSumMax)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, - kiInnergainMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, - ifIaccuHiTgt)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, - clpCyclen)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, - 1023)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, - (u16) -1023)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, - 50)); - - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, - 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, - clpSumMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, - snsSumMin)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, - clpDirTo)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, - snsDirTo)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); - - /* Initialize inner-loop KI gain factors */ - CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); - if (IsQAM(state)) { - data = 0x0657; - data &= ~SCU_RAM_AGC_KI_RF__M; - data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); - data &= ~SCU_RAM_AGC_KI_IF__M; - data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); - } - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); - } while(0); - return status; -} - -static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr) -{ - int status; - - do { - if (packetErr == NULL) { - CHK_ERROR(Write16_0(state, - SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, - 0)); - } else { - CHK_ERROR(Read16_0(state, - SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, - packetErr)); - } - } while (0); - return status; -} - -static int DVBTScCommand(struct drxk_state *state, - u16 cmd, u16 subcmd, - u16 param0, u16 param1, u16 param2, - u16 param3, u16 param4) -{ - u16 curCmd = 0; - u16 errCode = 0; - u16 retryCnt = 0; - u16 scExec = 0; - int status; - - status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); - if (scExec != 1) { - /* SC is not running */ - return -1; - } - - /* Wait until sc is ready to receive command */ - retryCnt =0; - do { - msleep(1); - status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); - retryCnt++; - } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); - if (retryCnt >= DRXK_MAX_RETRIES) - return -1; - /* Write sub-command */ - switch (cmd) { - /* All commands using sub-cmd */ - case OFDM_SC_RA_RAM_CMD_PROC_START: - case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: - case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: - status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); - break; - default: - /* Do nothing */ - break; - } /* switch (cmd->cmd) */ - - /* Write needed parameters and the command */ - switch (cmd) { - /* All commands using 5 parameters */ - /* All commands using 4 parameters */ - /* All commands using 3 parameters */ - /* All commands using 2 parameters */ - case OFDM_SC_RA_RAM_CMD_PROC_START: - case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: - case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: - status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); - /* All commands using 1 parameters */ - case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: - case OFDM_SC_RA_RAM_CMD_USER_IO: - status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); - /* All commands using 0 parameters */ - case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: - case OFDM_SC_RA_RAM_CMD_NULL: - /* Write command */ - status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); - break; - default: - /* Unknown command */ - return -EINVAL; - } /* switch (cmd->cmd) */ - - /* Wait until sc is ready processing command */ - retryCnt = 0; - do{ - msleep(1); - status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); - retryCnt++; - } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); - if (retryCnt >= DRXK_MAX_RETRIES) - return -1; - - /* Check for illegal cmd */ - status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); - if (errCode == 0xFFFF) - { - /* illegal command */ - return -EINVAL; - } - - /* Retreive results parameters from SC */ - switch (cmd) { - /* All commands yielding 5 results */ - /* All commands yielding 4 results */ - /* All commands yielding 3 results */ - /* All commands yielding 2 results */ - /* All commands yielding 1 result */ - case OFDM_SC_RA_RAM_CMD_USER_IO: - case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: - status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); - /* All commands yielding 0 results */ - case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: - case OFDM_SC_RA_RAM_CMD_SET_TIMER: - case OFDM_SC_RA_RAM_CMD_PROC_START: - case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: - case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: - case OFDM_SC_RA_RAM_CMD_NULL: - break; - default: - /* Unknown command */ - return -EINVAL; - break; - } /* switch (cmd->cmd) */ - return status; -} - -static int PowerUpDVBT (struct drxk_state *state) -{ - DRXPowerMode_t powerMode = DRX_POWER_UP; - int status; - - do { - CHK_ERROR(CtrlPowerMode(state, &powerMode)); - } while (0); - return status; -} - -static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled) -{ - int status; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - if (*enabled == true) - { - status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); - } - else - { - status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); - } - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - #define DEFAULT_FR_THRES_8K 4000 -static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled) -{ - - int status; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - if (*enabled == true) - { - /* write mask to 1 */ - status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, - DEFAULT_FR_THRES_8K); - } - else - { - /* write mask to 0 */ - status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); - } - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - -static int DVBTCtrlSetEchoThreshold (struct drxk_state *state, - struct DRXKCfgDvbtEchoThres_t* echoThres) -{ - u16 data = 0; - int status; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - do { - CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); - - switch (echoThres->fftMode) - { - case DRX_FFTMODE_2K: - data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M; - data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) & - (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); - break; - case DRX_FFTMODE_8K: - data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M; - data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & - (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); - break; - default: - return -1; - break; - } - - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); - } while (0); - - if (status<0) - { - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - -static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, - enum DRXKCfgDvbtSqiSpeed* speed) -{ - int status; - - switch (*speed) { - case DRXK_DVBT_SQI_SPEED_FAST: - case DRXK_DVBT_SQI_SPEED_MEDIUM: - case DRXK_DVBT_SQI_SPEED_SLOW: - break; - default: - return -EINVAL; - } - status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, - (u16) *speed); - return status; -} - -/*============================================================================*/ - -/** -* \brief Activate DVBT specific presets -* \param demod instance of demodulator. -* \return DRXStatus_t. -* -* Called in DVBTSetStandard -* -*/ -static int DVBTActivatePresets (struct drxk_state *state) -{ - int status; - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K}; - struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K}; - - do { - bool setincenable = false; - bool setfrenable = true; - CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable)); - CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable)); - CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); - CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, - state->m_dvbtIfAgcCfg.IngainTgtMax)); - } while (0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} -/*============================================================================*/ - -/** -* \brief Initialize channelswitch-independent settings for DVBT. -* \param demod instance of demodulator. -* \return DRXStatus_t. -* -* For ROM code channel filter taps are loaded from the bootloader. For microcode -* the DVB-T taps from the drxk_filters.h are used. -*/ -static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode) -{ - u16 cmdResult = 0; - u16 data = 0; - int status; - - //printk("%s\n", __FUNCTION__); - - PowerUpDVBT(state); - - do { - /* added antenna switch */ - SwitchAntennaToDVBT(state); - /* send OFDM reset command */ - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); - - /* send OFDM setenv command */ - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult)); - - /* reset datapath for OFDM, processors first */ - CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP )); - - /* IQM setup */ - /* synchronize on ofdstate->m_festart */ - CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); - /* window size for clipping ADC detection */ - CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); - /* window size for for sense pre-SAW detection */ - CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); - /* sense threshold for sense pre-SAW detection */ - CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); - CHK_ERROR(SetIqmAf(state,true)); - - CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); - - /* Impulse noise cruncher setup */ - CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ - CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ - CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ - - CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); - CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ - CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ - CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); - CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); - - /* virtual clipping threshold for clipping ADC detection */ - CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); - CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ - - CHK_ERROR(BLChainCmd(state, - DRXK_BL_ROM_OFFSET_TAPS_DVBT, - DRXK_BLCC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - - CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ - CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); - /* enable power measurement interrupt */ - CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); - - /* IQM will not be reset from here, sync ADC and update/init AGC */ - CHK_ERROR(ADCSynchronization(state)); - CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ; - CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true)); - - /* Set Noise Estimation notch width and enable DC fix */ - CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data)); - data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data)); - - /* Activate SCU to enable SCU commands */ - CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - - if (!state->m_DRXK_A3_ROM_CODE) - { - /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ - CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, - state->m_dvbtIfAgcCfg.FastClipCtrlDelay)); - } - - /* OFDM_SC setup */ -#ifdef COMPILE_FOR_NONRT - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); -#endif - - /* FEC setup */ - CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ - - -#ifdef COMPILE_FOR_NONRT - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400)); -#else - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000)); -#endif - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001)); - - /* Setup MPEG bus */ - CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT)); - /* Set DVBT Presets */ - CHK_ERROR (DVBTActivatePresets (state)); - - } while (0); - - if (status<0) - { - printk("%s status - %08x\n",__FUNCTION__,status); - } - - return status; -} - -/*============================================================================*/ -/** -* \brief Start dvbt demodulating for channel. -* \param demod instance of demodulator. -* \return DRXStatus_t. -*/ -static int DVBTStart(struct drxk_state *state) -{ - u16 param1; - - int status; -// DRXKOfdmScCmd_t scCmd; - - //printk("%s\n",__FUNCTION__); - /* Start correct processes to get in lock */ - /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ - do { - param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; - CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0)); - /* Start FEC OC */ - CHK_ERROR(MPEGTSStart(state)); - CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); - } while (0); - return (status); -} - - -/*============================================================================*/ - -/** -* \brief Set up dvbt demodulator for channel. -* \param demod instance of demodulator. -* \return DRXStatus_t. -* // original DVBTSetChannel() -*/ -static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) -{ - u16 cmdResult = 0; - u16 transmissionParams = 0; - u16 operationMode = 0; - u32 iqmRcRateOfs = 0; - u32 bandwidth = 0; - u16 param1; - int status; - - //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset); - do { - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | - SCU_RAM_COMMAND_CMD_DEMOD_STOP, - 0,NULL,1,&cmdResult)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - /* Stop processors */ - CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); - - /* Mandatory fix, always stop CP, required to set spl offset back to - hardware default (is set to 0 by ucode during pilot detection */ - CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP)); - - /*== Write channel settings to device =====================================*/ - - /* mode */ -#ifndef USE_API3 - switch(state->props.transmission_mode) { -#else - switch(state->param.u.ofdm.transmission_mode) { -#endif - case TRANSMISSION_MODE_AUTO: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; - /* fall through , try first guess DRX_FFTMODE_8K */ - case TRANSMISSION_MODE_8K: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; - break; - case TRANSMISSION_MODE_2K: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; - break; - } - - /* guard */ -#ifndef USE_API3 - switch(state->props.guard_interval) { -#else - switch(state->param.u.ofdm.guard_interval) { -#endif - default: - case GUARD_INTERVAL_AUTO: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; - /* fall through , try first guess DRX_GUARD_1DIV4 */ - case GUARD_INTERVAL_1_4: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; - break; - case GUARD_INTERVAL_1_32: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; - break; - case GUARD_INTERVAL_1_16: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; - break; - case GUARD_INTERVAL_1_8: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; - break; - } - - /* hierarchy */ -#ifndef USE_API3 - switch(state->props.hierarchy) { -#else - switch(state->param.u.ofdm.hierarchy_information) { -#endif - case HIERARCHY_AUTO: - case HIERARCHY_NONE: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; - /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ - // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; - //break; - case HIERARCHY_1: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; - break; - case HIERARCHY_2: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; - break; - case HIERARCHY_4: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; - break; - } - - - /* constellation */ -#ifndef USE_API3 - switch(state->props.modulation) { -#else - switch(state->param.u.ofdm.constellation) { -#endif - case QAM_AUTO: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; - /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ - case QAM_64: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; - break; - case QPSK: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; - break; - case QAM_16: - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; - break; - } -#if 0 - // No hierachical channels support in BDA - /* Priority (only for hierarchical channels) */ - switch (channel->priority) { - case DRX_PRIORITY_LOW : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; - WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO); - break; - case DRX_PRIORITY_HIGH : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; - WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); - break; - case DRX_PRIORITY_UNKNOWN : /* fall through */ - default: - return (DRX_STS_INVALID_ARG); - break; - } -#else - // Set Priorty high - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; - CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); -#endif - - /* coderate */ -#ifndef USE_API3 - switch(state->props.code_rate_HP) { -#else - switch(state->param.u.ofdm.code_rate_HP) { -#endif - case FEC_AUTO: - default: - operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; - /* fall through , try first guess DRX_CODERATE_2DIV3 */ - case FEC_2_3 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; - break; - case FEC_1_2 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; - break; - case FEC_3_4 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; - break; - case FEC_5_6 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; - break; - case FEC_7_8 : - transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; - break; - } - - /* SAW filter selection: normaly not necesarry, but if wanted - the application can select a SAW filter via the driver by using UIOs */ - /* First determine real bandwidth (Hz) */ - /* Also set delay for impulse noise cruncher */ - /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed - by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC - functions */ -#ifndef USE_API3 - switch(state->props.bandwidth_hz) { -#else - switch(state->param.u.ofdm.bandwidth) { -#endif -#ifndef USE_API3 - case 0: - case 8000000: -#else - case BANDWIDTH_AUTO: - case BANDWIDTH_8_MHZ: -#endif - bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052)); - /* cochannel protection for PAL 8 MHz */ - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); - break; -#ifndef USE_API3 - case 7000000: -#else - case BANDWIDTH_7_MHZ: -#endif - bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491)); - /* cochannel protection for PAL 7 MHz */ - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); - break; -#ifndef USE_API3 - case 6000000: -#else - case BANDWIDTH_6_MHZ: -#endif - bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073)); - /* cochannel protection for NTSC 6 MHz */ - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14)); - CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); - break; - } - - if (iqmRcRateOfs == 0) - { - /* Now compute IQM_RC_RATE_OFS - (((SysFreq/BandWidth)/2)/2) -1) * 2^23) - => - ((SysFreq / BandWidth) * (2^21)) - (2^23) - */ - /* (SysFreq / BandWidth) * (2^28) */ - /* assert (MAX(sysClk)/MIN(bandwidth) < 16) - => assert(MAX(sysClk) < 16*MIN(bandwidth)) - => assert(109714272 > 48000000) = true so Frac 28 can be used */ - iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth); - /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ - if ((iqmRcRateOfs & 0x7fL) >= 0x40) - { - iqmRcRateOfs += 0x80L; - } - iqmRcRateOfs = iqmRcRateOfs >> 7 ; - /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ - iqmRcRateOfs = iqmRcRateOfs - (1<<23); - } - - iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<m_DRXK_A3_ROM_CODE) - CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed)); - - } while(0); - if (status<0) { - //printk("%s status - %08x\n",__FUNCTION__,status); - } - - return status; -} - - -/*============================================================================*/ - -/** -* \brief Retreive lock status . -* \param demod Pointer to demodulator instance. -* \param lockStat Pointer to lock status structure. -* \return DRXStatus_t. -* -*/ -static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) -{ - int status; - const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | - OFDM_SC_RA_RAM_LOCK_FEC__M ); - const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); - const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ; - - u16 ScRaRamLock = 0; - u16 ScCommExec = 0; - - /* driver 0.9.0 */ - /* Check if SC is running */ - status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); - if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) - { - /* SC not active; return DRX_NOT_LOCKED */ - *pLockStatus = NOT_LOCKED; - return status; - } - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - - status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock)); - - if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { - *pLockStatus = MPEG_LOCK; - } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) { - *pLockStatus = FEC_LOCK; - } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) { - *pLockStatus = DEMOD_LOCK; - } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) { - *pLockStatus = NEVER_LOCK; - } else { - *pLockStatus = NOT_LOCKED; - } - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - - return status; -} - -static int PowerUpQAM (struct drxk_state *state) -{ - DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; - - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - CHK_ERROR(CtrlPowerMode(state, &powerMode)); - - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - - -/// Power Down QAM -static int PowerDownQAM(struct drxk_state *state) -{ - u16 data = 0; - u16 cmdResult; - - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); - if (data == SCU_COMM_EXEC_ACTIVE) - { - /* - STOP demodulator - QAM and HW blocks - */ - /* stop all comstate->m_exec */ - CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult)); - } - /* powerdown AFE */ - CHK_ERROR(SetIqmAf(state, false)); - } - while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} -/*============================================================================*/ - -/** -* \brief Setup of the QAM Measurement intervals for signal quality -* \param demod instance of demod. -* \param constellation current constellation. -* \return DRXStatus_t. -* -* NOTE: -* Take into account that for certain settings the errorcounters can overflow. -* The implementation does not check this. -* -*/ -static int SetQAMMeasurement(struct drxk_state *state, - enum EDrxkConstellation constellation, - u32 symbolRate) -{ - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode)); - - u32 fecBitsDesired = 0; /* BER accounting period */ - u32 fecRsPeriodTotal = 0; /* Total period */ - u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ - u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ - int status = 0; - - fecRsPrescale = 1; - - do { - - /* fecBitsDesired = symbolRate [kHz] * - FrameLenght [ms] * - (constellation + 1) * - SyncLoss (== 1) * - ViterbiLoss (==1) - */ - switch (constellation) - { - case DRX_CONSTELLATION_QAM16: - fecBitsDesired = 4 * symbolRate; - break; - case DRX_CONSTELLATION_QAM32: - fecBitsDesired = 5 * symbolRate; - break; - case DRX_CONSTELLATION_QAM64: - fecBitsDesired = 6 * symbolRate; - break; - case DRX_CONSTELLATION_QAM128: - fecBitsDesired = 7 * symbolRate; - break; - case DRX_CONSTELLATION_QAM256: - fecBitsDesired = 8 * symbolRate; - break; - default: - status = -EINVAL; - } - CHK_ERROR(status); - - fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ - fecBitsDesired *= 500; /* meas. period [ms] */ - - /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ - /* fecRsPeriodTotal = fecBitsDesired / 1632 */ - fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/ - - /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ - fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); - if (fecRsPrescale == 0) { - /* Divide by zero (though impossible) */ - status = -1; - } - CHK_ERROR(status); - fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) / - fecRsPrescale; - - /* write corresponding registers */ - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod)); - CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale)); - CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); - - } while (0); - - if (status<0) { - printk("%s: status - %08x\n",__FUNCTION__,status); - } - return status; -} - -static int SetQAM16 (struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16)); - - /* QAM Loop Controller Coeficients */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM32 specific setup -* \param demod instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM32 (struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM64 specific setup -* \param demod instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM64 (struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM128 specific setup -* \param demod: instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM128(struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - - /* QAM Slicer Settings */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - -/*============================================================================*/ - -/** -* \brief QAM256 specific setup -* \param demod: instance of demod. -* \return DRXStatus_t. -*/ -static int SetQAM256(struct drxk_state *state) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - do - { - /* QAM Equalizer Setup */ - /* Equalizer */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); - - /* Decision Feedback Equalizer */ - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); - CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); - - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); - CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); - - /* QAM Slicer Settings */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256)); - - - /* QAM Loop Controller Coeficients */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); - - - /* QAM State Machine (FSM) Thresholds */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); - - - /* QAM FSM Tracking Parameters */ - - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0)); - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8)); - }while(0); - - if (status<0) - { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - } - return status; -} - - -/*============================================================================*/ -/** -* \brief Reset QAM block. -* \param demod: instance of demod. -* \param channel: pointer to channel data. -* \return DRXStatus_t. -*/ -static int QAMResetQAM(struct drxk_state *state) -{ - int status; - u16 cmdResult; - - //printk("%s\n", __FUNCTION__); - do - { - /* Stop QAM comstate->m_exec */ - CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); - - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); - } while (0); - - /* All done, all OK */ - return status; -} - -/*============================================================================*/ - -/** -* \brief Set QAM symbolrate. -* \param demod: instance of demod. -* \param channel: pointer to channel data. -* \return DRXStatus_t. -*/ -static int QAMSetSymbolrate(struct drxk_state *state) -{ - u32 adcFrequency = 0; - u32 symbFreq = 0; - u32 iqmRcRate = 0; - u16 ratesel = 0; - u32 lcSymbRate = 0; - int status; - u32 srate = -#ifndef USE_API3 - state->props.symbol_rate; -#else - state->param.u.qam.symbol_rate; -#endif - - do - { - /* Select & calculate correct IQM rate */ - adcFrequency = (state->m_sysClockFreq * 1000) / 3; - ratesel = 0; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate)); - //printk("SR %d\n", state->param.u.qam.symbol_rate); - if (srate <= 1188750) - { - ratesel = 3; - } - else if (srate <= 2377500) - { - ratesel = 2; - } - else if (srate <= 4755000) - { - ratesel = 1; - } - CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel)); - - /* - IqmRcRate = ((Fadc / (symbolrate * (4<> 7) - - (1 << 23); - CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0)); - state->m_iqmRcRate = iqmRcRate; - /* - LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) - */ - symbFreq = srate; - if (adcFrequency == 0) - { - /* Divide by zero */ - return -1; - } - lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + - (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16); - if (lcSymbRate > 511) - { - lcSymbRate = 511; - } - CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate)); - } while (0); - - return status; -} - -/*============================================================================*/ - -/** -* \brief Get QAM lock status. -* \param demod: instance of demod. -* \param channel: pointer to channel data. -* \return DRXStatus_t. -*/ - -static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) -{ - int status; - u16 Result[2] = {0,0}; - - status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result); - if (status<0) - { - printk("%s status = %08x\n",__FUNCTION__,status); - } - if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) - { - /* 0x0000 NOT LOCKED */ - *pLockStatus = NOT_LOCKED; - } - else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) - { - /* 0x4000 DEMOD LOCKED */ - *pLockStatus = DEMOD_LOCK; - } - else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) - { - /* 0x8000 DEMOD + FEC LOCKED (system lock) */ - *pLockStatus = MPEG_LOCK; - } - else - { - /* 0xC000 NEVER LOCKED */ - /* (system will never be able to lock to the signal) */ - /* TODO: check this, intermediate & standard specific lock states are not - taken into account here */ - *pLockStatus = NEVER_LOCK; - } - return status; -} - -#define QAM_MIRROR__M 0x03 -#define QAM_MIRROR_NORMAL 0x00 -#define QAM_MIRRORED 0x01 -#define QAM_MIRROR_AUTO_ON 0x02 -#define QAM_LOCKRANGE__M 0x10 -#define QAM_LOCKRANGE_NORMAL 0x10 - -static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) -{ - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - int status = 0; - u8 parameterLen; - u16 setEnvParameters[5]; - u16 setParamParameters[4]={0,0,0,0}; - u16 cmdResult; - - //printk("%s\n", __FUNCTION__); - - do { - /* - STEP 1: reset demodulator - resets FEC DI and FEC RS - resets QAM block - resets SCU variables - */ - CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP)); - CHK_ERROR(QAMResetQAM(state)); - - /* - STEP 2: configure demodulator - -set env - -set params; resets IQM,QAM,FEC HW; initializes some SCU variables - */ - CHK_ERROR(QAMSetSymbolrate(state)); - - /* Env parameters */ - setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ - if (state->m_OperationMode == OM_QAM_ITU_C) - { - setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ - } - setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); -// check for LOCKRANGE Extented - // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; - parameterLen = 4; - - /* Set params */ -#ifndef USE_API3 - switch(state->props.modulation) -#else - switch(state->param.u.qam.modulation) -#endif - { - case QAM_256: - state->m_Constellation = DRX_CONSTELLATION_QAM256; - break; - case QAM_AUTO: - case QAM_64: - state->m_Constellation = DRX_CONSTELLATION_QAM64; - break; - case QAM_16: - state->m_Constellation = DRX_CONSTELLATION_QAM16; - break; - case QAM_32: - state->m_Constellation = DRX_CONSTELLATION_QAM32; - break; - case QAM_128: - state->m_Constellation = DRX_CONSTELLATION_QAM128; - break; - default: - status = -EINVAL; - break; - } - CHK_ERROR(status); - setParamParameters[0] = state->m_Constellation; /* constellation */ - setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ - - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult)); - - - /* STEP 3: enable the system in a mode where the ADC provides valid signal - setup constellation independent registers */ -// CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); - CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true)); - - /* Setup BER measurement */ - CHK_ERROR(SetQAMMeasurement (state, - state->m_Constellation, -#ifndef USE_API3 - state->props.symbol_rate)); -#else - state->param.u.qam.symbol_rate)); -#endif - - /* Reset default values */ - CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE)); - CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); - - /* Reset default LC values */ - CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); - CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); - CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); - CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); - - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); - CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); - - /* Mirroring, QAM-block starting point not inverted */ - CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - /* STEP 4: constellation specific setup */ -#ifndef USE_API3 - switch (state->props.modulation) -#else - switch (state->param.u.qam.modulation) -#endif - { - case QAM_16: - CHK_ERROR(SetQAM16(state)); - break; - case QAM_32: - CHK_ERROR(SetQAM32(state)); - break; - case QAM_AUTO: - case QAM_64: - CHK_ERROR(SetQAM64(state)); - break; - case QAM_128: - CHK_ERROR(SetQAM128(state)); - break; - case QAM_256: - //printk("SETQAM256\n"); - CHK_ERROR(SetQAM256(state)); - break; - default: - return -1; - break; - } /* switch */ - /* Activate SCU to enable SCU commands */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - - - /* Re-configure MPEG output, requires knowledge of channel bitrate */ -// extAttr->currentChannel.constellation = channel->constellation; -// extAttr->currentChannel.symbolrate = channel->symbolrate; - CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); - - /* Start processes */ - CHK_ERROR(MPEGTSStart(state)); - CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); - CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); - - /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ - CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_START,0, - NULL,1,&cmdResult)); - - /* update global DRXK data container */ -//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; - - /* All done, all OK */ - } while(0); - - if (status<0) { - printk("%s %d\n", __FUNCTION__, status); - } - return status; -} - -static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode) -{ -#ifdef DRXK_QAM_TAPS -#define DRXK_QAMA_TAPS_SELECT -#include "drxk_filters.h" -#undef DRXK_QAMA_TAPS_SELECT -#else - int status; -#endif - - //printk("%s\n", __FUNCTION__); - do - { - /* added antenna switch */ - SwitchAntennaToQAM(state); - - /* Ensure correct power-up mode */ - CHK_ERROR(PowerUpQAM(state)); - /* Reset QAM block */ - CHK_ERROR(QAMResetQAM(state)); - - /* Setup IQM */ - - CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); - CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); - - /* Upload IQM Channel Filter settings by - boot loader from ROM table */ - switch (oMode) - { - case OM_QAM_ITU_A: - CHK_ERROR(BLChainCmd(state, - DRXK_BL_ROM_OFFSET_TAPS_ITU_A, - DRXK_BLCC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - break; - case OM_QAM_ITU_C: - CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, - DRXK_BL_ROM_OFFSET_TAPS_ITU_C, - DRXK_BLDC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, - DRXK_BL_ROM_OFFSET_TAPS_ITU_C, - DRXK_BLDC_NR_ELEMENTS_TAPS, - DRXK_BLC_TIMEOUT)); - break; - default: - status=-EINVAL; - } - CHK_ERROR (status); - - CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, - (1 << IQM_CF_OUT_ENA_QAM__B))); - CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); - CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, - ((1 << IQM_CF_MIDTAP_RE__B) | - (1 << IQM_CF_MIDTAP_IM__B)))); - - CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); - CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); - CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); - CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); - CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); - - CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); - CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); - CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); - CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); - - /* IQM Impulse Noise Processing Unit */ - CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); - CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); - CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); - CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); - CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); - CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); - CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); - - /* turn on IQMAF. Must be done before setAgc**() */ - CHK_ERROR(SetIqmAf(state, true)); - CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); - - /* IQM will not be reset from here, sync ADC and update/init AGC */ - CHK_ERROR(ADCSynchronization (state)); - - /* Set the FSM step period */ - CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); - - /* Halt SCU to enable safe non-atomic accesses */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); - - /* No more resets of the IQM, current standard correctly set => - now AGCs can be configured. */ - - CHK_ERROR(InitAGC(state,true)); - CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); - - /* Configure AGC's */ - CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); - CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true)); - - /* Activate SCU to enable SCU commands */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - } while (0); - return status; -} - -static int WriteGPIO(struct drxk_state *state) -{ - int status; - u16 value = 0; - - do { - /* stop lock indicator process */ - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, - SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - - /* Write magic word to enable pdr reg write */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, - SIO_TOP_COMM_KEY_KEY)); - - if (state->m_hasSAWSW) { - /* write to io pad configuration register - output mode */ - CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, - state->m_GPIOCfg)); - - /* use corresponding bit in io data output registar */ - CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value)); - if (state->m_GPIO == 0) { - value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ - } else { - value |= 0x8000; /* write one to 15th bit - 1st UIO */ - } - /* write back to io data output register */ - CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value)); - - } - /* Write magic word to disable pdr reg write */ - CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); - } while (0); - return status; -} - -static int SwitchAntennaToQAM(struct drxk_state *state) -{ - int status = -1; - - if (state->m_AntennaSwitchDVBTDVBC != 0) { - if (state->m_GPIO != state->m_AntennaDVBC) { - state->m_GPIO = state->m_AntennaDVBC; - status = WriteGPIO(state); - } - } - return status; -} - -static int SwitchAntennaToDVBT(struct drxk_state *state) -{ - int status = -1; - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); - if (state->m_AntennaSwitchDVBTDVBC != 0) { - if (state->m_GPIO != state->m_AntennaDVBT) { - state->m_GPIO = state->m_AntennaDVBT; - status = WriteGPIO(state); - } - } - return status; -} - - -static int PowerDownDevice(struct drxk_state *state) -{ - /* Power down to requested mode */ - /* Backup some register settings */ - /* Set pins with possible pull-ups connected to them in input mode */ - /* Analog power down */ - /* ADC power down */ - /* Power down device */ - int status; - do { - if (state->m_bPDownOpenBridge) { - // Open I2C bridge before power down of DRXK - CHK_ERROR(ConfigureI2CBridge(state, true)); - } - // driver 0.9.0 - CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); - - CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY)); - state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - CHK_ERROR(HI_CfgCommand(state)); - } - while(0); - - if (status<0) { - //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); - return -1; - } - return 0; -} - -static int load_microcode(struct drxk_state *state, char *mc_name) -{ - const struct firmware *fw = NULL; - int err=0; - - err = request_firmware(&fw, mc_name, state->i2c->dev.parent); - if (err < 0) { - printk(KERN_ERR - ": Could not load firmware file %s.\n", mc_name); - printk(KERN_INFO - ": Copy %s to your hotplug directory!\n", mc_name); - return err; - } - err=DownloadMicrocode(state, fw->data, fw->size); - release_firmware(fw); - return err; -} - -static int init_drxk(struct drxk_state *state) -{ - int status; - DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; - u16 driverVersion; - - //printk("init_drxk\n"); - if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { - do { - CHK_ERROR(PowerUpDevice(state)); - CHK_ERROR (DRXX_Open(state)); - /* Soft reset of OFDM-, sys- and osc-clockdomain */ - CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, - SIO_CC_SOFT_RST_OFDM__M | - SIO_CC_SOFT_RST_SYS__M | - SIO_CC_SOFT_RST_OSC__M)); - CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); - /* TODO is this needed, if yes how much delay in worst case scenario */ - msleep(1); - state->m_DRXK_A3_PATCH_CODE = true; - CHK_ERROR(GetDeviceCapabilities(state)); - - /* Bridge delay, uses oscilator clock */ - /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ - /* SDA brdige delay */ - state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000; - /* Clipping */ - if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) - { - state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; - } - /* SCL bridge delay, same as SDA for now */ - state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; - - CHK_ERROR(InitHI(state)); - /* disable various processes */ -#if NOA1ROM - if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) ) -#endif - { - CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); - } - - /* disable MPEG port */ - CHK_ERROR(MPEGTSDisable(state)); - - /* Stop AUD and SCU */ - CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP)); - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP)); - - /* enable token-ring bus through OFDM block for possible ucode upload */ - CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); - - /* include boot loader section */ - CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE)); - CHK_ERROR(BLChainCmd(state, 0, 6, 100)); - -#if 0 - if (state->m_DRXK_A3_PATCH_CODE) - CHK_ERROR(DownloadMicrocode(state, - DRXK_A3_microcode, - DRXK_A3_microcode_length)); -#else - load_microcode(state, "drxk_a3.mc"); -#endif -#if NOA1ROM - if (state->m_DRXK_A2_PATCH_CODE) - CHK_ERROR(DownloadMicrocode(state, - DRXK_A2_microcode, - DRXK_A2_microcode_length)); -#endif - /* disable token-ring bus through OFDM block for possible ucode upload */ - CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); - - /* Run SCU for a little while to initialize microcode version numbers */ - CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); - CHK_ERROR (DRXX_Open(state)); - // added for test - msleep(30); - - powerMode = DRXK_POWER_DOWN_OFDM; - CHK_ERROR(CtrlPowerMode(state, &powerMode)); - - /* Stamp driver version number in SCU data RAM in BCD code - Done to enable field application engineers to retreive drxdriver version - via I2C from SCU RAM. - Not using SCU command interface for SCU register access since no - microcode may be present. - */ - driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) + - (((DRXK_VERSION_MAJOR/10) % 10) << 8) + - ((DRXK_VERSION_MAJOR%10) << 4) + - (DRXK_VERSION_MINOR%10); - CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion )); - driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) + - (((DRXK_VERSION_PATCH/100) % 10) << 8) + - (((DRXK_VERSION_PATCH/10) % 10) << 4) + - (DRXK_VERSION_PATCH%10); - CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion )); - - printk("DRXK driver version:%d.%d.%d\n", - DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH); - - /* Dirty fix of default values for ROM/PATCH microcode - Dirty because this fix makes it impossible to setup suitable values - before calling DRX_Open. This solution requires changes to RF AGC speed - to be done via the CTRL function after calling DRX_Open */ - - // m_dvbtRfAgcCfg.speed=3; - - /* Reset driver debug flags to 0 */ - CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0)); - /* driver 0.9.0 */ - /* Setup FEC OC: - NOTE: No more full FEC resets allowed afterwards!! */ - CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP)); - // MPEGTS functions are still the same - CHK_ERROR(MPEGTSDtoInit(state)); - CHK_ERROR(MPEGTSStop(state)); - CHK_ERROR(MPEGTSConfigurePolarity(state)); - CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput)); - // added: configure GPIO - CHK_ERROR(WriteGPIO(state)); - - state->m_DrxkState = DRXK_STOPPED; - - if (state->m_bPowerDown) { - CHK_ERROR(PowerDownDevice(state)); - state->m_DrxkState = DRXK_POWERED_DOWN; - } - else - state->m_DrxkState = DRXK_STOPPED; - } while(0); - //printk("%s=%d\n", __FUNCTION__, status); - } - else - { - //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n")); - } - - return 0; -} - -static void drxk_c_release(struct dvb_frontend* fe) -{ - struct drxk_state *state=fe->demodulator_priv; - printk("%s\n", __FUNCTION__); - kfree(state); -} - -static int drxk_c_init (struct dvb_frontend *fe) -{ - struct drxk_state *state=fe->demodulator_priv; - - if (mutex_trylock(&state->ctlock)==0) - return -EBUSY; - SetOperationMode(state, OM_QAM_ITU_A); - return 0; -} - -static int drxk_c_sleep(struct dvb_frontend* fe) -{ - struct drxk_state *state=fe->demodulator_priv; - - ShutDown(state); - mutex_unlock(&state->ctlock); - return 0; -} - -static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable) -{ - struct drxk_state *state = fe->demodulator_priv; - - //printk("drxk_gate %d\n", enable); - return ConfigureI2CBridge(state, enable ? true : false); -} - -#ifndef USE_API3 -static int drxk_set_parameters (struct dvb_frontend *fe) -#else -static int drxk_set_parameters (struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) -#endif -{ -#ifndef USE_API3 - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - u32 delsys = p->delivery_system, old_delsys; -#endif - struct drxk_state *state = fe->demodulator_priv; - u32 IF; - - //printk("%s\n", __FUNCTION__); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - if (fe->ops.tuner_ops.set_params) -#ifndef USE_API3 - fe->ops.tuner_ops.set_params(fe); -#else - fe->ops.tuner_ops.set_params(fe, p); -#endif - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); -#ifndef USE_API3 -#else - state->param=*p; -#endif - fe->ops.tuner_ops.get_if_frequency(fe, &IF); /* WTF is a frequency frequency? */ - Start(state, 0, IF); - - //printk("%s IF=%d done\n", __FUNCTION__, IF); - return 0; -} - -static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct drxk_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct drxk_state *state = fe->demodulator_priv; - u32 stat; - - *status=0; - GetLockStatus(state, &stat, 0); - if (stat==MPEG_LOCK) - *status|=0x1f; - if (stat==FEC_LOCK) - *status|=0x0f; - if (stat==DEMOD_LOCK) - *status|=0x07; - return 0; -} - -static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - //struct drxk_state *state = fe->demodulator_priv; - *ber=0; - return 0; -} - -static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - struct drxk_state *state = fe->demodulator_priv; - u32 val; - - ReadIFAgc(state, &val); - *strength = val & 0xffff;; - return 0; -} - -static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct drxk_state *state = fe->demodulator_priv; - s32 snr2; - - GetSignalToNoise(state, &snr2); - *snr = snr2&0xffff; - return 0; -} - -static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct drxk_state *state = fe->demodulator_priv; - u16 err; - - DVBTQAMGetAccPktErr(state, &err); - *ucblocks = (u32) err; - return 0; -} - -static int drxk_c_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) -{ - sets->min_delay_ms=3000; - sets->max_drift=0; - sets->step_size=0; - return 0; -} - -static void drxk_t_release(struct dvb_frontend* fe) -{ - //struct drxk_state *state=fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - //kfree(state); -} - -static int drxk_t_init (struct dvb_frontend *fe) -{ - struct drxk_state *state=fe->demodulator_priv; - if (mutex_trylock(&state->ctlock)==0) - return -EBUSY; - //printk("%s\n", __FUNCTION__); - SetOperationMode(state, OM_DVBT); - //printk("%s done\n", __FUNCTION__); - return 0; -} - -static int drxk_t_sleep(struct dvb_frontend* fe) -{ - struct drxk_state *state=fe->demodulator_priv; - mutex_unlock(&state->ctlock); - return 0; -} - -static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct drxk_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static struct dvb_frontend_ops drxk_c_ops = { - .info = { - .name = "DRXK DVB-C", - .type = FE_QAM, - .frequency_stepsize = 62500, - .frequency_min = 47000000, - .frequency_max = 862000000, - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO - }, - .release = drxk_c_release, - .init = drxk_c_init, - .sleep = drxk_c_sleep, - .i2c_gate_ctrl = drxk_gate_ctrl, - - .set_frontend = drxk_set_parameters, - .get_frontend = drxk_c_get_frontend, - .get_tune_settings = drxk_c_get_tune_settings, - - .read_status = drxk_read_status, - .read_ber = drxk_read_ber, - .read_signal_strength = drxk_read_signal_strength, - .read_snr = drxk_read_snr, - .read_ucblocks = drxk_read_ucblocks, -}; - -static struct dvb_frontend_ops drxk_t_ops = { - .info = { - .name = "DRXK DVB-T", - .type = FE_OFDM, - .frequency_min = 47125000, - .frequency_max = 865000000, - .frequency_stepsize = 166667, - .frequency_tolerance = 0, - .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | - FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | - FE_CAN_FEC_AUTO | - FE_CAN_QAM_16 | FE_CAN_QAM_64 | - FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | - FE_CAN_MUTE_TS - }, - .release = drxk_t_release, - .init = drxk_t_init, - .sleep = drxk_t_sleep, - .i2c_gate_ctrl = drxk_gate_ctrl, - - .set_frontend = drxk_set_parameters, - .get_frontend = drxk_t_get_frontend, - - .read_status = drxk_read_status, - .read_ber = drxk_read_ber, - .read_signal_strength = drxk_read_signal_strength, - .read_snr = drxk_read_snr, - .read_ucblocks = drxk_read_ucblocks, -}; - -struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, - struct dvb_frontend **fe_t) -{ - struct drxk_state *state = NULL; - - state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL); - if (!state) - return NULL; - - state->i2c=i2c; - state->demod_address=adr; - - mutex_init(&state->mutex); - mutex_init(&state->ctlock); - - memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops)); - memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops)); - state->c_frontend.demodulator_priv=state; - state->t_frontend.demodulator_priv=state; - - init_state(state); - if (init_drxk(state)<0) - goto error; - *fe_t = &state->t_frontend; - return &state->c_frontend; - -error: - printk("drxk: not found\n"); - kfree(state); - return NULL; -} - -MODULE_DESCRIPTION("DRX-K driver"); -MODULE_AUTHOR("Ralph Metzler"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(drxk_attach); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_hard.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,343 +0,0 @@ -#include "drxk_map.h" - -#define DRXK_VERSION_MAJOR 0 -#define DRXK_VERSION_MINOR 9 -#define DRXK_VERSION_PATCH 4300 - -#define HI_I2C_DELAY 42 -#define HI_I2C_BRIDGE_DELAY 350 -#define DRXK_MAX_RETRIES 100 - -#define DRIVER_4400 1 - -#define DRXX_JTAGID 0x039210D9 -#define DRXX_J_JTAGID 0x239310D9 -#define DRXX_K_JTAGID 0x039210D9 - -#define DRX_UNKNOWN 254 -#define DRX_AUTO 255 - -#define DRX_SCU_READY 0 -#define DRXK_MAX_WAITTIME (200) -#define SCU_RESULT_OK 0 -#define SCU_RESULT_UNKSTD -2 -#define SCU_RESULT_UNKCMD -1 - -#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT -#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) -#endif - -#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ -#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ -#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ -#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ -#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ -#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ -#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ -#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ - -#define IQM_CF_OUT_ENA_OFDM__M 0x4 -#define IQM_FS_ADJ_SEL_B_QAM 0x1 -#define IQM_FS_ADJ_SEL_B_OFF 0x0 -#define IQM_FS_ADJ_SEL_B_VSB 0x2 -#define IQM_RC_ADJ_SEL_B_OFF 0x0 -#define IQM_RC_ADJ_SEL_B_QAM 0x1 -#define IQM_RC_ADJ_SEL_B_VSB 0x2 - -enum OperationMode { - OM_NONE, - OM_QAM_ITU_A, - OM_QAM_ITU_B, - OM_QAM_ITU_C, - OM_DVBT -}; - -typedef enum { - DRX_POWER_UP = 0, - DRX_POWER_MODE_1, - DRX_POWER_MODE_2, - DRX_POWER_MODE_3, - DRX_POWER_MODE_4, - DRX_POWER_MODE_5, - DRX_POWER_MODE_6, - DRX_POWER_MODE_7, - DRX_POWER_MODE_8, - - DRX_POWER_MODE_9, - DRX_POWER_MODE_10, - DRX_POWER_MODE_11, - DRX_POWER_MODE_12, - DRX_POWER_MODE_13, - DRX_POWER_MODE_14, - DRX_POWER_MODE_15, - DRX_POWER_MODE_16, - DRX_POWER_DOWN = 255 -}DRXPowerMode_t, *pDRXPowerMode_t; - - -/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ -#ifndef DRXK_POWER_DOWN_OFDM -#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 -#endif - -/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ -#ifndef DRXK_POWER_DOWN_CORE -#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 -#endif - -/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ -#ifndef DRXK_POWER_DOWN_PLL -#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 -#endif - - -enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; -enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; -enum EDrxkCoefArrayIndex { - DRXK_COEF_IDX_MN = 0, - DRXK_COEF_IDX_FM , - DRXK_COEF_IDX_L , - DRXK_COEF_IDX_LP , - DRXK_COEF_IDX_BG , - DRXK_COEF_IDX_DK , - DRXK_COEF_IDX_I , - DRXK_COEF_IDX_MAX -}; -enum EDrxkSifAttenuation { - DRXK_SIF_ATTENUATION_0DB, - DRXK_SIF_ATTENUATION_3DB, - DRXK_SIF_ATTENUATION_6DB, - DRXK_SIF_ATTENUATION_9DB -}; -enum EDrxkConstellation { - DRX_CONSTELLATION_BPSK = 0, - DRX_CONSTELLATION_QPSK, - DRX_CONSTELLATION_PSK8, - DRX_CONSTELLATION_QAM16, - DRX_CONSTELLATION_QAM32, - DRX_CONSTELLATION_QAM64, - DRX_CONSTELLATION_QAM128, - DRX_CONSTELLATION_QAM256, - DRX_CONSTELLATION_QAM512, - DRX_CONSTELLATION_QAM1024, - DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, - DRX_CONSTELLATION_AUTO = DRX_AUTO -}; -enum EDrxkInterleaveMode { - DRXK_QAM_I12_J17 = 16, - DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN -}; -enum { - DRXK_SPIN_A1 = 0, - DRXK_SPIN_A2, - DRXK_SPIN_A3, - DRXK_SPIN_UNKNOWN -}; - -enum DRXKCfgDvbtSqiSpeed { - DRXK_DVBT_SQI_SPEED_FAST = 0, - DRXK_DVBT_SQI_SPEED_MEDIUM, - DRXK_DVBT_SQI_SPEED_SLOW, - DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN -} ; - -enum DRXFftmode_t { - DRX_FFTMODE_2K = 0, - DRX_FFTMODE_4K, - DRX_FFTMODE_8K, - DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, - DRX_FFTMODE_AUTO = DRX_AUTO -}; - -enum DRXMPEGStrWidth_t { - DRX_MPEG_STR_WIDTH_1, - DRX_MPEG_STR_WIDTH_8 -}; - -enum DRXQamLockRange_t { - DRX_QAM_LOCKRANGE_NORMAL, - DRX_QAM_LOCKRANGE_EXTENDED -}; - -struct DRXKCfgDvbtEchoThres_t { - u16 threshold; - enum DRXFftmode_t fftMode; -} ; - -struct SCfgAgc -{ - enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ - u16 outputLevel; /* range dependent on AGC */ - u16 minOutputLevel; /* range dependent on AGC */ - u16 maxOutputLevel; /* range dependent on AGC */ - u16 speed; /* range dependent on AGC */ - u16 top; /* rf-agc take over point */ - u16 cutOffCurrent; /* rf-agc is accelerated if output current - is below cut-off current */ - u16 IngainTgtMax; - u16 FastClipCtrlDelay; -}; - -struct SCfgPreSaw -{ - u16 reference; /* pre SAW reference value, range 0 .. 31 */ - bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ -}; - -struct DRXKOfdmScCmd_t -{ - u16 cmd; /**< Command number */ - u16 subcmd; /**< Sub-command parameter*/ - u16 param0; /**< General purpous param */ - u16 param1; /**< General purpous param */ - u16 param2; /**< General purpous param */ - u16 param3; /**< General purpous param */ - u16 param4; /**< General purpous param */ -}; - -struct drxk_state { - struct dvb_frontend c_frontend; - struct dvb_frontend t_frontend; -#ifndef USE_API3 - struct dtv_frontend_properties props; -#else - struct dvb_frontend_parameters param; -#endif - struct device *dev; - - struct i2c_adapter *i2c; - u8 demod_address; - void *priv; - - struct mutex mutex; - struct mutex ctlock; - - u32 m_Instance; ///< Channel 1,2,3 or 4 - - int m_ChunkSize; - u8 Chunk[256]; - - bool m_hasLNA; - bool m_hasDVBT; - bool m_hasDVBC; - bool m_hasAudio; - bool m_hasATV; - bool m_hasOOB; - bool m_hasSAWSW; /**< TRUE if mat_tx is available */ - bool m_hasGPIO1; /**< TRUE if mat_rx is available */ - bool m_hasGPIO2; /**< TRUE if GPIO is available */ - bool m_hasIRQN; /**< TRUE if IRQN is available */ - u16 m_oscClockFreq; - u16 m_HICfgTimingDiv; - u16 m_HICfgBridgeDelay; - u16 m_HICfgWakeUpKey; - u16 m_HICfgTimeout; - u16 m_HICfgCtrl; - s32 m_sysClockFreq ; ///< system clock frequency in kHz - - enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started) - enum OperationMode m_OperationMode; ///< digital standards - struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC - struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC - u16 m_vsbPgaCfg; ///< settings for VSB PGA - struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense - s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication - s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication - bool m_smartAntInverted; - bool m_bDebugEnableBridge; - bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed - bool m_bPowerDown; ///< Power down when not used - - u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint) - - bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ - bool m_insertRSByte; /**< If TRUE, insert RS byte */ - bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ - bool m_invertDATA; /**< If TRUE, invert DATA signals */ - bool m_invertERR; /**< If TRUE, invert ERR signal */ - bool m_invertSTR; /**< If TRUE, invert STR signals */ - bool m_invertVAL; /**< If TRUE, invert VAL signals */ - bool m_invertCLK; /**< If TRUE, invert CLK signals */ - bool m_DVBCStaticCLK; - bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will - be used, otherwise clockrate will - adapt to the bitrate of the TS */ - u32 m_DVBTBitrate; - u32 m_DVBCBitrate; - - u8 m_TSDataStrength; - u8 m_TSClockkStrength; - - enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/ - u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case - static clockrate is selected */ - - //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start - s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) - s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) - - bool m_disableTEIhandling; - - bool m_RfAgcPol; - bool m_IfAgcPol; - - struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC - struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC - struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense - bool m_phaseCorrectionBypass; - s16 m_atvTopVidPeak; - u16 m_atvTopNoiseTh; - enum EDrxkSifAttenuation m_sifAttenuation; - bool m_enableCVBSOutput; - bool m_enableSIFOutput; - bool m_bMirrorFreqSpect; - enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel - u32 m_CurrSymbolRate; ///< Current QAM symbol rate - struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC - struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC - u16 m_qamPgaCfg; ///< settings for QAM PGA - struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense - enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode - u16 m_fecRsPlen; - u16 m_fecRsPrescale; - - enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; - - u16 m_GPIO; - u16 m_GPIOCfg; - - struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC - struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC - struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense - - u16 m_agcFastClipCtrlDelay; - bool m_adcCompPassed; - u16 m_adcCompCoef[64]; - u16 m_adcState; - - u8 *m_microcode; - int m_microcode_length; - bool m_DRXK_A1_PATCH_CODE; - bool m_DRXK_A1_ROM_CODE; - bool m_DRXK_A2_ROM_CODE; - bool m_DRXK_A3_ROM_CODE; - bool m_DRXK_A2_PATCH_CODE; - bool m_DRXK_A3_PATCH_CODE; - - bool m_rfmirror; - u8 m_deviceSpin; - u32 m_iqmRcRate; - - u16 m_AntennaDVBC; - u16 m_AntennaDVBT; - u16 m_AntennaSwitchDVBTDVBC; - - DRXPowerMode_t m_currentPowerMode; -}; - -#define NEVER_LOCK 0 -#define NOT_LOCKED 1 -#define DEMOD_LOCK 2 -#define FEC_LOCK 3 -#define MPEG_LOCK 4 - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,16438 +0,0 @@ -#ifndef __DRXK_MAP__H__ -#define __DRXK_MAP__H__ 1 - -#define AUD_COMM_EXEC__A 0x1000000 -#define AUD_COMM_EXEC__W 2 -#define AUD_COMM_EXEC__M 0x3 -#define AUD_COMM_EXEC__PRE 0x0 -#define AUD_COMM_EXEC_STOP 0x0 - -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_COMM_EXEC__W 2 -#define FEC_COMM_EXEC__M 0x3 -#define FEC_COMM_EXEC__PRE 0x0 -#define FEC_COMM_EXEC_STOP 0x0 -#define FEC_COMM_EXEC_ACTIVE 0x1 -#define FEC_COMM_EXEC_HOLD 0x2 - -#define FEC_COMM_MB__A 0x1C00002 -#define FEC_COMM_MB__W 16 -#define FEC_COMM_MB__M 0xFFFF -#define FEC_COMM_MB__PRE 0x0 -#define FEC_COMM_INT_REQ__A 0x1C00003 -#define FEC_COMM_INT_REQ__W 16 -#define FEC_COMM_INT_REQ__M 0xFFFF -#define FEC_COMM_INT_REQ__PRE 0x0 -#define FEC_COMM_INT_REQ_OC_REQ__B 0 -#define FEC_COMM_INT_REQ_OC_REQ__W 1 -#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 -#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 -#define FEC_COMM_INT_REQ_RS_REQ__B 1 -#define FEC_COMM_INT_REQ_RS_REQ__W 1 -#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 -#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 -#define FEC_COMM_INT_REQ_DI_REQ__B 2 -#define FEC_COMM_INT_REQ_DI_REQ__W 1 -#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 -#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 - -#define FEC_COMM_INT_STA__A 0x1C00005 -#define FEC_COMM_INT_STA__W 16 -#define FEC_COMM_INT_STA__M 0xFFFF -#define FEC_COMM_INT_STA__PRE 0x0 -#define FEC_COMM_INT_MSK__A 0x1C00006 -#define FEC_COMM_INT_MSK__W 16 -#define FEC_COMM_INT_MSK__M 0xFFFF -#define FEC_COMM_INT_MSK__PRE 0x0 -#define FEC_COMM_INT_STM__A 0x1C00007 -#define FEC_COMM_INT_STM__W 16 -#define FEC_COMM_INT_STM__M 0xFFFF -#define FEC_COMM_INT_STM__PRE 0x0 - - - -#define FEC_TOP_COMM_EXEC__A 0x1C10000 -#define FEC_TOP_COMM_EXEC__W 2 -#define FEC_TOP_COMM_EXEC__M 0x3 -#define FEC_TOP_COMM_EXEC__PRE 0x0 -#define FEC_TOP_COMM_EXEC_STOP 0x0 -#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 -#define FEC_TOP_COMM_EXEC_HOLD 0x2 - -#define FEC_TOP_ANNEX__A 0x1C10010 -#define FEC_TOP_ANNEX__W 2 -#define FEC_TOP_ANNEX__M 0x3 -#define FEC_TOP_ANNEX__PRE 0x0 -#define FEC_TOP_ANNEX_A 0x0 -#define FEC_TOP_ANNEX_B 0x1 -#define FEC_TOP_ANNEX_C 0x2 -#define FEC_TOP_ANNEX_D 0x3 - - - -#define FEC_DI_COMM_EXEC__A 0x1C20000 -#define FEC_DI_COMM_EXEC__W 2 -#define FEC_DI_COMM_EXEC__M 0x3 -#define FEC_DI_COMM_EXEC__PRE 0x0 -#define FEC_DI_COMM_EXEC_STOP 0x0 -#define FEC_DI_COMM_EXEC_ACTIVE 0x1 -#define FEC_DI_COMM_EXEC_HOLD 0x2 - -#define FEC_DI_COMM_MB__A 0x1C20002 -#define FEC_DI_COMM_MB__W 2 -#define FEC_DI_COMM_MB__M 0x3 -#define FEC_DI_COMM_MB__PRE 0x0 -#define FEC_DI_COMM_MB_CTL__B 0 -#define FEC_DI_COMM_MB_CTL__W 1 -#define FEC_DI_COMM_MB_CTL__M 0x1 -#define FEC_DI_COMM_MB_CTL__PRE 0x0 -#define FEC_DI_COMM_MB_CTL_OFF 0x0 -#define FEC_DI_COMM_MB_CTL_ON 0x1 -#define FEC_DI_COMM_MB_OBS__B 1 -#define FEC_DI_COMM_MB_OBS__W 1 -#define FEC_DI_COMM_MB_OBS__M 0x2 -#define FEC_DI_COMM_MB_OBS__PRE 0x0 -#define FEC_DI_COMM_MB_OBS_OFF 0x0 -#define FEC_DI_COMM_MB_OBS_ON 0x2 - -#define FEC_DI_COMM_INT_REQ__A 0x1C20003 -#define FEC_DI_COMM_INT_REQ__W 1 -#define FEC_DI_COMM_INT_REQ__M 0x1 -#define FEC_DI_COMM_INT_REQ__PRE 0x0 -#define FEC_DI_COMM_INT_STA__A 0x1C20005 -#define FEC_DI_COMM_INT_STA__W 2 -#define FEC_DI_COMM_INT_STA__M 0x3 -#define FEC_DI_COMM_INT_STA__PRE 0x0 - -#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 -#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 -#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 -#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 - -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 -#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 - -#define FEC_DI_COMM_INT_MSK__A 0x1C20006 -#define FEC_DI_COMM_INT_MSK__W 2 -#define FEC_DI_COMM_INT_MSK__M 0x3 -#define FEC_DI_COMM_INT_MSK__PRE 0x0 -#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 -#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 -#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 -#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 -#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 - -#define FEC_DI_COMM_INT_STM__A 0x1C20007 -#define FEC_DI_COMM_INT_STM__W 2 -#define FEC_DI_COMM_INT_STM__M 0x3 -#define FEC_DI_COMM_INT_STM__PRE 0x0 -#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 -#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 -#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 -#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 -#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 - - -#define FEC_DI_STATUS__A 0x1C20010 -#define FEC_DI_STATUS__W 1 -#define FEC_DI_STATUS__M 0x1 -#define FEC_DI_STATUS__PRE 0x0 -#define FEC_DI_MODE__A 0x1C20011 -#define FEC_DI_MODE__W 3 -#define FEC_DI_MODE__M 0x7 -#define FEC_DI_MODE__PRE 0x0 - -#define FEC_DI_MODE_NO_SYNC__B 0 -#define FEC_DI_MODE_NO_SYNC__W 1 -#define FEC_DI_MODE_NO_SYNC__M 0x1 -#define FEC_DI_MODE_NO_SYNC__PRE 0x0 - -#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 -#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 -#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 -#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 - -#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 -#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 -#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 -#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 - - -#define FEC_DI_CONTROL_WORD__A 0x1C20012 -#define FEC_DI_CONTROL_WORD__W 4 -#define FEC_DI_CONTROL_WORD__M 0xF -#define FEC_DI_CONTROL_WORD__PRE 0x0 - -#define FEC_DI_RESTART__A 0x1C20013 -#define FEC_DI_RESTART__W 1 -#define FEC_DI_RESTART__M 0x1 -#define FEC_DI_RESTART__PRE 0x0 - -#define FEC_DI_TIMEOUT_LO__A 0x1C20014 -#define FEC_DI_TIMEOUT_LO__W 16 -#define FEC_DI_TIMEOUT_LO__M 0xFFFF -#define FEC_DI_TIMEOUT_LO__PRE 0x0 - -#define FEC_DI_TIMEOUT_HI__A 0x1C20015 -#define FEC_DI_TIMEOUT_HI__W 8 -#define FEC_DI_TIMEOUT_HI__M 0xFF -#define FEC_DI_TIMEOUT_HI__PRE 0xA - -#define FEC_DI_INPUT_CTL__A 0x1C20016 -#define FEC_DI_INPUT_CTL__W 1 -#define FEC_DI_INPUT_CTL__M 0x1 -#define FEC_DI_INPUT_CTL__PRE 0x0 - - - -#define FEC_RS_COMM_EXEC__A 0x1C30000 -#define FEC_RS_COMM_EXEC__W 2 -#define FEC_RS_COMM_EXEC__M 0x3 -#define FEC_RS_COMM_EXEC__PRE 0x0 -#define FEC_RS_COMM_EXEC_STOP 0x0 -#define FEC_RS_COMM_EXEC_ACTIVE 0x1 -#define FEC_RS_COMM_EXEC_HOLD 0x2 - -#define FEC_RS_COMM_MB__A 0x1C30002 -#define FEC_RS_COMM_MB__W 2 -#define FEC_RS_COMM_MB__M 0x3 -#define FEC_RS_COMM_MB__PRE 0x0 -#define FEC_RS_COMM_MB_CTL__B 0 -#define FEC_RS_COMM_MB_CTL__W 1 -#define FEC_RS_COMM_MB_CTL__M 0x1 -#define FEC_RS_COMM_MB_CTL__PRE 0x0 -#define FEC_RS_COMM_MB_CTL_OFF 0x0 -#define FEC_RS_COMM_MB_CTL_ON 0x1 -#define FEC_RS_COMM_MB_OBS__B 1 -#define FEC_RS_COMM_MB_OBS__W 1 -#define FEC_RS_COMM_MB_OBS__M 0x2 -#define FEC_RS_COMM_MB_OBS__PRE 0x0 -#define FEC_RS_COMM_MB_OBS_OFF 0x0 -#define FEC_RS_COMM_MB_OBS_ON 0x2 - -#define FEC_RS_COMM_INT_REQ__A 0x1C30003 -#define FEC_RS_COMM_INT_REQ__W 1 -#define FEC_RS_COMM_INT_REQ__M 0x1 -#define FEC_RS_COMM_INT_REQ__PRE 0x0 -#define FEC_RS_COMM_INT_STA__A 0x1C30005 -#define FEC_RS_COMM_INT_STA__W 2 -#define FEC_RS_COMM_INT_STA__M 0x3 -#define FEC_RS_COMM_INT_STA__PRE 0x0 - -#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 -#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 -#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 -#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 - -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 -#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 - -#define FEC_RS_COMM_INT_MSK__A 0x1C30006 -#define FEC_RS_COMM_INT_MSK__W 2 -#define FEC_RS_COMM_INT_MSK__M 0x3 -#define FEC_RS_COMM_INT_MSK__PRE 0x0 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 -#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 -#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 - -#define FEC_RS_COMM_INT_STM__A 0x1C30007 -#define FEC_RS_COMM_INT_STM__W 2 -#define FEC_RS_COMM_INT_STM__M 0x3 -#define FEC_RS_COMM_INT_STM__PRE 0x0 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 -#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 -#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 - -#define FEC_RS_STATUS__A 0x1C30010 -#define FEC_RS_STATUS__W 1 -#define FEC_RS_STATUS__M 0x1 -#define FEC_RS_STATUS__PRE 0x0 -#define FEC_RS_MODE__A 0x1C30011 -#define FEC_RS_MODE__W 1 -#define FEC_RS_MODE__M 0x1 -#define FEC_RS_MODE__PRE 0x0 - -#define FEC_RS_MODE_BYPASS__B 0 -#define FEC_RS_MODE_BYPASS__W 1 -#define FEC_RS_MODE_BYPASS__M 0x1 -#define FEC_RS_MODE_BYPASS__PRE 0x0 - -#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 -#define FEC_RS_MEASUREMENT_PERIOD__W 16 -#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF -#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993 - -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF -#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993 - -#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 -#define FEC_RS_MEASUREMENT_PRESCALE__W 16 -#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF -#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 - -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF -#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 - -#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 -#define FEC_RS_NR_BIT_ERRORS__W 16 -#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF -#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF - -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF - -#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 -#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 -#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 -#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 - -#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015 -#define FEC_RS_NR_SYMBOL_ERRORS__W 16 -#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF -#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF - -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF - -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 -#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 - -#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016 -#define FEC_RS_NR_PACKET_ERRORS__W 16 -#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF -#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF - -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF - -#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 -#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 -#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 -#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 - -#define FEC_RS_NR_FAILURES__A 0x1C30017 -#define FEC_RS_NR_FAILURES__W 16 -#define FEC_RS_NR_FAILURES__M 0xFFFF -#define FEC_RS_NR_FAILURES__PRE 0x0 - -#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 -#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 -#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF -#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 - -#define FEC_RS_NR_FAILURES_EXP__B 12 -#define FEC_RS_NR_FAILURES_EXP__W 4 -#define FEC_RS_NR_FAILURES_EXP__M 0xF000 -#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 - - - -#define FEC_OC_COMM_EXEC__A 0x1C40000 -#define FEC_OC_COMM_EXEC__W 2 -#define FEC_OC_COMM_EXEC__M 0x3 -#define FEC_OC_COMM_EXEC__PRE 0x0 -#define FEC_OC_COMM_EXEC_STOP 0x0 -#define FEC_OC_COMM_EXEC_ACTIVE 0x1 -#define FEC_OC_COMM_EXEC_HOLD 0x2 - -#define FEC_OC_COMM_MB__A 0x1C40002 -#define FEC_OC_COMM_MB__W 2 -#define FEC_OC_COMM_MB__M 0x3 -#define FEC_OC_COMM_MB__PRE 0x0 -#define FEC_OC_COMM_MB_CTL__B 0 -#define FEC_OC_COMM_MB_CTL__W 1 -#define FEC_OC_COMM_MB_CTL__M 0x1 -#define FEC_OC_COMM_MB_CTL__PRE 0x0 -#define FEC_OC_COMM_MB_CTL_OFF 0x0 -#define FEC_OC_COMM_MB_CTL_ON 0x1 -#define FEC_OC_COMM_MB_OBS__B 1 -#define FEC_OC_COMM_MB_OBS__W 1 -#define FEC_OC_COMM_MB_OBS__M 0x2 -#define FEC_OC_COMM_MB_OBS__PRE 0x0 -#define FEC_OC_COMM_MB_OBS_OFF 0x0 -#define FEC_OC_COMM_MB_OBS_ON 0x2 - -#define FEC_OC_COMM_INT_REQ__A 0x1C40003 -#define FEC_OC_COMM_INT_REQ__W 1 -#define FEC_OC_COMM_INT_REQ__M 0x1 -#define FEC_OC_COMM_INT_REQ__PRE 0x0 -#define FEC_OC_COMM_INT_STA__A 0x1C40005 -#define FEC_OC_COMM_INT_STA__W 8 -#define FEC_OC_COMM_INT_STA__M 0xFF -#define FEC_OC_COMM_INT_STA__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 -#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 -#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 -#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 -#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 -#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 -#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 -#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 -#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 - -#define FEC_OC_COMM_INT_MSK__A 0x1C40006 -#define FEC_OC_COMM_INT_MSK__W 8 -#define FEC_OC_COMM_INT_MSK__M 0xFF -#define FEC_OC_COMM_INT_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 -#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 -#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 -#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 -#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 -#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 -#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 -#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 -#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 - -#define FEC_OC_COMM_INT_STM__A 0x1C40007 -#define FEC_OC_COMM_INT_STM__W 8 -#define FEC_OC_COMM_INT_STM__M 0xFF -#define FEC_OC_COMM_INT_STM__PRE 0x0 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 -#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 -#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 -#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 -#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 -#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 -#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 -#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 -#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 - -#define FEC_OC_STATUS__A 0x1C40010 -#define FEC_OC_STATUS__W 5 -#define FEC_OC_STATUS__M 0x1F -#define FEC_OC_STATUS__PRE 0x0 - -#define FEC_OC_STATUS_DPR_STATUS__B 0 -#define FEC_OC_STATUS_DPR_STATUS__W 1 -#define FEC_OC_STATUS_DPR_STATUS__M 0x1 -#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 - -#define FEC_OC_STATUS_SNC_STATUS__B 1 -#define FEC_OC_STATUS_SNC_STATUS__W 2 -#define FEC_OC_STATUS_SNC_STATUS__M 0x6 -#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 -#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0 -#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2 -#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4 - -#define FEC_OC_STATUS_FIFO_FULL__B 3 -#define FEC_OC_STATUS_FIFO_FULL__W 1 -#define FEC_OC_STATUS_FIFO_FULL__M 0x8 -#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 - -#define FEC_OC_STATUS_FIFO_EMPTY__B 4 -#define FEC_OC_STATUS_FIFO_EMPTY__W 1 -#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 -#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 - -#define FEC_OC_MODE__A 0x1C40011 -#define FEC_OC_MODE__W 4 -#define FEC_OC_MODE__M 0xF -#define FEC_OC_MODE__PRE 0x0 - -#define FEC_OC_MODE_PARITY__B 0 -#define FEC_OC_MODE_PARITY__W 1 -#define FEC_OC_MODE_PARITY__M 0x1 -#define FEC_OC_MODE_PARITY__PRE 0x0 - -#define FEC_OC_MODE_TRANSPARENT__B 1 -#define FEC_OC_MODE_TRANSPARENT__W 1 -#define FEC_OC_MODE_TRANSPARENT__M 0x2 -#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 - -#define FEC_OC_MODE_CLEAR__B 2 -#define FEC_OC_MODE_CLEAR__W 1 -#define FEC_OC_MODE_CLEAR__M 0x4 -#define FEC_OC_MODE_CLEAR__PRE 0x0 - -#define FEC_OC_MODE_RETAIN_FRAMING__B 3 -#define FEC_OC_MODE_RETAIN_FRAMING__W 1 -#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 -#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 - -#define FEC_OC_DPR_MODE__A 0x1C40012 -#define FEC_OC_DPR_MODE__W 2 -#define FEC_OC_DPR_MODE__M 0x3 -#define FEC_OC_DPR_MODE__PRE 0x0 - -#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 -#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 -#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 -#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 - -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 -#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 - - -#define FEC_OC_DPR_UNLOCK__A 0x1C40013 -#define FEC_OC_DPR_UNLOCK__W 1 -#define FEC_OC_DPR_UNLOCK__M 0x1 -#define FEC_OC_DPR_UNLOCK__PRE 0x0 -#define FEC_OC_DTO_MODE__A 0x1C40014 -#define FEC_OC_DTO_MODE__W 3 -#define FEC_OC_DTO_MODE__M 0x7 -#define FEC_OC_DTO_MODE__PRE 0x0 - -#define FEC_OC_DTO_MODE_DYNAMIC__B 0 -#define FEC_OC_DTO_MODE_DYNAMIC__W 1 -#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 -#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 - -#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 -#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 -#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 -#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 - -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 - - -#define FEC_OC_DTO_PERIOD__A 0x1C40015 -#define FEC_OC_DTO_PERIOD__W 8 -#define FEC_OC_DTO_PERIOD__M 0xFF -#define FEC_OC_DTO_PERIOD__PRE 0x0 -#define FEC_OC_DTO_RATE_LO__A 0x1C40016 -#define FEC_OC_DTO_RATE_LO__W 16 -#define FEC_OC_DTO_RATE_LO__M 0xFFFF -#define FEC_OC_DTO_RATE_LO__PRE 0x0 - -#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 -#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 -#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF -#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 - -#define FEC_OC_DTO_RATE_HI__A 0x1C40017 -#define FEC_OC_DTO_RATE_HI__W 10 -#define FEC_OC_DTO_RATE_HI__M 0x3FF -#define FEC_OC_DTO_RATE_HI__PRE 0xC0 - -#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 -#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 -#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF -#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 - -#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 -#define FEC_OC_DTO_BURST_LEN__W 8 -#define FEC_OC_DTO_BURST_LEN__M 0xFF -#define FEC_OC_DTO_BURST_LEN__PRE 0xBC - -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF -#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC - -#define FEC_OC_FCT_MODE__A 0x1C4001A -#define FEC_OC_FCT_MODE__W 2 -#define FEC_OC_FCT_MODE__M 0x3 -#define FEC_OC_FCT_MODE__PRE 0x0 - -#define FEC_OC_FCT_MODE_RAT_ENA__B 0 -#define FEC_OC_FCT_MODE_RAT_ENA__W 1 -#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 -#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 - -#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 -#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 -#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 -#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 - -#define FEC_OC_FCT_USAGE__A 0x1C4001B -#define FEC_OC_FCT_USAGE__W 3 -#define FEC_OC_FCT_USAGE__M 0x7 -#define FEC_OC_FCT_USAGE__PRE 0x7 - -#define FEC_OC_FCT_USAGE_USAGE__B 0 -#define FEC_OC_FCT_USAGE_USAGE__W 3 -#define FEC_OC_FCT_USAGE_USAGE__M 0x7 -#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7 - -#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C -#define FEC_OC_FCT_OCCUPATION__W 12 -#define FEC_OC_FCT_OCCUPATION__M 0xFFF -#define FEC_OC_FCT_OCCUPATION__PRE 0x0 - -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF -#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 - -#define FEC_OC_TMD_MODE__A 0x1C4001E -#define FEC_OC_TMD_MODE__W 3 -#define FEC_OC_TMD_MODE__M 0x7 -#define FEC_OC_TMD_MODE__PRE 0x4 - -#define FEC_OC_TMD_MODE_MODE__B 0 -#define FEC_OC_TMD_MODE_MODE__W 3 -#define FEC_OC_TMD_MODE_MODE__M 0x7 -#define FEC_OC_TMD_MODE_MODE__PRE 0x4 - -#define FEC_OC_TMD_COUNT__A 0x1C4001F -#define FEC_OC_TMD_COUNT__W 10 -#define FEC_OC_TMD_COUNT__M 0x3FF -#define FEC_OC_TMD_COUNT__PRE 0x1F4 - -#define FEC_OC_TMD_COUNT_COUNT__B 0 -#define FEC_OC_TMD_COUNT_COUNT__W 10 -#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF -#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 - -#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 -#define FEC_OC_TMD_HI_MARGIN__W 11 -#define FEC_OC_TMD_HI_MARGIN__M 0x7FF -#define FEC_OC_TMD_HI_MARGIN__PRE 0x500 - -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF -#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500 - -#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 -#define FEC_OC_TMD_LO_MARGIN__W 11 -#define FEC_OC_TMD_LO_MARGIN__M 0x7FF -#define FEC_OC_TMD_LO_MARGIN__PRE 0x300 - -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF -#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300 - -#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022 -#define FEC_OC_TMD_CTL_UPD_RATE__W 4 -#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF -#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 - -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF -#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 - -#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 -#define FEC_OC_TMD_INT_UPD_RATE__W 4 -#define FEC_OC_TMD_INT_UPD_RATE__M 0xF -#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 - -#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 -#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 -#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF -#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 - -#define FEC_OC_AVR_PARM_A__A 0x1C40026 -#define FEC_OC_AVR_PARM_A__W 4 -#define FEC_OC_AVR_PARM_A__M 0xF -#define FEC_OC_AVR_PARM_A__PRE 0x6 - -#define FEC_OC_AVR_PARM_A_PARM__B 0 -#define FEC_OC_AVR_PARM_A_PARM__W 4 -#define FEC_OC_AVR_PARM_A_PARM__M 0xF -#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 - -#define FEC_OC_AVR_PARM_B__A 0x1C40027 -#define FEC_OC_AVR_PARM_B__W 4 -#define FEC_OC_AVR_PARM_B__M 0xF -#define FEC_OC_AVR_PARM_B__PRE 0x4 - -#define FEC_OC_AVR_PARM_B_PARM__B 0 -#define FEC_OC_AVR_PARM_B_PARM__W 4 -#define FEC_OC_AVR_PARM_B_PARM__M 0xF -#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 - -#define FEC_OC_AVR_AVG_LO__A 0x1C40028 -#define FEC_OC_AVR_AVG_LO__W 16 -#define FEC_OC_AVR_AVG_LO__M 0xFFFF -#define FEC_OC_AVR_AVG_LO__PRE 0x0 - -#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 -#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 -#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF -#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 - -#define FEC_OC_AVR_AVG_HI__A 0x1C40029 -#define FEC_OC_AVR_AVG_HI__W 6 -#define FEC_OC_AVR_AVG_HI__M 0x3F -#define FEC_OC_AVR_AVG_HI__PRE 0x0 - -#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 -#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 -#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F -#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 - -#define FEC_OC_RCN_MODE__A 0x1C4002C -#define FEC_OC_RCN_MODE__W 5 -#define FEC_OC_RCN_MODE__M 0x1F -#define FEC_OC_RCN_MODE__PRE 0x1F - -#define FEC_OC_RCN_MODE_MODE__B 0 -#define FEC_OC_RCN_MODE_MODE__W 5 -#define FEC_OC_RCN_MODE_MODE__M 0x1F -#define FEC_OC_RCN_MODE_MODE__PRE 0x1F - -#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D -#define FEC_OC_RCN_OCC_SETTLE__W 11 -#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF -#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400 - -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF -#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400 - -#define FEC_OC_RCN_GAIN__A 0x1C4002E -#define FEC_OC_RCN_GAIN__W 4 -#define FEC_OC_RCN_GAIN__M 0xF -#define FEC_OC_RCN_GAIN__PRE 0xC - -#define FEC_OC_RCN_GAIN_GAIN__B 0 -#define FEC_OC_RCN_GAIN_GAIN__W 4 -#define FEC_OC_RCN_GAIN_GAIN__M 0xF -#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC - -#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 -#define FEC_OC_RCN_CTL_RATE_LO__W 16 -#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031 -#define FEC_OC_RCN_CTL_RATE_HI__W 8 -#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF -#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 - -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF -#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 - -#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 -#define FEC_OC_RCN_CTL_STEP_LO__W 16 -#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF -#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 - -#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 -#define FEC_OC_RCN_CTL_STEP_HI__W 8 -#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF -#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 - -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF -#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 - -#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034 -#define FEC_OC_RCN_DTO_OFS_LO__W 16 -#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035 -#define FEC_OC_RCN_DTO_OFS_HI__W 8 -#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF -#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 - -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF -#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036 -#define FEC_OC_RCN_DTO_RATE_LO__W 16 -#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF -#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037 -#define FEC_OC_RCN_DTO_RATE_HI__W 8 -#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF -#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 - -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF -#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 - -#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038 -#define FEC_OC_RCN_RATE_CLIP_LO__W 16 -#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF -#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 - -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF -#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 - -#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039 -#define FEC_OC_RCN_RATE_CLIP_HI__W 8 -#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF -#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 - -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF -#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 - -#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A -#define FEC_OC_RCN_DYN_RATE_LO__W 16 -#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF -#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 - -#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B -#define FEC_OC_RCN_DYN_RATE_HI__W 8 -#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF -#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 - -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF -#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 - -#define FEC_OC_SNC_MODE__A 0x1C40040 -#define FEC_OC_SNC_MODE__W 5 -#define FEC_OC_SNC_MODE__M 0x1F -#define FEC_OC_SNC_MODE__PRE 0x0 - -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 -#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 - -#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 -#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 -#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 -#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 - -#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 -#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 -#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 -#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 - -#define FEC_OC_SNC_MODE_SHUTDOWN__B 4 -#define FEC_OC_SNC_MODE_SHUTDOWN__W 1 -#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 -#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0 - -#define FEC_OC_SNC_LWM__A 0x1C40041 -#define FEC_OC_SNC_LWM__W 4 -#define FEC_OC_SNC_LWM__M 0xF -#define FEC_OC_SNC_LWM__PRE 0x3 - -#define FEC_OC_SNC_LWM_MARK__B 0 -#define FEC_OC_SNC_LWM_MARK__W 4 -#define FEC_OC_SNC_LWM_MARK__M 0xF -#define FEC_OC_SNC_LWM_MARK__PRE 0x3 - -#define FEC_OC_SNC_HWM__A 0x1C40042 -#define FEC_OC_SNC_HWM__W 4 -#define FEC_OC_SNC_HWM__M 0xF -#define FEC_OC_SNC_HWM__PRE 0x5 - -#define FEC_OC_SNC_HWM_MARK__B 0 -#define FEC_OC_SNC_HWM_MARK__W 4 -#define FEC_OC_SNC_HWM_MARK__M 0xF -#define FEC_OC_SNC_HWM_MARK__PRE 0x5 - -#define FEC_OC_SNC_UNLOCK__A 0x1C40043 -#define FEC_OC_SNC_UNLOCK__W 1 -#define FEC_OC_SNC_UNLOCK__M 0x1 -#define FEC_OC_SNC_UNLOCK__PRE 0x0 - -#define FEC_OC_SNC_UNLOCK_RESTART__B 0 -#define FEC_OC_SNC_UNLOCK_RESTART__W 1 -#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 -#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 - -#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044 -#define FEC_OC_SNC_LOCK_COUNT__W 12 -#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF -#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 - -#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 -#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 -#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF -#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 - -#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045 -#define FEC_OC_SNC_FAIL_COUNT__W 12 -#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF -#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 - -#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 -#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 -#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF -#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 - -#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 -#define FEC_OC_SNC_FAIL_PERIOD__W 16 -#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF -#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 - -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF -#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 - -#define FEC_OC_EMS_MODE__A 0x1C40047 -#define FEC_OC_EMS_MODE__W 2 -#define FEC_OC_EMS_MODE__M 0x3 -#define FEC_OC_EMS_MODE__PRE 0x0 - -#define FEC_OC_EMS_MODE_MODE__B 0 -#define FEC_OC_EMS_MODE_MODE__W 2 -#define FEC_OC_EMS_MODE_MODE__M 0x3 -#define FEC_OC_EMS_MODE_MODE__PRE 0x0 - -#define FEC_OC_IPR_MODE__A 0x1C40048 -#define FEC_OC_IPR_MODE__W 12 -#define FEC_OC_IPR_MODE__M 0xFFF -#define FEC_OC_IPR_MODE__PRE 0x0 - -#define FEC_OC_IPR_MODE_SERIAL__B 0 -#define FEC_OC_IPR_MODE_SERIAL__W 1 -#define FEC_OC_IPR_MODE_SERIAL__M 0x1 -#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 - -#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 -#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 -#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 -#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 - -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 - -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 -#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 -#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 -#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 -#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 -#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 -#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 -#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 -#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 -#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 -#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 -#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 - -#define FEC_OC_IPR_INVERT__A 0x1C40049 -#define FEC_OC_IPR_INVERT__W 12 -#define FEC_OC_IPR_INVERT__M 0xFFF -#define FEC_OC_IPR_INVERT__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD0__B 0 -#define FEC_OC_IPR_INVERT_MD0__W 1 -#define FEC_OC_IPR_INVERT_MD0__M 0x1 -#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD1__B 1 -#define FEC_OC_IPR_INVERT_MD1__W 1 -#define FEC_OC_IPR_INVERT_MD1__M 0x2 -#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD2__B 2 -#define FEC_OC_IPR_INVERT_MD2__W 1 -#define FEC_OC_IPR_INVERT_MD2__M 0x4 -#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD3__B 3 -#define FEC_OC_IPR_INVERT_MD3__W 1 -#define FEC_OC_IPR_INVERT_MD3__M 0x8 -#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD4__B 4 -#define FEC_OC_IPR_INVERT_MD4__W 1 -#define FEC_OC_IPR_INVERT_MD4__M 0x10 -#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD5__B 5 -#define FEC_OC_IPR_INVERT_MD5__W 1 -#define FEC_OC_IPR_INVERT_MD5__M 0x20 -#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD6__B 6 -#define FEC_OC_IPR_INVERT_MD6__W 1 -#define FEC_OC_IPR_INVERT_MD6__M 0x40 -#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MD7__B 7 -#define FEC_OC_IPR_INVERT_MD7__W 1 -#define FEC_OC_IPR_INVERT_MD7__M 0x80 -#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MERR__B 8 -#define FEC_OC_IPR_INVERT_MERR__W 1 -#define FEC_OC_IPR_INVERT_MERR__M 0x100 -#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MSTRT__B 9 -#define FEC_OC_IPR_INVERT_MSTRT__W 1 -#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 -#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MVAL__B 10 -#define FEC_OC_IPR_INVERT_MVAL__W 1 -#define FEC_OC_IPR_INVERT_MVAL__M 0x400 -#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 - -#define FEC_OC_IPR_INVERT_MCLK__B 11 -#define FEC_OC_IPR_INVERT_MCLK__W 1 -#define FEC_OC_IPR_INVERT_MCLK__M 0x800 -#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 - -#define FEC_OC_OCR_MODE__A 0x1C40050 -#define FEC_OC_OCR_MODE__W 4 -#define FEC_OC_OCR_MODE__M 0xF -#define FEC_OC_OCR_MODE__PRE 0x0 - -#define FEC_OC_OCR_MODE_MB_SELECT__B 0 -#define FEC_OC_OCR_MODE_MB_SELECT__W 1 -#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 -#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 - -#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 -#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 -#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 -#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 - -#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 -#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 -#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 -#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 - -#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 -#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 -#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 -#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 - -#define FEC_OC_OCR_RATE__A 0x1C40051 -#define FEC_OC_OCR_RATE__W 4 -#define FEC_OC_OCR_RATE__M 0xF -#define FEC_OC_OCR_RATE__PRE 0x0 - -#define FEC_OC_OCR_RATE_RATE__B 0 -#define FEC_OC_OCR_RATE_RATE__W 4 -#define FEC_OC_OCR_RATE_RATE__M 0xF -#define FEC_OC_OCR_RATE_RATE__PRE 0x0 - -#define FEC_OC_OCR_INVERT__A 0x1C40052 -#define FEC_OC_OCR_INVERT__W 12 -#define FEC_OC_OCR_INVERT__M 0xFFF -#define FEC_OC_OCR_INVERT__PRE 0x800 - -#define FEC_OC_OCR_INVERT_INVERT__B 0 -#define FEC_OC_OCR_INVERT_INVERT__W 12 -#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF -#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 - -#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053 -#define FEC_OC_OCR_GRAB_COUNT__W 16 -#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF -#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 - -#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 -#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 -#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF -#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054 -#define FEC_OC_OCR_GRAB_SYNC__W 8 -#define FEC_OC_OCR_GRAB_SYNC__M 0xFF -#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 -#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 -#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 - -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 -#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055 -#define FEC_OC_OCR_GRAB_RD0__W 10 -#define FEC_OC_OCR_GRAB_RD0__M 0x3FF -#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056 -#define FEC_OC_OCR_GRAB_RD1__W 10 -#define FEC_OC_OCR_GRAB_RD1__M 0x3FF -#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057 -#define FEC_OC_OCR_GRAB_RD2__W 10 -#define FEC_OC_OCR_GRAB_RD2__M 0x3FF -#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058 -#define FEC_OC_OCR_GRAB_RD3__W 10 -#define FEC_OC_OCR_GRAB_RD3__M 0x3FF -#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059 -#define FEC_OC_OCR_GRAB_RD4__W 10 -#define FEC_OC_OCR_GRAB_RD4__M 0x3FF -#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A -#define FEC_OC_OCR_GRAB_RD5__W 10 -#define FEC_OC_OCR_GRAB_RD5__M 0x3FF -#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 - -#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 -#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 -#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF -#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 - - - -#define FEC_DI_RAM__A 0x1C50000 - - - -#define FEC_RS_RAM__A 0x1C60000 - - - -#define FEC_OC_RAM__A 0x1C70000 - - - - - -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__W 2 -#define IQM_COMM_EXEC__M 0x3 -#define IQM_COMM_EXEC__PRE 0x0 -#define IQM_COMM_EXEC_B__B 0 -#define IQM_COMM_EXEC_B__W 2 -#define IQM_COMM_EXEC_B__M 0x3 -#define IQM_COMM_EXEC_B__PRE 0x0 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC_B_ACTIVE 0x1 -#define IQM_COMM_EXEC_B_HOLD 0x2 - -#define IQM_COMM_MB__A 0x1800002 -#define IQM_COMM_MB__W 16 -#define IQM_COMM_MB__M 0xFFFF -#define IQM_COMM_MB__PRE 0x0 -#define IQM_COMM_MB_B__B 0 -#define IQM_COMM_MB_B__W 16 -#define IQM_COMM_MB_B__M 0xFFFF -#define IQM_COMM_MB_B__PRE 0x0 - -#define IQM_COMM_INT_REQ__A 0x1800003 -#define IQM_COMM_INT_REQ__W 3 -#define IQM_COMM_INT_REQ__M 0x7 -#define IQM_COMM_INT_REQ__PRE 0x0 - -#define IQM_COMM_INT_REQ_AF_REQ__B 0 -#define IQM_COMM_INT_REQ_AF_REQ__W 1 -#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 -#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 - -#define IQM_COMM_INT_REQ_CF_REQ__B 1 -#define IQM_COMM_INT_REQ_CF_REQ__W 1 -#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 -#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 - -#define IQM_COMM_INT_REQ_CW_REQ__B 2 -#define IQM_COMM_INT_REQ_CW_REQ__W 1 -#define IQM_COMM_INT_REQ_CW_REQ__M 0x4 -#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0 - -#define IQM_COMM_INT_STA__A 0x1800005 -#define IQM_COMM_INT_STA__W 16 -#define IQM_COMM_INT_STA__M 0xFFFF -#define IQM_COMM_INT_STA__PRE 0x0 -#define IQM_COMM_INT_STA_B__B 0 -#define IQM_COMM_INT_STA_B__W 16 -#define IQM_COMM_INT_STA_B__M 0xFFFF -#define IQM_COMM_INT_STA_B__PRE 0x0 - -#define IQM_COMM_INT_MSK__A 0x1800006 -#define IQM_COMM_INT_MSK__W 16 -#define IQM_COMM_INT_MSK__M 0xFFFF -#define IQM_COMM_INT_MSK__PRE 0x0 -#define IQM_COMM_INT_MSK_B__B 0 -#define IQM_COMM_INT_MSK_B__W 16 -#define IQM_COMM_INT_MSK_B__M 0xFFFF -#define IQM_COMM_INT_MSK_B__PRE 0x0 - -#define IQM_COMM_INT_STM__A 0x1800007 -#define IQM_COMM_INT_STM__W 16 -#define IQM_COMM_INT_STM__M 0xFFFF -#define IQM_COMM_INT_STM__PRE 0x0 -#define IQM_COMM_INT_STM_B__B 0 -#define IQM_COMM_INT_STM_B__W 16 -#define IQM_COMM_INT_STM_B__M 0xFFFF -#define IQM_COMM_INT_STM_B__PRE 0x0 - - - -#define IQM_FS_COMM_EXEC__A 0x1820000 -#define IQM_FS_COMM_EXEC__W 2 -#define IQM_FS_COMM_EXEC__M 0x3 -#define IQM_FS_COMM_EXEC__PRE 0x0 -#define IQM_FS_COMM_EXEC_STOP 0x0 -#define IQM_FS_COMM_EXEC_ACTIVE 0x1 -#define IQM_FS_COMM_EXEC_HOLD 0x2 - -#define IQM_FS_COMM_MB__A 0x1820002 -#define IQM_FS_COMM_MB__W 4 -#define IQM_FS_COMM_MB__M 0xF -#define IQM_FS_COMM_MB__PRE 0x0 -#define IQM_FS_COMM_MB_CTL__B 0 -#define IQM_FS_COMM_MB_CTL__W 1 -#define IQM_FS_COMM_MB_CTL__M 0x1 -#define IQM_FS_COMM_MB_CTL__PRE 0x0 -#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_FS_COMM_MB_OBS__B 1 -#define IQM_FS_COMM_MB_OBS__W 1 -#define IQM_FS_COMM_MB_OBS__M 0x2 -#define IQM_FS_COMM_MB_OBS__PRE 0x0 -#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 -#define IQM_FS_COMM_MB_CTL_MUX__B 2 -#define IQM_FS_COMM_MB_CTL_MUX__W 1 -#define IQM_FS_COMM_MB_CTL_MUX__M 0x4 -#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0 -#define IQM_FS_COMM_MB_OBS_MUX__B 3 -#define IQM_FS_COMM_MB_OBS_MUX__W 1 -#define IQM_FS_COMM_MB_OBS_MUX__M 0x8 -#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0 - -#define IQM_FS_RATE_OFS_LO__A 0x1820010 -#define IQM_FS_RATE_OFS_LO__W 16 -#define IQM_FS_RATE_OFS_LO__M 0xFFFF -#define IQM_FS_RATE_OFS_LO__PRE 0x0 -#define IQM_FS_RATE_OFS_LO_B__B 0 -#define IQM_FS_RATE_OFS_LO_B__W 16 -#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF -#define IQM_FS_RATE_OFS_LO_B__PRE 0x0 - -#define IQM_FS_RATE_OFS_HI__A 0x1820011 -#define IQM_FS_RATE_OFS_HI__W 12 -#define IQM_FS_RATE_OFS_HI__M 0xFFF -#define IQM_FS_RATE_OFS_HI__PRE 0x0 -#define IQM_FS_RATE_OFS_HI_B__B 0 -#define IQM_FS_RATE_OFS_HI_B__W 12 -#define IQM_FS_RATE_OFS_HI_B__M 0xFFF -#define IQM_FS_RATE_OFS_HI_B__PRE 0x0 - -#define IQM_FS_RATE_LO__A 0x1820012 -#define IQM_FS_RATE_LO__W 16 -#define IQM_FS_RATE_LO__M 0xFFFF -#define IQM_FS_RATE_LO__PRE 0x0 -#define IQM_FS_RATE_LO_B__B 0 -#define IQM_FS_RATE_LO_B__W 16 -#define IQM_FS_RATE_LO_B__M 0xFFFF -#define IQM_FS_RATE_LO_B__PRE 0x0 - -#define IQM_FS_RATE_HI__A 0x1820013 -#define IQM_FS_RATE_HI__W 12 -#define IQM_FS_RATE_HI__M 0xFFF -#define IQM_FS_RATE_HI__PRE 0x0 -#define IQM_FS_RATE_HI_B__B 0 -#define IQM_FS_RATE_HI_B__W 12 -#define IQM_FS_RATE_HI_B__M 0xFFF -#define IQM_FS_RATE_HI_B__PRE 0x0 - -#define IQM_FS_ADJ_SEL__A 0x1820014 -#define IQM_FS_ADJ_SEL__W 2 -#define IQM_FS_ADJ_SEL__M 0x3 -#define IQM_FS_ADJ_SEL__PRE 0x0 - -#define IQM_FS_ADJ_SEL_B__B 0 -#define IQM_FS_ADJ_SEL_B__W 2 -#define IQM_FS_ADJ_SEL_B__M 0x3 -#define IQM_FS_ADJ_SEL_B__PRE 0x0 -#define IQM_FS_ADJ_SEL_B_OFF 0x0 -#define IQM_FS_ADJ_SEL_B_QAM 0x1 -#define IQM_FS_ADJ_SEL_B_VSB 0x2 - - - -#define IQM_FD_COMM_EXEC__A 0x1830000 -#define IQM_FD_COMM_EXEC__W 2 -#define IQM_FD_COMM_EXEC__M 0x3 -#define IQM_FD_COMM_EXEC__PRE 0x0 -#define IQM_FD_COMM_EXEC_STOP 0x0 -#define IQM_FD_COMM_EXEC_ACTIVE 0x1 -#define IQM_FD_COMM_EXEC_HOLD 0x2 - -#define IQM_FD_COMM_MB__A 0x1830002 -#define IQM_FD_COMM_MB__W 2 -#define IQM_FD_COMM_MB__M 0x3 -#define IQM_FD_COMM_MB__PRE 0x0 -#define IQM_FD_COMM_MB_CTL__B 0 -#define IQM_FD_COMM_MB_CTL__W 1 -#define IQM_FD_COMM_MB_CTL__M 0x1 -#define IQM_FD_COMM_MB_CTL__PRE 0x0 -#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_FD_COMM_MB_OBS__B 1 -#define IQM_FD_COMM_MB_OBS__W 1 -#define IQM_FD_COMM_MB_OBS__M 0x2 -#define IQM_FD_COMM_MB_OBS__PRE 0x0 -#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_FD_RATESEL__A 0x1830010 -#define IQM_FD_RATESEL__W 2 -#define IQM_FD_RATESEL__M 0x3 -#define IQM_FD_RATESEL__PRE 0x0 -#define IQM_FD_RATESEL_B__B 0 -#define IQM_FD_RATESEL_B__W 2 -#define IQM_FD_RATESEL_B__M 0x3 -#define IQM_FD_RATESEL_B__PRE 0x0 -#define IQM_FD_RATESEL_B_DS0 0x0 -#define IQM_FD_RATESEL_B_DS1 0x1 -#define IQM_FD_RATESEL_B_DS2 0x2 -#define IQM_FD_RATESEL_B_DS3 0x3 - - - -#define IQM_RC_COMM_EXEC__A 0x1840000 -#define IQM_RC_COMM_EXEC__W 2 -#define IQM_RC_COMM_EXEC__M 0x3 -#define IQM_RC_COMM_EXEC__PRE 0x0 -#define IQM_RC_COMM_EXEC_STOP 0x0 -#define IQM_RC_COMM_EXEC_ACTIVE 0x1 -#define IQM_RC_COMM_EXEC_HOLD 0x2 - -#define IQM_RC_COMM_MB__A 0x1840002 -#define IQM_RC_COMM_MB__W 2 -#define IQM_RC_COMM_MB__M 0x3 -#define IQM_RC_COMM_MB__PRE 0x0 -#define IQM_RC_COMM_MB_CTL__B 0 -#define IQM_RC_COMM_MB_CTL__W 1 -#define IQM_RC_COMM_MB_CTL__M 0x1 -#define IQM_RC_COMM_MB_CTL__PRE 0x0 -#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_RC_COMM_MB_OBS__B 1 -#define IQM_RC_COMM_MB_OBS__W 1 -#define IQM_RC_COMM_MB_OBS__M 0x2 -#define IQM_RC_COMM_MB_OBS__PRE 0x0 -#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_RC_RATE_OFS_LO__A 0x1840010 -#define IQM_RC_RATE_OFS_LO__W 16 -#define IQM_RC_RATE_OFS_LO__M 0xFFFF -#define IQM_RC_RATE_OFS_LO__PRE 0x0 -#define IQM_RC_RATE_OFS_LO_B__B 0 -#define IQM_RC_RATE_OFS_LO_B__W 16 -#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF -#define IQM_RC_RATE_OFS_LO_B__PRE 0x0 - -#define IQM_RC_RATE_OFS_HI__A 0x1840011 -#define IQM_RC_RATE_OFS_HI__W 8 -#define IQM_RC_RATE_OFS_HI__M 0xFF -#define IQM_RC_RATE_OFS_HI__PRE 0x0 -#define IQM_RC_RATE_OFS_HI_B__B 0 -#define IQM_RC_RATE_OFS_HI_B__W 8 -#define IQM_RC_RATE_OFS_HI_B__M 0xFF -#define IQM_RC_RATE_OFS_HI_B__PRE 0x0 - -#define IQM_RC_RATE_LO__A 0x1840012 -#define IQM_RC_RATE_LO__W 16 -#define IQM_RC_RATE_LO__M 0xFFFF -#define IQM_RC_RATE_LO__PRE 0x0 -#define IQM_RC_RATE_LO_B__B 0 -#define IQM_RC_RATE_LO_B__W 16 -#define IQM_RC_RATE_LO_B__M 0xFFFF -#define IQM_RC_RATE_LO_B__PRE 0x0 - -#define IQM_RC_RATE_HI__A 0x1840013 -#define IQM_RC_RATE_HI__W 8 -#define IQM_RC_RATE_HI__M 0xFF -#define IQM_RC_RATE_HI__PRE 0x0 -#define IQM_RC_RATE_HI_B__B 0 -#define IQM_RC_RATE_HI_B__W 8 -#define IQM_RC_RATE_HI_B__M 0xFF -#define IQM_RC_RATE_HI_B__PRE 0x0 - -#define IQM_RC_ADJ_SEL__A 0x1840014 -#define IQM_RC_ADJ_SEL__W 2 -#define IQM_RC_ADJ_SEL__M 0x3 -#define IQM_RC_ADJ_SEL__PRE 0x0 - -#define IQM_RC_ADJ_SEL_B__B 0 -#define IQM_RC_ADJ_SEL_B__W 2 -#define IQM_RC_ADJ_SEL_B__M 0x3 -#define IQM_RC_ADJ_SEL_B__PRE 0x0 -#define IQM_RC_ADJ_SEL_B_OFF 0x0 -#define IQM_RC_ADJ_SEL_B_QAM 0x1 -#define IQM_RC_ADJ_SEL_B_VSB 0x2 - -#define IQM_RC_CROUT_ENA__A 0x1840015 -#define IQM_RC_CROUT_ENA__W 1 -#define IQM_RC_CROUT_ENA__M 0x1 -#define IQM_RC_CROUT_ENA__PRE 0x0 - -#define IQM_RC_CROUT_ENA_ENA__B 0 -#define IQM_RC_CROUT_ENA_ENA__W 1 -#define IQM_RC_CROUT_ENA_ENA__M 0x1 -#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 - -#define IQM_RC_STRETCH__A 0x1840016 -#define IQM_RC_STRETCH__W 5 -#define IQM_RC_STRETCH__M 0x1F -#define IQM_RC_STRETCH__PRE 0x0 - -#define IQM_RC_STRETCH_B__B 0 -#define IQM_RC_STRETCH_B__W 5 -#define IQM_RC_STRETCH_B__M 0x1F -#define IQM_RC_STRETCH_B__PRE 0x0 - - - -#define IQM_RT_COMM_EXEC__A 0x1850000 -#define IQM_RT_COMM_EXEC__W 2 -#define IQM_RT_COMM_EXEC__M 0x3 -#define IQM_RT_COMM_EXEC__PRE 0x0 -#define IQM_RT_COMM_EXEC_STOP 0x0 -#define IQM_RT_COMM_EXEC_ACTIVE 0x1 -#define IQM_RT_COMM_EXEC_HOLD 0x2 - -#define IQM_RT_COMM_MB__A 0x1850002 -#define IQM_RT_COMM_MB__W 2 -#define IQM_RT_COMM_MB__M 0x3 -#define IQM_RT_COMM_MB__PRE 0x0 -#define IQM_RT_COMM_MB_CTL__B 0 -#define IQM_RT_COMM_MB_CTL__W 1 -#define IQM_RT_COMM_MB_CTL__M 0x1 -#define IQM_RT_COMM_MB_CTL__PRE 0x0 -#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_RT_COMM_MB_OBS__B 1 -#define IQM_RT_COMM_MB_OBS__W 1 -#define IQM_RT_COMM_MB_OBS__M 0x2 -#define IQM_RT_COMM_MB_OBS__PRE 0x0 -#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_RT_ACTIVE__A 0x1850010 -#define IQM_RT_ACTIVE__W 2 -#define IQM_RT_ACTIVE__M 0x3 -#define IQM_RT_ACTIVE__PRE 0x0 - -#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 -#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 -#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 -#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 -#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 -#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 - -#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 -#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 -#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 -#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 -#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 -#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 - - -#define IQM_RT_LO_INCR__A 0x1850011 -#define IQM_RT_LO_INCR__W 12 -#define IQM_RT_LO_INCR__M 0xFFF -#define IQM_RT_LO_INCR__PRE 0x588 -#define IQM_RT_LO_INCR_FM 0x0 -#define IQM_RT_LO_INCR_MN 0x588 - -#define IQM_RT_ROT_BP__A 0x1850012 -#define IQM_RT_ROT_BP__W 3 -#define IQM_RT_ROT_BP__M 0x7 -#define IQM_RT_ROT_BP__PRE 0x0 - -#define IQM_RT_ROT_BP_ROT_OFF__B 0 -#define IQM_RT_ROT_BP_ROT_OFF__W 1 -#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 -#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 -#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 -#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 - -#define IQM_RT_ROT_BP_ROT_BPF__B 1 -#define IQM_RT_ROT_BP_ROT_BPF__W 1 -#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 -#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 - -#define IQM_RT_ROT_BP_MIX_BP__B 2 -#define IQM_RT_ROT_BP_MIX_BP__W 1 -#define IQM_RT_ROT_BP_MIX_BP__M 0x4 -#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0 - - -#define IQM_RT_LP_BP__A 0x1850013 -#define IQM_RT_LP_BP__W 1 -#define IQM_RT_LP_BP__M 0x1 -#define IQM_RT_LP_BP__PRE 0x0 - -#define IQM_RT_DELAY__A 0x1850014 -#define IQM_RT_DELAY__W 7 -#define IQM_RT_DELAY__M 0x7F -#define IQM_RT_DELAY__PRE 0x45 - - - -#define IQM_CF_COMM_EXEC__A 0x1860000 -#define IQM_CF_COMM_EXEC__W 2 -#define IQM_CF_COMM_EXEC__M 0x3 -#define IQM_CF_COMM_EXEC__PRE 0x0 -#define IQM_CF_COMM_EXEC_STOP 0x0 -#define IQM_CF_COMM_EXEC_ACTIVE 0x1 -#define IQM_CF_COMM_EXEC_HOLD 0x2 - -#define IQM_CF_COMM_MB__A 0x1860002 -#define IQM_CF_COMM_MB__W 2 -#define IQM_CF_COMM_MB__M 0x3 -#define IQM_CF_COMM_MB__PRE 0x0 -#define IQM_CF_COMM_MB_CTL__B 0 -#define IQM_CF_COMM_MB_CTL__W 1 -#define IQM_CF_COMM_MB_CTL__M 0x1 -#define IQM_CF_COMM_MB_CTL__PRE 0x0 -#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_CF_COMM_MB_OBS__B 1 -#define IQM_CF_COMM_MB_OBS__W 1 -#define IQM_CF_COMM_MB_OBS__M 0x2 -#define IQM_CF_COMM_MB_OBS__PRE 0x0 -#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 - -#define IQM_CF_COMM_INT_REQ__A 0x1860003 -#define IQM_CF_COMM_INT_REQ__W 1 -#define IQM_CF_COMM_INT_REQ__M 0x1 -#define IQM_CF_COMM_INT_REQ__PRE 0x0 -#define IQM_CF_COMM_INT_STA__A 0x1860005 -#define IQM_CF_COMM_INT_STA__W 2 -#define IQM_CF_COMM_INT_STA__M 0x3 -#define IQM_CF_COMM_INT_STA__PRE 0x0 -#define IQM_CF_COMM_INT_STA_PM__B 0 -#define IQM_CF_COMM_INT_STA_PM__W 1 -#define IQM_CF_COMM_INT_STA_PM__M 0x1 -#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 -#define IQM_CF_COMM_INT_STA_INC__B 1 -#define IQM_CF_COMM_INT_STA_INC__W 1 -#define IQM_CF_COMM_INT_STA_INC__M 0x2 -#define IQM_CF_COMM_INT_STA_INC__PRE 0x0 - -#define IQM_CF_COMM_INT_MSK__A 0x1860006 -#define IQM_CF_COMM_INT_MSK__W 2 -#define IQM_CF_COMM_INT_MSK__M 0x3 -#define IQM_CF_COMM_INT_MSK__PRE 0x0 -#define IQM_CF_COMM_INT_MSK_PM__B 0 -#define IQM_CF_COMM_INT_MSK_PM__W 1 -#define IQM_CF_COMM_INT_MSK_PM__M 0x1 -#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 -#define IQM_CF_COMM_INT_MSK_INC__B 1 -#define IQM_CF_COMM_INT_MSK_INC__W 1 -#define IQM_CF_COMM_INT_MSK_INC__M 0x2 -#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0 - -#define IQM_CF_COMM_INT_STM__A 0x1860007 -#define IQM_CF_COMM_INT_STM__W 2 -#define IQM_CF_COMM_INT_STM__M 0x3 -#define IQM_CF_COMM_INT_STM__PRE 0x0 -#define IQM_CF_COMM_INT_STM_PM__B 0 -#define IQM_CF_COMM_INT_STM_PM__W 1 -#define IQM_CF_COMM_INT_STM_PM__M 0x1 -#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 -#define IQM_CF_COMM_INT_STM_INC__B 1 -#define IQM_CF_COMM_INT_STM_INC__W 1 -#define IQM_CF_COMM_INT_STM_INC__M 0x2 -#define IQM_CF_COMM_INT_STM_INC__PRE 0x0 - -#define IQM_CF_SYMMETRIC__A 0x1860010 -#define IQM_CF_SYMMETRIC__W 2 -#define IQM_CF_SYMMETRIC__M 0x3 -#define IQM_CF_SYMMETRIC__PRE 0x0 - -#define IQM_CF_SYMMETRIC_RE__B 0 -#define IQM_CF_SYMMETRIC_RE__W 1 -#define IQM_CF_SYMMETRIC_RE__M 0x1 -#define IQM_CF_SYMMETRIC_RE__PRE 0x0 - -#define IQM_CF_SYMMETRIC_IM__B 1 -#define IQM_CF_SYMMETRIC_IM__W 1 -#define IQM_CF_SYMMETRIC_IM__M 0x2 -#define IQM_CF_SYMMETRIC_IM__PRE 0x0 - -#define IQM_CF_MIDTAP__A 0x1860011 -#define IQM_CF_MIDTAP__W 3 -#define IQM_CF_MIDTAP__M 0x7 -#define IQM_CF_MIDTAP__PRE 0x3 - -#define IQM_CF_MIDTAP_RE__B 0 -#define IQM_CF_MIDTAP_RE__W 1 -#define IQM_CF_MIDTAP_RE__M 0x1 -#define IQM_CF_MIDTAP_RE__PRE 0x1 - -#define IQM_CF_MIDTAP_IM__B 1 -#define IQM_CF_MIDTAP_IM__W 1 -#define IQM_CF_MIDTAP_IM__M 0x2 -#define IQM_CF_MIDTAP_IM__PRE 0x2 - -#define IQM_CF_MIDTAP_SCALE__B 2 -#define IQM_CF_MIDTAP_SCALE__W 1 -#define IQM_CF_MIDTAP_SCALE__M 0x4 -#define IQM_CF_MIDTAP_SCALE__PRE 0x0 - -#define IQM_CF_OUT_ENA__A 0x1860012 -#define IQM_CF_OUT_ENA__W 3 -#define IQM_CF_OUT_ENA__M 0x7 -#define IQM_CF_OUT_ENA__PRE 0x0 - -#define IQM_CF_OUT_ENA_ATV__B 0 -#define IQM_CF_OUT_ENA_ATV__W 1 -#define IQM_CF_OUT_ENA_ATV__M 0x1 -#define IQM_CF_OUT_ENA_ATV__PRE 0x0 - -#define IQM_CF_OUT_ENA_QAM__B 1 -#define IQM_CF_OUT_ENA_QAM__W 1 -#define IQM_CF_OUT_ENA_QAM__M 0x2 -#define IQM_CF_OUT_ENA_QAM__PRE 0x0 - -#define IQM_CF_OUT_ENA_OFDM__B 2 -#define IQM_CF_OUT_ENA_OFDM__W 1 -#define IQM_CF_OUT_ENA_OFDM__M 0x4 -#define IQM_CF_OUT_ENA_OFDM__PRE 0x0 - -#define IQM_CF_ADJ_SEL__A 0x1860013 -#define IQM_CF_ADJ_SEL__W 2 -#define IQM_CF_ADJ_SEL__M 0x3 -#define IQM_CF_ADJ_SEL__PRE 0x0 - -#define IQM_CF_ADJ_SEL_B__B 0 -#define IQM_CF_ADJ_SEL_B__W 2 -#define IQM_CF_ADJ_SEL_B__M 0x3 -#define IQM_CF_ADJ_SEL_B__PRE 0x0 - -#define IQM_CF_SCALE__A 0x1860014 -#define IQM_CF_SCALE__W 14 -#define IQM_CF_SCALE__M 0x3FFF -#define IQM_CF_SCALE__PRE 0x400 -#define IQM_CF_SCALE_B__B 0 -#define IQM_CF_SCALE_B__W 14 -#define IQM_CF_SCALE_B__M 0x3FFF -#define IQM_CF_SCALE_B__PRE 0x400 - -#define IQM_CF_SCALE_SH__A 0x1860015 -#define IQM_CF_SCALE_SH__W 2 -#define IQM_CF_SCALE_SH__M 0x3 -#define IQM_CF_SCALE_SH__PRE 0x0 - -#define IQM_CF_SCALE_SH_B__B 0 -#define IQM_CF_SCALE_SH_B__W 2 -#define IQM_CF_SCALE_SH_B__M 0x3 -#define IQM_CF_SCALE_SH_B__PRE 0x0 - -#define IQM_CF_AMP__A 0x1860016 -#define IQM_CF_AMP__W 14 -#define IQM_CF_AMP__M 0x3FFF -#define IQM_CF_AMP__PRE 0x0 - -#define IQM_CF_AMP_B__B 0 -#define IQM_CF_AMP_B__W 14 -#define IQM_CF_AMP_B__M 0x3FFF -#define IQM_CF_AMP_B__PRE 0x0 - -#define IQM_CF_POW_MEAS_LEN__A 0x1860017 -#define IQM_CF_POW_MEAS_LEN__W 3 -#define IQM_CF_POW_MEAS_LEN__M 0x7 -#define IQM_CF_POW_MEAS_LEN__PRE 0x2 - -#define IQM_CF_POW_MEAS_LEN_B__B 0 -#define IQM_CF_POW_MEAS_LEN_B__W 3 -#define IQM_CF_POW_MEAS_LEN_B__M 0x7 -#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2 - -#define IQM_CF_POW__A 0x1860018 -#define IQM_CF_POW__W 16 -#define IQM_CF_POW__M 0xFFFF -#define IQM_CF_POW__PRE 0x2 -#define IQM_CF_POW_B__B 0 -#define IQM_CF_POW_B__W 16 -#define IQM_CF_POW_B__M 0xFFFF -#define IQM_CF_POW_B__PRE 0x2 - -#define IQM_CF_DS_ENA__A 0x1860019 -#define IQM_CF_DS_ENA__W 3 -#define IQM_CF_DS_ENA__M 0x7 -#define IQM_CF_DS_ENA__PRE 0x4 - -#define IQM_CF_DS_ENA_ATV__B 0 -#define IQM_CF_DS_ENA_ATV__W 1 -#define IQM_CF_DS_ENA_ATV__M 0x1 -#define IQM_CF_DS_ENA_ATV__PRE 0x0 - -#define IQM_CF_DS_ENA_QAM__B 1 -#define IQM_CF_DS_ENA_QAM__W 1 -#define IQM_CF_DS_ENA_QAM__M 0x2 -#define IQM_CF_DS_ENA_QAM__PRE 0x0 - -#define IQM_CF_DS_ENA_VSB__B 2 -#define IQM_CF_DS_ENA_VSB__W 1 -#define IQM_CF_DS_ENA_VSB__M 0x4 -#define IQM_CF_DS_ENA_VSB__PRE 0x4 - - -#define IQM_CF_POW_UPD__A 0x186001A -#define IQM_CF_POW_UPD__W 1 -#define IQM_CF_POW_UPD__M 0x1 -#define IQM_CF_POW_UPD__PRE 0x0 -#define IQM_CF_TAP_RE0__A 0x1860020 -#define IQM_CF_TAP_RE0__W 7 -#define IQM_CF_TAP_RE0__M 0x7F -#define IQM_CF_TAP_RE0__PRE 0x2 -#define IQM_CF_TAP_RE0_B__B 0 -#define IQM_CF_TAP_RE0_B__W 7 -#define IQM_CF_TAP_RE0_B__M 0x7F -#define IQM_CF_TAP_RE0_B__PRE 0x2 - -#define IQM_CF_TAP_RE1__A 0x1860021 -#define IQM_CF_TAP_RE1__W 7 -#define IQM_CF_TAP_RE1__M 0x7F -#define IQM_CF_TAP_RE1__PRE 0x2 -#define IQM_CF_TAP_RE1_B__B 0 -#define IQM_CF_TAP_RE1_B__W 7 -#define IQM_CF_TAP_RE1_B__M 0x7F -#define IQM_CF_TAP_RE1_B__PRE 0x2 - -#define IQM_CF_TAP_RE2__A 0x1860022 -#define IQM_CF_TAP_RE2__W 7 -#define IQM_CF_TAP_RE2__M 0x7F -#define IQM_CF_TAP_RE2__PRE 0x2 -#define IQM_CF_TAP_RE2_B__B 0 -#define IQM_CF_TAP_RE2_B__W 7 -#define IQM_CF_TAP_RE2_B__M 0x7F -#define IQM_CF_TAP_RE2_B__PRE 0x2 - -#define IQM_CF_TAP_RE3__A 0x1860023 -#define IQM_CF_TAP_RE3__W 7 -#define IQM_CF_TAP_RE3__M 0x7F -#define IQM_CF_TAP_RE3__PRE 0x2 -#define IQM_CF_TAP_RE3_B__B 0 -#define IQM_CF_TAP_RE3_B__W 7 -#define IQM_CF_TAP_RE3_B__M 0x7F -#define IQM_CF_TAP_RE3_B__PRE 0x2 - -#define IQM_CF_TAP_RE4__A 0x1860024 -#define IQM_CF_TAP_RE4__W 7 -#define IQM_CF_TAP_RE4__M 0x7F -#define IQM_CF_TAP_RE4__PRE 0x2 -#define IQM_CF_TAP_RE4_B__B 0 -#define IQM_CF_TAP_RE4_B__W 7 -#define IQM_CF_TAP_RE4_B__M 0x7F -#define IQM_CF_TAP_RE4_B__PRE 0x2 - -#define IQM_CF_TAP_RE5__A 0x1860025 -#define IQM_CF_TAP_RE5__W 7 -#define IQM_CF_TAP_RE5__M 0x7F -#define IQM_CF_TAP_RE5__PRE 0x2 -#define IQM_CF_TAP_RE5_B__B 0 -#define IQM_CF_TAP_RE5_B__W 7 -#define IQM_CF_TAP_RE5_B__M 0x7F -#define IQM_CF_TAP_RE5_B__PRE 0x2 - -#define IQM_CF_TAP_RE6__A 0x1860026 -#define IQM_CF_TAP_RE6__W 7 -#define IQM_CF_TAP_RE6__M 0x7F -#define IQM_CF_TAP_RE6__PRE 0x2 -#define IQM_CF_TAP_RE6_B__B 0 -#define IQM_CF_TAP_RE6_B__W 7 -#define IQM_CF_TAP_RE6_B__M 0x7F -#define IQM_CF_TAP_RE6_B__PRE 0x2 - -#define IQM_CF_TAP_RE7__A 0x1860027 -#define IQM_CF_TAP_RE7__W 9 -#define IQM_CF_TAP_RE7__M 0x1FF -#define IQM_CF_TAP_RE7__PRE 0x2 -#define IQM_CF_TAP_RE7_B__B 0 -#define IQM_CF_TAP_RE7_B__W 9 -#define IQM_CF_TAP_RE7_B__M 0x1FF -#define IQM_CF_TAP_RE7_B__PRE 0x2 - -#define IQM_CF_TAP_RE8__A 0x1860028 -#define IQM_CF_TAP_RE8__W 9 -#define IQM_CF_TAP_RE8__M 0x1FF -#define IQM_CF_TAP_RE8__PRE 0x2 -#define IQM_CF_TAP_RE8_B__B 0 -#define IQM_CF_TAP_RE8_B__W 9 -#define IQM_CF_TAP_RE8_B__M 0x1FF -#define IQM_CF_TAP_RE8_B__PRE 0x2 - -#define IQM_CF_TAP_RE9__A 0x1860029 -#define IQM_CF_TAP_RE9__W 9 -#define IQM_CF_TAP_RE9__M 0x1FF -#define IQM_CF_TAP_RE9__PRE 0x2 -#define IQM_CF_TAP_RE9_B__B 0 -#define IQM_CF_TAP_RE9_B__W 9 -#define IQM_CF_TAP_RE9_B__M 0x1FF -#define IQM_CF_TAP_RE9_B__PRE 0x2 - -#define IQM_CF_TAP_RE10__A 0x186002A -#define IQM_CF_TAP_RE10__W 9 -#define IQM_CF_TAP_RE10__M 0x1FF -#define IQM_CF_TAP_RE10__PRE 0x2 -#define IQM_CF_TAP_RE10_B__B 0 -#define IQM_CF_TAP_RE10_B__W 9 -#define IQM_CF_TAP_RE10_B__M 0x1FF -#define IQM_CF_TAP_RE10_B__PRE 0x2 - -#define IQM_CF_TAP_RE11__A 0x186002B -#define IQM_CF_TAP_RE11__W 9 -#define IQM_CF_TAP_RE11__M 0x1FF -#define IQM_CF_TAP_RE11__PRE 0x2 -#define IQM_CF_TAP_RE11_B__B 0 -#define IQM_CF_TAP_RE11_B__W 9 -#define IQM_CF_TAP_RE11_B__M 0x1FF -#define IQM_CF_TAP_RE11_B__PRE 0x2 - -#define IQM_CF_TAP_RE12__A 0x186002C -#define IQM_CF_TAP_RE12__W 9 -#define IQM_CF_TAP_RE12__M 0x1FF -#define IQM_CF_TAP_RE12__PRE 0x2 -#define IQM_CF_TAP_RE12_B__B 0 -#define IQM_CF_TAP_RE12_B__W 9 -#define IQM_CF_TAP_RE12_B__M 0x1FF -#define IQM_CF_TAP_RE12_B__PRE 0x2 - -#define IQM_CF_TAP_RE13__A 0x186002D -#define IQM_CF_TAP_RE13__W 9 -#define IQM_CF_TAP_RE13__M 0x1FF -#define IQM_CF_TAP_RE13__PRE 0x2 -#define IQM_CF_TAP_RE13_B__B 0 -#define IQM_CF_TAP_RE13_B__W 9 -#define IQM_CF_TAP_RE13_B__M 0x1FF -#define IQM_CF_TAP_RE13_B__PRE 0x2 - -#define IQM_CF_TAP_RE14__A 0x186002E -#define IQM_CF_TAP_RE14__W 9 -#define IQM_CF_TAP_RE14__M 0x1FF -#define IQM_CF_TAP_RE14__PRE 0x2 -#define IQM_CF_TAP_RE14_B__B 0 -#define IQM_CF_TAP_RE14_B__W 9 -#define IQM_CF_TAP_RE14_B__M 0x1FF -#define IQM_CF_TAP_RE14_B__PRE 0x2 - -#define IQM_CF_TAP_RE15__A 0x186002F -#define IQM_CF_TAP_RE15__W 9 -#define IQM_CF_TAP_RE15__M 0x1FF -#define IQM_CF_TAP_RE15__PRE 0x2 -#define IQM_CF_TAP_RE15_B__B 0 -#define IQM_CF_TAP_RE15_B__W 9 -#define IQM_CF_TAP_RE15_B__M 0x1FF -#define IQM_CF_TAP_RE15_B__PRE 0x2 - -#define IQM_CF_TAP_RE16__A 0x1860030 -#define IQM_CF_TAP_RE16__W 9 -#define IQM_CF_TAP_RE16__M 0x1FF -#define IQM_CF_TAP_RE16__PRE 0x2 -#define IQM_CF_TAP_RE16_B__B 0 -#define IQM_CF_TAP_RE16_B__W 9 -#define IQM_CF_TAP_RE16_B__M 0x1FF -#define IQM_CF_TAP_RE16_B__PRE 0x2 - -#define IQM_CF_TAP_RE17__A 0x1860031 -#define IQM_CF_TAP_RE17__W 9 -#define IQM_CF_TAP_RE17__M 0x1FF -#define IQM_CF_TAP_RE17__PRE 0x2 -#define IQM_CF_TAP_RE17_B__B 0 -#define IQM_CF_TAP_RE17_B__W 9 -#define IQM_CF_TAP_RE17_B__M 0x1FF -#define IQM_CF_TAP_RE17_B__PRE 0x2 - -#define IQM_CF_TAP_RE18__A 0x1860032 -#define IQM_CF_TAP_RE18__W 9 -#define IQM_CF_TAP_RE18__M 0x1FF -#define IQM_CF_TAP_RE18__PRE 0x2 -#define IQM_CF_TAP_RE18_B__B 0 -#define IQM_CF_TAP_RE18_B__W 9 -#define IQM_CF_TAP_RE18_B__M 0x1FF -#define IQM_CF_TAP_RE18_B__PRE 0x2 - -#define IQM_CF_TAP_RE19__A 0x1860033 -#define IQM_CF_TAP_RE19__W 9 -#define IQM_CF_TAP_RE19__M 0x1FF -#define IQM_CF_TAP_RE19__PRE 0x2 -#define IQM_CF_TAP_RE19_B__B 0 -#define IQM_CF_TAP_RE19_B__W 9 -#define IQM_CF_TAP_RE19_B__M 0x1FF -#define IQM_CF_TAP_RE19_B__PRE 0x2 - -#define IQM_CF_TAP_RE20__A 0x1860034 -#define IQM_CF_TAP_RE20__W 9 -#define IQM_CF_TAP_RE20__M 0x1FF -#define IQM_CF_TAP_RE20__PRE 0x2 -#define IQM_CF_TAP_RE20_B__B 0 -#define IQM_CF_TAP_RE20_B__W 9 -#define IQM_CF_TAP_RE20_B__M 0x1FF -#define IQM_CF_TAP_RE20_B__PRE 0x2 - -#define IQM_CF_TAP_RE21__A 0x1860035 -#define IQM_CF_TAP_RE21__W 11 -#define IQM_CF_TAP_RE21__M 0x7FF -#define IQM_CF_TAP_RE21__PRE 0x2 -#define IQM_CF_TAP_RE21_B__B 0 -#define IQM_CF_TAP_RE21_B__W 11 -#define IQM_CF_TAP_RE21_B__M 0x7FF -#define IQM_CF_TAP_RE21_B__PRE 0x2 - -#define IQM_CF_TAP_RE22__A 0x1860036 -#define IQM_CF_TAP_RE22__W 11 -#define IQM_CF_TAP_RE22__M 0x7FF -#define IQM_CF_TAP_RE22__PRE 0x2 -#define IQM_CF_TAP_RE22_B__B 0 -#define IQM_CF_TAP_RE22_B__W 11 -#define IQM_CF_TAP_RE22_B__M 0x7FF -#define IQM_CF_TAP_RE22_B__PRE 0x2 - -#define IQM_CF_TAP_RE23__A 0x1860037 -#define IQM_CF_TAP_RE23__W 11 -#define IQM_CF_TAP_RE23__M 0x7FF -#define IQM_CF_TAP_RE23__PRE 0x2 -#define IQM_CF_TAP_RE23_B__B 0 -#define IQM_CF_TAP_RE23_B__W 11 -#define IQM_CF_TAP_RE23_B__M 0x7FF -#define IQM_CF_TAP_RE23_B__PRE 0x2 - -#define IQM_CF_TAP_RE24__A 0x1860038 -#define IQM_CF_TAP_RE24__W 11 -#define IQM_CF_TAP_RE24__M 0x7FF -#define IQM_CF_TAP_RE24__PRE 0x2 -#define IQM_CF_TAP_RE24_B__B 0 -#define IQM_CF_TAP_RE24_B__W 11 -#define IQM_CF_TAP_RE24_B__M 0x7FF -#define IQM_CF_TAP_RE24_B__PRE 0x2 - -#define IQM_CF_TAP_RE25__A 0x1860039 -#define IQM_CF_TAP_RE25__W 11 -#define IQM_CF_TAP_RE25__M 0x7FF -#define IQM_CF_TAP_RE25__PRE 0x2 -#define IQM_CF_TAP_RE25_B__B 0 -#define IQM_CF_TAP_RE25_B__W 11 -#define IQM_CF_TAP_RE25_B__M 0x7FF -#define IQM_CF_TAP_RE25_B__PRE 0x2 - -#define IQM_CF_TAP_RE26__A 0x186003A -#define IQM_CF_TAP_RE26__W 11 -#define IQM_CF_TAP_RE26__M 0x7FF -#define IQM_CF_TAP_RE26__PRE 0x2 -#define IQM_CF_TAP_RE26_B__B 0 -#define IQM_CF_TAP_RE26_B__W 11 -#define IQM_CF_TAP_RE26_B__M 0x7FF -#define IQM_CF_TAP_RE26_B__PRE 0x2 - -#define IQM_CF_TAP_RE27__A 0x186003B -#define IQM_CF_TAP_RE27__W 11 -#define IQM_CF_TAP_RE27__M 0x7FF -#define IQM_CF_TAP_RE27__PRE 0x2 -#define IQM_CF_TAP_RE27_B__B 0 -#define IQM_CF_TAP_RE27_B__W 11 -#define IQM_CF_TAP_RE27_B__M 0x7FF -#define IQM_CF_TAP_RE27_B__PRE 0x2 - -#define IQM_CF_TAP_IM0__A 0x1860040 -#define IQM_CF_TAP_IM0__W 7 -#define IQM_CF_TAP_IM0__M 0x7F -#define IQM_CF_TAP_IM0__PRE 0x2 -#define IQM_CF_TAP_IM0_B__B 0 -#define IQM_CF_TAP_IM0_B__W 7 -#define IQM_CF_TAP_IM0_B__M 0x7F -#define IQM_CF_TAP_IM0_B__PRE 0x2 - -#define IQM_CF_TAP_IM1__A 0x1860041 -#define IQM_CF_TAP_IM1__W 7 -#define IQM_CF_TAP_IM1__M 0x7F -#define IQM_CF_TAP_IM1__PRE 0x2 -#define IQM_CF_TAP_IM1_B__B 0 -#define IQM_CF_TAP_IM1_B__W 7 -#define IQM_CF_TAP_IM1_B__M 0x7F -#define IQM_CF_TAP_IM1_B__PRE 0x2 - -#define IQM_CF_TAP_IM2__A 0x1860042 -#define IQM_CF_TAP_IM2__W 7 -#define IQM_CF_TAP_IM2__M 0x7F -#define IQM_CF_TAP_IM2__PRE 0x2 -#define IQM_CF_TAP_IM2_B__B 0 -#define IQM_CF_TAP_IM2_B__W 7 -#define IQM_CF_TAP_IM2_B__M 0x7F -#define IQM_CF_TAP_IM2_B__PRE 0x2 - -#define IQM_CF_TAP_IM3__A 0x1860043 -#define IQM_CF_TAP_IM3__W 7 -#define IQM_CF_TAP_IM3__M 0x7F -#define IQM_CF_TAP_IM3__PRE 0x2 -#define IQM_CF_TAP_IM3_B__B 0 -#define IQM_CF_TAP_IM3_B__W 7 -#define IQM_CF_TAP_IM3_B__M 0x7F -#define IQM_CF_TAP_IM3_B__PRE 0x2 - -#define IQM_CF_TAP_IM4__A 0x1860044 -#define IQM_CF_TAP_IM4__W 7 -#define IQM_CF_TAP_IM4__M 0x7F -#define IQM_CF_TAP_IM4__PRE 0x2 -#define IQM_CF_TAP_IM4_B__B 0 -#define IQM_CF_TAP_IM4_B__W 7 -#define IQM_CF_TAP_IM4_B__M 0x7F -#define IQM_CF_TAP_IM4_B__PRE 0x2 - -#define IQM_CF_TAP_IM5__A 0x1860045 -#define IQM_CF_TAP_IM5__W 7 -#define IQM_CF_TAP_IM5__M 0x7F -#define IQM_CF_TAP_IM5__PRE 0x2 -#define IQM_CF_TAP_IM5_B__B 0 -#define IQM_CF_TAP_IM5_B__W 7 -#define IQM_CF_TAP_IM5_B__M 0x7F -#define IQM_CF_TAP_IM5_B__PRE 0x2 - -#define IQM_CF_TAP_IM6__A 0x1860046 -#define IQM_CF_TAP_IM6__W 7 -#define IQM_CF_TAP_IM6__M 0x7F -#define IQM_CF_TAP_IM6__PRE 0x2 -#define IQM_CF_TAP_IM6_B__B 0 -#define IQM_CF_TAP_IM6_B__W 7 -#define IQM_CF_TAP_IM6_B__M 0x7F -#define IQM_CF_TAP_IM6_B__PRE 0x2 - -#define IQM_CF_TAP_IM7__A 0x1860047 -#define IQM_CF_TAP_IM7__W 9 -#define IQM_CF_TAP_IM7__M 0x1FF -#define IQM_CF_TAP_IM7__PRE 0x2 -#define IQM_CF_TAP_IM7_B__B 0 -#define IQM_CF_TAP_IM7_B__W 9 -#define IQM_CF_TAP_IM7_B__M 0x1FF -#define IQM_CF_TAP_IM7_B__PRE 0x2 - -#define IQM_CF_TAP_IM8__A 0x1860048 -#define IQM_CF_TAP_IM8__W 9 -#define IQM_CF_TAP_IM8__M 0x1FF -#define IQM_CF_TAP_IM8__PRE 0x2 -#define IQM_CF_TAP_IM8_B__B 0 -#define IQM_CF_TAP_IM8_B__W 9 -#define IQM_CF_TAP_IM8_B__M 0x1FF -#define IQM_CF_TAP_IM8_B__PRE 0x2 - -#define IQM_CF_TAP_IM9__A 0x1860049 -#define IQM_CF_TAP_IM9__W 9 -#define IQM_CF_TAP_IM9__M 0x1FF -#define IQM_CF_TAP_IM9__PRE 0x2 -#define IQM_CF_TAP_IM9_B__B 0 -#define IQM_CF_TAP_IM9_B__W 9 -#define IQM_CF_TAP_IM9_B__M 0x1FF -#define IQM_CF_TAP_IM9_B__PRE 0x2 - -#define IQM_CF_TAP_IM10__A 0x186004A -#define IQM_CF_TAP_IM10__W 9 -#define IQM_CF_TAP_IM10__M 0x1FF -#define IQM_CF_TAP_IM10__PRE 0x2 -#define IQM_CF_TAP_IM10_B__B 0 -#define IQM_CF_TAP_IM10_B__W 9 -#define IQM_CF_TAP_IM10_B__M 0x1FF -#define IQM_CF_TAP_IM10_B__PRE 0x2 - -#define IQM_CF_TAP_IM11__A 0x186004B -#define IQM_CF_TAP_IM11__W 9 -#define IQM_CF_TAP_IM11__M 0x1FF -#define IQM_CF_TAP_IM11__PRE 0x2 -#define IQM_CF_TAP_IM11_B__B 0 -#define IQM_CF_TAP_IM11_B__W 9 -#define IQM_CF_TAP_IM11_B__M 0x1FF -#define IQM_CF_TAP_IM11_B__PRE 0x2 - -#define IQM_CF_TAP_IM12__A 0x186004C -#define IQM_CF_TAP_IM12__W 9 -#define IQM_CF_TAP_IM12__M 0x1FF -#define IQM_CF_TAP_IM12__PRE 0x2 -#define IQM_CF_TAP_IM12_B__B 0 -#define IQM_CF_TAP_IM12_B__W 9 -#define IQM_CF_TAP_IM12_B__M 0x1FF -#define IQM_CF_TAP_IM12_B__PRE 0x2 - -#define IQM_CF_TAP_IM13__A 0x186004D -#define IQM_CF_TAP_IM13__W 9 -#define IQM_CF_TAP_IM13__M 0x1FF -#define IQM_CF_TAP_IM13__PRE 0x2 -#define IQM_CF_TAP_IM13_B__B 0 -#define IQM_CF_TAP_IM13_B__W 9 -#define IQM_CF_TAP_IM13_B__M 0x1FF -#define IQM_CF_TAP_IM13_B__PRE 0x2 - -#define IQM_CF_TAP_IM14__A 0x186004E -#define IQM_CF_TAP_IM14__W 9 -#define IQM_CF_TAP_IM14__M 0x1FF -#define IQM_CF_TAP_IM14__PRE 0x2 -#define IQM_CF_TAP_IM14_B__B 0 -#define IQM_CF_TAP_IM14_B__W 9 -#define IQM_CF_TAP_IM14_B__M 0x1FF -#define IQM_CF_TAP_IM14_B__PRE 0x2 - -#define IQM_CF_TAP_IM15__A 0x186004F -#define IQM_CF_TAP_IM15__W 9 -#define IQM_CF_TAP_IM15__M 0x1FF -#define IQM_CF_TAP_IM15__PRE 0x2 -#define IQM_CF_TAP_IM15_B__B 0 -#define IQM_CF_TAP_IM15_B__W 9 -#define IQM_CF_TAP_IM15_B__M 0x1FF -#define IQM_CF_TAP_IM15_B__PRE 0x2 - -#define IQM_CF_TAP_IM16__A 0x1860050 -#define IQM_CF_TAP_IM16__W 9 -#define IQM_CF_TAP_IM16__M 0x1FF -#define IQM_CF_TAP_IM16__PRE 0x2 -#define IQM_CF_TAP_IM16_B__B 0 -#define IQM_CF_TAP_IM16_B__W 9 -#define IQM_CF_TAP_IM16_B__M 0x1FF -#define IQM_CF_TAP_IM16_B__PRE 0x2 - -#define IQM_CF_TAP_IM17__A 0x1860051 -#define IQM_CF_TAP_IM17__W 9 -#define IQM_CF_TAP_IM17__M 0x1FF -#define IQM_CF_TAP_IM17__PRE 0x2 -#define IQM_CF_TAP_IM17_B__B 0 -#define IQM_CF_TAP_IM17_B__W 9 -#define IQM_CF_TAP_IM17_B__M 0x1FF -#define IQM_CF_TAP_IM17_B__PRE 0x2 - -#define IQM_CF_TAP_IM18__A 0x1860052 -#define IQM_CF_TAP_IM18__W 9 -#define IQM_CF_TAP_IM18__M 0x1FF -#define IQM_CF_TAP_IM18__PRE 0x2 -#define IQM_CF_TAP_IM18_B__B 0 -#define IQM_CF_TAP_IM18_B__W 9 -#define IQM_CF_TAP_IM18_B__M 0x1FF -#define IQM_CF_TAP_IM18_B__PRE 0x2 - -#define IQM_CF_TAP_IM19__A 0x1860053 -#define IQM_CF_TAP_IM19__W 9 -#define IQM_CF_TAP_IM19__M 0x1FF -#define IQM_CF_TAP_IM19__PRE 0x2 -#define IQM_CF_TAP_IM19_B__B 0 -#define IQM_CF_TAP_IM19_B__W 9 -#define IQM_CF_TAP_IM19_B__M 0x1FF -#define IQM_CF_TAP_IM19_B__PRE 0x2 - -#define IQM_CF_TAP_IM20__A 0x1860054 -#define IQM_CF_TAP_IM20__W 9 -#define IQM_CF_TAP_IM20__M 0x1FF -#define IQM_CF_TAP_IM20__PRE 0x2 -#define IQM_CF_TAP_IM20_B__B 0 -#define IQM_CF_TAP_IM20_B__W 9 -#define IQM_CF_TAP_IM20_B__M 0x1FF -#define IQM_CF_TAP_IM20_B__PRE 0x2 - -#define IQM_CF_TAP_IM21__A 0x1860055 -#define IQM_CF_TAP_IM21__W 11 -#define IQM_CF_TAP_IM21__M 0x7FF -#define IQM_CF_TAP_IM21__PRE 0x2 -#define IQM_CF_TAP_IM21_B__B 0 -#define IQM_CF_TAP_IM21_B__W 11 -#define IQM_CF_TAP_IM21_B__M 0x7FF -#define IQM_CF_TAP_IM21_B__PRE 0x2 - -#define IQM_CF_TAP_IM22__A 0x1860056 -#define IQM_CF_TAP_IM22__W 11 -#define IQM_CF_TAP_IM22__M 0x7FF -#define IQM_CF_TAP_IM22__PRE 0x2 -#define IQM_CF_TAP_IM22_B__B 0 -#define IQM_CF_TAP_IM22_B__W 11 -#define IQM_CF_TAP_IM22_B__M 0x7FF -#define IQM_CF_TAP_IM22_B__PRE 0x2 - -#define IQM_CF_TAP_IM23__A 0x1860057 -#define IQM_CF_TAP_IM23__W 11 -#define IQM_CF_TAP_IM23__M 0x7FF -#define IQM_CF_TAP_IM23__PRE 0x2 -#define IQM_CF_TAP_IM23_B__B 0 -#define IQM_CF_TAP_IM23_B__W 11 -#define IQM_CF_TAP_IM23_B__M 0x7FF -#define IQM_CF_TAP_IM23_B__PRE 0x2 - -#define IQM_CF_TAP_IM24__A 0x1860058 -#define IQM_CF_TAP_IM24__W 11 -#define IQM_CF_TAP_IM24__M 0x7FF -#define IQM_CF_TAP_IM24__PRE 0x2 -#define IQM_CF_TAP_IM24_B__B 0 -#define IQM_CF_TAP_IM24_B__W 11 -#define IQM_CF_TAP_IM24_B__M 0x7FF -#define IQM_CF_TAP_IM24_B__PRE 0x2 - -#define IQM_CF_TAP_IM25__A 0x1860059 -#define IQM_CF_TAP_IM25__W 11 -#define IQM_CF_TAP_IM25__M 0x7FF -#define IQM_CF_TAP_IM25__PRE 0x2 -#define IQM_CF_TAP_IM25_B__B 0 -#define IQM_CF_TAP_IM25_B__W 11 -#define IQM_CF_TAP_IM25_B__M 0x7FF -#define IQM_CF_TAP_IM25_B__PRE 0x2 - -#define IQM_CF_TAP_IM26__A 0x186005A -#define IQM_CF_TAP_IM26__W 11 -#define IQM_CF_TAP_IM26__M 0x7FF -#define IQM_CF_TAP_IM26__PRE 0x2 -#define IQM_CF_TAP_IM26_B__B 0 -#define IQM_CF_TAP_IM26_B__W 11 -#define IQM_CF_TAP_IM26_B__M 0x7FF -#define IQM_CF_TAP_IM26_B__PRE 0x2 - -#define IQM_CF_TAP_IM27__A 0x186005B -#define IQM_CF_TAP_IM27__W 11 -#define IQM_CF_TAP_IM27__M 0x7FF -#define IQM_CF_TAP_IM27__PRE 0x2 -#define IQM_CF_TAP_IM27_B__B 0 -#define IQM_CF_TAP_IM27_B__W 11 -#define IQM_CF_TAP_IM27_B__M 0x7FF -#define IQM_CF_TAP_IM27_B__PRE 0x2 - - -#define IQM_CF_CLP_VAL__A 0x1860060 -#define IQM_CF_CLP_VAL__W 9 -#define IQM_CF_CLP_VAL__M 0x1FF -#define IQM_CF_CLP_VAL__PRE 0x3C - -#define IQM_CF_DATATH__A 0x1860061 -#define IQM_CF_DATATH__W 10 -#define IQM_CF_DATATH__M 0x3FF -#define IQM_CF_DATATH__PRE 0x180 - -#define IQM_CF_PKDTH__A 0x1860062 -#define IQM_CF_PKDTH__W 5 -#define IQM_CF_PKDTH__M 0x1F -#define IQM_CF_PKDTH__PRE 0x1 - -#define IQM_CF_WND_LEN__A 0x1860063 -#define IQM_CF_WND_LEN__W 4 -#define IQM_CF_WND_LEN__M 0xF -#define IQM_CF_WND_LEN__PRE 0x1 - -#define IQM_CF_DET_LCT__A 0x1860064 -#define IQM_CF_DET_LCT__W 1 -#define IQM_CF_DET_LCT__M 0x1 -#define IQM_CF_DET_LCT__PRE 0x1 - -#define IQM_CF_SNS_LEN__A 0x1860065 -#define IQM_CF_SNS_LEN__W 16 -#define IQM_CF_SNS_LEN__M 0xFFFF -#define IQM_CF_SNS_LEN__PRE 0x0 - -#define IQM_CF_SNS_SENSE__A 0x1860066 -#define IQM_CF_SNS_SENSE__W 16 -#define IQM_CF_SNS_SENSE__M 0xFFFF -#define IQM_CF_SNS_SENSE__PRE 0x0 - -#define IQM_CF_BYPASSDET__A 0x1860067 -#define IQM_CF_BYPASSDET__W 1 -#define IQM_CF_BYPASSDET__M 0x1 -#define IQM_CF_BYPASSDET__PRE 0x0 - -#define IQM_CF_UPD_ENA__A 0x1860068 -#define IQM_CF_UPD_ENA__W 1 -#define IQM_CF_UPD_ENA__M 0x1 -#define IQM_CF_UPD_ENA__PRE 0x0 -#define IQM_CF_UPD_ENA_DISABLE 0x0 -#define IQM_CF_UPD_ENA_ENABLE 0x1 - - - -#define IQM_AF_COMM_EXEC__A 0x1870000 -#define IQM_AF_COMM_EXEC__W 2 -#define IQM_AF_COMM_EXEC__M 0x3 -#define IQM_AF_COMM_EXEC__PRE 0x0 -#define IQM_AF_COMM_EXEC_STOP 0x0 -#define IQM_AF_COMM_EXEC_ACTIVE 0x1 -#define IQM_AF_COMM_EXEC_HOLD 0x2 - -#define IQM_AF_COMM_MB__A 0x1870002 -#define IQM_AF_COMM_MB__W 8 -#define IQM_AF_COMM_MB__M 0xFF -#define IQM_AF_COMM_MB__PRE 0x0 -#define IQM_AF_COMM_MB_CTL__B 0 -#define IQM_AF_COMM_MB_CTL__W 1 -#define IQM_AF_COMM_MB_CTL__M 0x1 -#define IQM_AF_COMM_MB_CTL__PRE 0x0 -#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 -#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 -#define IQM_AF_COMM_MB_OBS__B 1 -#define IQM_AF_COMM_MB_OBS__W 1 -#define IQM_AF_COMM_MB_OBS__M 0x2 -#define IQM_AF_COMM_MB_OBS__PRE 0x0 -#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 -#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 -#define IQM_AF_COMM_MB_MUX_CTRL__B 2 -#define IQM_AF_COMM_MB_MUX_CTRL__W 3 -#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C -#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 -#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 -#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 -#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 -#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC -#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 -#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14 -#define IQM_AF_COMM_MB_MUX_OBS__B 5 -#define IQM_AF_COMM_MB_MUX_OBS__W 3 -#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 -#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 -#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 -#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 -#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 -#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 -#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 -#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0 - -#define IQM_AF_COMM_INT_REQ__A 0x1870003 -#define IQM_AF_COMM_INT_REQ__W 1 -#define IQM_AF_COMM_INT_REQ__M 0x1 -#define IQM_AF_COMM_INT_REQ__PRE 0x0 -#define IQM_AF_COMM_INT_STA__A 0x1870005 -#define IQM_AF_COMM_INT_STA__W 3 -#define IQM_AF_COMM_INT_STA__M 0x7 -#define IQM_AF_COMM_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 -#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 -#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4 -#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0 - -#define IQM_AF_COMM_INT_MSK__A 0x1870006 -#define IQM_AF_COMM_INT_MSK__W 3 -#define IQM_AF_COMM_INT_MSK__M 0x7 -#define IQM_AF_COMM_INT_MSK__PRE 0x0 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 -#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 -#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4 -#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0 - -#define IQM_AF_COMM_INT_STM__A 0x1870007 -#define IQM_AF_COMM_INT_STM__W 3 -#define IQM_AF_COMM_INT_STM__M 0x7 -#define IQM_AF_COMM_INT_STM__PRE 0x0 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 -#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 -#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4 -#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0 - - -#define IQM_AF_FDB_SEL__A 0x1870010 -#define IQM_AF_FDB_SEL__W 2 -#define IQM_AF_FDB_SEL__M 0x3 -#define IQM_AF_FDB_SEL__PRE 0x0 -#define IQM_AF_CLKNEG__A 0x1870012 -#define IQM_AF_CLKNEG__W 2 -#define IQM_AF_CLKNEG__M 0x3 -#define IQM_AF_CLKNEG__PRE 0x0 - -#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 -#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 -#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 -#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 -#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 -#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 - -#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 -#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 -#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 -#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 - - -#define IQM_AF_MON_IN_MUX__A 0x1870013 -#define IQM_AF_MON_IN_MUX__W 2 -#define IQM_AF_MON_IN_MUX__M 0x3 -#define IQM_AF_MON_IN_MUX__PRE 0x0 - -#define IQM_AF_MON_IN5__A 0x1870014 -#define IQM_AF_MON_IN5__W 10 -#define IQM_AF_MON_IN5__M 0x3FF -#define IQM_AF_MON_IN5__PRE 0x0 - -#define IQM_AF_MON_IN4__A 0x1870015 -#define IQM_AF_MON_IN4__W 10 -#define IQM_AF_MON_IN4__M 0x3FF -#define IQM_AF_MON_IN4__PRE 0x0 - -#define IQM_AF_MON_IN3__A 0x1870016 -#define IQM_AF_MON_IN3__W 10 -#define IQM_AF_MON_IN3__M 0x3FF -#define IQM_AF_MON_IN3__PRE 0x0 - -#define IQM_AF_MON_IN2__A 0x1870017 -#define IQM_AF_MON_IN2__W 10 -#define IQM_AF_MON_IN2__M 0x3FF -#define IQM_AF_MON_IN2__PRE 0x0 - -#define IQM_AF_MON_IN1__A 0x1870018 -#define IQM_AF_MON_IN1__W 10 -#define IQM_AF_MON_IN1__M 0x3FF -#define IQM_AF_MON_IN1__PRE 0x0 - -#define IQM_AF_MON_IN0__A 0x1870019 -#define IQM_AF_MON_IN0__W 10 -#define IQM_AF_MON_IN0__M 0x3FF -#define IQM_AF_MON_IN0__PRE 0x0 - -#define IQM_AF_MON_IN_VAL__A 0x187001A -#define IQM_AF_MON_IN_VAL__W 1 -#define IQM_AF_MON_IN_VAL__M 0x1 -#define IQM_AF_MON_IN_VAL__PRE 0x0 - -#define IQM_AF_START_LOCK__A 0x187001B -#define IQM_AF_START_LOCK__W 1 -#define IQM_AF_START_LOCK__M 0x1 -#define IQM_AF_START_LOCK__PRE 0x0 - -#define IQM_AF_PHASE0__A 0x187001C -#define IQM_AF_PHASE0__W 7 -#define IQM_AF_PHASE0__M 0x7F -#define IQM_AF_PHASE0__PRE 0x0 - -#define IQM_AF_PHASE1__A 0x187001D -#define IQM_AF_PHASE1__W 7 -#define IQM_AF_PHASE1__M 0x7F -#define IQM_AF_PHASE1__PRE 0x0 - -#define IQM_AF_PHASE2__A 0x187001E -#define IQM_AF_PHASE2__W 7 -#define IQM_AF_PHASE2__M 0x7F -#define IQM_AF_PHASE2__PRE 0x0 - -#define IQM_AF_SCU_PHASE__A 0x187001F -#define IQM_AF_SCU_PHASE__W 2 -#define IQM_AF_SCU_PHASE__M 0x3 -#define IQM_AF_SCU_PHASE__PRE 0x0 - -#define IQM_AF_SYNC_SEL__A 0x1870020 -#define IQM_AF_SYNC_SEL__W 2 -#define IQM_AF_SYNC_SEL__M 0x3 -#define IQM_AF_SYNC_SEL__PRE 0x0 -#define IQM_AF_ADC_CONF__A 0x1870021 -#define IQM_AF_ADC_CONF__W 4 -#define IQM_AF_ADC_CONF__M 0xF -#define IQM_AF_ADC_CONF__PRE 0x0 - -#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 -#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 -#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 -#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 -#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 -#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 - -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 - -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 - -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 -#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 - - -#define IQM_AF_CLP_CLIP__A 0x1870022 -#define IQM_AF_CLP_CLIP__W 16 -#define IQM_AF_CLP_CLIP__M 0xFFFF -#define IQM_AF_CLP_CLIP__PRE 0x0 - -#define IQM_AF_CLP_LEN__A 0x1870023 -#define IQM_AF_CLP_LEN__W 16 -#define IQM_AF_CLP_LEN__M 0xFFFF -#define IQM_AF_CLP_LEN__PRE 0x0 - -#define IQM_AF_CLP_TH__A 0x1870024 -#define IQM_AF_CLP_TH__W 9 -#define IQM_AF_CLP_TH__M 0x1FF -#define IQM_AF_CLP_TH__PRE 0x0 - -#define IQM_AF_DCF_BYPASS__A 0x1870025 -#define IQM_AF_DCF_BYPASS__W 1 -#define IQM_AF_DCF_BYPASS__M 0x1 -#define IQM_AF_DCF_BYPASS__PRE 0x0 -#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 -#define IQM_AF_DCF_BYPASS_BYPASS 0x1 - - -#define IQM_AF_SNS_LEN__A 0x1870026 -#define IQM_AF_SNS_LEN__W 16 -#define IQM_AF_SNS_LEN__M 0xFFFF -#define IQM_AF_SNS_LEN__PRE 0x0 - -#define IQM_AF_SNS_SENSE__A 0x1870027 -#define IQM_AF_SNS_SENSE__W 16 -#define IQM_AF_SNS_SENSE__M 0xFFFF -#define IQM_AF_SNS_SENSE__PRE 0x0 - -#define IQM_AF_AGC_IF__A 0x1870028 -#define IQM_AF_AGC_IF__W 15 -#define IQM_AF_AGC_IF__M 0x7FFF -#define IQM_AF_AGC_IF__PRE 0x0 - -#define IQM_AF_AGC_RF__A 0x1870029 -#define IQM_AF_AGC_RF__W 15 -#define IQM_AF_AGC_RF__M 0x7FFF -#define IQM_AF_AGC_RF__PRE 0x0 - -#define IQM_AF_PDREF__A 0x187002B -#define IQM_AF_PDREF__W 5 -#define IQM_AF_PDREF__M 0x1F -#define IQM_AF_PDREF__PRE 0x0 -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_STDBY__W 6 -#define IQM_AF_STDBY__M 0x3F -#define IQM_AF_STDBY__PRE 0x3E - -#define IQM_AF_STDBY_STDBY_BIAS__B 0 -#define IQM_AF_STDBY_STDBY_BIAS__W 1 -#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 -#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 -#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 - -#define IQM_AF_STDBY_STDBY_ADC__B 1 -#define IQM_AF_STDBY_STDBY_ADC__W 1 -#define IQM_AF_STDBY_STDBY_ADC__M 0x2 -#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2 -#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 - -#define IQM_AF_STDBY_STDBY_AMP__B 2 -#define IQM_AF_STDBY_STDBY_AMP__W 1 -#define IQM_AF_STDBY_STDBY_AMP__M 0x4 -#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4 -#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 - -#define IQM_AF_STDBY_STDBY_PD__B 3 -#define IQM_AF_STDBY_STDBY_PD__W 1 -#define IQM_AF_STDBY_STDBY_PD__M 0x8 -#define IQM_AF_STDBY_STDBY_PD__PRE 0x8 -#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 - -#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 -#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 -#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 - -#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 -#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 -#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 -#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20 -#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0 -#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 - - -#define IQM_AF_AMUX__A 0x187002D -#define IQM_AF_AMUX__W 1 -#define IQM_AF_AMUX__M 0x1 -#define IQM_AF_AMUX__PRE 0x0 -#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 -#define IQM_AF_AMUX_SIGNAL2ADC 0x1 - - -#define IQM_AF_TST_AFEMAIN__A 0x187002E -#define IQM_AF_TST_AFEMAIN__W 8 -#define IQM_AF_TST_AFEMAIN__M 0xFF -#define IQM_AF_TST_AFEMAIN__PRE 0x0 - -#define IQM_AF_UPD_SEL__A 0x187002F -#define IQM_AF_UPD_SEL__W 1 -#define IQM_AF_UPD_SEL__M 0x1 -#define IQM_AF_UPD_SEL__PRE 0x0 - -#define IQM_AF_INC_DATATH__A 0x1870030 -#define IQM_AF_INC_DATATH__W 9 -#define IQM_AF_INC_DATATH__M 0x1FF -#define IQM_AF_INC_DATATH__PRE 0x180 - -#define IQM_AF_INC_PKDTH__A 0x1870031 -#define IQM_AF_INC_PKDTH__W 5 -#define IQM_AF_INC_PKDTH__M 0x1F -#define IQM_AF_INC_PKDTH__PRE 0x3 - -#define IQM_AF_INC_WND_LEN__A 0x1870032 -#define IQM_AF_INC_WND_LEN__W 4 -#define IQM_AF_INC_WND_LEN__M 0xF -#define IQM_AF_INC_WND_LEN__PRE 0xA - -#define IQM_AF_INC_DLY__A 0x1870033 -#define IQM_AF_INC_DLY__W 7 -#define IQM_AF_INC_DLY__M 0x7F -#define IQM_AF_INC_DLY__PRE 0x14 - -#define IQM_AF_INC_LCT__A 0x1870034 -#define IQM_AF_INC_LCT__W 1 -#define IQM_AF_INC_LCT__M 0x1 -#define IQM_AF_INC_LCT__PRE 0x1 - -#define IQM_AF_INC_CLP_VAL__A 0x1870035 -#define IQM_AF_INC_CLP_VAL__W 9 -#define IQM_AF_INC_CLP_VAL__M 0x1FF -#define IQM_AF_INC_CLP_VAL__PRE 0x3C - -#define IQM_AF_INC_BYPASS__A 0x1870036 -#define IQM_AF_INC_BYPASS__W 1 -#define IQM_AF_INC_BYPASS__M 0x1 -#define IQM_AF_INC_BYPASS__PRE 0x1 - -#define IQM_AF_INC_MODE_SEL__A 0x1870037 -#define IQM_AF_INC_MODE_SEL__W 2 -#define IQM_AF_INC_MODE_SEL__M 0x3 -#define IQM_AF_INC_MODE_SEL__PRE 0x1 - -#define IQM_AF_INC_A_DLY__A 0x1870038 -#define IQM_AF_INC_A_DLY__W 6 -#define IQM_AF_INC_A_DLY__M 0x3F -#define IQM_AF_INC_A_DLY__PRE 0xF - -#define IQM_AF_ISNS_LEN__A 0x1870039 -#define IQM_AF_ISNS_LEN__W 16 -#define IQM_AF_ISNS_LEN__M 0xFFFF -#define IQM_AF_ISNS_LEN__PRE 0x0 - -#define IQM_AF_ISNS_SENSE__A 0x187003A -#define IQM_AF_ISNS_SENSE__W 16 -#define IQM_AF_ISNS_SENSE__M 0xFFFF -#define IQM_AF_ISNS_SENSE__PRE 0x0 -#define IQM_AF_CMP_STATE__A 0x187003B -#define IQM_AF_CMP_STATE__W 7 -#define IQM_AF_CMP_STATE__M 0x7F -#define IQM_AF_CMP_STATE__PRE 0x0 - -#define IQM_AF_CMP_STATE_STATE__B 0 -#define IQM_AF_CMP_STATE_STATE__W 2 -#define IQM_AF_CMP_STATE_STATE__M 0x3 -#define IQM_AF_CMP_STATE_STATE__PRE 0x0 - -#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2 -#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1 -#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4 -#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0 - -#define IQM_AF_CMP_STATE_FILTERGAIN__B 3 -#define IQM_AF_CMP_STATE_FILTERGAIN__W 2 -#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18 -#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10 -#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18 - -#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5 -#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1 -#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20 -#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0 - -#define IQM_AF_CMP_STATE_SEG64__B 6 -#define IQM_AF_CMP_STATE_SEG64__W 1 -#define IQM_AF_CMP_STATE_SEG64__M 0x40 -#define IQM_AF_CMP_STATE_SEG64__PRE 0x0 -#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0 -#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40 - - -#define IQM_AF_CMP_DC_OUT__A 0x187003C -#define IQM_AF_CMP_DC_OUT__W 12 -#define IQM_AF_CMP_DC_OUT__M 0xFFF -#define IQM_AF_CMP_DC_OUT__PRE 0x0 -#define IQM_AF_CMP_DC_IN__A 0x187003D -#define IQM_AF_CMP_DC_IN__W 13 -#define IQM_AF_CMP_DC_IN__M 0x1FFF -#define IQM_AF_CMP_DC_IN__PRE 0x0 - -#define IQM_AF_CMP_DC_IN_DC__B 0 -#define IQM_AF_CMP_DC_IN_DC__W 12 -#define IQM_AF_CMP_DC_IN_DC__M 0xFFF -#define IQM_AF_CMP_DC_IN_DC__PRE 0x0 -#define IQM_AF_CMP_DC_IN_DC_EN__B 12 -#define IQM_AF_CMP_DC_IN_DC_EN__W 1 -#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000 -#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0 -#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0 -#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000 - - -#define IQM_AF_CMP_AMP__A 0x187003E -#define IQM_AF_CMP_AMP__W 10 -#define IQM_AF_CMP_AMP__M 0x3FF -#define IQM_AF_CMP_AMP__PRE 0x0 -#define IQM_AF_CMP_DN_AVG__A 0x187003F -#define IQM_AF_CMP_DN_AVG__W 8 -#define IQM_AF_CMP_DN_AVG__M 0xFF -#define IQM_AF_CMP_DN_AVG__PRE 0x0 - -#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0 -#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8 -#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF -#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0 - - -#define IQM_AF_CMP_ACTIVE__A 0x1870040 -#define IQM_AF_CMP_ACTIVE__W 1 -#define IQM_AF_CMP_ACTIVE__M 0x1 -#define IQM_AF_CMP_ACTIVE__PRE 0x0 -#define IQM_AF_CMP_MEM0__A 0x1870080 -#define IQM_AF_CMP_MEM0__W 13 -#define IQM_AF_CMP_MEM0__M 0x1FFF -#define IQM_AF_CMP_MEM0__PRE 0x0 - -#define IQM_AF_CMP_MEM0_COEF__B 0 -#define IQM_AF_CMP_MEM0_COEF__W 13 -#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM0_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM1__A 0x1870081 -#define IQM_AF_CMP_MEM1__W 13 -#define IQM_AF_CMP_MEM1__M 0x1FFF -#define IQM_AF_CMP_MEM1__PRE 0x0 - -#define IQM_AF_CMP_MEM1_COEF__B 0 -#define IQM_AF_CMP_MEM1_COEF__W 13 -#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM1_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM2__A 0x1870082 -#define IQM_AF_CMP_MEM2__W 13 -#define IQM_AF_CMP_MEM2__M 0x1FFF -#define IQM_AF_CMP_MEM2__PRE 0x0 - -#define IQM_AF_CMP_MEM2_COEF__B 0 -#define IQM_AF_CMP_MEM2_COEF__W 13 -#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM2_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM3__A 0x1870083 -#define IQM_AF_CMP_MEM3__W 13 -#define IQM_AF_CMP_MEM3__M 0x1FFF -#define IQM_AF_CMP_MEM3__PRE 0x0 - -#define IQM_AF_CMP_MEM3_COEF__B 0 -#define IQM_AF_CMP_MEM3_COEF__W 13 -#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM3_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM4__A 0x1870084 -#define IQM_AF_CMP_MEM4__W 13 -#define IQM_AF_CMP_MEM4__M 0x1FFF -#define IQM_AF_CMP_MEM4__PRE 0x0 - -#define IQM_AF_CMP_MEM4_COEF__B 0 -#define IQM_AF_CMP_MEM4_COEF__W 13 -#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM4_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM5__A 0x1870085 -#define IQM_AF_CMP_MEM5__W 13 -#define IQM_AF_CMP_MEM5__M 0x1FFF -#define IQM_AF_CMP_MEM5__PRE 0x0 - -#define IQM_AF_CMP_MEM5_COEF__B 0 -#define IQM_AF_CMP_MEM5_COEF__W 13 -#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM5_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM6__A 0x1870086 -#define IQM_AF_CMP_MEM6__W 13 -#define IQM_AF_CMP_MEM6__M 0x1FFF -#define IQM_AF_CMP_MEM6__PRE 0x0 - -#define IQM_AF_CMP_MEM6_COEF__B 0 -#define IQM_AF_CMP_MEM6_COEF__W 13 -#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM6_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM7__A 0x1870087 -#define IQM_AF_CMP_MEM7__W 13 -#define IQM_AF_CMP_MEM7__M 0x1FFF -#define IQM_AF_CMP_MEM7__PRE 0x0 - -#define IQM_AF_CMP_MEM7_COEF__B 0 -#define IQM_AF_CMP_MEM7_COEF__W 13 -#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM7_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM8__A 0x1870088 -#define IQM_AF_CMP_MEM8__W 13 -#define IQM_AF_CMP_MEM8__M 0x1FFF -#define IQM_AF_CMP_MEM8__PRE 0x0 - -#define IQM_AF_CMP_MEM8_COEF__B 0 -#define IQM_AF_CMP_MEM8_COEF__W 13 -#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM8_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM9__A 0x1870089 -#define IQM_AF_CMP_MEM9__W 13 -#define IQM_AF_CMP_MEM9__M 0x1FFF -#define IQM_AF_CMP_MEM9__PRE 0x0 - -#define IQM_AF_CMP_MEM9_COEF__B 0 -#define IQM_AF_CMP_MEM9_COEF__W 13 -#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM9_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM10__A 0x187008A -#define IQM_AF_CMP_MEM10__W 13 -#define IQM_AF_CMP_MEM10__M 0x1FFF -#define IQM_AF_CMP_MEM10__PRE 0x0 - -#define IQM_AF_CMP_MEM10_COEF__B 0 -#define IQM_AF_CMP_MEM10_COEF__W 13 -#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM10_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM11__A 0x187008B -#define IQM_AF_CMP_MEM11__W 13 -#define IQM_AF_CMP_MEM11__M 0x1FFF -#define IQM_AF_CMP_MEM11__PRE 0x0 - -#define IQM_AF_CMP_MEM11_COEF__B 0 -#define IQM_AF_CMP_MEM11_COEF__W 13 -#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM11_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM12__A 0x187008C -#define IQM_AF_CMP_MEM12__W 13 -#define IQM_AF_CMP_MEM12__M 0x1FFF -#define IQM_AF_CMP_MEM12__PRE 0x0 - -#define IQM_AF_CMP_MEM12_COEF__B 0 -#define IQM_AF_CMP_MEM12_COEF__W 13 -#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM12_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM13__A 0x187008D -#define IQM_AF_CMP_MEM13__W 13 -#define IQM_AF_CMP_MEM13__M 0x1FFF -#define IQM_AF_CMP_MEM13__PRE 0x0 - -#define IQM_AF_CMP_MEM13_COEF__B 0 -#define IQM_AF_CMP_MEM13_COEF__W 13 -#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM13_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM14__A 0x187008E -#define IQM_AF_CMP_MEM14__W 13 -#define IQM_AF_CMP_MEM14__M 0x1FFF -#define IQM_AF_CMP_MEM14__PRE 0x0 - -#define IQM_AF_CMP_MEM14_COEF__B 0 -#define IQM_AF_CMP_MEM14_COEF__W 13 -#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM14_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM15__A 0x187008F -#define IQM_AF_CMP_MEM15__W 13 -#define IQM_AF_CMP_MEM15__M 0x1FFF -#define IQM_AF_CMP_MEM15__PRE 0x0 - -#define IQM_AF_CMP_MEM15_COEF__B 0 -#define IQM_AF_CMP_MEM15_COEF__W 13 -#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM15_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM16__A 0x1870090 -#define IQM_AF_CMP_MEM16__W 13 -#define IQM_AF_CMP_MEM16__M 0x1FFF -#define IQM_AF_CMP_MEM16__PRE 0x0 - -#define IQM_AF_CMP_MEM16_COEF__B 0 -#define IQM_AF_CMP_MEM16_COEF__W 13 -#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM16_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM17__A 0x1870091 -#define IQM_AF_CMP_MEM17__W 13 -#define IQM_AF_CMP_MEM17__M 0x1FFF -#define IQM_AF_CMP_MEM17__PRE 0x0 - -#define IQM_AF_CMP_MEM17_COEF__B 0 -#define IQM_AF_CMP_MEM17_COEF__W 13 -#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM17_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM18__A 0x1870092 -#define IQM_AF_CMP_MEM18__W 13 -#define IQM_AF_CMP_MEM18__M 0x1FFF -#define IQM_AF_CMP_MEM18__PRE 0x0 - -#define IQM_AF_CMP_MEM18_COEF__B 0 -#define IQM_AF_CMP_MEM18_COEF__W 13 -#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM18_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM19__A 0x1870093 -#define IQM_AF_CMP_MEM19__W 13 -#define IQM_AF_CMP_MEM19__M 0x1FFF -#define IQM_AF_CMP_MEM19__PRE 0x0 - -#define IQM_AF_CMP_MEM19_COEF__B 0 -#define IQM_AF_CMP_MEM19_COEF__W 13 -#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM19_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM20__A 0x1870094 -#define IQM_AF_CMP_MEM20__W 13 -#define IQM_AF_CMP_MEM20__M 0x1FFF -#define IQM_AF_CMP_MEM20__PRE 0x0 - -#define IQM_AF_CMP_MEM20_COEF__B 0 -#define IQM_AF_CMP_MEM20_COEF__W 13 -#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM20_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM21__A 0x1870095 -#define IQM_AF_CMP_MEM21__W 13 -#define IQM_AF_CMP_MEM21__M 0x1FFF -#define IQM_AF_CMP_MEM21__PRE 0x0 - -#define IQM_AF_CMP_MEM21_COEF__B 0 -#define IQM_AF_CMP_MEM21_COEF__W 13 -#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM21_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM22__A 0x1870096 -#define IQM_AF_CMP_MEM22__W 13 -#define IQM_AF_CMP_MEM22__M 0x1FFF -#define IQM_AF_CMP_MEM22__PRE 0x0 - -#define IQM_AF_CMP_MEM22_COEF__B 0 -#define IQM_AF_CMP_MEM22_COEF__W 13 -#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM22_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM23__A 0x1870097 -#define IQM_AF_CMP_MEM23__W 13 -#define IQM_AF_CMP_MEM23__M 0x1FFF -#define IQM_AF_CMP_MEM23__PRE 0x0 - -#define IQM_AF_CMP_MEM23_COEF__B 0 -#define IQM_AF_CMP_MEM23_COEF__W 13 -#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM23_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM24__A 0x1870098 -#define IQM_AF_CMP_MEM24__W 13 -#define IQM_AF_CMP_MEM24__M 0x1FFF -#define IQM_AF_CMP_MEM24__PRE 0x0 - -#define IQM_AF_CMP_MEM24_COEF__B 0 -#define IQM_AF_CMP_MEM24_COEF__W 13 -#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM24_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM25__A 0x1870099 -#define IQM_AF_CMP_MEM25__W 13 -#define IQM_AF_CMP_MEM25__M 0x1FFF -#define IQM_AF_CMP_MEM25__PRE 0x0 - -#define IQM_AF_CMP_MEM25_COEF__B 0 -#define IQM_AF_CMP_MEM25_COEF__W 13 -#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM25_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM26__A 0x187009A -#define IQM_AF_CMP_MEM26__W 13 -#define IQM_AF_CMP_MEM26__M 0x1FFF -#define IQM_AF_CMP_MEM26__PRE 0x0 - -#define IQM_AF_CMP_MEM26_COEF__B 0 -#define IQM_AF_CMP_MEM26_COEF__W 13 -#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM26_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM27__A 0x187009B -#define IQM_AF_CMP_MEM27__W 13 -#define IQM_AF_CMP_MEM27__M 0x1FFF -#define IQM_AF_CMP_MEM27__PRE 0x0 - -#define IQM_AF_CMP_MEM27_COEF__B 0 -#define IQM_AF_CMP_MEM27_COEF__W 13 -#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM27_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM28__A 0x187009C -#define IQM_AF_CMP_MEM28__W 13 -#define IQM_AF_CMP_MEM28__M 0x1FFF -#define IQM_AF_CMP_MEM28__PRE 0x0 - -#define IQM_AF_CMP_MEM28_COEF__B 0 -#define IQM_AF_CMP_MEM28_COEF__W 13 -#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM28_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM29__A 0x187009D -#define IQM_AF_CMP_MEM29__W 13 -#define IQM_AF_CMP_MEM29__M 0x1FFF -#define IQM_AF_CMP_MEM29__PRE 0x0 - -#define IQM_AF_CMP_MEM29_COEF__B 0 -#define IQM_AF_CMP_MEM29_COEF__W 13 -#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM29_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM30__A 0x187009E -#define IQM_AF_CMP_MEM30__W 13 -#define IQM_AF_CMP_MEM30__M 0x1FFF -#define IQM_AF_CMP_MEM30__PRE 0x0 - -#define IQM_AF_CMP_MEM30_COEF__B 0 -#define IQM_AF_CMP_MEM30_COEF__W 13 -#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM30_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM31__A 0x187009F -#define IQM_AF_CMP_MEM31__W 13 -#define IQM_AF_CMP_MEM31__M 0x1FFF -#define IQM_AF_CMP_MEM31__PRE 0x0 - -#define IQM_AF_CMP_MEM31_COEF__B 0 -#define IQM_AF_CMP_MEM31_COEF__W 13 -#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM31_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM32__A 0x18700A0 -#define IQM_AF_CMP_MEM32__W 13 -#define IQM_AF_CMP_MEM32__M 0x1FFF -#define IQM_AF_CMP_MEM32__PRE 0x0 - -#define IQM_AF_CMP_MEM32_COEF__B 0 -#define IQM_AF_CMP_MEM32_COEF__W 13 -#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM32_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM33__A 0x18700A1 -#define IQM_AF_CMP_MEM33__W 13 -#define IQM_AF_CMP_MEM33__M 0x1FFF -#define IQM_AF_CMP_MEM33__PRE 0x0 - -#define IQM_AF_CMP_MEM33_COEF__B 0 -#define IQM_AF_CMP_MEM33_COEF__W 13 -#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM33_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM34__A 0x18700A2 -#define IQM_AF_CMP_MEM34__W 13 -#define IQM_AF_CMP_MEM34__M 0x1FFF -#define IQM_AF_CMP_MEM34__PRE 0x0 - -#define IQM_AF_CMP_MEM34_COEF__B 0 -#define IQM_AF_CMP_MEM34_COEF__W 13 -#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM34_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM35__A 0x18700A3 -#define IQM_AF_CMP_MEM35__W 13 -#define IQM_AF_CMP_MEM35__M 0x1FFF -#define IQM_AF_CMP_MEM35__PRE 0x0 - -#define IQM_AF_CMP_MEM35_COEF__B 0 -#define IQM_AF_CMP_MEM35_COEF__W 13 -#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM35_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM36__A 0x18700A4 -#define IQM_AF_CMP_MEM36__W 13 -#define IQM_AF_CMP_MEM36__M 0x1FFF -#define IQM_AF_CMP_MEM36__PRE 0x0 - -#define IQM_AF_CMP_MEM36_COEF__B 0 -#define IQM_AF_CMP_MEM36_COEF__W 13 -#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM36_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM37__A 0x18700A5 -#define IQM_AF_CMP_MEM37__W 13 -#define IQM_AF_CMP_MEM37__M 0x1FFF -#define IQM_AF_CMP_MEM37__PRE 0x0 - -#define IQM_AF_CMP_MEM37_COEF__B 0 -#define IQM_AF_CMP_MEM37_COEF__W 13 -#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM37_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM38__A 0x18700A6 -#define IQM_AF_CMP_MEM38__W 13 -#define IQM_AF_CMP_MEM38__M 0x1FFF -#define IQM_AF_CMP_MEM38__PRE 0x0 - -#define IQM_AF_CMP_MEM38_COEF__B 0 -#define IQM_AF_CMP_MEM38_COEF__W 13 -#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM38_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM39__A 0x18700A7 -#define IQM_AF_CMP_MEM39__W 13 -#define IQM_AF_CMP_MEM39__M 0x1FFF -#define IQM_AF_CMP_MEM39__PRE 0x0 - -#define IQM_AF_CMP_MEM39_COEF__B 0 -#define IQM_AF_CMP_MEM39_COEF__W 13 -#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM39_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM40__A 0x18700A8 -#define IQM_AF_CMP_MEM40__W 13 -#define IQM_AF_CMP_MEM40__M 0x1FFF -#define IQM_AF_CMP_MEM40__PRE 0x0 - -#define IQM_AF_CMP_MEM40_COEF__B 0 -#define IQM_AF_CMP_MEM40_COEF__W 13 -#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM40_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM41__A 0x18700A9 -#define IQM_AF_CMP_MEM41__W 13 -#define IQM_AF_CMP_MEM41__M 0x1FFF -#define IQM_AF_CMP_MEM41__PRE 0x0 - -#define IQM_AF_CMP_MEM41_COEF__B 0 -#define IQM_AF_CMP_MEM41_COEF__W 13 -#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM41_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM42__A 0x18700AA -#define IQM_AF_CMP_MEM42__W 13 -#define IQM_AF_CMP_MEM42__M 0x1FFF -#define IQM_AF_CMP_MEM42__PRE 0x0 - -#define IQM_AF_CMP_MEM42_COEF__B 0 -#define IQM_AF_CMP_MEM42_COEF__W 13 -#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM42_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM43__A 0x18700AB -#define IQM_AF_CMP_MEM43__W 13 -#define IQM_AF_CMP_MEM43__M 0x1FFF -#define IQM_AF_CMP_MEM43__PRE 0x0 - -#define IQM_AF_CMP_MEM43_COEF__B 0 -#define IQM_AF_CMP_MEM43_COEF__W 13 -#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM43_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM44__A 0x18700AC -#define IQM_AF_CMP_MEM44__W 13 -#define IQM_AF_CMP_MEM44__M 0x1FFF -#define IQM_AF_CMP_MEM44__PRE 0x0 - -#define IQM_AF_CMP_MEM44_COEF__B 0 -#define IQM_AF_CMP_MEM44_COEF__W 13 -#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM44_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM45__A 0x18700AD -#define IQM_AF_CMP_MEM45__W 13 -#define IQM_AF_CMP_MEM45__M 0x1FFF -#define IQM_AF_CMP_MEM45__PRE 0x0 - -#define IQM_AF_CMP_MEM45_COEF__B 0 -#define IQM_AF_CMP_MEM45_COEF__W 13 -#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM45_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM46__A 0x18700AE -#define IQM_AF_CMP_MEM46__W 13 -#define IQM_AF_CMP_MEM46__M 0x1FFF -#define IQM_AF_CMP_MEM46__PRE 0x0 - -#define IQM_AF_CMP_MEM46_COEF__B 0 -#define IQM_AF_CMP_MEM46_COEF__W 13 -#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM46_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM47__A 0x18700AF -#define IQM_AF_CMP_MEM47__W 13 -#define IQM_AF_CMP_MEM47__M 0x1FFF -#define IQM_AF_CMP_MEM47__PRE 0x0 - -#define IQM_AF_CMP_MEM47_COEF__B 0 -#define IQM_AF_CMP_MEM47_COEF__W 13 -#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM47_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM48__A 0x18700B0 -#define IQM_AF_CMP_MEM48__W 13 -#define IQM_AF_CMP_MEM48__M 0x1FFF -#define IQM_AF_CMP_MEM48__PRE 0x0 - -#define IQM_AF_CMP_MEM48_COEF__B 0 -#define IQM_AF_CMP_MEM48_COEF__W 13 -#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM48_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM49__A 0x18700B1 -#define IQM_AF_CMP_MEM49__W 13 -#define IQM_AF_CMP_MEM49__M 0x1FFF -#define IQM_AF_CMP_MEM49__PRE 0x0 - -#define IQM_AF_CMP_MEM49_COEF__B 0 -#define IQM_AF_CMP_MEM49_COEF__W 13 -#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM49_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM50__A 0x18700B2 -#define IQM_AF_CMP_MEM50__W 13 -#define IQM_AF_CMP_MEM50__M 0x1FFF -#define IQM_AF_CMP_MEM50__PRE 0x0 - -#define IQM_AF_CMP_MEM50_COEF__B 0 -#define IQM_AF_CMP_MEM50_COEF__W 13 -#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM50_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM51__A 0x18700B3 -#define IQM_AF_CMP_MEM51__W 13 -#define IQM_AF_CMP_MEM51__M 0x1FFF -#define IQM_AF_CMP_MEM51__PRE 0x0 - -#define IQM_AF_CMP_MEM51_COEF__B 0 -#define IQM_AF_CMP_MEM51_COEF__W 13 -#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM51_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM52__A 0x18700B4 -#define IQM_AF_CMP_MEM52__W 13 -#define IQM_AF_CMP_MEM52__M 0x1FFF -#define IQM_AF_CMP_MEM52__PRE 0x0 - -#define IQM_AF_CMP_MEM52_COEF__B 0 -#define IQM_AF_CMP_MEM52_COEF__W 13 -#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM52_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM53__A 0x18700B5 -#define IQM_AF_CMP_MEM53__W 13 -#define IQM_AF_CMP_MEM53__M 0x1FFF -#define IQM_AF_CMP_MEM53__PRE 0x0 - -#define IQM_AF_CMP_MEM53_COEF__B 0 -#define IQM_AF_CMP_MEM53_COEF__W 13 -#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM53_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM54__A 0x18700B6 -#define IQM_AF_CMP_MEM54__W 13 -#define IQM_AF_CMP_MEM54__M 0x1FFF -#define IQM_AF_CMP_MEM54__PRE 0x0 - -#define IQM_AF_CMP_MEM54_COEF__B 0 -#define IQM_AF_CMP_MEM54_COEF__W 13 -#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM54_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM55__A 0x18700B7 -#define IQM_AF_CMP_MEM55__W 13 -#define IQM_AF_CMP_MEM55__M 0x1FFF -#define IQM_AF_CMP_MEM55__PRE 0x0 - -#define IQM_AF_CMP_MEM55_COEF__B 0 -#define IQM_AF_CMP_MEM55_COEF__W 13 -#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM55_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM56__A 0x18700B8 -#define IQM_AF_CMP_MEM56__W 13 -#define IQM_AF_CMP_MEM56__M 0x1FFF -#define IQM_AF_CMP_MEM56__PRE 0x0 - -#define IQM_AF_CMP_MEM56_COEF__B 0 -#define IQM_AF_CMP_MEM56_COEF__W 13 -#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM56_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM57__A 0x18700B9 -#define IQM_AF_CMP_MEM57__W 13 -#define IQM_AF_CMP_MEM57__M 0x1FFF -#define IQM_AF_CMP_MEM57__PRE 0x0 - -#define IQM_AF_CMP_MEM57_COEF__B 0 -#define IQM_AF_CMP_MEM57_COEF__W 13 -#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM57_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM58__A 0x18700BA -#define IQM_AF_CMP_MEM58__W 13 -#define IQM_AF_CMP_MEM58__M 0x1FFF -#define IQM_AF_CMP_MEM58__PRE 0x0 - -#define IQM_AF_CMP_MEM58_COEF__B 0 -#define IQM_AF_CMP_MEM58_COEF__W 13 -#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM58_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM59__A 0x18700BB -#define IQM_AF_CMP_MEM59__W 13 -#define IQM_AF_CMP_MEM59__M 0x1FFF -#define IQM_AF_CMP_MEM59__PRE 0x0 - -#define IQM_AF_CMP_MEM59_COEF__B 0 -#define IQM_AF_CMP_MEM59_COEF__W 13 -#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM59_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM60__A 0x18700BC -#define IQM_AF_CMP_MEM60__W 13 -#define IQM_AF_CMP_MEM60__M 0x1FFF -#define IQM_AF_CMP_MEM60__PRE 0x0 - -#define IQM_AF_CMP_MEM60_COEF__B 0 -#define IQM_AF_CMP_MEM60_COEF__W 13 -#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM60_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM61__A 0x18700BD -#define IQM_AF_CMP_MEM61__W 13 -#define IQM_AF_CMP_MEM61__M 0x1FFF -#define IQM_AF_CMP_MEM61__PRE 0x0 - -#define IQM_AF_CMP_MEM61_COEF__B 0 -#define IQM_AF_CMP_MEM61_COEF__W 13 -#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM61_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM62__A 0x18700BE -#define IQM_AF_CMP_MEM62__W 13 -#define IQM_AF_CMP_MEM62__M 0x1FFF -#define IQM_AF_CMP_MEM62__PRE 0x0 - -#define IQM_AF_CMP_MEM62_COEF__B 0 -#define IQM_AF_CMP_MEM62_COEF__W 13 -#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM62_COEF__PRE 0x0 - -#define IQM_AF_CMP_MEM63__A 0x18700BF -#define IQM_AF_CMP_MEM63__W 13 -#define IQM_AF_CMP_MEM63__M 0x1FFF -#define IQM_AF_CMP_MEM63__PRE 0x0 - -#define IQM_AF_CMP_MEM63_COEF__B 0 -#define IQM_AF_CMP_MEM63_COEF__W 13 -#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF -#define IQM_AF_CMP_MEM63_COEF__PRE 0x0 - - - -#define IQM_RT_RAM__A 0x1880000 - -#define IQM_RT_RAM_DLY__B 0 -#define IQM_RT_RAM_DLY__W 13 -#define IQM_RT_RAM_DLY__M 0x1FFF -#define IQM_RT_RAM_DLY__PRE 0x0 - - - - - -#define OFDM_CE_COMM_EXEC__A 0x2C00000 -#define OFDM_CE_COMM_EXEC__W 3 -#define OFDM_CE_COMM_EXEC__M 0x7 -#define OFDM_CE_COMM_EXEC__PRE 0x0 -#define OFDM_CE_COMM_EXEC_STOP 0x0 -#define OFDM_CE_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CE_COMM_EXEC_HOLD 0x2 -#define OFDM_CE_COMM_EXEC_STEP 0x3 -#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_CE_COMM_STATE__A 0x2C00001 -#define OFDM_CE_COMM_STATE__W 16 -#define OFDM_CE_COMM_STATE__M 0xFFFF -#define OFDM_CE_COMM_STATE__PRE 0x0 -#define OFDM_CE_COMM_MB__A 0x2C00002 -#define OFDM_CE_COMM_MB__W 16 -#define OFDM_CE_COMM_MB__M 0xFFFF -#define OFDM_CE_COMM_MB__PRE 0x0 -#define OFDM_CE_COMM_INT_REQ__A 0x2C00004 -#define OFDM_CE_COMM_INT_REQ__W 16 -#define OFDM_CE_COMM_INT_REQ__M 0xFFFF -#define OFDM_CE_COMM_INT_REQ__PRE 0x0 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4 -#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0 - -#define OFDM_CE_COMM_INT_STA__A 0x2C00005 -#define OFDM_CE_COMM_INT_STA__W 16 -#define OFDM_CE_COMM_INT_STA__M 0xFFFF -#define OFDM_CE_COMM_INT_STA__PRE 0x0 -#define OFDM_CE_COMM_INT_MSK__A 0x2C00006 -#define OFDM_CE_COMM_INT_MSK__W 16 -#define OFDM_CE_COMM_INT_MSK__M 0xFFFF -#define OFDM_CE_COMM_INT_MSK__PRE 0x0 -#define OFDM_CE_COMM_INT_STM__A 0x2C00007 -#define OFDM_CE_COMM_INT_STM__W 16 -#define OFDM_CE_COMM_INT_STM__M 0xFFFF -#define OFDM_CE_COMM_INT_STM__PRE 0x0 -#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000 -#define OFDM_CE_TOP_COMM_EXEC__W 3 -#define OFDM_CE_TOP_COMM_EXEC__M 0x7 -#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_CE_TOP_COMM_MB__A 0x2C10002 -#define OFDM_CE_TOP_COMM_MB__W 4 -#define OFDM_CE_TOP_COMM_MB__M 0xF -#define OFDM_CE_TOP_COMM_MB__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_CTL__B 0 -#define OFDM_CE_TOP_COMM_MB_CTL__W 1 -#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_CE_TOP_COMM_MB_OBS__B 1 -#define OFDM_CE_TOP_COMM_MB_OBS__W 1 -#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC -#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8 -#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC - -#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004 -#define OFDM_CE_TOP_COMM_INT_REQ__W 1 -#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1 -#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005 -#define OFDM_CE_TOP_COMM_INT_STA__W 3 -#define OFDM_CE_TOP_COMM_INT_STA__M 0x7 -#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2 -#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4 -#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0 - -#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006 -#define OFDM_CE_TOP_COMM_INT_MSK__W 3 -#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7 -#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4 -#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0 - -#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007 -#define OFDM_CE_TOP_COMM_INT_STM__W 3 -#define OFDM_CE_TOP_COMM_INT_STM__M 0x7 -#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2 -#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4 -#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0 - - -#define OFDM_CE_TOP_MODE_2K__A 0x2C10010 -#define OFDM_CE_TOP_MODE_2K__W 1 -#define OFDM_CE_TOP_MODE_2K__M 0x1 -#define OFDM_CE_TOP_MODE_2K__PRE 0x0 - -#define OFDM_CE_TOP_TAPSET__A 0x2C10011 -#define OFDM_CE_TOP_TAPSET__W 4 -#define OFDM_CE_TOP_TAPSET__M 0xF -#define OFDM_CE_TOP_TAPSET__PRE 0x1 -#define OFDM_CE_TOP_AVG_POW__A 0x2C10012 -#define OFDM_CE_TOP_AVG_POW__W 8 -#define OFDM_CE_TOP_AVG_POW__M 0xFF -#define OFDM_CE_TOP_AVG_POW__PRE 0x65 -#define OFDM_CE_TOP_MAX_POW__A 0x2C10013 -#define OFDM_CE_TOP_MAX_POW__W 8 -#define OFDM_CE_TOP_MAX_POW__M 0xFF -#define OFDM_CE_TOP_MAX_POW__PRE 0x80 -#define OFDM_CE_TOP_ATT__A 0x2C10014 -#define OFDM_CE_TOP_ATT__W 8 -#define OFDM_CE_TOP_ATT__M 0xFF -#define OFDM_CE_TOP_ATT__PRE 0x70 -#define OFDM_CE_TOP_NRED__A 0x2C10015 -#define OFDM_CE_TOP_NRED__W 6 -#define OFDM_CE_TOP_NRED__M 0x3F -#define OFDM_CE_TOP_NRED__PRE 0x9 - -#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020 -#define OFDM_CE_TOP_PU_SIGN__W 1 -#define OFDM_CE_TOP_PU_SIGN__M 0x1 -#define OFDM_CE_TOP_PU_SIGN__PRE 0x0 - -#define OFDM_CE_TOP_PU_MIX__A 0x2C10021 -#define OFDM_CE_TOP_PU_MIX__W 1 -#define OFDM_CE_TOP_PU_MIX__M 0x1 -#define OFDM_CE_TOP_PU_MIX__PRE 0x0 -#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030 -#define OFDM_CE_TOP_PB_PILOT_REQ__W 15 -#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF -#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 -#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0 -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0 -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12 -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF -#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0 - - -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031 -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1 -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1 -#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0 - -#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032 -#define OFDM_CE_TOP_PB_FREEZE__W 1 -#define OFDM_CE_TOP_PB_FREEZE__M 0x1 -#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0 - -#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038 -#define OFDM_CE_TOP_PB_PILOT_EXP__W 4 -#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF -#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0 - -#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039 -#define OFDM_CE_TOP_PB_PILOT_REAL__W 10 -#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF -#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0 - -#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A -#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10 -#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF -#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0 - -#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B -#define OFDM_CE_TOP_PB_SMBNR__W 5 -#define OFDM_CE_TOP_PB_SMBNR__M 0x1F -#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0 - -#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040 -#define OFDM_CE_TOP_NE_PILOT_REQ__W 12 -#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF -#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 -#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0 - - -#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042 -#define OFDM_CE_TOP_NE_PILOT_DATA__W 10 -#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF -#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0 -#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043 -#define OFDM_CE_TOP_NE_ERR_SELECT__W 5 -#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F -#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7 - -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4 -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10 -#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0 - -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3 -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8 -#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0 - -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2 -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4 -#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4 - -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2 -#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2 - -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0 -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1 -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1 -#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1 - - -#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044 -#define OFDM_CE_TOP_NE_TD_CAL__W 9 -#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF -#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8 - -#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045 -#define OFDM_CE_TOP_NE_FD_CAL__W 9 -#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF -#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9 - -#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046 -#define OFDM_CE_TOP_NE_MIXAVG__W 3 -#define OFDM_CE_TOP_NE_MIXAVG__M 0x7 -#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6 - -#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047 -#define OFDM_CE_TOP_NE_NUPD_OFS__W 4 -#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF -#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4 -#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048 -#define OFDM_CE_TOP_NE_TD_POW__W 15 -#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF -#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0 - -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10 -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5 -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0 -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10 -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049 -#define OFDM_CE_TOP_NE_FD_POW__W 15 -#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF -#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0 - -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10 -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5 -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0 -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10 -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0 - - -#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A -#define OFDM_CE_TOP_NE_NEXP_AVG__W 8 -#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF -#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0 - -#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B -#define OFDM_CE_TOP_NE_OFFSET__W 9 -#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF -#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0 - -#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C -#define OFDM_CE_TOP_NE_NUPD_TRH__W 5 -#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F -#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14 - -#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050 -#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8 -#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF -#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0 - -#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051 -#define OFDM_CE_TOP_PE_TIMESHIFT__W 14 -#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF -#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052 -#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16 -#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053 -#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16 -#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054 -#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16 -#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055 -#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16 -#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF -#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056 -#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16 -#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057 -#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16 -#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058 -#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16 -#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059 -#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16 -#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF -#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A -#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5 -#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F -#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0 - -#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B -#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5 -#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F -#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0 - -#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060 -#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1 -#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1 -#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0 - -#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061 -#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1 -#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1 -#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064 -#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10 -#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF -#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100 - -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065 -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1 -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1 -#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066 -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5 -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F -#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE - -#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067 -#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10 -#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF -#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068 -#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10 -#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF -#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069 -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1 -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1 -#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5 -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F -#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA - -#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B -#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10 -#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF -#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0 -#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C -#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15 -#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0 - -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10 -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF -#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0 - - -#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072 -#define OFDM_CE_TOP_TI_SYM_CNT__W 6 -#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F -#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20 - -#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073 -#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1 -#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1 -#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1 - -#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074 -#define OFDM_CE_TOP_TI_SHIFT__W 2 -#define OFDM_CE_TOP_TI_SHIFT__M 0x3 -#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0 - -#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075 -#define OFDM_CE_TOP_TI_SLOW__W 1 -#define OFDM_CE_TOP_TI_SLOW__M 0x1 -#define OFDM_CE_TOP_TI_SLOW__PRE 0x1 - -#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076 -#define OFDM_CE_TOP_TI_MGAIN__W 8 -#define OFDM_CE_TOP_TI_MGAIN__M 0xFF -#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0 - -#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077 -#define OFDM_CE_TOP_TI_ACCU1__W 8 -#define OFDM_CE_TOP_TI_ACCU1__M 0xFF -#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0 - -#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0 -#define OFDM_CE_TOP_NI_PER_LEFT__W 5 -#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F -#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE - -#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1 -#define OFDM_CE_TOP_NI_PER_RIGHT__W 5 -#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F -#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7 - -#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2 -#define OFDM_CE_TOP_NI_POS_LR__W 9 -#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF -#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0 - -#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090 -#define OFDM_CE_TOP_FI_SHT_INCR__W 9 -#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF -#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E - -#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091 -#define OFDM_CE_TOP_FI_EXP_NORM__W 4 -#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF -#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC - -#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092 -#define OFDM_CE_TOP_FI_SUPR_VAL__W 1 -#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1 -#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0 - -#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0 -#define OFDM_CE_TOP_IR_INPUTSEL__W 1 -#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1 -#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0 - -#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1 -#define OFDM_CE_TOP_IR_STARTPOS__W 8 -#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF -#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0 - -#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2 -#define OFDM_CE_TOP_IR_NEXP_THRES__W 8 -#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF -#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF - -#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3 -#define OFDM_CE_TOP_IR_LENGTH__W 4 -#define OFDM_CE_TOP_IR_LENGTH__M 0xF -#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9 - -#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4 -#define OFDM_CE_TOP_IR_FREQ__W 11 -#define OFDM_CE_TOP_IR_FREQ__M 0x7FF -#define OFDM_CE_TOP_IR_FREQ__PRE 0x0 - -#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5 -#define OFDM_CE_TOP_IR_FREQINC__W 11 -#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF -#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4 - -#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6 -#define OFDM_CE_TOP_IR_KAISINC__W 15 -#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF -#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100 - -#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7 -#define OFDM_CE_TOP_IR_CTL__W 3 -#define OFDM_CE_TOP_IR_CTL__M 0x7 -#define OFDM_CE_TOP_IR_CTL__PRE 0x0 - -#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8 -#define OFDM_CE_TOP_IR_REAL__W 16 -#define OFDM_CE_TOP_IR_REAL__M 0xFFFF -#define OFDM_CE_TOP_IR_REAL__PRE 0x0 - -#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9 -#define OFDM_CE_TOP_IR_IMAG__W 16 -#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF -#define OFDM_CE_TOP_IR_IMAG__PRE 0x0 - -#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA -#define OFDM_CE_TOP_IR_INDEX__W 12 -#define OFDM_CE_TOP_IR_INDEX__M 0xFFF -#define OFDM_CE_TOP_IR_INDEX__PRE 0x0 - - - -#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000 -#define OFDM_CE_FR_COMM_EXEC__W 3 -#define OFDM_CE_FR_COMM_EXEC__M 0x7 -#define OFDM_CE_FR_COMM_EXEC__PRE 0x0 -#define OFDM_CE_FR_COMM_EXEC_STOP 0x0 -#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2 -#define OFDM_CE_FR_COMM_EXEC_STEP 0x3 - - -#define OFDM_CE_FR_TREAL00__A 0x2C20010 -#define OFDM_CE_FR_TREAL00__W 11 -#define OFDM_CE_FR_TREAL00__M 0x7FF -#define OFDM_CE_FR_TREAL00__PRE 0x52 - -#define OFDM_CE_FR_TIMAG00__A 0x2C20011 -#define OFDM_CE_FR_TIMAG00__W 11 -#define OFDM_CE_FR_TIMAG00__M 0x7FF -#define OFDM_CE_FR_TIMAG00__PRE 0x0 - -#define OFDM_CE_FR_TREAL01__A 0x2C20012 -#define OFDM_CE_FR_TREAL01__W 11 -#define OFDM_CE_FR_TREAL01__M 0x7FF -#define OFDM_CE_FR_TREAL01__PRE 0x52 - -#define OFDM_CE_FR_TIMAG01__A 0x2C20013 -#define OFDM_CE_FR_TIMAG01__W 11 -#define OFDM_CE_FR_TIMAG01__M 0x7FF -#define OFDM_CE_FR_TIMAG01__PRE 0x0 - -#define OFDM_CE_FR_TREAL02__A 0x2C20014 -#define OFDM_CE_FR_TREAL02__W 11 -#define OFDM_CE_FR_TREAL02__M 0x7FF -#define OFDM_CE_FR_TREAL02__PRE 0x52 - -#define OFDM_CE_FR_TIMAG02__A 0x2C20015 -#define OFDM_CE_FR_TIMAG02__W 11 -#define OFDM_CE_FR_TIMAG02__M 0x7FF -#define OFDM_CE_FR_TIMAG02__PRE 0x0 - -#define OFDM_CE_FR_TREAL03__A 0x2C20016 -#define OFDM_CE_FR_TREAL03__W 11 -#define OFDM_CE_FR_TREAL03__M 0x7FF -#define OFDM_CE_FR_TREAL03__PRE 0x52 - -#define OFDM_CE_FR_TIMAG03__A 0x2C20017 -#define OFDM_CE_FR_TIMAG03__W 11 -#define OFDM_CE_FR_TIMAG03__M 0x7FF -#define OFDM_CE_FR_TIMAG03__PRE 0x0 - -#define OFDM_CE_FR_TREAL04__A 0x2C20018 -#define OFDM_CE_FR_TREAL04__W 11 -#define OFDM_CE_FR_TREAL04__M 0x7FF -#define OFDM_CE_FR_TREAL04__PRE 0x52 - -#define OFDM_CE_FR_TIMAG04__A 0x2C20019 -#define OFDM_CE_FR_TIMAG04__W 11 -#define OFDM_CE_FR_TIMAG04__M 0x7FF -#define OFDM_CE_FR_TIMAG04__PRE 0x0 - -#define OFDM_CE_FR_TREAL05__A 0x2C2001A -#define OFDM_CE_FR_TREAL05__W 11 -#define OFDM_CE_FR_TREAL05__M 0x7FF -#define OFDM_CE_FR_TREAL05__PRE 0x52 - -#define OFDM_CE_FR_TIMAG05__A 0x2C2001B -#define OFDM_CE_FR_TIMAG05__W 11 -#define OFDM_CE_FR_TIMAG05__M 0x7FF -#define OFDM_CE_FR_TIMAG05__PRE 0x0 - -#define OFDM_CE_FR_TREAL06__A 0x2C2001C -#define OFDM_CE_FR_TREAL06__W 11 -#define OFDM_CE_FR_TREAL06__M 0x7FF -#define OFDM_CE_FR_TREAL06__PRE 0x52 - -#define OFDM_CE_FR_TIMAG06__A 0x2C2001D -#define OFDM_CE_FR_TIMAG06__W 11 -#define OFDM_CE_FR_TIMAG06__M 0x7FF -#define OFDM_CE_FR_TIMAG06__PRE 0x0 - -#define OFDM_CE_FR_TREAL07__A 0x2C2001E -#define OFDM_CE_FR_TREAL07__W 11 -#define OFDM_CE_FR_TREAL07__M 0x7FF -#define OFDM_CE_FR_TREAL07__PRE 0x52 - -#define OFDM_CE_FR_TIMAG07__A 0x2C2001F -#define OFDM_CE_FR_TIMAG07__W 11 -#define OFDM_CE_FR_TIMAG07__M 0x7FF -#define OFDM_CE_FR_TIMAG07__PRE 0x0 - -#define OFDM_CE_FR_TREAL08__A 0x2C20020 -#define OFDM_CE_FR_TREAL08__W 11 -#define OFDM_CE_FR_TREAL08__M 0x7FF -#define OFDM_CE_FR_TREAL08__PRE 0x52 - -#define OFDM_CE_FR_TIMAG08__A 0x2C20021 -#define OFDM_CE_FR_TIMAG08__W 11 -#define OFDM_CE_FR_TIMAG08__M 0x7FF -#define OFDM_CE_FR_TIMAG08__PRE 0x0 - -#define OFDM_CE_FR_TREAL09__A 0x2C20022 -#define OFDM_CE_FR_TREAL09__W 11 -#define OFDM_CE_FR_TREAL09__M 0x7FF -#define OFDM_CE_FR_TREAL09__PRE 0x52 - -#define OFDM_CE_FR_TIMAG09__A 0x2C20023 -#define OFDM_CE_FR_TIMAG09__W 11 -#define OFDM_CE_FR_TIMAG09__M 0x7FF -#define OFDM_CE_FR_TIMAG09__PRE 0x0 - -#define OFDM_CE_FR_TREAL10__A 0x2C20024 -#define OFDM_CE_FR_TREAL10__W 11 -#define OFDM_CE_FR_TREAL10__M 0x7FF -#define OFDM_CE_FR_TREAL10__PRE 0x52 - -#define OFDM_CE_FR_TIMAG10__A 0x2C20025 -#define OFDM_CE_FR_TIMAG10__W 11 -#define OFDM_CE_FR_TIMAG10__M 0x7FF -#define OFDM_CE_FR_TIMAG10__PRE 0x0 - -#define OFDM_CE_FR_TREAL11__A 0x2C20026 -#define OFDM_CE_FR_TREAL11__W 11 -#define OFDM_CE_FR_TREAL11__M 0x7FF -#define OFDM_CE_FR_TREAL11__PRE 0x52 - -#define OFDM_CE_FR_TIMAG11__A 0x2C20027 -#define OFDM_CE_FR_TIMAG11__W 11 -#define OFDM_CE_FR_TIMAG11__M 0x7FF -#define OFDM_CE_FR_TIMAG11__PRE 0x0 - -#define OFDM_CE_FR_MID_TAP__A 0x2C20028 -#define OFDM_CE_FR_MID_TAP__W 11 -#define OFDM_CE_FR_MID_TAP__M 0x7FF -#define OFDM_CE_FR_MID_TAP__PRE 0x51 - -#define OFDM_CE_FR_SQS_G00__A 0x2C20029 -#define OFDM_CE_FR_SQS_G00__W 8 -#define OFDM_CE_FR_SQS_G00__M 0xFF -#define OFDM_CE_FR_SQS_G00__PRE 0xB - -#define OFDM_CE_FR_SQS_G01__A 0x2C2002A -#define OFDM_CE_FR_SQS_G01__W 8 -#define OFDM_CE_FR_SQS_G01__M 0xFF -#define OFDM_CE_FR_SQS_G01__PRE 0xB - -#define OFDM_CE_FR_SQS_G02__A 0x2C2002B -#define OFDM_CE_FR_SQS_G02__W 8 -#define OFDM_CE_FR_SQS_G02__M 0xFF -#define OFDM_CE_FR_SQS_G02__PRE 0xB - -#define OFDM_CE_FR_SQS_G03__A 0x2C2002C -#define OFDM_CE_FR_SQS_G03__W 8 -#define OFDM_CE_FR_SQS_G03__M 0xFF -#define OFDM_CE_FR_SQS_G03__PRE 0xB - -#define OFDM_CE_FR_SQS_G04__A 0x2C2002D -#define OFDM_CE_FR_SQS_G04__W 8 -#define OFDM_CE_FR_SQS_G04__M 0xFF -#define OFDM_CE_FR_SQS_G04__PRE 0xB - -#define OFDM_CE_FR_SQS_G05__A 0x2C2002E -#define OFDM_CE_FR_SQS_G05__W 8 -#define OFDM_CE_FR_SQS_G05__M 0xFF -#define OFDM_CE_FR_SQS_G05__PRE 0xB - -#define OFDM_CE_FR_SQS_G06__A 0x2C2002F -#define OFDM_CE_FR_SQS_G06__W 8 -#define OFDM_CE_FR_SQS_G06__M 0xFF -#define OFDM_CE_FR_SQS_G06__PRE 0xB - -#define OFDM_CE_FR_SQS_G07__A 0x2C20030 -#define OFDM_CE_FR_SQS_G07__W 8 -#define OFDM_CE_FR_SQS_G07__M 0xFF -#define OFDM_CE_FR_SQS_G07__PRE 0xB - -#define OFDM_CE_FR_SQS_G08__A 0x2C20031 -#define OFDM_CE_FR_SQS_G08__W 8 -#define OFDM_CE_FR_SQS_G08__M 0xFF -#define OFDM_CE_FR_SQS_G08__PRE 0xB - -#define OFDM_CE_FR_SQS_G09__A 0x2C20032 -#define OFDM_CE_FR_SQS_G09__W 8 -#define OFDM_CE_FR_SQS_G09__M 0xFF -#define OFDM_CE_FR_SQS_G09__PRE 0xB - -#define OFDM_CE_FR_SQS_G10__A 0x2C20033 -#define OFDM_CE_FR_SQS_G10__W 8 -#define OFDM_CE_FR_SQS_G10__M 0xFF -#define OFDM_CE_FR_SQS_G10__PRE 0xB - -#define OFDM_CE_FR_SQS_G11__A 0x2C20034 -#define OFDM_CE_FR_SQS_G11__W 8 -#define OFDM_CE_FR_SQS_G11__M 0xFF -#define OFDM_CE_FR_SQS_G11__PRE 0xB - -#define OFDM_CE_FR_SQS_G12__A 0x2C20035 -#define OFDM_CE_FR_SQS_G12__W 8 -#define OFDM_CE_FR_SQS_G12__M 0xFF -#define OFDM_CE_FR_SQS_G12__PRE 0x5 - -#define OFDM_CE_FR_RIO_G00__A 0x2C20036 -#define OFDM_CE_FR_RIO_G00__W 9 -#define OFDM_CE_FR_RIO_G00__M 0x1FF -#define OFDM_CE_FR_RIO_G00__PRE 0x1FF - -#define OFDM_CE_FR_RIO_G01__A 0x2C20037 -#define OFDM_CE_FR_RIO_G01__W 9 -#define OFDM_CE_FR_RIO_G01__M 0x1FF -#define OFDM_CE_FR_RIO_G01__PRE 0x190 - -#define OFDM_CE_FR_RIO_G02__A 0x2C20038 -#define OFDM_CE_FR_RIO_G02__W 9 -#define OFDM_CE_FR_RIO_G02__M 0x1FF -#define OFDM_CE_FR_RIO_G02__PRE 0x10B - -#define OFDM_CE_FR_RIO_G03__A 0x2C20039 -#define OFDM_CE_FR_RIO_G03__W 9 -#define OFDM_CE_FR_RIO_G03__M 0x1FF -#define OFDM_CE_FR_RIO_G03__PRE 0xC8 - -#define OFDM_CE_FR_RIO_G04__A 0x2C2003A -#define OFDM_CE_FR_RIO_G04__W 9 -#define OFDM_CE_FR_RIO_G04__M 0x1FF -#define OFDM_CE_FR_RIO_G04__PRE 0xA0 - -#define OFDM_CE_FR_RIO_G05__A 0x2C2003B -#define OFDM_CE_FR_RIO_G05__W 9 -#define OFDM_CE_FR_RIO_G05__M 0x1FF -#define OFDM_CE_FR_RIO_G05__PRE 0x85 - -#define OFDM_CE_FR_RIO_G06__A 0x2C2003C -#define OFDM_CE_FR_RIO_G06__W 9 -#define OFDM_CE_FR_RIO_G06__M 0x1FF -#define OFDM_CE_FR_RIO_G06__PRE 0x72 - -#define OFDM_CE_FR_RIO_G07__A 0x2C2003D -#define OFDM_CE_FR_RIO_G07__W 9 -#define OFDM_CE_FR_RIO_G07__M 0x1FF -#define OFDM_CE_FR_RIO_G07__PRE 0x64 - -#define OFDM_CE_FR_RIO_G08__A 0x2C2003E -#define OFDM_CE_FR_RIO_G08__W 9 -#define OFDM_CE_FR_RIO_G08__M 0x1FF -#define OFDM_CE_FR_RIO_G08__PRE 0x59 - -#define OFDM_CE_FR_RIO_G09__A 0x2C2003F -#define OFDM_CE_FR_RIO_G09__W 9 -#define OFDM_CE_FR_RIO_G09__M 0x1FF -#define OFDM_CE_FR_RIO_G09__PRE 0x50 - -#define OFDM_CE_FR_RIO_G10__A 0x2C20040 -#define OFDM_CE_FR_RIO_G10__W 9 -#define OFDM_CE_FR_RIO_G10__M 0x1FF -#define OFDM_CE_FR_RIO_G10__PRE 0x49 -#define OFDM_CE_FR_MODE__A 0x2C20041 -#define OFDM_CE_FR_MODE__W 9 -#define OFDM_CE_FR_MODE__M 0x1FF -#define OFDM_CE_FR_MODE__PRE 0xDE - -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0 -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1 -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1 -#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0 - -#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1 -#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1 -#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2 -#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2 - -#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2 -#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1 -#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4 -#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4 - -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3 -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1 -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8 -#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8 - -#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4 -#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1 -#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10 -#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10 - -#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5 -#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1 -#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20 -#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0 - -#define OFDM_CE_FR_MODE_MID_MODE__B 6 -#define OFDM_CE_FR_MODE_MID_MODE__W 1 -#define OFDM_CE_FR_MODE_MID_MODE__M 0x40 -#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40 - -#define OFDM_CE_FR_MODE_NOISE_MODE__B 7 -#define OFDM_CE_FR_MODE_NOISE_MODE__W 1 -#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80 -#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80 - -#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8 -#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1 -#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100 -#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0 - - -#define OFDM_CE_FR_SQS_TRH__A 0x2C20042 -#define OFDM_CE_FR_SQS_TRH__W 8 -#define OFDM_CE_FR_SQS_TRH__M 0xFF -#define OFDM_CE_FR_SQS_TRH__PRE 0x80 - -#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043 -#define OFDM_CE_FR_RIO_GAIN__W 3 -#define OFDM_CE_FR_RIO_GAIN__M 0x7 -#define OFDM_CE_FR_RIO_GAIN__PRE 0x7 -#define OFDM_CE_FR_BYPASS__A 0x2C20044 -#define OFDM_CE_FR_BYPASS__W 10 -#define OFDM_CE_FR_BYPASS__M 0x3FF -#define OFDM_CE_FR_BYPASS__PRE 0x13B - -#define OFDM_CE_FR_BYPASS_RUN_IN__B 0 -#define OFDM_CE_FR_BYPASS_RUN_IN__W 4 -#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF -#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB - -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4 -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5 -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 -#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130 - -#define OFDM_CE_FR_BYPASS_TOTAL__B 9 -#define OFDM_CE_FR_BYPASS_TOTAL__W 1 -#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200 -#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0 - - -#define OFDM_CE_FR_PM_SET__A 0x2C20045 -#define OFDM_CE_FR_PM_SET__W 4 -#define OFDM_CE_FR_PM_SET__M 0xF -#define OFDM_CE_FR_PM_SET__PRE 0xD - -#define OFDM_CE_FR_ERR_SH__A 0x2C20046 -#define OFDM_CE_FR_ERR_SH__W 4 -#define OFDM_CE_FR_ERR_SH__M 0xF -#define OFDM_CE_FR_ERR_SH__PRE 0x4 - -#define OFDM_CE_FR_MAN_SH__A 0x2C20047 -#define OFDM_CE_FR_MAN_SH__W 4 -#define OFDM_CE_FR_MAN_SH__M 0xF -#define OFDM_CE_FR_MAN_SH__PRE 0x7 - -#define OFDM_CE_FR_TAP_SH__A 0x2C20048 -#define OFDM_CE_FR_TAP_SH__W 3 -#define OFDM_CE_FR_TAP_SH__M 0x7 -#define OFDM_CE_FR_TAP_SH__PRE 0x3 - -#define OFDM_CE_FR_CLIP__A 0x2C20049 -#define OFDM_CE_FR_CLIP__W 9 -#define OFDM_CE_FR_CLIP__M 0x1FF -#define OFDM_CE_FR_CLIP__PRE 0x49 - -#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A -#define OFDM_CE_FR_LEAK_UPD__W 3 -#define OFDM_CE_FR_LEAK_UPD__M 0x7 -#define OFDM_CE_FR_LEAK_UPD__PRE 0x0 - -#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B -#define OFDM_CE_FR_LEAK_SH__W 3 -#define OFDM_CE_FR_LEAK_SH__M 0x7 -#define OFDM_CE_FR_LEAK_SH__PRE 0x1 - - - -#define OFDM_CE_NE_RAM__A 0x2C30000 - - - -#define OFDM_CE_PB_RAM__A 0x2C40000 - - - - - -#define OFDM_CP_COMM_EXEC__A 0x2800000 -#define OFDM_CP_COMM_EXEC__W 3 -#define OFDM_CP_COMM_EXEC__M 0x7 -#define OFDM_CP_COMM_EXEC__PRE 0x0 -#define OFDM_CP_COMM_EXEC_STOP 0x0 -#define OFDM_CP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CP_COMM_EXEC_HOLD 0x2 -#define OFDM_CP_COMM_EXEC_STEP 0x3 -#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_CP_COMM_STATE__A 0x2800001 -#define OFDM_CP_COMM_STATE__W 16 -#define OFDM_CP_COMM_STATE__M 0xFFFF -#define OFDM_CP_COMM_STATE__PRE 0x0 -#define OFDM_CP_COMM_MB__A 0x2800002 -#define OFDM_CP_COMM_MB__W 16 -#define OFDM_CP_COMM_MB__M 0xFFFF -#define OFDM_CP_COMM_MB__PRE 0x0 -#define OFDM_CP_COMM_INT_REQ__A 0x2800004 -#define OFDM_CP_COMM_INT_REQ__W 16 -#define OFDM_CP_COMM_INT_REQ__M 0xFFFF -#define OFDM_CP_COMM_INT_REQ__PRE 0x0 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2 -#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0 - -#define OFDM_CP_COMM_INT_STA__A 0x2800005 -#define OFDM_CP_COMM_INT_STA__W 16 -#define OFDM_CP_COMM_INT_STA__M 0xFFFF -#define OFDM_CP_COMM_INT_STA__PRE 0x0 -#define OFDM_CP_COMM_INT_MSK__A 0x2800006 -#define OFDM_CP_COMM_INT_MSK__W 16 -#define OFDM_CP_COMM_INT_MSK__M 0xFFFF -#define OFDM_CP_COMM_INT_MSK__PRE 0x0 -#define OFDM_CP_COMM_INT_STM__A 0x2800007 -#define OFDM_CP_COMM_INT_STM__W 16 -#define OFDM_CP_COMM_INT_STM__M 0xFFFF -#define OFDM_CP_COMM_INT_STM__PRE 0x0 -#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000 -#define OFDM_CP_TOP_COMM_EXEC__W 3 -#define OFDM_CP_TOP_COMM_EXEC__M 0x7 -#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_CP_TOP_COMM_MB__A 0x2810002 -#define OFDM_CP_TOP_COMM_MB__W 3 -#define OFDM_CP_TOP_COMM_MB__M 0x7 -#define OFDM_CP_TOP_COMM_MB__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_CTL__B 0 -#define OFDM_CP_TOP_COMM_MB_CTL__W 1 -#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_CP_TOP_COMM_MB_OBS__B 1 -#define OFDM_CP_TOP_COMM_MB_OBS__W 1 -#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0 -#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4 - -#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004 -#define OFDM_CP_TOP_COMM_INT_REQ__W 1 -#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1 -#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005 -#define OFDM_CP_TOP_COMM_INT_STA__W 1 -#define OFDM_CP_TOP_COMM_INT_STA__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0 - -#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006 -#define OFDM_CP_TOP_COMM_INT_MSK__W 1 -#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1 -#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1 -#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0 - -#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007 -#define OFDM_CP_TOP_COMM_INT_STM__W 1 -#define OFDM_CP_TOP_COMM_INT_STM__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1 -#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0 - - -#define OFDM_CP_TOP_MODE_2K__A 0x2810010 -#define OFDM_CP_TOP_MODE_2K__W 1 -#define OFDM_CP_TOP_MODE_2K__M 0x1 -#define OFDM_CP_TOP_MODE_2K__PRE 0x0 - -#define OFDM_CP_TOP_INTERVAL__A 0x2810011 -#define OFDM_CP_TOP_INTERVAL__W 4 -#define OFDM_CP_TOP_INTERVAL__M 0xF -#define OFDM_CP_TOP_INTERVAL__PRE 0x5 -#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012 -#define OFDM_CP_TOP_DETECT_ENA__W 2 -#define OFDM_CP_TOP_DETECT_ENA__M 0x3 -#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0 - -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0 -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1 -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1 -#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0 - -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1 -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1 -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2 -#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0 - -#define OFDM_CP_TOP_FIX__A 0x2810013 -#define OFDM_CP_TOP_FIX__W 4 -#define OFDM_CP_TOP_FIX__M 0xF -#define OFDM_CP_TOP_FIX__PRE 0xF - -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1 - -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2 - -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4 - -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0 -#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8 - -#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021 -#define OFDM_CP_TOP_BR_SMB_NR__W 4 -#define OFDM_CP_TOP_BR_SMB_NR__M 0xF -#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0 - -#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0 -#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2 -#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3 -#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0 - -#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2 -#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1 -#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4 -#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0 - -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3 -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1 -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8 -#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0 - - -#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022 -#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2 -#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3 -#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0 - -#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023 -#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4 -#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF -#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8 - -#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024 -#define OFDM_CP_TOP_BR_STR_DEL__W 10 -#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF -#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA - -#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025 -#define OFDM_CP_TOP_BR_EXP_ADJ__W 5 -#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F -#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10 - -#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030 -#define OFDM_CP_TOP_RT_ANG_INC0__W 16 -#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF -#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0 - -#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031 -#define OFDM_CP_TOP_RT_ANG_INC1__W 8 -#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF -#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032 -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5 -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F -#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5 - -#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033 -#define OFDM_CP_TOP_RT_DETECT_TRH__W 2 -#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3 -#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3 - -#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034 -#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3 -#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7 -#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035 -#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1 -#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1 -#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036 -#define OFDM_CP_TOP_RT_SPD_MOD__W 2 -#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3 -#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0 - -#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037 -#define OFDM_CP_TOP_RT_SPD_SMB__W 2 -#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3 -#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0 -#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038 -#define OFDM_CP_TOP_RT_CPD_MODE__W 3 -#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7 -#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0 -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2 -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3 -#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2 -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1 -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4 -#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0 - - -#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039 -#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3 -#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7 -#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A -#define OFDM_CP_TOP_RT_CPD_BIN__W 5 -#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F -#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B -#define OFDM_CP_TOP_RT_CPD_MAX__W 4 -#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF -#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0 -#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C -#define OFDM_CP_TOP_RT_SUPR_VAL__W 2 -#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3 -#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0 - -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0 -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1 -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1 -#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0 - -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1 -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1 -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2 -#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0 - - -#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D -#define OFDM_CP_TOP_RT_EXP_AVE__W 5 -#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F -#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0 - -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5 -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F -#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3 - -#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040 -#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8 -#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF -#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0 - -#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041 -#define OFDM_CP_TOP_AC_AVER_POW__W 8 -#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF -#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F - -#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042 -#define OFDM_CP_TOP_AC_MAX_POW__W 8 -#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF -#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A - -#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043 -#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6 -#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F -#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31 - -#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044 -#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5 -#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F -#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10 - -#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045 -#define OFDM_CP_TOP_AC_GAIN_MAN__W 16 -#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF -#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0 - -#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046 -#define OFDM_CP_TOP_AC_GAIN_EXP__W 5 -#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F -#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047 -#define OFDM_CP_TOP_AC_AMP_MODE__W 2 -#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3 -#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2 -#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0 -#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1 -#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2 - -#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048 -#define OFDM_CP_TOP_AC_AMP_FIX__W 14 -#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF -#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0 -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10 -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF -#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10 -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4 -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00 -#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049 -#define OFDM_CP_TOP_AC_AMP_READ__W 14 -#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF -#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0 -#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10 -#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF -#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0 - -#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10 -#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4 -#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00 -#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0 - - -#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A -#define OFDM_CP_TOP_AC_ANG_MODE__W 2 -#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3 -#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3 -#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0 -#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1 -#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2 -#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3 - - -#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B -#define OFDM_CP_TOP_AC_ANG_OFFS__W 16 -#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF -#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0 - -#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C -#define OFDM_CP_TOP_AC_ANG_READ__W 16 -#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF -#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060 -#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8 -#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061 -#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8 -#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062 -#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8 -#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0 - -#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063 -#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8 -#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF -#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050 -#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15 -#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF -#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0 -#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051 -#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5 -#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F -#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2 -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3 -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C -#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2 -#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0 -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1 -#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0 - - -#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052 -#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15 -#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF -#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0 -#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053 -#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11 -#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF -#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10 -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400 -#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5 -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3 -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0 -#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2 -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3 -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C -#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2 -#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0 - -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0 -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1 -#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0 - - - -#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000 - - - -#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000 - - - -#define OFDM_CP_DL_0_RAM__A 0x2840000 - - - -#define OFDM_CP_DL_1_RAM__A 0x2850000 - - - -#define OFDM_CP_DL_2_RAM__A 0x2860000 - - - - - -#define OFDM_EC_COMM_EXEC__A 0x3400000 -#define OFDM_EC_COMM_EXEC__W 3 -#define OFDM_EC_COMM_EXEC__M 0x7 -#define OFDM_EC_COMM_EXEC__PRE 0x0 -#define OFDM_EC_COMM_EXEC_STOP 0x0 -#define OFDM_EC_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_COMM_EXEC_STEP 0x3 -#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_EC_COMM_STATE__A 0x3400001 -#define OFDM_EC_COMM_STATE__W 16 -#define OFDM_EC_COMM_STATE__M 0xFFFF -#define OFDM_EC_COMM_STATE__PRE 0x0 -#define OFDM_EC_COMM_MB__A 0x3400002 -#define OFDM_EC_COMM_MB__W 16 -#define OFDM_EC_COMM_MB__M 0xFFFF -#define OFDM_EC_COMM_MB__PRE 0x0 -#define OFDM_EC_COMM_INT_REQ__A 0x3400004 -#define OFDM_EC_COMM_INT_REQ__W 16 -#define OFDM_EC_COMM_INT_REQ__M 0xFFFF -#define OFDM_EC_COMM_INT_REQ__PRE 0x0 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10 -#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20 -#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0 - -#define OFDM_EC_COMM_INT_STA__A 0x3400005 -#define OFDM_EC_COMM_INT_STA__W 16 -#define OFDM_EC_COMM_INT_STA__M 0xFFFF -#define OFDM_EC_COMM_INT_STA__PRE 0x0 -#define OFDM_EC_COMM_INT_MSK__A 0x3400006 -#define OFDM_EC_COMM_INT_MSK__W 16 -#define OFDM_EC_COMM_INT_MSK__M 0xFFFF -#define OFDM_EC_COMM_INT_MSK__PRE 0x0 -#define OFDM_EC_COMM_INT_STM__A 0x3400007 -#define OFDM_EC_COMM_INT_STM__W 16 -#define OFDM_EC_COMM_INT_STM__M 0xFFFF -#define OFDM_EC_COMM_INT_STM__PRE 0x0 -#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_EC_SB_COMM_EXEC__A 0x3410000 -#define OFDM_EC_SB_COMM_EXEC__W 3 -#define OFDM_EC_SB_COMM_EXEC__M 0x7 -#define OFDM_EC_SB_COMM_EXEC__PRE 0x0 -#define OFDM_EC_SB_COMM_EXEC_STOP 0x0 -#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_SB_COMM_EXEC_STEP 0x3 - -#define OFDM_EC_SB_COMM_STATE__A 0x3410001 -#define OFDM_EC_SB_COMM_STATE__W 4 -#define OFDM_EC_SB_COMM_STATE__M 0xF -#define OFDM_EC_SB_COMM_STATE__PRE 0x0 -#define OFDM_EC_SB_COMM_MB__A 0x3410002 -#define OFDM_EC_SB_COMM_MB__W 2 -#define OFDM_EC_SB_COMM_MB__M 0x3 -#define OFDM_EC_SB_COMM_MB__PRE 0x0 -#define OFDM_EC_SB_COMM_MB_CTL__B 0 -#define OFDM_EC_SB_COMM_MB_CTL__W 1 -#define OFDM_EC_SB_COMM_MB_CTL__M 0x1 -#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0 -#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0 -#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1 -#define OFDM_EC_SB_COMM_MB_OBS__B 1 -#define OFDM_EC_SB_COMM_MB_OBS__W 1 -#define OFDM_EC_SB_COMM_MB_OBS__M 0x2 -#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0 -#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0 -#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2 - - -#define OFDM_EC_SB_TR_MODE__A 0x3410010 -#define OFDM_EC_SB_TR_MODE__W 1 -#define OFDM_EC_SB_TR_MODE__M 0x1 -#define OFDM_EC_SB_TR_MODE__PRE 0x0 -#define OFDM_EC_SB_TR_MODE_8K 0x0 -#define OFDM_EC_SB_TR_MODE_2K 0x1 - - -#define OFDM_EC_SB_CONST__A 0x3410011 -#define OFDM_EC_SB_CONST__W 2 -#define OFDM_EC_SB_CONST__M 0x3 -#define OFDM_EC_SB_CONST__PRE 0x2 -#define OFDM_EC_SB_CONST_QPSK 0x0 -#define OFDM_EC_SB_CONST_16QAM 0x1 -#define OFDM_EC_SB_CONST_64QAM 0x2 - - -#define OFDM_EC_SB_ALPHA__A 0x3410012 -#define OFDM_EC_SB_ALPHA__W 3 -#define OFDM_EC_SB_ALPHA__M 0x7 -#define OFDM_EC_SB_ALPHA__PRE 0x0 -#define OFDM_EC_SB_ALPHA_NH 0x0 -#define OFDM_EC_SB_ALPHA_H1 0x1 -#define OFDM_EC_SB_ALPHA_H2 0x2 -#define OFDM_EC_SB_ALPHA_H4 0x3 - - -#define OFDM_EC_SB_PRIOR__A 0x3410013 -#define OFDM_EC_SB_PRIOR__W 1 -#define OFDM_EC_SB_PRIOR__M 0x1 -#define OFDM_EC_SB_PRIOR__PRE 0x0 -#define OFDM_EC_SB_PRIOR_HI 0x0 -#define OFDM_EC_SB_PRIOR_LO 0x1 - - -#define OFDM_EC_SB_CSI_HI__A 0x3410014 -#define OFDM_EC_SB_CSI_HI__W 5 -#define OFDM_EC_SB_CSI_HI__M 0x1F -#define OFDM_EC_SB_CSI_HI__PRE 0x18 -#define OFDM_EC_SB_CSI_HI_MAX 0x1F -#define OFDM_EC_SB_CSI_HI_MIN 0x0 -#define OFDM_EC_SB_CSI_HI_TAG 0x0 - - -#define OFDM_EC_SB_CSI_LO__A 0x3410015 -#define OFDM_EC_SB_CSI_LO__W 5 -#define OFDM_EC_SB_CSI_LO__M 0x1F -#define OFDM_EC_SB_CSI_LO__PRE 0xC -#define OFDM_EC_SB_CSI_LO_MAX 0x1F -#define OFDM_EC_SB_CSI_LO_MIN 0x0 -#define OFDM_EC_SB_CSI_LO_TAG 0x0 - - -#define OFDM_EC_SB_SMB_TGL__A 0x3410016 -#define OFDM_EC_SB_SMB_TGL__W 1 -#define OFDM_EC_SB_SMB_TGL__M 0x1 -#define OFDM_EC_SB_SMB_TGL__PRE 0x1 -#define OFDM_EC_SB_SMB_TGL_OFF 0x0 -#define OFDM_EC_SB_SMB_TGL_ON 0x1 - - -#define OFDM_EC_SB_SNR_HI__A 0x3410017 -#define OFDM_EC_SB_SNR_HI__W 7 -#define OFDM_EC_SB_SNR_HI__M 0x7F -#define OFDM_EC_SB_SNR_HI__PRE 0x7F -#define OFDM_EC_SB_SNR_HI_MAX 0x7F -#define OFDM_EC_SB_SNR_HI_MIN 0x0 -#define OFDM_EC_SB_SNR_HI_TAG 0x0 - - -#define OFDM_EC_SB_SNR_MID__A 0x3410018 -#define OFDM_EC_SB_SNR_MID__W 7 -#define OFDM_EC_SB_SNR_MID__M 0x7F -#define OFDM_EC_SB_SNR_MID__PRE 0x7F -#define OFDM_EC_SB_SNR_MID_MAX 0x7F -#define OFDM_EC_SB_SNR_MID_MIN 0x0 -#define OFDM_EC_SB_SNR_MID_TAG 0x0 - - -#define OFDM_EC_SB_SNR_LO__A 0x3410019 -#define OFDM_EC_SB_SNR_LO__W 7 -#define OFDM_EC_SB_SNR_LO__M 0x7F -#define OFDM_EC_SB_SNR_LO__PRE 0x7F -#define OFDM_EC_SB_SNR_LO_MAX 0x7F -#define OFDM_EC_SB_SNR_LO_MIN 0x0 -#define OFDM_EC_SB_SNR_LO_TAG 0x0 - - -#define OFDM_EC_SB_SCALE_MSB__A 0x341001A -#define OFDM_EC_SB_SCALE_MSB__W 6 -#define OFDM_EC_SB_SCALE_MSB__M 0x3F -#define OFDM_EC_SB_SCALE_MSB__PRE 0x30 -#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F - - -#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B -#define OFDM_EC_SB_SCALE_BIT2__W 6 -#define OFDM_EC_SB_SCALE_BIT2__M 0x3F -#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC -#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F - - -#define OFDM_EC_SB_SCALE_LSB__A 0x341001C -#define OFDM_EC_SB_SCALE_LSB__W 6 -#define OFDM_EC_SB_SCALE_LSB__M 0x3F -#define OFDM_EC_SB_SCALE_LSB__PRE 0x3 -#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F - - -#define OFDM_EC_SB_CSI_OFS0__A 0x341001D -#define OFDM_EC_SB_CSI_OFS0__W 4 -#define OFDM_EC_SB_CSI_OFS0__M 0xF -#define OFDM_EC_SB_CSI_OFS0__PRE 0x1 - -#define OFDM_EC_SB_CSI_OFS1__A 0x341001E -#define OFDM_EC_SB_CSI_OFS1__W 4 -#define OFDM_EC_SB_CSI_OFS1__M 0xF -#define OFDM_EC_SB_CSI_OFS1__PRE 0x1 - -#define OFDM_EC_SB_CSI_OFS2__A 0x341001F -#define OFDM_EC_SB_CSI_OFS2__W 4 -#define OFDM_EC_SB_CSI_OFS2__M 0xF -#define OFDM_EC_SB_CSI_OFS2__PRE 0x1 - -#define OFDM_EC_SB_MAX0__A 0x3410020 -#define OFDM_EC_SB_MAX0__W 6 -#define OFDM_EC_SB_MAX0__M 0x3F -#define OFDM_EC_SB_MAX0__PRE 0x3F - -#define OFDM_EC_SB_MAX1__A 0x3410021 -#define OFDM_EC_SB_MAX1__W 6 -#define OFDM_EC_SB_MAX1__M 0x3F -#define OFDM_EC_SB_MAX1__PRE 0x3F -#define OFDM_EC_SB_MAX1_INIT 0x3F - - -#define OFDM_EC_SB_MAX2__A 0x3410022 -#define OFDM_EC_SB_MAX2__W 6 -#define OFDM_EC_SB_MAX2__M 0x3F -#define OFDM_EC_SB_MAX2__PRE 0x3F - -#define OFDM_EC_SB_CSI_DIS__A 0x3410023 -#define OFDM_EC_SB_CSI_DIS__W 1 -#define OFDM_EC_SB_CSI_DIS__M 0x1 -#define OFDM_EC_SB_CSI_DIS__PRE 0x0 - - - -#define OFDM_EC_VD_COMM_EXEC__A 0x3420000 -#define OFDM_EC_VD_COMM_EXEC__W 3 -#define OFDM_EC_VD_COMM_EXEC__M 0x7 -#define OFDM_EC_VD_COMM_EXEC__PRE 0x0 -#define OFDM_EC_VD_COMM_EXEC_STOP 0x0 -#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_VD_COMM_EXEC_STEP 0x3 - -#define OFDM_EC_VD_COMM_STATE__A 0x3420001 -#define OFDM_EC_VD_COMM_STATE__W 4 -#define OFDM_EC_VD_COMM_STATE__M 0xF -#define OFDM_EC_VD_COMM_STATE__PRE 0x0 -#define OFDM_EC_VD_COMM_MB__A 0x3420002 -#define OFDM_EC_VD_COMM_MB__W 2 -#define OFDM_EC_VD_COMM_MB__M 0x3 -#define OFDM_EC_VD_COMM_MB__PRE 0x0 -#define OFDM_EC_VD_COMM_MB_CTL__B 0 -#define OFDM_EC_VD_COMM_MB_CTL__W 1 -#define OFDM_EC_VD_COMM_MB_CTL__M 0x1 -#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0 -#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0 -#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1 -#define OFDM_EC_VD_COMM_MB_OBS__B 1 -#define OFDM_EC_VD_COMM_MB_OBS__W 1 -#define OFDM_EC_VD_COMM_MB_OBS__M 0x2 -#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0 -#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0 -#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2 - -#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003 -#define OFDM_EC_VD_COMM_INT_REQ__W 1 -#define OFDM_EC_VD_COMM_INT_REQ__M 0x1 -#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005 -#define OFDM_EC_VD_COMM_INT_STA__W 1 -#define OFDM_EC_VD_COMM_INT_STA__M 0x1 -#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1 -#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0 - -#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006 -#define OFDM_EC_VD_COMM_INT_MSK__W 1 -#define OFDM_EC_VD_COMM_INT_MSK__M 0x1 -#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1 -#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0 - -#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007 -#define OFDM_EC_VD_COMM_INT_STM__W 1 -#define OFDM_EC_VD_COMM_INT_STM__M 0x1 -#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1 -#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0 - - -#define OFDM_EC_VD_FORCE__A 0x3420010 -#define OFDM_EC_VD_FORCE__W 2 -#define OFDM_EC_VD_FORCE__M 0x3 -#define OFDM_EC_VD_FORCE__PRE 0x2 -#define OFDM_EC_VD_FORCE_FREE 0x0 -#define OFDM_EC_VD_FORCE_PROP 0x1 -#define OFDM_EC_VD_FORCE_FORCED 0x2 -#define OFDM_EC_VD_FORCE_FIXED 0x3 - - -#define OFDM_EC_VD_SET_CODERATE__A 0x3420011 -#define OFDM_EC_VD_SET_CODERATE__W 3 -#define OFDM_EC_VD_SET_CODERATE__M 0x7 -#define OFDM_EC_VD_SET_CODERATE__PRE 0x1 -#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0 -#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1 -#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2 -#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3 -#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4 - - -#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012 -#define OFDM_EC_VD_REQ_SMB_CNT__W 16 -#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF -#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1 - -#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013 -#define OFDM_EC_VD_REQ_BIT_CNT__W 16 -#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF -#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF - -#define OFDM_EC_VD_RLK_ENA__A 0x3420014 -#define OFDM_EC_VD_RLK_ENA__W 1 -#define OFDM_EC_VD_RLK_ENA__M 0x1 -#define OFDM_EC_VD_RLK_ENA__PRE 0x1 -#define OFDM_EC_VD_RLK_ENA_OFF 0x0 -#define OFDM_EC_VD_RLK_ENA_ON 0x1 - - -#define OFDM_EC_VD_VAL__A 0x3420015 -#define OFDM_EC_VD_VAL__W 2 -#define OFDM_EC_VD_VAL__M 0x3 -#define OFDM_EC_VD_VAL__PRE 0x0 -#define OFDM_EC_VD_VAL_CODE 0x1 -#define OFDM_EC_VD_VAL_CNT 0x2 - - -#define OFDM_EC_VD_GET_CODERATE__A 0x3420016 -#define OFDM_EC_VD_GET_CODERATE__W 3 -#define OFDM_EC_VD_GET_CODERATE__M 0x7 -#define OFDM_EC_VD_GET_CODERATE__PRE 0x0 -#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0 -#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1 -#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2 -#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3 -#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4 - - -#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 -#define OFDM_EC_VD_ERR_BIT_CNT__W 16 -#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF -#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF - -#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 -#define OFDM_EC_VD_IN_BIT_CNT__W 16 -#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF -#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0 - -#define OFDM_EC_VD_STS__A 0x3420019 -#define OFDM_EC_VD_STS__W 1 -#define OFDM_EC_VD_STS__M 0x1 -#define OFDM_EC_VD_STS__PRE 0x0 -#define OFDM_EC_VD_STS_NO_LOCK 0x0 -#define OFDM_EC_VD_STS_IN_LOCK 0x1 - - -#define OFDM_EC_VD_RLK_CNT__A 0x342001A -#define OFDM_EC_VD_RLK_CNT__W 16 -#define OFDM_EC_VD_RLK_CNT__M 0xFFFF -#define OFDM_EC_VD_RLK_CNT__PRE 0x0 - - - -#define OFDM_EC_SY_COMM_EXEC__A 0x3430000 -#define OFDM_EC_SY_COMM_EXEC__W 2 -#define OFDM_EC_SY_COMM_EXEC__M 0x3 -#define OFDM_EC_SY_COMM_EXEC__PRE 0x0 -#define OFDM_EC_SY_COMM_EXEC_STOP 0x0 -#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2 -#define OFDM_EC_SY_COMM_EXEC_STEP 0x3 - -#define OFDM_EC_SY_COMM_MB__A 0x3430002 -#define OFDM_EC_SY_COMM_MB__W 2 -#define OFDM_EC_SY_COMM_MB__M 0x3 -#define OFDM_EC_SY_COMM_MB__PRE 0x0 -#define OFDM_EC_SY_COMM_MB_CTL__B 0 -#define OFDM_EC_SY_COMM_MB_CTL__W 1 -#define OFDM_EC_SY_COMM_MB_CTL__M 0x1 -#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0 -#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0 -#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1 -#define OFDM_EC_SY_COMM_MB_OBS__B 1 -#define OFDM_EC_SY_COMM_MB_OBS__W 1 -#define OFDM_EC_SY_COMM_MB_OBS__M 0x2 -#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0 -#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0 -#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2 - -#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003 -#define OFDM_EC_SY_COMM_INT_REQ__W 1 -#define OFDM_EC_SY_COMM_INT_REQ__M 0x1 -#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005 -#define OFDM_EC_SY_COMM_INT_STA__W 3 -#define OFDM_EC_SY_COMM_INT_STA__M 0x7 -#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0 -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1 -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1 -#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1 -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1 -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 -#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2 -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1 -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 -#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006 -#define OFDM_EC_SY_COMM_INT_MSK__W 3 -#define OFDM_EC_SY_COMM_INT_MSK__M 0x7 -#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 -#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 -#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 -#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 - -#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007 -#define OFDM_EC_SY_COMM_INT_STM__W 3 -#define OFDM_EC_SY_COMM_INT_STM__M 0x7 -#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1 -#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 -#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 -#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 - -#define OFDM_EC_SY_STATUS__A 0x3430010 -#define OFDM_EC_SY_STATUS__W 2 -#define OFDM_EC_SY_STATUS__M 0x3 -#define OFDM_EC_SY_STATUS__PRE 0x0 -#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0 -#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2 -#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3 -#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0 -#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0 -#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1 -#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2 - - -#define OFDM_EC_SY_TIMEOUT__A 0x3430011 -#define OFDM_EC_SY_TIMEOUT__W 16 -#define OFDM_EC_SY_TIMEOUT__M 0xFFFF -#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98 - -#define OFDM_EC_SY_SYNC_LWM__A 0x3430012 -#define OFDM_EC_SY_SYNC_LWM__W 4 -#define OFDM_EC_SY_SYNC_LWM__M 0xF -#define OFDM_EC_SY_SYNC_LWM__PRE 0x2 - -#define OFDM_EC_SY_SYNC_AWM__A 0x3430013 -#define OFDM_EC_SY_SYNC_AWM__W 4 -#define OFDM_EC_SY_SYNC_AWM__M 0xF -#define OFDM_EC_SY_SYNC_AWM__PRE 0x3 - -#define OFDM_EC_SY_SYNC_HWM__A 0x3430014 -#define OFDM_EC_SY_SYNC_HWM__W 4 -#define OFDM_EC_SY_SYNC_HWM__M 0xF -#define OFDM_EC_SY_SYNC_HWM__PRE 0x5 - -#define OFDM_EC_SY_UNLOCK__A 0x3430015 -#define OFDM_EC_SY_UNLOCK__W 1 -#define OFDM_EC_SY_UNLOCK__M 0x1 -#define OFDM_EC_SY_UNLOCK__PRE 0x0 - - - -#define OFDM_EC_SB_BD0_RAM__A 0x3440000 - - - -#define OFDM_EC_SB_BD1_RAM__A 0x3450000 - - - -#define OFDM_EC_SB_SD_RAM__A 0x3460000 - - - -#define OFDM_EC_VD_RE_RAM__A 0x3470000 - - - -#define OFDM_EC_VD_TB0_RAM__A 0x3480000 - - - -#define OFDM_EC_VD_TB1_RAM__A 0x3490000 - - - -#define OFDM_EC_VD_TB2_RAM__A 0x34A0000 - - - -#define OFDM_EC_VD_TB3_RAM__A 0x34B0000 - - - - - -#define OFDM_EQ_COMM_EXEC__A 0x3000000 -#define OFDM_EQ_COMM_EXEC__W 3 -#define OFDM_EQ_COMM_EXEC__M 0x7 -#define OFDM_EQ_COMM_EXEC__PRE 0x0 -#define OFDM_EQ_COMM_EXEC_STOP 0x0 -#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EQ_COMM_EXEC_HOLD 0x2 -#define OFDM_EQ_COMM_EXEC_STEP 0x3 -#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_EQ_COMM_STATE__A 0x3000001 -#define OFDM_EQ_COMM_STATE__W 16 -#define OFDM_EQ_COMM_STATE__M 0xFFFF -#define OFDM_EQ_COMM_STATE__PRE 0x0 -#define OFDM_EQ_COMM_MB__A 0x3000002 -#define OFDM_EQ_COMM_MB__W 16 -#define OFDM_EQ_COMM_MB__M 0xFFFF -#define OFDM_EQ_COMM_MB__PRE 0x0 -#define OFDM_EQ_COMM_INT_REQ__A 0x3000004 -#define OFDM_EQ_COMM_INT_REQ__W 16 -#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF -#define OFDM_EQ_COMM_INT_REQ__PRE 0x0 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8 -#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0 - -#define OFDM_EQ_COMM_INT_STA__A 0x3000005 -#define OFDM_EQ_COMM_INT_STA__W 16 -#define OFDM_EQ_COMM_INT_STA__M 0xFFFF -#define OFDM_EQ_COMM_INT_STA__PRE 0x0 -#define OFDM_EQ_COMM_INT_MSK__A 0x3000006 -#define OFDM_EQ_COMM_INT_MSK__W 16 -#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF -#define OFDM_EQ_COMM_INT_MSK__PRE 0x0 -#define OFDM_EQ_COMM_INT_STM__A 0x3000007 -#define OFDM_EQ_COMM_INT_STM__W 16 -#define OFDM_EQ_COMM_INT_STM__M 0xFFFF -#define OFDM_EQ_COMM_INT_STM__PRE 0x0 -#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000 -#define OFDM_EQ_TOP_COMM_EXEC__W 3 -#define OFDM_EQ_TOP_COMM_EXEC__M 0x7 -#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001 -#define OFDM_EQ_TOP_COMM_STATE__W 4 -#define OFDM_EQ_TOP_COMM_STATE__M 0xF -#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB__A 0x3010002 -#define OFDM_EQ_TOP_COMM_MB__W 6 -#define OFDM_EQ_TOP_COMM_MB__M 0x3F -#define OFDM_EQ_TOP_COMM_MB__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL__B 0 -#define OFDM_EQ_TOP_COMM_MB_CTL__W 1 -#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_EQ_TOP_COMM_MB_OBS__B 1 -#define OFDM_EQ_TOP_COMM_MB_OBS__W 1 -#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4 -#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20 -#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30 - -#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004 -#define OFDM_EQ_TOP_COMM_INT_REQ__W 1 -#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005 -#define OFDM_EQ_TOP_COMM_INT_STA__W 2 -#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3 -#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2 -#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0 - -#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006 -#define OFDM_EQ_TOP_COMM_INT_MSK__W 2 -#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3 -#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2 -#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0 - -#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007 -#define OFDM_EQ_TOP_COMM_INT_STM__W 2 -#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3 -#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1 -#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2 -#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0 - -#define OFDM_EQ_TOP_IS_MODE__A 0x3010014 -#define OFDM_EQ_TOP_IS_MODE__W 4 -#define OFDM_EQ_TOP_IS_MODE__M 0xF -#define OFDM_EQ_TOP_IS_MODE__PRE 0x0 - -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1 - -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4 - -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0 -#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8 - - -#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015 -#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10 -#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF -#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114 - -#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016 -#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5 -#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F -#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5 - -#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017 -#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5 -#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F -#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10 -#define OFDM_EQ_TOP_DV_MODE__A 0x301001E -#define OFDM_EQ_TOP_DV_MODE__W 4 -#define OFDM_EQ_TOP_DV_MODE__M 0xF -#define OFDM_EQ_TOP_DV_MODE__PRE 0xF - -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1 - -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2 - -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4 - -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0 -#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8 - - -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16 -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF -#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE__A 0x3010028 -#define OFDM_EQ_TOP_SN_MODE__W 8 -#define OFDM_EQ_TOP_SN_MODE__M 0xFF -#define OFDM_EQ_TOP_SN_MODE__PRE 0x18 - -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1 - -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2 - -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4 - -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8 - -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10 - -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0 -#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20 - -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0 -#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40 - -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0 -#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80 - - -#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029 -#define OFDM_EQ_TOP_SN_PFIX__W 8 -#define OFDM_EQ_TOP_SN_PFIX__M 0xFF -#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0 - -#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A -#define OFDM_EQ_TOP_SN_CEGAIN__W 8 -#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF -#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30 - -#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B -#define OFDM_EQ_TOP_SN_OFFSET__W 6 -#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F -#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39 - -#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C -#define OFDM_EQ_TOP_SN_NULLIFY__W 6 -#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F -#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0 -#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D -#define OFDM_EQ_TOP_SN_SQUASH__W 10 -#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF -#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7 - -#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0 -#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6 -#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F -#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7 - -#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6 -#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4 -#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0 -#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0 - -#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032 -#define OFDM_EQ_TOP_RC_SEL_CAR__W 8 -#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF -#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1 - -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4 -#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6 - -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10 -#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18 - -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40 -#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60 - -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0 -#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80 - -#define OFDM_EQ_TOP_RC_STS__A 0x3010033 -#define OFDM_EQ_TOP_RC_STS__W 16 -#define OFDM_EQ_TOP_RC_STS__M 0xFFFF -#define OFDM_EQ_TOP_RC_STS__PRE 0x0 - -#define OFDM_EQ_TOP_RC_STS_DIFF__B 0 -#define OFDM_EQ_TOP_RC_STS_DIFF__W 11 -#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF -#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0 - -#define OFDM_EQ_TOP_RC_STS_FIRST__B 11 -#define OFDM_EQ_TOP_RC_STS_FIRST__W 1 -#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800 -#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0 -#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800 - -#define OFDM_EQ_TOP_RC_STS_SELEC__B 12 -#define OFDM_EQ_TOP_RC_STS_SELEC__W 1 -#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000 -#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0 -#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000 - -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0 -#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000 - -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0 -#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000 - -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0 -#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000 - - -#define OFDM_EQ_TOP_OT_CONST__A 0x3010046 -#define OFDM_EQ_TOP_OT_CONST__W 2 -#define OFDM_EQ_TOP_OT_CONST__M 0x3 -#define OFDM_EQ_TOP_OT_CONST__PRE 0x2 - -#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047 -#define OFDM_EQ_TOP_OT_ALPHA__W 2 -#define OFDM_EQ_TOP_OT_ALPHA__M 0x3 -#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0 - -#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048 -#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5 -#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F -#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E - -#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049 -#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5 -#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F -#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F - -#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A -#define OFDM_EQ_TOP_OT_CSI_STEP__W 4 -#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF -#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5 - -#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B -#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8 -#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF -#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5 - -#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C -#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8 -#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF -#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B - -#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D -#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7 -#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F -#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0 - -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7 -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F -#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050 -#define OFDM_EQ_TOP_TD_TPS_INIT__W 1 -#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1 -#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0 -#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1 - - -#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051 -#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16 -#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF -#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE -#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11 - - -#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052 -#define OFDM_EQ_TOP_TD_TPS_LEN__W 6 -#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F -#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17 -#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F - - -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2 -#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3 - - -#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 -#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 -#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 -#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 - - -#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055 -#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3 -#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0 -#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1 -#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2 -#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3 - - -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4 - - -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 - - -#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058 -#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2 -#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0 -#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1 -#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2 -#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3 - - -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0 -#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1 - - -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8 -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8 -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF -#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C -#define OFDM_EQ_TOP_TD_TPS_RSV__W 6 -#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F -#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0 - -#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D -#define OFDM_EQ_TOP_TD_TPS_BCH__W 14 -#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF -#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0 - -#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E -#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16 -#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF -#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0 - -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16 -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0 - -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4 -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0 - -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16 -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200 - -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10 -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F - - - - - -#define OFDM_FE_COMM_EXEC__A 0x2000000 -#define OFDM_FE_COMM_EXEC__W 3 -#define OFDM_FE_COMM_EXEC__M 0x7 -#define OFDM_FE_COMM_EXEC__PRE 0x0 -#define OFDM_FE_COMM_EXEC_STOP 0x0 -#define OFDM_FE_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FE_COMM_EXEC_HOLD 0x2 -#define OFDM_FE_COMM_EXEC_STEP 0x3 - -#define OFDM_FE_COMM_STATE__A 0x2000001 -#define OFDM_FE_COMM_STATE__W 16 -#define OFDM_FE_COMM_STATE__M 0xFFFF -#define OFDM_FE_COMM_STATE__PRE 0x0 -#define OFDM_FE_COMM_MB__A 0x2000002 -#define OFDM_FE_COMM_MB__W 16 -#define OFDM_FE_COMM_MB__M 0xFFFF -#define OFDM_FE_COMM_MB__PRE 0x0 -#define OFDM_FE_COMM_INT_REQ__A 0x2000004 -#define OFDM_FE_COMM_INT_REQ__W 16 -#define OFDM_FE_COMM_INT_REQ__M 0xFFFF -#define OFDM_FE_COMM_INT_REQ__PRE 0x0 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1 -#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0 - -#define OFDM_FE_COMM_INT_STA__A 0x2000005 -#define OFDM_FE_COMM_INT_STA__W 16 -#define OFDM_FE_COMM_INT_STA__M 0xFFFF -#define OFDM_FE_COMM_INT_STA__PRE 0x0 -#define OFDM_FE_COMM_INT_MSK__A 0x2000006 -#define OFDM_FE_COMM_INT_MSK__W 16 -#define OFDM_FE_COMM_INT_MSK__M 0xFFFF -#define OFDM_FE_COMM_INT_MSK__PRE 0x0 -#define OFDM_FE_COMM_INT_STM__A 0x2000007 -#define OFDM_FE_COMM_INT_STM__W 16 -#define OFDM_FE_COMM_INT_STM__M 0xFFFF -#define OFDM_FE_COMM_INT_STM__PRE 0x0 -#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_FE_CU_COMM_EXEC__A 0x2010000 -#define OFDM_FE_CU_COMM_EXEC__W 3 -#define OFDM_FE_CU_COMM_EXEC__M 0x7 -#define OFDM_FE_CU_COMM_EXEC__PRE 0x0 -#define OFDM_FE_CU_COMM_EXEC_STOP 0x0 -#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2 -#define OFDM_FE_CU_COMM_EXEC_STEP 0x3 - -#define OFDM_FE_CU_COMM_STATE__A 0x2010001 -#define OFDM_FE_CU_COMM_STATE__W 4 -#define OFDM_FE_CU_COMM_STATE__M 0xF -#define OFDM_FE_CU_COMM_STATE__PRE 0x0 -#define OFDM_FE_CU_COMM_MB__A 0x2010002 -#define OFDM_FE_CU_COMM_MB__W 2 -#define OFDM_FE_CU_COMM_MB__M 0x3 -#define OFDM_FE_CU_COMM_MB__PRE 0x0 -#define OFDM_FE_CU_COMM_MB_CTL__B 0 -#define OFDM_FE_CU_COMM_MB_CTL__W 1 -#define OFDM_FE_CU_COMM_MB_CTL__M 0x1 -#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0 -#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0 -#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1 -#define OFDM_FE_CU_COMM_MB_OBS__B 1 -#define OFDM_FE_CU_COMM_MB_OBS__W 1 -#define OFDM_FE_CU_COMM_MB_OBS__M 0x2 -#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0 -#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0 -#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2 - -#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004 -#define OFDM_FE_CU_COMM_INT_REQ__W 1 -#define OFDM_FE_CU_COMM_INT_REQ__M 0x1 -#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005 -#define OFDM_FE_CU_COMM_INT_STA__W 4 -#define OFDM_FE_CU_COMM_INT_STA__M 0xF -#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1 -#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2 -#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4 -#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8 -#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0 - -#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006 -#define OFDM_FE_CU_COMM_INT_MSK__W 4 -#define OFDM_FE_CU_COMM_INT_MSK__M 0xF -#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1 -#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2 -#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4 -#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8 -#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0 - -#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007 -#define OFDM_FE_CU_COMM_INT_STM__W 4 -#define OFDM_FE_CU_COMM_INT_STM__M 0xF -#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1 -#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2 -#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4 -#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8 -#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0 - -#define OFDM_FE_CU_MODE__A 0x2010010 -#define OFDM_FE_CU_MODE__W 8 -#define OFDM_FE_CU_MODE__M 0xFF -#define OFDM_FE_CU_MODE__PRE 0x20 - -#define OFDM_FE_CU_MODE_FFT__B 0 -#define OFDM_FE_CU_MODE_FFT__W 1 -#define OFDM_FE_CU_MODE_FFT__M 0x1 -#define OFDM_FE_CU_MODE_FFT__PRE 0x0 -#define OFDM_FE_CU_MODE_FFT_M8K 0x0 -#define OFDM_FE_CU_MODE_FFT_M2K 0x1 - -#define OFDM_FE_CU_MODE_COR__B 1 -#define OFDM_FE_CU_MODE_COR__W 1 -#define OFDM_FE_CU_MODE_COR__M 0x2 -#define OFDM_FE_CU_MODE_COR__PRE 0x0 -#define OFDM_FE_CU_MODE_COR_OFF 0x0 -#define OFDM_FE_CU_MODE_COR_ON 0x2 - -#define OFDM_FE_CU_MODE_IFD__B 2 -#define OFDM_FE_CU_MODE_IFD__W 1 -#define OFDM_FE_CU_MODE_IFD__M 0x4 -#define OFDM_FE_CU_MODE_IFD__PRE 0x0 -#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0 -#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4 - -#define OFDM_FE_CU_MODE_SEL__B 3 -#define OFDM_FE_CU_MODE_SEL__W 1 -#define OFDM_FE_CU_MODE_SEL__M 0x8 -#define OFDM_FE_CU_MODE_SEL__PRE 0x0 -#define OFDM_FE_CU_MODE_SEL_COR 0x0 -#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8 - -#define OFDM_FE_CU_MODE_FES__B 4 -#define OFDM_FE_CU_MODE_FES__W 1 -#define OFDM_FE_CU_MODE_FES__M 0x10 -#define OFDM_FE_CU_MODE_FES__PRE 0x0 -#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0 -#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10 -#define OFDM_FE_CU_MODE_AVG__B 5 -#define OFDM_FE_CU_MODE_AVG__W 1 -#define OFDM_FE_CU_MODE_AVG__M 0x20 -#define OFDM_FE_CU_MODE_AVG__PRE 0x20 -#define OFDM_FE_CU_MODE_AVG_OFF 0x0 -#define OFDM_FE_CU_MODE_AVG_ON 0x20 -#define OFDM_FE_CU_MODE_SHF_ENA__B 6 -#define OFDM_FE_CU_MODE_SHF_ENA__W 1 -#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40 -#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0 -#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0 -#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40 -#define OFDM_FE_CU_MODE_SHF_DIR__B 7 -#define OFDM_FE_CU_MODE_SHF_DIR__W 1 -#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80 -#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0 -#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0 -#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80 - - -#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011 -#define OFDM_FE_CU_FRM_CNT_RST__W 15 -#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF -#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF - -#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012 -#define OFDM_FE_CU_FRM_CNT_STR__W 15 -#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF -#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E - -#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013 -#define OFDM_FE_CU_FRM_SMP_CNT__W 15 -#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF -#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0 - -#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014 -#define OFDM_FE_CU_FRM_SMB_CNT__W 16 -#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF -#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015 -#define OFDM_FE_CU_CMP_MAX_DAT__W 12 -#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016 -#define OFDM_FE_CU_CMP_MAX_ADR__W 10 -#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF -#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017 -#define OFDM_FE_CU_CMP_MAX_RE__W 12 -#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018 -#define OFDM_FE_CU_CMP_MAX_IM__W 12 -#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0 - -#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F -#define OFDM_FE_CU_BUF_NFC_DEL__W 14 -#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF -#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0 - -#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020 -#define OFDM_FE_CU_CTR_NFC_ICR__W 5 -#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F -#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1 - -#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021 -#define OFDM_FE_CU_CTR_NFC_OCR__W 15 -#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF -#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8 - -#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022 -#define OFDM_FE_CU_CTR_NFC_CNT__W 15 -#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF -#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0 - -#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023 -#define OFDM_FE_CU_CTR_NFC_STS__W 3 -#define OFDM_FE_CU_CTR_NFC_STS__M 0x7 -#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0 -#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0 -#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1 -#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2 -#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4 - - -#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024 -#define OFDM_FE_CU_DIV_NFC_REA__W 14 -#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF -#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0 - -#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025 -#define OFDM_FE_CU_DIV_NFC_IMA__W 14 -#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF -#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0 - -#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026 -#define OFDM_FE_CU_FRM_CNT_UPD__W 15 -#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF -#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF - -#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027 -#define OFDM_FE_CU_DIV_NFC_CLP__W 2 -#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3 -#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2 -#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3 - - -#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028 -#define OFDM_FE_CU_CMP_MAX_32__W 12 -#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029 -#define OFDM_FE_CU_CMP_MAX_16__W 12 -#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A -#define OFDM_FE_CU_CMP_MAX_8__W 12 -#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0 - -#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B -#define OFDM_FE_CU_CMP_MAX_4__W 12 -#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF -#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C -#define OFDM_FE_CU_CMP_SUM_32_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D -#define OFDM_FE_CU_CMP_SUM_32_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E -#define OFDM_FE_CU_CMP_SUM_16_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F -#define OFDM_FE_CU_CMP_SUM_16_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030 -#define OFDM_FE_CU_CMP_SUM_8_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031 -#define OFDM_FE_CU_CMP_SUM_8_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032 -#define OFDM_FE_CU_CMP_SUM_4_RE__W 14 -#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0 - -#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033 -#define OFDM_FE_CU_CMP_SUM_4_IM__W 14 -#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF -#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0 - - - -#define OFDM_FE_CU_BUF_RAM__A 0x2020000 - - - -#define OFDM_FE_CU_CMP_RAM__A 0x2030000 - - - - - -#define OFDM_FT_COMM_EXEC__A 0x2400000 -#define OFDM_FT_COMM_EXEC__W 3 -#define OFDM_FT_COMM_EXEC__M 0x7 -#define OFDM_FT_COMM_EXEC__PRE 0x0 -#define OFDM_FT_COMM_EXEC_STOP 0x0 -#define OFDM_FT_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FT_COMM_EXEC_HOLD 0x2 -#define OFDM_FT_COMM_EXEC_STEP 0x3 -#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_FT_COMM_STATE__A 0x2400001 -#define OFDM_FT_COMM_STATE__W 16 -#define OFDM_FT_COMM_STATE__M 0xFFFF -#define OFDM_FT_COMM_STATE__PRE 0x0 -#define OFDM_FT_COMM_MB__A 0x2400002 -#define OFDM_FT_COMM_MB__W 16 -#define OFDM_FT_COMM_MB__M 0xFFFF -#define OFDM_FT_COMM_MB__PRE 0x0 - - - -#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000 -#define OFDM_FT_TOP_COMM_EXEC__W 3 -#define OFDM_FT_TOP_COMM_EXEC__M 0x7 -#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0 -#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0 -#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1 -#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2 -#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3 - -#define OFDM_FT_TOP_COMM_MB__A 0x2410002 -#define OFDM_FT_TOP_COMM_MB__W 2 -#define OFDM_FT_TOP_COMM_MB__M 0x3 -#define OFDM_FT_TOP_COMM_MB__PRE 0x0 -#define OFDM_FT_TOP_COMM_MB_CTL__B 0 -#define OFDM_FT_TOP_COMM_MB_CTL__W 1 -#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1 -#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0 -#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0 -#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1 -#define OFDM_FT_TOP_COMM_MB_OBS__B 1 -#define OFDM_FT_TOP_COMM_MB_OBS__W 1 -#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2 -#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0 -#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0 -#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2 - - -#define OFDM_FT_TOP_MODE_2K__A 0x2410010 -#define OFDM_FT_TOP_MODE_2K__W 1 -#define OFDM_FT_TOP_MODE_2K__M 0x1 -#define OFDM_FT_TOP_MODE_2K__PRE 0x0 -#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0 -#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1 - - -#define OFDM_FT_TOP_NORM_OFF__A 0x2410016 -#define OFDM_FT_TOP_NORM_OFF__W 4 -#define OFDM_FT_TOP_NORM_OFF__M 0xF -#define OFDM_FT_TOP_NORM_OFF__PRE 0x2 - - - -#define OFDM_FT_0TO2_0_RAM__A 0x2420000 - - - -#define OFDM_FT_0TO2_1_RAM__A 0x2430000 - - - -#define OFDM_FT_0TO2_2_RAM__A 0x2440000 - - - -#define OFDM_FT_3TO7_0_RAM__A 0x2450000 - - - -#define OFDM_FT_3TO7_1_RAM__A 0x2460000 - - - - - -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_LC_COMM_EXEC__W 3 -#define OFDM_LC_COMM_EXEC__M 0x7 -#define OFDM_LC_COMM_EXEC__PRE 0x0 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC_ACTIVE 0x1 -#define OFDM_LC_COMM_EXEC_HOLD 0x2 -#define OFDM_LC_COMM_EXEC_STEP 0x3 -#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_LC_COMM_STATE__A 0x3800001 -#define OFDM_LC_COMM_STATE__W 16 -#define OFDM_LC_COMM_STATE__M 0xFFFF -#define OFDM_LC_COMM_STATE__PRE 0x0 -#define OFDM_LC_COMM_MB__A 0x3800002 -#define OFDM_LC_COMM_MB__W 16 -#define OFDM_LC_COMM_MB__M 0xFFFF -#define OFDM_LC_COMM_MB__PRE 0x0 -#define OFDM_LC_COMM_INT_REQ__A 0x3800004 -#define OFDM_LC_COMM_INT_REQ__W 16 -#define OFDM_LC_COMM_INT_REQ__M 0xFFFF -#define OFDM_LC_COMM_INT_REQ__PRE 0x0 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40 -#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0 - -#define OFDM_LC_COMM_INT_STA__A 0x3800005 -#define OFDM_LC_COMM_INT_STA__W 16 -#define OFDM_LC_COMM_INT_STA__M 0xFFFF -#define OFDM_LC_COMM_INT_STA__PRE 0x0 -#define OFDM_LC_COMM_INT_MSK__A 0x3800006 -#define OFDM_LC_COMM_INT_MSK__W 16 -#define OFDM_LC_COMM_INT_MSK__M 0xFFFF -#define OFDM_LC_COMM_INT_MSK__PRE 0x0 -#define OFDM_LC_COMM_INT_STM__A 0x3800007 -#define OFDM_LC_COMM_INT_STM__W 16 -#define OFDM_LC_COMM_INT_STM__M 0xFFFF -#define OFDM_LC_COMM_INT_STM__PRE 0x0 -#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_LC_CT_COMM_EXEC__A 0x3810000 -#define OFDM_LC_CT_COMM_EXEC__W 3 -#define OFDM_LC_CT_COMM_EXEC__M 0x7 -#define OFDM_LC_CT_COMM_EXEC__PRE 0x0 -#define OFDM_LC_CT_COMM_EXEC_STOP 0x0 -#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1 -#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2 -#define OFDM_LC_CT_COMM_EXEC_STEP 0x3 - - -#define OFDM_LC_CT_COMM_STATE__A 0x3810001 -#define OFDM_LC_CT_COMM_STATE__W 10 -#define OFDM_LC_CT_COMM_STATE__M 0x3FF -#define OFDM_LC_CT_COMM_STATE__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004 -#define OFDM_LC_CT_COMM_INT_REQ__W 1 -#define OFDM_LC_CT_COMM_INT_REQ__M 0x1 -#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005 -#define OFDM_LC_CT_COMM_INT_STA__W 1 -#define OFDM_LC_CT_COMM_INT_STA__M 0x1 -#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1 -#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0 - -#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006 -#define OFDM_LC_CT_COMM_INT_MSK__W 1 -#define OFDM_LC_CT_COMM_INT_MSK__M 0x1 -#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1 -#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 - -#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007 -#define OFDM_LC_CT_COMM_INT_STM__W 1 -#define OFDM_LC_CT_COMM_INT_STM__M 0x1 -#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1 -#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0 - - -#define OFDM_LC_CT_CTL_STK_0__A 0x3810010 -#define OFDM_LC_CT_CTL_STK_0__W 10 -#define OFDM_LC_CT_CTL_STK_0__M 0x3FF -#define OFDM_LC_CT_CTL_STK_0__PRE 0x0 - -#define OFDM_LC_CT_CTL_STK_1__A 0x3810011 -#define OFDM_LC_CT_CTL_STK_1__W 10 -#define OFDM_LC_CT_CTL_STK_1__M 0x3FF -#define OFDM_LC_CT_CTL_STK_1__PRE 0x0 - -#define OFDM_LC_CT_CTL_STK_2__A 0x3810012 -#define OFDM_LC_CT_CTL_STK_2__W 10 -#define OFDM_LC_CT_CTL_STK_2__M 0x3FF -#define OFDM_LC_CT_CTL_STK_2__PRE 0x0 - -#define OFDM_LC_CT_CTL_STK_3__A 0x3810013 -#define OFDM_LC_CT_CTL_STK_3__W 10 -#define OFDM_LC_CT_CTL_STK_3__M 0x3FF -#define OFDM_LC_CT_CTL_STK_3__PRE 0x0 - -#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F -#define OFDM_LC_CT_CTL_BPT_IDX__W 1 -#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1 -#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0 - -#define OFDM_LC_CT_CTL_BPT__A 0x3810020 -#define OFDM_LC_CT_CTL_BPT__W 10 -#define OFDM_LC_CT_CTL_BPT__M 0x3FF -#define OFDM_LC_CT_CTL_BPT__PRE 0x0 - - - -#define OFDM_LC_RA_RAM__A 0x3820000 - - - - -#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000 -#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12 -#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001 -#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12 -#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002 -#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12 -#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004 -#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12 -#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006 -#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12 -#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0 - -#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007 -#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12 -#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF -#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0 - - - - - - - -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006 -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16 -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF -#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007 -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16 -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF -#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008 -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16 -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009 -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16 -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 -#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A -#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16 -#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF -#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0 -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16 -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF -#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0 -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16 -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF -#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0 -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16 -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF -#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0 -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16 -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF -#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0 -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16 -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF -#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010 -#define OFDM_LC_RA_RAM_MODE_2K__W 16 -#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF -#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011 -#define OFDM_LC_RA_RAM_MODE_GUARD__W 16 -#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF -#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0 -#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1 -#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2 -#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3 - -#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012 -#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16 -#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF -#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 -#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 -#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 -#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 -#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000 -#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000 -#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0 - -#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014 -#define OFDM_LC_RA_RAM_RC_STS__W 16 -#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF -#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16 -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16 -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16 -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF -#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16 -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF -#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020 -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021 -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022 -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0 -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023 -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16 -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF -#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024 -#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16 -#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025 -#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16 -#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026 -#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16 -#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0 -#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027 -#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16 -#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF -#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E -#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16 -#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF -#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060 -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7 -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061 -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068 -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069 -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070 -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071 -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078 -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079 -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16 -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF -#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0 - - - - - -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__W 3 -#define OFDM_SC_COMM_EXEC__M 0x7 -#define OFDM_SC_COMM_EXEC__PRE 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_ACTIVE 0x1 -#define OFDM_SC_COMM_EXEC_HOLD 0x2 -#define OFDM_SC_COMM_EXEC_STEP 0x3 -#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4 -#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6 - -#define OFDM_SC_COMM_STATE__A 0x3C00001 -#define OFDM_SC_COMM_STATE__W 16 -#define OFDM_SC_COMM_STATE__M 0xFFFF -#define OFDM_SC_COMM_STATE__PRE 0x0 -#define OFDM_SC_COMM_MB__A 0x3C00002 -#define OFDM_SC_COMM_MB__W 16 -#define OFDM_SC_COMM_MB__M 0xFFFF -#define OFDM_SC_COMM_MB__PRE 0x0 -#define OFDM_SC_COMM_INT_REQ__A 0x3C00004 -#define OFDM_SC_COMM_INT_REQ__W 16 -#define OFDM_SC_COMM_INT_REQ__M 0xFFFF -#define OFDM_SC_COMM_INT_REQ__PRE 0x0 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80 -#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0 - -#define OFDM_SC_COMM_INT_STA__A 0x3C00005 -#define OFDM_SC_COMM_INT_STA__W 16 -#define OFDM_SC_COMM_INT_STA__M 0xFFFF -#define OFDM_SC_COMM_INT_STA__PRE 0x0 -#define OFDM_SC_COMM_INT_MSK__A 0x3C00006 -#define OFDM_SC_COMM_INT_MSK__W 16 -#define OFDM_SC_COMM_INT_MSK__M 0xFFFF -#define OFDM_SC_COMM_INT_MSK__PRE 0x0 -#define OFDM_SC_COMM_INT_STM__A 0x3C00007 -#define OFDM_SC_COMM_INT_STM__W 16 -#define OFDM_SC_COMM_INT_STM__M 0xFFFF -#define OFDM_SC_COMM_INT_STM__PRE 0x0 -#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0 -#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16 -#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF -#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0 - - - -#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000 -#define OFDM_SC_CT_COMM_EXEC__W 3 -#define OFDM_SC_CT_COMM_EXEC__M 0x7 -#define OFDM_SC_CT_COMM_EXEC__PRE 0x0 -#define OFDM_SC_CT_COMM_EXEC_STOP 0x0 -#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1 -#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2 -#define OFDM_SC_CT_COMM_EXEC_STEP 0x3 - - -#define OFDM_SC_CT_COMM_STATE__A 0x3C10001 -#define OFDM_SC_CT_COMM_STATE__W 10 -#define OFDM_SC_CT_COMM_STATE__M 0x3FF -#define OFDM_SC_CT_COMM_STATE__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004 -#define OFDM_SC_CT_COMM_INT_REQ__W 1 -#define OFDM_SC_CT_COMM_INT_REQ__M 0x1 -#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005 -#define OFDM_SC_CT_COMM_INT_STA__W 1 -#define OFDM_SC_CT_COMM_INT_STA__M 0x1 -#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1 -#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0 - -#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006 -#define OFDM_SC_CT_COMM_INT_MSK__W 1 -#define OFDM_SC_CT_COMM_INT_MSK__M 0x1 -#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1 -#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 - -#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007 -#define OFDM_SC_CT_COMM_INT_STM__W 1 -#define OFDM_SC_CT_COMM_INT_STM__M 0x1 -#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1 -#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0 - - -#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010 -#define OFDM_SC_CT_CTL_STK_0__W 10 -#define OFDM_SC_CT_CTL_STK_0__M 0x3FF -#define OFDM_SC_CT_CTL_STK_0__PRE 0x0 - -#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011 -#define OFDM_SC_CT_CTL_STK_1__W 10 -#define OFDM_SC_CT_CTL_STK_1__M 0x3FF -#define OFDM_SC_CT_CTL_STK_1__PRE 0x0 - -#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012 -#define OFDM_SC_CT_CTL_STK_2__W 10 -#define OFDM_SC_CT_CTL_STK_2__M 0x3FF -#define OFDM_SC_CT_CTL_STK_2__PRE 0x0 - -#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013 -#define OFDM_SC_CT_CTL_STK_3__W 10 -#define OFDM_SC_CT_CTL_STK_3__M 0x3FF -#define OFDM_SC_CT_CTL_STK_3__PRE 0x0 - -#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F -#define OFDM_SC_CT_CTL_BPT_IDX__W 1 -#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1 -#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0 - -#define OFDM_SC_CT_CTL_BPT__A 0x3C10020 -#define OFDM_SC_CT_CTL_BPT__W 13 -#define OFDM_SC_CT_CTL_BPT__M 0x1FFF -#define OFDM_SC_CT_CTL_BPT__PRE 0x0 - - - -#define OFDM_SC_RA_RAM__A 0x3C20000 - - - - -#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000 -#define OFDM_SC_IF_RAM_TRP_RST_0__W 12 -#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001 -#define OFDM_SC_IF_RAM_TRP_RST_1__W 12 -#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002 -#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12 -#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004 -#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12 -#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004 -#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12 -#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0 - -#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005 -#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12 -#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF -#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0 - -#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE -#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12 -#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF -#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0 - -#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF -#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12 -#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF -#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0 - - - - - - - -#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 -#define OFDM_SC_RA_RAM_PARAM0__W 16 -#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 -#define OFDM_SC_RA_RAM_PARAM1__W 16 -#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 -#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 -#define OFDM_SC_RA_RAM_CMD_ADDR__W 16 -#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF -#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0 -#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 -#define OFDM_SC_RA_RAM_CMD__W 16 -#define OFDM_SC_RA_RAM_CMD__M 0xFFFF -#define OFDM_SC_RA_RAM_CMD__PRE 0x0 -#define OFDM_SC_RA_RAM_CMD_NULL 0x0 -#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 -#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 -#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 -#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 -#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 -#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define OFDM_SC_RA_RAM_CMD_MAX 0x9 -#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4 - -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044 -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16 -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF -#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF -#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045 -#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16 -#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF -#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046 -#define OFDM_SC_RA_RAM_SW_EVENT__W 14 -#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF -#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 -#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 -#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 -#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 -#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 -#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 -#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 -#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0 - -#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047 -#define OFDM_SC_RA_RAM_LOCKTRACK__W 16 -#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF -#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0 -#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1 -#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 -#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3 -#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4 -#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5 -#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6 -#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7 -#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8 -#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9 - -#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 -#define OFDM_SC_RA_RAM_OP_PARAM__W 13 -#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF -#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 - -#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049 -#define OFDM_SC_RA_RAM_OP_AUTO__W 6 -#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F -#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 -#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0 - -#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A -#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16 -#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0 -#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0 -#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 -#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 -#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 - -#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B -#define OFDM_SC_RA_RAM_LOCK__W 4 -#define OFDM_SC_RA_RAM_LOCK__M 0xF -#define OFDM_SC_RA_RAM_LOCK__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_FEC__B 1 -#define OFDM_SC_RA_RAM_LOCK_FEC__W 1 -#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 -#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2 -#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1 -#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 -#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0 - -#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C -#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5 -#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F -#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10 -#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10 - -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16 -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF -#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80 -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF -#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 -#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F -#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 -#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 - -#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 -#define OFDM_SC_RA_RAM_CONFIG__W 16 -#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF -#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14 -#define OFDM_SC_RA_RAM_CONFIG_ID__B 0 -#define OFDM_SC_RA_RAM_CONFIG_ID__W 1 -#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1 -#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 -#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 -#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 -#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 -#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20 -#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 -#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 -#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 -#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 -#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 -#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 -#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0 - -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054 -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF -#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055 -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16 -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056 -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16 -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16 -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059 -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16 -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16 -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16 -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1 -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16 -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16 -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 -#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F -#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16 -#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF -#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16 -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1 -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16 -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320 -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070 -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071 -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072 -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40 -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073 -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074 -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075 -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780 -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076 -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230 -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077 -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16 -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF -#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 -#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C -#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 -#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D -#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C -#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E -#define OFDM_SC_RA_RAM_STATUS__W 16 -#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF -#define OFDM_SC_RA_RAM_STATUS__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16 -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 -#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080 -#define OFDM_SC_RA_RAM_TIMER__W 16 -#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF -#define OFDM_SC_RA_RAM_TIMER__PRE 0x0 -#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081 -#define OFDM_SC_RA_RAM_FI_OFFSET__W 16 -#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF -#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382 -#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082 -#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16 -#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18 -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16 -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF -#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640 -#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E -#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16 -#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF -#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0 -#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F -#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16 -#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF -#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF -#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2 -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16 -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF -#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8 -#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7 -#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16 -#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230 -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8 -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16 -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320 -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9 -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16 -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400 - -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3 -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16 -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6 -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16 -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28 -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6 -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16 -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF -#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14 -#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0 -#define OFDM_SC_RA_RAM_IR_FREQ__W 16 -#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100 -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7 -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8 -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9 -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF -#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16 -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 -#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400 - -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7 -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16 -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF -#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF -#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF -#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16 -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF -#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC -#define OFDM_SC_RA_RAM_BAND__W 16 -#define OFDM_SC_RA_RAM_BAND__M 0xFFFF -#define OFDM_SC_RA_RAM_BAND__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4 -#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF -#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 -#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 -#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0 - -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF -#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16 -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B -#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0 -#define OFDM_SC_RA_RAM_REG_0__W 16 -#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF -#define OFDM_SC_RA_RAM_REG_0__PRE 0x0 -#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1 -#define OFDM_SC_RA_RAM_REG_1__W 16 -#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF -#define OFDM_SC_RA_RAM_REG_1__PRE 0x0 -#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2 -#define OFDM_SC_RA_RAM_BREAK__W 16 -#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF -#define OFDM_SC_RA_RAM_BREAK__PRE 0x0 -#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3 -#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16 -#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF -#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0 -#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4 -#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16 -#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F -#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5 -#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16 -#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6 -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16 -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF -#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1 -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7 -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF -#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F - -#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9 -#define OFDM_SC_RA_RAM_LC_CP__W 16 -#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1 -#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA -#define OFDM_SC_RA_RAM_LC_DIFF__W 16 -#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF -#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7 -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16 -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58 -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16 -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0 - -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16 -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38 -#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE -#define OFDM_SC_RA_RAM_RELOCK__W 16 -#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF -#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0 -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16 -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF -#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148 -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149 -#define OFDM_SC_RA_RAM_NF_PREPOST__W 16 -#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A -#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16 -#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B -#define OFDM_SC_RA_RAM_NF_START__W 16 -#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_START__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C -#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16 -#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D -#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16 -#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F -#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16 -#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16 -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF -#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF -#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF -#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16 -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF -#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0 - - - - - -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_COMM_EXEC__W 2 -#define QAM_COMM_EXEC__M 0x3 -#define QAM_COMM_EXEC__PRE 0x0 -#define QAM_COMM_EXEC_STOP 0x0 -#define QAM_COMM_EXEC_ACTIVE 0x1 -#define QAM_COMM_EXEC_HOLD 0x2 - -#define QAM_COMM_MB__A 0x1400002 -#define QAM_COMM_MB__W 16 -#define QAM_COMM_MB__M 0xFFFF -#define QAM_COMM_MB__PRE 0x0 -#define QAM_COMM_INT_REQ__A 0x1400003 -#define QAM_COMM_INT_REQ__W 16 -#define QAM_COMM_INT_REQ__M 0xFFFF -#define QAM_COMM_INT_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_SL_REQ__B 0 -#define QAM_COMM_INT_REQ_SL_REQ__W 1 -#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 -#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_LC_REQ__B 1 -#define QAM_COMM_INT_REQ_LC_REQ__W 1 -#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 -#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_VD_REQ__B 2 -#define QAM_COMM_INT_REQ_VD_REQ__W 1 -#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 -#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 - -#define QAM_COMM_INT_REQ_SY_REQ__B 3 -#define QAM_COMM_INT_REQ_SY_REQ__W 1 -#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 -#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 - -#define QAM_COMM_INT_STA__A 0x1400005 -#define QAM_COMM_INT_STA__W 16 -#define QAM_COMM_INT_STA__M 0xFFFF -#define QAM_COMM_INT_STA__PRE 0x0 -#define QAM_COMM_INT_MSK__A 0x1400006 -#define QAM_COMM_INT_MSK__W 16 -#define QAM_COMM_INT_MSK__M 0xFFFF -#define QAM_COMM_INT_MSK__PRE 0x0 -#define QAM_COMM_INT_STM__A 0x1400007 -#define QAM_COMM_INT_STM__W 16 -#define QAM_COMM_INT_STM__M 0xFFFF -#define QAM_COMM_INT_STM__PRE 0x0 - - - -#define QAM_TOP_COMM_EXEC__A 0x1410000 -#define QAM_TOP_COMM_EXEC__W 2 -#define QAM_TOP_COMM_EXEC__M 0x3 -#define QAM_TOP_COMM_EXEC__PRE 0x0 -#define QAM_TOP_COMM_EXEC_STOP 0x0 -#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 -#define QAM_TOP_COMM_EXEC_HOLD 0x2 - - -#define QAM_TOP_ANNEX__A 0x1410010 -#define QAM_TOP_ANNEX__W 2 -#define QAM_TOP_ANNEX__M 0x3 -#define QAM_TOP_ANNEX__PRE 0x0 -#define QAM_TOP_ANNEX_A 0x0 -#define QAM_TOP_ANNEX_B 0x1 -#define QAM_TOP_ANNEX_C 0x2 -#define QAM_TOP_ANNEX_D 0x3 - - -#define QAM_TOP_CONSTELLATION__A 0x1410011 -#define QAM_TOP_CONSTELLATION__W 3 -#define QAM_TOP_CONSTELLATION__M 0x7 -#define QAM_TOP_CONSTELLATION__PRE 0x5 -#define QAM_TOP_CONSTELLATION_NONE 0x0 -#define QAM_TOP_CONSTELLATION_QPSK 0x1 -#define QAM_TOP_CONSTELLATION_QAM8 0x2 -#define QAM_TOP_CONSTELLATION_QAM16 0x3 -#define QAM_TOP_CONSTELLATION_QAM32 0x4 -#define QAM_TOP_CONSTELLATION_QAM64 0x5 -#define QAM_TOP_CONSTELLATION_QAM128 0x6 -#define QAM_TOP_CONSTELLATION_QAM256 0x7 - - - -#define QAM_FQ_COMM_EXEC__A 0x1420000 -#define QAM_FQ_COMM_EXEC__W 2 -#define QAM_FQ_COMM_EXEC__M 0x3 -#define QAM_FQ_COMM_EXEC__PRE 0x0 -#define QAM_FQ_COMM_EXEC_STOP 0x0 -#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 -#define QAM_FQ_COMM_EXEC_HOLD 0x2 - -#define QAM_FQ_MODE__A 0x1420010 -#define QAM_FQ_MODE__W 3 -#define QAM_FQ_MODE__M 0x7 -#define QAM_FQ_MODE__PRE 0x0 - -#define QAM_FQ_MODE_TAPRESET__B 0 -#define QAM_FQ_MODE_TAPRESET__W 1 -#define QAM_FQ_MODE_TAPRESET__M 0x1 -#define QAM_FQ_MODE_TAPRESET__PRE 0x0 -#define QAM_FQ_MODE_TAPRESET_RST 0x1 - -#define QAM_FQ_MODE_TAPLMS__B 1 -#define QAM_FQ_MODE_TAPLMS__W 1 -#define QAM_FQ_MODE_TAPLMS__M 0x2 -#define QAM_FQ_MODE_TAPLMS__PRE 0x0 -#define QAM_FQ_MODE_TAPLMS_UPD 0x2 - -#define QAM_FQ_MODE_TAPDRAIN__B 2 -#define QAM_FQ_MODE_TAPDRAIN__W 1 -#define QAM_FQ_MODE_TAPDRAIN__M 0x4 -#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 -#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 - - -#define QAM_FQ_MU_FACTOR__A 0x1420011 -#define QAM_FQ_MU_FACTOR__W 3 -#define QAM_FQ_MU_FACTOR__M 0x7 -#define QAM_FQ_MU_FACTOR__PRE 0x0 - -#define QAM_FQ_LA_FACTOR__A 0x1420012 -#define QAM_FQ_LA_FACTOR__W 4 -#define QAM_FQ_LA_FACTOR__M 0xF -#define QAM_FQ_LA_FACTOR__PRE 0xC -#define QAM_FQ_CENTTAP_IDX__A 0x1420016 -#define QAM_FQ_CENTTAP_IDX__W 5 -#define QAM_FQ_CENTTAP_IDX__M 0x1F -#define QAM_FQ_CENTTAP_IDX__PRE 0x13 - -#define QAM_FQ_CENTTAP_IDX_IDX__B 0 -#define QAM_FQ_CENTTAP_IDX_IDX__W 5 -#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F -#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 - -#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 -#define QAM_FQ_CENTTAP_VALUE__W 12 -#define QAM_FQ_CENTTAP_VALUE__M 0xFFF -#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 - -#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 -#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 -#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF -#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 - -#define QAM_FQ_TAP_RE_EL0__A 0x1420020 -#define QAM_FQ_TAP_RE_EL0__W 12 -#define QAM_FQ_TAP_RE_EL0__M 0xFFF -#define QAM_FQ_TAP_RE_EL0__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL0_TAP__B 0 -#define QAM_FQ_TAP_RE_EL0_TAP__W 12 -#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL0__A 0x1420021 -#define QAM_FQ_TAP_IM_EL0__W 12 -#define QAM_FQ_TAP_IM_EL0__M 0xFFF -#define QAM_FQ_TAP_IM_EL0__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL0_TAP__B 0 -#define QAM_FQ_TAP_IM_EL0_TAP__W 12 -#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL1__A 0x1420022 -#define QAM_FQ_TAP_RE_EL1__W 12 -#define QAM_FQ_TAP_RE_EL1__M 0xFFF -#define QAM_FQ_TAP_RE_EL1__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL1_TAP__B 0 -#define QAM_FQ_TAP_RE_EL1_TAP__W 12 -#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL1__A 0x1420023 -#define QAM_FQ_TAP_IM_EL1__W 12 -#define QAM_FQ_TAP_IM_EL1__M 0xFFF -#define QAM_FQ_TAP_IM_EL1__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL1_TAP__B 0 -#define QAM_FQ_TAP_IM_EL1_TAP__W 12 -#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL2__A 0x1420024 -#define QAM_FQ_TAP_RE_EL2__W 12 -#define QAM_FQ_TAP_RE_EL2__M 0xFFF -#define QAM_FQ_TAP_RE_EL2__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL2_TAP__B 0 -#define QAM_FQ_TAP_RE_EL2_TAP__W 12 -#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL2__A 0x1420025 -#define QAM_FQ_TAP_IM_EL2__W 12 -#define QAM_FQ_TAP_IM_EL2__M 0xFFF -#define QAM_FQ_TAP_IM_EL2__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL2_TAP__B 0 -#define QAM_FQ_TAP_IM_EL2_TAP__W 12 -#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL3__A 0x1420026 -#define QAM_FQ_TAP_RE_EL3__W 12 -#define QAM_FQ_TAP_RE_EL3__M 0xFFF -#define QAM_FQ_TAP_RE_EL3__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL3_TAP__B 0 -#define QAM_FQ_TAP_RE_EL3_TAP__W 12 -#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL3__A 0x1420027 -#define QAM_FQ_TAP_IM_EL3__W 12 -#define QAM_FQ_TAP_IM_EL3__M 0xFFF -#define QAM_FQ_TAP_IM_EL3__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL3_TAP__B 0 -#define QAM_FQ_TAP_IM_EL3_TAP__W 12 -#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL4__A 0x1420028 -#define QAM_FQ_TAP_RE_EL4__W 12 -#define QAM_FQ_TAP_RE_EL4__M 0xFFF -#define QAM_FQ_TAP_RE_EL4__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL4_TAP__B 0 -#define QAM_FQ_TAP_RE_EL4_TAP__W 12 -#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL4__A 0x1420029 -#define QAM_FQ_TAP_IM_EL4__W 12 -#define QAM_FQ_TAP_IM_EL4__M 0xFFF -#define QAM_FQ_TAP_IM_EL4__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL4_TAP__B 0 -#define QAM_FQ_TAP_IM_EL4_TAP__W 12 -#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL5__A 0x142002A -#define QAM_FQ_TAP_RE_EL5__W 12 -#define QAM_FQ_TAP_RE_EL5__M 0xFFF -#define QAM_FQ_TAP_RE_EL5__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL5_TAP__B 0 -#define QAM_FQ_TAP_RE_EL5_TAP__W 12 -#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL5__A 0x142002B -#define QAM_FQ_TAP_IM_EL5__W 12 -#define QAM_FQ_TAP_IM_EL5__M 0xFFF -#define QAM_FQ_TAP_IM_EL5__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL5_TAP__B 0 -#define QAM_FQ_TAP_IM_EL5_TAP__W 12 -#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL6__A 0x142002C -#define QAM_FQ_TAP_RE_EL6__W 12 -#define QAM_FQ_TAP_RE_EL6__M 0xFFF -#define QAM_FQ_TAP_RE_EL6__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL6_TAP__B 0 -#define QAM_FQ_TAP_RE_EL6_TAP__W 12 -#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL6__A 0x142002D -#define QAM_FQ_TAP_IM_EL6__W 12 -#define QAM_FQ_TAP_IM_EL6__M 0xFFF -#define QAM_FQ_TAP_IM_EL6__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL6_TAP__B 0 -#define QAM_FQ_TAP_IM_EL6_TAP__W 12 -#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL7__A 0x142002E -#define QAM_FQ_TAP_RE_EL7__W 12 -#define QAM_FQ_TAP_RE_EL7__M 0xFFF -#define QAM_FQ_TAP_RE_EL7__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL7_TAP__B 0 -#define QAM_FQ_TAP_RE_EL7_TAP__W 12 -#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL7__A 0x142002F -#define QAM_FQ_TAP_IM_EL7__W 12 -#define QAM_FQ_TAP_IM_EL7__M 0xFFF -#define QAM_FQ_TAP_IM_EL7__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL7_TAP__B 0 -#define QAM_FQ_TAP_IM_EL7_TAP__W 12 -#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL8__A 0x1420030 -#define QAM_FQ_TAP_RE_EL8__W 12 -#define QAM_FQ_TAP_RE_EL8__M 0xFFF -#define QAM_FQ_TAP_RE_EL8__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL8_TAP__B 0 -#define QAM_FQ_TAP_RE_EL8_TAP__W 12 -#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL8__A 0x1420031 -#define QAM_FQ_TAP_IM_EL8__W 12 -#define QAM_FQ_TAP_IM_EL8__M 0xFFF -#define QAM_FQ_TAP_IM_EL8__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL8_TAP__B 0 -#define QAM_FQ_TAP_IM_EL8_TAP__W 12 -#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL9__A 0x1420032 -#define QAM_FQ_TAP_RE_EL9__W 12 -#define QAM_FQ_TAP_RE_EL9__M 0xFFF -#define QAM_FQ_TAP_RE_EL9__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL9_TAP__B 0 -#define QAM_FQ_TAP_RE_EL9_TAP__W 12 -#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL9__A 0x1420033 -#define QAM_FQ_TAP_IM_EL9__W 12 -#define QAM_FQ_TAP_IM_EL9__M 0xFFF -#define QAM_FQ_TAP_IM_EL9__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL9_TAP__B 0 -#define QAM_FQ_TAP_IM_EL9_TAP__W 12 -#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL10__A 0x1420034 -#define QAM_FQ_TAP_RE_EL10__W 12 -#define QAM_FQ_TAP_RE_EL10__M 0xFFF -#define QAM_FQ_TAP_RE_EL10__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL10_TAP__B 0 -#define QAM_FQ_TAP_RE_EL10_TAP__W 12 -#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL10__A 0x1420035 -#define QAM_FQ_TAP_IM_EL10__W 12 -#define QAM_FQ_TAP_IM_EL10__M 0xFFF -#define QAM_FQ_TAP_IM_EL10__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL10_TAP__B 0 -#define QAM_FQ_TAP_IM_EL10_TAP__W 12 -#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL11__A 0x1420036 -#define QAM_FQ_TAP_RE_EL11__W 12 -#define QAM_FQ_TAP_RE_EL11__M 0xFFF -#define QAM_FQ_TAP_RE_EL11__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL11_TAP__B 0 -#define QAM_FQ_TAP_RE_EL11_TAP__W 12 -#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL11__A 0x1420037 -#define QAM_FQ_TAP_IM_EL11__W 12 -#define QAM_FQ_TAP_IM_EL11__M 0xFFF -#define QAM_FQ_TAP_IM_EL11__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL11_TAP__B 0 -#define QAM_FQ_TAP_IM_EL11_TAP__W 12 -#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL12__A 0x1420038 -#define QAM_FQ_TAP_RE_EL12__W 12 -#define QAM_FQ_TAP_RE_EL12__M 0xFFF -#define QAM_FQ_TAP_RE_EL12__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL12_TAP__B 0 -#define QAM_FQ_TAP_RE_EL12_TAP__W 12 -#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL12__A 0x1420039 -#define QAM_FQ_TAP_IM_EL12__W 12 -#define QAM_FQ_TAP_IM_EL12__M 0xFFF -#define QAM_FQ_TAP_IM_EL12__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL12_TAP__B 0 -#define QAM_FQ_TAP_IM_EL12_TAP__W 12 -#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL13__A 0x142003A -#define QAM_FQ_TAP_RE_EL13__W 12 -#define QAM_FQ_TAP_RE_EL13__M 0xFFF -#define QAM_FQ_TAP_RE_EL13__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL13_TAP__B 0 -#define QAM_FQ_TAP_RE_EL13_TAP__W 12 -#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL13__A 0x142003B -#define QAM_FQ_TAP_IM_EL13__W 12 -#define QAM_FQ_TAP_IM_EL13__M 0xFFF -#define QAM_FQ_TAP_IM_EL13__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL13_TAP__B 0 -#define QAM_FQ_TAP_IM_EL13_TAP__W 12 -#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL14__A 0x142003C -#define QAM_FQ_TAP_RE_EL14__W 12 -#define QAM_FQ_TAP_RE_EL14__M 0xFFF -#define QAM_FQ_TAP_RE_EL14__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL14_TAP__B 0 -#define QAM_FQ_TAP_RE_EL14_TAP__W 12 -#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL14__A 0x142003D -#define QAM_FQ_TAP_IM_EL14__W 12 -#define QAM_FQ_TAP_IM_EL14__M 0xFFF -#define QAM_FQ_TAP_IM_EL14__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL14_TAP__B 0 -#define QAM_FQ_TAP_IM_EL14_TAP__W 12 -#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL15__A 0x142003E -#define QAM_FQ_TAP_RE_EL15__W 12 -#define QAM_FQ_TAP_RE_EL15__M 0xFFF -#define QAM_FQ_TAP_RE_EL15__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL15_TAP__B 0 -#define QAM_FQ_TAP_RE_EL15_TAP__W 12 -#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL15__A 0x142003F -#define QAM_FQ_TAP_IM_EL15__W 12 -#define QAM_FQ_TAP_IM_EL15__M 0xFFF -#define QAM_FQ_TAP_IM_EL15__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL15_TAP__B 0 -#define QAM_FQ_TAP_IM_EL15_TAP__W 12 -#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL16__A 0x1420040 -#define QAM_FQ_TAP_RE_EL16__W 12 -#define QAM_FQ_TAP_RE_EL16__M 0xFFF -#define QAM_FQ_TAP_RE_EL16__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL16_TAP__B 0 -#define QAM_FQ_TAP_RE_EL16_TAP__W 12 -#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL16__A 0x1420041 -#define QAM_FQ_TAP_IM_EL16__W 12 -#define QAM_FQ_TAP_IM_EL16__M 0xFFF -#define QAM_FQ_TAP_IM_EL16__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL16_TAP__B 0 -#define QAM_FQ_TAP_IM_EL16_TAP__W 12 -#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL17__A 0x1420042 -#define QAM_FQ_TAP_RE_EL17__W 12 -#define QAM_FQ_TAP_RE_EL17__M 0xFFF -#define QAM_FQ_TAP_RE_EL17__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL17_TAP__B 0 -#define QAM_FQ_TAP_RE_EL17_TAP__W 12 -#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL17__A 0x1420043 -#define QAM_FQ_TAP_IM_EL17__W 12 -#define QAM_FQ_TAP_IM_EL17__M 0xFFF -#define QAM_FQ_TAP_IM_EL17__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL17_TAP__B 0 -#define QAM_FQ_TAP_IM_EL17_TAP__W 12 -#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL18__A 0x1420044 -#define QAM_FQ_TAP_RE_EL18__W 12 -#define QAM_FQ_TAP_RE_EL18__M 0xFFF -#define QAM_FQ_TAP_RE_EL18__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL18_TAP__B 0 -#define QAM_FQ_TAP_RE_EL18_TAP__W 12 -#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL18__A 0x1420045 -#define QAM_FQ_TAP_IM_EL18__W 12 -#define QAM_FQ_TAP_IM_EL18__M 0xFFF -#define QAM_FQ_TAP_IM_EL18__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL18_TAP__B 0 -#define QAM_FQ_TAP_IM_EL18_TAP__W 12 -#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL19__A 0x1420046 -#define QAM_FQ_TAP_RE_EL19__W 12 -#define QAM_FQ_TAP_RE_EL19__M 0xFFF -#define QAM_FQ_TAP_RE_EL19__PRE 0x600 - -#define QAM_FQ_TAP_RE_EL19_TAP__B 0 -#define QAM_FQ_TAP_RE_EL19_TAP__W 12 -#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 - -#define QAM_FQ_TAP_IM_EL19__A 0x1420047 -#define QAM_FQ_TAP_IM_EL19__W 12 -#define QAM_FQ_TAP_IM_EL19__M 0xFFF -#define QAM_FQ_TAP_IM_EL19__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL19_TAP__B 0 -#define QAM_FQ_TAP_IM_EL19_TAP__W 12 -#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL20__A 0x1420048 -#define QAM_FQ_TAP_RE_EL20__W 12 -#define QAM_FQ_TAP_RE_EL20__M 0xFFF -#define QAM_FQ_TAP_RE_EL20__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL20_TAP__B 0 -#define QAM_FQ_TAP_RE_EL20_TAP__W 12 -#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL20__A 0x1420049 -#define QAM_FQ_TAP_IM_EL20__W 12 -#define QAM_FQ_TAP_IM_EL20__M 0xFFF -#define QAM_FQ_TAP_IM_EL20__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL20_TAP__B 0 -#define QAM_FQ_TAP_IM_EL20_TAP__W 12 -#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL21__A 0x142004A -#define QAM_FQ_TAP_RE_EL21__W 12 -#define QAM_FQ_TAP_RE_EL21__M 0xFFF -#define QAM_FQ_TAP_RE_EL21__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL21_TAP__B 0 -#define QAM_FQ_TAP_RE_EL21_TAP__W 12 -#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL21__A 0x142004B -#define QAM_FQ_TAP_IM_EL21__W 12 -#define QAM_FQ_TAP_IM_EL21__M 0xFFF -#define QAM_FQ_TAP_IM_EL21__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL21_TAP__B 0 -#define QAM_FQ_TAP_IM_EL21_TAP__W 12 -#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL22__A 0x142004C -#define QAM_FQ_TAP_RE_EL22__W 12 -#define QAM_FQ_TAP_RE_EL22__M 0xFFF -#define QAM_FQ_TAP_RE_EL22__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL22_TAP__B 0 -#define QAM_FQ_TAP_RE_EL22_TAP__W 12 -#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL22__A 0x142004D -#define QAM_FQ_TAP_IM_EL22__W 12 -#define QAM_FQ_TAP_IM_EL22__M 0xFFF -#define QAM_FQ_TAP_IM_EL22__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL22_TAP__B 0 -#define QAM_FQ_TAP_IM_EL22_TAP__W 12 -#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL23__A 0x142004E -#define QAM_FQ_TAP_RE_EL23__W 12 -#define QAM_FQ_TAP_RE_EL23__M 0xFFF -#define QAM_FQ_TAP_RE_EL23__PRE 0x2 - -#define QAM_FQ_TAP_RE_EL23_TAP__B 0 -#define QAM_FQ_TAP_RE_EL23_TAP__W 12 -#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF -#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL23__A 0x142004F -#define QAM_FQ_TAP_IM_EL23__W 12 -#define QAM_FQ_TAP_IM_EL23__M 0xFFF -#define QAM_FQ_TAP_IM_EL23__PRE 0x2 - -#define QAM_FQ_TAP_IM_EL23_TAP__B 0 -#define QAM_FQ_TAP_IM_EL23_TAP__W 12 -#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF -#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 - - - -#define QAM_SL_COMM_EXEC__A 0x1430000 -#define QAM_SL_COMM_EXEC__W 2 -#define QAM_SL_COMM_EXEC__M 0x3 -#define QAM_SL_COMM_EXEC__PRE 0x0 -#define QAM_SL_COMM_EXEC_STOP 0x0 -#define QAM_SL_COMM_EXEC_ACTIVE 0x1 -#define QAM_SL_COMM_EXEC_HOLD 0x2 - -#define QAM_SL_COMM_MB__A 0x1430002 -#define QAM_SL_COMM_MB__W 4 -#define QAM_SL_COMM_MB__M 0xF -#define QAM_SL_COMM_MB__PRE 0x0 -#define QAM_SL_COMM_MB_CTL__B 0 -#define QAM_SL_COMM_MB_CTL__W 1 -#define QAM_SL_COMM_MB_CTL__M 0x1 -#define QAM_SL_COMM_MB_CTL__PRE 0x0 -#define QAM_SL_COMM_MB_CTL_OFF 0x0 -#define QAM_SL_COMM_MB_CTL_ON 0x1 -#define QAM_SL_COMM_MB_OBS__B 1 -#define QAM_SL_COMM_MB_OBS__W 1 -#define QAM_SL_COMM_MB_OBS__M 0x2 -#define QAM_SL_COMM_MB_OBS__PRE 0x0 -#define QAM_SL_COMM_MB_OBS_OFF 0x0 -#define QAM_SL_COMM_MB_OBS_ON 0x2 -#define QAM_SL_COMM_MB_MUX_OBS__B 2 -#define QAM_SL_COMM_MB_MUX_OBS__W 2 -#define QAM_SL_COMM_MB_MUX_OBS__M 0xC -#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 -#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 -#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 -#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 -#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC - -#define QAM_SL_COMM_INT_REQ__A 0x1430003 -#define QAM_SL_COMM_INT_REQ__W 1 -#define QAM_SL_COMM_INT_REQ__M 0x1 -#define QAM_SL_COMM_INT_REQ__PRE 0x0 -#define QAM_SL_COMM_INT_STA__A 0x1430005 -#define QAM_SL_COMM_INT_STA__W 2 -#define QAM_SL_COMM_INT_STA__M 0x3 -#define QAM_SL_COMM_INT_STA__PRE 0x0 - -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 -#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 - -#define QAM_SL_COMM_INT_STA_MER_INT__B 1 -#define QAM_SL_COMM_INT_STA_MER_INT__W 1 -#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 -#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 - -#define QAM_SL_COMM_INT_MSK__A 0x1430006 -#define QAM_SL_COMM_INT_MSK__W 2 -#define QAM_SL_COMM_INT_MSK__M 0x3 -#define QAM_SL_COMM_INT_MSK__PRE 0x0 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 -#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 -#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 -#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 -#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 -#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 - -#define QAM_SL_COMM_INT_STM__A 0x1430007 -#define QAM_SL_COMM_INT_STM__W 2 -#define QAM_SL_COMM_INT_STM__M 0x3 -#define QAM_SL_COMM_INT_STM__PRE 0x0 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 -#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 -#define QAM_SL_COMM_INT_STM_MER_STM__B 1 -#define QAM_SL_COMM_INT_STM_MER_STM__W 1 -#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 -#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 - -#define QAM_SL_MODE__A 0x1430010 -#define QAM_SL_MODE__W 11 -#define QAM_SL_MODE__M 0x7FF -#define QAM_SL_MODE__PRE 0xA - -#define QAM_SL_MODE_SLICER4LC__B 0 -#define QAM_SL_MODE_SLICER4LC__W 2 -#define QAM_SL_MODE_SLICER4LC__M 0x3 -#define QAM_SL_MODE_SLICER4LC__PRE 0x2 -#define QAM_SL_MODE_SLICER4LC_RECT 0x0 -#define QAM_SL_MODE_SLICER4LC_ONET 0x1 -#define QAM_SL_MODE_SLICER4LC_RAD 0x2 - -#define QAM_SL_MODE_SLICER4DQ__B 2 -#define QAM_SL_MODE_SLICER4DQ__W 2 -#define QAM_SL_MODE_SLICER4DQ__M 0xC -#define QAM_SL_MODE_SLICER4DQ__PRE 0x8 -#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 -#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 -#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 - -#define QAM_SL_MODE_SLICER4VD__B 4 -#define QAM_SL_MODE_SLICER4VD__W 2 -#define QAM_SL_MODE_SLICER4VD__M 0x30 -#define QAM_SL_MODE_SLICER4VD__PRE 0x0 -#define QAM_SL_MODE_SLICER4VD_RECT 0x0 -#define QAM_SL_MODE_SLICER4VD_ONET 0x10 -#define QAM_SL_MODE_SLICER4VD_RAD 0x20 - -#define QAM_SL_MODE_ROT_DIS__B 6 -#define QAM_SL_MODE_ROT_DIS__W 1 -#define QAM_SL_MODE_ROT_DIS__M 0x40 -#define QAM_SL_MODE_ROT_DIS__PRE 0x0 -#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0 -#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40 - -#define QAM_SL_MODE_DQROT_DIS__B 7 -#define QAM_SL_MODE_DQROT_DIS__W 1 -#define QAM_SL_MODE_DQROT_DIS__M 0x80 -#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 -#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0 -#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80 - -#define QAM_SL_MODE_DFE_DIS__B 8 -#define QAM_SL_MODE_DFE_DIS__W 1 -#define QAM_SL_MODE_DFE_DIS__M 0x100 -#define QAM_SL_MODE_DFE_DIS__PRE 0x0 -#define QAM_SL_MODE_DFE_DIS_DQ 0x0 -#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100 - -#define QAM_SL_MODE_RADIUS_MIX__B 9 -#define QAM_SL_MODE_RADIUS_MIX__W 1 -#define QAM_SL_MODE_RADIUS_MIX__M 0x200 -#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 -#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0 -#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200 - -#define QAM_SL_MODE_TILT_COMP__B 10 -#define QAM_SL_MODE_TILT_COMP__W 1 -#define QAM_SL_MODE_TILT_COMP__M 0x400 -#define QAM_SL_MODE_TILT_COMP__PRE 0x0 -#define QAM_SL_MODE_TILT_COMP_OFF 0x0 -#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400 - - -#define QAM_SL_K_FACTOR__A 0x1430011 -#define QAM_SL_K_FACTOR__W 4 -#define QAM_SL_K_FACTOR__M 0xF -#define QAM_SL_K_FACTOR__PRE 0xC -#define QAM_SL_MEDIAN__A 0x1430012 -#define QAM_SL_MEDIAN__W 14 -#define QAM_SL_MEDIAN__M 0x3FFF -#define QAM_SL_MEDIAN__PRE 0x2C86 - -#define QAM_SL_MEDIAN_LENGTH__B 0 -#define QAM_SL_MEDIAN_LENGTH__W 2 -#define QAM_SL_MEDIAN_LENGTH__M 0x3 -#define QAM_SL_MEDIAN_LENGTH__PRE 0x2 -#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0 -#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1 -#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2 -#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3 - -#define QAM_SL_MEDIAN_CORRECT__B 2 -#define QAM_SL_MEDIAN_CORRECT__W 4 -#define QAM_SL_MEDIAN_CORRECT__M 0x3C -#define QAM_SL_MEDIAN_CORRECT__PRE 0x4 - -#define QAM_SL_MEDIAN_TOLERANCE__B 6 -#define QAM_SL_MEDIAN_TOLERANCE__W 7 -#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 -#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80 - -#define QAM_SL_MEDIAN_FAST__B 13 -#define QAM_SL_MEDIAN_FAST__W 1 -#define QAM_SL_MEDIAN_FAST__M 0x2000 -#define QAM_SL_MEDIAN_FAST__PRE 0x2000 -#define QAM_SL_MEDIAN_FAST_AVER 0x0 -#define QAM_SL_MEDIAN_FAST_LAST 0x2000 - - -#define QAM_SL_ALPHA__A 0x1430013 -#define QAM_SL_ALPHA__W 3 -#define QAM_SL_ALPHA__M 0x7 -#define QAM_SL_ALPHA__PRE 0x0 - -#define QAM_SL_PHASELIMIT__A 0x1430014 -#define QAM_SL_PHASELIMIT__W 9 -#define QAM_SL_PHASELIMIT__M 0x1FF -#define QAM_SL_PHASELIMIT__PRE 0x0 -#define QAM_SL_MTA_LENGTH__A 0x1430015 -#define QAM_SL_MTA_LENGTH__W 2 -#define QAM_SL_MTA_LENGTH__M 0x3 -#define QAM_SL_MTA_LENGTH__PRE 0x1 - -#define QAM_SL_MTA_LENGTH_LENGTH__B 0 -#define QAM_SL_MTA_LENGTH_LENGTH__W 2 -#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 -#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 - -#define QAM_SL_MEDIAN_ERROR__A 0x1430016 -#define QAM_SL_MEDIAN_ERROR__W 10 -#define QAM_SL_MEDIAN_ERROR__M 0x3FF -#define QAM_SL_MEDIAN_ERROR__PRE 0x0 - -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF -#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 - - -#define QAM_SL_ERR_POWER__A 0x1430017 -#define QAM_SL_ERR_POWER__W 16 -#define QAM_SL_ERR_POWER__M 0xFFFF -#define QAM_SL_ERR_POWER__PRE 0x0 -#define QAM_SL_QUAL_QAM_4_0__A 0x1430018 -#define QAM_SL_QUAL_QAM_4_0__W 3 -#define QAM_SL_QUAL_QAM_4_0__M 0x7 -#define QAM_SL_QUAL_QAM_4_0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_4_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_4_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_8_0__A 0x1430019 -#define QAM_SL_QUAL_QAM_8_0__W 6 -#define QAM_SL_QUAL_QAM_8_0__M 0x3F -#define QAM_SL_QUAL_QAM_8_0__PRE 0xD - -#define QAM_SL_QUAL_QAM_8_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_8_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_8_0_Q1__B 3 -#define QAM_SL_QUAL_QAM_8_0_Q1__W 3 -#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_16_0__A 0x143001A -#define QAM_SL_QUAL_QAM_16_0__W 3 -#define QAM_SL_QUAL_QAM_16_0__M 0x7 -#define QAM_SL_QUAL_QAM_16_0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_16_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_16_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_16_1__A 0x143001B -#define QAM_SL_QUAL_QAM_16_1__W 6 -#define QAM_SL_QUAL_QAM_16_1__M 0x3F -#define QAM_SL_QUAL_QAM_16_1__PRE 0x5 - -#define QAM_SL_QUAL_QAM_16_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_16_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_16_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_16_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_0__A 0x143001C -#define QAM_SL_QUAL_QAM_32_0__W 3 -#define QAM_SL_QUAL_QAM_32_0__M 0x7 -#define QAM_SL_QUAL_QAM_32_0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_32_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_32_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_32_1__A 0x143001D -#define QAM_SL_QUAL_QAM_32_1__W 6 -#define QAM_SL_QUAL_QAM_32_1__M 0x3F -#define QAM_SL_QUAL_QAM_32_1__PRE 0x3 - -#define QAM_SL_QUAL_QAM_32_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_32_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_32_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_32_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2__A 0x143001E -#define QAM_SL_QUAL_QAM_32_2__W 9 -#define QAM_SL_QUAL_QAM_32_2__M 0x1FF -#define QAM_SL_QUAL_QAM_32_2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_32_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_32_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_32_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_32_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_0__A 0x143001F -#define QAM_SL_QUAL_QAM_64_0__W 3 -#define QAM_SL_QUAL_QAM_64_0__M 0x7 -#define QAM_SL_QUAL_QAM_64_0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_64_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_64_1__A 0x1430020 -#define QAM_SL_QUAL_QAM_64_1__W 6 -#define QAM_SL_QUAL_QAM_64_1__M 0x3F -#define QAM_SL_QUAL_QAM_64_1__PRE 0x2 - -#define QAM_SL_QUAL_QAM_64_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2 - -#define QAM_SL_QUAL_QAM_64_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_64_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_2__A 0x1430021 -#define QAM_SL_QUAL_QAM_64_2__W 9 -#define QAM_SL_QUAL_QAM_64_2__M 0x1FF -#define QAM_SL_QUAL_QAM_64_2__PRE 0x9 - -#define QAM_SL_QUAL_QAM_64_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_64_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_64_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_64_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_64_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_3__A 0x1430022 -#define QAM_SL_QUAL_QAM_64_3__W 12 -#define QAM_SL_QUAL_QAM_64_3__M 0xFFF -#define QAM_SL_QUAL_QAM_64_3__PRE 0xD - -#define QAM_SL_QUAL_QAM_64_3_Q0__B 0 -#define QAM_SL_QUAL_QAM_64_3_Q0__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_64_3_Q1__B 3 -#define QAM_SL_QUAL_QAM_64_3_Q1__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_64_3_Q2__B 6 -#define QAM_SL_QUAL_QAM_64_3_Q2__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_64_3_Q3__B 9 -#define QAM_SL_QUAL_QAM_64_3_Q3__W 3 -#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_0__A 0x1430023 -#define QAM_SL_QUAL_QAM_128_0__W 3 -#define QAM_SL_QUAL_QAM_128_0__M 0x7 -#define QAM_SL_QUAL_QAM_128_0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_128_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4 - -#define QAM_SL_QUAL_QAM_128_1__A 0x1430024 -#define QAM_SL_QUAL_QAM_128_1__W 6 -#define QAM_SL_QUAL_QAM_128_1__M 0x3F -#define QAM_SL_QUAL_QAM_128_1__PRE 0x5 - -#define QAM_SL_QUAL_QAM_128_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_128_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_2__A 0x1430025 -#define QAM_SL_QUAL_QAM_128_2__W 9 -#define QAM_SL_QUAL_QAM_128_2__M 0x1FF -#define QAM_SL_QUAL_QAM_128_2__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_3__A 0x1430026 -#define QAM_SL_QUAL_QAM_128_3__W 12 -#define QAM_SL_QUAL_QAM_128_3__M 0xFFF -#define QAM_SL_QUAL_QAM_128_3__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_3_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_3_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_128_3_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_3_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_3_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_3_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_3_Q3__B 9 -#define QAM_SL_QUAL_QAM_128_3_Q3__W 3 -#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4__A 0x1430027 -#define QAM_SL_QUAL_QAM_128_4__W 15 -#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF -#define QAM_SL_QUAL_QAM_128_4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_4_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_4_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_4_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q3__B 9 -#define QAM_SL_QUAL_QAM_128_4_Q3__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_4_Q4__B 12 -#define QAM_SL_QUAL_QAM_128_4_Q4__W 3 -#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5__A 0x1430028 -#define QAM_SL_QUAL_QAM_128_5__W 15 -#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF -#define QAM_SL_QUAL_QAM_128_5__PRE 0x90 - -#define QAM_SL_QUAL_QAM_128_5_Q0__B 0 -#define QAM_SL_QUAL_QAM_128_5_Q0__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5_Q1__B 3 -#define QAM_SL_QUAL_QAM_128_5_Q1__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10 - -#define QAM_SL_QUAL_QAM_128_5_Q2__B 6 -#define QAM_SL_QUAL_QAM_128_5_Q2__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80 - -#define QAM_SL_QUAL_QAM_128_5_Q3__B 9 -#define QAM_SL_QUAL_QAM_128_5_Q3__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5_Q4__B 12 -#define QAM_SL_QUAL_QAM_128_5_Q4__W 3 -#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029 -#define QAM_SL_QUAL_QAM_128_5H__W 3 -#define QAM_SL_QUAL_QAM_128_5H__M 0x7 -#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0 -#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3 -#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_0__A 0x143002A -#define QAM_SL_QUAL_QAM_256_0__W 3 -#define QAM_SL_QUAL_QAM_256_0__M 0x7 -#define QAM_SL_QUAL_QAM_256_0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_256_0_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_0_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_256_1__A 0x143002B -#define QAM_SL_QUAL_QAM_256_1__W 6 -#define QAM_SL_QUAL_QAM_256_1__M 0x3F -#define QAM_SL_QUAL_QAM_256_1__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_1_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_1_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_1_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_1_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_2__A 0x143002C -#define QAM_SL_QUAL_QAM_256_2__W 9 -#define QAM_SL_QUAL_QAM_256_2__M 0x1FF -#define QAM_SL_QUAL_QAM_256_2__PRE 0x9 - -#define QAM_SL_QUAL_QAM_256_2_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_2_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_2_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_2_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_256_2_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_2_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_3__A 0x143002D -#define QAM_SL_QUAL_QAM_256_3__W 12 -#define QAM_SL_QUAL_QAM_256_3__M 0xFFF -#define QAM_SL_QUAL_QAM_256_3__PRE 0x13 - -#define QAM_SL_QUAL_QAM_256_3_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_3_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3 - -#define QAM_SL_QUAL_QAM_256_3_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_3_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10 - -#define QAM_SL_QUAL_QAM_256_3_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_3_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_3_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_3_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_4__A 0x143002E -#define QAM_SL_QUAL_QAM_256_4__W 15 -#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_4__PRE 0x49 - -#define QAM_SL_QUAL_QAM_256_4_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_4_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_4_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_4_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8 - -#define QAM_SL_QUAL_QAM_256_4_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_4_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40 - -#define QAM_SL_QUAL_QAM_256_4_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_4_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_4_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_4_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5__A 0x143002F -#define QAM_SL_QUAL_QAM_256_5__W 15 -#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_5__PRE 0x59 - -#define QAM_SL_QUAL_QAM_256_5_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_5_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1 - -#define QAM_SL_QUAL_QAM_256_5_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_5_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18 - -#define QAM_SL_QUAL_QAM_256_5_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_5_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40 - -#define QAM_SL_QUAL_QAM_256_5_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_5_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_5_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030 -#define QAM_SL_QUAL_QAM_256_5H__W 3 -#define QAM_SL_QUAL_QAM_256_5H__M 0x7 -#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0 -#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3 -#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6__A 0x1430031 -#define QAM_SL_QUAL_QAM_256_6__W 15 -#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A - -#define QAM_SL_QUAL_QAM_256_6_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_6_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2 - -#define QAM_SL_QUAL_QAM_256_6_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_6_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18 - -#define QAM_SL_QUAL_QAM_256_6_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_6_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_6_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200 - -#define QAM_SL_QUAL_QAM_256_6_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_6_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032 -#define QAM_SL_QUAL_QAM_256_6H__W 6 -#define QAM_SL_QUAL_QAM_256_6H__M 0x3F -#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0 -#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3 -#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3 -#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3 -#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38 -#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7__A 0x1430033 -#define QAM_SL_QUAL_QAM_256_7__W 15 -#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF -#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D - -#define QAM_SL_QUAL_QAM_256_7_Q0__B 0 -#define QAM_SL_QUAL_QAM_256_7_Q0__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7 -#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5 - -#define QAM_SL_QUAL_QAM_256_7_Q1__B 3 -#define QAM_SL_QUAL_QAM_256_7_Q1__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38 -#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18 - -#define QAM_SL_QUAL_QAM_256_7_Q2__B 6 -#define QAM_SL_QUAL_QAM_256_7_Q2__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80 - -#define QAM_SL_QUAL_QAM_256_7_Q3__B 9 -#define QAM_SL_QUAL_QAM_256_7_Q3__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00 -#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200 - -#define QAM_SL_QUAL_QAM_256_7_Q4__B 12 -#define QAM_SL_QUAL_QAM_256_7_Q4__W 3 -#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000 -#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034 -#define QAM_SL_QUAL_QAM_256_7H__W 9 -#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF -#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0 -#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3 -#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7 -#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3 -#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3 -#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38 -#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0 - -#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6 -#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3 -#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0 -#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0 - - - -#define QAM_DQ_COMM_EXEC__A 0x1440000 -#define QAM_DQ_COMM_EXEC__W 2 -#define QAM_DQ_COMM_EXEC__M 0x3 -#define QAM_DQ_COMM_EXEC__PRE 0x0 -#define QAM_DQ_COMM_EXEC_STOP 0x0 -#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 -#define QAM_DQ_COMM_EXEC_HOLD 0x2 - -#define QAM_DQ_MODE__A 0x1440010 -#define QAM_DQ_MODE__W 5 -#define QAM_DQ_MODE__M 0x1F -#define QAM_DQ_MODE__PRE 0x0 - -#define QAM_DQ_MODE_TAPRESET__B 0 -#define QAM_DQ_MODE_TAPRESET__W 1 -#define QAM_DQ_MODE_TAPRESET__M 0x1 -#define QAM_DQ_MODE_TAPRESET__PRE 0x0 -#define QAM_DQ_MODE_TAPRESET_RST 0x1 - -#define QAM_DQ_MODE_TAPLMS__B 1 -#define QAM_DQ_MODE_TAPLMS__W 1 -#define QAM_DQ_MODE_TAPLMS__M 0x2 -#define QAM_DQ_MODE_TAPLMS__PRE 0x0 -#define QAM_DQ_MODE_TAPLMS_UPD 0x2 - -#define QAM_DQ_MODE_TAPDRAIN__B 2 -#define QAM_DQ_MODE_TAPDRAIN__W 1 -#define QAM_DQ_MODE_TAPDRAIN__M 0x4 -#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 -#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 - -#define QAM_DQ_MODE_FB__B 3 -#define QAM_DQ_MODE_FB__W 2 -#define QAM_DQ_MODE_FB__M 0x18 -#define QAM_DQ_MODE_FB__PRE 0x0 -#define QAM_DQ_MODE_FB_CMA 0x0 -#define QAM_DQ_MODE_FB_RADIUS 0x8 -#define QAM_DQ_MODE_FB_DFB 0x10 -#define QAM_DQ_MODE_FB_TRELLIS 0x18 - - -#define QAM_DQ_MU_FACTOR__A 0x1440011 -#define QAM_DQ_MU_FACTOR__W 3 -#define QAM_DQ_MU_FACTOR__M 0x7 -#define QAM_DQ_MU_FACTOR__PRE 0x0 - -#define QAM_DQ_LA_FACTOR__A 0x1440012 -#define QAM_DQ_LA_FACTOR__W 4 -#define QAM_DQ_LA_FACTOR__M 0xF -#define QAM_DQ_LA_FACTOR__PRE 0xC - -#define QAM_DQ_CMA_RATIO__A 0x1440013 -#define QAM_DQ_CMA_RATIO__W 14 -#define QAM_DQ_CMA_RATIO__M 0x3FFF -#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 -#define QAM_DQ_CMA_RATIO_QPSK 0x2000 -#define QAM_DQ_CMA_RATIO_QAM16 0x34CD -#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 -#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D -#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 - -#define QAM_DQ_QUAL_RADSEL__A 0x1440014 -#define QAM_DQ_QUAL_RADSEL__W 3 -#define QAM_DQ_QUAL_RADSEL__M 0x7 -#define QAM_DQ_QUAL_RADSEL__PRE 0x0 - -#define QAM_DQ_QUAL_RADSEL_BIT__B 0 -#define QAM_DQ_QUAL_RADSEL_BIT__W 3 -#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 -#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 -#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 -#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 - -#define QAM_DQ_QUAL_ENA__A 0x1440015 -#define QAM_DQ_QUAL_ENA__W 1 -#define QAM_DQ_QUAL_ENA__M 0x1 -#define QAM_DQ_QUAL_ENA__PRE 0x0 - -#define QAM_DQ_QUAL_ENA_ENA__B 0 -#define QAM_DQ_QUAL_ENA_ENA__W 1 -#define QAM_DQ_QUAL_ENA_ENA__M 0x1 -#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 -#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 - -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__PRE 0x4 - -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__PRE 0x4 - -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__PRE 0x4 - -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__PRE 0x4 - -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 - -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__PRE 0x6 - -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 - -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__PRE 0x6 - -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 - -#define QAM_DQ_RAW_LIM__A 0x144001E -#define QAM_DQ_RAW_LIM__W 5 -#define QAM_DQ_RAW_LIM__M 0x1F -#define QAM_DQ_RAW_LIM__PRE 0x1F - -#define QAM_DQ_RAW_LIM_BIT__B 0 -#define QAM_DQ_RAW_LIM_BIT__W 5 -#define QAM_DQ_RAW_LIM_BIT__M 0x1F -#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F - -#define QAM_DQ_TAP_RE_EL0__A 0x1440020 -#define QAM_DQ_TAP_RE_EL0__W 12 -#define QAM_DQ_TAP_RE_EL0__M 0xFFF -#define QAM_DQ_TAP_RE_EL0__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL0_TAP__B 0 -#define QAM_DQ_TAP_RE_EL0_TAP__W 12 -#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL0__A 0x1440021 -#define QAM_DQ_TAP_IM_EL0__W 12 -#define QAM_DQ_TAP_IM_EL0__M 0xFFF -#define QAM_DQ_TAP_IM_EL0__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL0_TAP__B 0 -#define QAM_DQ_TAP_IM_EL0_TAP__W 12 -#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL1__A 0x1440022 -#define QAM_DQ_TAP_RE_EL1__W 12 -#define QAM_DQ_TAP_RE_EL1__M 0xFFF -#define QAM_DQ_TAP_RE_EL1__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL1_TAP__B 0 -#define QAM_DQ_TAP_RE_EL1_TAP__W 12 -#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL1__A 0x1440023 -#define QAM_DQ_TAP_IM_EL1__W 12 -#define QAM_DQ_TAP_IM_EL1__M 0xFFF -#define QAM_DQ_TAP_IM_EL1__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL1_TAP__B 0 -#define QAM_DQ_TAP_IM_EL1_TAP__W 12 -#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL2__A 0x1440024 -#define QAM_DQ_TAP_RE_EL2__W 12 -#define QAM_DQ_TAP_RE_EL2__M 0xFFF -#define QAM_DQ_TAP_RE_EL2__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL2_TAP__B 0 -#define QAM_DQ_TAP_RE_EL2_TAP__W 12 -#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL2__A 0x1440025 -#define QAM_DQ_TAP_IM_EL2__W 12 -#define QAM_DQ_TAP_IM_EL2__M 0xFFF -#define QAM_DQ_TAP_IM_EL2__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL2_TAP__B 0 -#define QAM_DQ_TAP_IM_EL2_TAP__W 12 -#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL3__A 0x1440026 -#define QAM_DQ_TAP_RE_EL3__W 12 -#define QAM_DQ_TAP_RE_EL3__M 0xFFF -#define QAM_DQ_TAP_RE_EL3__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL3_TAP__B 0 -#define QAM_DQ_TAP_RE_EL3_TAP__W 12 -#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL3__A 0x1440027 -#define QAM_DQ_TAP_IM_EL3__W 12 -#define QAM_DQ_TAP_IM_EL3__M 0xFFF -#define QAM_DQ_TAP_IM_EL3__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL3_TAP__B 0 -#define QAM_DQ_TAP_IM_EL3_TAP__W 12 -#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL4__A 0x1440028 -#define QAM_DQ_TAP_RE_EL4__W 12 -#define QAM_DQ_TAP_RE_EL4__M 0xFFF -#define QAM_DQ_TAP_RE_EL4__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL4_TAP__B 0 -#define QAM_DQ_TAP_RE_EL4_TAP__W 12 -#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL4__A 0x1440029 -#define QAM_DQ_TAP_IM_EL4__W 12 -#define QAM_DQ_TAP_IM_EL4__M 0xFFF -#define QAM_DQ_TAP_IM_EL4__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL4_TAP__B 0 -#define QAM_DQ_TAP_IM_EL4_TAP__W 12 -#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL5__A 0x144002A -#define QAM_DQ_TAP_RE_EL5__W 12 -#define QAM_DQ_TAP_RE_EL5__M 0xFFF -#define QAM_DQ_TAP_RE_EL5__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL5_TAP__B 0 -#define QAM_DQ_TAP_RE_EL5_TAP__W 12 -#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL5__A 0x144002B -#define QAM_DQ_TAP_IM_EL5__W 12 -#define QAM_DQ_TAP_IM_EL5__M 0xFFF -#define QAM_DQ_TAP_IM_EL5__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL5_TAP__B 0 -#define QAM_DQ_TAP_IM_EL5_TAP__W 12 -#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL6__A 0x144002C -#define QAM_DQ_TAP_RE_EL6__W 12 -#define QAM_DQ_TAP_RE_EL6__M 0xFFF -#define QAM_DQ_TAP_RE_EL6__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL6_TAP__B 0 -#define QAM_DQ_TAP_RE_EL6_TAP__W 12 -#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL6__A 0x144002D -#define QAM_DQ_TAP_IM_EL6__W 12 -#define QAM_DQ_TAP_IM_EL6__M 0xFFF -#define QAM_DQ_TAP_IM_EL6__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL6_TAP__B 0 -#define QAM_DQ_TAP_IM_EL6_TAP__W 12 -#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL7__A 0x144002E -#define QAM_DQ_TAP_RE_EL7__W 12 -#define QAM_DQ_TAP_RE_EL7__M 0xFFF -#define QAM_DQ_TAP_RE_EL7__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL7_TAP__B 0 -#define QAM_DQ_TAP_RE_EL7_TAP__W 12 -#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL7__A 0x144002F -#define QAM_DQ_TAP_IM_EL7__W 12 -#define QAM_DQ_TAP_IM_EL7__M 0xFFF -#define QAM_DQ_TAP_IM_EL7__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL7_TAP__B 0 -#define QAM_DQ_TAP_IM_EL7_TAP__W 12 -#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL8__A 0x1440030 -#define QAM_DQ_TAP_RE_EL8__W 12 -#define QAM_DQ_TAP_RE_EL8__M 0xFFF -#define QAM_DQ_TAP_RE_EL8__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL8_TAP__B 0 -#define QAM_DQ_TAP_RE_EL8_TAP__W 12 -#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL8__A 0x1440031 -#define QAM_DQ_TAP_IM_EL8__W 12 -#define QAM_DQ_TAP_IM_EL8__M 0xFFF -#define QAM_DQ_TAP_IM_EL8__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL8_TAP__B 0 -#define QAM_DQ_TAP_IM_EL8_TAP__W 12 -#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL9__A 0x1440032 -#define QAM_DQ_TAP_RE_EL9__W 12 -#define QAM_DQ_TAP_RE_EL9__M 0xFFF -#define QAM_DQ_TAP_RE_EL9__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL9_TAP__B 0 -#define QAM_DQ_TAP_RE_EL9_TAP__W 12 -#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL9__A 0x1440033 -#define QAM_DQ_TAP_IM_EL9__W 12 -#define QAM_DQ_TAP_IM_EL9__M 0xFFF -#define QAM_DQ_TAP_IM_EL9__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL9_TAP__B 0 -#define QAM_DQ_TAP_IM_EL9_TAP__W 12 -#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL10__A 0x1440034 -#define QAM_DQ_TAP_RE_EL10__W 12 -#define QAM_DQ_TAP_RE_EL10__M 0xFFF -#define QAM_DQ_TAP_RE_EL10__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL10_TAP__B 0 -#define QAM_DQ_TAP_RE_EL10_TAP__W 12 -#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL10__A 0x1440035 -#define QAM_DQ_TAP_IM_EL10__W 12 -#define QAM_DQ_TAP_IM_EL10__M 0xFFF -#define QAM_DQ_TAP_IM_EL10__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL10_TAP__B 0 -#define QAM_DQ_TAP_IM_EL10_TAP__W 12 -#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL11__A 0x1440036 -#define QAM_DQ_TAP_RE_EL11__W 12 -#define QAM_DQ_TAP_RE_EL11__M 0xFFF -#define QAM_DQ_TAP_RE_EL11__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL11_TAP__B 0 -#define QAM_DQ_TAP_RE_EL11_TAP__W 12 -#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL11__A 0x1440037 -#define QAM_DQ_TAP_IM_EL11__W 12 -#define QAM_DQ_TAP_IM_EL11__M 0xFFF -#define QAM_DQ_TAP_IM_EL11__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL11_TAP__B 0 -#define QAM_DQ_TAP_IM_EL11_TAP__W 12 -#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL12__A 0x1440038 -#define QAM_DQ_TAP_RE_EL12__W 12 -#define QAM_DQ_TAP_RE_EL12__M 0xFFF -#define QAM_DQ_TAP_RE_EL12__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL12_TAP__B 0 -#define QAM_DQ_TAP_RE_EL12_TAP__W 12 -#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL12__A 0x1440039 -#define QAM_DQ_TAP_IM_EL12__W 12 -#define QAM_DQ_TAP_IM_EL12__M 0xFFF -#define QAM_DQ_TAP_IM_EL12__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL12_TAP__B 0 -#define QAM_DQ_TAP_IM_EL12_TAP__W 12 -#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL13__A 0x144003A -#define QAM_DQ_TAP_RE_EL13__W 12 -#define QAM_DQ_TAP_RE_EL13__M 0xFFF -#define QAM_DQ_TAP_RE_EL13__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL13_TAP__B 0 -#define QAM_DQ_TAP_RE_EL13_TAP__W 12 -#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL13__A 0x144003B -#define QAM_DQ_TAP_IM_EL13__W 12 -#define QAM_DQ_TAP_IM_EL13__M 0xFFF -#define QAM_DQ_TAP_IM_EL13__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL13_TAP__B 0 -#define QAM_DQ_TAP_IM_EL13_TAP__W 12 -#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL14__A 0x144003C -#define QAM_DQ_TAP_RE_EL14__W 12 -#define QAM_DQ_TAP_RE_EL14__M 0xFFF -#define QAM_DQ_TAP_RE_EL14__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL14_TAP__B 0 -#define QAM_DQ_TAP_RE_EL14_TAP__W 12 -#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL14__A 0x144003D -#define QAM_DQ_TAP_IM_EL14__W 12 -#define QAM_DQ_TAP_IM_EL14__M 0xFFF -#define QAM_DQ_TAP_IM_EL14__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL14_TAP__B 0 -#define QAM_DQ_TAP_IM_EL14_TAP__W 12 -#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL15__A 0x144003E -#define QAM_DQ_TAP_RE_EL15__W 12 -#define QAM_DQ_TAP_RE_EL15__M 0xFFF -#define QAM_DQ_TAP_RE_EL15__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL15_TAP__B 0 -#define QAM_DQ_TAP_RE_EL15_TAP__W 12 -#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL15__A 0x144003F -#define QAM_DQ_TAP_IM_EL15__W 12 -#define QAM_DQ_TAP_IM_EL15__M 0xFFF -#define QAM_DQ_TAP_IM_EL15__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL15_TAP__B 0 -#define QAM_DQ_TAP_IM_EL15_TAP__W 12 -#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL16__A 0x1440040 -#define QAM_DQ_TAP_RE_EL16__W 12 -#define QAM_DQ_TAP_RE_EL16__M 0xFFF -#define QAM_DQ_TAP_RE_EL16__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL16_TAP__B 0 -#define QAM_DQ_TAP_RE_EL16_TAP__W 12 -#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL16__A 0x1440041 -#define QAM_DQ_TAP_IM_EL16__W 12 -#define QAM_DQ_TAP_IM_EL16__M 0xFFF -#define QAM_DQ_TAP_IM_EL16__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL16_TAP__B 0 -#define QAM_DQ_TAP_IM_EL16_TAP__W 12 -#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL17__A 0x1440042 -#define QAM_DQ_TAP_RE_EL17__W 12 -#define QAM_DQ_TAP_RE_EL17__M 0xFFF -#define QAM_DQ_TAP_RE_EL17__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL17_TAP__B 0 -#define QAM_DQ_TAP_RE_EL17_TAP__W 12 -#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL17__A 0x1440043 -#define QAM_DQ_TAP_IM_EL17__W 12 -#define QAM_DQ_TAP_IM_EL17__M 0xFFF -#define QAM_DQ_TAP_IM_EL17__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL17_TAP__B 0 -#define QAM_DQ_TAP_IM_EL17_TAP__W 12 -#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL18__A 0x1440044 -#define QAM_DQ_TAP_RE_EL18__W 12 -#define QAM_DQ_TAP_RE_EL18__M 0xFFF -#define QAM_DQ_TAP_RE_EL18__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL18_TAP__B 0 -#define QAM_DQ_TAP_RE_EL18_TAP__W 12 -#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL18__A 0x1440045 -#define QAM_DQ_TAP_IM_EL18__W 12 -#define QAM_DQ_TAP_IM_EL18__M 0xFFF -#define QAM_DQ_TAP_IM_EL18__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL18_TAP__B 0 -#define QAM_DQ_TAP_IM_EL18_TAP__W 12 -#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL19__A 0x1440046 -#define QAM_DQ_TAP_RE_EL19__W 12 -#define QAM_DQ_TAP_RE_EL19__M 0xFFF -#define QAM_DQ_TAP_RE_EL19__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL19_TAP__B 0 -#define QAM_DQ_TAP_RE_EL19_TAP__W 12 -#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL19__A 0x1440047 -#define QAM_DQ_TAP_IM_EL19__W 12 -#define QAM_DQ_TAP_IM_EL19__M 0xFFF -#define QAM_DQ_TAP_IM_EL19__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL19_TAP__B 0 -#define QAM_DQ_TAP_IM_EL19_TAP__W 12 -#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL20__A 0x1440048 -#define QAM_DQ_TAP_RE_EL20__W 12 -#define QAM_DQ_TAP_RE_EL20__M 0xFFF -#define QAM_DQ_TAP_RE_EL20__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL20_TAP__B 0 -#define QAM_DQ_TAP_RE_EL20_TAP__W 12 -#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL20__A 0x1440049 -#define QAM_DQ_TAP_IM_EL20__W 12 -#define QAM_DQ_TAP_IM_EL20__M 0xFFF -#define QAM_DQ_TAP_IM_EL20__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL20_TAP__B 0 -#define QAM_DQ_TAP_IM_EL20_TAP__W 12 -#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL21__A 0x144004A -#define QAM_DQ_TAP_RE_EL21__W 12 -#define QAM_DQ_TAP_RE_EL21__M 0xFFF -#define QAM_DQ_TAP_RE_EL21__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL21_TAP__B 0 -#define QAM_DQ_TAP_RE_EL21_TAP__W 12 -#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL21__A 0x144004B -#define QAM_DQ_TAP_IM_EL21__W 12 -#define QAM_DQ_TAP_IM_EL21__M 0xFFF -#define QAM_DQ_TAP_IM_EL21__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL21_TAP__B 0 -#define QAM_DQ_TAP_IM_EL21_TAP__W 12 -#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL22__A 0x144004C -#define QAM_DQ_TAP_RE_EL22__W 12 -#define QAM_DQ_TAP_RE_EL22__M 0xFFF -#define QAM_DQ_TAP_RE_EL22__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL22_TAP__B 0 -#define QAM_DQ_TAP_RE_EL22_TAP__W 12 -#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL22__A 0x144004D -#define QAM_DQ_TAP_IM_EL22__W 12 -#define QAM_DQ_TAP_IM_EL22__M 0xFFF -#define QAM_DQ_TAP_IM_EL22__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL22_TAP__B 0 -#define QAM_DQ_TAP_IM_EL22_TAP__W 12 -#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL23__A 0x144004E -#define QAM_DQ_TAP_RE_EL23__W 12 -#define QAM_DQ_TAP_RE_EL23__M 0xFFF -#define QAM_DQ_TAP_RE_EL23__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL23_TAP__B 0 -#define QAM_DQ_TAP_RE_EL23_TAP__W 12 -#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL23__A 0x144004F -#define QAM_DQ_TAP_IM_EL23__W 12 -#define QAM_DQ_TAP_IM_EL23__M 0xFFF -#define QAM_DQ_TAP_IM_EL23__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL23_TAP__B 0 -#define QAM_DQ_TAP_IM_EL23_TAP__W 12 -#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL24__A 0x1440050 -#define QAM_DQ_TAP_RE_EL24__W 12 -#define QAM_DQ_TAP_RE_EL24__M 0xFFF -#define QAM_DQ_TAP_RE_EL24__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL24_TAP__B 0 -#define QAM_DQ_TAP_RE_EL24_TAP__W 12 -#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL24__A 0x1440051 -#define QAM_DQ_TAP_IM_EL24__W 12 -#define QAM_DQ_TAP_IM_EL24__M 0xFFF -#define QAM_DQ_TAP_IM_EL24__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL24_TAP__B 0 -#define QAM_DQ_TAP_IM_EL24_TAP__W 12 -#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL25__A 0x1440052 -#define QAM_DQ_TAP_RE_EL25__W 12 -#define QAM_DQ_TAP_RE_EL25__M 0xFFF -#define QAM_DQ_TAP_RE_EL25__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL25_TAP__B 0 -#define QAM_DQ_TAP_RE_EL25_TAP__W 12 -#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL25__A 0x1440053 -#define QAM_DQ_TAP_IM_EL25__W 12 -#define QAM_DQ_TAP_IM_EL25__M 0xFFF -#define QAM_DQ_TAP_IM_EL25__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL25_TAP__B 0 -#define QAM_DQ_TAP_IM_EL25_TAP__W 12 -#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL26__A 0x1440054 -#define QAM_DQ_TAP_RE_EL26__W 12 -#define QAM_DQ_TAP_RE_EL26__M 0xFFF -#define QAM_DQ_TAP_RE_EL26__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL26_TAP__B 0 -#define QAM_DQ_TAP_RE_EL26_TAP__W 12 -#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL26__A 0x1440055 -#define QAM_DQ_TAP_IM_EL26__W 12 -#define QAM_DQ_TAP_IM_EL26__M 0xFFF -#define QAM_DQ_TAP_IM_EL26__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL26_TAP__B 0 -#define QAM_DQ_TAP_IM_EL26_TAP__W 12 -#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL27__A 0x1440056 -#define QAM_DQ_TAP_RE_EL27__W 12 -#define QAM_DQ_TAP_RE_EL27__M 0xFFF -#define QAM_DQ_TAP_RE_EL27__PRE 0x2 - -#define QAM_DQ_TAP_RE_EL27_TAP__B 0 -#define QAM_DQ_TAP_RE_EL27_TAP__W 12 -#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF -#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL27__A 0x1440057 -#define QAM_DQ_TAP_IM_EL27__W 12 -#define QAM_DQ_TAP_IM_EL27__M 0xFFF -#define QAM_DQ_TAP_IM_EL27__PRE 0x2 - -#define QAM_DQ_TAP_IM_EL27_TAP__B 0 -#define QAM_DQ_TAP_IM_EL27_TAP__W 12 -#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF -#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 - - - -#define QAM_LC_COMM_EXEC__A 0x1450000 -#define QAM_LC_COMM_EXEC__W 2 -#define QAM_LC_COMM_EXEC__M 0x3 -#define QAM_LC_COMM_EXEC__PRE 0x0 -#define QAM_LC_COMM_EXEC_STOP 0x0 -#define QAM_LC_COMM_EXEC_ACTIVE 0x1 -#define QAM_LC_COMM_EXEC_HOLD 0x2 - -#define QAM_LC_COMM_MB__A 0x1450002 -#define QAM_LC_COMM_MB__W 2 -#define QAM_LC_COMM_MB__M 0x3 -#define QAM_LC_COMM_MB__PRE 0x0 -#define QAM_LC_COMM_MB_CTL__B 0 -#define QAM_LC_COMM_MB_CTL__W 1 -#define QAM_LC_COMM_MB_CTL__M 0x1 -#define QAM_LC_COMM_MB_CTL__PRE 0x0 -#define QAM_LC_COMM_MB_CTL_OFF 0x0 -#define QAM_LC_COMM_MB_CTL_ON 0x1 -#define QAM_LC_COMM_MB_OBS__B 1 -#define QAM_LC_COMM_MB_OBS__W 1 -#define QAM_LC_COMM_MB_OBS__M 0x2 -#define QAM_LC_COMM_MB_OBS__PRE 0x0 -#define QAM_LC_COMM_MB_OBS_OFF 0x0 -#define QAM_LC_COMM_MB_OBS_ON 0x2 - -#define QAM_LC_COMM_INT_REQ__A 0x1450003 -#define QAM_LC_COMM_INT_REQ__W 1 -#define QAM_LC_COMM_INT_REQ__M 0x1 -#define QAM_LC_COMM_INT_REQ__PRE 0x0 -#define QAM_LC_COMM_INT_STA__A 0x1450005 -#define QAM_LC_COMM_INT_STA__W 3 -#define QAM_LC_COMM_INT_STA__M 0x7 -#define QAM_LC_COMM_INT_STA__PRE 0x0 - -#define QAM_LC_COMM_INT_STA_READY__B 0 -#define QAM_LC_COMM_INT_STA_READY__W 1 -#define QAM_LC_COMM_INT_STA_READY__M 0x1 -#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 - -#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 -#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 -#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 -#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 - -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 -#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 - -#define QAM_LC_COMM_INT_MSK__A 0x1450006 -#define QAM_LC_COMM_INT_MSK__W 3 -#define QAM_LC_COMM_INT_MSK__M 0x7 -#define QAM_LC_COMM_INT_MSK__PRE 0x0 -#define QAM_LC_COMM_INT_MSK_READY__B 0 -#define QAM_LC_COMM_INT_MSK_READY__W 1 -#define QAM_LC_COMM_INT_MSK_READY__M 0x1 -#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 -#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 -#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 - -#define QAM_LC_COMM_INT_STM__A 0x1450007 -#define QAM_LC_COMM_INT_STM__W 3 -#define QAM_LC_COMM_INT_STM__M 0x7 -#define QAM_LC_COMM_INT_STM__PRE 0x0 -#define QAM_LC_COMM_INT_STM_READY__B 0 -#define QAM_LC_COMM_INT_STM_READY__W 1 -#define QAM_LC_COMM_INT_STM_READY__M 0x1 -#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 -#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 -#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 -#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 -#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 -#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 - -#define QAM_LC_MODE__A 0x1450010 -#define QAM_LC_MODE__W 4 -#define QAM_LC_MODE__M 0xF -#define QAM_LC_MODE__PRE 0xE - -#define QAM_LC_MODE_ENABLE_A__B 0 -#define QAM_LC_MODE_ENABLE_A__W 1 -#define QAM_LC_MODE_ENABLE_A__M 0x1 -#define QAM_LC_MODE_ENABLE_A__PRE 0x0 - -#define QAM_LC_MODE_ENABLE_F__B 1 -#define QAM_LC_MODE_ENABLE_F__W 1 -#define QAM_LC_MODE_ENABLE_F__M 0x2 -#define QAM_LC_MODE_ENABLE_F__PRE 0x2 - -#define QAM_LC_MODE_ENABLE_R__B 2 -#define QAM_LC_MODE_ENABLE_R__W 1 -#define QAM_LC_MODE_ENABLE_R__M 0x4 -#define QAM_LC_MODE_ENABLE_R__PRE 0x4 - -#define QAM_LC_MODE_ENABLE_PQUAL__B 3 -#define QAM_LC_MODE_ENABLE_PQUAL__W 1 -#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8 -#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8 - -#define QAM_LC_CA__A 0x1450011 -#define QAM_LC_CA__W 6 -#define QAM_LC_CA__M 0x3F -#define QAM_LC_CA__PRE 0x28 - -#define QAM_LC_CA_COEF__B 0 -#define QAM_LC_CA_COEF__W 6 -#define QAM_LC_CA_COEF__M 0x3F -#define QAM_LC_CA_COEF__PRE 0x28 - -#define QAM_LC_CF__A 0x1450012 -#define QAM_LC_CF__W 8 -#define QAM_LC_CF__M 0xFF -#define QAM_LC_CF__PRE 0x30 - -#define QAM_LC_CF_COEF__B 0 -#define QAM_LC_CF_COEF__W 8 -#define QAM_LC_CF_COEF__M 0xFF -#define QAM_LC_CF_COEF__PRE 0x30 - -#define QAM_LC_CF1__A 0x1450013 -#define QAM_LC_CF1__W 8 -#define QAM_LC_CF1__M 0xFF -#define QAM_LC_CF1__PRE 0x14 - -#define QAM_LC_CF1_COEF__B 0 -#define QAM_LC_CF1_COEF__W 8 -#define QAM_LC_CF1_COEF__M 0xFF -#define QAM_LC_CF1_COEF__PRE 0x14 - -#define QAM_LC_CP__A 0x1450014 -#define QAM_LC_CP__W 8 -#define QAM_LC_CP__M 0xFF -#define QAM_LC_CP__PRE 0x64 - -#define QAM_LC_CP_COEF__B 0 -#define QAM_LC_CP_COEF__W 8 -#define QAM_LC_CP_COEF__M 0xFF -#define QAM_LC_CP_COEF__PRE 0x64 - -#define QAM_LC_CI__A 0x1450015 -#define QAM_LC_CI__W 8 -#define QAM_LC_CI__M 0xFF -#define QAM_LC_CI__PRE 0x32 - -#define QAM_LC_CI_COEF__B 0 -#define QAM_LC_CI_COEF__W 8 -#define QAM_LC_CI_COEF__M 0xFF -#define QAM_LC_CI_COEF__PRE 0x32 - -#define QAM_LC_EP__A 0x1450016 -#define QAM_LC_EP__W 6 -#define QAM_LC_EP__M 0x3F -#define QAM_LC_EP__PRE 0x0 - -#define QAM_LC_EP_COEF__B 0 -#define QAM_LC_EP_COEF__W 6 -#define QAM_LC_EP_COEF__M 0x3F -#define QAM_LC_EP_COEF__PRE 0x0 - -#define QAM_LC_EI__A 0x1450017 -#define QAM_LC_EI__W 6 -#define QAM_LC_EI__M 0x3F -#define QAM_LC_EI__PRE 0x0 - -#define QAM_LC_EI_COEF__B 0 -#define QAM_LC_EI_COEF__W 6 -#define QAM_LC_EI_COEF__M 0x3F -#define QAM_LC_EI_COEF__PRE 0x0 - -#define QAM_LC_QUAL_TAB0__A 0x1450018 -#define QAM_LC_QUAL_TAB0__W 5 -#define QAM_LC_QUAL_TAB0__M 0x1F -#define QAM_LC_QUAL_TAB0__PRE 0x0 - -#define QAM_LC_QUAL_TAB0_VALUE__B 0 -#define QAM_LC_QUAL_TAB0_VALUE__W 5 -#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 - -#define QAM_LC_QUAL_TAB1__A 0x1450019 -#define QAM_LC_QUAL_TAB1__W 5 -#define QAM_LC_QUAL_TAB1__M 0x1F -#define QAM_LC_QUAL_TAB1__PRE 0x1 - -#define QAM_LC_QUAL_TAB1_VALUE__B 0 -#define QAM_LC_QUAL_TAB1_VALUE__W 5 -#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 - -#define QAM_LC_QUAL_TAB2__A 0x145001A -#define QAM_LC_QUAL_TAB2__W 5 -#define QAM_LC_QUAL_TAB2__M 0x1F -#define QAM_LC_QUAL_TAB2__PRE 0x2 - -#define QAM_LC_QUAL_TAB2_VALUE__B 0 -#define QAM_LC_QUAL_TAB2_VALUE__W 5 -#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 - -#define QAM_LC_QUAL_TAB3__A 0x145001B -#define QAM_LC_QUAL_TAB3__W 5 -#define QAM_LC_QUAL_TAB3__M 0x1F -#define QAM_LC_QUAL_TAB3__PRE 0x3 - -#define QAM_LC_QUAL_TAB3_VALUE__B 0 -#define QAM_LC_QUAL_TAB3_VALUE__W 5 -#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 - -#define QAM_LC_QUAL_TAB4__A 0x145001C -#define QAM_LC_QUAL_TAB4__W 5 -#define QAM_LC_QUAL_TAB4__M 0x1F -#define QAM_LC_QUAL_TAB4__PRE 0x4 - -#define QAM_LC_QUAL_TAB4_VALUE__B 0 -#define QAM_LC_QUAL_TAB4_VALUE__W 5 -#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 - -#define QAM_LC_QUAL_TAB5__A 0x145001D -#define QAM_LC_QUAL_TAB5__W 5 -#define QAM_LC_QUAL_TAB5__M 0x1F -#define QAM_LC_QUAL_TAB5__PRE 0x5 - -#define QAM_LC_QUAL_TAB5_VALUE__B 0 -#define QAM_LC_QUAL_TAB5_VALUE__W 5 -#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 - -#define QAM_LC_QUAL_TAB6__A 0x145001E -#define QAM_LC_QUAL_TAB6__W 5 -#define QAM_LC_QUAL_TAB6__M 0x1F -#define QAM_LC_QUAL_TAB6__PRE 0x6 - -#define QAM_LC_QUAL_TAB6_VALUE__B 0 -#define QAM_LC_QUAL_TAB6_VALUE__W 5 -#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 - -#define QAM_LC_QUAL_TAB8__A 0x145001F -#define QAM_LC_QUAL_TAB8__W 5 -#define QAM_LC_QUAL_TAB8__M 0x1F -#define QAM_LC_QUAL_TAB8__PRE 0x8 - -#define QAM_LC_QUAL_TAB8_VALUE__B 0 -#define QAM_LC_QUAL_TAB8_VALUE__W 5 -#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 - -#define QAM_LC_QUAL_TAB9__A 0x1450020 -#define QAM_LC_QUAL_TAB9__W 5 -#define QAM_LC_QUAL_TAB9__M 0x1F -#define QAM_LC_QUAL_TAB9__PRE 0x9 - -#define QAM_LC_QUAL_TAB9_VALUE__B 0 -#define QAM_LC_QUAL_TAB9_VALUE__W 5 -#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 - -#define QAM_LC_QUAL_TAB10__A 0x1450021 -#define QAM_LC_QUAL_TAB10__W 5 -#define QAM_LC_QUAL_TAB10__M 0x1F -#define QAM_LC_QUAL_TAB10__PRE 0xA - -#define QAM_LC_QUAL_TAB10_VALUE__B 0 -#define QAM_LC_QUAL_TAB10_VALUE__W 5 -#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA - -#define QAM_LC_QUAL_TAB12__A 0x1450022 -#define QAM_LC_QUAL_TAB12__W 5 -#define QAM_LC_QUAL_TAB12__M 0x1F -#define QAM_LC_QUAL_TAB12__PRE 0xC - -#define QAM_LC_QUAL_TAB12_VALUE__B 0 -#define QAM_LC_QUAL_TAB12_VALUE__W 5 -#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC - -#define QAM_LC_QUAL_TAB15__A 0x1450023 -#define QAM_LC_QUAL_TAB15__W 5 -#define QAM_LC_QUAL_TAB15__M 0x1F -#define QAM_LC_QUAL_TAB15__PRE 0xF - -#define QAM_LC_QUAL_TAB15_VALUE__B 0 -#define QAM_LC_QUAL_TAB15_VALUE__W 5 -#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF - -#define QAM_LC_QUAL_TAB16__A 0x1450024 -#define QAM_LC_QUAL_TAB16__W 5 -#define QAM_LC_QUAL_TAB16__M 0x1F -#define QAM_LC_QUAL_TAB16__PRE 0x10 - -#define QAM_LC_QUAL_TAB16_VALUE__B 0 -#define QAM_LC_QUAL_TAB16_VALUE__W 5 -#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 - -#define QAM_LC_QUAL_TAB20__A 0x1450025 -#define QAM_LC_QUAL_TAB20__W 5 -#define QAM_LC_QUAL_TAB20__M 0x1F -#define QAM_LC_QUAL_TAB20__PRE 0x14 - -#define QAM_LC_QUAL_TAB20_VALUE__B 0 -#define QAM_LC_QUAL_TAB20_VALUE__W 5 -#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 - -#define QAM_LC_QUAL_TAB25__A 0x1450026 -#define QAM_LC_QUAL_TAB25__W 5 -#define QAM_LC_QUAL_TAB25__M 0x1F -#define QAM_LC_QUAL_TAB25__PRE 0x19 - -#define QAM_LC_QUAL_TAB25_VALUE__B 0 -#define QAM_LC_QUAL_TAB25_VALUE__W 5 -#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 - -#define QAM_LC_EQ_TIMING__A 0x1450027 -#define QAM_LC_EQ_TIMING__W 10 -#define QAM_LC_EQ_TIMING__M 0x3FF -#define QAM_LC_EQ_TIMING__PRE 0x0 - -#define QAM_LC_EQ_TIMING_OFFS__B 0 -#define QAM_LC_EQ_TIMING_OFFS__W 10 -#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF -#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 - -#define QAM_LC_LPF_FACTORP__A 0x1450028 -#define QAM_LC_LPF_FACTORP__W 3 -#define QAM_LC_LPF_FACTORP__M 0x7 -#define QAM_LC_LPF_FACTORP__PRE 0x3 - -#define QAM_LC_LPF_FACTORP_FACTOR__B 0 -#define QAM_LC_LPF_FACTORP_FACTOR__W 3 -#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 -#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 - -#define QAM_LC_LPF_FACTORI__A 0x1450029 -#define QAM_LC_LPF_FACTORI__W 3 -#define QAM_LC_LPF_FACTORI__M 0x7 -#define QAM_LC_LPF_FACTORI__PRE 0x3 - -#define QAM_LC_LPF_FACTORI_FACTOR__B 0 -#define QAM_LC_LPF_FACTORI_FACTOR__W 3 -#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 -#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 - -#define QAM_LC_RATE_LIMIT__A 0x145002A -#define QAM_LC_RATE_LIMIT__W 2 -#define QAM_LC_RATE_LIMIT__M 0x3 -#define QAM_LC_RATE_LIMIT__PRE 0x3 - -#define QAM_LC_RATE_LIMIT_LIMIT__B 0 -#define QAM_LC_RATE_LIMIT_LIMIT__W 2 -#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 -#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 - -#define QAM_LC_SYMBOL_FREQ__A 0x145002B -#define QAM_LC_SYMBOL_FREQ__W 10 -#define QAM_LC_SYMBOL_FREQ__M 0x3FF -#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF - -#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 -#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 -#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF -#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF - -#define QAM_LC_MTA_LENGTH__A 0x145002C -#define QAM_LC_MTA_LENGTH__W 2 -#define QAM_LC_MTA_LENGTH__M 0x3 -#define QAM_LC_MTA_LENGTH__PRE 0x2 - -#define QAM_LC_MTA_LENGTH_LENGTH__B 0 -#define QAM_LC_MTA_LENGTH_LENGTH__W 2 -#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 -#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 - -#define QAM_LC_AMP_ACCU__A 0x145002D -#define QAM_LC_AMP_ACCU__W 14 -#define QAM_LC_AMP_ACCU__M 0x3FFF -#define QAM_LC_AMP_ACCU__PRE 0x600 - -#define QAM_LC_AMP_ACCU_ACCU__B 0 -#define QAM_LC_AMP_ACCU_ACCU__W 14 -#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF -#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 - -#define QAM_LC_FREQ_ACCU__A 0x145002E -#define QAM_LC_FREQ_ACCU__W 10 -#define QAM_LC_FREQ_ACCU__M 0x3FF -#define QAM_LC_FREQ_ACCU__PRE 0x0 - -#define QAM_LC_FREQ_ACCU_ACCU__B 0 -#define QAM_LC_FREQ_ACCU_ACCU__W 10 -#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF -#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 - -#define QAM_LC_RATE_ACCU__A 0x145002F -#define QAM_LC_RATE_ACCU__W 10 -#define QAM_LC_RATE_ACCU__M 0x3FF -#define QAM_LC_RATE_ACCU__PRE 0x0 - -#define QAM_LC_RATE_ACCU_ACCU__B 0 -#define QAM_LC_RATE_ACCU_ACCU__W 10 -#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF -#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 - -#define QAM_LC_AMPLITUDE__A 0x1450030 -#define QAM_LC_AMPLITUDE__W 10 -#define QAM_LC_AMPLITUDE__M 0x3FF -#define QAM_LC_AMPLITUDE__PRE 0x0 - -#define QAM_LC_AMPLITUDE_SIZE__B 0 -#define QAM_LC_AMPLITUDE_SIZE__W 10 -#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF -#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 - -#define QAM_LC_RAD_ERROR__A 0x1450031 -#define QAM_LC_RAD_ERROR__W 10 -#define QAM_LC_RAD_ERROR__M 0x3FF -#define QAM_LC_RAD_ERROR__PRE 0x0 - -#define QAM_LC_RAD_ERROR_SIZE__B 0 -#define QAM_LC_RAD_ERROR_SIZE__W 10 -#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF -#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 - -#define QAM_LC_FREQ_OFFS__A 0x1450032 -#define QAM_LC_FREQ_OFFS__W 10 -#define QAM_LC_FREQ_OFFS__M 0x3FF -#define QAM_LC_FREQ_OFFS__PRE 0x0 - -#define QAM_LC_FREQ_OFFS_OFFS__B 0 -#define QAM_LC_FREQ_OFFS_OFFS__W 10 -#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF -#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 - -#define QAM_LC_PHASE_ERROR__A 0x1450033 -#define QAM_LC_PHASE_ERROR__W 10 -#define QAM_LC_PHASE_ERROR__M 0x3FF -#define QAM_LC_PHASE_ERROR__PRE 0x0 - -#define QAM_LC_PHASE_ERROR_SIZE__B 0 -#define QAM_LC_PHASE_ERROR_SIZE__W 10 -#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF -#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 - - - -#define QAM_SY_COMM_EXEC__A 0x1470000 -#define QAM_SY_COMM_EXEC__W 2 -#define QAM_SY_COMM_EXEC__M 0x3 -#define QAM_SY_COMM_EXEC__PRE 0x0 -#define QAM_SY_COMM_EXEC_STOP 0x0 -#define QAM_SY_COMM_EXEC_ACTIVE 0x1 -#define QAM_SY_COMM_EXEC_HOLD 0x2 - -#define QAM_SY_COMM_MB__A 0x1470002 -#define QAM_SY_COMM_MB__W 4 -#define QAM_SY_COMM_MB__M 0xF -#define QAM_SY_COMM_MB__PRE 0x0 -#define QAM_SY_COMM_MB_CTL__B 0 -#define QAM_SY_COMM_MB_CTL__W 1 -#define QAM_SY_COMM_MB_CTL__M 0x1 -#define QAM_SY_COMM_MB_CTL__PRE 0x0 -#define QAM_SY_COMM_MB_CTL_OFF 0x0 -#define QAM_SY_COMM_MB_CTL_ON 0x1 -#define QAM_SY_COMM_MB_OBS__B 1 -#define QAM_SY_COMM_MB_OBS__W 1 -#define QAM_SY_COMM_MB_OBS__M 0x2 -#define QAM_SY_COMM_MB_OBS__PRE 0x0 -#define QAM_SY_COMM_MB_OBS_OFF 0x0 -#define QAM_SY_COMM_MB_OBS_ON 0x2 -#define QAM_SY_COMM_MB_MUX_CTL__B 2 -#define QAM_SY_COMM_MB_MUX_CTL__W 1 -#define QAM_SY_COMM_MB_MUX_CTL__M 0x4 -#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0 -#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0 -#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4 -#define QAM_SY_COMM_MB_MUX_OBS__B 3 -#define QAM_SY_COMM_MB_MUX_OBS__W 1 -#define QAM_SY_COMM_MB_MUX_OBS__M 0x8 -#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0 -#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0 -#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8 - -#define QAM_SY_COMM_INT_REQ__A 0x1470003 -#define QAM_SY_COMM_INT_REQ__W 1 -#define QAM_SY_COMM_INT_REQ__M 0x1 -#define QAM_SY_COMM_INT_REQ__PRE 0x0 -#define QAM_SY_COMM_INT_STA__A 0x1470005 -#define QAM_SY_COMM_INT_STA__W 4 -#define QAM_SY_COMM_INT_STA__M 0xF -#define QAM_SY_COMM_INT_STA__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 -#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 -#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 -#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 -#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 -#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 -#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 - -#define QAM_SY_COMM_INT_MSK__A 0x1470006 -#define QAM_SY_COMM_INT_MSK__W 4 -#define QAM_SY_COMM_INT_MSK__M 0xF -#define QAM_SY_COMM_INT_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 -#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 -#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 -#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 -#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 - -#define QAM_SY_COMM_INT_STM__A 0x1470007 -#define QAM_SY_COMM_INT_STM__W 4 -#define QAM_SY_COMM_INT_STM__M 0xF -#define QAM_SY_COMM_INT_STM__PRE 0x0 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 -#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 -#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 -#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 -#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 - -#define QAM_SY_STATUS__A 0x1470010 -#define QAM_SY_STATUS__W 2 -#define QAM_SY_STATUS__M 0x3 -#define QAM_SY_STATUS__PRE 0x0 - -#define QAM_SY_STATUS_SYNC_STATE__B 0 -#define QAM_SY_STATUS_SYNC_STATE__W 2 -#define QAM_SY_STATUS_SYNC_STATE__M 0x3 -#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 - - -#define QAM_SY_TIMEOUT__A 0x1470011 -#define QAM_SY_TIMEOUT__W 16 -#define QAM_SY_TIMEOUT__M 0xFFFF -#define QAM_SY_TIMEOUT__PRE 0x3A98 - -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__W 4 -#define QAM_SY_SYNC_LWM__M 0xF -#define QAM_SY_SYNC_LWM__PRE 0x2 - -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__W 4 -#define QAM_SY_SYNC_AWM__M 0xF -#define QAM_SY_SYNC_AWM__PRE 0x3 - -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__W 4 -#define QAM_SY_SYNC_HWM__M 0xF -#define QAM_SY_SYNC_HWM__PRE 0x5 - -#define QAM_SY_UNLOCK__A 0x1470015 -#define QAM_SY_UNLOCK__W 1 -#define QAM_SY_UNLOCK__M 0x1 -#define QAM_SY_UNLOCK__PRE 0x0 -#define QAM_SY_CONTROL_WORD__A 0x1470016 -#define QAM_SY_CONTROL_WORD__W 4 -#define QAM_SY_CONTROL_WORD__M 0xF -#define QAM_SY_CONTROL_WORD__PRE 0x0 - -#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 -#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 -#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF -#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 - - -#define QAM_SY_SP_INV__A 0x1470017 -#define QAM_SY_SP_INV__W 1 -#define QAM_SY_SP_INV__M 0x1 -#define QAM_SY_SP_INV__PRE 0x0 -#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 -#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1 - - - -#define QAM_VD_ISS_RAM__A 0x1480000 - - - -#define QAM_VD_QSS_RAM__A 0x1490000 - - - -#define QAM_VD_SYM_RAM__A 0x14A0000 - - - - - -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__W 2 -#define SCU_COMM_EXEC__M 0x3 -#define SCU_COMM_EXEC__PRE 0x0 -#define SCU_COMM_EXEC_STOP 0x0 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_HOLD 0x2 - -#define SCU_COMM_STATE__A 0x800001 -#define SCU_COMM_STATE__W 16 -#define SCU_COMM_STATE__M 0xFFFF -#define SCU_COMM_STATE__PRE 0x0 - -#define SCU_COMM_STATE_COMM_STATE__B 0 -#define SCU_COMM_STATE_COMM_STATE__W 16 -#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF -#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 - - - -#define SCU_TOP_COMM_EXEC__A 0x810000 -#define SCU_TOP_COMM_EXEC__W 2 -#define SCU_TOP_COMM_EXEC__M 0x3 -#define SCU_TOP_COMM_EXEC__PRE 0x0 -#define SCU_TOP_COMM_EXEC_STOP 0x0 -#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 -#define SCU_TOP_COMM_EXEC_HOLD 0x2 - - -#define SCU_TOP_COMM_STATE__A 0x810001 -#define SCU_TOP_COMM_STATE__W 16 -#define SCU_TOP_COMM_STATE__M 0xFFFF -#define SCU_TOP_COMM_STATE__PRE 0x0 -#define SCU_TOP_MWAIT_CTR__A 0x810010 -#define SCU_TOP_MWAIT_CTR__W 2 -#define SCU_TOP_MWAIT_CTR__M 0x3 -#define SCU_TOP_MWAIT_CTR__PRE 0x0 - -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 -#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 - -#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 -#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 -#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 -#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 -#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 -#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 - - - -#define SCU_LOW_RAM__A 0x820000 - -#define SCU_LOW_RAM_LOW__B 0 -#define SCU_LOW_RAM_LOW__W 16 -#define SCU_LOW_RAM_LOW__M 0xFFFF -#define SCU_LOW_RAM_LOW__PRE 0x0 - - - -#define SCU_HIGH_RAM__A 0x830000 - -#define SCU_HIGH_RAM_HIGH__B 0 -#define SCU_HIGH_RAM_HIGH__W 16 -#define SCU_HIGH_RAM_HIGH__M 0xFFFF -#define SCU_HIGH_RAM_HIGH__PRE 0x0 - - - - - - -#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF -#define SCU_RAM_DRIVER_DEBUG__W 16 -#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF -#define SCU_RAM_DRIVER_DEBUG__PRE 0x0 - -#define SCU_RAM_SP__A 0x831EC0 -#define SCU_RAM_SP__W 16 -#define SCU_RAM_SP__M 0xFFFF -#define SCU_RAM_SP__PRE 0x0 - -#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1 -#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16 -#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF -#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0 - -#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2 -#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16 -#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF -#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0 - -#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3 -#define SCU_RAM_QAM_NO_ACQ_CNT__W 16 -#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF -#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 -#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16 -#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF -#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0 - -#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5 -#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 -#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000 - -#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6 -#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 -#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__W 2 -#define SCU_RAM_GPIO__M 0x3 -#define SCU_RAM_GPIO__PRE 0x0 - -#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 -#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 -#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 -#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 - -#define SCU_RAM_GPIO_VSYNC_IND__B 1 -#define SCU_RAM_GPIO_VSYNC_IND__W 1 -#define SCU_RAM_GPIO_VSYNC_IND__M 0x2 -#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0 -#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2 - -#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 -#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 -#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF -#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 - -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 - -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 - -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 -#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 - - -#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 -#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 -#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000 - -#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA -#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 -#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 - -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 - -#define SCU_RAM_INHIBIT_1__A 0x831ECC -#define SCU_RAM_INHIBIT_1__W 16 -#define SCU_RAM_INHIBIT_1__M 0xFFFF -#define SCU_RAM_INHIBIT_1__PRE 0x0 - -#define SCU_RAM_HTOL_BUF_0__A 0x831ECD -#define SCU_RAM_HTOL_BUF_0__W 16 -#define SCU_RAM_HTOL_BUF_0__M 0xFFFF -#define SCU_RAM_HTOL_BUF_0__PRE 0x0 - -#define SCU_RAM_HTOL_BUF_1__A 0x831ECE -#define SCU_RAM_HTOL_BUF_1__W 16 -#define SCU_RAM_HTOL_BUF_1__M 0xFFFF -#define SCU_RAM_HTOL_BUF_1__PRE 0x0 - -#define SCU_RAM_INHIBIT_2__A 0x831ECF -#define SCU_RAM_INHIBIT_2__W 16 -#define SCU_RAM_INHIBIT_2__M 0xFFFF -#define SCU_RAM_INHIBIT_2__PRE 0x0 - -#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 -#define SCU_RAM_TR_SHORT_BUF_0__W 16 -#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF -#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 - -#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 -#define SCU_RAM_TR_SHORT_BUF_1__W 16 -#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF -#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 -#define SCU_RAM_TR_LONG_BUF_0__W 16 -#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 -#define SCU_RAM_TR_LONG_BUF_1__W 16 -#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 -#define SCU_RAM_TR_LONG_BUF_2__W 16 -#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 -#define SCU_RAM_TR_LONG_BUF_3__W 16 -#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 -#define SCU_RAM_TR_LONG_BUF_4__W 16 -#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 -#define SCU_RAM_TR_LONG_BUF_5__W 16 -#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 -#define SCU_RAM_TR_LONG_BUF_6__W 16 -#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 -#define SCU_RAM_TR_LONG_BUF_7__W 16 -#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA -#define SCU_RAM_TR_LONG_BUF_8__W 16 -#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB -#define SCU_RAM_TR_LONG_BUF_9__W 16 -#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC -#define SCU_RAM_TR_LONG_BUF_10__W 16 -#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD -#define SCU_RAM_TR_LONG_BUF_11__W 16 -#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE -#define SCU_RAM_TR_LONG_BUF_12__W 16 -#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF -#define SCU_RAM_TR_LONG_BUF_13__W 16 -#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 -#define SCU_RAM_TR_LONG_BUF_14__W 16 -#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 -#define SCU_RAM_TR_LONG_BUF_15__W 16 -#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 -#define SCU_RAM_TR_LONG_BUF_16__W 16 -#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 -#define SCU_RAM_TR_LONG_BUF_17__W 16 -#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 -#define SCU_RAM_TR_LONG_BUF_18__W 16 -#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 -#define SCU_RAM_TR_LONG_BUF_19__W 16 -#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 -#define SCU_RAM_TR_LONG_BUF_20__W 16 -#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 -#define SCU_RAM_TR_LONG_BUF_21__W 16 -#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 -#define SCU_RAM_TR_LONG_BUF_22__W 16 -#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 -#define SCU_RAM_TR_LONG_BUF_23__W 16 -#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA -#define SCU_RAM_TR_LONG_BUF_24__W 16 -#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB -#define SCU_RAM_TR_LONG_BUF_25__W 16 -#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC -#define SCU_RAM_TR_LONG_BUF_26__W 16 -#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED -#define SCU_RAM_TR_LONG_BUF_27__W 16 -#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE -#define SCU_RAM_TR_LONG_BUF_28__W 16 -#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF -#define SCU_RAM_TR_LONG_BUF_29__W 16 -#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 -#define SCU_RAM_TR_LONG_BUF_30__W 16 -#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 - -#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 -#define SCU_RAM_TR_LONG_BUF_31__W 16 -#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF -#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 -#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 -#define SCU_RAM_ATV_AMS_MAX__W 11 -#define SCU_RAM_ATV_AMS_MAX__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 - -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 - -#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 -#define SCU_RAM_ATV_AMS_MIN__W 11 -#define SCU_RAM_ATV_AMS_MIN__M 0x7FF -#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF - -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF -#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF - -#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 -#define SCU_RAM_ATV_FIELD_CNT__W 9 -#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF -#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF -#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 -#define SCU_RAM_ATV_AAGC_FAST__W 1 -#define SCU_RAM_ATV_AAGC_FAST__M 0x1 -#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 - -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 -#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 - -#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 -#define SCU_RAM_ATV_AAGC_LP2__W 16 -#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF -#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 - -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF -#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 - -#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 -#define SCU_RAM_ATV_BP_LVL__W 11 -#define SCU_RAM_ATV_BP_LVL__M 0x7FF -#define SCU_RAM_ATV_BP_LVL__PRE 0x0 - -#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 -#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 -#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF -#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 - -#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 -#define SCU_RAM_ATV_BP_RELY__W 8 -#define SCU_RAM_ATV_BP_RELY__M 0xFF -#define SCU_RAM_ATV_BP_RELY__PRE 0x0 - -#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 -#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 -#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF -#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 - -#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 -#define SCU_RAM_ATV_BP_MTA__W 14 -#define SCU_RAM_ATV_BP_MTA__M 0x3FFF -#define SCU_RAM_ATV_BP_MTA__PRE 0x0 - -#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 -#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 -#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF -#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 - -#define SCU_RAM_ATV_BP_REF__A 0x831EFA -#define SCU_RAM_ATV_BP_REF__W 11 -#define SCU_RAM_ATV_BP_REF__M 0x7FF -#define SCU_RAM_ATV_BP_REF__PRE 0x0 - -#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 -#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 -#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF -#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 - -#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB -#define SCU_RAM_ATV_BP_REF_MIN__W 11 -#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64 - -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64 - -#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC -#define SCU_RAM_ATV_BP_REF_MAX__W 11 -#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104 - -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF -#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104 - -#define SCU_RAM_ATV_BP_CNT__A 0x831EFD -#define SCU_RAM_ATV_BP_CNT__W 8 -#define SCU_RAM_ATV_BP_CNT__M 0xFF -#define SCU_RAM_ATV_BP_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 -#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 -#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF -#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE -#define SCU_RAM_ATV_BP_XD_CNT__W 12 -#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF -#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF -#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 - -#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF -#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445 - -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445 - -#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 -#define SCU_RAM_ATV_BPC_KI_MIN__W 12 -#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223 - -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223 - - -#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01 -#define SCU_RAM_OFDM_AGC_POW_TGT__W 15 -#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF -#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848 - -#define SCU_RAM_OFDM_RSV_01__A 0x831F02 -#define SCU_RAM_OFDM_RSV_01__W 16 -#define SCU_RAM_OFDM_RSV_01__M 0xFFFF -#define SCU_RAM_OFDM_RSV_01__PRE 0x0 - -#define SCU_RAM_OFDM_RSV_02__A 0x831F03 -#define SCU_RAM_OFDM_RSV_02__W 16 -#define SCU_RAM_OFDM_RSV_02__M 0xFFFF -#define SCU_RAM_OFDM_RSV_02__PRE 0x0 -#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04 -#define SCU_RAM_FEC_PRE_RS_BER__W 16 -#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0 - -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0 -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16 -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0 - -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0 - -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16 -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06 -#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16 -#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16 -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07 -#define SCU_RAM_ATV_VSYNC_PERIOD__W 16 -#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0 - -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16 -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF -#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0 - -#define SCU_RAM_FREE_7944__A 0x831F08 -#define SCU_RAM_FREE_7944__W 16 -#define SCU_RAM_FREE_7944__M 0xFFFF -#define SCU_RAM_FREE_7944__PRE 0x0 - -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7945__A 0x831F09 -#define SCU_RAM_FREE_7945__W 16 -#define SCU_RAM_FREE_7945__M 0xFFFF -#define SCU_RAM_FREE_7945__PRE 0x0 - -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7946__A 0x831F0A -#define SCU_RAM_FREE_7946__W 16 -#define SCU_RAM_FREE_7946__M 0xFFFF -#define SCU_RAM_FREE_7946__PRE 0x0 - -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7947__A 0x831F0B -#define SCU_RAM_FREE_7947__W 16 -#define SCU_RAM_FREE_7947__M 0xFFFF -#define SCU_RAM_FREE_7947__PRE 0x0 - -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7948__A 0x831F0C -#define SCU_RAM_FREE_7948__W 16 -#define SCU_RAM_FREE_7948__M 0xFFFF -#define SCU_RAM_FREE_7948__PRE 0x0 - -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7949__A 0x831F0D -#define SCU_RAM_FREE_7949__W 16 -#define SCU_RAM_FREE_7949__M 0xFFFF -#define SCU_RAM_FREE_7949__PRE 0x0 - -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7950__A 0x831F0E -#define SCU_RAM_FREE_7950__W 16 -#define SCU_RAM_FREE_7950__M 0xFFFF -#define SCU_RAM_FREE_7950__PRE 0x0 - -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7951__A 0x831F0F -#define SCU_RAM_FREE_7951__W 16 -#define SCU_RAM_FREE_7951__M 0xFFFF -#define SCU_RAM_FREE_7951__PRE 0x0 - -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7952__A 0x831F10 -#define SCU_RAM_FREE_7952__W 16 -#define SCU_RAM_FREE_7952__M 0xFFFF -#define SCU_RAM_FREE_7952__PRE 0x0 - -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7953__A 0x831F11 -#define SCU_RAM_FREE_7953__W 16 -#define SCU_RAM_FREE_7953__M 0xFFFF -#define SCU_RAM_FREE_7953__PRE 0x0 - -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7954__A 0x831F12 -#define SCU_RAM_FREE_7954__W 16 -#define SCU_RAM_FREE_7954__M 0xFFFF -#define SCU_RAM_FREE_7954__PRE 0x0 - -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7955__A 0x831F13 -#define SCU_RAM_FREE_7955__W 16 -#define SCU_RAM_FREE_7955__M 0xFFFF -#define SCU_RAM_FREE_7955__PRE 0x0 - -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0 - - -#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14 -#define SCU_RAM_ADC_COMP_CONTROL__W 3 -#define SCU_RAM_ADC_COMP_CONTROL__M 0x7 -#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0 -#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0 -#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1 -#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2 -#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3 - - -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32 - -#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16 -#define SCU_RAM_AGC_KI_CYCCNT__W 16 -#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF -#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 - -#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 -#define SCU_RAM_AGC_KI_CYCLEN__W 16 -#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF -#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4 - -#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 -#define SCU_RAM_AGC_SNS_CYCLEN__W 16 -#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF -#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4 - -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF - -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01 - -#define SCU_RAM_AGC_RF_MAX__A 0x831F1B -#define SCU_RAM_AGC_RF_MAX__W 15 -#define SCU_RAM_AGC_RF_MAX__M 0x7FFF -#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF -#define SCU_RAM_FREE_7964__A 0x831F1C -#define SCU_RAM_FREE_7964__W 16 -#define SCU_RAM_FREE_7964__M 0xFFFF -#define SCU_RAM_FREE_7964__PRE 0x0 - -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7965__A 0x831F1D -#define SCU_RAM_FREE_7965__W 16 -#define SCU_RAM_FREE_7965__M 0xFFFF -#define SCU_RAM_FREE_7965__PRE 0x0 - -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7966__A 0x831F1E -#define SCU_RAM_FREE_7966__W 16 -#define SCU_RAM_FREE_7966__M 0xFFFF -#define SCU_RAM_FREE_7966__PRE 0x0 - -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7967__A 0x831F1F -#define SCU_RAM_FREE_7967__W 16 -#define SCU_RAM_FREE_7967__M 0xFFFF -#define SCU_RAM_FREE_7967__PRE 0x0 - -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20 -#define SCU_RAM_QAM_PARAM_MIRRORING__W 8 -#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF -#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1 - -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2 - -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0 -#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4 - -#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21 -#define SCU_RAM_QAM_PARAM_OPTIONS__W 8 -#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF -#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1 - -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2 - -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0 -#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10 - -#define SCU_RAM_FREE_7970__A 0x831F22 -#define SCU_RAM_FREE_7970__W 16 -#define SCU_RAM_FREE_7970__M 0xFFFF -#define SCU_RAM_FREE_7970__PRE 0x0 - -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_FREE_7971__A 0x831F23 -#define SCU_RAM_FREE_7971__W 16 -#define SCU_RAM_FREE_7971__M 0xFFFF -#define SCU_RAM_FREE_7971__PRE 0x0 - -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0 -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16 -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF -#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG__A 0x831F24 -#define SCU_RAM_AGC_CONFIG__W 16 -#define SCU_RAM_AGC_CONFIG__M 0xFFFF -#define SCU_RAM_AGC_CONFIG__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2 -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1 -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4 -#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0 - -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0 - -#define SCU_RAM_AGC_KI__A 0x831F25 -#define SCU_RAM_AGC_KI__W 15 -#define SCU_RAM_AGC_KI__M 0x7FFF -#define SCU_RAM_AGC_KI__PRE 0x22A - -#define SCU_RAM_AGC_KI_DGAIN__B 0 -#define SCU_RAM_AGC_KI_DGAIN__W 4 -#define SCU_RAM_AGC_KI_DGAIN__M 0xF -#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA - -#define SCU_RAM_AGC_KI_RF__B 4 -#define SCU_RAM_AGC_KI_RF__W 4 -#define SCU_RAM_AGC_KI_RF__M 0xF0 -#define SCU_RAM_AGC_KI_RF__PRE 0x20 - -#define SCU_RAM_AGC_KI_IF__B 8 -#define SCU_RAM_AGC_KI_IF__W 4 -#define SCU_RAM_AGC_KI_IF__M 0xF00 -#define SCU_RAM_AGC_KI_IF__PRE 0x200 - -#define SCU_RAM_AGC_KI_RED__A 0x831F26 -#define SCU_RAM_AGC_KI_RED__W 6 -#define SCU_RAM_AGC_KI_RED__M 0x3F -#define SCU_RAM_AGC_KI_RED__PRE 0x0 - -#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 -#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 -#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 -#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 - -#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC -#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 - -#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 - - -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 - -#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 -#define SCU_RAM_AGC_KI_MINGAIN__W 16 -#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000 - -#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 -#define SCU_RAM_AGC_KI_MAXGAIN__W 16 -#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF -#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 - -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 -#define SCU_RAM_AGC_KI_MIN__A 0x831F2B -#define SCU_RAM_AGC_KI_MIN__W 12 -#define SCU_RAM_AGC_KI_MIN__M 0xFFF -#define SCU_RAM_AGC_KI_MIN__PRE 0x111 - -#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 -#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 -#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF -#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1 - -#define SCU_RAM_AGC_KI_MIN_RF__B 4 -#define SCU_RAM_AGC_KI_MIN_RF__W 4 -#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 -#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10 - -#define SCU_RAM_AGC_KI_MIN_IF__B 8 -#define SCU_RAM_AGC_KI_MIN_IF__W 4 -#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 -#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100 - -#define SCU_RAM_AGC_KI_MAX__A 0x831F2C -#define SCU_RAM_AGC_KI_MAX__W 12 -#define SCU_RAM_AGC_KI_MAX__M 0xFFF -#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF - -#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 -#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 -#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF -#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF - -#define SCU_RAM_AGC_KI_MAX_RF__B 4 -#define SCU_RAM_AGC_KI_MAX_RF__W 4 -#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 -#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0 - -#define SCU_RAM_AGC_KI_MAX_IF__B 8 -#define SCU_RAM_AGC_KI_MAX_IF__W 4 -#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 -#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00 - - -#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D -#define SCU_RAM_AGC_CLP_SUM__W 16 -#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF -#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 - -#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E -#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 -#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF -#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8 - -#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F -#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 -#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF -#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400 - -#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 -#define SCU_RAM_AGC_CLP_CYCLEN__W 16 -#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF -#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4 - -#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 -#define SCU_RAM_AGC_CLP_CYCCNT__W 16 -#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF -#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 - -#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 -#define SCU_RAM_AGC_CLP_DIR_TO__W 8 -#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF -#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC - -#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 -#define SCU_RAM_AGC_CLP_DIR_WD__W 8 -#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF -#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 - -#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 -#define SCU_RAM_AGC_CLP_DIR_STP__W 16 -#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF -#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1 - -#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 -#define SCU_RAM_AGC_SNS_SUM__W 16 -#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF -#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 - -#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 -#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 -#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF -#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8 - -#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 -#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 -#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF -#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400 - -#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 -#define SCU_RAM_AGC_SNS_CYCCNT__W 16 -#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF -#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 - -#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 -#define SCU_RAM_AGC_SNS_DIR_TO__W 8 -#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF -#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC - -#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A -#define SCU_RAM_AGC_SNS_DIR_WD__W 8 -#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF -#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 - -#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B -#define SCU_RAM_AGC_SNS_DIR_STP__W 16 -#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF -#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1 - -#define SCU_RAM_AGC_INGAIN__A 0x831F3C -#define SCU_RAM_AGC_INGAIN__W 16 -#define SCU_RAM_AGC_INGAIN__M 0xFFFF -#define SCU_RAM_AGC_INGAIN__PRE 0x708 - -#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D -#define SCU_RAM_AGC_INGAIN_TGT__W 15 -#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF -#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708 - -#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E -#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 -#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF -#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708 - -#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F -#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 -#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF -#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF - -#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 -#define SCU_RAM_AGC_IF_IACCU_HI__W 16 -#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF -#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 - -#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 -#define SCU_RAM_AGC_IF_IACCU_LO__W 8 -#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF -#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 - -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008 - -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 - -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C - -#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 -#define SCU_RAM_AGC_RF_IACCU_HI__W 16 -#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF -#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 - -#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 -#define SCU_RAM_AGC_RF_IACCU_LO__W 8 -#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF -#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 - -#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 -#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 -#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF -#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 -#define SCU_RAM_ATV_STANDARD__A 0x831F48 -#define SCU_RAM_ATV_STANDARD__W 12 -#define SCU_RAM_ATV_STANDARD__M 0xFFF -#define SCU_RAM_ATV_STANDARD__PRE 0x2 - -#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 -#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 -#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF -#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2 -#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 -#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 -#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 -#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 -#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 -#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 -#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA -#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 - -#define SCU_RAM_ATV_DETECT__A 0x831F49 -#define SCU_RAM_ATV_DETECT__W 1 -#define SCU_RAM_ATV_DETECT__M 0x1 -#define SCU_RAM_ATV_DETECT__PRE 0x0 - -#define SCU_RAM_ATV_DETECT_DETECT__B 0 -#define SCU_RAM_ATV_DETECT_DETECT__W 1 -#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 -#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 -#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 -#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 - -#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A -#define SCU_RAM_ATV_DETECT_TH__W 8 -#define SCU_RAM_ATV_DETECT_TH__M 0xFF -#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F - -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF -#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F - -#define SCU_RAM_ATV_LOCK__A 0x831F4B -#define SCU_RAM_ATV_LOCK__W 2 -#define SCU_RAM_ATV_LOCK__M 0x3 -#define SCU_RAM_ATV_LOCK__PRE 0x0 - -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 -#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 - -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 -#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 - -#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C -#define SCU_RAM_ATV_CR_LOCK__W 11 -#define SCU_RAM_ATV_CR_LOCK__M 0x7FF -#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 - -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF -#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 - -#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D -#define SCU_RAM_ATV_AGC_MODE__W 8 -#define SCU_RAM_ATV_AGC_MODE__M 0xFF -#define SCU_RAM_ATV_AGC_MODE__PRE 0x50 - -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 -#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 - -#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 -#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 -#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 -#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 -#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 -#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 - -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 -#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 - -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 -#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 - -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 -#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 - - -#define SCU_RAM_ATV_RSV_01__A 0x831F4E -#define SCU_RAM_ATV_RSV_01__W 16 -#define SCU_RAM_ATV_RSV_01__M 0xFFFF -#define SCU_RAM_ATV_RSV_01__PRE 0x0 - -#define SCU_RAM_ATV_RSV_02__A 0x831F4F -#define SCU_RAM_ATV_RSV_02__W 16 -#define SCU_RAM_ATV_RSV_02__M 0xFFFF -#define SCU_RAM_ATV_RSV_02__PRE 0x0 - -#define SCU_RAM_ATV_RSV_03__A 0x831F50 -#define SCU_RAM_ATV_RSV_03__W 16 -#define SCU_RAM_ATV_RSV_03__M 0xFFFF -#define SCU_RAM_ATV_RSV_03__PRE 0x0 - -#define SCU_RAM_ATV_RSV_04__A 0x831F51 -#define SCU_RAM_ATV_RSV_04__W 16 -#define SCU_RAM_ATV_RSV_04__M 0xFFFF -#define SCU_RAM_ATV_RSV_04__PRE 0x0 -#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 -#define SCU_RAM_ATV_FAGC_TH_RED__W 8 -#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF -#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA - -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF -#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA - -#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 -#define SCU_RAM_ATV_AMS_MAX_REF__W 11 -#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC - -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 -#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A - -#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 -#define SCU_RAM_ATV_ACT_AMX__W 11 -#define SCU_RAM_ATV_ACT_AMX__M 0x7FF -#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 - -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF -#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 - -#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 -#define SCU_RAM_ATV_ACT_AMI__W 11 -#define SCU_RAM_ATV_ACT_AMI__M 0x7FF -#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 - -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF -#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56 -#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16 -#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0 -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16 -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57 -#define SCU_RAM_ATV_BPC_REF_CNT__W 16 -#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0 - -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0 -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16 -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF -#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0 - - -#define SCU_RAM_ATV_RSV_07__A 0x831F58 -#define SCU_RAM_ATV_RSV_07__W 16 -#define SCU_RAM_ATV_RSV_07__M 0xFFFF -#define SCU_RAM_ATV_RSV_07__PRE 0x0 - -#define SCU_RAM_ATV_RSV_08__A 0x831F59 -#define SCU_RAM_ATV_RSV_08__W 16 -#define SCU_RAM_ATV_RSV_08__M 0xFFFF -#define SCU_RAM_ATV_RSV_08__PRE 0x0 - -#define SCU_RAM_ATV_RSV_09__A 0x831F5A -#define SCU_RAM_ATV_RSV_09__W 16 -#define SCU_RAM_ATV_RSV_09__M 0xFFFF -#define SCU_RAM_ATV_RSV_09__PRE 0x0 - -#define SCU_RAM_ATV_RSV_10__A 0x831F5B -#define SCU_RAM_ATV_RSV_10__W 16 -#define SCU_RAM_ATV_RSV_10__M 0xFFFF -#define SCU_RAM_ATV_RSV_10__PRE 0x0 - -#define SCU_RAM_ATV_RSV_11__A 0x831F5C -#define SCU_RAM_ATV_RSV_11__W 16 -#define SCU_RAM_ATV_RSV_11__M 0xFFFF -#define SCU_RAM_ATV_RSV_11__PRE 0x0 - -#define SCU_RAM_ATV_RSV_12__A 0x831F5D -#define SCU_RAM_ATV_RSV_12__W 16 -#define SCU_RAM_ATV_RSV_12__M 0xFFFF -#define SCU_RAM_ATV_RSV_12__PRE 0x0 -#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E -#define SCU_RAM_ATV_VID_GAIN_HI__W 16 -#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF -#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000 - -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF -#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000 - -#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F -#define SCU_RAM_ATV_VID_GAIN_LO__W 8 -#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF -#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 - -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF -#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 - - -#define SCU_RAM_ATV_RSV_13__A 0x831F60 -#define SCU_RAM_ATV_RSV_13__W 16 -#define SCU_RAM_ATV_RSV_13__M 0xFFFF -#define SCU_RAM_ATV_RSV_13__PRE 0x0 - -#define SCU_RAM_ATV_RSV_14__A 0x831F61 -#define SCU_RAM_ATV_RSV_14__W 16 -#define SCU_RAM_ATV_RSV_14__M 0xFFFF -#define SCU_RAM_ATV_RSV_14__PRE 0x0 - -#define SCU_RAM_ATV_RSV_15__A 0x831F62 -#define SCU_RAM_ATV_RSV_15__W 16 -#define SCU_RAM_ATV_RSV_15__M 0xFFFF -#define SCU_RAM_ATV_RSV_15__PRE 0x0 - -#define SCU_RAM_ATV_RSV_16__A 0x831F63 -#define SCU_RAM_ATV_RSV_16__W 16 -#define SCU_RAM_ATV_RSV_16__M 0xFFFF -#define SCU_RAM_ATV_RSV_16__PRE 0x0 -#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 -#define SCU_RAM_ATV_AAGC_CNT__W 8 -#define SCU_RAM_ATV_AAGC_CNT__M 0xFF -#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7 - -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF -#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7 - -#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 -#define SCU_RAM_ATV_SIF_GAIN__W 11 -#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF -#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80 - -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF -#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80 - - -#define SCU_RAM_ATV_RSV_17__A 0x831F66 -#define SCU_RAM_ATV_RSV_17__W 16 -#define SCU_RAM_ATV_RSV_17__M 0xFFFF -#define SCU_RAM_ATV_RSV_17__PRE 0x0 - -#define SCU_RAM_ATV_RSV_18__A 0x831F67 -#define SCU_RAM_ATV_RSV_18__W 16 -#define SCU_RAM_ATV_RSV_18__M 0xFFFF -#define SCU_RAM_ATV_RSV_18__PRE 0x0 - -#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 -#define SCU_RAM_ATV_RATE_OFS__W 12 -#define SCU_RAM_ATV_RATE_OFS__M 0xFFF -#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 - -#define SCU_RAM_ATV_LO_INCR__A 0x831F69 -#define SCU_RAM_ATV_LO_INCR__W 12 -#define SCU_RAM_ATV_LO_INCR__M 0xFFF -#define SCU_RAM_ATV_LO_INCR__PRE 0x0 - -#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A -#define SCU_RAM_ATV_IIR_CRIT__W 12 -#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF -#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 - -#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B -#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 -#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF -#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 - -#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C -#define SCU_RAM_ATV_DEF_LO_INCR__W 12 -#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF -#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 - -#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D -#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 -#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 -#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 -#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E -#define SCU_RAM_ATV_MOD_CONTROL__W 12 -#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF -#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 - -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0 - -#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F -#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 -#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667 - -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667 - -#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 -#define SCU_RAM_ATV_BPC_KI_MAX__W 12 -#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337 - -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337 - -#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 -#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 -#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447 - -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0 -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12 -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447 - -#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 -#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225 - -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF -#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225 - -#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 -#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 -#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF -#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14 - -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 -#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 - -#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 -#define SCU_RAM_QAM_PARAM_ANNEX__W 2 -#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 -#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1 - -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 -#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 - -#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 -#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 -#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 -#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5 - -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 -#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 - -#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 -#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 -#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF -#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1 - -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE -#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 -#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 -#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF -#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13 - -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF -#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13 - -#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A -#define SCU_RAM_QAM_WR_RSV_0__W 16 -#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 - -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D -#define SCU_RAM_QAM_WR_RSV_5__W 16 -#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E -#define SCU_RAM_QAM_WR_RSV_6__W 16 -#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F -#define SCU_RAM_QAM_WR_RSV_7__W 16 -#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 -#define SCU_RAM_QAM_WR_RSV_8__W 16 -#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 -#define SCU_RAM_QAM_WR_RSV_9__W 16 -#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 -#define SCU_RAM_QAM_WR_RSV_10__W 16 -#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 -#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 -#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF -#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258 - -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258 -#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 - -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B -#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 -#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 -#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 - -#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D -#define SCU_RAM_QAM_FSM_ATH__W 16 -#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF -#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 - -#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 -#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 -#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__W 16 -#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B - -#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 -#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D - -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__W 16 -#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C - -#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 -#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 - -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__W 16 -#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_PTH__PRE 0x64 - -#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 -#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 - -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__W 16 -#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E - -#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C -#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 - -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__W 16 -#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_CTH__PRE 0x50 - -#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50 -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C -#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C - -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__W 16 -#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF -#define SCU_RAM_QAM_FSM_QTH__PRE 0x96 - -#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 -#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 -#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96 -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C -#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 - -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 -#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28 - -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 -#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 - -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 -#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF - -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 -#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 - -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 -#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF -#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4 - -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 -#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 - -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__W 16 -#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 -#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28 - -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__W 16 -#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF - -#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF - -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__W 16 -#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64 - -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64 - -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E - -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E - -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__W 16 -#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5 - -#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5 - -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__W 16 -#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32 - -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32 - -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E - -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E - -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__W 16 -#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5 - -#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5 - -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__W 16 -#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18 - -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__W 16 -#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC - -#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC - -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__W 16 -#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10 - -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__W 16 -#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC - -#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC - -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 - -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 - -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 - -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 - -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 - -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 - -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA - -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 - -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 - -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__W 16 -#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF -#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00 - -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF -#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00 - -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 - -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE - -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A - -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 - -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 - -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF - -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 - -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 - -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 - -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D - -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 - -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 - -#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 -#define SCU_RAM_QAM_CTL_ENA__W 16 -#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF -#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF - -#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 -#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 -#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 -#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1 - -#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 -#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 -#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 -#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2 - -#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 -#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 -#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 -#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4 - -#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 -#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 -#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 -#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8 - -#define SCU_RAM_QAM_CTL_ENA_LC__B 4 -#define SCU_RAM_QAM_CTL_ENA_LC__W 1 -#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 -#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10 - -#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 -#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 -#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 -#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20 - -#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 -#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 -#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 -#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40 - -#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 -#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 -#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 -#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80 - -#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 -#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 -#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 -#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100 - -#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 -#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 -#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 -#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200 - -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 -#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400 - -#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 -#define SCU_RAM_QAM_WR_RSV_1__W 16 -#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 -#define SCU_RAM_QAM_WR_RSV_2__W 16 -#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 -#define SCU_RAM_QAM_WR_RSV_3__W 16 -#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 - -#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 -#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 -#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF -#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 -#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 - -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1 - -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 -#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE - -#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 -#define SCU_RAM_QAM_RD_RSV_4__W 16 -#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 - -#define SCU_RAM_QAM_LOCKED__A 0x831FBA -#define SCU_RAM_QAM_LOCKED__W 16 -#define SCU_RAM_QAM_LOCKED__M 0xFFFF -#define SCU_RAM_QAM_LOCKED__PRE 0x0 - -#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 -#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 -#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF -#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 -#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 - -#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 -#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 -#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 -#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 -#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 -#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 -#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 -#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 - -#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB -#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 -#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 -#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 -#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 -#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 -#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 -#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 -#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC -#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 -#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 -#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 -#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 -#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 -#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 -#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 -#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 -#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD -#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE -#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 - -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF -#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 -#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 -#define SCU_RAM_QAM_TASKLETS_RUN__W 16 -#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 - -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF -#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 - -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF -#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 -#define SCU_RAM_QAM_RD_RSV_5__W 16 -#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 -#define SCU_RAM_QAM_RD_RSV_6__W 16 -#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 -#define SCU_RAM_QAM_RD_RSV_7__W 16 -#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 -#define SCU_RAM_QAM_RD_RSV_8__W 16 -#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 -#define SCU_RAM_QAM_RD_RSV_9__W 16 -#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 -#define SCU_RAM_QAM_RD_RSV_10__W 16 -#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 - -#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 -#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 -#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF -#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 - -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF -#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA -#define SCU_RAM_QAM_FSM_STATE__W 4 -#define SCU_RAM_QAM_FSM_STATE__M 0xF -#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 -#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 -#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB -#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 -#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF -#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 - -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF -#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0 - -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000 -#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0 - -#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD -#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 -#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46 - -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46 - -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E - -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E - -#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF -#define SCU_RAM_QAM_ERR_STATE__W 4 -#define SCU_RAM_QAM_ERR_STATE__M 0xF -#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 - -#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 -#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 -#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF -#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 -#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 -#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 -#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 -#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 - -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF -#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 - -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 -#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 - -#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 -#define SCU_RAM_QAM_EQ_LOCK__W 1 -#define SCU_RAM_QAM_EQ_LOCK__M 0x1 -#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 - -#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 -#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 -#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 -#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 - -#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 -#define SCU_RAM_QAM_EQ_STATE__W 16 -#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF -#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 - -#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 -#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 -#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF -#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 -#define SCU_RAM_QAM_RD_RSV_0__W 16 -#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 -#define SCU_RAM_QAM_RD_RSV_1__W 16 -#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 -#define SCU_RAM_QAM_RD_RSV_2__W 16 -#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 -#define SCU_RAM_QAM_RD_RSV_3__W 16 -#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 - -#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 -#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 -#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF -#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 - - -#define SCU_RAM_FREE_8151__A 0x831FD7 -#define SCU_RAM_FREE_8151__W 16 -#define SCU_RAM_FREE_8151__M 0xFFFF -#define SCU_RAM_FREE_8151__PRE 0x0 - -#define SCU_RAM_FREE_8152__A 0x831FD8 -#define SCU_RAM_FREE_8152__W 16 -#define SCU_RAM_FREE_8152__M 0xFFFF -#define SCU_RAM_FREE_8152__PRE 0x0 - -#define SCU_RAM_FREE_8153__A 0x831FD9 -#define SCU_RAM_FREE_8153__W 16 -#define SCU_RAM_FREE_8153__M 0xFFFF -#define SCU_RAM_FREE_8153__PRE 0x0 - -#define SCU_RAM_FREE_8154__A 0x831FDA -#define SCU_RAM_FREE_8154__W 16 -#define SCU_RAM_FREE_8154__M 0xFFFF -#define SCU_RAM_FREE_8154__PRE 0x0 - -#define SCU_RAM_FREE_8155__A 0x831FDB -#define SCU_RAM_FREE_8155__W 16 -#define SCU_RAM_FREE_8155__M 0xFFFF -#define SCU_RAM_FREE_8155__PRE 0x0 - -#define SCU_RAM_FREE_8156__A 0x831FDC -#define SCU_RAM_FREE_8156__W 16 -#define SCU_RAM_FREE_8156__M 0xFFFF -#define SCU_RAM_FREE_8156__PRE 0x0 - -#define SCU_RAM_FREE_8157__A 0x831FDD -#define SCU_RAM_FREE_8157__W 16 -#define SCU_RAM_FREE_8157__M 0xFFFF -#define SCU_RAM_FREE_8157__PRE 0x0 - -#define SCU_RAM_FREE_8158__A 0x831FDE -#define SCU_RAM_FREE_8158__W 16 -#define SCU_RAM_FREE_8158__M 0xFFFF -#define SCU_RAM_FREE_8158__PRE 0x0 - -#define SCU_RAM_FREE_8159__A 0x831FDF -#define SCU_RAM_FREE_8159__W 16 -#define SCU_RAM_FREE_8159__M 0xFFFF -#define SCU_RAM_FREE_8159__PRE 0x0 - -#define SCU_RAM_FREE_8160__A 0x831FE0 -#define SCU_RAM_FREE_8160__W 16 -#define SCU_RAM_FREE_8160__M 0xFFFF -#define SCU_RAM_FREE_8160__PRE 0x0 - -#define SCU_RAM_FREE_8161__A 0x831FE1 -#define SCU_RAM_FREE_8161__W 16 -#define SCU_RAM_FREE_8161__M 0xFFFF -#define SCU_RAM_FREE_8161__PRE 0x0 - -#define SCU_RAM_FREE_8162__A 0x831FE2 -#define SCU_RAM_FREE_8162__W 16 -#define SCU_RAM_FREE_8162__M 0xFFFF -#define SCU_RAM_FREE_8162__PRE 0x0 - -#define SCU_RAM_FREE_8163__A 0x831FE3 -#define SCU_RAM_FREE_8163__W 16 -#define SCU_RAM_FREE_8163__M 0xFFFF -#define SCU_RAM_FREE_8163__PRE 0x0 - -#define SCU_RAM_FREE_8164__A 0x831FE4 -#define SCU_RAM_FREE_8164__W 16 -#define SCU_RAM_FREE_8164__M 0xFFFF -#define SCU_RAM_FREE_8164__PRE 0x0 - -#define SCU_RAM_FREE_8165__A 0x831FE5 -#define SCU_RAM_FREE_8165__W 16 -#define SCU_RAM_FREE_8165__M 0xFFFF -#define SCU_RAM_FREE_8165__PRE 0x0 - -#define SCU_RAM_FREE_8166__A 0x831FE6 -#define SCU_RAM_FREE_8166__W 16 -#define SCU_RAM_FREE_8166__M 0xFFFF -#define SCU_RAM_FREE_8166__PRE 0x0 - -#define SCU_RAM_FREE_8167__A 0x831FE7 -#define SCU_RAM_FREE_8167__W 16 -#define SCU_RAM_FREE_8167__M 0xFFFF -#define SCU_RAM_FREE_8167__PRE 0x0 - -#define SCU_RAM_FREE_8168__A 0x831FE8 -#define SCU_RAM_FREE_8168__W 16 -#define SCU_RAM_FREE_8168__M 0xFFFF -#define SCU_RAM_FREE_8168__PRE 0x0 - -#define SCU_RAM_FREE_8169__A 0x831FE9 -#define SCU_RAM_FREE_8169__W 16 -#define SCU_RAM_FREE_8169__M 0xFFFF -#define SCU_RAM_FREE_8169__PRE 0x0 - -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E - -#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB -#define SCU_RAM_DRIVER_VER_HI__W 16 -#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF -#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 - -#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC -#define SCU_RAM_DRIVER_VER_LO__W 16 -#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF -#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 - -#define SCU_RAM_PARAM_15__A 0x831FED -#define SCU_RAM_PARAM_15__W 16 -#define SCU_RAM_PARAM_15__M 0xFFFF -#define SCU_RAM_PARAM_15__PRE 0x0 - -#define SCU_RAM_PARAM_14__A 0x831FEE -#define SCU_RAM_PARAM_14__W 16 -#define SCU_RAM_PARAM_14__M 0xFFFF -#define SCU_RAM_PARAM_14__PRE 0x0 - -#define SCU_RAM_PARAM_13__A 0x831FEF -#define SCU_RAM_PARAM_13__W 16 -#define SCU_RAM_PARAM_13__M 0xFFFF -#define SCU_RAM_PARAM_13__PRE 0x0 - -#define SCU_RAM_PARAM_12__A 0x831FF0 -#define SCU_RAM_PARAM_12__W 16 -#define SCU_RAM_PARAM_12__M 0xFFFF -#define SCU_RAM_PARAM_12__PRE 0x0 - -#define SCU_RAM_PARAM_11__A 0x831FF1 -#define SCU_RAM_PARAM_11__W 16 -#define SCU_RAM_PARAM_11__M 0xFFFF -#define SCU_RAM_PARAM_11__PRE 0x0 - -#define SCU_RAM_PARAM_10__A 0x831FF2 -#define SCU_RAM_PARAM_10__W 16 -#define SCU_RAM_PARAM_10__M 0xFFFF -#define SCU_RAM_PARAM_10__PRE 0x0 - -#define SCU_RAM_PARAM_9__A 0x831FF3 -#define SCU_RAM_PARAM_9__W 16 -#define SCU_RAM_PARAM_9__M 0xFFFF -#define SCU_RAM_PARAM_9__PRE 0x0 - -#define SCU_RAM_PARAM_8__A 0x831FF4 -#define SCU_RAM_PARAM_8__W 16 -#define SCU_RAM_PARAM_8__M 0xFFFF -#define SCU_RAM_PARAM_8__PRE 0x0 - -#define SCU_RAM_PARAM_7__A 0x831FF5 -#define SCU_RAM_PARAM_7__W 16 -#define SCU_RAM_PARAM_7__M 0xFFFF -#define SCU_RAM_PARAM_7__PRE 0x0 - -#define SCU_RAM_PARAM_6__A 0x831FF6 -#define SCU_RAM_PARAM_6__W 16 -#define SCU_RAM_PARAM_6__M 0xFFFF -#define SCU_RAM_PARAM_6__PRE 0x0 - -#define SCU_RAM_PARAM_5__A 0x831FF7 -#define SCU_RAM_PARAM_5__W 16 -#define SCU_RAM_PARAM_5__M 0xFFFF -#define SCU_RAM_PARAM_5__PRE 0x0 - -#define SCU_RAM_PARAM_4__A 0x831FF8 -#define SCU_RAM_PARAM_4__W 16 -#define SCU_RAM_PARAM_4__M 0xFFFF -#define SCU_RAM_PARAM_4__PRE 0x0 - -#define SCU_RAM_PARAM_3__A 0x831FF9 -#define SCU_RAM_PARAM_3__W 16 -#define SCU_RAM_PARAM_3__M 0xFFFF -#define SCU_RAM_PARAM_3__PRE 0x0 - -#define SCU_RAM_PARAM_2__A 0x831FFA -#define SCU_RAM_PARAM_2__W 16 -#define SCU_RAM_PARAM_2__M 0xFFFF -#define SCU_RAM_PARAM_2__PRE 0x0 - -#define SCU_RAM_PARAM_1__A 0x831FFB -#define SCU_RAM_PARAM_1__W 16 -#define SCU_RAM_PARAM_1__M 0xFFFF -#define SCU_RAM_PARAM_1__PRE 0x0 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 - - -#define SCU_RAM_PARAM_0__A 0x831FFC -#define SCU_RAM_PARAM_0__W 16 -#define SCU_RAM_PARAM_0__M 0xFFFF -#define SCU_RAM_PARAM_0__PRE 0x0 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 -#define SCU_RAM_PARAM_0_RESULT_OK 0x0 -#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF -#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE -#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD -#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC - - -#define SCU_RAM_COMMAND__A 0x831FFD -#define SCU_RAM_COMMAND__W 16 -#define SCU_RAM_COMMAND__M 0xFFFF -#define SCU_RAM_COMMAND__PRE 0x0 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 -#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 -#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 -#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 -#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 -#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 -#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 -#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 -#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 -#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 -#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 -#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 -#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 -#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85 -#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86 -#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87 -#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF -#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE -#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD -#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 -#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1 - -#define SCU_RAM_COMMAND_STANDARD__B 8 -#define SCU_RAM_COMMAND_STANDARD__W 8 -#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 -#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 -#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 -#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 - -#define SCU_RAM_VERSION_HI__A 0x831FFE -#define SCU_RAM_VERSION_HI__W 16 -#define SCU_RAM_VERSION_HI__M 0xFFFF -#define SCU_RAM_VERSION_HI__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 -#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 - -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF -#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 - -#define SCU_RAM_VERSION_LO__A 0x831FFF -#define SCU_RAM_VERSION_LO__W 16 -#define SCU_RAM_VERSION_LO__M 0xFFFF -#define SCU_RAM_VERSION_LO__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 -#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 -#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 -#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 - -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF -#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 - - - - - -#define SIO_COMM_EXEC__A 0x400000 -#define SIO_COMM_EXEC__W 2 -#define SIO_COMM_EXEC__M 0x3 -#define SIO_COMM_EXEC__PRE 0x0 -#define SIO_COMM_EXEC_STOP 0x0 -#define SIO_COMM_EXEC_ACTIVE 0x1 -#define SIO_COMM_EXEC_HOLD 0x2 - -#define SIO_COMM_STATE__A 0x400001 -#define SIO_COMM_STATE__W 16 -#define SIO_COMM_STATE__M 0xFFFF -#define SIO_COMM_STATE__PRE 0x0 -#define SIO_COMM_MB__A 0x400002 -#define SIO_COMM_MB__W 16 -#define SIO_COMM_MB__M 0xFFFF -#define SIO_COMM_MB__PRE 0x0 -#define SIO_COMM_INT_REQ__A 0x400003 -#define SIO_COMM_INT_REQ__W 16 -#define SIO_COMM_INT_REQ__M 0xFFFF -#define SIO_COMM_INT_REQ__PRE 0x0 - -#define SIO_COMM_INT_REQ_HI_REQ__B 0 -#define SIO_COMM_INT_REQ_HI_REQ__W 1 -#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 -#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 - -#define SIO_COMM_INT_REQ_SA_REQ__B 1 -#define SIO_COMM_INT_REQ_SA_REQ__W 1 -#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 -#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 - -#define SIO_COMM_INT_REQ_BL_REQ__B 2 -#define SIO_COMM_INT_REQ_BL_REQ__W 1 -#define SIO_COMM_INT_REQ_BL_REQ__M 0x4 -#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0 - -#define SIO_COMM_INT_STA__A 0x400005 -#define SIO_COMM_INT_STA__W 16 -#define SIO_COMM_INT_STA__M 0xFFFF -#define SIO_COMM_INT_STA__PRE 0x0 -#define SIO_COMM_INT_MSK__A 0x400006 -#define SIO_COMM_INT_MSK__W 16 -#define SIO_COMM_INT_MSK__M 0xFFFF -#define SIO_COMM_INT_MSK__PRE 0x0 -#define SIO_COMM_INT_STM__A 0x400007 -#define SIO_COMM_INT_STM__W 16 -#define SIO_COMM_INT_STM__M 0xFFFF -#define SIO_COMM_INT_STM__PRE 0x0 - - - -#define SIO_TOP_COMM_EXEC__A 0x410000 -#define SIO_TOP_COMM_EXEC__W 2 -#define SIO_TOP_COMM_EXEC__M 0x3 -#define SIO_TOP_COMM_EXEC__PRE 0x0 -#define SIO_TOP_COMM_EXEC_STOP 0x0 -#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 -#define SIO_TOP_COMM_EXEC_HOLD 0x2 - - -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__W 16 -#define SIO_TOP_COMM_KEY__M 0xFFFF -#define SIO_TOP_COMM_KEY__PRE 0x0 -#define SIO_TOP_COMM_KEY_KEY 0xFABA - - -#define SIO_TOP_JTAGID_LO__A 0x410012 -#define SIO_TOP_JTAGID_LO__W 16 -#define SIO_TOP_JTAGID_LO__M 0xFFFF -#define SIO_TOP_JTAGID_LO__PRE 0x0 - -#define SIO_TOP_JTAGID_HI__A 0x410013 -#define SIO_TOP_JTAGID_HI__W 16 -#define SIO_TOP_JTAGID_HI__M 0xFFFF -#define SIO_TOP_JTAGID_HI__PRE 0x0 - - - - -#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 -#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 -#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 -#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 -#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 -#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F -#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 - -#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 -#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 -#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 -#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 -#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 -#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 -#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF -#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 -#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 -#define SIO_HI_RA_RAM_S0_STATE__W 1 -#define SIO_HI_RA_RAM_S0_STATE__M 0x1 -#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 -#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 -#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 -#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF -#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 - -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 - -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 - -#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 -#define SIO_HI_RA_RAM_S0_ADDR__W 16 -#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 - - -#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 -#define SIO_HI_RA_RAM_S0_CRC__W 16 -#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF -#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 -#define SIO_HI_RA_RAM_S0_BUFFER__W 16 -#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF -#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 -#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 -#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF -#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A -#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 -#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 -#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B -#define SIO_HI_RA_RAM_S0_TEMP0__W 16 -#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF -#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C -#define SIO_HI_RA_RAM_S0_TEMP1__W 16 -#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF -#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 - -#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D -#define SIO_HI_RA_RAM_S0_OFFSET__W 16 -#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF -#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 -#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 -#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 -#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 -#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 -#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F -#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 - -#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 -#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 -#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 -#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 -#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 -#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 -#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF -#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 -#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 -#define SIO_HI_RA_RAM_S1_STATE__W 1 -#define SIO_HI_RA_RAM_S1_STATE__M 0x1 -#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 -#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 -#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 -#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF -#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 - -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 - -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 - -#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 -#define SIO_HI_RA_RAM_S1_ADDR__W 16 -#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF -#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 - - -#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 -#define SIO_HI_RA_RAM_S1_CRC__W 16 -#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF -#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 -#define SIO_HI_RA_RAM_S1_BUFFER__W 16 -#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF -#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 -#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 -#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF -#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A -#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 -#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 -#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B -#define SIO_HI_RA_RAM_S1_TEMP0__W 16 -#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF -#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C -#define SIO_HI_RA_RAM_S1_TEMP1__W 16 -#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF -#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 - -#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D -#define SIO_HI_RA_RAM_S1_OFFSET__W 16 -#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF -#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 -#define SIO_HI_RA_RAM_SEMA__A 0x420030 -#define SIO_HI_RA_RAM_SEMA__W 1 -#define SIO_HI_RA_RAM_SEMA__M 0x1 -#define SIO_HI_RA_RAM_SEMA__PRE 0x0 -#define SIO_HI_RA_RAM_SEMA_FREE 0x0 -#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 - -#define SIO_HI_RA_RAM_RES__A 0x420031 -#define SIO_HI_RA_RAM_RES__W 3 -#define SIO_HI_RA_RAM_RES__M 0x7 -#define SIO_HI_RA_RAM_RES__PRE 0x0 -#define SIO_HI_RA_RAM_RES_OK 0x0 -#define SIO_HI_RA_RAM_RES_ERROR 0x1 -#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 -#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 -#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 -#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 - -#define SIO_HI_RA_RAM_CMD__A 0x420032 -#define SIO_HI_RA_RAM_CMD__W 4 -#define SIO_HI_RA_RAM_CMD__M 0xF -#define SIO_HI_RA_RAM_CMD__PRE 0x0 -#define SIO_HI_RA_RAM_CMD_NULL 0x0 -#define SIO_HI_RA_RAM_CMD_UIO 0x1 -#define SIO_HI_RA_RAM_CMD_RESET 0x2 -#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 -#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 -#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 -#define SIO_HI_RA_RAM_CMD_EXEC 0x6 -#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 -#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 - -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 - -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 - -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 - -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 - -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F - -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 - -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 - -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 - -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 - -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 - -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 - -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 - -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 - -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF - -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 - - -#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E -#define SIO_HI_RA_RAM_AB_TEMP__W 16 -#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF -#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 - -#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F -#define SIO_HI_RA_RAM_I2C_CTL__W 16 -#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF -#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 -#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 -#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 -#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 -#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 -#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 -#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 -#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 -#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 -#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 -#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 -#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A -#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B -#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C -#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D -#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 - - -#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E -#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 -#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF -#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 -#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F -#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 - -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 - - - -#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 -#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 -#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF -#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 -#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 -#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 -#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF -#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 -#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 -#define SIO_HI_IF_RAM_TRP_STK_0__W 12 -#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF -#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 -#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 -#define SIO_HI_IF_RAM_TRP_STK_1__W 12 -#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF -#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 -#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 -#define SIO_HI_IF_RAM_FUN_BASE__W 12 -#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF -#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 - - - -#define SIO_HI_IF_COMM_EXEC__A 0x440000 -#define SIO_HI_IF_COMM_EXEC__W 2 -#define SIO_HI_IF_COMM_EXEC__M 0x3 -#define SIO_HI_IF_COMM_EXEC__PRE 0x0 -#define SIO_HI_IF_COMM_EXEC_STOP 0x0 -#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 -#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 -#define SIO_HI_IF_COMM_EXEC_STEP 0x3 - - -#define SIO_HI_IF_COMM_STATE__A 0x440001 -#define SIO_HI_IF_COMM_STATE__W 10 -#define SIO_HI_IF_COMM_STATE__M 0x3FF -#define SIO_HI_IF_COMM_STATE__PRE 0x0 -#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 -#define SIO_HI_IF_COMM_INT_REQ__W 1 -#define SIO_HI_IF_COMM_INT_REQ__M 0x1 -#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 -#define SIO_HI_IF_COMM_INT_STA__A 0x440005 -#define SIO_HI_IF_COMM_INT_STA__W 1 -#define SIO_HI_IF_COMM_INT_STA__M 0x1 -#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 -#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 -#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 -#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 -#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 - -#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 -#define SIO_HI_IF_COMM_INT_MSK__W 1 -#define SIO_HI_IF_COMM_INT_MSK__M 0x1 -#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 -#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 -#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 -#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 -#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 - -#define SIO_HI_IF_COMM_INT_STM__A 0x440007 -#define SIO_HI_IF_COMM_INT_STM__W 1 -#define SIO_HI_IF_COMM_INT_STM__M 0x1 -#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 -#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 -#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 -#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 -#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 - -#define SIO_HI_IF_STK_0__A 0x440010 -#define SIO_HI_IF_STK_0__W 10 -#define SIO_HI_IF_STK_0__M 0x3FF -#define SIO_HI_IF_STK_0__PRE 0x2 - -#define SIO_HI_IF_STK_0_ADDR__B 0 -#define SIO_HI_IF_STK_0_ADDR__W 10 -#define SIO_HI_IF_STK_0_ADDR__M 0x3FF -#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 - -#define SIO_HI_IF_STK_1__A 0x440011 -#define SIO_HI_IF_STK_1__W 10 -#define SIO_HI_IF_STK_1__M 0x3FF -#define SIO_HI_IF_STK_1__PRE 0x2 -#define SIO_HI_IF_STK_1_ADDR__B 0 -#define SIO_HI_IF_STK_1_ADDR__W 10 -#define SIO_HI_IF_STK_1_ADDR__M 0x3FF -#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 - -#define SIO_HI_IF_STK_2__A 0x440012 -#define SIO_HI_IF_STK_2__W 10 -#define SIO_HI_IF_STK_2__M 0x3FF -#define SIO_HI_IF_STK_2__PRE 0x2 -#define SIO_HI_IF_STK_2_ADDR__B 0 -#define SIO_HI_IF_STK_2_ADDR__W 10 -#define SIO_HI_IF_STK_2_ADDR__M 0x3FF -#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 - -#define SIO_HI_IF_STK_3__A 0x440013 -#define SIO_HI_IF_STK_3__W 10 -#define SIO_HI_IF_STK_3__M 0x3FF -#define SIO_HI_IF_STK_3__PRE 0x2 - -#define SIO_HI_IF_STK_3_ADDR__B 0 -#define SIO_HI_IF_STK_3_ADDR__W 10 -#define SIO_HI_IF_STK_3_ADDR__M 0x3FF -#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 - -#define SIO_HI_IF_BPT_IDX__A 0x44001F -#define SIO_HI_IF_BPT_IDX__W 1 -#define SIO_HI_IF_BPT_IDX__M 0x1 -#define SIO_HI_IF_BPT_IDX__PRE 0x0 - -#define SIO_HI_IF_BPT_IDX_ADDR__B 0 -#define SIO_HI_IF_BPT_IDX_ADDR__W 1 -#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 -#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 - -#define SIO_HI_IF_BPT__A 0x440020 -#define SIO_HI_IF_BPT__W 10 -#define SIO_HI_IF_BPT__M 0x3FF -#define SIO_HI_IF_BPT__PRE 0x2 - -#define SIO_HI_IF_BPT_ADDR__B 0 -#define SIO_HI_IF_BPT_ADDR__W 10 -#define SIO_HI_IF_BPT_ADDR__M 0x3FF -#define SIO_HI_IF_BPT_ADDR__PRE 0x2 - - - -#define SIO_CC_COMM_EXEC__A 0x450000 -#define SIO_CC_COMM_EXEC__W 2 -#define SIO_CC_COMM_EXEC__M 0x3 -#define SIO_CC_COMM_EXEC__PRE 0x0 -#define SIO_CC_COMM_EXEC_STOP 0x0 -#define SIO_CC_COMM_EXEC_ACTIVE 0x1 -#define SIO_CC_COMM_EXEC_HOLD 0x2 - -#define SIO_CC_PLL_MODE__A 0x450010 -#define SIO_CC_PLL_MODE__W 6 -#define SIO_CC_PLL_MODE__M 0x3F -#define SIO_CC_PLL_MODE__PRE 0x0 - -#define SIO_CC_PLL_MODE_FREF_SEL__B 0 -#define SIO_CC_PLL_MODE_FREF_SEL__W 2 -#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 -#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 -#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 -#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 -#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 -#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 - -#define SIO_CC_PLL_MODE_LOCKSEL__B 2 -#define SIO_CC_PLL_MODE_LOCKSEL__W 2 -#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC -#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 - -#define SIO_CC_PLL_MODE_BYPASS__B 4 -#define SIO_CC_PLL_MODE_BYPASS__W 2 -#define SIO_CC_PLL_MODE_BYPASS__M 0x30 -#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 -#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 -#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 -#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 - - -#define SIO_CC_PLL_TEST__A 0x450011 -#define SIO_CC_PLL_TEST__W 8 -#define SIO_CC_PLL_TEST__M 0xFF -#define SIO_CC_PLL_TEST__PRE 0x0 - -#define SIO_CC_PLL_LOCK__A 0x450012 -#define SIO_CC_PLL_LOCK__W 1 -#define SIO_CC_PLL_LOCK__M 0x1 -#define SIO_CC_PLL_LOCK__PRE 0x0 -#define SIO_CC_CLK_TEST__A 0x450013 -#define SIO_CC_CLK_TEST__W 8 -#define SIO_CC_CLK_TEST__M 0xFF -#define SIO_CC_CLK_TEST__PRE 0x0 - -#define SIO_CC_CLK_TEST_SEL1__B 0 -#define SIO_CC_CLK_TEST_SEL1__W 3 -#define SIO_CC_CLK_TEST_SEL1__M 0x7 -#define SIO_CC_CLK_TEST_SEL1__PRE 0x0 - -#define SIO_CC_CLK_TEST_ENAB1__B 3 -#define SIO_CC_CLK_TEST_ENAB1__W 1 -#define SIO_CC_CLK_TEST_ENAB1__M 0x8 -#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0 - -#define SIO_CC_CLK_TEST_SEL2__B 4 -#define SIO_CC_CLK_TEST_SEL2__W 3 -#define SIO_CC_CLK_TEST_SEL2__M 0x70 -#define SIO_CC_CLK_TEST_SEL2__PRE 0x0 - -#define SIO_CC_CLK_TEST_ENAB2__B 7 -#define SIO_CC_CLK_TEST_ENAB2__W 1 -#define SIO_CC_CLK_TEST_ENAB2__M 0x80 -#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0 - -#define SIO_CC_CLK_MODE__A 0x450014 -#define SIO_CC_CLK_MODE__W 7 -#define SIO_CC_CLK_MODE__M 0x7F -#define SIO_CC_CLK_MODE__PRE 0x0 - -#define SIO_CC_CLK_MODE_DELAY__B 0 -#define SIO_CC_CLK_MODE_DELAY__W 4 -#define SIO_CC_CLK_MODE_DELAY__M 0xF -#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 - -#define SIO_CC_CLK_MODE_INVERT__B 4 -#define SIO_CC_CLK_MODE_INVERT__W 1 -#define SIO_CC_CLK_MODE_INVERT__M 0x10 -#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 - -#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5 -#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1 -#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20 -#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0 - -#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6 -#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1 -#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40 -#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0 - -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_PWD_MODE__W 4 -#define SIO_CC_PWD_MODE__M 0xF -#define SIO_CC_PWD_MODE__PRE 0x0 - -#define SIO_CC_PWD_MODE_LEVEL__B 0 -#define SIO_CC_PWD_MODE_LEVEL__W 3 -#define SIO_CC_PWD_MODE_LEVEL__M 0x7 -#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 -#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 -#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 -#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 - -#define SIO_CC_PWD_MODE_USE_LOCK__B 3 -#define SIO_CC_PWD_MODE_USE_LOCK__W 1 -#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8 -#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 - -#define SIO_CC_SOFT_RST__A 0x450016 -#define SIO_CC_SOFT_RST__W 3 -#define SIO_CC_SOFT_RST__M 0x7 -#define SIO_CC_SOFT_RST__PRE 0x0 - -#define SIO_CC_SOFT_RST_OFDM__B 0 -#define SIO_CC_SOFT_RST_OFDM__W 1 -#define SIO_CC_SOFT_RST_OFDM__M 0x1 -#define SIO_CC_SOFT_RST_OFDM__PRE 0x0 - -#define SIO_CC_SOFT_RST_SYS__B 1 -#define SIO_CC_SOFT_RST_SYS__W 1 -#define SIO_CC_SOFT_RST_SYS__M 0x2 -#define SIO_CC_SOFT_RST_SYS__PRE 0x0 - -#define SIO_CC_SOFT_RST_OSC__B 2 -#define SIO_CC_SOFT_RST_OSC__W 1 -#define SIO_CC_SOFT_RST_OSC__M 0x4 -#define SIO_CC_SOFT_RST_OSC__PRE 0x0 - - -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__W 16 -#define SIO_CC_UPDATE__M 0xFFFF -#define SIO_CC_UPDATE__PRE 0x0 -#define SIO_CC_UPDATE_KEY 0xFABA - - - -#define SIO_SA_COMM_EXEC__A 0x460000 -#define SIO_SA_COMM_EXEC__W 2 -#define SIO_SA_COMM_EXEC__M 0x3 -#define SIO_SA_COMM_EXEC__PRE 0x0 -#define SIO_SA_COMM_EXEC_STOP 0x0 -#define SIO_SA_COMM_EXEC_ACTIVE 0x1 -#define SIO_SA_COMM_EXEC_HOLD 0x2 - -#define SIO_SA_COMM_INT_REQ__A 0x460003 -#define SIO_SA_COMM_INT_REQ__W 1 -#define SIO_SA_COMM_INT_REQ__M 0x1 -#define SIO_SA_COMM_INT_REQ__PRE 0x0 -#define SIO_SA_COMM_INT_STA__A 0x460005 -#define SIO_SA_COMM_INT_STA__W 4 -#define SIO_SA_COMM_INT_STA__M 0xF -#define SIO_SA_COMM_INT_STA__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 -#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 -#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 -#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 - -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 -#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK__A 0x460006 -#define SIO_SA_COMM_INT_MSK__W 4 -#define SIO_SA_COMM_INT_MSK__M 0xF -#define SIO_SA_COMM_INT_MSK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 -#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 -#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 -#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 -#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM__A 0x460007 -#define SIO_SA_COMM_INT_STM__W 4 -#define SIO_SA_COMM_INT_STM__M 0xF -#define SIO_SA_COMM_INT_STM__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 -#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 -#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 -#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 - -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 -#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 - -#define SIO_SA_PRESCALER__A 0x460010 -#define SIO_SA_PRESCALER__W 13 -#define SIO_SA_PRESCALER__M 0x1FFF -#define SIO_SA_PRESCALER__PRE 0x18B7 -#define SIO_SA_TX_DATA0__A 0x460011 -#define SIO_SA_TX_DATA0__W 16 -#define SIO_SA_TX_DATA0__M 0xFFFF -#define SIO_SA_TX_DATA0__PRE 0x0 -#define SIO_SA_TX_DATA1__A 0x460012 -#define SIO_SA_TX_DATA1__W 16 -#define SIO_SA_TX_DATA1__M 0xFFFF -#define SIO_SA_TX_DATA1__PRE 0x0 -#define SIO_SA_TX_DATA2__A 0x460013 -#define SIO_SA_TX_DATA2__W 16 -#define SIO_SA_TX_DATA2__M 0xFFFF -#define SIO_SA_TX_DATA2__PRE 0x0 -#define SIO_SA_TX_DATA3__A 0x460014 -#define SIO_SA_TX_DATA3__W 16 -#define SIO_SA_TX_DATA3__M 0xFFFF -#define SIO_SA_TX_DATA3__PRE 0x0 -#define SIO_SA_TX_LENGTH__A 0x460015 -#define SIO_SA_TX_LENGTH__W 6 -#define SIO_SA_TX_LENGTH__M 0x3F -#define SIO_SA_TX_LENGTH__PRE 0x0 -#define SIO_SA_TX_COMMAND__A 0x460016 -#define SIO_SA_TX_COMMAND__W 2 -#define SIO_SA_TX_COMMAND__M 0x3 -#define SIO_SA_TX_COMMAND__PRE 0x3 - -#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 -#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 -#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 -#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 - -#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 -#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 -#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 -#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 - -#define SIO_SA_TX_STATUS__A 0x460017 -#define SIO_SA_TX_STATUS__W 2 -#define SIO_SA_TX_STATUS__M 0x3 -#define SIO_SA_TX_STATUS__PRE 0x0 - -#define SIO_SA_TX_STATUS_BUSY__B 0 -#define SIO_SA_TX_STATUS_BUSY__W 1 -#define SIO_SA_TX_STATUS_BUSY__M 0x1 -#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 - -#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 -#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 -#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 -#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 - -#define SIO_SA_RX_DATA0__A 0x460018 -#define SIO_SA_RX_DATA0__W 16 -#define SIO_SA_RX_DATA0__M 0xFFFF -#define SIO_SA_RX_DATA0__PRE 0x0 -#define SIO_SA_RX_DATA1__A 0x460019 -#define SIO_SA_RX_DATA1__W 16 -#define SIO_SA_RX_DATA1__M 0xFFFF -#define SIO_SA_RX_DATA1__PRE 0x0 -#define SIO_SA_RX_LENGTH__A 0x46001A -#define SIO_SA_RX_LENGTH__W 6 -#define SIO_SA_RX_LENGTH__M 0x3F -#define SIO_SA_RX_LENGTH__PRE 0x0 -#define SIO_SA_RX_COMMAND__A 0x46001B -#define SIO_SA_RX_COMMAND__W 1 -#define SIO_SA_RX_COMMAND__M 0x1 -#define SIO_SA_RX_COMMAND__PRE 0x1 - -#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 -#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 -#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 -#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 - -#define SIO_SA_RX_STATUS__A 0x46001C -#define SIO_SA_RX_STATUS__W 2 -#define SIO_SA_RX_STATUS__M 0x3 -#define SIO_SA_RX_STATUS__PRE 0x0 - -#define SIO_SA_RX_STATUS_BUSY__B 0 -#define SIO_SA_RX_STATUS_BUSY__W 1 -#define SIO_SA_RX_STATUS_BUSY__M 0x1 -#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 - -#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 -#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 -#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 -#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 - - - -#define SIO_OFDM_SH_COMM_EXEC__A 0x470000 -#define SIO_OFDM_SH_COMM_EXEC__W 2 -#define SIO_OFDM_SH_COMM_EXEC__M 0x3 -#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0 -#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0 -#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1 -#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2 - -#define SIO_OFDM_SH_COMM_MB__A 0x470002 -#define SIO_OFDM_SH_COMM_MB__W 2 -#define SIO_OFDM_SH_COMM_MB__M 0x3 -#define SIO_OFDM_SH_COMM_MB__PRE 0x0 -#define SIO_OFDM_SH_COMM_MB_CTL__B 0 -#define SIO_OFDM_SH_COMM_MB_CTL__W 1 -#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1 -#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0 -#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0 -#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1 -#define SIO_OFDM_SH_COMM_MB_OBS__B 1 -#define SIO_OFDM_SH_COMM_MB_OBS__W 1 -#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2 -#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0 -#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0 -#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2 - -#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 - -#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011 -#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2 -#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3 -#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0 - -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1 - -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0 -#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2 - -#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 -#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1 -#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1 -#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0 -#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 -#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 - -#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013 -#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3 -#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7 -#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7 -#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6 - - - -#define SIO_BL_COMM_EXEC__A 0x480000 -#define SIO_BL_COMM_EXEC__W 2 -#define SIO_BL_COMM_EXEC__M 0x3 -#define SIO_BL_COMM_EXEC__PRE 0x0 -#define SIO_BL_COMM_EXEC_STOP 0x0 -#define SIO_BL_COMM_EXEC_ACTIVE 0x1 -#define SIO_BL_COMM_EXEC_HOLD 0x2 - -#define SIO_BL_COMM_INT_REQ__A 0x480003 -#define SIO_BL_COMM_INT_REQ__W 1 -#define SIO_BL_COMM_INT_REQ__M 0x1 -#define SIO_BL_COMM_INT_REQ__PRE 0x0 -#define SIO_BL_COMM_INT_STA__A 0x480005 -#define SIO_BL_COMM_INT_STA__W 1 -#define SIO_BL_COMM_INT_STA__M 0x1 -#define SIO_BL_COMM_INT_STA__PRE 0x0 - -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0 -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1 -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1 -#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0 - -#define SIO_BL_COMM_INT_MSK__A 0x480006 -#define SIO_BL_COMM_INT_MSK__W 1 -#define SIO_BL_COMM_INT_MSK__M 0x1 -#define SIO_BL_COMM_INT_MSK__PRE 0x0 - -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0 -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1 -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1 -#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0 - -#define SIO_BL_COMM_INT_STM__A 0x480007 -#define SIO_BL_COMM_INT_STM__W 1 -#define SIO_BL_COMM_INT_STM__M 0x1 -#define SIO_BL_COMM_INT_STM__PRE 0x0 - -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0 -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1 -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1 -#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0 - -#define SIO_BL_STATUS__A 0x480010 -#define SIO_BL_STATUS__W 1 -#define SIO_BL_STATUS__M 0x1 -#define SIO_BL_STATUS__PRE 0x0 -#define SIO_BL_MODE__A 0x480011 -#define SIO_BL_MODE__W 1 -#define SIO_BL_MODE__M 0x1 -#define SIO_BL_MODE__PRE 0x1 -#define SIO_BL_MODE_DIRECT 0x0 -#define SIO_BL_MODE_CHAIN 0x1 - -#define SIO_BL_ENABLE__A 0x480012 -#define SIO_BL_ENABLE__W 1 -#define SIO_BL_ENABLE__M 0x1 -#define SIO_BL_ENABLE__PRE 0x0 -#define SIO_BL_ENABLE_OFF 0x0 -#define SIO_BL_ENABLE_ON 0x1 - -#define SIO_BL_TGT_HDR__A 0x480014 -#define SIO_BL_TGT_HDR__W 12 -#define SIO_BL_TGT_HDR__M 0xFFF -#define SIO_BL_TGT_HDR__PRE 0x0 -#define SIO_BL_TGT_HDR_BANK__B 0 -#define SIO_BL_TGT_HDR_BANK__W 6 -#define SIO_BL_TGT_HDR_BANK__M 0x3F -#define SIO_BL_TGT_HDR_BANK__PRE 0x0 -#define SIO_BL_TGT_HDR_BLOCK__B 6 -#define SIO_BL_TGT_HDR_BLOCK__W 6 -#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0 -#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0 - -#define SIO_BL_TGT_ADDR__A 0x480015 -#define SIO_BL_TGT_ADDR__W 16 -#define SIO_BL_TGT_ADDR__M 0xFFFF -#define SIO_BL_TGT_ADDR__PRE 0x0 -#define SIO_BL_SRC_ADDR__A 0x480016 -#define SIO_BL_SRC_ADDR__W 16 -#define SIO_BL_SRC_ADDR__M 0xFFFF -#define SIO_BL_SRC_ADDR__PRE 0x0 -#define SIO_BL_SRC_LEN__A 0x480017 -#define SIO_BL_SRC_LEN__W 16 -#define SIO_BL_SRC_LEN__M 0xFFFF -#define SIO_BL_SRC_LEN__PRE 0x0 - -#define SIO_BL_CHAIN_ADDR__A 0x480018 -#define SIO_BL_CHAIN_ADDR__W 16 -#define SIO_BL_CHAIN_ADDR__M 0xFFFF -#define SIO_BL_CHAIN_ADDR__PRE 0x0 - -#define SIO_BL_CHAIN_LEN__A 0x480019 -#define SIO_BL_CHAIN_LEN__W 4 -#define SIO_BL_CHAIN_LEN__M 0xF -#define SIO_BL_CHAIN_LEN__PRE 0x2 - - - -#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000 - - - -#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000 - - - -#define SIO_BL_ROM__A 0x4E0000 - - - -#define SIO_PDR_COMM_EXEC__A 0x7F0000 -#define SIO_PDR_COMM_EXEC__W 2 -#define SIO_PDR_COMM_EXEC__M 0x3 -#define SIO_PDR_COMM_EXEC__PRE 0x0 -#define SIO_PDR_COMM_EXEC_STOP 0x0 -#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 -#define SIO_PDR_COMM_EXEC_HOLD 0x2 - -#define SIO_PDR_MON_CFG__A 0x7F0010 -#define SIO_PDR_MON_CFG__W 4 -#define SIO_PDR_MON_CFG__M 0xF -#define SIO_PDR_MON_CFG__PRE 0x0 - -#define SIO_PDR_MON_CFG_OSEL__B 0 -#define SIO_PDR_MON_CFG_OSEL__W 1 -#define SIO_PDR_MON_CFG_OSEL__M 0x1 -#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 - -#define SIO_PDR_MON_CFG_IACT__B 1 -#define SIO_PDR_MON_CFG_IACT__W 1 -#define SIO_PDR_MON_CFG_IACT__M 0x2 -#define SIO_PDR_MON_CFG_IACT__PRE 0x0 - -#define SIO_PDR_MON_CFG_ISEL__B 2 -#define SIO_PDR_MON_CFG_ISEL__W 1 -#define SIO_PDR_MON_CFG_ISEL__M 0x4 -#define SIO_PDR_MON_CFG_ISEL__PRE 0x0 - -#define SIO_PDR_MON_CFG_INV_CLK__B 3 -#define SIO_PDR_MON_CFG_INV_CLK__W 1 -#define SIO_PDR_MON_CFG_INV_CLK__M 0x8 -#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0 - -#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 -#define SIO_PDR_SMA_RX_SEL__W 4 -#define SIO_PDR_SMA_RX_SEL__M 0xF -#define SIO_PDR_SMA_RX_SEL__PRE 0x0 - -#define SIO_PDR_SMA_RX_SEL_SEL__B 0 -#define SIO_PDR_SMA_RX_SEL_SEL__W 4 -#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF -#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 - -#define SIO_PDR_SILENT__A 0x7F0013 -#define SIO_PDR_SILENT__W 13 -#define SIO_PDR_SILENT__M 0x1FFF -#define SIO_PDR_SILENT__PRE 0x0 - -#define SIO_PDR_SILENT_I2S_WS__B 0 -#define SIO_PDR_SILENT_I2S_WS__W 1 -#define SIO_PDR_SILENT_I2S_WS__M 0x1 -#define SIO_PDR_SILENT_I2S_WS__PRE 0x0 - -#define SIO_PDR_SILENT_I2S_DA__B 1 -#define SIO_PDR_SILENT_I2S_DA__W 1 -#define SIO_PDR_SILENT_I2S_DA__M 0x2 -#define SIO_PDR_SILENT_I2S_DA__PRE 0x0 - -#define SIO_PDR_SILENT_I2S_CL__B 2 -#define SIO_PDR_SILENT_I2S_CL__W 1 -#define SIO_PDR_SILENT_I2S_CL__M 0x4 -#define SIO_PDR_SILENT_I2S_CL__PRE 0x0 - -#define SIO_PDR_SILENT_I2C_SCL2__B 3 -#define SIO_PDR_SILENT_I2C_SCL2__W 1 -#define SIO_PDR_SILENT_I2C_SCL2__M 0x8 -#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0 - -#define SIO_PDR_SILENT_I2C_SDA2__B 4 -#define SIO_PDR_SILENT_I2C_SDA2__W 1 -#define SIO_PDR_SILENT_I2C_SDA2__M 0x10 -#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0 - -#define SIO_PDR_SILENT_SMA_TX__B 8 -#define SIO_PDR_SILENT_SMA_TX__W 1 -#define SIO_PDR_SILENT_SMA_TX__M 0x100 -#define SIO_PDR_SILENT_SMA_TX__PRE 0x0 - -#define SIO_PDR_SILENT_SMA_RX__B 9 -#define SIO_PDR_SILENT_SMA_RX__W 1 -#define SIO_PDR_SILENT_SMA_RX__M 0x200 -#define SIO_PDR_SILENT_SMA_RX__PRE 0x0 - -#define SIO_PDR_SILENT_GPIO__B 10 -#define SIO_PDR_SILENT_GPIO__W 1 -#define SIO_PDR_SILENT_GPIO__M 0x400 -#define SIO_PDR_SILENT_GPIO__PRE 0x0 - -#define SIO_PDR_SILENT_VSYNC__B 11 -#define SIO_PDR_SILENT_VSYNC__W 1 -#define SIO_PDR_SILENT_VSYNC__M 0x800 -#define SIO_PDR_SILENT_VSYNC__PRE 0x0 - -#define SIO_PDR_SILENT_IRQN__B 12 -#define SIO_PDR_SILENT_IRQN__W 1 -#define SIO_PDR_SILENT_IRQN__M 0x1000 -#define SIO_PDR_SILENT_IRQN__PRE 0x0 - -#define SIO_PDR_UIO_IN_LO__A 0x7F0014 -#define SIO_PDR_UIO_IN_LO__W 16 -#define SIO_PDR_UIO_IN_LO__M 0xFFFF -#define SIO_PDR_UIO_IN_LO__PRE 0x0 -#define SIO_PDR_UIO_IN_LO_DATA__B 0 -#define SIO_PDR_UIO_IN_LO_DATA__W 16 -#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF -#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 - -#define SIO_PDR_UIO_IN_HI__A 0x7F0015 -#define SIO_PDR_UIO_IN_HI__W 14 -#define SIO_PDR_UIO_IN_HI__M 0x3FFF -#define SIO_PDR_UIO_IN_HI__PRE 0x0 -#define SIO_PDR_UIO_IN_HI_DATA__B 0 -#define SIO_PDR_UIO_IN_HI_DATA__W 14 -#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF -#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 - -#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 -#define SIO_PDR_UIO_OUT_LO__W 16 -#define SIO_PDR_UIO_OUT_LO__M 0xFFFF -#define SIO_PDR_UIO_OUT_LO__PRE 0x0 -#define SIO_PDR_UIO_OUT_LO_DATA__B 0 -#define SIO_PDR_UIO_OUT_LO_DATA__W 16 -#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF -#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 - -#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 -#define SIO_PDR_UIO_OUT_HI__W 14 -#define SIO_PDR_UIO_OUT_HI__M 0x3FFF -#define SIO_PDR_UIO_OUT_HI__PRE 0x0 -#define SIO_PDR_UIO_OUT_HI_DATA__B 0 -#define SIO_PDR_UIO_OUT_HI_DATA__W 14 -#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF -#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 - -#define SIO_PDR_PWM1_MODE__A 0x7F0018 -#define SIO_PDR_PWM1_MODE__W 2 -#define SIO_PDR_PWM1_MODE__M 0x3 -#define SIO_PDR_PWM1_MODE__PRE 0x0 -#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 -#define SIO_PDR_PWM1_PRESCALE__W 6 -#define SIO_PDR_PWM1_PRESCALE__M 0x3F -#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 -#define SIO_PDR_PWM1_VALUE__A 0x7F001A -#define SIO_PDR_PWM1_VALUE__W 11 -#define SIO_PDR_PWM1_VALUE__M 0x7FF -#define SIO_PDR_PWM1_VALUE__PRE 0x0 - -#define SIO_PDR_IRQN_SEL__A 0x7F001B -#define SIO_PDR_IRQN_SEL__W 4 -#define SIO_PDR_IRQN_SEL__M 0xF -#define SIO_PDR_IRQN_SEL__PRE 0x3 -#define SIO_PDR_PWM2_MODE__A 0x7F001C -#define SIO_PDR_PWM2_MODE__W 2 -#define SIO_PDR_PWM2_MODE__M 0x3 -#define SIO_PDR_PWM2_MODE__PRE 0x0 -#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D -#define SIO_PDR_PWM2_PRESCALE__W 6 -#define SIO_PDR_PWM2_PRESCALE__M 0x3F -#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 -#define SIO_PDR_PWM2_VALUE__A 0x7F001E -#define SIO_PDR_PWM2_VALUE__W 11 -#define SIO_PDR_PWM2_VALUE__M 0x7FF -#define SIO_PDR_PWM2_VALUE__PRE 0x0 -#define SIO_PDR_OHW_CFG__A 0x7F001F -#define SIO_PDR_OHW_CFG__W 7 -#define SIO_PDR_OHW_CFG__M 0x7F -#define SIO_PDR_OHW_CFG__PRE 0x0 - -#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 -#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 -#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 -#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 - -#define SIO_PDR_OHW_CFG_BYPASS__B 2 -#define SIO_PDR_OHW_CFG_BYPASS__W 1 -#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 -#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 - -#define SIO_PDR_OHW_CFG_ASEL__B 3 -#define SIO_PDR_OHW_CFG_ASEL__W 3 -#define SIO_PDR_OHW_CFG_ASEL__M 0x38 -#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 - -#define SIO_PDR_OHW_CFG_SPEED__B 6 -#define SIO_PDR_OHW_CFG_SPEED__W 1 -#define SIO_PDR_OHW_CFG_SPEED__M 0x40 -#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 - -#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 -#define SIO_PDR_I2S_WS_CFG__W 9 -#define SIO_PDR_I2S_WS_CFG__M 0x1FF -#define SIO_PDR_I2S_WS_CFG__PRE 0x10 -#define SIO_PDR_I2S_WS_CFG_MODE__B 0 -#define SIO_PDR_I2S_WS_CFG_MODE__W 3 -#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 -#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 -#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 -#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 -#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 -#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 -#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2S_WS_CFG_UIO__B 8 -#define SIO_PDR_I2S_WS_CFG_UIO__W 1 -#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 -#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 - -#define SIO_PDR_GPIO_CFG__A 0x7F0021 -#define SIO_PDR_GPIO_CFG__W 9 -#define SIO_PDR_GPIO_CFG__M 0x1FF -#define SIO_PDR_GPIO_CFG__PRE 0x10 -#define SIO_PDR_GPIO_CFG_MODE__B 0 -#define SIO_PDR_GPIO_CFG_MODE__W 3 -#define SIO_PDR_GPIO_CFG_MODE__M 0x7 -#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 -#define SIO_PDR_GPIO_CFG_DRIVE__B 3 -#define SIO_PDR_GPIO_CFG_DRIVE__W 3 -#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 -#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_GPIO_CFG_KEEP__B 6 -#define SIO_PDR_GPIO_CFG_KEEP__W 2 -#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 -#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 -#define SIO_PDR_GPIO_CFG_UIO__B 8 -#define SIO_PDR_GPIO_CFG_UIO__W 1 -#define SIO_PDR_GPIO_CFG_UIO__M 0x100 -#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MSTRT_CFG__A 0x7F0025 -#define SIO_PDR_MSTRT_CFG__W 9 -#define SIO_PDR_MSTRT_CFG__M 0x1FF -#define SIO_PDR_MSTRT_CFG__PRE 0x50 -#define SIO_PDR_MSTRT_CFG_MODE__B 0 -#define SIO_PDR_MSTRT_CFG_MODE__W 3 -#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 -#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 -#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 -#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 -#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 -#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MSTRT_CFG_KEEP__B 6 -#define SIO_PDR_MSTRT_CFG_KEEP__W 2 -#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 -#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MSTRT_CFG_UIO__B 8 -#define SIO_PDR_MSTRT_CFG_UIO__W 1 -#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 -#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MERR_CFG__A 0x7F0026 -#define SIO_PDR_MERR_CFG__W 9 -#define SIO_PDR_MERR_CFG__M 0x1FF -#define SIO_PDR_MERR_CFG__PRE 0x50 -#define SIO_PDR_MERR_CFG_MODE__B 0 -#define SIO_PDR_MERR_CFG_MODE__W 3 -#define SIO_PDR_MERR_CFG_MODE__M 0x7 -#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 -#define SIO_PDR_MERR_CFG_DRIVE__B 3 -#define SIO_PDR_MERR_CFG_DRIVE__W 3 -#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 -#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MERR_CFG_KEEP__B 6 -#define SIO_PDR_MERR_CFG_KEEP__W 2 -#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 -#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MERR_CFG_UIO__B 8 -#define SIO_PDR_MERR_CFG_UIO__W 1 -#define SIO_PDR_MERR_CFG_UIO__M 0x100 -#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MCLK_CFG__A 0x7F0028 -#define SIO_PDR_MCLK_CFG__W 9 -#define SIO_PDR_MCLK_CFG__M 0x1FF -#define SIO_PDR_MCLK_CFG__PRE 0x50 -#define SIO_PDR_MCLK_CFG_MODE__B 0 -#define SIO_PDR_MCLK_CFG_MODE__W 3 -#define SIO_PDR_MCLK_CFG_MODE__M 0x7 -#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 -#define SIO_PDR_MCLK_CFG_DRIVE__B 3 -#define SIO_PDR_MCLK_CFG_DRIVE__W 3 -#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 -#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MCLK_CFG_KEEP__B 6 -#define SIO_PDR_MCLK_CFG_KEEP__W 2 -#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 -#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MCLK_CFG_UIO__B 8 -#define SIO_PDR_MCLK_CFG_UIO__W 1 -#define SIO_PDR_MCLK_CFG_UIO__M 0x100 -#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MVAL_CFG__A 0x7F0029 -#define SIO_PDR_MVAL_CFG__W 9 -#define SIO_PDR_MVAL_CFG__M 0x1FF -#define SIO_PDR_MVAL_CFG__PRE 0x50 -#define SIO_PDR_MVAL_CFG_MODE__B 0 -#define SIO_PDR_MVAL_CFG_MODE__W 3 -#define SIO_PDR_MVAL_CFG_MODE__M 0x7 -#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 -#define SIO_PDR_MVAL_CFG_DRIVE__B 3 -#define SIO_PDR_MVAL_CFG_DRIVE__W 3 -#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 -#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MVAL_CFG_KEEP__B 6 -#define SIO_PDR_MVAL_CFG_KEEP__W 2 -#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 -#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MVAL_CFG_UIO__B 8 -#define SIO_PDR_MVAL_CFG_UIO__W 1 -#define SIO_PDR_MVAL_CFG_UIO__M 0x100 -#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD0_CFG__A 0x7F002A -#define SIO_PDR_MD0_CFG__W 9 -#define SIO_PDR_MD0_CFG__M 0x1FF -#define SIO_PDR_MD0_CFG__PRE 0x50 -#define SIO_PDR_MD0_CFG_MODE__B 0 -#define SIO_PDR_MD0_CFG_MODE__W 3 -#define SIO_PDR_MD0_CFG_MODE__M 0x7 -#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD0_CFG_DRIVE__B 3 -#define SIO_PDR_MD0_CFG_DRIVE__W 3 -#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD0_CFG_KEEP__B 6 -#define SIO_PDR_MD0_CFG_KEEP__W 2 -#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD0_CFG_UIO__B 8 -#define SIO_PDR_MD0_CFG_UIO__W 1 -#define SIO_PDR_MD0_CFG_UIO__M 0x100 -#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD1_CFG__A 0x7F002B -#define SIO_PDR_MD1_CFG__W 9 -#define SIO_PDR_MD1_CFG__M 0x1FF -#define SIO_PDR_MD1_CFG__PRE 0x50 -#define SIO_PDR_MD1_CFG_MODE__B 0 -#define SIO_PDR_MD1_CFG_MODE__W 3 -#define SIO_PDR_MD1_CFG_MODE__M 0x7 -#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD1_CFG_DRIVE__B 3 -#define SIO_PDR_MD1_CFG_DRIVE__W 3 -#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD1_CFG_KEEP__B 6 -#define SIO_PDR_MD1_CFG_KEEP__W 2 -#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD1_CFG_UIO__B 8 -#define SIO_PDR_MD1_CFG_UIO__W 1 -#define SIO_PDR_MD1_CFG_UIO__M 0x100 -#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD2_CFG__A 0x7F002C -#define SIO_PDR_MD2_CFG__W 9 -#define SIO_PDR_MD2_CFG__M 0x1FF -#define SIO_PDR_MD2_CFG__PRE 0x50 -#define SIO_PDR_MD2_CFG_MODE__B 0 -#define SIO_PDR_MD2_CFG_MODE__W 3 -#define SIO_PDR_MD2_CFG_MODE__M 0x7 -#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD2_CFG_DRIVE__B 3 -#define SIO_PDR_MD2_CFG_DRIVE__W 3 -#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD2_CFG_KEEP__B 6 -#define SIO_PDR_MD2_CFG_KEEP__W 2 -#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD2_CFG_UIO__B 8 -#define SIO_PDR_MD2_CFG_UIO__W 1 -#define SIO_PDR_MD2_CFG_UIO__M 0x100 -#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD3_CFG__A 0x7F002D -#define SIO_PDR_MD3_CFG__W 9 -#define SIO_PDR_MD3_CFG__M 0x1FF -#define SIO_PDR_MD3_CFG__PRE 0x50 -#define SIO_PDR_MD3_CFG_MODE__B 0 -#define SIO_PDR_MD3_CFG_MODE__W 3 -#define SIO_PDR_MD3_CFG_MODE__M 0x7 -#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD3_CFG_DRIVE__B 3 -#define SIO_PDR_MD3_CFG_DRIVE__W 3 -#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD3_CFG_KEEP__B 6 -#define SIO_PDR_MD3_CFG_KEEP__W 2 -#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD3_CFG_UIO__B 8 -#define SIO_PDR_MD3_CFG_UIO__W 1 -#define SIO_PDR_MD3_CFG_UIO__M 0x100 -#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD4_CFG__A 0x7F002F -#define SIO_PDR_MD4_CFG__W 9 -#define SIO_PDR_MD4_CFG__M 0x1FF -#define SIO_PDR_MD4_CFG__PRE 0x50 -#define SIO_PDR_MD4_CFG_MODE__B 0 -#define SIO_PDR_MD4_CFG_MODE__W 3 -#define SIO_PDR_MD4_CFG_MODE__M 0x7 -#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD4_CFG_DRIVE__B 3 -#define SIO_PDR_MD4_CFG_DRIVE__W 3 -#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD4_CFG_KEEP__B 6 -#define SIO_PDR_MD4_CFG_KEEP__W 2 -#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD4_CFG_UIO__B 8 -#define SIO_PDR_MD4_CFG_UIO__W 1 -#define SIO_PDR_MD4_CFG_UIO__M 0x100 -#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD5_CFG__A 0x7F0030 -#define SIO_PDR_MD5_CFG__W 9 -#define SIO_PDR_MD5_CFG__M 0x1FF -#define SIO_PDR_MD5_CFG__PRE 0x50 -#define SIO_PDR_MD5_CFG_MODE__B 0 -#define SIO_PDR_MD5_CFG_MODE__W 3 -#define SIO_PDR_MD5_CFG_MODE__M 0x7 -#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD5_CFG_DRIVE__B 3 -#define SIO_PDR_MD5_CFG_DRIVE__W 3 -#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD5_CFG_KEEP__B 6 -#define SIO_PDR_MD5_CFG_KEEP__W 2 -#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD5_CFG_UIO__B 8 -#define SIO_PDR_MD5_CFG_UIO__W 1 -#define SIO_PDR_MD5_CFG_UIO__M 0x100 -#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD6_CFG__A 0x7F0031 -#define SIO_PDR_MD6_CFG__W 9 -#define SIO_PDR_MD6_CFG__M 0x1FF -#define SIO_PDR_MD6_CFG__PRE 0x50 -#define SIO_PDR_MD6_CFG_MODE__B 0 -#define SIO_PDR_MD6_CFG_MODE__W 3 -#define SIO_PDR_MD6_CFG_MODE__M 0x7 -#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD6_CFG_DRIVE__B 3 -#define SIO_PDR_MD6_CFG_DRIVE__W 3 -#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD6_CFG_KEEP__B 6 -#define SIO_PDR_MD6_CFG_KEEP__W 2 -#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD6_CFG_UIO__B 8 -#define SIO_PDR_MD6_CFG_UIO__W 1 -#define SIO_PDR_MD6_CFG_UIO__M 0x100 -#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 - -#define SIO_PDR_MD7_CFG__A 0x7F0032 -#define SIO_PDR_MD7_CFG__W 9 -#define SIO_PDR_MD7_CFG__M 0x1FF -#define SIO_PDR_MD7_CFG__PRE 0x50 -#define SIO_PDR_MD7_CFG_MODE__B 0 -#define SIO_PDR_MD7_CFG_MODE__W 3 -#define SIO_PDR_MD7_CFG_MODE__M 0x7 -#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD7_CFG_DRIVE__B 3 -#define SIO_PDR_MD7_CFG_DRIVE__W 3 -#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD7_CFG_KEEP__B 6 -#define SIO_PDR_MD7_CFG_KEEP__W 2 -#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD7_CFG_UIO__B 8 -#define SIO_PDR_MD7_CFG_UIO__W 1 -#define SIO_PDR_MD7_CFG_UIO__M 0x100 -#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 -#define SIO_PDR_I2C_SCL1_CFG__W 9 -#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF -#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 -#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 -#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 -#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 -#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 -#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 -#define SIO_PDR_I2C_SDA1_CFG__W 9 -#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF -#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 -#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 -#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 -#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 -#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 -#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 - -#define SIO_PDR_VSYNC_CFG__A 0x7F0036 -#define SIO_PDR_VSYNC_CFG__W 9 -#define SIO_PDR_VSYNC_CFG__M 0x1FF -#define SIO_PDR_VSYNC_CFG__PRE 0x10 -#define SIO_PDR_VSYNC_CFG_MODE__B 0 -#define SIO_PDR_VSYNC_CFG_MODE__W 3 -#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 -#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 -#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 -#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 -#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 -#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_VSYNC_CFG_KEEP__B 6 -#define SIO_PDR_VSYNC_CFG_KEEP__W 2 -#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 -#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 -#define SIO_PDR_VSYNC_CFG_UIO__B 8 -#define SIO_PDR_VSYNC_CFG_UIO__W 1 -#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 -#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 - -#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 -#define SIO_PDR_SMA_RX_CFG__W 9 -#define SIO_PDR_SMA_RX_CFG__M 0x1FF -#define SIO_PDR_SMA_RX_CFG__PRE 0x10 -#define SIO_PDR_SMA_RX_CFG_MODE__B 0 -#define SIO_PDR_SMA_RX_CFG_MODE__W 3 -#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 -#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 -#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 -#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 -#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 -#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 -#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 -#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 -#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 -#define SIO_PDR_SMA_RX_CFG_UIO__B 8 -#define SIO_PDR_SMA_RX_CFG_UIO__W 1 -#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 -#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 - -#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 -#define SIO_PDR_SMA_TX_CFG__W 9 -#define SIO_PDR_SMA_TX_CFG__M 0x1FF -#define SIO_PDR_SMA_TX_CFG__PRE 0x90 -#define SIO_PDR_SMA_TX_CFG_MODE__B 0 -#define SIO_PDR_SMA_TX_CFG_MODE__W 3 -#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 -#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 -#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 -#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 -#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 -#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 -#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 -#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 -#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 -#define SIO_PDR_SMA_TX_CFG_UIO__B 8 -#define SIO_PDR_SMA_TX_CFG_UIO__W 1 -#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 -#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F -#define SIO_PDR_I2C_SDA2_CFG__W 9 -#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF -#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 -#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 -#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 -#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 -#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 -#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 -#define SIO_PDR_I2C_SCL2_CFG__W 9 -#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF -#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 -#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 -#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 -#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 -#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 -#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 -#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 -#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 -#define SIO_PDR_I2S_CL_CFG__W 9 -#define SIO_PDR_I2S_CL_CFG__M 0x1FF -#define SIO_PDR_I2S_CL_CFG__PRE 0x10 -#define SIO_PDR_I2S_CL_CFG_MODE__B 0 -#define SIO_PDR_I2S_CL_CFG_MODE__W 3 -#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 -#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 -#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 -#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 -#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 -#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 -#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2S_CL_CFG_UIO__B 8 -#define SIO_PDR_I2S_CL_CFG_UIO__W 1 -#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 -#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 - -#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 -#define SIO_PDR_I2S_DA_CFG__W 9 -#define SIO_PDR_I2S_DA_CFG__M 0x1FF -#define SIO_PDR_I2S_DA_CFG__PRE 0x10 -#define SIO_PDR_I2S_DA_CFG_MODE__B 0 -#define SIO_PDR_I2S_DA_CFG_MODE__W 3 -#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 -#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 -#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 -#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 -#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 -#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 -#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 -#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 -#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 -#define SIO_PDR_I2S_DA_CFG_UIO__B 8 -#define SIO_PDR_I2S_DA_CFG_UIO__W 1 -#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 -#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 - -#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 -#define SIO_PDR_GPIO_GPIO_FNC__W 2 -#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 -#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 -#define SIO_PDR_MSTRT_GPIO_FNC__W 2 -#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 -#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 -#define SIO_PDR_MERR_GPIO_FNC__W 2 -#define SIO_PDR_MERR_GPIO_FNC__M 0x3 -#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 -#define SIO_PDR_MCLK_GPIO_FNC__W 2 -#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 -#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 -#define SIO_PDR_MVAL_GPIO_FNC__W 2 -#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 -#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 -#define SIO_PDR_MD0_GPIO_FNC__W 2 -#define SIO_PDR_MD0_GPIO_FNC__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 -#define SIO_PDR_MD1_GPIO_FNC__W 2 -#define SIO_PDR_MD1_GPIO_FNC__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 -#define SIO_PDR_MD2_GPIO_FNC__W 2 -#define SIO_PDR_MD2_GPIO_FNC__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 -#define SIO_PDR_MD3_GPIO_FNC__W 2 -#define SIO_PDR_MD3_GPIO_FNC__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A -#define SIO_PDR_MD4_GPIO_FNC__W 2 -#define SIO_PDR_MD4_GPIO_FNC__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B -#define SIO_PDR_MD5_GPIO_FNC__W 2 -#define SIO_PDR_MD5_GPIO_FNC__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C -#define SIO_PDR_MD6_GPIO_FNC__W 2 -#define SIO_PDR_MD6_GPIO_FNC__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D -#define SIO_PDR_MD7_GPIO_FNC__W 2 -#define SIO_PDR_MD7_GPIO_FNC__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E -#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 -#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 -#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 - -#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F -#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 -#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 -#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 - -#endif - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map_b.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map_b.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map_b.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/drxk_map_b.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,4340 +0,0 @@ -#define AUD_COMM_EXEC_STOP 0x0 -#define AUD_COMM_EXEC__A 0x1000000 -#define FEC_COMM_EXEC_ACTIVE 0x1 -#define FEC_COMM_EXEC_ACTIVE 0x1 -#define FEC_COMM_EXEC_STOP 0x0 -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_COMM_EXEC__A 0x1C00000 -#define FEC_DI_COMM_EXEC_STOP 0x0 -#define FEC_DI_COMM_EXEC__A 0x1C20000 -#define FEC_DI_INPUT_CTL__A 0x1C20016 -#define FEC_OC_AVR_PARM_A__A 0x1C40026 -#define FEC_OC_AVR_PARM_B__A 0x1C40027 -#define FEC_OC_COMM_MB_CTL_ON 0x1 -#define FEC_OC_COMM_MB__A 0x1C40002 -#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 -#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 -#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 -#define FEC_OC_DTO_MODE__A 0x1C40014 -#define FEC_OC_DTO_PERIOD__A 0x1C40015 -#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 -#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 -#define FEC_OC_FCT_MODE__A 0x1C4001A -#define FEC_OC_FCT_MODE__PRE 0x0 -#define FEC_OC_IPR_INVERT_MCLK__M 0x800 -#define FEC_OC_IPR_INVERT_MD0__B 0 -#define FEC_OC_IPR_INVERT_MD0__M 0x1 -#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD0__W 1 -#define FEC_OC_IPR_INVERT_MD1__B 1 -#define FEC_OC_IPR_INVERT_MD1__M 0x2 -#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD1__W 1 -#define FEC_OC_IPR_INVERT_MD2__B 2 -#define FEC_OC_IPR_INVERT_MD2__M 0x4 -#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD2__W 1 -#define FEC_OC_IPR_INVERT_MD3__B 3 -#define FEC_OC_IPR_INVERT_MD3__M 0x8 -#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD3__W 1 -#define FEC_OC_IPR_INVERT_MD4__B 4 -#define FEC_OC_IPR_INVERT_MD4__M 0x10 -#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD4__W 1 -#define FEC_OC_IPR_INVERT_MD5__B 5 -#define FEC_OC_IPR_INVERT_MD5__M 0x20 -#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD5__W 1 -#define FEC_OC_IPR_INVERT_MD6__B 6 -#define FEC_OC_IPR_INVERT_MD6__M 0x40 -#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD6__W 1 -#define FEC_OC_IPR_INVERT_MD7__B 7 -#define FEC_OC_IPR_INVERT_MD7__M 0x80 -#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 -#define FEC_OC_IPR_INVERT_MD7__W 1 -#define FEC_OC_IPR_INVERT_MERR__M 0x100 -#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 -#define FEC_OC_IPR_INVERT_MVAL__M 0x400 -#define FEC_OC_IPR_INVERT__A 0x1C40049 -#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 -#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 -#define FEC_OC_IPR_MODE_SERIAL__M 0x1 -#define FEC_OC_IPR_MODE__A 0x1C40048 -#define FEC_OC_IPR_MODE__A 0x1C40048 -#define FEC_OC_MODE_PARITY__M 0x1 -#define FEC_OC_MODE__A 0x1C40011 -#define FEC_OC_OCR_INVERT__A 0x1C40052 -#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 -#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 -#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 -#define FEC_OC_RCN_GAIN__A 0x1C4002E -#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 -#define FEC_OC_SNC_HWM__A 0x1C40042 -#define FEC_OC_SNC_LWM__A 0x1C40041 -#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 -#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 -#define FEC_OC_SNC_MODE__A 0x1C40040 -#define FEC_OC_SNC_MODE__A 0x1C40040 -#define FEC_OC_SNC_UNLOCK__A 0x1C40043 -#define FEC_OC_TMD_COUNT__A 0x1C4001F -#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 -#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 -#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 -#define FEC_OC_TMD_MODE__A 0x1C4001E -#define FEC_RS_COMM_EXEC_STOP 0x0 -#define FEC_RS_COMM_EXEC__A 0x1C30000 -#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 -#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 -#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 -#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 -#define IQM_AF_AGC_IF__A 0x1870028 -#define IQM_AF_AGC_RF__A 0x1870029 -#define IQM_AF_AMUX_SIGNAL2ADC 0x1 -#define IQM_AF_AMUX_SIGNAL2ADC 0x1 -#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 -#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 -#define IQM_AF_AMUX__A 0x187002D -#define IQM_AF_AMUX__A 0x187002D -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 -#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 -#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 -#define IQM_AF_CLKNEG__A 0x1870012 -#define IQM_AF_CLP_LEN__A 0x1870023 -#define IQM_AF_CLP_LEN__A 0x1870023 -#define IQM_AF_CLP_TH__A 0x1870024 -#define IQM_AF_CLP_TH__A 0x1870024 -#define IQM_AF_COMM_EXEC_ACTIVE 0x1 -#define IQM_AF_COMM_EXEC__A 0x1870000 -#define IQM_AF_INC_BYPASS__A 0x1870036 -#define IQM_AF_INC_LCT__A 0x1870034 -#define IQM_AF_PDREF__A 0x187002B -#define IQM_AF_PDREF__M 0x1F -#define IQM_AF_PHASE0__A 0x187001C -#define IQM_AF_PHASE0__M 0x7F -#define IQM_AF_PHASE0__PRE 0x0 -#define IQM_AF_PHASE0__W 7 -#define IQM_AF_PHASE1__A 0x187001D -#define IQM_AF_PHASE1__M 0x7F -#define IQM_AF_PHASE1__PRE 0x0 -#define IQM_AF_PHASE1__W 7 -#define IQM_AF_PHASE2__A 0x187001E -#define IQM_AF_PHASE2__M 0x7F -#define IQM_AF_PHASE2__PRE 0x0 -#define IQM_AF_PHASE2__W 7 -#define IQM_AF_SNS_LEN__A 0x1870026 -#define IQM_AF_SNS_LEN__A 0x1870026 -#define IQM_AF_START_LOCK__A 0x187001B -#define IQM_AF_START_LOCK__A 0x187001B -#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 -#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 -#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 -#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 -#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 -#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_STDBY__A 0x187002C -#define IQM_AF_UPD_SEL__A 0x187002F -#define IQM_AF_UPD_SEL__A 0x187002F -#define IQM_CF_ADJ_SEL__A 0x1860013 -#define IQM_CF_BYPASSDET__A 0x1860067 -#define IQM_CF_BYPASSDET__A 0x1860067 -#define IQM_CF_CLP_VAL__A 0x1860060 -#define IQM_CF_COMM_INT_MSK__A 0x1860006 -#define IQM_CF_DATATH__A 0x1860061 -#define IQM_CF_DATATH__A 0x1860061 -#define IQM_CF_DET_LCT__A 0x1860064 -#define IQM_CF_DET_LCT__A 0x1860064 -#define IQM_CF_DS_ENA__A 0x1860019 -#define IQM_CF_MIDTAP_IM__B 1 -#define IQM_CF_MIDTAP_RE__B 0 -#define IQM_CF_MIDTAP__A 0x1860011 -#define IQM_CF_OUT_ENA_QAM__B 1 -#define IQM_CF_OUT_ENA__A 0x1860012 -#define IQM_CF_OUT_ENA__A 0x1860012 -#define IQM_CF_PKDTH__A 0x1860062 -#define IQM_CF_PKDTH__A 0x1860062 -#define IQM_CF_POW_MEAS_LEN__A 0x1860017 -#define IQM_CF_POW_MEAS_LEN__A 0x1860017 -#define IQM_CF_SCALE_SH__A 0x1860015 -#define IQM_CF_SCALE_SH__A 0x1860015 -#define IQM_CF_SCALE_SH__PRE 0x0 -#define IQM_CF_SCALE__A 0x1860014 -#define IQM_CF_SYMMETRIC__A 0x1860010 -#define IQM_CF_TAP_IM0_B__B 0 -#define IQM_CF_TAP_IM0_B__M 0x7F -#define IQM_CF_TAP_IM0_B__PRE 0x2 -#define IQM_CF_TAP_IM0_B__W 7 -#define IQM_CF_TAP_IM0__A 0x1860040 -#define IQM_CF_TAP_IM0__M 0x7F -#define IQM_CF_TAP_IM0__PRE 0x2 -#define IQM_CF_TAP_IM0__W 7 -#define IQM_CF_TAP_IM10_B__B 0 -#define IQM_CF_TAP_IM10_B__M 0x1FF -#define IQM_CF_TAP_IM10_B__PRE 0x2 -#define IQM_CF_TAP_IM10_B__W 9 -#define IQM_CF_TAP_IM10__A 0x186004A -#define IQM_CF_TAP_IM10__M 0x1FF -#define IQM_CF_TAP_IM10__PRE 0x2 -#define IQM_CF_TAP_IM10__W 9 -#define IQM_CF_TAP_IM11_B__B 0 -#define IQM_CF_TAP_IM11_B__M 0x1FF -#define IQM_CF_TAP_IM11_B__PRE 0x2 -#define IQM_CF_TAP_IM11_B__W 9 -#define IQM_CF_TAP_IM11__A 0x186004B -#define IQM_CF_TAP_IM11__M 0x1FF -#define IQM_CF_TAP_IM11__PRE 0x2 -#define IQM_CF_TAP_IM11__W 9 -#define IQM_CF_TAP_IM12_B__B 0 -#define IQM_CF_TAP_IM12_B__M 0x1FF -#define IQM_CF_TAP_IM12_B__PRE 0x2 -#define IQM_CF_TAP_IM12_B__W 9 -#define IQM_CF_TAP_IM12__A 0x186004C -#define IQM_CF_TAP_IM12__M 0x1FF -#define IQM_CF_TAP_IM12__PRE 0x2 -#define IQM_CF_TAP_IM12__W 9 -#define IQM_CF_TAP_IM13_B__B 0 -#define IQM_CF_TAP_IM13_B__M 0x1FF -#define IQM_CF_TAP_IM13_B__PRE 0x2 -#define IQM_CF_TAP_IM13_B__W 9 -#define IQM_CF_TAP_IM13__A 0x186004D -#define IQM_CF_TAP_IM13__M 0x1FF -#define IQM_CF_TAP_IM13__PRE 0x2 -#define IQM_CF_TAP_IM13__W 9 -#define IQM_CF_TAP_IM14_B__B 0 -#define IQM_CF_TAP_IM14_B__M 0x1FF -#define IQM_CF_TAP_IM14_B__PRE 0x2 -#define IQM_CF_TAP_IM14_B__W 9 -#define IQM_CF_TAP_IM14__A 0x186004E -#define IQM_CF_TAP_IM14__M 0x1FF -#define IQM_CF_TAP_IM14__PRE 0x2 -#define IQM_CF_TAP_IM14__W 9 -#define IQM_CF_TAP_IM15_B__B 0 -#define IQM_CF_TAP_IM15_B__M 0x1FF -#define IQM_CF_TAP_IM15_B__PRE 0x2 -#define IQM_CF_TAP_IM15_B__W 9 -#define IQM_CF_TAP_IM15__A 0x186004F -#define IQM_CF_TAP_IM15__M 0x1FF -#define IQM_CF_TAP_IM15__PRE 0x2 -#define IQM_CF_TAP_IM15__W 9 -#define IQM_CF_TAP_IM16_B__B 0 -#define IQM_CF_TAP_IM16_B__M 0x1FF -#define IQM_CF_TAP_IM16_B__PRE 0x2 -#define IQM_CF_TAP_IM16_B__W 9 -#define IQM_CF_TAP_IM16__A 0x1860050 -#define IQM_CF_TAP_IM16__M 0x1FF -#define IQM_CF_TAP_IM16__PRE 0x2 -#define IQM_CF_TAP_IM16__W 9 -#define IQM_CF_TAP_IM17_B__B 0 -#define IQM_CF_TAP_IM17_B__M 0x1FF -#define IQM_CF_TAP_IM17_B__PRE 0x2 -#define IQM_CF_TAP_IM17_B__W 9 -#define IQM_CF_TAP_IM17__A 0x1860051 -#define IQM_CF_TAP_IM17__M 0x1FF -#define IQM_CF_TAP_IM17__PRE 0x2 -#define IQM_CF_TAP_IM17__W 9 -#define IQM_CF_TAP_IM18_B__B 0 -#define IQM_CF_TAP_IM18_B__M 0x1FF -#define IQM_CF_TAP_IM18_B__PRE 0x2 -#define IQM_CF_TAP_IM18_B__W 9 -#define IQM_CF_TAP_IM18__A 0x1860052 -#define IQM_CF_TAP_IM18__M 0x1FF -#define IQM_CF_TAP_IM18__PRE 0x2 -#define IQM_CF_TAP_IM18__W 9 -#define IQM_CF_TAP_IM19_B__B 0 -#define IQM_CF_TAP_IM19_B__M 0x1FF -#define IQM_CF_TAP_IM19_B__PRE 0x2 -#define IQM_CF_TAP_IM19_B__W 9 -#define IQM_CF_TAP_IM19__A 0x1860053 -#define IQM_CF_TAP_IM19__M 0x1FF -#define IQM_CF_TAP_IM19__PRE 0x2 -#define IQM_CF_TAP_IM19__W 9 -#define IQM_CF_TAP_IM1_B__B 0 -#define IQM_CF_TAP_IM1_B__M 0x7F -#define IQM_CF_TAP_IM1_B__PRE 0x2 -#define IQM_CF_TAP_IM1_B__W 7 -#define IQM_CF_TAP_IM1__A 0x1860041 -#define IQM_CF_TAP_IM1__M 0x7F -#define IQM_CF_TAP_IM1__PRE 0x2 -#define IQM_CF_TAP_IM1__W 7 -#define IQM_CF_TAP_IM20_B__B 0 -#define IQM_CF_TAP_IM20_B__M 0x1FF -#define IQM_CF_TAP_IM20_B__PRE 0x2 -#define IQM_CF_TAP_IM20_B__W 9 -#define IQM_CF_TAP_IM20__A 0x1860054 -#define IQM_CF_TAP_IM20__M 0x1FF -#define IQM_CF_TAP_IM20__PRE 0x2 -#define IQM_CF_TAP_IM20__W 9 -#define IQM_CF_TAP_IM21_B__B 0 -#define IQM_CF_TAP_IM21_B__M 0x7FF -#define IQM_CF_TAP_IM21_B__PRE 0x2 -#define IQM_CF_TAP_IM21_B__W 11 -#define IQM_CF_TAP_IM21__A 0x1860055 -#define IQM_CF_TAP_IM21__M 0x7FF -#define IQM_CF_TAP_IM21__PRE 0x2 -#define IQM_CF_TAP_IM21__W 11 -#define IQM_CF_TAP_IM22_B__B 0 -#define IQM_CF_TAP_IM22_B__M 0x7FF -#define IQM_CF_TAP_IM22_B__PRE 0x2 -#define IQM_CF_TAP_IM22_B__W 11 -#define IQM_CF_TAP_IM22__A 0x1860056 -#define IQM_CF_TAP_IM22__M 0x7FF -#define IQM_CF_TAP_IM22__PRE 0x2 -#define IQM_CF_TAP_IM22__W 11 -#define IQM_CF_TAP_IM23_B__B 0 -#define IQM_CF_TAP_IM23_B__M 0x7FF -#define IQM_CF_TAP_IM23_B__PRE 0x2 -#define IQM_CF_TAP_IM23_B__W 11 -#define IQM_CF_TAP_IM23__A 0x1860057 -#define IQM_CF_TAP_IM23__M 0x7FF -#define IQM_CF_TAP_IM23__PRE 0x2 -#define IQM_CF_TAP_IM23__W 11 -#define IQM_CF_TAP_IM24_B__B 0 -#define IQM_CF_TAP_IM24_B__M 0x7FF -#define IQM_CF_TAP_IM24_B__PRE 0x2 -#define IQM_CF_TAP_IM24_B__W 11 -#define IQM_CF_TAP_IM24__A 0x1860058 -#define IQM_CF_TAP_IM24__M 0x7FF -#define IQM_CF_TAP_IM24__PRE 0x2 -#define IQM_CF_TAP_IM24__W 11 -#define IQM_CF_TAP_IM25_B__B 0 -#define IQM_CF_TAP_IM25_B__M 0x7FF -#define IQM_CF_TAP_IM25_B__PRE 0x2 -#define IQM_CF_TAP_IM25_B__W 11 -#define IQM_CF_TAP_IM25__A 0x1860059 -#define IQM_CF_TAP_IM25__M 0x7FF -#define IQM_CF_TAP_IM25__PRE 0x2 -#define IQM_CF_TAP_IM25__W 11 -#define IQM_CF_TAP_IM26_B__B 0 -#define IQM_CF_TAP_IM26_B__M 0x7FF -#define IQM_CF_TAP_IM26_B__PRE 0x2 -#define IQM_CF_TAP_IM26_B__W 11 -#define IQM_CF_TAP_IM26__A 0x186005A -#define IQM_CF_TAP_IM26__M 0x7FF -#define IQM_CF_TAP_IM26__PRE 0x2 -#define IQM_CF_TAP_IM26__W 11 -#define IQM_CF_TAP_IM27_B__B 0 -#define IQM_CF_TAP_IM27_B__M 0x7FF -#define IQM_CF_TAP_IM27_B__PRE 0x2 -#define IQM_CF_TAP_IM27_B__W 11 -#define IQM_CF_TAP_IM27__A 0x186005B -#define IQM_CF_TAP_IM27__M 0x7FF -#define IQM_CF_TAP_IM27__PRE 0x2 -#define IQM_CF_TAP_IM27__W 11 -#define IQM_CF_TAP_IM2_B__B 0 -#define IQM_CF_TAP_IM2_B__M 0x7F -#define IQM_CF_TAP_IM2_B__PRE 0x2 -#define IQM_CF_TAP_IM2_B__W 7 -#define IQM_CF_TAP_IM2__A 0x1860042 -#define IQM_CF_TAP_IM2__M 0x7F -#define IQM_CF_TAP_IM2__PRE 0x2 -#define IQM_CF_TAP_IM2__W 7 -#define IQM_CF_TAP_IM3_B__B 0 -#define IQM_CF_TAP_IM3_B__M 0x7F -#define IQM_CF_TAP_IM3_B__PRE 0x2 -#define IQM_CF_TAP_IM3_B__W 7 -#define IQM_CF_TAP_IM3__A 0x1860043 -#define IQM_CF_TAP_IM3__M 0x7F -#define IQM_CF_TAP_IM3__PRE 0x2 -#define IQM_CF_TAP_IM3__W 7 -#define IQM_CF_TAP_IM4_B__B 0 -#define IQM_CF_TAP_IM4_B__M 0x7F -#define IQM_CF_TAP_IM4_B__PRE 0x2 -#define IQM_CF_TAP_IM4_B__W 7 -#define IQM_CF_TAP_IM4__A 0x1860044 -#define IQM_CF_TAP_IM4__M 0x7F -#define IQM_CF_TAP_IM4__PRE 0x2 -#define IQM_CF_TAP_IM4__W 7 -#define IQM_CF_TAP_IM5_B__B 0 -#define IQM_CF_TAP_IM5_B__M 0x7F -#define IQM_CF_TAP_IM5_B__PRE 0x2 -#define IQM_CF_TAP_IM5_B__W 7 -#define IQM_CF_TAP_IM5__A 0x1860045 -#define IQM_CF_TAP_IM5__M 0x7F -#define IQM_CF_TAP_IM5__PRE 0x2 -#define IQM_CF_TAP_IM5__W 7 -#define IQM_CF_TAP_IM6_B__B 0 -#define IQM_CF_TAP_IM6_B__M 0x7F -#define IQM_CF_TAP_IM6_B__PRE 0x2 -#define IQM_CF_TAP_IM6_B__W 7 -#define IQM_CF_TAP_IM6__A 0x1860046 -#define IQM_CF_TAP_IM6__M 0x7F -#define IQM_CF_TAP_IM6__PRE 0x2 -#define IQM_CF_TAP_IM6__W 7 -#define IQM_CF_TAP_IM7_B__B 0 -#define IQM_CF_TAP_IM7_B__M 0x1FF -#define IQM_CF_TAP_IM7_B__PRE 0x2 -#define IQM_CF_TAP_IM7_B__W 9 -#define IQM_CF_TAP_IM7__A 0x1860047 -#define IQM_CF_TAP_IM7__M 0x1FF -#define IQM_CF_TAP_IM7__PRE 0x2 -#define IQM_CF_TAP_IM7__W 9 -#define IQM_CF_TAP_IM8_B__B 0 -#define IQM_CF_TAP_IM8_B__M 0x1FF -#define IQM_CF_TAP_IM8_B__PRE 0x2 -#define IQM_CF_TAP_IM8_B__W 9 -#define IQM_CF_TAP_IM8__A 0x1860048 -#define IQM_CF_TAP_IM8__M 0x1FF -#define IQM_CF_TAP_IM8__PRE 0x2 -#define IQM_CF_TAP_IM8__W 9 -#define IQM_CF_TAP_IM9_B__B 0 -#define IQM_CF_TAP_IM9_B__M 0x1FF -#define IQM_CF_TAP_IM9_B__PRE 0x2 -#define IQM_CF_TAP_IM9_B__W 9 -#define IQM_CF_TAP_IM9__A 0x1860049 -#define IQM_CF_TAP_IM9__M 0x1FF -#define IQM_CF_TAP_IM9__PRE 0x2 -#define IQM_CF_TAP_IM9__W 9 -#define IQM_CF_TAP_RE0_B__B 0 -#define IQM_CF_TAP_RE0_B__M 0x7F -#define IQM_CF_TAP_RE0_B__PRE 0x2 -#define IQM_CF_TAP_RE0_B__W 7 -#define IQM_CF_TAP_RE0__A 0x1860020 -#define IQM_CF_TAP_RE0__M 0x7F -#define IQM_CF_TAP_RE0__PRE 0x2 -#define IQM_CF_TAP_RE0__W 7 -#define IQM_CF_TAP_RE10_B__B 0 -#define IQM_CF_TAP_RE10_B__M 0x1FF -#define IQM_CF_TAP_RE10_B__PRE 0x2 -#define IQM_CF_TAP_RE10_B__W 9 -#define IQM_CF_TAP_RE10__A 0x186002A -#define IQM_CF_TAP_RE10__M 0x1FF -#define IQM_CF_TAP_RE10__PRE 0x2 -#define IQM_CF_TAP_RE10__W 9 -#define IQM_CF_TAP_RE11_B__B 0 -#define IQM_CF_TAP_RE11_B__M 0x1FF -#define IQM_CF_TAP_RE11_B__PRE 0x2 -#define IQM_CF_TAP_RE11_B__W 9 -#define IQM_CF_TAP_RE11__A 0x186002B -#define IQM_CF_TAP_RE11__M 0x1FF -#define IQM_CF_TAP_RE11__PRE 0x2 -#define IQM_CF_TAP_RE11__W 9 -#define IQM_CF_TAP_RE12_B__B 0 -#define IQM_CF_TAP_RE12_B__M 0x1FF -#define IQM_CF_TAP_RE12_B__PRE 0x2 -#define IQM_CF_TAP_RE12_B__W 9 -#define IQM_CF_TAP_RE12__A 0x186002C -#define IQM_CF_TAP_RE12__M 0x1FF -#define IQM_CF_TAP_RE12__PRE 0x2 -#define IQM_CF_TAP_RE12__W 9 -#define IQM_CF_TAP_RE13_B__B 0 -#define IQM_CF_TAP_RE13_B__M 0x1FF -#define IQM_CF_TAP_RE13_B__PRE 0x2 -#define IQM_CF_TAP_RE13_B__W 9 -#define IQM_CF_TAP_RE13__A 0x186002D -#define IQM_CF_TAP_RE13__M 0x1FF -#define IQM_CF_TAP_RE13__PRE 0x2 -#define IQM_CF_TAP_RE13__W 9 -#define IQM_CF_TAP_RE14_B__B 0 -#define IQM_CF_TAP_RE14_B__M 0x1FF -#define IQM_CF_TAP_RE14_B__PRE 0x2 -#define IQM_CF_TAP_RE14_B__W 9 -#define IQM_CF_TAP_RE14__A 0x186002E -#define IQM_CF_TAP_RE14__M 0x1FF -#define IQM_CF_TAP_RE14__PRE 0x2 -#define IQM_CF_TAP_RE14__W 9 -#define IQM_CF_TAP_RE15_B__B 0 -#define IQM_CF_TAP_RE15_B__M 0x1FF -#define IQM_CF_TAP_RE15_B__PRE 0x2 -#define IQM_CF_TAP_RE15_B__W 9 -#define IQM_CF_TAP_RE15__A 0x186002F -#define IQM_CF_TAP_RE15__M 0x1FF -#define IQM_CF_TAP_RE15__PRE 0x2 -#define IQM_CF_TAP_RE15__W 9 -#define IQM_CF_TAP_RE16_B__B 0 -#define IQM_CF_TAP_RE16_B__M 0x1FF -#define IQM_CF_TAP_RE16_B__PRE 0x2 -#define IQM_CF_TAP_RE16_B__W 9 -#define IQM_CF_TAP_RE16__A 0x1860030 -#define IQM_CF_TAP_RE16__M 0x1FF -#define IQM_CF_TAP_RE16__PRE 0x2 -#define IQM_CF_TAP_RE16__W 9 -#define IQM_CF_TAP_RE17_B__B 0 -#define IQM_CF_TAP_RE17_B__M 0x1FF -#define IQM_CF_TAP_RE17_B__PRE 0x2 -#define IQM_CF_TAP_RE17_B__W 9 -#define IQM_CF_TAP_RE17__A 0x1860031 -#define IQM_CF_TAP_RE17__M 0x1FF -#define IQM_CF_TAP_RE17__PRE 0x2 -#define IQM_CF_TAP_RE17__W 9 -#define IQM_CF_TAP_RE18_B__B 0 -#define IQM_CF_TAP_RE18_B__M 0x1FF -#define IQM_CF_TAP_RE18_B__PRE 0x2 -#define IQM_CF_TAP_RE18_B__W 9 -#define IQM_CF_TAP_RE18__A 0x1860032 -#define IQM_CF_TAP_RE18__M 0x1FF -#define IQM_CF_TAP_RE18__PRE 0x2 -#define IQM_CF_TAP_RE18__W 9 -#define IQM_CF_TAP_RE19_B__B 0 -#define IQM_CF_TAP_RE19_B__M 0x1FF -#define IQM_CF_TAP_RE19_B__PRE 0x2 -#define IQM_CF_TAP_RE19_B__W 9 -#define IQM_CF_TAP_RE19__A 0x1860033 -#define IQM_CF_TAP_RE19__M 0x1FF -#define IQM_CF_TAP_RE19__PRE 0x2 -#define IQM_CF_TAP_RE19__W 9 -#define IQM_CF_TAP_RE1_B__B 0 -#define IQM_CF_TAP_RE1_B__M 0x7F -#define IQM_CF_TAP_RE1_B__PRE 0x2 -#define IQM_CF_TAP_RE1_B__W 7 -#define IQM_CF_TAP_RE1__A 0x1860021 -#define IQM_CF_TAP_RE1__M 0x7F -#define IQM_CF_TAP_RE1__PRE 0x2 -#define IQM_CF_TAP_RE1__W 7 -#define IQM_CF_TAP_RE20_B__B 0 -#define IQM_CF_TAP_RE20_B__M 0x1FF -#define IQM_CF_TAP_RE20_B__PRE 0x2 -#define IQM_CF_TAP_RE20_B__W 9 -#define IQM_CF_TAP_RE20__A 0x1860034 -#define IQM_CF_TAP_RE20__M 0x1FF -#define IQM_CF_TAP_RE20__PRE 0x2 -#define IQM_CF_TAP_RE20__W 9 -#define IQM_CF_TAP_RE21_B__B 0 -#define IQM_CF_TAP_RE21_B__M 0x7FF -#define IQM_CF_TAP_RE21_B__PRE 0x2 -#define IQM_CF_TAP_RE21_B__W 11 -#define IQM_CF_TAP_RE21__A 0x1860035 -#define IQM_CF_TAP_RE21__M 0x7FF -#define IQM_CF_TAP_RE21__PRE 0x2 -#define IQM_CF_TAP_RE21__W 11 -#define IQM_CF_TAP_RE22_B__B 0 -#define IQM_CF_TAP_RE22_B__M 0x7FF -#define IQM_CF_TAP_RE22_B__PRE 0x2 -#define IQM_CF_TAP_RE22_B__W 11 -#define IQM_CF_TAP_RE22__A 0x1860036 -#define IQM_CF_TAP_RE22__M 0x7FF -#define IQM_CF_TAP_RE22__PRE 0x2 -#define IQM_CF_TAP_RE22__W 11 -#define IQM_CF_TAP_RE23_B__B 0 -#define IQM_CF_TAP_RE23_B__M 0x7FF -#define IQM_CF_TAP_RE23_B__PRE 0x2 -#define IQM_CF_TAP_RE23_B__W 11 -#define IQM_CF_TAP_RE23__A 0x1860037 -#define IQM_CF_TAP_RE23__M 0x7FF -#define IQM_CF_TAP_RE23__PRE 0x2 -#define IQM_CF_TAP_RE23__W 11 -#define IQM_CF_TAP_RE24_B__B 0 -#define IQM_CF_TAP_RE24_B__M 0x7FF -#define IQM_CF_TAP_RE24_B__PRE 0x2 -#define IQM_CF_TAP_RE24_B__W 11 -#define IQM_CF_TAP_RE24__A 0x1860038 -#define IQM_CF_TAP_RE24__M 0x7FF -#define IQM_CF_TAP_RE24__PRE 0x2 -#define IQM_CF_TAP_RE24__W 11 -#define IQM_CF_TAP_RE25_B__B 0 -#define IQM_CF_TAP_RE25_B__M 0x7FF -#define IQM_CF_TAP_RE25_B__PRE 0x2 -#define IQM_CF_TAP_RE25_B__W 11 -#define IQM_CF_TAP_RE25__A 0x1860039 -#define IQM_CF_TAP_RE25__M 0x7FF -#define IQM_CF_TAP_RE25__PRE 0x2 -#define IQM_CF_TAP_RE25__W 11 -#define IQM_CF_TAP_RE26_B__B 0 -#define IQM_CF_TAP_RE26_B__M 0x7FF -#define IQM_CF_TAP_RE26_B__PRE 0x2 -#define IQM_CF_TAP_RE26_B__W 11 -#define IQM_CF_TAP_RE26__A 0x186003A -#define IQM_CF_TAP_RE26__M 0x7FF -#define IQM_CF_TAP_RE26__PRE 0x2 -#define IQM_CF_TAP_RE26__W 11 -#define IQM_CF_TAP_RE27_B__B 0 -#define IQM_CF_TAP_RE27_B__M 0x7FF -#define IQM_CF_TAP_RE27_B__PRE 0x2 -#define IQM_CF_TAP_RE27_B__W 11 -#define IQM_CF_TAP_RE27__A 0x186003B -#define IQM_CF_TAP_RE27__M 0x7FF -#define IQM_CF_TAP_RE27__PRE 0x2 -#define IQM_CF_TAP_RE27__W 11 -#define IQM_CF_TAP_RE2_B__B 0 -#define IQM_CF_TAP_RE2_B__M 0x7F -#define IQM_CF_TAP_RE2_B__PRE 0x2 -#define IQM_CF_TAP_RE2_B__W 7 -#define IQM_CF_TAP_RE2__A 0x1860022 -#define IQM_CF_TAP_RE2__M 0x7F -#define IQM_CF_TAP_RE2__PRE 0x2 -#define IQM_CF_TAP_RE2__W 7 -#define IQM_CF_TAP_RE3_B__B 0 -#define IQM_CF_TAP_RE3_B__M 0x7F -#define IQM_CF_TAP_RE3_B__PRE 0x2 -#define IQM_CF_TAP_RE3_B__W 7 -#define IQM_CF_TAP_RE3__A 0x1860023 -#define IQM_CF_TAP_RE3__M 0x7F -#define IQM_CF_TAP_RE3__PRE 0x2 -#define IQM_CF_TAP_RE3__W 7 -#define IQM_CF_TAP_RE4_B__B 0 -#define IQM_CF_TAP_RE4_B__M 0x7F -#define IQM_CF_TAP_RE4_B__PRE 0x2 -#define IQM_CF_TAP_RE4_B__W 7 -#define IQM_CF_TAP_RE4__A 0x1860024 -#define IQM_CF_TAP_RE4__M 0x7F -#define IQM_CF_TAP_RE4__PRE 0x2 -#define IQM_CF_TAP_RE4__W 7 -#define IQM_CF_TAP_RE5_B__B 0 -#define IQM_CF_TAP_RE5_B__M 0x7F -#define IQM_CF_TAP_RE5_B__PRE 0x2 -#define IQM_CF_TAP_RE5_B__W 7 -#define IQM_CF_TAP_RE5__A 0x1860025 -#define IQM_CF_TAP_RE5__M 0x7F -#define IQM_CF_TAP_RE5__PRE 0x2 -#define IQM_CF_TAP_RE5__W 7 -#define IQM_CF_TAP_RE6_B__B 0 -#define IQM_CF_TAP_RE6_B__M 0x7F -#define IQM_CF_TAP_RE6_B__PRE 0x2 -#define IQM_CF_TAP_RE6_B__W 7 -#define IQM_CF_TAP_RE6__A 0x1860026 -#define IQM_CF_TAP_RE6__M 0x7F -#define IQM_CF_TAP_RE6__PRE 0x2 -#define IQM_CF_TAP_RE6__W 7 -#define IQM_CF_TAP_RE7_B__B 0 -#define IQM_CF_TAP_RE7_B__M 0x1FF -#define IQM_CF_TAP_RE7_B__PRE 0x2 -#define IQM_CF_TAP_RE7_B__W 9 -#define IQM_CF_TAP_RE7__A 0x1860027 -#define IQM_CF_TAP_RE7__M 0x1FF -#define IQM_CF_TAP_RE7__PRE 0x2 -#define IQM_CF_TAP_RE7__W 9 -#define IQM_CF_TAP_RE8_B__B 0 -#define IQM_CF_TAP_RE8_B__M 0x1FF -#define IQM_CF_TAP_RE8_B__PRE 0x2 -#define IQM_CF_TAP_RE8_B__W 9 -#define IQM_CF_TAP_RE8__A 0x1860028 -#define IQM_CF_TAP_RE8__M 0x1FF -#define IQM_CF_TAP_RE8__PRE 0x2 -#define IQM_CF_TAP_RE8__W 9 -#define IQM_CF_TAP_RE9_B__B 0 -#define IQM_CF_TAP_RE9_B__M 0x1FF -#define IQM_CF_TAP_RE9_B__PRE 0x2 -#define IQM_CF_TAP_RE9_B__W 9 -#define IQM_CF_TAP_RE9__A 0x1860029 -#define IQM_CF_TAP_RE9__M 0x1FF -#define IQM_CF_TAP_RE9__PRE 0x2 -#define IQM_CF_TAP_RE9__W 9 -#define IQM_CF_WND_LEN__A 0x1860063 -#define IQM_CF_WND_LEN__A 0x1860063 -#define IQM_COMM_EXEC_B_ACTIVE 0x1 -#define IQM_COMM_EXEC_B_ACTIVE 0x1 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC_B_STOP 0x0 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_COMM_EXEC__A 0x1800000 -#define IQM_FD_RATESEL__A 0x1830010 -#define IQM_FS_ADJ_SEL__A 0x1820014 -#define IQM_FS_RATE_LO__A 0x1820012 -#define IQM_FS_RATE_OFS_LO__A 0x1820010 -#define IQM_RC_ADJ_SEL__A 0x1840014 -#define IQM_RC_RATE_OFS_HI__M 0xFF -#define IQM_RC_RATE_OFS_LO__A 0x1840010 -#define IQM_RC_RATE_OFS_LO__A 0x1840010 -#define IQM_RC_RATE_OFS_LO__M 0xFFFF -#define IQM_RC_RATE_OFS_LO__W 16 -#define IQM_RC_STRETCH__A 0x1840016 -#define IQM_RC_STRETCH__A 0x1840016 -#define OFDM_CP_COMM_EXEC_STOP 0x0 -#define OFDM_CP_COMM_EXEC__A 0x2800000 -#define OFDM_EC_SB_PRIOR_HI 0x0 -#define OFDM_EC_SB_PRIOR__A 0x3410013 -#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 -#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 -#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E -#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 -#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 -#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 -#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 -#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 -#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 -#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 -#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 -#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 -#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC_STOP 0x0 -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_LC_COMM_EXEC__A 0x3800000 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC_STOP 0x0 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_EXEC__A 0x3C00000 -#define OFDM_SC_COMM_STATE__A 0x3C00001 -#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 -#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define OFDM_SC_RA_RAM_CMD_NULL 0x0 -#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 -#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 -#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 -#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 -#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 -#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 -#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 -#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 -#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 -#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 -#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F -#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F -#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 -#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C -#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 -#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 -#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D -#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C -#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 -#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 -#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 -#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 -#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 -#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 -#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 -#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 -#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 -#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 -#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 -#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 -#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM0__W 16 -#define OFDM_SC_RA_RAM_PARAM0__W 16 -#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 -#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 -#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF -#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 -#define OFDM_SC_RA_RAM_PARAM1__W 16 -#define OFDM_SC_RA_RAM_PARAM1__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F -#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 -#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define QAM_COMM_EXEC_ACTIVE 0x1 -#define QAM_COMM_EXEC_STOP 0x0 -#define QAM_COMM_EXEC_STOP 0x0 -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_COMM_EXEC__A 0x1400000 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__B 0 -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0_BIT__W 6 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__A 0x1440018 -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__M 0x3F -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__PRE 0x4 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN0__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__B 0 -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1_BIT__W 6 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__A 0x1440019 -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__M 0x3F -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__PRE 0x4 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN1__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__B 0 -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2_BIT__W 6 -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__A 0x144001A -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__M 0x3F -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__PRE 0x4 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN2__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__B 0 -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3_BIT__W 6 -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__A 0x144001B -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__M 0x3F -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__PRE 0x4 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN3__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__B 0 -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4_BIT__W 6 -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__A 0x144001C -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__M 0x3F -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__PRE 0x6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN4__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__B 0 -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5_BIT__W 6 -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__A 0x144001D -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__M 0x3F -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__PRE 0x6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_DQ_QUAL_FUN5__W 6 -#define QAM_LC_LPF_FACTORI__A 0x1450029 -#define QAM_LC_LPF_FACTORP__A 0x1450028 -#define QAM_LC_MODE__A 0x1450010 -#define QAM_LC_QUAL_TAB0_VALUE__B 0 -#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 -#define QAM_LC_QUAL_TAB0_VALUE__W 5 -#define QAM_LC_QUAL_TAB0__A 0x1450018 -#define QAM_LC_QUAL_TAB0__M 0x1F -#define QAM_LC_QUAL_TAB0__PRE 0x0 -#define QAM_LC_QUAL_TAB0__W 5 -#define QAM_LC_QUAL_TAB10_VALUE__B 0 -#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA -#define QAM_LC_QUAL_TAB10_VALUE__W 5 -#define QAM_LC_QUAL_TAB10__A 0x1450021 -#define QAM_LC_QUAL_TAB10__M 0x1F -#define QAM_LC_QUAL_TAB10__PRE 0xA -#define QAM_LC_QUAL_TAB10__W 5 -#define QAM_LC_QUAL_TAB12_VALUE__B 0 -#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC -#define QAM_LC_QUAL_TAB12_VALUE__W 5 -#define QAM_LC_QUAL_TAB12__A 0x1450022 -#define QAM_LC_QUAL_TAB12__M 0x1F -#define QAM_LC_QUAL_TAB12__PRE 0xC -#define QAM_LC_QUAL_TAB12__W 5 -#define QAM_LC_QUAL_TAB15_VALUE__B 0 -#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF -#define QAM_LC_QUAL_TAB15_VALUE__W 5 -#define QAM_LC_QUAL_TAB15__A 0x1450023 -#define QAM_LC_QUAL_TAB15__M 0x1F -#define QAM_LC_QUAL_TAB15__PRE 0xF -#define QAM_LC_QUAL_TAB15__W 5 -#define QAM_LC_QUAL_TAB16_VALUE__B 0 -#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 -#define QAM_LC_QUAL_TAB16_VALUE__W 5 -#define QAM_LC_QUAL_TAB16__A 0x1450024 -#define QAM_LC_QUAL_TAB16__M 0x1F -#define QAM_LC_QUAL_TAB16__PRE 0x10 -#define QAM_LC_QUAL_TAB16__W 5 -#define QAM_LC_QUAL_TAB1_VALUE__B 0 -#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 -#define QAM_LC_QUAL_TAB1_VALUE__W 5 -#define QAM_LC_QUAL_TAB1__A 0x1450019 -#define QAM_LC_QUAL_TAB1__M 0x1F -#define QAM_LC_QUAL_TAB1__PRE 0x1 -#define QAM_LC_QUAL_TAB1__W 5 -#define QAM_LC_QUAL_TAB20_VALUE__B 0 -#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 -#define QAM_LC_QUAL_TAB20_VALUE__W 5 -#define QAM_LC_QUAL_TAB20__A 0x1450025 -#define QAM_LC_QUAL_TAB20__M 0x1F -#define QAM_LC_QUAL_TAB20__PRE 0x14 -#define QAM_LC_QUAL_TAB20__W 5 -#define QAM_LC_QUAL_TAB25_VALUE__B 0 -#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 -#define QAM_LC_QUAL_TAB25_VALUE__W 5 -#define QAM_LC_QUAL_TAB25__A 0x1450026 -#define QAM_LC_QUAL_TAB25__M 0x1F -#define QAM_LC_QUAL_TAB25__PRE 0x19 -#define QAM_LC_QUAL_TAB25__W 5 -#define QAM_LC_QUAL_TAB2_VALUE__B 0 -#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 -#define QAM_LC_QUAL_TAB2_VALUE__W 5 -#define QAM_LC_QUAL_TAB2__A 0x145001A -#define QAM_LC_QUAL_TAB2__M 0x1F -#define QAM_LC_QUAL_TAB2__PRE 0x2 -#define QAM_LC_QUAL_TAB2__W 5 -#define QAM_LC_QUAL_TAB3_VALUE__B 0 -#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 -#define QAM_LC_QUAL_TAB3_VALUE__W 5 -#define QAM_LC_QUAL_TAB3__A 0x145001B -#define QAM_LC_QUAL_TAB3__M 0x1F -#define QAM_LC_QUAL_TAB3__PRE 0x3 -#define QAM_LC_QUAL_TAB3__W 5 -#define QAM_LC_QUAL_TAB4_VALUE__B 0 -#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 -#define QAM_LC_QUAL_TAB4_VALUE__W 5 -#define QAM_LC_QUAL_TAB4__A 0x145001C -#define QAM_LC_QUAL_TAB4__M 0x1F -#define QAM_LC_QUAL_TAB4__PRE 0x4 -#define QAM_LC_QUAL_TAB4__W 5 -#define QAM_LC_QUAL_TAB5_VALUE__B 0 -#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 -#define QAM_LC_QUAL_TAB5_VALUE__W 5 -#define QAM_LC_QUAL_TAB5__A 0x145001D -#define QAM_LC_QUAL_TAB5__M 0x1F -#define QAM_LC_QUAL_TAB5__PRE 0x5 -#define QAM_LC_QUAL_TAB5__W 5 -#define QAM_LC_QUAL_TAB6_VALUE__B 0 -#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 -#define QAM_LC_QUAL_TAB6_VALUE__W 5 -#define QAM_LC_QUAL_TAB6__A 0x145001E -#define QAM_LC_QUAL_TAB6__M 0x1F -#define QAM_LC_QUAL_TAB6__PRE 0x6 -#define QAM_LC_QUAL_TAB6__W 5 -#define QAM_LC_QUAL_TAB8_VALUE__B 0 -#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 -#define QAM_LC_QUAL_TAB8_VALUE__W 5 -#define QAM_LC_QUAL_TAB8__A 0x145001F -#define QAM_LC_QUAL_TAB8__M 0x1F -#define QAM_LC_QUAL_TAB8__PRE 0x8 -#define QAM_LC_QUAL_TAB8__W 5 -#define QAM_LC_QUAL_TAB9_VALUE__B 0 -#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F -#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 -#define QAM_LC_QUAL_TAB9_VALUE__W 5 -#define QAM_LC_QUAL_TAB9__A 0x1450020 -#define QAM_LC_QUAL_TAB9__M 0x1F -#define QAM_LC_QUAL_TAB9__PRE 0x9 -#define QAM_LC_QUAL_TAB9__W 5 -#define QAM_LC_RATE_LIMIT__A 0x145002A -#define QAM_LC_SYMBOL_FREQ__A 0x145002B -#define QAM_SL_ERR_POWER__A 0x1430017 -#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 -#define QAM_SY_SP_INV__A 0x1470017 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_AWM__A 0x1470013 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_HWM__A 0x1470014 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_SYNC_LWM__A 0x1470012 -#define QAM_SY_TIMEOUT__A 0x1470011 -#define QAM_SY_TIMEOUT__PRE 0x3A98 -#define QAM_TOP_ANNEX_A 0x0 -#define QAM_TOP_ANNEX_C 0x2 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_ACTIVE 0x1 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_HOLD 0x2 -#define SCU_COMM_EXEC_STOP 0x0 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_COMM_EXEC__A 0x800000 -#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 -#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 -#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 -#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 -#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 -#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 -#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F -#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E -#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D -#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 -#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 -#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 -#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 -#define SCU_RAM_AGC_CONFIG__A 0x831F24 -#define SCU_RAM_AGC_CONFIG__A 0x831F24 -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA -#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA -#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 -#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 -#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 -#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 -#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F -#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F -#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E -#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E -#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D -#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 -#define SCU_RAM_AGC_KI_IF__B 8 -#define SCU_RAM_AGC_KI_IF__M 0xF00 -#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 -#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 -#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A -#define SCU_RAM_AGC_KI_MAX__A 0x831F2C -#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 -#define SCU_RAM_AGC_KI_MIN__A 0x831F2B -#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 -#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 -#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC -#define SCU_RAM_AGC_KI_RED__A 0x831F26 -#define SCU_RAM_AGC_KI_RED__A 0x831F26 -#define SCU_RAM_AGC_KI_RF__B 4 -#define SCU_RAM_AGC_KI_RF__M 0xF0 -#define SCU_RAM_AGC_KI__A 0x831F25 -#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 -#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 -#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 -#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 -#define SCU_RAM_AGC_RF_MAX__A 0x831F1B -#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 -#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A -#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 -#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 -#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B -#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 -#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A -#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 -#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 -#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 -#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 -#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 -#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 -#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -#define SCU_RAM_COMMAND__A 0x831FFD -#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF -#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB -#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC -#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB -#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_GPIO__A 0x831EC7 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 -#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 -#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 -#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD -#define SCU_RAM_PARAM_0_RESULT_OK 0x0 -#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC -#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF -#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE -#define SCU_RAM_PARAM_0__A 0x831FFC -#define SCU_RAM_PARAM_0__M 0xFFFF -#define SCU_RAM_PARAM_0__PRE 0x0 -#define SCU_RAM_PARAM_0__W 16 -#define SCU_RAM_PARAM_10__A 0x831FF2 -#define SCU_RAM_PARAM_10__M 0xFFFF -#define SCU_RAM_PARAM_10__PRE 0x0 -#define SCU_RAM_PARAM_10__W 16 -#define SCU_RAM_PARAM_11__A 0x831FF1 -#define SCU_RAM_PARAM_11__M 0xFFFF -#define SCU_RAM_PARAM_11__PRE 0x0 -#define SCU_RAM_PARAM_11__W 16 -#define SCU_RAM_PARAM_12__A 0x831FF0 -#define SCU_RAM_PARAM_12__M 0xFFFF -#define SCU_RAM_PARAM_12__PRE 0x0 -#define SCU_RAM_PARAM_12__W 16 -#define SCU_RAM_PARAM_13__A 0x831FEF -#define SCU_RAM_PARAM_13__M 0xFFFF -#define SCU_RAM_PARAM_13__PRE 0x0 -#define SCU_RAM_PARAM_13__W 16 -#define SCU_RAM_PARAM_14__A 0x831FEE -#define SCU_RAM_PARAM_14__M 0xFFFF -#define SCU_RAM_PARAM_14__PRE 0x0 -#define SCU_RAM_PARAM_14__W 16 -#define SCU_RAM_PARAM_15__A 0x831FED -#define SCU_RAM_PARAM_15__M 0xFFFF -#define SCU_RAM_PARAM_15__PRE 0x0 -#define SCU_RAM_PARAM_15__W 16 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 -#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 -#define SCU_RAM_PARAM_1__A 0x831FFB -#define SCU_RAM_PARAM_1__M 0xFFFF -#define SCU_RAM_PARAM_1__PRE 0x0 -#define SCU_RAM_PARAM_1__W 16 -#define SCU_RAM_PARAM_2__A 0x831FFA -#define SCU_RAM_PARAM_2__M 0xFFFF -#define SCU_RAM_PARAM_2__PRE 0x0 -#define SCU_RAM_PARAM_2__W 16 -#define SCU_RAM_PARAM_3__A 0x831FF9 -#define SCU_RAM_PARAM_3__M 0xFFFF -#define SCU_RAM_PARAM_3__PRE 0x0 -#define SCU_RAM_PARAM_3__W 16 -#define SCU_RAM_PARAM_4__A 0x831FF8 -#define SCU_RAM_PARAM_4__M 0xFFFF -#define SCU_RAM_PARAM_4__PRE 0x0 -#define SCU_RAM_PARAM_4__W 16 -#define SCU_RAM_PARAM_5__A 0x831FF7 -#define SCU_RAM_PARAM_5__M 0xFFFF -#define SCU_RAM_PARAM_5__PRE 0x0 -#define SCU_RAM_PARAM_5__W 16 -#define SCU_RAM_PARAM_6__A 0x831FF6 -#define SCU_RAM_PARAM_6__M 0xFFFF -#define SCU_RAM_PARAM_6__PRE 0x0 -#define SCU_RAM_PARAM_6__W 16 -#define SCU_RAM_PARAM_7__A 0x831FF5 -#define SCU_RAM_PARAM_7__M 0xFFFF -#define SCU_RAM_PARAM_7__PRE 0x0 -#define SCU_RAM_PARAM_7__W 16 -#define SCU_RAM_PARAM_8__A 0x831FF4 -#define SCU_RAM_PARAM_8__M 0xFFFF -#define SCU_RAM_PARAM_8__PRE 0x0 -#define SCU_RAM_PARAM_8__W 16 -#define SCU_RAM_PARAM_9__A 0x831FF3 -#define SCU_RAM_PARAM_9__M 0xFFFF -#define SCU_RAM_PARAM_9__PRE 0x0 -#define SCU_RAM_PARAM_9__W 16 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_FINE__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_COARSE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_FINE__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 -#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 -#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -#define SIO_BL_CHAIN_ADDR__A 0x480018 -#define SIO_BL_CHAIN_LEN__A 0x480019 -#define SIO_BL_COMM_EXEC_ACTIVE 0x1 -#define SIO_BL_COMM_EXEC__A 0x480000 -#define SIO_BL_ENABLE_ON 0x1 -#define SIO_BL_ENABLE_ON 0x1 -#define SIO_BL_ENABLE__A 0x480012 -#define SIO_BL_ENABLE__A 0x480012 -#define SIO_BL_MODE_CHAIN 0x1 -#define SIO_BL_MODE_DIRECT 0x0 -#define SIO_BL_MODE__A 0x480011 -#define SIO_BL_MODE__A 0x480011 -#define SIO_BL_SRC_ADDR__A 0x480016 -#define SIO_BL_SRC_LEN__A 0x480017 -#define SIO_BL_STATUS__A 0x480010 -#define SIO_BL_STATUS__A 0x480010 -#define SIO_BL_TGT_ADDR__A 0x480015 -#define SIO_BL_TGT_HDR__A 0x480014 -#define SIO_CC_PLL_LOCK__A 0x450012 -#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 -#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 -#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 -#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 -#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 -#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_PWD_MODE__A 0x450015 -#define SIO_CC_SOFT_RST_OFDM__M 0x1 -#define SIO_CC_SOFT_RST_OSC__M 0x4 -#define SIO_CC_SOFT_RST_SYS__M 0x2 -#define SIO_CC_SOFT_RST__A 0x450016 -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE_KEY 0xFABA -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_CC_UPDATE__A 0x450017 -#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 -#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 -#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 -#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 -#define SIO_HI_RA_RAM_CMD_RESET 0x2 -#define SIO_HI_RA_RAM_CMD__A 0x420032 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_1__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_2__W 16 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_3__W 16 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_4__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_5__W 16 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_PAR_6__W 16 -#define SIO_HI_RA_RAM_RES__A 0x420031 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 -#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 -#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 -#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 -#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 -#define SIO_PDR_MCLK_CFG_DRIVE__B 3 -#define SIO_PDR_MCLK_CFG__A 0x7F0028 -#define SIO_PDR_MD0_CFG_DRIVE__B 3 -#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD0_CFG_DRIVE__W 3 -#define SIO_PDR_MD0_CFG_KEEP__B 6 -#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD0_CFG_KEEP__W 2 -#define SIO_PDR_MD0_CFG_MODE__B 0 -#define SIO_PDR_MD0_CFG_MODE__M 0x7 -#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD0_CFG_MODE__W 3 -#define SIO_PDR_MD0_CFG_UIO__B 8 -#define SIO_PDR_MD0_CFG_UIO__M 0x100 -#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD0_CFG_UIO__W 1 -#define SIO_PDR_MD0_CFG__A 0x7F002A -#define SIO_PDR_MD0_CFG__M 0x1FF -#define SIO_PDR_MD0_CFG__PRE 0x50 -#define SIO_PDR_MD0_CFG__W 9 -#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 -#define SIO_PDR_MD0_GPIO_FNC__M 0x3 -#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD0_GPIO_FNC__W 2 -#define SIO_PDR_MD1_CFG_DRIVE__B 3 -#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD1_CFG_DRIVE__W 3 -#define SIO_PDR_MD1_CFG_KEEP__B 6 -#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD1_CFG_KEEP__W 2 -#define SIO_PDR_MD1_CFG_MODE__B 0 -#define SIO_PDR_MD1_CFG_MODE__M 0x7 -#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD1_CFG_MODE__W 3 -#define SIO_PDR_MD1_CFG_UIO__B 8 -#define SIO_PDR_MD1_CFG_UIO__M 0x100 -#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD1_CFG_UIO__W 1 -#define SIO_PDR_MD1_CFG__A 0x7F002B -#define SIO_PDR_MD1_CFG__M 0x1FF -#define SIO_PDR_MD1_CFG__PRE 0x50 -#define SIO_PDR_MD1_CFG__W 9 -#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 -#define SIO_PDR_MD1_GPIO_FNC__M 0x3 -#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD1_GPIO_FNC__W 2 -#define SIO_PDR_MD2_CFG_DRIVE__B 3 -#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD2_CFG_DRIVE__W 3 -#define SIO_PDR_MD2_CFG_KEEP__B 6 -#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD2_CFG_KEEP__W 2 -#define SIO_PDR_MD2_CFG_MODE__B 0 -#define SIO_PDR_MD2_CFG_MODE__M 0x7 -#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD2_CFG_MODE__W 3 -#define SIO_PDR_MD2_CFG_UIO__B 8 -#define SIO_PDR_MD2_CFG_UIO__M 0x100 -#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD2_CFG_UIO__W 1 -#define SIO_PDR_MD2_CFG__A 0x7F002C -#define SIO_PDR_MD2_CFG__M 0x1FF -#define SIO_PDR_MD2_CFG__PRE 0x50 -#define SIO_PDR_MD2_CFG__W 9 -#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 -#define SIO_PDR_MD2_GPIO_FNC__M 0x3 -#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD2_GPIO_FNC__W 2 -#define SIO_PDR_MD3_CFG_DRIVE__B 3 -#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD3_CFG_DRIVE__W 3 -#define SIO_PDR_MD3_CFG_KEEP__B 6 -#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD3_CFG_KEEP__W 2 -#define SIO_PDR_MD3_CFG_MODE__B 0 -#define SIO_PDR_MD3_CFG_MODE__M 0x7 -#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD3_CFG_MODE__W 3 -#define SIO_PDR_MD3_CFG_UIO__B 8 -#define SIO_PDR_MD3_CFG_UIO__M 0x100 -#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD3_CFG_UIO__W 1 -#define SIO_PDR_MD3_CFG__A 0x7F002D -#define SIO_PDR_MD3_CFG__M 0x1FF -#define SIO_PDR_MD3_CFG__PRE 0x50 -#define SIO_PDR_MD3_CFG__W 9 -#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 -#define SIO_PDR_MD3_GPIO_FNC__M 0x3 -#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD3_GPIO_FNC__W 2 -#define SIO_PDR_MD4_CFG_DRIVE__B 3 -#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD4_CFG_DRIVE__W 3 -#define SIO_PDR_MD4_CFG_KEEP__B 6 -#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD4_CFG_KEEP__W 2 -#define SIO_PDR_MD4_CFG_MODE__B 0 -#define SIO_PDR_MD4_CFG_MODE__M 0x7 -#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD4_CFG_MODE__W 3 -#define SIO_PDR_MD4_CFG_UIO__B 8 -#define SIO_PDR_MD4_CFG_UIO__M 0x100 -#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD4_CFG_UIO__W 1 -#define SIO_PDR_MD4_CFG__A 0x7F002F -#define SIO_PDR_MD4_CFG__M 0x1FF -#define SIO_PDR_MD4_CFG__PRE 0x50 -#define SIO_PDR_MD4_CFG__W 9 -#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A -#define SIO_PDR_MD4_GPIO_FNC__M 0x3 -#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD4_GPIO_FNC__W 2 -#define SIO_PDR_MD5_CFG_DRIVE__B 3 -#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD5_CFG_DRIVE__W 3 -#define SIO_PDR_MD5_CFG_KEEP__B 6 -#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD5_CFG_KEEP__W 2 -#define SIO_PDR_MD5_CFG_MODE__B 0 -#define SIO_PDR_MD5_CFG_MODE__M 0x7 -#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD5_CFG_MODE__W 3 -#define SIO_PDR_MD5_CFG_UIO__B 8 -#define SIO_PDR_MD5_CFG_UIO__M 0x100 -#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD5_CFG_UIO__W 1 -#define SIO_PDR_MD5_CFG__A 0x7F0030 -#define SIO_PDR_MD5_CFG__M 0x1FF -#define SIO_PDR_MD5_CFG__PRE 0x50 -#define SIO_PDR_MD5_CFG__W 9 -#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B -#define SIO_PDR_MD5_GPIO_FNC__M 0x3 -#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD5_GPIO_FNC__W 2 -#define SIO_PDR_MD6_CFG_DRIVE__B 3 -#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD6_CFG_DRIVE__W 3 -#define SIO_PDR_MD6_CFG_KEEP__B 6 -#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD6_CFG_KEEP__W 2 -#define SIO_PDR_MD6_CFG_MODE__B 0 -#define SIO_PDR_MD6_CFG_MODE__M 0x7 -#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD6_CFG_MODE__W 3 -#define SIO_PDR_MD6_CFG_UIO__B 8 -#define SIO_PDR_MD6_CFG_UIO__M 0x100 -#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD6_CFG_UIO__W 1 -#define SIO_PDR_MD6_CFG__A 0x7F0031 -#define SIO_PDR_MD6_CFG__M 0x1FF -#define SIO_PDR_MD6_CFG__PRE 0x50 -#define SIO_PDR_MD6_CFG__W 9 -#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C -#define SIO_PDR_MD6_GPIO_FNC__M 0x3 -#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD6_GPIO_FNC__W 2 -#define SIO_PDR_MD7_CFG_DRIVE__B 3 -#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 -#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 -#define SIO_PDR_MD7_CFG_DRIVE__W 3 -#define SIO_PDR_MD7_CFG_KEEP__B 6 -#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 -#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 -#define SIO_PDR_MD7_CFG_KEEP__W 2 -#define SIO_PDR_MD7_CFG_MODE__B 0 -#define SIO_PDR_MD7_CFG_MODE__M 0x7 -#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 -#define SIO_PDR_MD7_CFG_MODE__W 3 -#define SIO_PDR_MD7_CFG_UIO__B 8 -#define SIO_PDR_MD7_CFG_UIO__M 0x100 -#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 -#define SIO_PDR_MD7_CFG_UIO__W 1 -#define SIO_PDR_MD7_CFG__A 0x7F0032 -#define SIO_PDR_MD7_CFG__M 0x1FF -#define SIO_PDR_MD7_CFG__PRE 0x50 -#define SIO_PDR_MD7_CFG__W 9 -#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 -#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 -#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D -#define SIO_PDR_MD7_GPIO_FNC__M 0x3 -#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 -#define SIO_PDR_MD7_GPIO_FNC__W 2 -#define SIO_PDR_MERR_CFG__A 0x7F0026 -#define SIO_PDR_MON_CFG__A 0x7F0010 -#define SIO_PDR_MSTRT_CFG__A 0x7F0025 -#define SIO_PDR_MVAL_CFG__A 0x7F0029 -#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 -#define SIO_PDR_OHW_CFG__A 0x7F001F -#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 -#define SIO_PDR_UIO_IN_HI__A 0x7F0015 -#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 -#define SIO_TOP_COMM_KEY_KEY 0xFABA -#define SIO_TOP_COMM_KEY_KEY 0xFABA -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_COMM_KEY__A 0x41000F -#define SIO_TOP_JTAGID_LO__A 0x410012 -#define SIO_TOP_JTAGID_LO__A 0x410012 diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbh24.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbh24.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbh24.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbh24.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,55 +0,0 @@ -/* - * lnbh24.h - driver for lnb supply and control ic lnbh24 - * - * Copyright (C) 2009 NetUP Inc. - * Copyright (C) 2009 Igor M. Liplianin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _LNBH24_H -#define _LNBH24_H - -/* system register bits */ -#define LNBH24_OLF 0x01 -#define LNBH24_OTF 0x02 -#define LNBH24_EN 0x04 -#define LNBH24_VSEL 0x08 -#define LNBH24_LLC 0x10 -#define LNBH24_TEN 0x20 -#define LNBH24_TTX 0x40 -#define LNBH24_PCL 0x80 - -#include - -#if defined(CONFIG_DVB_LNBP21) || (defined(CONFIG_DVB_LNBP21_MODULE) \ - && defined(MODULE)) -/* override_set and override_clear control which - system register bits (above) to always set & clear */ -extern struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 override_set, - u8 override_clear, u8 i2c_addr); -#else -static inline struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 override_set, - u8 override_clear, u8 i2c_addr) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,188 +0,0 @@ -/* - * lnbp21.c - driver for lnb supply and control ic lnbp21 - * - * Copyright (C) 2006, 2009 Oliver Endriss - * Copyright (C) 2009 Igor M. Liplianin - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - * - * - * the project's page is at http://www.linuxtv.org - */ -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "lnbp21.h" -#include "lnbh24.h" - -struct lnbp21 { - u8 config; - u8 override_or; - u8 override_and; - struct i2c_adapter *i2c; - u8 i2c_addr; -}; - -static int lnbp21_set_voltage(struct dvb_frontend *fe, - fe_sec_voltage_t voltage) -{ - struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv; - struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0, - .buf = &lnbp21->config, - .len = sizeof(lnbp21->config) }; - - lnbp21->config &= ~(LNBP21_VSEL | LNBP21_EN); - - switch(voltage) { - case SEC_VOLTAGE_OFF: - break; - case SEC_VOLTAGE_13: - lnbp21->config |= LNBP21_EN; - break; - case SEC_VOLTAGE_18: - lnbp21->config |= (LNBP21_EN | LNBP21_VSEL); - break; - default: - return -EINVAL; - }; - - lnbp21->config |= lnbp21->override_or; - lnbp21->config &= lnbp21->override_and; - - return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO; -} - -static int lnbp21_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg) -{ - struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv; - struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0, - .buf = &lnbp21->config, - .len = sizeof(lnbp21->config) }; - - if (arg) - lnbp21->config |= LNBP21_LLC; - else - lnbp21->config &= ~LNBP21_LLC; - - lnbp21->config |= lnbp21->override_or; - lnbp21->config &= lnbp21->override_and; - - return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO; -} - -static int lnbp21_set_tone(struct dvb_frontend *fe, - fe_sec_tone_mode_t tone) -{ - struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv; - struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0, - .buf = &lnbp21->config, - .len = sizeof(lnbp21->config) }; - - switch (tone) { - case SEC_TONE_OFF: - lnbp21->config &= ~LNBP21_TEN; - break; - case SEC_TONE_ON: - lnbp21->config |= LNBP21_TEN; - break; - default: - return -EINVAL; - }; - - lnbp21->config |= lnbp21->override_or; - lnbp21->config &= lnbp21->override_and; - - return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO; -} - -static void lnbp21_release(struct dvb_frontend *fe) -{ - /* LNBP power off */ - lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF); - - /* free data */ - kfree(fe->sec_priv); - fe->sec_priv = NULL; -} - -static struct dvb_frontend *lnbx2x_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 override_set, - u8 override_clear, u8 i2c_addr, u8 config) -{ - struct lnbp21 *lnbp21 = kmalloc(sizeof(struct lnbp21), GFP_KERNEL); - if (!lnbp21) - return NULL; - - /* default configuration */ - lnbp21->config = config; - lnbp21->i2c = i2c; - lnbp21->i2c_addr = i2c_addr; - fe->sec_priv = lnbp21; - - /* bits which should be forced to '1' */ - lnbp21->override_or = override_set; - - /* bits which should be forced to '0' */ - lnbp21->override_and = ~override_clear; - - /* detect if it is present or not */ - if (lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF)) { - kfree(lnbp21); - return NULL; - } - - /* install release callback */ - fe->ops.release_sec = lnbp21_release; - - /* override frontend ops */ - fe->ops.set_voltage = lnbp21_set_voltage; - fe->ops.enable_high_lnb_voltage = lnbp21_enable_high_lnb_voltage; - if (!(override_clear & LNBH24_TEN)) /*22kHz logic controlled by demod*/ - fe->ops.set_tone = lnbp21_set_tone; - printk(KERN_INFO "LNBx2x attached on addr=%x\n", lnbp21->i2c_addr); - - return fe; -} - -struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 override_set, - u8 override_clear, u8 i2c_addr) -{ - return lnbx2x_attach(fe, i2c, override_set, override_clear, - i2c_addr, LNBH24_TTX); -} -EXPORT_SYMBOL(lnbh24_attach); - -struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 override_set, - u8 override_clear) -{ - return lnbx2x_attach(fe, i2c, override_set, override_clear, - 0x08, LNBP21_ISEL); -} -EXPORT_SYMBOL(lnbp21_attach); - -MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp21, lnbh24"); -MODULE_AUTHOR("Oliver Endriss, Igor M. Liplianin"); -MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/lnbp21.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,75 +0,0 @@ -/* - * lnbp21.h - driver for lnb supply and control ic lnbp21 - * - * Copyright (C) 2006 Oliver Endriss - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - * - * - * the project's page is at http://www.linuxtv.org - */ - -#ifndef _LNBP21_H -#define _LNBP21_H - -/* system register bits */ -/* [RO] 0=OK; 1=over current limit flag */ -#define LNBP21_OLF 0x01 -/* [RO] 0=OK; 1=over temperature flag (150 C) */ -#define LNBP21_OTF 0x02 -/* [RW] 0=disable LNB power, enable loopthrough - 1=enable LNB power, disable loopthrough */ -#define LNBP21_EN 0x04 -/* [RW] 0=low voltage (13/14V, vert pol) - 1=high voltage (18/19V,horiz pol) */ -#define LNBP21_VSEL 0x08 -/* [RW] increase LNB voltage by 1V: - 0=13/18V; 1=14/19V */ -#define LNBP21_LLC 0x10 -/* [RW] 0=tone controlled by DSQIN pin - 1=tone enable, disable DSQIN */ -#define LNBP21_TEN 0x20 -/* [RW] current limit select: - 0:Iout=500-650mA Isc=300mA - 1:Iout=400-550mA Isc=200mA */ -#define LNBP21_ISEL 0x40 -/* [RW] short-circuit protect: - 0=pulsed (dynamic) curr limiting - 1=static curr limiting */ -#define LNBP21_PCL 0x80 - -#include - -#if defined(CONFIG_DVB_LNBP21) || (defined(CONFIG_DVB_LNBP21_MODULE) \ - && defined(MODULE)) -/* override_set and override_clear control which - system register bits (above) to always set & clear */ -extern struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 override_set, - u8 override_clear); -#else -static inline struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 override_set, - u8 override_clear) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,3472 +0,0 @@ -/* - * stv0367.c - * - * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. - * - * Copyright (C) ST Microelectronics. - * Copyright (C) 2010,2011 NetUP Inc. - * Copyright (C) 2010,2011 Igor M. Liplianin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include - -#include "stv0367.h" -#include "stv0367_regs.h" -#include "stv0367_priv.h" - -static int stvdebug; -module_param_named(debug, stvdebug, int, 0644); - -static int i2cdebug; -module_param_named(i2c_debug, i2cdebug, int, 0644); - -#define dprintk(args...) \ - do { \ - if (stvdebug) \ - printk(KERN_DEBUG args); \ - } while (0) - /* DVB-C */ - -struct stv0367cab_state { - enum stv0367_cab_signal_type state; - u32 mclk; - u32 adc_clk; - s32 search_range; - s32 derot_offset; - /* results */ - int locked; /* channel found */ - u32 freq_khz; /* found frequency (in kHz) */ - u32 symbol_rate; /* found symbol rate (in Bds) */ - enum stv0367cab_mod modulation; /* modulation */ - fe_spectral_inversion_t spect_inv; /* Spectrum Inversion */ -}; - -struct stv0367ter_state { - /* DVB-T */ - enum stv0367_ter_signal_type state; - enum stv0367_ter_if_iq_mode if_iq_mode; - enum stv0367_ter_mode mode;/* mode 2K or 8K */ - fe_guard_interval_t guard; - enum stv0367_ter_hierarchy hierarchy; - u32 frequency; - fe_spectral_inversion_t sense; /* current search spectrum */ - u8 force; /* force mode/guard */ - u8 bw; /* channel width 6, 7 or 8 in MHz */ - u8 pBW; /* channel width used during previous lock */ - u32 pBER; - u32 pPER; - u32 ucblocks; - s8 echo_pos; /* echo position */ - u8 first_lock; - u8 unlock_counter; - u32 agc_val; -}; - -struct stv0367_state { - struct dvb_frontend fe; - struct i2c_adapter *i2c; - /* config settings */ - const struct stv0367_config *config; - u8 chip_id; - /* DVB-C */ - struct stv0367cab_state *cab_state; - /* DVB-T */ - struct stv0367ter_state *ter_state; - s32 IF; -}; - -struct st_register { - u16 addr; - u8 value; -}; - -/* values for STV4100 XTAL=30M int clk=53.125M*/ -static struct st_register def0367ter[STV0367TER_NBREGS] = { - {R367TER_ID, 0x60}, - {R367TER_I2CRPT, 0x38}, - /* {R367TER_I2CRPT, 0x22},*/ - {R367TER_TOPCTRL, 0x00},/* for xc5000; was 0x02 */ - {R367TER_IOCFG0, 0x40}, - {R367TER_DAC0R, 0x00}, - {R367TER_IOCFG1, 0x00}, - {R367TER_DAC1R, 0x00}, - {R367TER_IOCFG2, 0x62}, - {R367TER_SDFR, 0x00}, - {R367TER_STATUS, 0xf8}, - {R367TER_AUX_CLK, 0x0a}, - {R367TER_FREESYS1, 0x00}, - {R367TER_FREESYS2, 0x00}, - {R367TER_FREESYS3, 0x00}, - {R367TER_GPIO_CFG, 0x55}, - {R367TER_GPIO_CMD, 0x00}, - {R367TER_AGC2MAX, 0xff}, - {R367TER_AGC2MIN, 0x00}, - {R367TER_AGC1MAX, 0xff}, - {R367TER_AGC1MIN, 0x00}, - {R367TER_AGCR, 0xbc}, - {R367TER_AGC2TH, 0x00}, - {R367TER_AGC12C, 0x00}, - {R367TER_AGCCTRL1, 0x85}, - {R367TER_AGCCTRL2, 0x1f}, - {R367TER_AGC1VAL1, 0x00}, - {R367TER_AGC1VAL2, 0x00}, - {R367TER_AGC2VAL1, 0x6f}, - {R367TER_AGC2VAL2, 0x05}, - {R367TER_AGC2PGA, 0x00}, - {R367TER_OVF_RATE1, 0x00}, - {R367TER_OVF_RATE2, 0x00}, - {R367TER_GAIN_SRC1, 0xaa},/* for xc5000; was 0x2b */ - {R367TER_GAIN_SRC2, 0xd6},/* for xc5000; was 0x04 */ - {R367TER_INC_DEROT1, 0x55}, - {R367TER_INC_DEROT2, 0x55}, - {R367TER_PPM_CPAMP_DIR, 0x2c}, - {R367TER_PPM_CPAMP_INV, 0x00}, - {R367TER_FREESTFE_1, 0x00}, - {R367TER_FREESTFE_2, 0x1c}, - {R367TER_DCOFFSET, 0x00}, - {R367TER_EN_PROCESS, 0x05}, - {R367TER_SDI_SMOOTHER, 0x80}, - {R367TER_FE_LOOP_OPEN, 0x1c}, - {R367TER_FREQOFF1, 0x00}, - {R367TER_FREQOFF2, 0x00}, - {R367TER_FREQOFF3, 0x00}, - {R367TER_TIMOFF1, 0x00}, - {R367TER_TIMOFF2, 0x00}, - {R367TER_EPQ, 0x02}, - {R367TER_EPQAUTO, 0x01}, - {R367TER_SYR_UPDATE, 0xf5}, - {R367TER_CHPFREE, 0x00}, - {R367TER_PPM_STATE_MAC, 0x23}, - {R367TER_INR_THRESHOLD, 0xff}, - {R367TER_EPQ_TPS_ID_CELL, 0xf9}, - {R367TER_EPQ_CFG, 0x00}, - {R367TER_EPQ_STATUS, 0x01}, - {R367TER_AUTORELOCK, 0x81}, - {R367TER_BER_THR_VMSB, 0x00}, - {R367TER_BER_THR_MSB, 0x00}, - {R367TER_BER_THR_LSB, 0x00}, - {R367TER_CCD, 0x83}, - {R367TER_SPECTR_CFG, 0x00}, - {R367TER_CHC_DUMMY, 0x18}, - {R367TER_INC_CTL, 0x88}, - {R367TER_INCTHRES_COR1, 0xb4}, - {R367TER_INCTHRES_COR2, 0x96}, - {R367TER_INCTHRES_DET1, 0x0e}, - {R367TER_INCTHRES_DET2, 0x11}, - {R367TER_IIR_CELLNB, 0x8d}, - {R367TER_IIRCX_COEFF1_MSB, 0x00}, - {R367TER_IIRCX_COEFF1_LSB, 0x00}, - {R367TER_IIRCX_COEFF2_MSB, 0x09}, - {R367TER_IIRCX_COEFF2_LSB, 0x18}, - {R367TER_IIRCX_COEFF3_MSB, 0x14}, - {R367TER_IIRCX_COEFF3_LSB, 0x9c}, - {R367TER_IIRCX_COEFF4_MSB, 0x00}, - {R367TER_IIRCX_COEFF4_LSB, 0x00}, - {R367TER_IIRCX_COEFF5_MSB, 0x36}, - {R367TER_IIRCX_COEFF5_LSB, 0x42}, - {R367TER_FEPATH_CFG, 0x00}, - {R367TER_PMC1_FUNC, 0x65}, - {R367TER_PMC1_FOR, 0x00}, - {R367TER_PMC2_FUNC, 0x00}, - {R367TER_STATUS_ERR_DA, 0xe0}, - {R367TER_DIG_AGC_R, 0xfe}, - {R367TER_COMAGC_TARMSB, 0x0b}, - {R367TER_COM_AGC_TAR_ENMODE, 0x41}, - {R367TER_COM_AGC_CFG, 0x3e}, - {R367TER_COM_AGC_GAIN1, 0x39}, - {R367TER_AUT_AGC_TARGETMSB, 0x0b}, - {R367TER_LOCK_DET_MSB, 0x01}, - {R367TER_AGCTAR_LOCK_LSBS, 0x40}, - {R367TER_AUT_GAIN_EN, 0xf4}, - {R367TER_AUT_CFG, 0xf0}, - {R367TER_LOCKN, 0x23}, - {R367TER_INT_X_3, 0x00}, - {R367TER_INT_X_2, 0x03}, - {R367TER_INT_X_1, 0x8d}, - {R367TER_INT_X_0, 0xa0}, - {R367TER_MIN_ERRX_MSB, 0x00}, - {R367TER_COR_CTL, 0x23}, - {R367TER_COR_STAT, 0xf6}, - {R367TER_COR_INTEN, 0x00}, - {R367TER_COR_INTSTAT, 0x3f}, - {R367TER_COR_MODEGUARD, 0x03}, - {R367TER_AGC_CTL, 0x08}, - {R367TER_AGC_MANUAL1, 0x00}, - {R367TER_AGC_MANUAL2, 0x00}, - {R367TER_AGC_TARG, 0x16}, - {R367TER_AGC_GAIN1, 0x53}, - {R367TER_AGC_GAIN2, 0x1d}, - {R367TER_RESERVED_1, 0x00}, - {R367TER_RESERVED_2, 0x00}, - {R367TER_RESERVED_3, 0x00}, - {R367TER_CAS_CTL, 0x44}, - {R367TER_CAS_FREQ, 0xb3}, - {R367TER_CAS_DAGCGAIN, 0x12}, - {R367TER_SYR_CTL, 0x04}, - {R367TER_SYR_STAT, 0x10}, - {R367TER_SYR_NCO1, 0x00}, - {R367TER_SYR_NCO2, 0x00}, - {R367TER_SYR_OFFSET1, 0x00}, - {R367TER_SYR_OFFSET2, 0x00}, - {R367TER_FFT_CTL, 0x00}, - {R367TER_SCR_CTL, 0x70}, - {R367TER_PPM_CTL1, 0xf8}, - {R367TER_TRL_CTL, 0x14},/* for xc5000; was 0xac */ - {R367TER_TRL_NOMRATE1, 0xae},/* for xc5000; was 0x1e */ - {R367TER_TRL_NOMRATE2, 0x56},/* for xc5000; was 0x58 */ - {R367TER_TRL_TIME1, 0x1d}, - {R367TER_TRL_TIME2, 0xfc}, - {R367TER_CRL_CTL, 0x24}, - {R367TER_CRL_FREQ1, 0xad}, - {R367TER_CRL_FREQ2, 0x9d}, - {R367TER_CRL_FREQ3, 0xff}, - {R367TER_CHC_CTL, 0x01}, - {R367TER_CHC_SNR, 0xf0}, - {R367TER_BDI_CTL, 0x00}, - {R367TER_DMP_CTL, 0x00}, - {R367TER_TPS_RCVD1, 0x30}, - {R367TER_TPS_RCVD2, 0x02}, - {R367TER_TPS_RCVD3, 0x01}, - {R367TER_TPS_RCVD4, 0x00}, - {R367TER_TPS_ID_CELL1, 0x00}, - {R367TER_TPS_ID_CELL2, 0x00}, - {R367TER_TPS_RCVD5_SET1, 0x02}, - {R367TER_TPS_SET2, 0x02}, - {R367TER_TPS_SET3, 0x01}, - {R367TER_TPS_CTL, 0x00}, - {R367TER_CTL_FFTOSNUM, 0x34}, - {R367TER_TESTSELECT, 0x09}, - {R367TER_MSC_REV, 0x0a}, - {R367TER_PIR_CTL, 0x00}, - {R367TER_SNR_CARRIER1, 0xa1}, - {R367TER_SNR_CARRIER2, 0x9a}, - {R367TER_PPM_CPAMP, 0x2c}, - {R367TER_TSM_AP0, 0x00}, - {R367TER_TSM_AP1, 0x00}, - {R367TER_TSM_AP2 , 0x00}, - {R367TER_TSM_AP3, 0x00}, - {R367TER_TSM_AP4, 0x00}, - {R367TER_TSM_AP5, 0x00}, - {R367TER_TSM_AP6, 0x00}, - {R367TER_TSM_AP7, 0x00}, - {R367TER_TSTRES, 0x00}, - {R367TER_ANACTRL, 0x0D},/* PLL stoped, restart at init!!! */ - {R367TER_TSTBUS, 0x00}, - {R367TER_TSTRATE, 0x00}, - {R367TER_CONSTMODE, 0x01}, - {R367TER_CONSTCARR1, 0x00}, - {R367TER_CONSTCARR2, 0x00}, - {R367TER_ICONSTEL, 0x0a}, - {R367TER_QCONSTEL, 0x15}, - {R367TER_TSTBISTRES0, 0x00}, - {R367TER_TSTBISTRES1, 0x00}, - {R367TER_TSTBISTRES2, 0x28}, - {R367TER_TSTBISTRES3, 0x00}, - {R367TER_RF_AGC1, 0xff}, - {R367TER_RF_AGC2, 0x83}, - {R367TER_ANADIGCTRL, 0x19}, - {R367TER_PLLMDIV, 0x01},/* for xc5000; was 0x0c */ - {R367TER_PLLNDIV, 0x06},/* for xc5000; was 0x55 */ - {R367TER_PLLSETUP, 0x18}, - {R367TER_DUAL_AD12, 0x0C},/* for xc5000 AGC voltage 1.6V */ - {R367TER_TSTBIST, 0x00}, - {R367TER_PAD_COMP_CTRL, 0x00}, - {R367TER_PAD_COMP_WR, 0x00}, - {R367TER_PAD_COMP_RD, 0xe0}, - {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00}, - {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00}, - {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00}, - {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00}, - {R367TER_SYR_FLAG, 0x00}, - {R367TER_CRL_TARGET1, 0x00}, - {R367TER_CRL_TARGET2, 0x00}, - {R367TER_CRL_TARGET3, 0x00}, - {R367TER_CRL_TARGET4, 0x00}, - {R367TER_CRL_FLAG, 0x00}, - {R367TER_TRL_TARGET1, 0x00}, - {R367TER_TRL_TARGET2, 0x00}, - {R367TER_TRL_CHC, 0x00}, - {R367TER_CHC_SNR_TARG, 0x00}, - {R367TER_TOP_TRACK, 0x00}, - {R367TER_TRACKER_FREE1, 0x00}, - {R367TER_ERROR_CRL1, 0x00}, - {R367TER_ERROR_CRL2, 0x00}, - {R367TER_ERROR_CRL3, 0x00}, - {R367TER_ERROR_CRL4, 0x00}, - {R367TER_DEC_NCO1, 0x2c}, - {R367TER_DEC_NCO2, 0x0f}, - {R367TER_DEC_NCO3, 0x20}, - {R367TER_SNR, 0xf1}, - {R367TER_SYR_FFTADJ1, 0x00}, - {R367TER_SYR_FFTADJ2, 0x00}, - {R367TER_SYR_CHCADJ1, 0x00}, - {R367TER_SYR_CHCADJ2, 0x00}, - {R367TER_SYR_OFF, 0x00}, - {R367TER_PPM_OFFSET1, 0x00}, - {R367TER_PPM_OFFSET2, 0x03}, - {R367TER_TRACKER_FREE2, 0x00}, - {R367TER_DEBG_LT10, 0x00}, - {R367TER_DEBG_LT11, 0x00}, - {R367TER_DEBG_LT12, 0x00}, - {R367TER_DEBG_LT13, 0x00}, - {R367TER_DEBG_LT14, 0x00}, - {R367TER_DEBG_LT15, 0x00}, - {R367TER_DEBG_LT16, 0x00}, - {R367TER_DEBG_LT17, 0x00}, - {R367TER_DEBG_LT18, 0x00}, - {R367TER_DEBG_LT19, 0x00}, - {R367TER_DEBG_LT1A, 0x00}, - {R367TER_DEBG_LT1B, 0x00}, - {R367TER_DEBG_LT1C, 0x00}, - {R367TER_DEBG_LT1D, 0x00}, - {R367TER_DEBG_LT1E, 0x00}, - {R367TER_DEBG_LT1F, 0x00}, - {R367TER_RCCFGH, 0x00}, - {R367TER_RCCFGM, 0x00}, - {R367TER_RCCFGL, 0x00}, - {R367TER_RCINSDELH, 0x00}, - {R367TER_RCINSDELM, 0x00}, - {R367TER_RCINSDELL, 0x00}, - {R367TER_RCSTATUS, 0x00}, - {R367TER_RCSPEED, 0x6f}, - {R367TER_RCDEBUGM, 0xe7}, - {R367TER_RCDEBUGL, 0x9b}, - {R367TER_RCOBSCFG, 0x00}, - {R367TER_RCOBSM, 0x00}, - {R367TER_RCOBSL, 0x00}, - {R367TER_RCFECSPY, 0x00}, - {R367TER_RCFSPYCFG, 0x00}, - {R367TER_RCFSPYDATA, 0x00}, - {R367TER_RCFSPYOUT, 0x00}, - {R367TER_RCFSTATUS, 0x00}, - {R367TER_RCFGOODPACK, 0x00}, - {R367TER_RCFPACKCNT, 0x00}, - {R367TER_RCFSPYMISC, 0x00}, - {R367TER_RCFBERCPT4, 0x00}, - {R367TER_RCFBERCPT3, 0x00}, - {R367TER_RCFBERCPT2, 0x00}, - {R367TER_RCFBERCPT1, 0x00}, - {R367TER_RCFBERCPT0, 0x00}, - {R367TER_RCFBERERR2, 0x00}, - {R367TER_RCFBERERR1, 0x00}, - {R367TER_RCFBERERR0, 0x00}, - {R367TER_RCFSTATESM, 0x00}, - {R367TER_RCFSTATESL, 0x00}, - {R367TER_RCFSPYBER, 0x00}, - {R367TER_RCFSPYDISTM, 0x00}, - {R367TER_RCFSPYDISTL, 0x00}, - {R367TER_RCFSPYOBS7, 0x00}, - {R367TER_RCFSPYOBS6, 0x00}, - {R367TER_RCFSPYOBS5, 0x00}, - {R367TER_RCFSPYOBS4, 0x00}, - {R367TER_RCFSPYOBS3, 0x00}, - {R367TER_RCFSPYOBS2, 0x00}, - {R367TER_RCFSPYOBS1, 0x00}, - {R367TER_RCFSPYOBS0, 0x00}, - {R367TER_TSGENERAL, 0x00}, - {R367TER_RC1SPEED, 0x6f}, - {R367TER_TSGSTATUS, 0x18}, - {R367TER_FECM, 0x01}, - {R367TER_VTH12, 0xff}, - {R367TER_VTH23, 0xa1}, - {R367TER_VTH34, 0x64}, - {R367TER_VTH56, 0x40}, - {R367TER_VTH67, 0x00}, - {R367TER_VTH78, 0x2c}, - {R367TER_VITCURPUN, 0x12}, - {R367TER_VERROR, 0x01}, - {R367TER_PRVIT, 0x3f}, - {R367TER_VAVSRVIT, 0x00}, - {R367TER_VSTATUSVIT, 0xbd}, - {R367TER_VTHINUSE, 0xa1}, - {R367TER_KDIV12, 0x20}, - {R367TER_KDIV23, 0x40}, - {R367TER_KDIV34, 0x20}, - {R367TER_KDIV56, 0x30}, - {R367TER_KDIV67, 0x00}, - {R367TER_KDIV78, 0x30}, - {R367TER_SIGPOWER, 0x54}, - {R367TER_DEMAPVIT, 0x40}, - {R367TER_VITSCALE, 0x00}, - {R367TER_FFEC1PRG, 0x00}, - {R367TER_FVITCURPUN, 0x12}, - {R367TER_FVERROR, 0x01}, - {R367TER_FVSTATUSVIT, 0xbd}, - {R367TER_DEBUG_LT1, 0x00}, - {R367TER_DEBUG_LT2, 0x00}, - {R367TER_DEBUG_LT3, 0x00}, - {R367TER_TSTSFMET, 0x00}, - {R367TER_SELOUT, 0x00}, - {R367TER_TSYNC, 0x00}, - {R367TER_TSTERR, 0x00}, - {R367TER_TSFSYNC, 0x00}, - {R367TER_TSTSFERR, 0x00}, - {R367TER_TSTTSSF1, 0x01}, - {R367TER_TSTTSSF2, 0x1f}, - {R367TER_TSTTSSF3, 0x00}, - {R367TER_TSTTS1, 0x00}, - {R367TER_TSTTS2, 0x1f}, - {R367TER_TSTTS3, 0x01}, - {R367TER_TSTTS4, 0x00}, - {R367TER_TSTTSRC, 0x00}, - {R367TER_TSTTSRS, 0x00}, - {R367TER_TSSTATEM, 0xb0}, {R367TER_TSSTATEL, 0x40}, - {R367TER_TSCFGH, 0x70}, - {R367TER_TSCFGM, 0xc0},/* for xc5000; was 0x00 */ - {R367TER_TSCFGL, 0x20}, - {R367TER_TSSYNC, 0x00}, - {R367TER_TSINSDELH, 0x00}, - {R367TER_TSINSDELM, 0x00}, - {R367TER_TSINSDELL, 0x00}, - {R367TER_TSDIVN, 0x03}, - {R367TER_TSDIVPM, 0x00}, - {R367TER_TSDIVPL, 0x00}, - {R367TER_TSDIVQM, 0x00}, - {R367TER_TSDIVQL, 0x00}, - {R367TER_TSDILSTKM, 0x00}, - {R367TER_TSDILSTKL, 0x00}, - {R367TER_TSSPEED, 0x40},/* for xc5000; was 0x6f */ - {R367TER_TSSTATUS, 0x81}, - {R367TER_TSSTATUS2, 0x6a}, - {R367TER_TSBITRATEM, 0x0f}, - {R367TER_TSBITRATEL, 0xc6}, - {R367TER_TSPACKLENM, 0x00}, - {R367TER_TSPACKLENL, 0xfc}, - {R367TER_TSBLOCLENM, 0x0a}, - {R367TER_TSBLOCLENL, 0x80}, - {R367TER_TSDLYH, 0x90}, - {R367TER_TSDLYM, 0x68}, - {R367TER_TSDLYL, 0x01}, - {R367TER_TSNPDAV, 0x00}, - {R367TER_TSBUFSTATH, 0x00}, - {R367TER_TSBUFSTATM, 0x00}, - {R367TER_TSBUFSTATL, 0x00}, - {R367TER_TSDEBUGM, 0xcf}, - {R367TER_TSDEBUGL, 0x1e}, - {R367TER_TSDLYSETH, 0x00}, - {R367TER_TSDLYSETM, 0x68}, - {R367TER_TSDLYSETL, 0x00}, - {R367TER_TSOBSCFG, 0x00}, - {R367TER_TSOBSM, 0x47}, - {R367TER_TSOBSL, 0x1f}, - {R367TER_ERRCTRL1, 0x95}, - {R367TER_ERRCNT1H, 0x80}, - {R367TER_ERRCNT1M, 0x00}, - {R367TER_ERRCNT1L, 0x00}, - {R367TER_ERRCTRL2, 0x95}, - {R367TER_ERRCNT2H, 0x00}, - {R367TER_ERRCNT2M, 0x00}, - {R367TER_ERRCNT2L, 0x00}, - {R367TER_FECSPY, 0x88}, - {R367TER_FSPYCFG, 0x2c}, - {R367TER_FSPYDATA, 0x3a}, - {R367TER_FSPYOUT, 0x06}, - {R367TER_FSTATUS, 0x61}, - {R367TER_FGOODPACK, 0xff}, - {R367TER_FPACKCNT, 0xff}, - {R367TER_FSPYMISC, 0x66}, - {R367TER_FBERCPT4, 0x00}, - {R367TER_FBERCPT3, 0x00}, - {R367TER_FBERCPT2, 0x36}, - {R367TER_FBERCPT1, 0x36}, - {R367TER_FBERCPT0, 0x14}, - {R367TER_FBERERR2, 0x00}, - {R367TER_FBERERR1, 0x03}, - {R367TER_FBERERR0, 0x28}, - {R367TER_FSTATESM, 0x00}, - {R367TER_FSTATESL, 0x02}, - {R367TER_FSPYBER, 0x00}, - {R367TER_FSPYDISTM, 0x01}, - {R367TER_FSPYDISTL, 0x9f}, - {R367TER_FSPYOBS7, 0xc9}, - {R367TER_FSPYOBS6, 0x99}, - {R367TER_FSPYOBS5, 0x08}, - {R367TER_FSPYOBS4, 0xec}, - {R367TER_FSPYOBS3, 0x01}, - {R367TER_FSPYOBS2, 0x0f}, - {R367TER_FSPYOBS1, 0xf5}, - {R367TER_FSPYOBS0, 0x08}, - {R367TER_SFDEMAP, 0x40}, - {R367TER_SFERROR, 0x00}, - {R367TER_SFAVSR, 0x30}, - {R367TER_SFECSTATUS, 0xcc}, - {R367TER_SFKDIV12, 0x20}, - {R367TER_SFKDIV23, 0x40}, - {R367TER_SFKDIV34, 0x20}, - {R367TER_SFKDIV56, 0x20}, - {R367TER_SFKDIV67, 0x00}, - {R367TER_SFKDIV78, 0x20}, - {R367TER_SFDILSTKM, 0x00}, - {R367TER_SFDILSTKL, 0x00}, - {R367TER_SFSTATUS, 0xb5}, - {R367TER_SFDLYH, 0x90}, - {R367TER_SFDLYM, 0x60}, - {R367TER_SFDLYL, 0x01}, - {R367TER_SFDLYSETH, 0xc0}, - {R367TER_SFDLYSETM, 0x60}, - {R367TER_SFDLYSETL, 0x00}, - {R367TER_SFOBSCFG, 0x00}, - {R367TER_SFOBSM, 0x47}, - {R367TER_SFOBSL, 0x05}, - {R367TER_SFECINFO, 0x40}, - {R367TER_SFERRCTRL, 0x74}, - {R367TER_SFERRCNTH, 0x80}, - {R367TER_SFERRCNTM , 0x00}, - {R367TER_SFERRCNTL, 0x00}, - {R367TER_SYMBRATEM, 0x2f}, - {R367TER_SYMBRATEL, 0x50}, - {R367TER_SYMBSTATUS, 0x7f}, - {R367TER_SYMBCFG, 0x00}, - {R367TER_SYMBFIFOM, 0xf4}, - {R367TER_SYMBFIFOL, 0x0d}, - {R367TER_SYMBOFFSM, 0xf0}, - {R367TER_SYMBOFFSL, 0x2d}, - {R367TER_DEBUG_LT4, 0x00}, - {R367TER_DEBUG_LT5, 0x00}, - {R367TER_DEBUG_LT6, 0x00}, - {R367TER_DEBUG_LT7, 0x00}, - {R367TER_DEBUG_LT8, 0x00}, - {R367TER_DEBUG_LT9, 0x00}, -}; - -#define RF_LOOKUP_TABLE_SIZE 31 -#define RF_LOOKUP_TABLE2_SIZE 16 -/* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/ -s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = { - {/*AGC1*/ - 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, - 76, 77, 78, 80, 83, 85, 88, - }, {/*RF(dbm)*/ - 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, - 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47, - 49, 50, 52, 53, 54, 55, 56, - } -}; -/* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/ -s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = { - {/*AGC2*/ - 28, 29, 31, 32, 34, 35, 36, 37, - 38, 39, 40, 41, 42, 43, 44, 45, - }, {/*RF(dbm)*/ - 57, 58, 59, 60, 61, 62, 63, 64, - 65, 66, 67, 68, 69, 70, 71, 72, - } -}; - -static struct st_register def0367cab[STV0367CAB_NBREGS] = { - {R367CAB_ID, 0x60}, - {R367CAB_I2CRPT, 0x38}, - /*{R367CAB_I2CRPT, 0x22},*/ - {R367CAB_TOPCTRL, 0x10}, - {R367CAB_IOCFG0, 0x80}, - {R367CAB_DAC0R, 0x00}, - {R367CAB_IOCFG1, 0x00}, - {R367CAB_DAC1R, 0x00}, - {R367CAB_IOCFG2, 0x00}, - {R367CAB_SDFR, 0x00}, - {R367CAB_AUX_CLK, 0x00}, - {R367CAB_FREESYS1, 0x00}, - {R367CAB_FREESYS2, 0x00}, - {R367CAB_FREESYS3, 0x00}, - {R367CAB_GPIO_CFG, 0x55}, - {R367CAB_GPIO_CMD, 0x01}, - {R367CAB_TSTRES, 0x00}, - {R367CAB_ANACTRL, 0x0d},/* was 0x00 need to check - I.M.L.*/ - {R367CAB_TSTBUS, 0x00}, - {R367CAB_RF_AGC1, 0xea}, - {R367CAB_RF_AGC2, 0x82}, - {R367CAB_ANADIGCTRL, 0x0b}, - {R367CAB_PLLMDIV, 0x01}, - {R367CAB_PLLNDIV, 0x08}, - {R367CAB_PLLSETUP, 0x18}, - {R367CAB_DUAL_AD12, 0x0C}, /* for xc5000 AGC voltage 1.6V */ - {R367CAB_TSTBIST, 0x00}, - {R367CAB_CTRL_1, 0x00}, - {R367CAB_CTRL_2, 0x03}, - {R367CAB_IT_STATUS1, 0x2b}, - {R367CAB_IT_STATUS2, 0x08}, - {R367CAB_IT_EN1, 0x00}, - {R367CAB_IT_EN2, 0x00}, - {R367CAB_CTRL_STATUS, 0x04}, - {R367CAB_TEST_CTL, 0x00}, - {R367CAB_AGC_CTL, 0x73}, - {R367CAB_AGC_IF_CFG, 0x50}, - {R367CAB_AGC_RF_CFG, 0x00}, - {R367CAB_AGC_PWM_CFG, 0x03}, - {R367CAB_AGC_PWR_REF_L, 0x5a}, - {R367CAB_AGC_PWR_REF_H, 0x00}, - {R367CAB_AGC_RF_TH_L, 0xff}, - {R367CAB_AGC_RF_TH_H, 0x07}, - {R367CAB_AGC_IF_LTH_L, 0x00}, - {R367CAB_AGC_IF_LTH_H, 0x08}, - {R367CAB_AGC_IF_HTH_L, 0xff}, - {R367CAB_AGC_IF_HTH_H, 0x07}, - {R367CAB_AGC_PWR_RD_L, 0xa0}, - {R367CAB_AGC_PWR_RD_M, 0xe9}, - {R367CAB_AGC_PWR_RD_H, 0x03}, - {R367CAB_AGC_PWM_IFCMD_L, 0xe4}, - {R367CAB_AGC_PWM_IFCMD_H, 0x00}, - {R367CAB_AGC_PWM_RFCMD_L, 0xff}, - {R367CAB_AGC_PWM_RFCMD_H, 0x07}, - {R367CAB_IQDEM_CFG, 0x01}, - {R367CAB_MIX_NCO_LL, 0x22}, - {R367CAB_MIX_NCO_HL, 0x96}, - {R367CAB_MIX_NCO_HH, 0x55}, - {R367CAB_SRC_NCO_LL, 0xff}, - {R367CAB_SRC_NCO_LH, 0x0c}, - {R367CAB_SRC_NCO_HL, 0xf5}, - {R367CAB_SRC_NCO_HH, 0x20}, - {R367CAB_IQDEM_GAIN_SRC_L, 0x06}, - {R367CAB_IQDEM_GAIN_SRC_H, 0x01}, - {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe}, - {R367CAB_IQDEM_DCRM_CFG_LH, 0xff}, - {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f}, - {R367CAB_IQDEM_DCRM_CFG_HH, 0x00}, - {R367CAB_IQDEM_ADJ_COEFF0, 0x34}, - {R367CAB_IQDEM_ADJ_COEFF1, 0xae}, - {R367CAB_IQDEM_ADJ_COEFF2, 0x46}, - {R367CAB_IQDEM_ADJ_COEFF3, 0x77}, - {R367CAB_IQDEM_ADJ_COEFF4, 0x96}, - {R367CAB_IQDEM_ADJ_COEFF5, 0x69}, - {R367CAB_IQDEM_ADJ_COEFF6, 0xc7}, - {R367CAB_IQDEM_ADJ_COEFF7, 0x01}, - {R367CAB_IQDEM_ADJ_EN, 0x04}, - {R367CAB_IQDEM_ADJ_AGC_REF, 0x94}, - {R367CAB_ALLPASSFILT1, 0xc9}, - {R367CAB_ALLPASSFILT2, 0x2d}, - {R367CAB_ALLPASSFILT3, 0xa3}, - {R367CAB_ALLPASSFILT4, 0xfb}, - {R367CAB_ALLPASSFILT5, 0xf6}, - {R367CAB_ALLPASSFILT6, 0x45}, - {R367CAB_ALLPASSFILT7, 0x6f}, - {R367CAB_ALLPASSFILT8, 0x7e}, - {R367CAB_ALLPASSFILT9, 0x05}, - {R367CAB_ALLPASSFILT10, 0x0a}, - {R367CAB_ALLPASSFILT11, 0x51}, - {R367CAB_TRL_AGC_CFG, 0x20}, - {R367CAB_TRL_LPF_CFG, 0x28}, - {R367CAB_TRL_LPF_ACQ_GAIN, 0x44}, - {R367CAB_TRL_LPF_TRK_GAIN, 0x22}, - {R367CAB_TRL_LPF_OUT_GAIN, 0x03}, - {R367CAB_TRL_LOCKDET_LTH, 0x04}, - {R367CAB_TRL_LOCKDET_HTH, 0x11}, - {R367CAB_TRL_LOCKDET_TRGVAL, 0x20}, - {R367CAB_IQ_QAM, 0x01}, - {R367CAB_FSM_STATE, 0xa0}, - {R367CAB_FSM_CTL, 0x08}, - {R367CAB_FSM_STS, 0x0c}, - {R367CAB_FSM_SNR0_HTH, 0x00}, - {R367CAB_FSM_SNR1_HTH, 0x00}, - {R367CAB_FSM_SNR2_HTH, 0x23},/* 0x00 */ - {R367CAB_FSM_SNR0_LTH, 0x00}, - {R367CAB_FSM_SNR1_LTH, 0x00}, - {R367CAB_FSM_EQA1_HTH, 0x00}, - {R367CAB_FSM_TEMPO, 0x32}, - {R367CAB_FSM_CONFIG, 0x03}, - {R367CAB_EQU_I_TESTTAP_L, 0x11}, - {R367CAB_EQU_I_TESTTAP_M, 0x00}, - {R367CAB_EQU_I_TESTTAP_H, 0x00}, - {R367CAB_EQU_TESTAP_CFG, 0x00}, - {R367CAB_EQU_Q_TESTTAP_L, 0xff}, - {R367CAB_EQU_Q_TESTTAP_M, 0x00}, - {R367CAB_EQU_Q_TESTTAP_H, 0x00}, - {R367CAB_EQU_TAP_CTRL, 0x00}, - {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11}, - {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05}, - {R367CAB_EQU_CTR_HIPOW_L, 0x00}, - {R367CAB_EQU_CTR_HIPOW_H, 0x00}, - {R367CAB_EQU_I_EQU_LO, 0xef}, - {R367CAB_EQU_I_EQU_HI, 0x00}, - {R367CAB_EQU_Q_EQU_LO, 0xee}, - {R367CAB_EQU_Q_EQU_HI, 0x00}, - {R367CAB_EQU_MAPPER, 0xc5}, - {R367CAB_EQU_SWEEP_RATE, 0x80}, - {R367CAB_EQU_SNR_LO, 0x64}, - {R367CAB_EQU_SNR_HI, 0x03}, - {R367CAB_EQU_GAMMA_LO, 0x00}, - {R367CAB_EQU_GAMMA_HI, 0x00}, - {R367CAB_EQU_ERR_GAIN, 0x36}, - {R367CAB_EQU_RADIUS, 0xaa}, - {R367CAB_EQU_FFE_MAINTAP, 0x00}, - {R367CAB_EQU_FFE_LEAKAGE, 0x63}, - {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf}, - {R367CAB_EQU_GAIN_WIDE, 0x88}, - {R367CAB_EQU_GAIN_NARROW, 0x41}, - {R367CAB_EQU_CTR_LPF_GAIN, 0xd1}, - {R367CAB_EQU_CRL_LPF_GAIN, 0xa7}, - {R367CAB_EQU_GLOBAL_GAIN, 0x06}, - {R367CAB_EQU_CRL_LD_SEN, 0x85}, - {R367CAB_EQU_CRL_LD_VAL, 0xe2}, - {R367CAB_EQU_CRL_TFR, 0x20}, - {R367CAB_EQU_CRL_BISTH_LO, 0x00}, - {R367CAB_EQU_CRL_BISTH_HI, 0x00}, - {R367CAB_EQU_SWEEP_RANGE_LO, 0x00}, - {R367CAB_EQU_SWEEP_RANGE_HI, 0x00}, - {R367CAB_EQU_CRL_LIMITER, 0x40}, - {R367CAB_EQU_MODULUS_MAP, 0x90}, - {R367CAB_EQU_PNT_GAIN, 0xa7}, - {R367CAB_FEC_AC_CTR_0, 0x16}, - {R367CAB_FEC_AC_CTR_1, 0x0b}, - {R367CAB_FEC_AC_CTR_2, 0x88}, - {R367CAB_FEC_AC_CTR_3, 0x02}, - {R367CAB_FEC_STATUS, 0x12}, - {R367CAB_RS_COUNTER_0, 0x7d}, - {R367CAB_RS_COUNTER_1, 0xd0}, - {R367CAB_RS_COUNTER_2, 0x19}, - {R367CAB_RS_COUNTER_3, 0x0b}, - {R367CAB_RS_COUNTER_4, 0xa3}, - {R367CAB_RS_COUNTER_5, 0x00}, - {R367CAB_BERT_0, 0x01}, - {R367CAB_BERT_1, 0x25}, - {R367CAB_BERT_2, 0x41}, - {R367CAB_BERT_3, 0x39}, - {R367CAB_OUTFORMAT_0, 0xc2}, - {R367CAB_OUTFORMAT_1, 0x22}, - {R367CAB_SMOOTHER_2, 0x28}, - {R367CAB_TSMF_CTRL_0, 0x01}, - {R367CAB_TSMF_CTRL_1, 0xc6}, - {R367CAB_TSMF_CTRL_3, 0x43}, - {R367CAB_TS_ON_ID_0, 0x00}, - {R367CAB_TS_ON_ID_1, 0x00}, - {R367CAB_TS_ON_ID_2, 0x00}, - {R367CAB_TS_ON_ID_3, 0x00}, - {R367CAB_RE_STATUS_0, 0x00}, - {R367CAB_RE_STATUS_1, 0x00}, - {R367CAB_RE_STATUS_2, 0x00}, - {R367CAB_RE_STATUS_3, 0x00}, - {R367CAB_TS_STATUS_0, 0x00}, - {R367CAB_TS_STATUS_1, 0x00}, - {R367CAB_TS_STATUS_2, 0xa0}, - {R367CAB_TS_STATUS_3, 0x00}, - {R367CAB_T_O_ID_0, 0x00}, - {R367CAB_T_O_ID_1, 0x00}, - {R367CAB_T_O_ID_2, 0x00}, - {R367CAB_T_O_ID_3, 0x00}, -}; - -static -int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len) -{ - u8 buf[len + 2]; - struct i2c_msg msg = { - .addr = state->config->demod_address, - .flags = 0, - .buf = buf, - .len = len + 2 - }; - int ret; - - buf[0] = MSB(reg); - buf[1] = LSB(reg); - memcpy(buf + 2, data, len); - - if (i2cdebug) - printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]); - - ret = i2c_transfer(state->i2c, &msg, 1); - if (ret != 1) - printk(KERN_ERR "%s: i2c write error!\n", __func__); - - return (ret != 1) ? -EREMOTEIO : 0; -} - -static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) -{ - return stv0367_writeregs(state, reg, &data, 1); -} - -static u8 stv0367_readreg(struct stv0367_state *state, u16 reg) -{ - u8 b0[] = { 0, 0 }; - u8 b1[] = { 0 }; - struct i2c_msg msg[] = { - { - .addr = state->config->demod_address, - .flags = 0, - .buf = b0, - .len = 2 - }, { - .addr = state->config->demod_address, - .flags = I2C_M_RD, - .buf = b1, - .len = 1 - } - }; - int ret; - - b0[0] = MSB(reg); - b0[1] = LSB(reg); - - ret = i2c_transfer(state->i2c, msg, 2); - if (ret != 2) - printk(KERN_ERR "%s: i2c read error\n", __func__); - - if (i2cdebug) - printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]); - - return b1[0]; -} - -static void extract_mask_pos(u32 label, u8 *mask, u8 *pos) -{ - u8 position = 0, i = 0; - - (*mask) = label & 0xff; - - while ((position == 0) && (i < 8)) { - position = ((*mask) >> i) & 0x01; - i++; - } - - (*pos) = (i - 1); -} - -static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val) -{ - u8 reg, mask, pos; - - reg = stv0367_readreg(state, (label >> 16) & 0xffff); - extract_mask_pos(label, &mask, &pos); - - val = mask & (val << pos); - - reg = (reg & (~mask)) | val; - stv0367_writereg(state, (label >> 16) & 0xffff, reg); - -} - -static void stv0367_setbits(u8 *reg, u32 label, u8 val) -{ - u8 mask, pos; - - extract_mask_pos(label, &mask, &pos); - - val = mask & (val << pos); - - (*reg) = ((*reg) & (~mask)) | val; -} - -static u8 stv0367_readbits(struct stv0367_state *state, u32 label) -{ - u8 val = 0xff; - u8 mask, pos; - - extract_mask_pos(label, &mask, &pos); - - val = stv0367_readreg(state, label >> 16); - val = (val & mask) >> pos; - - return val; -} - -u8 stv0367_getbits(u8 reg, u32 label) -{ - u8 mask, pos; - - extract_mask_pos(label, &mask, &pos); - - return (reg & mask) >> pos; -} - -static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable) -{ - struct stv0367_state *state = fe->demodulator_priv; - u8 tmp = stv0367_readreg(state, R367TER_I2CRPT); - - dprintk("%s:\n", __func__); - printk("%s: %d %02x\n", __func__, enable, tmp); - - tmp=0x58; - if (enable) { - stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0); - stv0367_setbits(&tmp, F367TER_I2CT_ON, 1); - } else { - //stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1); - stv0367_setbits(&tmp, F367TER_I2CT_ON, 0); - } - - stv0367_writereg(state, R367TER_I2CRPT, tmp); - - printk("%s: %02x\n", __func__, tmp); - - return 0; -} - -static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe) -{ - struct dvb_frontend_ops *frontend_ops = NULL; - struct dvb_tuner_ops *tuner_ops = NULL; - u32 freq = 0; - int err = 0; - - dprintk("%s:\n", __func__); - - - if (&fe->ops) - frontend_ops = &fe->ops; - if (&frontend_ops->tuner_ops) - tuner_ops = &frontend_ops->tuner_ops; - if (tuner_ops->get_frequency) { - err = tuner_ops->get_frequency(fe, &freq); - if (err < 0) { - printk(KERN_ERR "%s: Invalid parameter\n", __func__); - return err; - } - - dprintk("%s: frequency=%d\n", __func__, freq); - - } else - return -1; - - return freq; -} - -static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = { - { - {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/ - {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */ - {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */ - {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */ - {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */ - {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */ - }, { - {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/ - {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29}, - {0x2532, 0xC000, 0x251D, 0xC391, 0x706F}, - {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F}, - {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193}, - {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */ - }, { - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - } -}; - -static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = { - { - {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/ - {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */ - {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */ - {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */ - {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */ - {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */ - }, { - {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/ - {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206}, - {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3}, - {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F}, - {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB}, - {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF} - }, { - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - } -}; - -static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = { - { - {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/ - {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */ - {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */ - {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */ - {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */ - {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */ - }, { - {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/ - {0x225E, 0xC000, 0x2256, 0xC589, 0x7489}, - {0x2293, 0xC000, 0x2295, 0xC209, 0x767E}, - {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746}, - {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799}, - {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757} - - }, { - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} - } -}; - -static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz) -{ - u32 mclk_Hz = 0; /* master clock frequency (Hz) */ - u32 m, n, p; - - dprintk("%s:\n", __func__); - - if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) { - n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV); - if (n == 0) - n = n + 1; - - m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV); - if (m == 0) - m = m + 1; - - p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV); - if (p > 5) - p = 5; - - mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p)); - - dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n", - n, m, p, mclk_Hz, ExtClk_Hz); - } else - mclk_Hz = ExtClk_Hz; - - dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz); - - return mclk_Hz; -} - -static int stv0367ter_filt_coeff_init(struct stv0367_state *state, - u16 CellsCoeffs[3][6][5], u32 DemodXtal) -{ - int i, j, k, freq; - - dprintk("%s:\n", __func__); - - freq = stv0367ter_get_mclk(state, DemodXtal); - - if (freq == 53125000) - k = 1; /* equivalent to Xtal 25M on 362*/ - else if (freq == 54000000) - k = 0; /* equivalent to Xtal 27M on 362*/ - else if (freq == 52500000) - k = 2; /* equivalent to Xtal 30M on 362*/ - else - return 0; - - for (i = 1; i <= 6; i++) { - stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1); - - for (j = 1; j <= 5; j++) { - stv0367_writereg(state, - (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)), - MSB(CellsCoeffs[k][i-1][j-1])); - stv0367_writereg(state, - (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)), - LSB(CellsCoeffs[k][i-1][j-1])); - } - } - - return 1; - -} - -static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state) -{ - dprintk("%s:\n", __func__); - - stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00); - - /* Lock detect 1 */ - stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00); - stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); - stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); - - /* Lock detect 2 */ - stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01); - stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); - stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); - - /* Lock detect 3 */ - stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02); - stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); - stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); - - /* Lock detect 4 */ - stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03); - stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); - stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); - -} - -static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth, - u32 DemodXtalValue) -{ - dprintk("%s:\n", __func__); - - stv0367_writebits(state, F367TER_NRST_IIR, 0); - - switch (Bandwidth) { - case 6: - if (!stv0367ter_filt_coeff_init(state, - CellsCoeffs_6MHz_367cofdm, - DemodXtalValue)) - return 0; - break; - case 7: - if (!stv0367ter_filt_coeff_init(state, - CellsCoeffs_7MHz_367cofdm, - DemodXtalValue)) - return 0; - break; - case 8: - if (!stv0367ter_filt_coeff_init(state, - CellsCoeffs_8MHz_367cofdm, - DemodXtalValue)) - return 0; - break; - default: - return 0; - } - - stv0367_writebits(state, F367TER_NRST_IIR, 1); - - return 1; -} - -static void stv0367ter_agc_iir_rst(struct stv0367_state *state) -{ - - u8 com_n; - - dprintk("%s:\n", __func__); - - com_n = stv0367_readbits(state, F367TER_COM_N); - - stv0367_writebits(state, F367TER_COM_N, 0x07); - - stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00); - stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00); - - stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01); - stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01); - - stv0367_writebits(state, F367TER_COM_N, com_n); - -} - -static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3) -{ - int local_tempo = 0; - switch (mode) { - case 0: - local_tempo = tempo1; - break; - case 1: - local_tempo = tempo2; - break ; - - case 2: - local_tempo = tempo3; - break; - - default: - break; - } - /* msleep(local_tempo); */ - return local_tempo; -} - -static enum -stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state) -{ - int wd = 100; - unsigned short int SYR_var; - s32 SYRStatus; - - dprintk("%s:\n", __func__); - - SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); - - while ((!SYR_var) && (wd > 0)) { - usleep_range(2000, 3000); - wd -= 2; - SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); - } - - if (!SYR_var) - SYRStatus = FE_TER_NOSYMBOL; - else - SYRStatus = FE_TER_SYMBOLOK; - - dprintk("stv0367ter_check_syr SYRStatus %s\n", - SYR_var == 0 ? "No Symbol" : "OK"); - - return SYRStatus; -} - -static enum -stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state, - s32 FFTmode) -{ - - s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin; - int wd = 0; - - dprintk("%s:\n", __func__); - - switch (FFTmode) { - case 0: /*2k mode*/ - CPAMPMin = 20; - wd = 10; - break; - case 1: /*8k mode*/ - CPAMPMin = 80; - wd = 55; - break; - case 2: /*4k mode*/ - CPAMPMin = 40; - wd = 30; - break; - default: - CPAMPMin = 0xffff; /*drives to NOCPAMP */ - break; - } - - dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd); - - CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); - while ((CPAMPvalue < CPAMPMin) && (wd > 0)) { - usleep_range(1000, 2000); - wd -= 1; - CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); - /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */ - } - dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd); - if (CPAMPvalue < CPAMPMin) { - CPAMPStatus = FE_TER_NOCPAMP; - printk(KERN_ERR "CPAMP failed\n"); - } else { - printk(KERN_ERR "CPAMP OK !\n"); - CPAMPStatus = FE_TER_CPAMPOK; - } - - return CPAMPStatus; -} - -enum -stv0367_ter_signal_type stv0367ter_lock_algo(struct stv0367_state *state) -{ - enum stv0367_ter_signal_type ret_flag; - short int wd, tempo; - u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard; - u8 tmp, tmp2; - - dprintk("%s:\n", __func__); - - if (state == NULL) - return FE_TER_SWNOK; - - try = 0; - do { - ret_flag = FE_TER_LOCKOK; - - stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); - - if (state->config->if_iq_mode != 0) - stv0367_writebits(state, F367TER_COM_N, 0x07); - - stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */ - stv0367_writebits(state, F367TER_MODE, 0); - stv0367_writebits(state, F367TER_SYR_TR_DIS, 0); - usleep_range(5000, 10000); - - stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); - - - if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL) - return FE_TER_NOSYMBOL; - else { /* - if chip locked on wrong mode first try, - it must lock correctly second try */ - mode = stv0367_readbits(state, F367TER_SYR_MODE); - if (stv0367ter_check_cpamp(state, mode) == - FE_TER_NOCPAMP) { - if (try == 0) - ret_flag = FE_TER_NOCPAMP; - - } - } - - try++; - } while ((try < 10) && (ret_flag != FE_TER_LOCKOK)); - - tmp = stv0367_readreg(state, R367TER_SYR_STAT); - tmp2 = stv0367_readreg(state, R367TER_STATUS); - dprintk("state=%p\n", state); - dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n", - mode, tmp, tmp2); - - tmp = stv0367_readreg(state, R367TER_PRVIT); - tmp2 = stv0367_readreg(state, R367TER_I2CRPT); - dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2); - - tmp = stv0367_readreg(state, R367TER_GAIN_SRC1); - dprintk("GAIN_SRC1=0x%x\n", tmp); - - if ((mode != 0) && (mode != 1) && (mode != 2)) - return FE_TER_SWNOK; - - /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */ - - /*suppress EPQ auto for SYR_GARD 1/16 or 1/32 - and set channel predictor in automatic */ -#if 0 - switch (guard) { - - case 0: - case 1: - stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); - stv0367_writereg(state, R367TER_CHC_CTL, 0x01); - break; - case 2: - case 3: - stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); - stv0367_writereg(state, R367TER_CHC_CTL, 0x11); - break; - - default: - return FE_TER_SWNOK; - } -#endif - - /*reset fec an reedsolo FOR 367 only*/ - stv0367_writebits(state, F367TER_RST_SFEC, 1); - stv0367_writebits(state, F367TER_RST_REEDSOLO, 1); - usleep_range(1000, 2000); - stv0367_writebits(state, F367TER_RST_SFEC, 0); - stv0367_writebits(state, F367TER_RST_REEDSOLO, 0); - - u_var1 = stv0367_readbits(state, F367TER_LK); - u_var2 = stv0367_readbits(state, F367TER_PRF); - u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); - /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */ - - wd = stv0367ter_duration(mode, 125, 500, 250); - tempo = stv0367ter_duration(mode, 4, 16, 8); - - /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */ - while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) { - usleep_range(1000 * tempo, 1000 * (tempo + 1)); - wd -= tempo; - u_var1 = stv0367_readbits(state, F367TER_LK); - u_var2 = stv0367_readbits(state, F367TER_PRF); - u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); - /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */ - } - - if (!u_var1) - return FE_TER_NOLOCK; - - - if (!u_var2) - return FE_TER_NOPRFOUND; - - if (!u_var3) - return FE_TER_NOTPS; - - guard = stv0367_readbits(state, F367TER_SYR_GUARD); - stv0367_writereg(state, R367TER_CHC_CTL, 0x11); - switch (guard) { - case 0: - case 1: - stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); - /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/ - stv0367_writebits(state, F367TER_SYR_FILTER, 0); - break; - case 2: - case 3: - stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); - /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/ - stv0367_writebits(state, F367TER_SYR_FILTER, 1); - break; - - default: - return FE_TER_SWNOK; - } - - /* apply Sfec workaround if 8K 64QAM CR!=1/2*/ - if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) && - (mode == 1) && - (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) { - stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0); - stv0367_writereg(state, R367TER_SFDLYSETM, 0x60); - stv0367_writereg(state, R367TER_SFDLYSETL, 0x0); - } else - stv0367_writereg(state, R367TER_SFDLYSETH, 0x0); - - wd = stv0367ter_duration(mode, 125, 500, 250); - u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); - - while ((!u_var4) && (wd >= 0)) { - usleep_range(1000 * tempo, 1000 * (tempo + 1)); - wd -= tempo; - u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); - } - - if (!u_var4) - return FE_TER_NOLOCK; - - /* for 367 leave COM_N at 0x7 for IQ_mode*/ - /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) { - tempo=0; - while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) && - (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) { - ChipWaitOrAbort(state,1); - tempo+=1; - } - - stv0367_writebits(state,F367TER_COM_N,0x17); - } */ - - stv0367_writebits(state, F367TER_SYR_TR_DIS, 1); - - dprintk("FE_TER_LOCKOK !!!\n"); - - return FE_TER_LOCKOK; - -} - -static void stv0367ter_set_ts_mode(struct stv0367_state *state, - enum stv0367_ts_mode PathTS) -{ - - dprintk("%s:\n", __func__); - - if (state == NULL) - return; - - stv0367_writebits(state, F367TER_TS_DIS, 0); - switch (PathTS) { - default: - /*for removing warning :default we can assume in parallel mode*/ - case STV0367_PARALLEL_PUNCT_CLOCK: - stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0); - stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0); - break; - case STV0367_SERIAL_PUNCT_CLOCK: - stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1); -// stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1); - break; - } -} - -static void stv0367ter_set_clk_pol(struct stv0367_state *state, - enum stv0367_clk_pol clock) -{ - - dprintk("%s:\n", __func__); - - if (state == NULL) - return; - - switch (clock) { - case STV0367_RISINGEDGE_CLOCK: - stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1); - break; - case STV0367_FALLINGEDGE_CLOCK: - stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); - break; - /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/ - default: - stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); - break; - } -} - -#if 0 -static void stv0367ter_core_sw(struct stv0367_state *state) -{ - - dprintk("%s:\n", __func__); - - stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); - stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); - msleep(350); -} -#endif -static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on) -{ - struct stv0367_state *state = fe->demodulator_priv; - - dprintk("%s:\n", __func__); - - if (standby_on) { - stv0367_writebits(state, F367TER_STDBY, 1); - stv0367_writebits(state, F367TER_STDBY_FEC, 1); - stv0367_writebits(state, F367TER_STDBY_CORE, 1); - } else { - stv0367_writebits(state, F367TER_STDBY, 0); - stv0367_writebits(state, F367TER_STDBY_FEC, 0); - stv0367_writebits(state, F367TER_STDBY_CORE, 0); - } - - return 0; -} - -static int stv0367ter_sleep(struct dvb_frontend *fe) -{ - return stv0367ter_standby(fe, 1); -} - -int stv0367ter_init(struct dvb_frontend *fe) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367ter_state *ter_state = state->ter_state; - int i; - - dprintk("%s:\n", __func__); - - ter_state->pBER = 0; - - for (i = 0; i < STV0367TER_NBREGS; i++) - stv0367_writereg(state, def0367ter[i].addr, - def0367ter[i].value); - - switch (state->config->xtal) { - /*set internal freq to 53.125MHz */ - case 25000000: - stv0367_writereg(state, R367TER_PLLMDIV, 0xa); - stv0367_writereg(state, R367TER_PLLNDIV, 0x55); - stv0367_writereg(state, R367TER_PLLSETUP, 0x18); - break; - default: - case 27000000: - dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n"); - stv0367_writereg(state, R367TER_PLLMDIV, 0x1); - stv0367_writereg(state, R367TER_PLLNDIV, 0x8); - stv0367_writereg(state, R367TER_PLLSETUP, 0x18); - break; - case 30000000: - stv0367_writereg(state, R367TER_PLLMDIV, 0xc); - stv0367_writereg(state, R367TER_PLLNDIV, 0x55); - stv0367_writereg(state, R367TER_PLLSETUP, 0x18); - break; - } - - stv0367_writereg(state, R367TER_I2CRPT, 0x38); - stv0367_writereg(state, R367TER_ANACTRL, 0x00); - - /*Set TS1 and TS2 to serial or parallel mode */ - stv0367ter_set_ts_mode(state, state->config->ts_mode); - stv0367ter_set_clk_pol(state, state->config->clk_pol); - - state->chip_id = stv0367_readreg(state, R367TER_ID); - ter_state->first_lock = 0; - ter_state->unlock_counter = 2; - - return 0; -} - -static int stv0367ter_algo(struct dvb_frontend *fe, - struct dvb_frontend_parameters *param) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367ter_state *ter_state = state->ter_state; - int offset = 0, tempo = 0; - u8 u_var; - u8 /*constell,*/ counter, tps_rcvd[2]; - s8 step; - s32 timing_offset = 0; - u32 trl_nomrate = 0, InternalFreq = 0, temp = 0; - - dprintk("%s:\n", __func__); - - ter_state->frequency = param->frequency; - ter_state->force = FE_TER_FORCENONE - + stv0367_readbits(state, F367TER_FORCE) * 2; - ter_state->if_iq_mode = state->config->if_iq_mode; - switch (state->config->if_iq_mode) { - case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */ - dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n"); - stv0367_writebits(state, F367TER_TUNER_BB, 0); - stv0367_writebits(state, F367TER_LONGPATH_IF, 0); - stv0367_writebits(state, F367TER_DEMUX_SWAP, 0); - break; - case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */ - dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n"); - stv0367_writebits(state, F367TER_TUNER_BB, 0); - stv0367_writebits(state, F367TER_LONGPATH_IF, 1); - stv0367_writebits(state, F367TER_DEMUX_SWAP, 1); - break; - case FE_TER_IQ_TUNER: /* IQ mode */ - dprintk("ALGO: FE_TER_IQ_TUNER selected\n"); - stv0367_writebits(state, F367TER_TUNER_BB, 1); - stv0367_writebits(state, F367TER_PPM_INVSEL, 0); - break; - default: - printk(KERN_ERR "ALGO: wrong TUNER type selected\n"); - return -EINVAL; - } - - usleep_range(5000, 7000); - - switch (param->inversion) { - case INVERSION_AUTO: - default: - dprintk("%s: inversion AUTO\n", __func__); - if (ter_state->if_iq_mode == FE_TER_IQ_TUNER) - stv0367_writebits(state, F367TER_IQ_INVERT, - ter_state->sense); - else - stv0367_writebits(state, F367TER_INV_SPECTR, - ter_state->sense); - - break; - case INVERSION_ON: - case INVERSION_OFF: - if (ter_state->if_iq_mode == FE_TER_IQ_TUNER) - stv0367_writebits(state, F367TER_IQ_INVERT, - param->inversion); - else - stv0367_writebits(state, F367TER_INV_SPECTR, - param->inversion); - - break; - } - - if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) && - (ter_state->pBW != ter_state->bw)) { - stv0367ter_agc_iir_lock_detect_set(state); - - /*set fine agc target to 180 for LPIF or IQ mode*/ - /* set Q_AGCTarget */ - stv0367_writebits(state, F367TER_SEL_IQNTAR, 1); - stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); - /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ - - /* set Q_AGCTarget */ - stv0367_writebits(state, F367TER_SEL_IQNTAR, 0); - stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); - /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ - - if (!stv0367_iir_filt_init(state, ter_state->bw, - state->config->xtal)) - return -EINVAL; - /*set IIR filter once for 6,7 or 8MHz BW*/ - ter_state->pBW = ter_state->bw; - - stv0367ter_agc_iir_rst(state); - } - - if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO) - stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01); - else - stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00); - - InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000; - temp = (int) - ((((ter_state->bw * 64 * (1 << 15) * 100) - / (InternalFreq)) * 10) / 7); - - stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2); - temp = temp / 2; - stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256); - stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256); - - temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 + - stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 + - stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB); - temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq))); - stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256); - stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256); - temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 + - stv0367_readbits(state, F367TER_GAIN_SRC_LO); - - temp = (int) - ((InternalFreq - state->IF) * (1 << 16) / (InternalFreq)); - - dprintk("DEROT temp=0x%x\n", temp); - stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256); - stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256); - - ter_state->echo_pos = 0; - ter_state->ucblocks = 0; /* liplianin */ - ter_state->pBER = 0; /* liplianin */ - stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos); - - if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK) - return 0; - - ter_state->state = FE_TER_LOCKOK; - /* update results */ - tps_rcvd[0] = stv0367_readreg(state, R367TER_TPS_RCVD2); - tps_rcvd[1] = stv0367_readreg(state, R367TER_TPS_RCVD3); - - ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE); - ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD); - - ter_state->first_lock = 1; /* we know sense now :) */ - - ter_state->agc_val = - (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) + - (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) + - stv0367_readbits(state, F367TER_AGC2_VAL_LO) + - (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8); - - /* Carrier offset calculation */ - stv0367_writebits(state, F367TER_FREEZE, 1); - offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ; - offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8); - offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO)); - stv0367_writebits(state, F367TER_FREEZE, 0); - if (offset > 8388607) - offset -= 16777216; - - offset = offset * 2 / 16384; - - if (ter_state->mode == FE_TER_MODE_2K) - offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/ - else if (ter_state->mode == FE_TER_MODE_4K) - offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/ - else if (ter_state->mode == FE_TER_MODE_8K) - offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/ - - if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) { - if ((stv0367_readbits(state, F367TER_INV_SPECTR) == - (stv0367_readbits(state, - F367TER_STATUS_INV_SPECRUM) == 1))) - offset = offset * -1; - } - - if (ter_state->bw == 6) - offset = (offset * 6) / 8; - else if (ter_state->bw == 7) - offset = (offset * 7) / 8; - - ter_state->frequency += offset; - - tempo = 10; /* exit even if timing_offset stays null */ - while ((timing_offset == 0) && (tempo > 0)) { - usleep_range(10000, 20000); /*was 20ms */ - /* fine tuning of timing offset if required */ - timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO) - + 256 * stv0367_readbits(state, - F367TER_TRL_TOFFSET_HI); - if (timing_offset >= 32768) - timing_offset -= 65536; - trl_nomrate = (512 * stv0367_readbits(state, - F367TER_TRL_NOMRATE_HI) - + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 - + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB)); - - timing_offset = ((signed)(1000000 / trl_nomrate) * - timing_offset) / 2048; - tempo--; - } - - if (timing_offset <= 0) { - timing_offset = (timing_offset - 11) / 22; - step = -1; - } else { - timing_offset = (timing_offset + 11) / 22; - step = 1; - } - - for (counter = 0; counter < abs(timing_offset); counter++) { - trl_nomrate += step; - stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, - trl_nomrate % 2); - stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, - trl_nomrate / 2); - usleep_range(1000, 2000); - } - - usleep_range(5000, 6000); - /* unlocks could happen in case of trl centring big step, - then a core off/on restarts demod */ - u_var = stv0367_readbits(state, F367TER_LK); - - if (!u_var) { - stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); - msleep(20); - stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); - } - - return 0; -} - -static int stv0367ter_set_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *param) -{ - struct dvb_ofdm_parameters *op = ¶m->u.ofdm; - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367ter_state *ter_state = state->ter_state; - - /*u8 trials[2]; */ - s8 num_trials, index; - u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF }; - - stv0367ter_init(fe); - - if (fe->ops.tuner_ops.set_params) { - //if (fe->ops.i2c_gate_ctrl) - //fe->ops.i2c_gate_ctrl(fe, 1); - fe->ops.tuner_ops.set_params(fe, param); - //if (fe->ops.i2c_gate_ctrl) - //fe->ops.i2c_gate_ctrl(fe, 0); - } - if (fe->ops.tuner_ops.get_if) { - s32 IF; - fe->ops.tuner_ops.get_if(fe, &IF); - state->IF = IF / 1000; - } - switch (op->transmission_mode) { - default: - case TRANSMISSION_MODE_AUTO: - case TRANSMISSION_MODE_2K: - ter_state->mode = FE_TER_MODE_2K; - break; -/* case TRANSMISSION_MODE_4K: - pLook.mode = FE_TER_MODE_4K; - break;*/ - case TRANSMISSION_MODE_8K: - ter_state->mode = FE_TER_MODE_8K; - break; - } - - switch (op->guard_interval) { - default: - case GUARD_INTERVAL_1_32: - case GUARD_INTERVAL_1_16: - case GUARD_INTERVAL_1_8: - case GUARD_INTERVAL_1_4: - ter_state->guard = op->guard_interval; - break; - case GUARD_INTERVAL_AUTO: - ter_state->guard = GUARD_INTERVAL_1_32; - break; - } - - switch (op->bandwidth) { - case BANDWIDTH_6_MHZ: - ter_state->bw = FE_TER_CHAN_BW_6M; - break; - case BANDWIDTH_7_MHZ: - ter_state->bw = FE_TER_CHAN_BW_7M; - break; - case BANDWIDTH_8_MHZ: - default: - ter_state->bw = FE_TER_CHAN_BW_8M; - } - - ter_state->hierarchy = FE_TER_HIER_NONE; - - switch (param->inversion) { - case INVERSION_OFF: - case INVERSION_ON: - num_trials = 1; - break; - default: - num_trials = 2; - if (ter_state->first_lock) - num_trials = 1; - break; - } - - ter_state->state = FE_TER_NOLOCK; - index = 0; - - while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) { - if (!ter_state->first_lock) { - if (param->inversion == INVERSION_AUTO) - ter_state->sense = SenseTrials[index]; - - } - stv0367ter_algo(fe,/* &pLook, result,*/ param); - - if ((ter_state->state == FE_TER_LOCKOK) && - (param->inversion == INVERSION_AUTO) && - (index == 1)) { - /* invert spectrum sense */ - SenseTrials[index] = SenseTrials[0]; - SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2; - } - - index++; - } - - return 0; -} - -static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367ter_state *ter_state = state->ter_state; - u32 errs = 0; - - /*wait for counting completion*/ - if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) { - errs = - ((u32)stv0367_readbits(state, F367TER_ERR_CNT1) - * (1 << 16)) - + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI) - * (1 << 8)) - + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO)); - ter_state->ucblocks = errs; - } - - (*ucblocks) = ter_state->ucblocks; - - return 0; -} - -static int stv0367ter_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *param) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367ter_state *ter_state = state->ter_state; - struct dvb_ofdm_parameters *op = ¶m->u.ofdm; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - - int error = 0; - enum stv0367_ter_mode mode; - int constell = 0,/* snr = 0,*/ Data = 0; - - param->frequency = stv0367_get_tuner_freq(fe); - if ((int)param->frequency < 0) - param->frequency = c->frequency; - - constell = stv0367_readbits(state, F367TER_TPS_CONST); - if (constell == 0) - op->constellation = QPSK; - else if (constell == 1) - op->constellation = QAM_16; - else - op->constellation = QAM_64; - - param->inversion = stv0367_readbits(state, F367TER_INV_SPECTR); - - /* Get the Hierarchical mode */ - Data = stv0367_readbits(state, F367TER_TPS_HIERMODE); - - switch (Data) { - case 0: - op->hierarchy_information = HIERARCHY_NONE; - break; - case 1: - op->hierarchy_information = HIERARCHY_1; - break; - case 2: - op->hierarchy_information = HIERARCHY_2; - break; - case 3: - op->hierarchy_information = HIERARCHY_4; - break; - default: - op->hierarchy_information = HIERARCHY_AUTO; - break; /* error */ - } - - /* Get the FEC Rate */ - if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO) - Data = stv0367_readbits(state, F367TER_TPS_LPCODE); - else - Data = stv0367_readbits(state, F367TER_TPS_HPCODE); - - switch (Data) { - case 0: - op->code_rate_HP = FEC_1_2; - break; - case 1: - op->code_rate_HP = FEC_2_3; - break; - case 2: - op->code_rate_HP = FEC_3_4; - break; - case 3: - op->code_rate_HP = FEC_5_6; - break; - case 4: - op->code_rate_HP = FEC_7_8; - break; - default: - op->code_rate_HP = FEC_AUTO; - break; /* error */ - } - - mode = stv0367_readbits(state, F367TER_SYR_MODE); - - switch (mode) { - case FE_TER_MODE_2K: - op->transmission_mode = TRANSMISSION_MODE_2K; - break; -/* case FE_TER_MODE_4K: - op->transmission_mode = TRANSMISSION_MODE_4K; - break;*/ - case FE_TER_MODE_8K: - op->transmission_mode = TRANSMISSION_MODE_8K; - break; - default: - op->transmission_mode = TRANSMISSION_MODE_AUTO; - } - - op->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD); - - return error; -} - -static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct stv0367_state *state = fe->demodulator_priv; - u32 snru32 = 0; - int cpt = 0; - u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG); - - while (cpt < 10) { - usleep_range(2000, 3000); - if (cut == 0x50) /*cut 1.0 cut 1.1*/ - snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4; - else /*cu2.0*/ - snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR); - - cpt++; - } - - snru32 /= 10;/*average on 10 values*/ - - *snr = snru32 / 1000; - - return 0; -} - -#if 0 -static int stv0367ter_status(struct dvb_frontend *fe) -{ - - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367ter_state *ter_state = state->ter_state; - int locked = FALSE; - - locked = (stv0367_readbits(state, F367TER_LK)); - if (!locked) - ter_state->unlock_counter += 1; - else - ter_state->unlock_counter = 0; - - if (ter_state->unlock_counter > 2) { - if (!stv0367_readbits(state, F367TER_TPS_LOCK) || - (!stv0367_readbits(state, F367TER_LK))) { - stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); - usleep_range(2000, 3000); - stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); - msleep(350); - locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) && - (stv0367_readbits(state, F367TER_LK)); - } - - } - - return locked; -} -#endif - -static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct stv0367_state *state = fe->demodulator_priv; - - dprintk("%s:\n", __func__); - - *status = 0; - - if (stv0367_readbits(state, F367TER_LK)) { - *status |= FE_HAS_LOCK; - dprintk("%s: stv0367 has locked\n", __func__); - } - - return 0; -} - -static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367ter_state *ter_state = state->ter_state; - u32 Errors = 0, tber = 0, temporary = 0; - int abc = 0, def = 0; - - - /*wait for counting completion*/ - if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) - Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT) - * (1 << 16)) - + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI) - * (1 << 8)) - + ((u32)stv0367_readbits(state, - F367TER_SFEC_ERR_CNT_LO)); - /*measurement not completed, load previous value*/ - else { - tber = ter_state->pBER; - return 0; - } - - abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE); - def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT); - - if (Errors == 0) { - tber = 0; - } else if (abc == 0x7) { - if (Errors <= 4) { - temporary = (Errors * 1000000000) / (8 * (1 << 14)); - temporary = temporary; - } else if (Errors <= 42) { - temporary = (Errors * 100000000) / (8 * (1 << 14)); - temporary = temporary * 10; - } else if (Errors <= 429) { - temporary = (Errors * 10000000) / (8 * (1 << 14)); - temporary = temporary * 100; - } else if (Errors <= 4294) { - temporary = (Errors * 1000000) / (8 * (1 << 14)); - temporary = temporary * 1000; - } else if (Errors <= 42949) { - temporary = (Errors * 100000) / (8 * (1 << 14)); - temporary = temporary * 10000; - } else if (Errors <= 429496) { - temporary = (Errors * 10000) / (8 * (1 << 14)); - temporary = temporary * 100000; - } else { /*if (Errors<4294967) 2^22 max error*/ - temporary = (Errors * 1000) / (8 * (1 << 14)); - temporary = temporary * 100000; /* still to *10 */ - } - - /* Byte error*/ - if (def == 2) - /*tber=Errors/(8*(1 <<14));*/ - tber = temporary; - else if (def == 3) - /*tber=Errors/(8*(1 <<16));*/ - tber = temporary / 4; - else if (def == 4) - /*tber=Errors/(8*(1 <<18));*/ - tber = temporary / 16; - else if (def == 5) - /*tber=Errors/(8*(1 <<20));*/ - tber = temporary / 64; - else if (def == 6) - /*tber=Errors/(8*(1 <<22));*/ - tber = temporary / 256; - else - /* should not pass here*/ - tber = 0; - - if ((Errors < 4294967) && (Errors > 429496)) - tber *= 10; - - } - - /* save actual value */ - ter_state->pBER = tber; - - (*ber) = tber; - - return 0; -} -#if 0 -static u32 stv0367ter_get_per(struct stv0367_state *state) -{ - struct stv0367ter_state *ter_state = state->ter_state; - u32 Errors = 0, Per = 0, temporary = 0; - int abc = 0, def = 0, cpt = 0; - - while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) && - (cpt < 400)) || ((Errors == 0) && (cpt < 400))) { - usleep_range(1000, 2000); - Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1) - * (1 << 16)) - + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI) - * (1 << 8)) - + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO)); - cpt++; - } - abc = stv0367_readbits(state, F367TER_ERR_SRC1); - def = stv0367_readbits(state, F367TER_NUM_EVT1); - - if (Errors == 0) - Per = 0; - else if (abc == 0x9) { - if (Errors <= 4) { - temporary = (Errors * 1000000000) / (8 * (1 << 8)); - temporary = temporary; - } else if (Errors <= 42) { - temporary = (Errors * 100000000) / (8 * (1 << 8)); - temporary = temporary * 10; - } else if (Errors <= 429) { - temporary = (Errors * 10000000) / (8 * (1 << 8)); - temporary = temporary * 100; - } else if (Errors <= 4294) { - temporary = (Errors * 1000000) / (8 * (1 << 8)); - temporary = temporary * 1000; - } else if (Errors <= 42949) { - temporary = (Errors * 100000) / (8 * (1 << 8)); - temporary = temporary * 10000; - } else { /*if(Errors<=429496) 2^16 errors max*/ - temporary = (Errors * 10000) / (8 * (1 << 8)); - temporary = temporary * 100000; - } - - /* pkt error*/ - if (def == 2) - /*Per=Errors/(1 << 8);*/ - Per = temporary; - else if (def == 3) - /*Per=Errors/(1 << 10);*/ - Per = temporary / 4; - else if (def == 4) - /*Per=Errors/(1 << 12);*/ - Per = temporary / 16; - else if (def == 5) - /*Per=Errors/(1 << 14);*/ - Per = temporary / 64; - else if (def == 6) - /*Per=Errors/(1 << 16);*/ - Per = temporary / 256; - else - Per = 0; - - } - /* save actual value */ - ter_state->pPER = Per; - - return Per; -} -#endif -static int stv0367_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings - *fe_tune_settings) -{ - fe_tune_settings->min_delay_ms = 1000; - fe_tune_settings->step_size = 0; - fe_tune_settings->max_drift = 0; - - return 0; -} - -static void stv0367_release(struct dvb_frontend *fe) -{ - struct stv0367_state *state = fe->demodulator_priv; - - kfree(state->ter_state); - kfree(state->cab_state); - kfree(state); -} - -static struct dvb_frontend_ops stv0367ter_ops = { - .info = { - .name = "ST STV0367 DVB-T", - .type = FE_OFDM, - .frequency_min = 47000000, - .frequency_max = 862000000, - .frequency_stepsize = 15625, - .frequency_tolerance = 0, - .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | - FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | - FE_CAN_FEC_AUTO | - FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | - FE_CAN_INVERSION_AUTO | - FE_CAN_MUTE_TS - }, - .release = stv0367_release, - .init = stv0367ter_init, - .sleep = stv0367ter_sleep, - .i2c_gate_ctrl = stv0367ter_gate_ctrl, - .set_frontend = stv0367ter_set_frontend, - .get_frontend = stv0367ter_get_frontend, - .get_tune_settings = stv0367_get_tune_settings, - .read_status = stv0367ter_read_status, - .read_ber = stv0367ter_read_ber,/* too slow */ -/* .read_signal_strength = stv0367_read_signal_strength,*/ - .read_snr = stv0367ter_read_snr, - .read_ucblocks = stv0367ter_read_ucblocks, -}; - -struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, - struct i2c_adapter *i2c) -{ - struct stv0367_state *state = NULL; - struct stv0367ter_state *ter_state = NULL; - - /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); - if (state == NULL) - goto error; - ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL); - if (ter_state == NULL) - goto error; - - /* setup the state */ - state->i2c = i2c; - state->config = config; - state->ter_state = ter_state; - state->fe.ops = stv0367ter_ops; - state->fe.demodulator_priv = state; - state->chip_id = stv0367_readreg(state, 0xf000); - - dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); - - /* check if the demod is there */ - if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) - goto error; - - return &state->fe; - -error: - kfree(ter_state); - kfree(state); - return NULL; -} -EXPORT_SYMBOL(stv0367ter_attach); - -static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable) -{ - struct stv0367_state *state = fe->demodulator_priv; - - dprintk("%s:\n", __func__); - - stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0); - - return 0; -} - -static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz) -{ - struct stv0367_state *state = fe->demodulator_priv; - u32 mclk_Hz = 0; /* master clock frequency (Hz) */ - u32 M, N, P; - - if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) { - N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV); - if (N == 0) - N = N + 1; - - M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV); - if (M == 0) - M = M + 1; - - P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV); - - if (P > 5) - P = 5; - - mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P)); - dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n", - mclk_Hz); - } else - mclk_Hz = ExtClk_Hz; - - dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz); - - return mclk_Hz; -} - -static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz) -{ - u32 ADCClk_Hz = ExtClk_Hz; - - ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz); - - return ADCClk_Hz; -} - -enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state, - u32 SymbolRate, - enum stv0367cab_mod QAMSize) -{ - /* Set QAM size */ - stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize); - - /* Set Registers settings specific to the QAM size */ - switch (QAMSize) { - case FE_CAB_MOD_QAM4: - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); - break; - case FE_CAB_MOD_QAM16: - stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64); - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); - stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); - stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); - stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); - stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a); - break; - case FE_CAB_MOD_QAM32: - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); - stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e); - stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7); - stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d); - stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); - stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); - break; - case FE_CAB_MOD_QAM64: - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82); - stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); - if (SymbolRate > 45000000) { - stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5); - } else if (SymbolRate > 25000000) { - stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); - } else { - stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); - } - stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); - stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); - stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99); - break; - case FE_CAB_MOD_QAM128: - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); - stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76); - stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1); - if (SymbolRate > 45000000) - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); - else if (SymbolRate > 25000000) - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); - else - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97); - - stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e); - stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); - stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); - break; - case FE_CAB_MOD_QAM256: - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94); - stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); - stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); - if (SymbolRate > 45000000) - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); - else if (SymbolRate > 25000000) - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); - else - stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); - - stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); - stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85); - stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); - stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); - break; - case FE_CAB_MOD_QAM512: - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); - break; - case FE_CAB_MOD_QAM1024: - stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); - break; - default: - break; - } - - return QAMSize; -} - -static u32 stv0367cab_set_derot_freq(struct stv0367_state *state, - u32 adc_hz, s32 derot_hz) -{ - u32 sampled_if = 0; - u32 adc_khz; - - adc_khz = adc_hz / 1000; - - dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz); - - if (adc_khz != 0) { - if (derot_hz < 1000000) - derot_hz = adc_hz / 4; /* ZIF operation */ - if (derot_hz > adc_hz) - derot_hz = derot_hz - adc_hz; - sampled_if = (u32)derot_hz / 1000; - sampled_if *= 32768; - sampled_if /= adc_khz; - sampled_if *= 256; - } - - if (sampled_if > 8388607) - sampled_if = 8388607; - - dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if); - - stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if); - stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8)); - stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16)); - - return derot_hz; -} - -static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz) -{ - u32 sampled_if; - - sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) + - (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) + - (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16); - - sampled_if /= 256; - sampled_if *= (adc_hz / 1000); - sampled_if += 1; - sampled_if /= 32768; - - return sampled_if; -} - -static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz, - u32 mclk_hz, u32 SymbolRate, - enum stv0367cab_mod QAMSize) -{ - u32 QamSizeCorr = 0; - u32 u32_tmp = 0, u32_tmp1 = 0; - u32 adp_khz; - - dprintk("%s:\n", __func__); - - /* Set Correction factor of SRC gain */ - switch (QAMSize) { - case FE_CAB_MOD_QAM4: - QamSizeCorr = 1110; - break; - case FE_CAB_MOD_QAM16: - QamSizeCorr = 1032; - break; - case FE_CAB_MOD_QAM32: - QamSizeCorr = 954; - break; - case FE_CAB_MOD_QAM64: - QamSizeCorr = 983; - break; - case FE_CAB_MOD_QAM128: - QamSizeCorr = 957; - break; - case FE_CAB_MOD_QAM256: - QamSizeCorr = 948; - break; - case FE_CAB_MOD_QAM512: - QamSizeCorr = 0; - break; - case FE_CAB_MOD_QAM1024: - QamSizeCorr = 944; - break; - default: - break; - } - - /* Transfer ratio calculation */ - if (adc_hz != 0) { - u32_tmp = 256 * SymbolRate; - u32_tmp = u32_tmp / adc_hz; - } - stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp); - - /* Symbol rate and SRC gain calculation */ - adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */ - if (adp_khz != 0) { - u32_tmp = SymbolRate; - u32_tmp1 = SymbolRate; - - if (u32_tmp < 2097152) { /* 2097152 = 2^21 */ - /* Symbol rate calculation */ - u32_tmp *= 2048; /* 2048 = 2^11 */ - u32_tmp = u32_tmp / adp_khz; - u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */ - u32_tmp /= 125 ; /* 125 = 1000/2^3 */ - u32_tmp = u32_tmp * 8; /* 8 = 2^3 */ - - /* SRC Gain Calculation */ - u32_tmp1 *= 2048; /* *2*2^10 */ - u32_tmp1 /= 439; /* *2/878 */ - u32_tmp1 *= 256; /* *2^8 */ - u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ - u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ - u32_tmp1 = u32_tmp1 / 10000000; - - } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */ - /* Symbol rate calculation */ - u32_tmp *= 1024 ; /* 1024 = 2**10 */ - u32_tmp = u32_tmp / adp_khz; - u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */ - u32_tmp /= 125 ; /* 125 = 1000/2**3 */ - u32_tmp = u32_tmp * 16; /* 16 = 2**4 */ - - /* SRC Gain Calculation */ - u32_tmp1 *= 1024; /* *2*2^9 */ - u32_tmp1 /= 439; /* *2/878 */ - u32_tmp1 *= 256; /* *2^8 */ - u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/ - u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ - u32_tmp1 = u32_tmp1 / 5000000; - } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */ - /* Symbol rate calculation */ - u32_tmp *= 512 ; /* 512 = 2**9 */ - u32_tmp = u32_tmp / adp_khz; - u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */ - u32_tmp /= 125 ; /* 125 = 1000/2**3 */ - u32_tmp = u32_tmp * 32; /* 32 = 2**5 */ - - /* SRC Gain Calculation */ - u32_tmp1 *= 512; /* *2*2^8 */ - u32_tmp1 /= 439; /* *2/878 */ - u32_tmp1 *= 256; /* *2^8 */ - u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ - u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ - u32_tmp1 = u32_tmp1 / 2500000; - } else { - /* Symbol rate calculation */ - u32_tmp *= 256 ; /* 256 = 2**8 */ - u32_tmp = u32_tmp / adp_khz; - u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */ - u32_tmp /= 125 ; /* 125 = 1000/2**3 */ - u32_tmp = u32_tmp * 64; /* 64 = 2**6 */ - - /* SRC Gain Calculation */ - u32_tmp1 *= 256; /* 2*2^7 */ - u32_tmp1 /= 439; /* *2/878 */ - u32_tmp1 *= 256; /* *2^8 */ - u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ - u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ - u32_tmp1 = u32_tmp1 / 1250000; - } - } -#if 0 - /* Filters' coefficients are calculated and written - into registers only if the filters are enabled */ - if (stv0367_readbits(state, F367CAB_ADJ_EN)) { - stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz, - SymbolRate); - /* AllPass filter must be enabled - when the adjacents filter is used */ - stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1); - stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate); - } else - /* AllPass filter must be disabled - when the adjacents filter is not used */ -#endif - stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); - - stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp); - stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8)); - stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16)); - stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24)); - - stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff); - stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff); - - return SymbolRate ; -} - -static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz) -{ - u32 regsym; - u32 adp_khz; - - regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) + - (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) + - (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) + - (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24); - - adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */ - - if (regsym < 134217728) { /* 134217728L = 2**27*/ - regsym = regsym * 32; /* 32 = 2**5 */ - regsym = regsym / 32768; /* 32768L = 2**15 */ - regsym = adp_khz * regsym; /* AdpClk in kHz */ - regsym = regsym / 128; /* 128 = 2**7 */ - regsym *= 125 ; /* 125 = 1000/2**3 */ - regsym /= 2048 ; /* 2048 = 2**11 */ - } else if (regsym < 268435456) { /* 268435456L = 2**28 */ - regsym = regsym * 16; /* 16 = 2**4 */ - regsym = regsym / 32768; /* 32768L = 2**15 */ - regsym = adp_khz * regsym; /* AdpClk in kHz */ - regsym = regsym / 128; /* 128 = 2**7 */ - regsym *= 125 ; /* 125 = 1000/2**3*/ - regsym /= 1024 ; /* 256 = 2**10*/ - } else if (regsym < 536870912) { /* 536870912L = 2**29*/ - regsym = regsym * 8; /* 8 = 2**3 */ - regsym = regsym / 32768; /* 32768L = 2**15 */ - regsym = adp_khz * regsym; /* AdpClk in kHz */ - regsym = regsym / 128; /* 128 = 2**7 */ - regsym *= 125 ; /* 125 = 1000/2**3 */ - regsym /= 512 ; /* 128 = 2**9 */ - } else { - regsym = regsym * 4; /* 4 = 2**2 */ - regsym = regsym / 32768; /* 32768L = 2**15 */ - regsym = adp_khz * regsym; /* AdpClk in kHz */ - regsym = regsym / 128; /* 128 = 2**7 */ - regsym *= 125 ; /* 125 = 1000/2**3 */ - regsym /= 256 ; /* 64 = 2**8 */ - } - - return regsym; -} - -static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct stv0367_state *state = fe->demodulator_priv; - - dprintk("%s:\n", __func__); - - *status = 0; - - if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) { - *status |= FE_HAS_LOCK; - dprintk("%s: stv0367 has locked\n", __func__); - } - - return 0; -} - -static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on) -{ - struct stv0367_state *state = fe->demodulator_priv; - - dprintk("%s:\n", __func__); - - if (standby_on) { - stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03); - stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01); - stv0367_writebits(state, F367CAB_STDBY, 1); - stv0367_writebits(state, F367CAB_STDBY_CORE, 1); - stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0); - stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0); - stv0367_writebits(state, F367CAB_POFFQ, 1); - stv0367_writebits(state, F367CAB_POFFI, 1); - } else { - stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00); - stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00); - stv0367_writebits(state, F367CAB_STDBY, 0); - stv0367_writebits(state, F367CAB_STDBY_CORE, 0); - stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1); - stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1); - stv0367_writebits(state, F367CAB_POFFQ, 0); - stv0367_writebits(state, F367CAB_POFFI, 0); - } - - return 0; -} - -static int stv0367cab_sleep(struct dvb_frontend *fe) -{ - return stv0367cab_standby(fe, 1); -} - -int stv0367cab_init(struct dvb_frontend *fe) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367cab_state *cab_state = state->cab_state; - int i; - - dprintk("%s:\n", __func__); - - for (i = 0; i < STV0367CAB_NBREGS; i++) - stv0367_writereg(state, def0367cab[i].addr, - def0367cab[i].value); - - switch (state->config->ts_mode) { - case STV0367_DVBCI_CLOCK: - dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n"); - stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03); - break; - case STV0367_SERIAL_PUNCT_CLOCK: - case STV0367_SERIAL_CONT_CLOCK: - stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01); - break; - case STV0367_PARALLEL_PUNCT_CLOCK: - case STV0367_OUTPUTMODE_DEFAULT: - stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00); - break; - } - - switch (state->config->clk_pol) { - case STV0367_RISINGEDGE_CLOCK: - stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00); - break; - case STV0367_FALLINGEDGE_CLOCK: - case STV0367_CLOCKPOLARITY_DEFAULT: - stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01); - break; - } - - stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00); - - stv0367_writebits(state, F367CAB_CT_NBST, 0x01); - - stv0367_writebits(state, F367CAB_TS_SWAP, 0x01); - - stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00); - - stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */ - - cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal); - cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal); - - return 0; -} -static -enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state, - struct dvb_frontend_parameters *param) -{ - struct dvb_qam_parameters *op = ¶m->u.qam; - struct stv0367cab_state *cab_state = state->cab_state; - enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC; - u32 QAMFEC_Lock, QAM_Lock, u32_tmp, - LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols, - CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut; - u8 TrackAGCAccum; - s32 tmp; - - dprintk("%s:\n", __func__); - - /* Timeouts calculation */ - /* A max lock time of 25 ms is allowed for delayed AGC */ - AGCTimeOut = 25; - /* 100000 symbols needed by the TRL as a maximum value */ - TRLTimeOut = 100000000 / op->symbol_rate; - /* CRLSymbols is the needed number of symbols to achieve a lock - within [-4%, +4%] of the symbol rate. - CRL timeout is calculated - for a lock within [-search_range, +search_range]. - EQL timeout can be changed depending on - the micro-reflections we want to handle. - A characterization must be performed - with these echoes to get new timeout values. - */ - switch (op->modulation) { - case QAM_16: - CRLSymbols = 150000; - EQLTimeOut = 100; - break; - case QAM_32: - CRLSymbols = 250000; - EQLTimeOut = 100; - break; - case QAM_64: - CRLSymbols = 200000; - EQLTimeOut = 100; - break; - case QAM_128: - CRLSymbols = 250000; - EQLTimeOut = 100; - break; - case QAM_256: - CRLSymbols = 250000; - EQLTimeOut = 100; - break; - default: - CRLSymbols = 200000; - EQLTimeOut = 100; - break; - } -#if 0 - if (pIntParams->search_range < 0) { - CRLTimeOut = (25 * CRLSymbols * - (-pIntParams->search_range / 1000)) / - (pIntParams->symbol_rate / 1000); - } else -#endif - CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) / - (op->symbol_rate / 1000); - - CRLTimeOut = (1000 * CRLTimeOut) / op->symbol_rate; - /* Timeouts below 50ms are coerced */ - if (CRLTimeOut < 50) - CRLTimeOut = 50; - /* A maximum of 100 TS packets is needed to get FEC lock even in case - the spectrum inversion needs to be changed. - This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps - */ - FECTimeOut = 20; - DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; - - dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut); - - /* Reset the TRL to ensure nothing starts until the - AGC is stable which ensures a better lock time - */ - stv0367_writereg(state, R367CAB_CTRL_1, 0x04); - /* Set AGC accumulation time to minimum and lock threshold to maximum - in order to speed up the AGC lock */ - TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL); - stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0); - /* Modulus Mapper is disabled */ - stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0); - /* Disable the sweep function */ - stv0367_writebits(state, F367CAB_SWEEP_EN, 0); - /* The sweep function is never used, Sweep rate must be set to 0 */ - /* Set the derotator frequency in Hz */ - stv0367cab_set_derot_freq(state, cab_state->adc_clk, - (1000 * (s32)state->IF + cab_state->derot_offset)); - /* Disable the Allpass Filter when the symbol rate is out of range */ - if ((op->symbol_rate > 10800000) | (op->symbol_rate < 1800000)) { - stv0367_writebits(state, F367CAB_ADJ_EN, 0); - stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); - } -#if 0 - /* Check if the tuner is locked */ - tuner_lock = stv0367cab_tuner_get_status(fe); - if (tuner_lock == 0) - return FE_367CAB_NOTUNER; -#endif - /* Relase the TRL to start demodulator acquisition */ - /* Wait for QAM lock */ - LockTime = 0; - stv0367_writereg(state, R367CAB_CTRL_1, 0x00); - do { - QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS); - if ((LockTime >= (DemodTimeOut - EQLTimeOut)) && - (QAM_Lock == 0x04)) - /* - * We don't wait longer, the frequency/phase offset - * must be too big - */ - LockTime = DemodTimeOut; - else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) && - (QAM_Lock == 0x02)) - /* - * We don't wait longer, either there is no signal or - * it is not the right symbol rate or it is an analog - * carrier - */ - { - LockTime = DemodTimeOut; - u32_tmp = stv0367_readbits(state, - F367CAB_AGC_PWR_WORD_LO) + - (stv0367_readbits(state, - F367CAB_AGC_PWR_WORD_ME) << 8) + - (stv0367_readbits(state, - F367CAB_AGC_PWR_WORD_HI) << 16); - if (u32_tmp >= 131072) - u32_tmp = 262144 - u32_tmp; - u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state, - F367CAB_AGC_IF_BWSEL))); - - if (u32_tmp < stv0367_readbits(state, - F367CAB_AGC_PWRREF_LO) + - 256 * stv0367_readbits(state, - F367CAB_AGC_PWRREF_HI) - 10) - QAM_Lock = 0x0f; - } else { - usleep_range(10000, 20000); - LockTime += 10; - } - dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime); - tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); - - dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp); - - } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) && - (LockTime < DemodTimeOut)); - - dprintk("QAM_Lock=0x%x\n", QAM_Lock); - - tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); - dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp); - tmp = stv0367_readreg(state, R367CAB_IT_STATUS2); - dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp); - - tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk); - dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp); - - if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) { - /* Wait for FEC lock */ - LockTime = 0; - do { - usleep_range(5000, 7000); - LockTime += 5; - QAMFEC_Lock = stv0367_readbits(state, - F367CAB_QAMFEC_LOCK); - } while (!QAMFEC_Lock && (LockTime < FECTimeOut)); - } else - QAMFEC_Lock = 0; - - if (QAMFEC_Lock) { - signalType = FE_CAB_DATAOK; - cab_state->modulation = op->modulation; - cab_state->spect_inv = stv0367_readbits(state, - F367CAB_QUAD_INV); -#if 0 -/* not clear for me */ - if (state->IF != 0) { - if (state->IF > cab_state->adc_clk / 1000) { - cab_state->freq_khz = - FE_Cab_TunerGetFrequency(pIntParams->hTuner) - - stv0367cab_get_derot_freq(state, cab_state->adc_clk) - - cab_state->adc_clk / 1000 + state->IF; - } else { - cab_state->freq_khz = - FE_Cab_TunerGetFrequency(pIntParams->hTuner) - - stv0367cab_get_derot_freq(state, cab_state->adc_clk) - + state->IF; - } - } else { - cab_state->freq_khz = - FE_Cab_TunerGetFrequency(pIntParams->hTuner) + - stv0367cab_get_derot_freq(state, - cab_state->adc_clk) - - cab_state->adc_clk / 4000; - } -#endif - cab_state->symbol_rate = stv0367cab_GetSymbolRate(state, - cab_state->mclk); - cab_state->locked = 1; - - /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/ - } else { - switch (QAM_Lock) { - case 1: - signalType = FE_CAB_NOAGC; - break; - case 2: - signalType = FE_CAB_NOTIMING; - break; - case 3: - signalType = FE_CAB_TIMINGOK; - break; - case 4: - signalType = FE_CAB_NOCARRIER; - break; - case 5: - signalType = FE_CAB_CARRIEROK; - break; - case 7: - signalType = FE_CAB_NOBLIND; - break; - case 8: - signalType = FE_CAB_BLINDOK; - break; - case 10: - signalType = FE_CAB_NODEMOD; - break; - case 11: - signalType = FE_CAB_DEMODOK; - break; - case 12: - signalType = FE_CAB_DEMODOK; - break; - case 13: - signalType = FE_CAB_NODEMOD; - break; - case 14: - signalType = FE_CAB_NOBLIND; - break; - case 15: - signalType = FE_CAB_NOSIGNAL; - break; - default: - break; - } - - } - - /* Set the AGC control values to tracking values */ - stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum); - return signalType; -} - -static int stv0367cab_set_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *param) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367cab_state *cab_state = state->cab_state; - struct dvb_qam_parameters *op = ¶m->u.qam; - enum stv0367cab_mod QAMSize = 0; - - dprintk("%s: freq = %d, srate = %d\n", __func__, - param->frequency, op->symbol_rate); - - cab_state->derot_offset = 0; - - switch (op->modulation) { - case QAM_16: - QAMSize = FE_CAB_MOD_QAM16; - break; - case QAM_32: - QAMSize = FE_CAB_MOD_QAM32; - break; - case QAM_64: - QAMSize = FE_CAB_MOD_QAM64; - break; - case QAM_128: - QAMSize = FE_CAB_MOD_QAM128; - break; - case QAM_256: - QAMSize = FE_CAB_MOD_QAM256; - break; - default: - break; - } - - stv0367cab_init(fe); - - /* Tuner Frequency Setting */ - if (fe->ops.tuner_ops.set_params) { - //if (fe->ops.i2c_gate_ctrl) - //fe->ops.i2c_gate_ctrl(fe, 1); - fe->ops.tuner_ops.set_params(fe, param); - //if (fe->ops.i2c_gate_ctrl) - //fe->ops.i2c_gate_ctrl(fe, 0); - } - if (fe->ops.tuner_ops.get_if) { - s32 IF; - fe->ops.tuner_ops.get_if(fe, &IF); - state->IF = IF / 1000; - } - - stv0367cab_SetQamSize( - state, - op->symbol_rate, - QAMSize); - - stv0367cab_set_srate(state, - cab_state->adc_clk, - cab_state->mclk, - op->symbol_rate, - QAMSize); - /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */ - cab_state->state = stv0367cab_algo(state, param); - return 0; -} - -static int stv0367cab_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *param) -{ - struct stv0367_state *state = fe->demodulator_priv; - struct stv0367cab_state *cab_state = state->cab_state; - struct dvb_qam_parameters *op = ¶m->u.qam; - - enum stv0367cab_mod QAMSize; - - dprintk("%s:\n", __func__); - - op->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk); - - QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); - switch (QAMSize) { - case FE_CAB_MOD_QAM16: - op->modulation = QAM_16; - break; - case FE_CAB_MOD_QAM32: - op->modulation = QAM_32; - break; - case FE_CAB_MOD_QAM64: - op->modulation = QAM_64; - break; - case FE_CAB_MOD_QAM128: - op->modulation = QAM_128; - break; - case QAM_256: - op->modulation = QAM_256; - break; - default: - break; - } - - param->frequency = stv0367_get_tuner_freq(fe); - - dprintk("%s: tuner frequency = %d\n", __func__, param->frequency); - - if (state->IF == 0) { - param->frequency += - (stv0367cab_get_derot_freq(state, cab_state->adc_clk) - - cab_state->adc_clk / 4000); - return 0; - } - - if (state->IF > cab_state->adc_clk / 1000) - param->frequency += (state->IF - - stv0367cab_get_derot_freq(state, cab_state->adc_clk) - - cab_state->adc_clk / 1000); - else - param->frequency += (state->IF - - stv0367cab_get_derot_freq(state, cab_state->adc_clk)); - - return 0; -} - -#if 0 -void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize, - u32 symbol_rate, FE_367qam_Monitor *Monitor_results) -{ - stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results); - stv0367cab_GetPacketsCount(state, Monitor_results); - - return; -} - -static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct stv0367_state *state = fe->demodulator_priv; - - return 0; -} -#endif -static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state) -{ - s32 rfLevel = 0; - s32 RfAgcPwm = 0, IfAgcPwm = 0; - u8 i; - - stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0); - - RfAgcPwm = - (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) + - (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2); - RfAgcPwm = 100 * RfAgcPwm / 1023; - - IfAgcPwm = - stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) + - (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8); - if (IfAgcPwm >= 2048) - IfAgcPwm -= 2048; - else - IfAgcPwm += 2048; - - IfAgcPwm = 100 * IfAgcPwm / 4095; - - /* For DTT75467 on NIM */ - if (RfAgcPwm < 90 && IfAgcPwm < 28) { - for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) { - if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) { - rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i]; - break; - } - } - if (i == RF_LOOKUP_TABLE_SIZE) - rfLevel = -56; - } else { /*if IF AGC>10*/ - for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) { - if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) { - rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i]; - break; - } - } - if (i == RF_LOOKUP_TABLE2_SIZE) - rfLevel = -72; - } - return rfLevel; -} - -static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength) -{ - struct stv0367_state *state = fe->demodulator_priv; - - s32 signal = stv0367cab_get_rf_lvl(state); - - dprintk("%s: signal=%d dBm\n", __func__, signal); - - if (signal <= -72) - *strength = 65535; - else - *strength = (22 + signal) * (-1311); - - dprintk("%s: strength=%d\n", __func__, (*strength)); - - return 0; -} - -static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct stv0367_state *state = fe->demodulator_priv; - u32 noisepercentage; - enum stv0367cab_mod QAMSize; - u32 regval = 0, temp = 0; - int power, i; - - QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); - switch (QAMSize) { - case FE_CAB_MOD_QAM4: - power = 21904; - break; - case FE_CAB_MOD_QAM16: - power = 20480; - break; - case FE_CAB_MOD_QAM32: - power = 23040; - break; - case FE_CAB_MOD_QAM64: - power = 21504; - break; - case FE_CAB_MOD_QAM128: - power = 23616; - break; - case FE_CAB_MOD_QAM256: - power = 21760; - break; - case FE_CAB_MOD_QAM512: - power = 1; - break; - case FE_CAB_MOD_QAM1024: - power = 21280; - break; - default: - power = 1; - break; - } - - for (i = 0; i < 10; i++) { - regval += (stv0367_readbits(state, F367CAB_SNR_LO) - + 256 * stv0367_readbits(state, F367CAB_SNR_HI)); - } - - regval /= 10; /*for average over 10 times in for loop above*/ - if (regval != 0) { - temp = power - * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER))); - temp /= regval; - } - - /* table values, not needed to calculate logarithms */ - if (temp >= 5012) - noisepercentage = 100; - else if (temp >= 3981) - noisepercentage = 93; - else if (temp >= 3162) - noisepercentage = 86; - else if (temp >= 2512) - noisepercentage = 79; - else if (temp >= 1995) - noisepercentage = 72; - else if (temp >= 1585) - noisepercentage = 65; - else if (temp >= 1259) - noisepercentage = 58; - else if (temp >= 1000) - noisepercentage = 50; - else if (temp >= 794) - noisepercentage = 43; - else if (temp >= 501) - noisepercentage = 36; - else if (temp >= 316) - noisepercentage = 29; - else if (temp >= 200) - noisepercentage = 22; - else if (temp >= 158) - noisepercentage = 14; - else if (temp >= 126) - noisepercentage = 7; - else - noisepercentage = 0; - - dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage); - - *snr = (noisepercentage * 65535) / 100; - - return 0; -} - -static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct stv0367_state *state = fe->demodulator_priv; - int corrected, tscount; - - *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8) - | stv0367_readreg(state, R367CAB_RS_COUNTER_4); - corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8) - | stv0367_readreg(state, R367CAB_RS_COUNTER_2); - tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8) - | stv0367_readreg(state, R367CAB_RS_COUNTER_1); - - dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n", - __func__, *ucblocks, corrected, tscount); - - return 0; -}; - -static struct dvb_frontend_ops stv0367cab_ops = { - .info = { - .name = "ST STV0367 DVB-C", - .type = FE_QAM, - .frequency_min = 47000000, - .frequency_max = 862000000, - .frequency_stepsize = 62500, - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = 0x400 |/* FE_CAN_QAM_4 */ - FE_CAN_QAM_16 | FE_CAN_QAM_32 | - FE_CAN_QAM_64 | FE_CAN_QAM_128 | - FE_CAN_QAM_256 | FE_CAN_FEC_AUTO - }, - .release = stv0367_release, - .init = stv0367cab_init, - .sleep = stv0367cab_sleep, - .i2c_gate_ctrl = stv0367cab_gate_ctrl, - .set_frontend = stv0367cab_set_frontend, - .get_frontend = stv0367cab_get_frontend, - .read_status = stv0367cab_read_status, -/* .read_ber = stv0367cab_read_ber, */ - .read_signal_strength = stv0367cab_read_strength, - .read_snr = stv0367cab_read_snr, - .read_ucblocks = stv0367cab_read_ucblcks, - .get_tune_settings = stv0367_get_tune_settings, -}; - -struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, - struct i2c_adapter *i2c) -{ - struct stv0367_state *state = NULL; - struct stv0367cab_state *cab_state = NULL; - - /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); - if (state == NULL) - goto error; - cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL); - if (cab_state == NULL) - goto error; - - /* setup the state */ - state->i2c = i2c; - state->config = config; - cab_state->search_range = 280000; - state->cab_state = cab_state; - state->fe.ops = stv0367cab_ops; - state->fe.demodulator_priv = state; - state->chip_id = stv0367_readreg(state, 0xf000); - - dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); - - /* check if the demod is there */ - if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) - goto error; - - stv0367_writereg(state, R367TER_I2CRPT, 0x38); - return &state->fe; - -error: - kfree(cab_state); - kfree(state); - return NULL; -} -EXPORT_SYMBOL(stv0367cab_attach); - -MODULE_PARM_DESC(debug, "Set debug"); -MODULE_PARM_DESC(i2c_debug, "Set i2c debug"); - -MODULE_AUTHOR("Igor M. Liplianin"); -MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver"); -MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,89 +0,0 @@ -/* - * stv0367.h - * - * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. - * - * Copyright (C) ST Microelectronics. - * Copyright (C) 2010,2011 NetUP Inc. - * Copyright (C) 2010,2011 Igor M. Liplianin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef STV0367_H -#define STV0367_H - -#include -#include "dvb_frontend.h" - -enum stv0367_ts_mode { - STV0367_OUTPUTMODE_DEFAULT, - STV0367_SERIAL_PUNCT_CLOCK, - STV0367_SERIAL_CONT_CLOCK, - STV0367_PARALLEL_PUNCT_CLOCK, - STV0367_DVBCI_CLOCK -}; - -enum stv0367_clk_pol { - STV0367_CLOCKPOLARITY_DEFAULT, - STV0367_RISINGEDGE_CLOCK, - STV0367_FALLINGEDGE_CLOCK -}; - -struct stv0367_config { - u8 demod_address; - u32 xtal; - u32 if_khz;/*4500*/ - int if_iq_mode; - int ts_mode; - int clk_pol; -}; - -enum stv0367_ter_if_iq_mode { - FE_TER_NORMAL_IF_TUNER = 0, - FE_TER_LONGPATH_IF_TUNER = 1, - FE_TER_IQ_TUNER = 2 - -}; - - - -#if defined(CONFIG_DVB_STV0367) || (defined(CONFIG_DVB_STV0367_MODULE) \ - && defined(MODULE)) -extern struct -dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, - struct i2c_adapter *i2c); -extern struct -dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, - struct i2c_adapter *i2c); -#else -static inline struct -dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, - struct i2c_adapter *i2c) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -static inline struct -dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, - struct i2c_adapter *i2c) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_priv.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_priv.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,191 +0,0 @@ -/* - * stv0367_priv.h - * - * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. - * - * Copyright (C) ST Microelectronics. - * Copyright (C) 2010,2011 NetUP Inc. - * Copyright (C) 2010,2011 Igor M. Liplianin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ -/* Common driver error constants */ - -#ifndef STV0367_PRIV_H -#define STV0367_PRIV_H - -#ifndef TRUE - #define TRUE (1 == 1) -#endif -#ifndef FALSE - #define FALSE (!TRUE) -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/* MACRO definitions */ -#define ABS(X) ((X) < 0 ? (-1 * (X)) : (X)) -#define MAX(X, Y) ((X) >= (Y) ? (X) : (Y)) -#define MIN(X, Y) ((X) <= (Y) ? (X) : (Y)) -#define INRANGE(X, Y, Z) \ - ((((X) <= (Y)) && ((Y) <= (Z))) || \ - (((Z) <= (Y)) && ((Y) <= (X))) ? 1 : 0) - -#ifndef MAKEWORD -#define MAKEWORD(X, Y) (((X) << 8) + (Y)) -#endif - -#define LSB(X) (((X) & 0xff)) -#define MSB(Y) (((Y) >> 8) & 0xff) -#define MMSB(Y)(((Y) >> 16) & 0xff) - -enum stv0367_ter_signal_type { - FE_TER_NOAGC = 0, - FE_TER_AGCOK = 5, - FE_TER_NOTPS = 6, - FE_TER_TPSOK = 7, - FE_TER_NOSYMBOL = 8, - FE_TER_BAD_CPQ = 9, - FE_TER_PRFOUNDOK = 10, - FE_TER_NOPRFOUND = 11, - FE_TER_LOCKOK = 12, - FE_TER_NOLOCK = 13, - FE_TER_SYMBOLOK = 15, - FE_TER_CPAMPOK = 16, - FE_TER_NOCPAMP = 17, - FE_TER_SWNOK = 18 -}; - -enum stv0367_ter_bw { - FE_TER_CHAN_BW_6M = 6, - FE_TER_CHAN_BW_7M = 7, - FE_TER_CHAN_BW_8M = 8 -}; - -#if 0 -enum FE_TER_Rate_TPS { - FE_TER_TPS_1_2 = 0, - FE_TER_TPS_2_3 = 1, - FE_TER_TPS_3_4 = 2, - FE_TER_TPS_5_6 = 3, - FE_TER_TPS_7_8 = 4 -}; -#endif - -enum stv0367_ter_mode { - FE_TER_MODE_2K, - FE_TER_MODE_8K, - FE_TER_MODE_4K -}; -#if 0 -enum FE_TER_Hierarchy_Alpha { - FE_TER_HIER_ALPHA_NONE, /* Regular modulation */ - FE_TER_HIER_ALPHA_1, /* Hierarchical modulation a = 1*/ - FE_TER_HIER_ALPHA_2, /* Hierarchical modulation a = 2*/ - FE_TER_HIER_ALPHA_4 /* Hierarchical modulation a = 4*/ -}; -#endif -enum stv0367_ter_hierarchy { - FE_TER_HIER_NONE, /*Hierarchy None*/ - FE_TER_HIER_LOW_PRIO, /*Hierarchy : Low Priority*/ - FE_TER_HIER_HIGH_PRIO, /*Hierarchy : High Priority*/ - FE_TER_HIER_PRIO_ANY /*Hierarchy :Any*/ -}; - -#if 0 -enum fe_stv0367_ter_spec { - FE_TER_INVERSION_NONE = 0, - FE_TER_INVERSION = 1, - FE_TER_INVERSION_AUTO = 2, - FE_TER_INVERSION_UNK = 4 -}; -#endif - -#if 0 -enum FE_TER_FECRate { - FE_TER_FEC_NONE = 0x00, /* no FEC rate specified */ - FE_TER_FEC_ALL = 0xFF, /* Logical OR of all FECs */ - FE_TER_FEC_1_2 = 1, - FE_TER_FEC_2_3 = (1 << 1), - FE_TER_FEC_3_4 = (1 << 2), - FE_TER_FEC_4_5 = (1 << 3), - FE_TER_FEC_5_6 = (1 << 4), - FE_TER_FEC_6_7 = (1 << 5), - FE_TER_FEC_7_8 = (1 << 6), - FE_TER_FEC_8_9 = (1 << 7) -}; - -enum FE_TER_Rate { - FE_TER_FE_1_2 = 0, - FE_TER_FE_2_3 = 1, - FE_TER_FE_3_4 = 2, - FE_TER_FE_5_6 = 3, - FE_TER_FE_6_7 = 4, - FE_TER_FE_7_8 = 5 -}; -#endif - -enum stv0367_ter_force { - FE_TER_FORCENONE = 0, - FE_TER_FORCE_M_G = 1 -}; - -enum stv0367cab_mod { - FE_CAB_MOD_QAM4, - FE_CAB_MOD_QAM16, - FE_CAB_MOD_QAM32, - FE_CAB_MOD_QAM64, - FE_CAB_MOD_QAM128, - FE_CAB_MOD_QAM256, - FE_CAB_MOD_QAM512, - FE_CAB_MOD_QAM1024 -}; -#if 0 -enum { - FE_CAB_FEC_A = 1, /* J83 Annex A */ - FE_CAB_FEC_B = (1 << 1),/* J83 Annex B */ - FE_CAB_FEC_C = (1 << 2) /* J83 Annex C */ -} FE_CAB_FECType_t; -#endif -struct stv0367_cab_signal_info { - int locked; - u32 frequency; /* kHz */ - u32 symbol_rate; /* Mbds */ - enum stv0367cab_mod modulation; - fe_spectral_inversion_t spect_inv; - s32 Power_dBmx10; /* Power of the RF signal (dBm x 10) */ - u32 CN_dBx10; /* Carrier to noise ratio (dB x 10) */ - u32 BER; /* Bit error rate (x 10000000) */ -}; - -enum stv0367_cab_signal_type { - FE_CAB_NOTUNER, - FE_CAB_NOAGC, - FE_CAB_NOSIGNAL, - FE_CAB_NOTIMING, - FE_CAB_TIMINGOK, - FE_CAB_NOCARRIER, - FE_CAB_CARRIEROK, - FE_CAB_NOBLIND, - FE_CAB_BLINDOK, - FE_CAB_NODEMOD, - FE_CAB_DEMODOK, - FE_CAB_DATAOK -}; - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_regs.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_regs.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_regs.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,3614 +0,0 @@ -/* - * stv0367_regs.h - * - * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. - * - * Copyright (C) ST Microelectronics. - * Copyright (C) 2010,2011 NetUP Inc. - * Copyright (C) 2010,2011 Igor M. Liplianin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef STV0367_REGS_H -#define STV0367_REGS_H - -/* ID */ -#define R367TER_ID 0xf000 -#define F367TER_IDENTIFICATIONREG 0xf00000ff - -/* I2CRPT */ -#define R367TER_I2CRPT 0xf001 -#define F367TER_I2CT_ON 0xf0010080 -#define F367TER_ENARPT_LEVEL 0xf0010070 -#define F367TER_SCLT_DELAY 0xf0010008 -#define F367TER_SCLT_NOD 0xf0010004 -#define F367TER_STOP_ENABLE 0xf0010002 -#define F367TER_SDAT_NOD 0xf0010001 - -/* TOPCTRL */ -#define R367TER_TOPCTRL 0xf002 -#define F367TER_STDBY 0xf0020080 -#define F367TER_STDBY_FEC 0xf0020040 -#define F367TER_STDBY_CORE 0xf0020020 -#define F367TER_QAM_COFDM 0xf0020010 -#define F367TER_TS_DIS 0xf0020008 -#define F367TER_DIR_CLK_216 0xf0020004 -#define F367TER_TUNER_BB 0xf0020002 -#define F367TER_DVBT_H 0xf0020001 - -/* IOCFG0 */ -#define R367TER_IOCFG0 0xf003 -#define F367TER_OP0_SD 0xf0030080 -#define F367TER_OP0_VAL 0xf0030040 -#define F367TER_OP0_OD 0xf0030020 -#define F367TER_OP0_INV 0xf0030010 -#define F367TER_OP0_DACVALUE_HI 0xf003000f - -/* DAc0R */ -#define R367TER_DAC0R 0xf004 -#define F367TER_OP0_DACVALUE_LO 0xf00400ff - -/* IOCFG1 */ -#define R367TER_IOCFG1 0xf005 -#define F367TER_IP0 0xf0050040 -#define F367TER_OP1_OD 0xf0050020 -#define F367TER_OP1_INV 0xf0050010 -#define F367TER_OP1_DACVALUE_HI 0xf005000f - -/* DAC1R */ -#define R367TER_DAC1R 0xf006 -#define F367TER_OP1_DACVALUE_LO 0xf00600ff - -/* IOCFG2 */ -#define R367TER_IOCFG2 0xf007 -#define F367TER_OP2_LOCK_CONF 0xf00700e0 -#define F367TER_OP2_OD 0xf0070010 -#define F367TER_OP2_VAL 0xf0070008 -#define F367TER_OP1_LOCK_CONF 0xf0070007 - -/* SDFR */ -#define R367TER_SDFR 0xf008 -#define F367TER_OP0_FREQ 0xf00800f0 -#define F367TER_OP1_FREQ 0xf008000f - -/* STATUS */ -#define R367TER_STATUS 0xf009 -#define F367TER_TPS_LOCK 0xf0090080 -#define F367TER_SYR_LOCK 0xf0090040 -#define F367TER_AGC_LOCK 0xf0090020 -#define F367TER_PRF 0xf0090010 -#define F367TER_LK 0xf0090008 -#define F367TER_PR 0xf0090007 - -/* AUX_CLK */ -#define R367TER_AUX_CLK 0xf00a -#define F367TER_AUXFEC_CTL 0xf00a00c0 -#define F367TER_DIS_CKX4 0xf00a0020 -#define F367TER_CKSEL 0xf00a0018 -#define F367TER_CKDIV_PROG 0xf00a0006 -#define F367TER_AUXCLK_ENA 0xf00a0001 - -/* FREESYS1 */ -#define R367TER_FREESYS1 0xf00b -#define F367TER_FREE_SYS1 0xf00b00ff - -/* FREESYS2 */ -#define R367TER_FREESYS2 0xf00c -#define F367TER_FREE_SYS2 0xf00c00ff - -/* FREESYS3 */ -#define R367TER_FREESYS3 0xf00d -#define F367TER_FREE_SYS3 0xf00d00ff - -/* GPIO_CFG */ -#define R367TER_GPIO_CFG 0xf00e -#define F367TER_GPIO7_NOD 0xf00e0080 -#define F367TER_GPIO7_CFG 0xf00e0040 -#define F367TER_GPIO6_NOD 0xf00e0020 -#define F367TER_GPIO6_CFG 0xf00e0010 -#define F367TER_GPIO5_NOD 0xf00e0008 -#define F367TER_GPIO5_CFG 0xf00e0004 -#define F367TER_GPIO4_NOD 0xf00e0002 -#define F367TER_GPIO4_CFG 0xf00e0001 - -/* GPIO_CMD */ -#define R367TER_GPIO_CMD 0xf00f -#define F367TER_GPIO7_VAL 0xf00f0008 -#define F367TER_GPIO6_VAL 0xf00f0004 -#define F367TER_GPIO5_VAL 0xf00f0002 -#define F367TER_GPIO4_VAL 0xf00f0001 - -/* AGC2MAX */ -#define R367TER_AGC2MAX 0xf010 -#define F367TER_AGC2_MAX 0xf01000ff - -/* AGC2MIN */ -#define R367TER_AGC2MIN 0xf011 -#define F367TER_AGC2_MIN 0xf01100ff - -/* AGC1MAX */ -#define R367TER_AGC1MAX 0xf012 -#define F367TER_AGC1_MAX 0xf01200ff - -/* AGC1MIN */ -#define R367TER_AGC1MIN 0xf013 -#define F367TER_AGC1_MIN 0xf01300ff - -/* AGCR */ -#define R367TER_AGCR 0xf014 -#define F367TER_RATIO_A 0xf01400e0 -#define F367TER_RATIO_B 0xf0140018 -#define F367TER_RATIO_C 0xf0140007 - -/* AGC2TH */ -#define R367TER_AGC2TH 0xf015 -#define F367TER_AGC2_THRES 0xf01500ff - -/* AGC12c */ -#define R367TER_AGC12C 0xf016 -#define F367TER_AGC1_IV 0xf0160080 -#define F367TER_AGC1_OD 0xf0160040 -#define F367TER_AGC1_LOAD 0xf0160020 -#define F367TER_AGC2_IV 0xf0160010 -#define F367TER_AGC2_OD 0xf0160008 -#define F367TER_AGC2_LOAD 0xf0160004 -#define F367TER_AGC12_MODE 0xf0160003 - -/* AGCCTRL1 */ -#define R367TER_AGCCTRL1 0xf017 -#define F367TER_DAGC_ON 0xf0170080 -#define F367TER_INVERT_AGC12 0xf0170040 -#define F367TER_AGC1_MODE 0xf0170008 -#define F367TER_AGC2_MODE 0xf0170007 - -/* AGCCTRL2 */ -#define R367TER_AGCCTRL2 0xf018 -#define F367TER_FRZ2_CTRL 0xf0180060 -#define F367TER_FRZ1_CTRL 0xf0180018 -#define F367TER_TIME_CST 0xf0180007 - -/* AGC1VAL1 */ -#define R367TER_AGC1VAL1 0xf019 -#define F367TER_AGC1_VAL_LO 0xf01900ff - -/* AGC1VAL2 */ -#define R367TER_AGC1VAL2 0xf01a -#define F367TER_AGC1_VAL_HI 0xf01a000f - -/* AGC2VAL1 */ -#define R367TER_AGC2VAL1 0xf01b -#define F367TER_AGC2_VAL_LO 0xf01b00ff - -/* AGC2VAL2 */ -#define R367TER_AGC2VAL2 0xf01c -#define F367TER_AGC2_VAL_HI 0xf01c000f - -/* AGC2PGA */ -#define R367TER_AGC2PGA 0xf01d -#define F367TER_AGC2_PGA 0xf01d00ff - -/* OVF_RATE1 */ -#define R367TER_OVF_RATE1 0xf01e -#define F367TER_OVF_RATE_HI 0xf01e000f - -/* OVF_RATE2 */ -#define R367TER_OVF_RATE2 0xf01f -#define F367TER_OVF_RATE_LO 0xf01f00ff - -/* GAIN_SRC1 */ -#define R367TER_GAIN_SRC1 0xf020 -#define F367TER_INV_SPECTR 0xf0200080 -#define F367TER_IQ_INVERT 0xf0200040 -#define F367TER_INR_BYPASS 0xf0200020 -#define F367TER_STATUS_INV_SPECRUM 0xf0200010 -#define F367TER_GAIN_SRC_HI 0xf020000f - -/* GAIN_SRC2 */ -#define R367TER_GAIN_SRC2 0xf021 -#define F367TER_GAIN_SRC_LO 0xf02100ff - -/* INC_DEROT1 */ -#define R367TER_INC_DEROT1 0xf022 -#define F367TER_INC_DEROT_HI 0xf02200ff - -/* INC_DEROT2 */ -#define R367TER_INC_DEROT2 0xf023 -#define F367TER_INC_DEROT_LO 0xf02300ff - -/* PPM_CPAMP_DIR */ -#define R367TER_PPM_CPAMP_DIR 0xf024 -#define F367TER_PPM_CPAMP_DIRECT 0xf02400ff - -/* PPM_CPAMP_INV */ -#define R367TER_PPM_CPAMP_INV 0xf025 -#define F367TER_PPM_CPAMP_INVER 0xf02500ff - -/* FREESTFE_1 */ -#define R367TER_FREESTFE_1 0xf026 -#define F367TER_SYMBOL_NUMBER_INC 0xf02600c0 -#define F367TER_SEL_LSB 0xf0260004 -#define F367TER_AVERAGE_ON 0xf0260002 -#define F367TER_DC_ADJ 0xf0260001 - -/* FREESTFE_2 */ -#define R367TER_FREESTFE_2 0xf027 -#define F367TER_SEL_SRCOUT 0xf02700c0 -#define F367TER_SEL_SYRTHR 0xf027001f - -/* DCOFFSET */ -#define R367TER_DCOFFSET 0xf028 -#define F367TER_SELECT_I_Q 0xf0280080 -#define F367TER_DC_OFFSET 0xf028007f - -/* EN_PROCESS */ -#define R367TER_EN_PROCESS 0xf029 -#define F367TER_FREE 0xf02900f0 -#define F367TER_ENAB_MANUAL 0xf0290001 - -/* SDI_SMOOTHER */ -#define R367TER_SDI_SMOOTHER 0xf02a -#define F367TER_DIS_SMOOTH 0xf02a0080 -#define F367TER_SDI_INC_SMOOTHER 0xf02a007f - -/* FE_LOOP_OPEN */ -#define R367TER_FE_LOOP_OPEN 0xf02b -#define F367TER_TRL_LOOP_OP 0xf02b0002 -#define F367TER_CRL_LOOP_OP 0xf02b0001 - -/* FREQOFF1 */ -#define R367TER_FREQOFF1 0xf02c -#define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff - -/* FREQOFF2 */ -#define R367TER_FREQOFF2 0xf02d -#define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff - -/* FREQOFF3 */ -#define R367TER_FREQOFF3 0xf02e -#define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff - -/* TIMOFF1 */ -#define R367TER_TIMOFF1 0xf02f -#define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff - -/* TIMOFF2 */ -#define R367TER_TIMOFF2 0xf030 -#define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff - -/* EPQ */ -#define R367TER_EPQ 0xf031 -#define F367TER_EPQ1 0xf03100ff - -/* EPQAUTO */ -#define R367TER_EPQAUTO 0xf032 -#define F367TER_EPQ2 0xf03200ff - -/* SYR_UPDATE */ -#define R367TER_SYR_UPDATE 0xf033 -#define F367TER_SYR_PROTV 0xf0330080 -#define F367TER_SYR_PROTV_GAIN 0xf0330060 -#define F367TER_SYR_FILTER 0xf0330010 -#define F367TER_SYR_TRACK_THRES 0xf033000c - -/* CHPFREE */ -#define R367TER_CHPFREE 0xf034 -#define F367TER_CHP_FREE 0xf03400ff - -/* PPM_STATE_MAC */ -#define R367TER_PPM_STATE_MAC 0xf035 -#define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f - -/* INR_THRESHOLD */ -#define R367TER_INR_THRESHOLD 0xf036 -#define F367TER_INR_THRESH 0xf03600ff - -/* EPQ_TPS_ID_CELL */ -#define R367TER_EPQ_TPS_ID_CELL 0xf037 -#define F367TER_ENABLE_LGTH_TO_CF 0xf0370080 -#define F367TER_DIS_TPS_RSVD 0xf0370040 -#define F367TER_DIS_BCH 0xf0370020 -#define F367TER_DIS_ID_CEL 0xf0370010 -#define F367TER_TPS_ADJUST_SYM 0xf037000f - -/* EPQ_CFG */ -#define R367TER_EPQ_CFG 0xf038 -#define F367TER_EPQ_RANGE 0xf0380002 -#define F367TER_EPQ_SOFT 0xf0380001 - -/* EPQ_STATUS */ -#define R367TER_EPQ_STATUS 0xf039 -#define F367TER_SLOPE_INC 0xf03900fc -#define F367TER_TPS_FIELD 0xf0390003 - -/* AUTORELOCK */ -#define R367TER_AUTORELOCK 0xf03a -#define F367TER_BYPASS_BER_TEMPO 0xf03a0080 -#define F367TER_BER_TEMPO 0xf03a0070 -#define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008 -#define F367TER_COFDM_TEMPO 0xf03a0007 - -/* BER_THR_VMSB */ -#define R367TER_BER_THR_VMSB 0xf03b -#define F367TER_BER_THRESHOLD_HI 0xf03b00ff - -/* BER_THR_MSB */ -#define R367TER_BER_THR_MSB 0xf03c -#define F367TER_BER_THRESHOLD_MID 0xf03c00ff - -/* BER_THR_LSB */ -#define R367TER_BER_THR_LSB 0xf03d -#define F367TER_BER_THRESHOLD_LO 0xf03d00ff - -/* CCD */ -#define R367TER_CCD 0xf03e -#define F367TER_CCD_DETECTED 0xf03e0080 -#define F367TER_CCD_RESET 0xf03e0040 -#define F367TER_CCD_THRESHOLD 0xf03e000f - -/* SPECTR_CFG */ -#define R367TER_SPECTR_CFG 0xf03f -#define F367TER_SPECT_CFG 0xf03f0003 - -/* CONSTMU_MSB */ -#define R367TER_CONSTMU_MSB 0xf040 -#define F367TER_CONSTMU_FREEZE 0xf0400080 -#define F367TER_CONSTNU_FORCE_EN 0xf0400040 -#define F367TER_CONST_MU_MSB 0xf040003f - -/* CONSTMU_LSB */ -#define R367TER_CONSTMU_LSB 0xf041 -#define F367TER_CONST_MU_LSB 0xf04100ff - -/* CONSTMU_MAX_MSB */ -#define R367TER_CONSTMU_MAX_MSB 0xf042 -#define F367TER_CONST_MU_MAX_MSB 0xf042003f - -/* CONSTMU_MAX_LSB */ -#define R367TER_CONSTMU_MAX_LSB 0xf043 -#define F367TER_CONST_MU_MAX_LSB 0xf04300ff - -/* ALPHANOISE */ -#define R367TER_ALPHANOISE 0xf044 -#define F367TER_USE_ALLFILTER 0xf0440080 -#define F367TER_INTER_ON 0xf0440040 -#define F367TER_ALPHA_NOISE 0xf044001f - -/* MAXGP_MSB */ -#define R367TER_MAXGP_MSB 0xf045 -#define F367TER_MUFILTER_LENGTH 0xf04500f0 -#define F367TER_MAX_GP_MSB 0xf045000f - -/* MAXGP_LSB */ -#define R367TER_MAXGP_LSB 0xf046 -#define F367TER_MAX_GP_LSB 0xf04600ff - -/* ALPHAMSB */ -#define R367TER_ALPHAMSB 0xf047 -#define F367TER_CHC_DATARATE 0xf04700c0 -#define F367TER_ALPHA_MSB 0xf047003f - -/* ALPHALSB */ -#define R367TER_ALPHALSB 0xf048 -#define F367TER_ALPHA_LSB 0xf04800ff - -/* PILOT_ACCU */ -#define R367TER_PILOT_ACCU 0xf049 -#define F367TER_USE_SCAT4ADDAPT 0xf0490080 -#define F367TER_PILOT_ACC 0xf049001f - -/* PILOTMU_ACCU */ -#define R367TER_PILOTMU_ACCU 0xf04a -#define F367TER_DISCARD_BAD_SP 0xf04a0080 -#define F367TER_DISCARD_BAD_CP 0xf04a0040 -#define F367TER_PILOT_MU_ACCU 0xf04a001f - -/* FILT_CHANNEL_EST */ -#define R367TER_FILT_CHANNEL_EST 0xf04b -#define F367TER_USE_FILT_PILOT 0xf04b0080 -#define F367TER_FILT_CHANNEL 0xf04b007f - -/* ALPHA_NOPISE_FREQ */ -#define R367TER_ALPHA_NOPISE_FREQ 0xf04c -#define F367TER_NOISE_FREQ_FILT 0xf04c0040 -#define F367TER_ALPHA_NOISE_FREQ 0xf04c003f - -/* RATIO_PILOT */ -#define R367TER_RATIO_PILOT 0xf04d -#define F367TER_RATIO_MEAN_SP 0xf04d00f0 -#define F367TER_RATIO_MEAN_CP 0xf04d000f - -/* CHC_CTL */ -#define R367TER_CHC_CTL 0xf04e -#define F367TER_TRACK_EN 0xf04e0080 -#define F367TER_NOISE_NORM_EN 0xf04e0040 -#define F367TER_FORCE_CHC_RESET 0xf04e0020 -#define F367TER_SHORT_TIME 0xf04e0010 -#define F367TER_FORCE_STATE_EN 0xf04e0008 -#define F367TER_FORCE_STATE 0xf04e0007 - -/* EPQ_ADJUST */ -#define R367TER_EPQ_ADJUST 0xf04f -#define F367TER_ADJUST_SCAT_IND 0xf04f00c0 -#define F367TER_ONE_SYMBOL 0xf04f0010 -#define F367TER_EPQ_DECAY 0xf04f000e -#define F367TER_HOLD_SLOPE 0xf04f0001 - -/* EPQ_THRES */ -#define R367TER_EPQ_THRES 0xf050 -#define F367TER_EPQ_THR 0xf05000ff - -/* OMEGA_CTL */ -#define R367TER_OMEGA_CTL 0xf051 -#define F367TER_OMEGA_RST 0xf0510080 -#define F367TER_FREEZE_OMEGA 0xf0510040 -#define F367TER_OMEGA_SEL 0xf051003f - -/* GP_CTL */ -#define R367TER_GP_CTL 0xf052 -#define F367TER_CHC_STATE 0xf05200e0 -#define F367TER_FREEZE_GP 0xf0520010 -#define F367TER_GP_SEL 0xf052000f - -/* MUMSB */ -#define R367TER_MUMSB 0xf053 -#define F367TER_MU_MSB 0xf053007f - -/* MULSB */ -#define R367TER_MULSB 0xf054 -#define F367TER_MU_LSB 0xf05400ff - -/* GPMSB */ -#define R367TER_GPMSB 0xf055 -#define F367TER_CSI_THRESHOLD 0xf05500e0 -#define F367TER_GP_MSB 0xf055000f - -/* GPLSB */ -#define R367TER_GPLSB 0xf056 -#define F367TER_GP_LSB 0xf05600ff - -/* OMEGAMSB */ -#define R367TER_OMEGAMSB 0xf057 -#define F367TER_OMEGA_MSB 0xf057007f - -/* OMEGALSB */ -#define R367TER_OMEGALSB 0xf058 -#define F367TER_OMEGA_LSB 0xf05800ff - -/* SCAT_NB */ -#define R367TER_SCAT_NB 0xf059 -#define F367TER_CHC_TEST 0xf05900f8 -#define F367TER_SCAT_NUMB 0xf0590003 - -/* CHC_DUMMY */ -#define R367TER_CHC_DUMMY 0xf05a -#define F367TER_CHC_DUM 0xf05a00ff - -/* INC_CTL */ -#define R367TER_INC_CTL 0xf05b -#define F367TER_INC_BYPASS 0xf05b0080 -#define F367TER_INC_NDEPTH 0xf05b000c -#define F367TER_INC_MADEPTH 0xf05b0003 - -/* INCTHRES_COR1 */ -#define R367TER_INCTHRES_COR1 0xf05c -#define F367TER_INC_THRES_COR1 0xf05c00ff - -/* INCTHRES_COR2 */ -#define R367TER_INCTHRES_COR2 0xf05d -#define F367TER_INC_THRES_COR2 0xf05d00ff - -/* INCTHRES_DET1 */ -#define R367TER_INCTHRES_DET1 0xf05e -#define F367TER_INC_THRES_DET1 0xf05e003f - -/* INCTHRES_DET2 */ -#define R367TER_INCTHRES_DET2 0xf05f -#define F367TER_INC_THRES_DET2 0xf05f003f - -/* IIR_CELLNB */ -#define R367TER_IIR_CELLNB 0xf060 -#define F367TER_NRST_IIR 0xf0600080 -#define F367TER_IIR_CELL_NB 0xf0600007 - -/* IIRCX_COEFF1_MSB */ -#define R367TER_IIRCX_COEFF1_MSB 0xf061 -#define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff - -/* IIRCX_COEFF1_LSB */ -#define R367TER_IIRCX_COEFF1_LSB 0xf062 -#define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff - -/* IIRCX_COEFF2_MSB */ -#define R367TER_IIRCX_COEFF2_MSB 0xf063 -#define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff - -/* IIRCX_COEFF2_LSB */ -#define R367TER_IIRCX_COEFF2_LSB 0xf064 -#define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff - -/* IIRCX_COEFF3_MSB */ -#define R367TER_IIRCX_COEFF3_MSB 0xf065 -#define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff - -/* IIRCX_COEFF3_LSB */ -#define R367TER_IIRCX_COEFF3_LSB 0xf066 -#define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff - -/* IIRCX_COEFF4_MSB */ -#define R367TER_IIRCX_COEFF4_MSB 0xf067 -#define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff - -/* IIRCX_COEFF4_LSB */ -#define R367TER_IIRCX_COEFF4_LSB 0xf068 -#define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff - -/* IIRCX_COEFF5_MSB */ -#define R367TER_IIRCX_COEFF5_MSB 0xf069 -#define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff - -/* IIRCX_COEFF5_LSB */ -#define R367TER_IIRCX_COEFF5_LSB 0xf06a -#define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff - -/* FEPATH_CFG */ -#define R367TER_FEPATH_CFG 0xf06b -#define F367TER_DEMUX_SWAP 0xf06b0004 -#define F367TER_DIGAGC_SWAP 0xf06b0002 -#define F367TER_LONGPATH_IF 0xf06b0001 - -/* PMC1_FUNC */ -#define R367TER_PMC1_FUNC 0xf06c -#define F367TER_SOFT_RSTN 0xf06c0080 -#define F367TER_PMC1_AVERAGE_TIME 0xf06c0078 -#define F367TER_PMC1_WAIT_TIME 0xf06c0006 -#define F367TER_PMC1_2N_SEL 0xf06c0001 - -/* PMC1_FOR */ -#define R367TER_PMC1_FOR 0xf06d -#define F367TER_PMC1_FORCE 0xf06d0080 -#define F367TER_PMC1_FORCE_VALUE 0xf06d007c - -/* PMC2_FUNC */ -#define R367TER_PMC2_FUNC 0xf06e -#define F367TER_PMC2_SOFT_STN 0xf06e0080 -#define F367TER_PMC2_ACCU_TIME 0xf06e0070 -#define F367TER_PMC2_CMDP_MN 0xf06e0008 -#define F367TER_PMC2_SWAP 0xf06e0004 - -/* STATUS_ERR_DA */ -#define R367TER_STATUS_ERR_DA 0xf06f -#define F367TER_COM_USEGAINTRK 0xf06f0080 -#define F367TER_COM_AGCLOCK 0xf06f0040 -#define F367TER_AUT_AGCLOCK 0xf06f0020 -#define F367TER_MIN_ERR_X_LSB 0xf06f000f - -/* DIG_AGC_R */ -#define R367TER_DIG_AGC_R 0xf070 -#define F367TER_COM_SOFT_RSTN 0xf0700080 -#define F367TER_COM_AGC_ON 0xf0700040 -#define F367TER_COM_EARLY 0xf0700020 -#define F367TER_AUT_SOFT_RESETN 0xf0700010 -#define F367TER_AUT_AGC_ON 0xf0700008 -#define F367TER_AUT_EARLY 0xf0700004 -#define F367TER_AUT_ROT_EN 0xf0700002 -#define F367TER_LOCK_SOFT_RESETN 0xf0700001 - -/* COMAGC_TARMSB */ -#define R367TER_COMAGC_TARMSB 0xf071 -#define F367TER_COM_AGC_TARGET_MSB 0xf07100ff - -/* COM_AGC_TAR_ENMODE */ -#define R367TER_COM_AGC_TAR_ENMODE 0xf072 -#define F367TER_COM_AGC_TARGET_LSB 0xf07200f0 -#define F367TER_COM_ENMODE 0xf072000f - -/* COM_AGC_CFG */ -#define R367TER_COM_AGC_CFG 0xf073 -#define F367TER_COM_N 0xf07300f8 -#define F367TER_COM_STABMODE 0xf0730006 -#define F367TER_ERR_SEL 0xf0730001 - -/* COM_AGC_GAIN1 */ -#define R367TER_COM_AGC_GAIN1 0xf074 -#define F367TER_COM_GAIN1aCK 0xf07400f0 -#define F367TER_COM_GAIN1TRK 0xf074000f - -/* AUT_AGC_TARGETMSB */ -#define R367TER_AUT_AGC_TARGETMSB 0xf075 -#define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff - -/* LOCK_DET_MSB */ -#define R367TER_LOCK_DET_MSB 0xf076 -#define F367TER_LOCK_DETECT_MSB 0xf07600ff - -/* AGCTAR_LOCK_LSBS */ -#define R367TER_AGCTAR_LOCK_LSBS 0xf077 -#define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0 -#define F367TER_LOCK_DETECT_LSB 0xf077000f - -/* AUT_GAIN_EN */ -#define R367TER_AUT_GAIN_EN 0xf078 -#define F367TER_AUT_ENMODE 0xf07800f0 -#define F367TER_AUT_GAIN2 0xf078000f - -/* AUT_CFG */ -#define R367TER_AUT_CFG 0xf079 -#define F367TER_AUT_N 0xf07900f8 -#define F367TER_INT_CHOICE 0xf0790006 -#define F367TER_INT_LOAD 0xf0790001 - -/* LOCKN */ -#define R367TER_LOCKN 0xf07a -#define F367TER_LOCK_N 0xf07a00f8 -#define F367TER_SEL_IQNTAR 0xf07a0004 -#define F367TER_LOCK_DETECT_CHOICE 0xf07a0003 - -/* INT_X_3 */ -#define R367TER_INT_X_3 0xf07b -#define F367TER_INT_X3 0xf07b00ff - -/* INT_X_2 */ -#define R367TER_INT_X_2 0xf07c -#define F367TER_INT_X2 0xf07c00ff - -/* INT_X_1 */ -#define R367TER_INT_X_1 0xf07d -#define F367TER_INT_X1 0xf07d00ff - -/* INT_X_0 */ -#define R367TER_INT_X_0 0xf07e -#define F367TER_INT_X0 0xf07e00ff - -/* MIN_ERRX_MSB */ -#define R367TER_MIN_ERRX_MSB 0xf07f -#define F367TER_MIN_ERR_X_MSB 0xf07f00ff - -/* COR_CTL */ -#define R367TER_COR_CTL 0xf080 -#define F367TER_CORE_ACTIVE 0xf0800020 -#define F367TER_HOLD 0xf0800010 -#define F367TER_CORE_STATE_CTL 0xf080000f - -/* COR_STAT */ -#define R367TER_COR_STAT 0xf081 -#define F367TER_SCATT_LOCKED 0xf0810080 -#define F367TER_TPS_LOCKED 0xf0810040 -#define F367TER_SYR_LOCKED_COR 0xf0810020 -#define F367TER_AGC_LOCKED_STAT 0xf0810010 -#define F367TER_CORE_STATE_STAT 0xf081000f - -/* COR_INTEN */ -#define R367TER_COR_INTEN 0xf082 -#define F367TER_INTEN 0xf0820080 -#define F367TER_INTEN_SYR 0xf0820020 -#define F367TER_INTEN_FFT 0xf0820010 -#define F367TER_INTEN_AGC 0xf0820008 -#define F367TER_INTEN_TPS1 0xf0820004 -#define F367TER_INTEN_TPS2 0xf0820002 -#define F367TER_INTEN_TPS3 0xf0820001 - -/* COR_INTSTAT */ -#define R367TER_COR_INTSTAT 0xf083 -#define F367TER_INTSTAT_SYR 0xf0830020 -#define F367TER_INTSTAT_FFT 0xf0830010 -#define F367TER_INTSAT_AGC 0xf0830008 -#define F367TER_INTSTAT_TPS1 0xf0830004 -#define F367TER_INTSTAT_TPS2 0xf0830002 -#define F367TER_INTSTAT_TPS3 0xf0830001 - -/* COR_MODEGUARD */ -#define R367TER_COR_MODEGUARD 0xf084 -#define F367TER_FORCE 0xf0840010 -#define F367TER_MODE 0xf084000c -#define F367TER_GUARD 0xf0840003 - -/* AGC_CTL */ -#define R367TER_AGC_CTL 0xf085 -#define F367TER_AGC_TIMING_FACTOR 0xf08500e0 -#define F367TER_AGC_LAST 0xf0850010 -#define F367TER_AGC_GAIN 0xf085000c -#define F367TER_AGC_NEG 0xf0850002 -#define F367TER_AGC_SET 0xf0850001 - -/* AGC_MANUAL1 */ -#define R367TER_AGC_MANUAL1 0xf086 -#define F367TER_AGC_VAL_LO 0xf08600ff - -/* AGC_MANUAL2 */ -#define R367TER_AGC_MANUAL2 0xf087 -#define F367TER_AGC_VAL_HI 0xf087000f - -/* AGC_TARG */ -#define R367TER_AGC_TARG 0xf088 -#define F367TER_AGC_TARGET 0xf08800ff - -/* AGC_GAIN1 */ -#define R367TER_AGC_GAIN1 0xf089 -#define F367TER_AGC_GAIN_LO 0xf08900ff - -/* AGC_GAIN2 */ -#define R367TER_AGC_GAIN2 0xf08a -#define F367TER_AGC_LOCKED_GAIN2 0xf08a0010 -#define F367TER_AGC_GAIN_HI 0xf08a000f - -/* RESERVED_1 */ -#define R367TER_RESERVED_1 0xf08b -#define F367TER_RESERVED1 0xf08b00ff - -/* RESERVED_2 */ -#define R367TER_RESERVED_2 0xf08c -#define F367TER_RESERVED2 0xf08c00ff - -/* RESERVED_3 */ -#define R367TER_RESERVED_3 0xf08d -#define F367TER_RESERVED3 0xf08d00ff - -/* CAS_CTL */ -#define R367TER_CAS_CTL 0xf08e -#define F367TER_CCS_ENABLE 0xf08e0080 -#define F367TER_ACS_DISABLE 0xf08e0040 -#define F367TER_DAGC_DIS 0xf08e0020 -#define F367TER_DAGC_GAIN 0xf08e0018 -#define F367TER_CCSMU 0xf08e0007 - -/* CAS_FREQ */ -#define R367TER_CAS_FREQ 0xf08f -#define F367TER_CCS_FREQ 0xf08f00ff - -/* CAS_DAGCGAIN */ -#define R367TER_CAS_DAGCGAIN 0xf090 -#define F367TER_CAS_DAGC_GAIN 0xf09000ff - -/* SYR_CTL */ -#define R367TER_SYR_CTL 0xf091 -#define F367TER_SICTH_ENABLE 0xf0910080 -#define F367TER_LONG_ECHO 0xf0910078 -#define F367TER_AUTO_LE_EN 0xf0910004 -#define F367TER_SYR_BYPASS 0xf0910002 -#define F367TER_SYR_TR_DIS 0xf0910001 - -/* SYR_STAT */ -#define R367TER_SYR_STAT 0xf092 -#define F367TER_SYR_LOCKED_STAT 0xf0920010 -#define F367TER_SYR_MODE 0xf092000c -#define F367TER_SYR_GUARD 0xf0920003 - -/* SYR_NCO1 */ -#define R367TER_SYR_NCO1 0xf093 -#define F367TER_SYR_NCO_LO 0xf09300ff - -/* SYR_NCO2 */ -#define R367TER_SYR_NCO2 0xf094 -#define F367TER_SYR_NCO_HI 0xf094003f - -/* SYR_OFFSET1 */ -#define R367TER_SYR_OFFSET1 0xf095 -#define F367TER_SYR_OFFSET_LO 0xf09500ff - -/* SYR_OFFSET2 */ -#define R367TER_SYR_OFFSET2 0xf096 -#define F367TER_SYR_OFFSET_HI 0xf096003f - -/* FFT_CTL */ -#define R367TER_FFT_CTL 0xf097 -#define F367TER_SHIFT_FFT_TRIG 0xf0970018 -#define F367TER_FFT_TRIGGER 0xf0970004 -#define F367TER_FFT_MANUAL 0xf0970002 -#define F367TER_IFFT_MODE 0xf0970001 - -/* SCR_CTL */ -#define R367TER_SCR_CTL 0xf098 -#define F367TER_SYRADJDECAY 0xf0980070 -#define F367TER_SCR_CPEDIS 0xf0980002 -#define F367TER_SCR_DIS 0xf0980001 - -/* PPM_CTL1 */ -#define R367TER_PPM_CTL1 0xf099 -#define F367TER_PPM_MAXFREQ 0xf0990030 -#define F367TER_PPM_MAXTIM 0xf0990008 -#define F367TER_PPM_INVSEL 0xf0990004 -#define F367TER_PPM_SCATDIS 0xf0990002 -#define F367TER_PPM_BYP 0xf0990001 - -/* TRL_CTL */ -#define R367TER_TRL_CTL 0xf09a -#define F367TER_TRL_NOMRATE_LSB 0xf09a0080 -#define F367TER_TRL_GAIN_FACTOR 0xf09a0078 -#define F367TER_TRL_LOOPGAIN 0xf09a0007 - -/* TRL_NOMRATE1 */ -#define R367TER_TRL_NOMRATE1 0xf09b -#define F367TER_TRL_NOMRATE_LO 0xf09b00ff - -/* TRL_NOMRATE2 */ -#define R367TER_TRL_NOMRATE2 0xf09c -#define F367TER_TRL_NOMRATE_HI 0xf09c00ff - -/* TRL_TIME1 */ -#define R367TER_TRL_TIME1 0xf09d -#define F367TER_TRL_TOFFSET_LO 0xf09d00ff - -/* TRL_TIME2 */ -#define R367TER_TRL_TIME2 0xf09e -#define F367TER_TRL_TOFFSET_HI 0xf09e00ff - -/* CRL_CTL */ -#define R367TER_CRL_CTL 0xf09f -#define F367TER_CRL_DIS 0xf09f0080 -#define F367TER_CRL_GAIN_FACTOR 0xf09f0078 -#define F367TER_CRL_LOOPGAIN 0xf09f0007 - -/* CRL_FREQ1 */ -#define R367TER_CRL_FREQ1 0xf0a0 -#define F367TER_CRL_FOFFSET_LO 0xf0a000ff - -/* CRL_FREQ2 */ -#define R367TER_CRL_FREQ2 0xf0a1 -#define F367TER_CRL_FOFFSET_HI 0xf0a100ff - -/* CRL_FREQ3 */ -#define R367TER_CRL_FREQ3 0xf0a2 -#define F367TER_CRL_FOFFSET_VHI 0xf0a200ff - -/* TPS_SFRAME_CTL */ -#define R367TER_TPS_SFRAME_CTL 0xf0a3 -#define F367TER_TPS_SFRAME_SYNC 0xf0a30001 - -/* CHC_SNR */ -#define R367TER_CHC_SNR 0xf0a4 -#define F367TER_CHCSNR 0xf0a400ff - -/* BDI_CTL */ -#define R367TER_BDI_CTL 0xf0a5 -#define F367TER_BDI_LPSEL 0xf0a50002 -#define F367TER_BDI_SERIAL 0xf0a50001 - -/* DMP_CTL */ -#define R367TER_DMP_CTL 0xf0a6 -#define F367TER_DMP_SCALING_FACTOR 0xf0a6001e -#define F367TER_DMP_SDDIS 0xf0a60001 - -/* TPS_RCVD1 */ -#define R367TER_TPS_RCVD1 0xf0a7 -#define F367TER_TPS_CHANGE 0xf0a70040 -#define F367TER_BCH_OK 0xf0a70020 -#define F367TER_TPS_SYNC 0xf0a70010 -#define F367TER_TPS_FRAME 0xf0a70003 - -/* TPS_RCVD2 */ -#define R367TER_TPS_RCVD2 0xf0a8 -#define F367TER_TPS_HIERMODE 0xf0a80070 -#define F367TER_TPS_CONST 0xf0a80003 - -/* TPS_RCVD3 */ -#define R367TER_TPS_RCVD3 0xf0a9 -#define F367TER_TPS_LPCODE 0xf0a90070 -#define F367TER_TPS_HPCODE 0xf0a90007 - -/* TPS_RCVD4 */ -#define R367TER_TPS_RCVD4 0xf0aa -#define F367TER_TPS_GUARD 0xf0aa0030 -#define F367TER_TPS_MODE 0xf0aa0003 - -/* TPS_ID_CELL1 */ -#define R367TER_TPS_ID_CELL1 0xf0ab -#define F367TER_TPS_ID_CELL_LO 0xf0ab00ff - -/* TPS_ID_CELL2 */ -#define R367TER_TPS_ID_CELL2 0xf0ac -#define F367TER_TPS_ID_CELL_HI 0xf0ac00ff - -/* TPS_RCVD5_SET1 */ -#define R367TER_TPS_RCVD5_SET1 0xf0ad -#define F367TER_TPS_NA 0xf0ad00fC -#define F367TER_TPS_SETFRAME 0xf0ad0003 - -/* TPS_SET2 */ -#define R367TER_TPS_SET2 0xf0ae -#define F367TER_TPS_SETHIERMODE 0xf0ae0070 -#define F367TER_TPS_SETCONST 0xf0ae0003 - -/* TPS_SET3 */ -#define R367TER_TPS_SET3 0xf0af -#define F367TER_TPS_SETLPCODE 0xf0af0070 -#define F367TER_TPS_SETHPCODE 0xf0af0007 - -/* TPS_CTL */ -#define R367TER_TPS_CTL 0xf0b0 -#define F367TER_TPS_IMM 0xf0b00004 -#define F367TER_TPS_BCHDIS 0xf0b00002 -#define F367TER_TPS_UPDDIS 0xf0b00001 - -/* CTL_FFTOSNUM */ -#define R367TER_CTL_FFTOSNUM 0xf0b1 -#define F367TER_SYMBOL_NUMBER 0xf0b1007f - -/* TESTSELECT */ -#define R367TER_TESTSELECT 0xf0b2 -#define F367TER_TEST_SELECT 0xf0b2001f - -/* MSC_REV */ -#define R367TER_MSC_REV 0xf0b3 -#define F367TER_REV_NUMBER 0xf0b300ff - -/* PIR_CTL */ -#define R367TER_PIR_CTL 0xf0b4 -#define F367TER_FREEZE 0xf0b40001 - -/* SNR_CARRIER1 */ -#define R367TER_SNR_CARRIER1 0xf0b5 -#define F367TER_SNR_CARRIER_LO 0xf0b500ff - -/* SNR_CARRIER2 */ -#define R367TER_SNR_CARRIER2 0xf0b6 -#define F367TER_MEAN 0xf0b600c0 -#define F367TER_SNR_CARRIER_HI 0xf0b6001f - -/* PPM_CPAMP */ -#define R367TER_PPM_CPAMP 0xf0b7 -#define F367TER_PPM_CPC 0xf0b700ff - -/* TSM_AP0 */ -#define R367TER_TSM_AP0 0xf0b8 -#define F367TER_ADDRESS_BYTE_0 0xf0b800ff - -/* TSM_AP1 */ -#define R367TER_TSM_AP1 0xf0b9 -#define F367TER_ADDRESS_BYTE_1 0xf0b900ff - -/* TSM_AP2 */ -#define R367TER_TSM_AP2 0xf0bA -#define F367TER_DATA_BYTE_0 0xf0ba00ff - -/* TSM_AP3 */ -#define R367TER_TSM_AP3 0xf0bB -#define F367TER_DATA_BYTE_1 0xf0bb00ff - -/* TSM_AP4 */ -#define R367TER_TSM_AP4 0xf0bC -#define F367TER_DATA_BYTE_2 0xf0bc00ff - -/* TSM_AP5 */ -#define R367TER_TSM_AP5 0xf0bD -#define F367TER_DATA_BYTE_3 0xf0bd00ff - -/* TSM_AP6 */ -#define R367TER_TSM_AP6 0xf0bE -#define F367TER_TSM_AP_6 0xf0be00ff - -/* TSM_AP7 */ -#define R367TER_TSM_AP7 0xf0bF -#define F367TER_MEM_SELECT_BYTE 0xf0bf00ff - -/* TSTRES */ -#define R367TER_TSTRES 0xf0c0 -#define F367TER_FRES_DISPLAY 0xf0c00080 -#define F367TER_FRES_FIFO_AD 0xf0c00020 -#define F367TER_FRESRS 0xf0c00010 -#define F367TER_FRESACS 0xf0c00008 -#define F367TER_FRESFEC 0xf0c00004 -#define F367TER_FRES_PRIF 0xf0c00002 -#define F367TER_FRESCORE 0xf0c00001 - -/* ANACTRL */ -#define R367TER_ANACTRL 0xf0c1 -#define F367TER_BYPASS_XTAL 0xf0c10040 -#define F367TER_BYPASS_PLLXN 0xf0c1000c -#define F367TER_DIS_PAD_OSC 0xf0c10002 -#define F367TER_STDBY_PLLXN 0xf0c10001 - -/* TSTBUS */ -#define R367TER_TSTBUS 0xf0c2 -#define F367TER_TS_BYTE_CLK_INV 0xf0c20080 -#define F367TER_CFG_IP 0xf0c20070 -#define F367TER_CFG_TST 0xf0c2000f - -/* TSTRATE */ -#define R367TER_TSTRATE 0xf0c6 -#define F367TER_FORCEPHA 0xf0c60080 -#define F367TER_FNEWPHA 0xf0c60010 -#define F367TER_FROT90 0xf0c60008 -#define F367TER_FR 0xf0c60007 - -/* CONSTMODE */ -#define R367TER_CONSTMODE 0xf0cb -#define F367TER_TST_PRIF 0xf0cb00e0 -#define F367TER_CAR_TYPE 0xf0cb0018 -#define F367TER_CONST_MODE 0xf0cb0003 - -/* CONSTCARR1 */ -#define R367TER_CONSTCARR1 0xf0cc -#define F367TER_CONST_CARR_LO 0xf0cc00ff - -/* CONSTCARR2 */ -#define R367TER_CONSTCARR2 0xf0cd -#define F367TER_CONST_CARR_HI 0xf0cd001f - -/* ICONSTEL */ -#define R367TER_ICONSTEL 0xf0ce -#define F367TER_PICONSTEL 0xf0ce00ff - -/* QCONSTEL */ -#define R367TER_QCONSTEL 0xf0cf -#define F367TER_PQCONSTEL 0xf0cf00ff - -/* TSTBISTRES0 */ -#define R367TER_TSTBISTRES0 0xf0d0 -#define F367TER_BEND_PPM 0xf0d00080 -#define F367TER_BBAD_PPM 0xf0d00040 -#define F367TER_BEND_FFTW 0xf0d00020 -#define F367TER_BBAD_FFTW 0xf0d00010 -#define F367TER_BEND_FFT_BUF 0xf0d00008 -#define F367TER_BBAD_FFT_BUF 0xf0d00004 -#define F367TER_BEND_SYR 0xf0d00002 -#define F367TER_BBAD_SYR 0xf0d00001 - -/* TSTBISTRES1 */ -#define R367TER_TSTBISTRES1 0xf0d1 -#define F367TER_BEND_CHC_CP 0xf0d10080 -#define F367TER_BBAD_CHC_CP 0xf0d10040 -#define F367TER_BEND_CHCI 0xf0d10020 -#define F367TER_BBAD_CHCI 0xf0d10010 -#define F367TER_BEND_BDI 0xf0d10008 -#define F367TER_BBAD_BDI 0xf0d10004 -#define F367TER_BEND_SDI 0xf0d10002 -#define F367TER_BBAD_SDI 0xf0d10001 - -/* TSTBISTRES2 */ -#define R367TER_TSTBISTRES2 0xf0d2 -#define F367TER_BEND_CHC_INC 0xf0d20080 -#define F367TER_BBAD_CHC_INC 0xf0d20040 -#define F367TER_BEND_CHC_SPP 0xf0d20020 -#define F367TER_BBAD_CHC_SPP 0xf0d20010 -#define F367TER_BEND_CHC_CPP 0xf0d20008 -#define F367TER_BBAD_CHC_CPP 0xf0d20004 -#define F367TER_BEND_CHC_SP 0xf0d20002 -#define F367TER_BBAD_CHC_SP 0xf0d20001 - -/* TSTBISTRES3 */ -#define R367TER_TSTBISTRES3 0xf0d3 -#define F367TER_BEND_QAM 0xf0d30080 -#define F367TER_BBAD_QAM 0xf0d30040 -#define F367TER_BEND_SFEC_VIT 0xf0d30020 -#define F367TER_BBAD_SFEC_VIT 0xf0d30010 -#define F367TER_BEND_SFEC_DLINE 0xf0d30008 -#define F367TER_BBAD_SFEC_DLINE 0xf0d30004 -#define F367TER_BEND_SFEC_HW 0xf0d30002 -#define F367TER_BBAD_SFEC_HW 0xf0d30001 - -/* RF_AGC1 */ -#define R367TER_RF_AGC1 0xf0d4 -#define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff - -/* RF_AGC2 */ -#define R367TER_RF_AGC2 0xf0d5 -#define F367TER_REF_ADGP 0xf0d50080 -#define F367TER_STDBY_ADCGP 0xf0d50020 -#define F367TER_CHANNEL_SEL 0xf0d5001c -#define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003 - -/* ANADIGCTRL */ -#define R367TER_ANADIGCTRL 0xf0d7 -#define F367TER_SEL_CLKDEM 0xf0d70020 -#define F367TER_EN_BUFFER_Q 0xf0d70010 -#define F367TER_EN_BUFFER_I 0xf0d70008 -#define F367TER_ADC_RIS_EGDE 0xf0d70004 -#define F367TER_SGN_ADC 0xf0d70002 -#define F367TER_SEL_AD12_SYNC 0xf0d70001 - -/* PLLMDIV */ -#define R367TER_PLLMDIV 0xf0d8 -#define F367TER_PLL_MDIV 0xf0d800ff - -/* PLLNDIV */ -#define R367TER_PLLNDIV 0xf0d9 -#define F367TER_PLL_NDIV 0xf0d900ff - -/* PLLSETUP */ -#define R367TER_PLLSETUP 0xf0dA -#define F367TER_PLL_PDIV 0xf0da0070 -#define F367TER_PLL_KDIV 0xf0da000f - -/* DUAL_AD12 */ -#define R367TER_DUAL_AD12 0xf0dB -#define F367TER_FS20M 0xf0db0020 -#define F367TER_FS50M 0xf0db0010 -#define F367TER_INMODe0 0xf0db0008 -#define F367TER_POFFQ 0xf0db0004 -#define F367TER_POFFI 0xf0db0002 -#define F367TER_INMODE1 0xf0db0001 - -/* TSTBIST */ -#define R367TER_TSTBIST 0xf0dC -#define F367TER_TST_BYP_CLK 0xf0dc0080 -#define F367TER_TST_GCLKENA_STD 0xf0dc0040 -#define F367TER_TST_GCLKENA 0xf0dc0020 -#define F367TER_TST_MEMBIST 0xf0dc001f - -/* PAD_COMP_CTRL */ -#define R367TER_PAD_COMP_CTRL 0xf0dD -#define F367TER_COMPTQ 0xf0dd0010 -#define F367TER_COMPEN 0xf0dd0008 -#define F367TER_FREEZE2 0xf0dd0004 -#define F367TER_SLEEP_INHBT 0xf0dd0002 -#define F367TER_CHIP_SLEEP 0xf0dd0001 - -/* PAD_COMP_WR */ -#define R367TER_PAD_COMP_WR 0xf0de -#define F367TER_WR_ASRC 0xf0de007f - -/* PAD_COMP_RD */ -#define R367TER_PAD_COMP_RD 0xf0df -#define F367TER_COMPOK 0xf0df0080 -#define F367TER_RD_ASRC 0xf0df007f - -/* SYR_TARGET_FFTADJT_MSB */ -#define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100 -#define F367TER_SYR_START 0xf1000080 -#define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f - -/* SYR_TARGET_FFTADJT_LSB */ -#define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101 -#define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff - -/* SYR_TARGET_CHCADJT_MSB */ -#define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102 -#define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f - -/* SYR_TARGET_CHCADJT_LSB */ -#define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103 -#define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff - -/* SYR_FLAG */ -#define R367TER_SYR_FLAG 0xf104 -#define F367TER_TRIG_FLG1 0xf1040080 -#define F367TER_TRIG_FLG0 0xf1040040 -#define F367TER_FFT_FLG1 0xf1040008 -#define F367TER_FFT_FLG0 0xf1040004 -#define F367TER_CHC_FLG1 0xf1040002 -#define F367TER_CHC_FLG0 0xf1040001 - -/* CRL_TARGET1 */ -#define R367TER_CRL_TARGET1 0xf105 -#define F367TER_CRL_START 0xf1050080 -#define F367TER_CRL_TARGET_VHI 0xf105000f - -/* CRL_TARGET2 */ -#define R367TER_CRL_TARGET2 0xf106 -#define F367TER_CRL_TARGET_HI 0xf10600ff - -/* CRL_TARGET3 */ -#define R367TER_CRL_TARGET3 0xf107 -#define F367TER_CRL_TARGET_LO 0xf10700ff - -/* CRL_TARGET4 */ -#define R367TER_CRL_TARGET4 0xf108 -#define F367TER_CRL_TARGET_VLO 0xf10800ff - -/* CRL_FLAG */ -#define R367TER_CRL_FLAG 0xf109 -#define F367TER_CRL_FLAG1 0xf1090002 -#define F367TER_CRL_FLAG0 0xf1090001 - -/* TRL_TARGET1 */ -#define R367TER_TRL_TARGET1 0xf10a -#define F367TER_TRL_TARGET_HI 0xf10a00ff - -/* TRL_TARGET2 */ -#define R367TER_TRL_TARGET2 0xf10b -#define F367TER_TRL_TARGET_LO 0xf10b00ff - -/* TRL_CHC */ -#define R367TER_TRL_CHC 0xf10c -#define F367TER_TRL_START 0xf10c0080 -#define F367TER_CHC_START 0xf10c0040 -#define F367TER_TRL_FLAG1 0xf10c0002 -#define F367TER_TRL_FLAG0 0xf10c0001 - -/* CHC_SNR_TARG */ -#define R367TER_CHC_SNR_TARG 0xf10d -#define F367TER_CHC_SNR_TARGET 0xf10d00ff - -/* TOP_TRACK */ -#define R367TER_TOP_TRACK 0xf10e -#define F367TER_TOP_START 0xf10e0080 -#define F367TER_FIRST_FLAG 0xf10e0070 -#define F367TER_TOP_FLAG1 0xf10e0008 -#define F367TER_TOP_FLAG0 0xf10e0004 -#define F367TER_CHC_FLAG1 0xf10e0002 -#define F367TER_CHC_FLAG0 0xf10e0001 - -/* TRACKER_FREE1 */ -#define R367TER_TRACKER_FREE1 0xf10f -#define F367TER_TRACKER_FREE_1 0xf10f00ff - -/* ERROR_CRL1 */ -#define R367TER_ERROR_CRL1 0xf110 -#define F367TER_ERROR_CRL_VHI 0xf11000ff - -/* ERROR_CRL2 */ -#define R367TER_ERROR_CRL2 0xf111 -#define F367TER_ERROR_CRL_HI 0xf11100ff - -/* ERROR_CRL3 */ -#define R367TER_ERROR_CRL3 0xf112 -#define F367TER_ERROR_CRL_LOI 0xf11200ff - -/* ERROR_CRL4 */ -#define R367TER_ERROR_CRL4 0xf113 -#define F367TER_ERROR_CRL_VLO 0xf11300ff - -/* DEC_NCO1 */ -#define R367TER_DEC_NCO1 0xf114 -#define F367TER_DEC_NCO_VHI 0xf11400ff - -/* DEC_NCO2 */ -#define R367TER_DEC_NCO2 0xf115 -#define F367TER_DEC_NCO_HI 0xf11500ff - -/* DEC_NCO3 */ -#define R367TER_DEC_NCO3 0xf116 -#define F367TER_DEC_NCO_LO 0xf11600ff - -/* SNR */ -#define R367TER_SNR 0xf117 -#define F367TER_SNRATIO 0xf11700ff - -/* SYR_FFTADJ1 */ -#define R367TER_SYR_FFTADJ1 0xf118 -#define F367TER_SYR_FFTADJ_HI 0xf11800ff - -/* SYR_FFTADJ2 */ -#define R367TER_SYR_FFTADJ2 0xf119 -#define F367TER_SYR_FFTADJ_LO 0xf11900ff - -/* SYR_CHCADJ1 */ -#define R367TER_SYR_CHCADJ1 0xf11a -#define F367TER_SYR_CHCADJ_HI 0xf11a00ff - -/* SYR_CHCADJ2 */ -#define R367TER_SYR_CHCADJ2 0xf11b -#define F367TER_SYR_CHCADJ_LO 0xf11b00ff - -/* SYR_OFF */ -#define R367TER_SYR_OFF 0xf11c -#define F367TER_SYR_OFFSET 0xf11c00ff - -/* PPM_OFFSET1 */ -#define R367TER_PPM_OFFSET1 0xf11d -#define F367TER_PPM_OFFSET_HI 0xf11d00ff - -/* PPM_OFFSET2 */ -#define R367TER_PPM_OFFSET2 0xf11e -#define F367TER_PPM_OFFSET_LO 0xf11e00ff - -/* TRACKER_FREE2 */ -#define R367TER_TRACKER_FREE2 0xf11f -#define F367TER_TRACKER_FREE_2 0xf11f00ff - -/* DEBG_LT10 */ -#define R367TER_DEBG_LT10 0xf120 -#define F367TER_DEBUG_LT10 0xf12000ff - -/* DEBG_LT11 */ -#define R367TER_DEBG_LT11 0xf121 -#define F367TER_DEBUG_LT11 0xf12100ff - -/* DEBG_LT12 */ -#define R367TER_DEBG_LT12 0xf122 -#define F367TER_DEBUG_LT12 0xf12200ff - -/* DEBG_LT13 */ -#define R367TER_DEBG_LT13 0xf123 -#define F367TER_DEBUG_LT13 0xf12300ff - -/* DEBG_LT14 */ -#define R367TER_DEBG_LT14 0xf124 -#define F367TER_DEBUG_LT14 0xf12400ff - -/* DEBG_LT15 */ -#define R367TER_DEBG_LT15 0xf125 -#define F367TER_DEBUG_LT15 0xf12500ff - -/* DEBG_LT16 */ -#define R367TER_DEBG_LT16 0xf126 -#define F367TER_DEBUG_LT16 0xf12600ff - -/* DEBG_LT17 */ -#define R367TER_DEBG_LT17 0xf127 -#define F367TER_DEBUG_LT17 0xf12700ff - -/* DEBG_LT18 */ -#define R367TER_DEBG_LT18 0xf128 -#define F367TER_DEBUG_LT18 0xf12800ff - -/* DEBG_LT19 */ -#define R367TER_DEBG_LT19 0xf129 -#define F367TER_DEBUG_LT19 0xf12900ff - -/* DEBG_LT1a */ -#define R367TER_DEBG_LT1A 0xf12a -#define F367TER_DEBUG_LT1A 0xf12a00ff - -/* DEBG_LT1b */ -#define R367TER_DEBG_LT1B 0xf12b -#define F367TER_DEBUG_LT1B 0xf12b00ff - -/* DEBG_LT1c */ -#define R367TER_DEBG_LT1C 0xf12c -#define F367TER_DEBUG_LT1C 0xf12c00ff - -/* DEBG_LT1D */ -#define R367TER_DEBG_LT1D 0xf12d -#define F367TER_DEBUG_LT1D 0xf12d00ff - -/* DEBG_LT1E */ -#define R367TER_DEBG_LT1E 0xf12e -#define F367TER_DEBUG_LT1E 0xf12e00ff - -/* DEBG_LT1F */ -#define R367TER_DEBG_LT1F 0xf12f -#define F367TER_DEBUG_LT1F 0xf12f00ff - -/* RCCFGH */ -#define R367TER_RCCFGH 0xf200 -#define F367TER_TSRCFIFO_DVBCI 0xf2000080 -#define F367TER_TSRCFIFO_SERIAL 0xf2000040 -#define F367TER_TSRCFIFO_DISABLE 0xf2000020 -#define F367TER_TSFIFO_2TORC 0xf2000010 -#define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008 -#define F367TER_TSRCFIFO_ERRMODE 0xf2000006 -#define F367TER_RCCFGH_0 0xf2000001 - -/* RCCFGM */ -#define R367TER_RCCFGM 0xf201 -#define F367TER_TSRCFIFO_MANSPEED 0xf20100c0 -#define F367TER_TSRCFIFO_PERMDATA 0xf2010020 -#define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010 -#define F367TER_RCBYTE_OVERSAMPLING 0xf201000e -#define F367TER_TSRCFIFO_INVDATA 0xf2010001 - -/* RCCFGL */ -#define R367TER_RCCFGL 0xf202 -#define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0 -#define F367TER_RCCFGL_5 0xf2020020 -#define F367TER_TSRCFIFO_DUTY50 0xf2020010 -#define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008 -#define F367TER_TSRCFIFO_DISSERMUX 0xf2020004 -#define F367TER_RCCFGL_1 0xf2020002 -#define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001 - -/* RCINSDELH */ -#define R367TER_RCINSDELH 0xf203 -#define F367TER_TSRCDEL_SYNCBYTE 0xf2030080 -#define F367TER_TSRCDEL_XXHEADER 0xf2030040 -#define F367TER_TSRCDEL_BBHEADER 0xf2030020 -#define F367TER_TSRCDEL_DATAFIELD 0xf2030010 -#define F367TER_TSRCINSDEL_ISCR 0xf2030008 -#define F367TER_TSRCINSDEL_NPD 0xf2030004 -#define F367TER_TSRCINSDEL_RSPARITY 0xf2030002 -#define F367TER_TSRCINSDEL_CRC8 0xf2030001 - -/* RCINSDELM */ -#define R367TER_RCINSDELM 0xf204 -#define F367TER_TSRCINS_BBPADDING 0xf2040080 -#define F367TER_TSRCINS_BCHFEC 0xf2040040 -#define F367TER_TSRCINS_LDPCFEC 0xf2040020 -#define F367TER_TSRCINS_EMODCOD 0xf2040010 -#define F367TER_TSRCINS_TOKEN 0xf2040008 -#define F367TER_TSRCINS_XXXERR 0xf2040004 -#define F367TER_TSRCINS_MATYPE 0xf2040002 -#define F367TER_TSRCINS_UPL 0xf2040001 - -/* RCINSDELL */ -#define R367TER_RCINSDELL 0xf205 -#define F367TER_TSRCINS_DFL 0xf2050080 -#define F367TER_TSRCINS_SYNCD 0xf2050040 -#define F367TER_TSRCINS_BLOCLEN 0xf2050020 -#define F367TER_TSRCINS_SIGPCOUNT 0xf2050010 -#define F367TER_TSRCINS_FIFO 0xf2050008 -#define F367TER_TSRCINS_REALPACK 0xf2050004 -#define F367TER_TSRCINS_TSCONFIG 0xf2050002 -#define F367TER_TSRCINS_LATENCY 0xf2050001 - -/* RCSTATUS */ -#define R367TER_RCSTATUS 0xf206 -#define F367TER_TSRCFIFO_LINEOK 0xf2060080 -#define F367TER_TSRCFIFO_ERROR 0xf2060040 -#define F367TER_TSRCFIFO_DATA7 0xf2060020 -#define F367TER_RCSTATUS_4 0xf2060010 -#define F367TER_TSRCFIFO_DEMODSEL 0xf2060008 -#define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004 -#define F367TER_RCSTATUS_1 0xf2060002 -#define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001 - -/* RCSPEED */ -#define R367TER_RCSPEED 0xf207 -#define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff - -/* RCDEBUGM */ -#define R367TER_RCDEBUGM 0xf208 -#define F367TER_SD_UNSYNC 0xf2080080 -#define F367TER_ULFLOCK_DETECTM 0xf2080040 -#define F367TER_SUL_SELECTOS 0xf2080020 -#define F367TER_DILUL_NOSCRBLE 0xf2080010 -#define F367TER_NUL_SCRB 0xf2080008 -#define F367TER_UL_SCRB 0xf2080004 -#define F367TER_SCRAULBAD 0xf2080002 -#define F367TER_SCRAUL_UNSYNC 0xf2080001 - -/* RCDEBUGL */ -#define R367TER_RCDEBUGL 0xf209 -#define F367TER_RS_ERR 0xf2090080 -#define F367TER_LLFLOCK_DETECTM 0xf2090040 -#define F367TER_NOT_SUL_SELECTOS 0xf2090020 -#define F367TER_DILLL_NOSCRBLE 0xf2090010 -#define F367TER_NLL_SCRB 0xf2090008 -#define F367TER_LL_SCRB 0xf2090004 -#define F367TER_SCRALLBAD 0xf2090002 -#define F367TER_SCRALL_UNSYNC 0xf2090001 - -/* RCOBSCFG */ -#define R367TER_RCOBSCFG 0xf20a -#define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff - -/* RCOBSM */ -#define R367TER_RCOBSM 0xf20b -#define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff - -/* RCOBSL */ -#define R367TER_RCOBSL 0xf20c -#define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff - -/* RCFECSPY */ -#define R367TER_RCFECSPY 0xf210 -#define F367TER_SPYRC_ENABLE 0xf2100080 -#define F367TER_RCNO_SYNCBYTE 0xf2100040 -#define F367TER_RCSERIAL_MODE 0xf2100020 -#define F367TER_RCUNUSUAL_PACKET 0xf2100010 -#define F367TER_BERRCMETER_DATAMODE 0xf210000c -#define F367TER_BERRCMETER_LMODE 0xf2100002 -#define F367TER_BERRCMETER_RESET 0xf2100001 - -/* RCFSPYCFG */ -#define R367TER_RCFSPYCFG 0xf211 -#define F367TER_FECSPYRC_INPUT 0xf21100c0 -#define F367TER_RCRST_ON_ERROR 0xf2110020 -#define F367TER_RCONE_SHOT 0xf2110010 -#define F367TER_RCI2C_MODE 0xf211000c -#define F367TER_SPYRC_HSTERESIS 0xf2110003 - -/* RCFSPYDATA */ -#define R367TER_RCFSPYDATA 0xf212 -#define F367TER_SPYRC_STUFFING 0xf2120080 -#define F367TER_RCNOERR_PKTJITTER 0xf2120040 -#define F367TER_SPYRC_CNULLPKT 0xf2120020 -#define F367TER_SPYRC_OUTDATA_MODE 0xf212001f - -/* RCFSPYOUT */ -#define R367TER_RCFSPYOUT 0xf213 -#define F367TER_FSPYRC_DIRECT 0xf2130080 -#define F367TER_RCFSPYOUT_6 0xf2130040 -#define F367TER_SPYRC_OUTDATA_BUS 0xf2130038 -#define F367TER_RCSTUFF_MODE 0xf2130007 - -/* RCFSTATUS */ -#define R367TER_RCFSTATUS 0xf214 -#define F367TER_SPYRC_ENDSIM 0xf2140080 -#define F367TER_RCVALID_SIM 0xf2140040 -#define F367TER_RCFOUND_SIGNAL 0xf2140020 -#define F367TER_RCDSS_SYNCBYTE 0xf2140010 -#define F367TER_RCRESULT_STATE 0xf214000f - -/* RCFGOODPACK */ -#define R367TER_RCFGOODPACK 0xf215 -#define F367TER_RCGOOD_PACKET 0xf21500ff - -/* RCFPACKCNT */ -#define R367TER_RCFPACKCNT 0xf216 -#define F367TER_RCPACKET_COUNTER 0xf21600ff - -/* RCFSPYMISC */ -#define R367TER_RCFSPYMISC 0xf217 -#define F367TER_RCLABEL_COUNTER 0xf21700ff - -/* RCFBERCPT4 */ -#define R367TER_RCFBERCPT4 0xf218 -#define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff - -/* RCFBERCPT3 */ -#define R367TER_RCFBERCPT3 0xf219 -#define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff - -/* RCFBERCPT2 */ -#define R367TER_RCFBERCPT2 0xf21a -#define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff - -/* RCFBERCPT1 */ -#define R367TER_RCFBERCPT1 0xf21b -#define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff - -/* RCFBERCPT0 */ -#define R367TER_RCFBERCPT0 0xf21c -#define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff - -/* RCFBERERR2 */ -#define R367TER_RCFBERERR2 0xf21d -#define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff - -/* RCFBERERR1 */ -#define R367TER_RCFBERERR1 0xf21e -#define F367TER_FBERRCMETER_ERR 0xf21e00ff - -/* RCFBERERR0 */ -#define R367TER_RCFBERERR0 0xf21f -#define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff - -/* RCFSTATESM */ -#define R367TER_RCFSTATESM 0xf220 -#define F367TER_RCRSTATE_F 0xf2200080 -#define F367TER_RCRSTATE_E 0xf2200040 -#define F367TER_RCRSTATE_D 0xf2200020 -#define F367TER_RCRSTATE_C 0xf2200010 -#define F367TER_RCRSTATE_B 0xf2200008 -#define F367TER_RCRSTATE_A 0xf2200004 -#define F367TER_RCRSTATE_9 0xf2200002 -#define F367TER_RCRSTATE_8 0xf2200001 - -/* RCFSTATESL */ -#define R367TER_RCFSTATESL 0xf221 -#define F367TER_RCRSTATE_7 0xf2210080 -#define F367TER_RCRSTATE_6 0xf2210040 -#define F367TER_RCRSTATE_5 0xf2210020 -#define F367TER_RCRSTATE_4 0xf2210010 -#define F367TER_RCRSTATE_3 0xf2210008 -#define F367TER_RCRSTATE_2 0xf2210004 -#define F367TER_RCRSTATE_1 0xf2210002 -#define F367TER_RCRSTATE_0 0xf2210001 - -/* RCFSPYBER */ -#define R367TER_RCFSPYBER 0xf222 -#define F367TER_RCFSPYBER_7 0xf2220080 -#define F367TER_SPYRCOBS_XORREAD 0xf2220040 -#define F367TER_FSPYRCBER_OBSMODE 0xf2220020 -#define F367TER_FSPYRCBER_SYNCBYT 0xf2220010 -#define F367TER_FSPYRCBER_UNSYNC 0xf2220008 -#define F367TER_FSPYRCBER_CTIME 0xf2220007 - -/* RCFSPYDISTM */ -#define R367TER_RCFSPYDISTM 0xf223 -#define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff - -/* RCFSPYDISTL */ -#define R367TER_RCFSPYDISTL 0xf224 -#define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff - -/* RCFSPYOBS7 */ -#define R367TER_RCFSPYOBS7 0xf228 -#define F367TER_RCSPYOBS_SPYFAIL 0xf2280080 -#define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040 -#define F367TER_RCSPYOBS_ERROR 0xf2280020 -#define F367TER_RCSPYOBS_STROUT 0xf2280010 -#define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f - -/* RCFSPYOBS6 */ -#define R367TER_RCFSPYOBS6 0xf229 -#define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0 -#define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f - -/* RCFSPYOBS5 */ -#define R367TER_RCFSPYOBS5 0xf22a -#define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff - -/* RCFSPYOBS4 */ -#define R367TER_RCFSPYOBS4 0xf22b -#define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff - -/* RCFSPYOBS3 */ -#define R367TER_RCFSPYOBS3 0xf22c -#define F367TER_RCSPYOBS_DATA1 0xf22c00ff - -/* RCFSPYOBS2 */ -#define R367TER_RCFSPYOBS2 0xf22d -#define F367TER_RCSPYOBS_DATa0 0xf22d00ff - -/* RCFSPYOBS1 */ -#define R367TER_RCFSPYOBS1 0xf22e -#define F367TER_RCSPYOBS_DATAM1 0xf22e00ff - -/* RCFSPYOBS0 */ -#define R367TER_RCFSPYOBS0 0xf22f -#define F367TER_RCSPYOBS_DATAM2 0xf22f00ff - -/* TSGENERAL */ -#define R367TER_TSGENERAL 0xf230 -#define F367TER_TSGENERAL_7 0xf2300080 -#define F367TER_TSGENERAL_6 0xf2300040 -#define F367TER_TSFIFO_BCLK1aLL 0xf2300020 -#define F367TER_TSGENERAL_4 0xf2300010 -#define F367TER_MUXSTREAM_OUTMODE 0xf2300008 -#define F367TER_TSFIFO_PERMPARAL 0xf2300006 -#define F367TER_RST_REEDSOLO 0xf2300001 - -/* RC1SPEED */ -#define R367TER_RC1SPEED 0xf231 -#define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff - -/* TSGSTATUS */ -#define R367TER_TSGSTATUS 0xf232 -#define F367TER_TSGSTATUS_7 0xf2320080 -#define F367TER_TSGSTATUS_6 0xf2320040 -#define F367TER_RSMEM_FULL 0xf2320020 -#define F367TER_RS_MULTCALC 0xf2320010 -#define F367TER_RSIN_OVERTIME 0xf2320008 -#define F367TER_TSFIFO3_DEMODSEL 0xf2320004 -#define F367TER_TSFIFO2_DEMODSEL 0xf2320002 -#define F367TER_TSFIFO1_DEMODSEL 0xf2320001 - - -/* FECM */ -#define R367TER_FECM 0xf233 -#define F367TER_DSS_DVB 0xf2330080 -#define F367TER_DEMOD_BYPASS 0xf2330040 -#define F367TER_CMP_SLOWMODE 0xf2330020 -#define F367TER_DSS_SRCH 0xf2330010 -#define F367TER_FECM_3 0xf2330008 -#define F367TER_DIFF_MODEVIT 0xf2330004 -#define F367TER_SYNCVIT 0xf2330002 -#define F367TER_I2CSYM 0xf2330001 - -/* VTH12 */ -#define R367TER_VTH12 0xf234 -#define F367TER_VTH_12 0xf23400ff - -/* VTH23 */ -#define R367TER_VTH23 0xf235 -#define F367TER_VTH_23 0xf23500ff - -/* VTH34 */ -#define R367TER_VTH34 0xf236 -#define F367TER_VTH_34 0xf23600ff - -/* VTH56 */ -#define R367TER_VTH56 0xf237 -#define F367TER_VTH_56 0xf23700ff - -/* VTH67 */ -#define R367TER_VTH67 0xf238 -#define F367TER_VTH_67 0xf23800ff - -/* VTH78 */ -#define R367TER_VTH78 0xf239 -#define F367TER_VTH_78 0xf23900ff - -/* VITCURPUN */ -#define R367TER_VITCURPUN 0xf23a -#define F367TER_VIT_MAPPING 0xf23a00e0 -#define F367TER_VIT_CURPUN 0xf23a001f - -/* VERROR */ -#define R367TER_VERROR 0xf23b -#define F367TER_REGERR_VIT 0xf23b00ff - -/* PRVIT */ -#define R367TER_PRVIT 0xf23c -#define F367TER_PRVIT_7 0xf23c0080 -#define F367TER_DIS_VTHLOCK 0xf23c0040 -#define F367TER_E7_8VIT 0xf23c0020 -#define F367TER_E6_7VIT 0xf23c0010 -#define F367TER_E5_6VIT 0xf23c0008 -#define F367TER_E3_4VIT 0xf23c0004 -#define F367TER_E2_3VIT 0xf23c0002 -#define F367TER_E1_2VIT 0xf23c0001 - -/* VAVSRVIT */ -#define R367TER_VAVSRVIT 0xf23d -#define F367TER_AMVIT 0xf23d0080 -#define F367TER_FROZENVIT 0xf23d0040 -#define F367TER_SNVIT 0xf23d0030 -#define F367TER_TOVVIT 0xf23d000c -#define F367TER_HYPVIT 0xf23d0003 - -/* VSTATUSVIT */ -#define R367TER_VSTATUSVIT 0xf23e -#define F367TER_VITERBI_ON 0xf23e0080 -#define F367TER_END_LOOPVIT 0xf23e0040 -#define F367TER_VITERBI_DEPRF 0xf23e0020 -#define F367TER_PRFVIT 0xf23e0010 -#define F367TER_LOCKEDVIT 0xf23e0008 -#define F367TER_VITERBI_DELOCK 0xf23e0004 -#define F367TER_VIT_DEMODSEL 0xf23e0002 -#define F367TER_VITERBI_COMPOUT 0xf23e0001 - -/* VTHINUSE */ -#define R367TER_VTHINUSE 0xf23f -#define F367TER_VIT_INUSE 0xf23f00ff - -/* KDIV12 */ -#define R367TER_KDIV12 0xf240 -#define F367TER_KDIV12_MANUAL 0xf2400080 -#define F367TER_K_DIVIDER_12 0xf240007f - -/* KDIV23 */ -#define R367TER_KDIV23 0xf241 -#define F367TER_KDIV23_MANUAL 0xf2410080 -#define F367TER_K_DIVIDER_23 0xf241007f - -/* KDIV34 */ -#define R367TER_KDIV34 0xf242 -#define F367TER_KDIV34_MANUAL 0xf2420080 -#define F367TER_K_DIVIDER_34 0xf242007f - -/* KDIV56 */ -#define R367TER_KDIV56 0xf243 -#define F367TER_KDIV56_MANUAL 0xf2430080 -#define F367TER_K_DIVIDER_56 0xf243007f - -/* KDIV67 */ -#define R367TER_KDIV67 0xf244 -#define F367TER_KDIV67_MANUAL 0xf2440080 -#define F367TER_K_DIVIDER_67 0xf244007f - -/* KDIV78 */ -#define R367TER_KDIV78 0xf245 -#define F367TER_KDIV78_MANUAL 0xf2450080 -#define F367TER_K_DIVIDER_78 0xf245007f - -/* SIGPOWER */ -#define R367TER_SIGPOWER 0xf246 -#define F367TER_SIGPOWER_MANUAL 0xf2460080 -#define F367TER_SIG_POWER 0xf246007f - -/* DEMAPVIT */ -#define R367TER_DEMAPVIT 0xf247 -#define F367TER_DEMAPVIT_7 0xf2470080 -#define F367TER_K_DIVIDER_VIT 0xf247007f - -/* VITSCALE */ -#define R367TER_VITSCALE 0xf248 -#define F367TER_NVTH_NOSRANGE 0xf2480080 -#define F367TER_VERROR_MAXMODE 0xf2480040 -#define F367TER_KDIV_MODE 0xf2480030 -#define F367TER_NSLOWSN_LOCKED 0xf2480008 -#define F367TER_DELOCK_PRFLOSS 0xf2480004 -#define F367TER_DIS_RSFLOCK 0xf2480002 -#define F367TER_VITSCALE_0 0xf2480001 - -/* FFEC1PRG */ -#define R367TER_FFEC1PRG 0xf249 -#define F367TER_FDSS_DVB 0xf2490080 -#define F367TER_FDSS_SRCH 0xf2490040 -#define F367TER_FFECPROG_5 0xf2490020 -#define F367TER_FFECPROG_4 0xf2490010 -#define F367TER_FFECPROG_3 0xf2490008 -#define F367TER_FFECPROG_2 0xf2490004 -#define F367TER_FTS1_DISABLE 0xf2490002 -#define F367TER_FTS2_DISABLE 0xf2490001 - -/* FVITCURPUN */ -#define R367TER_FVITCURPUN 0xf24a -#define F367TER_FVIT_MAPPING 0xf24a00e0 -#define F367TER_FVIT_CURPUN 0xf24a001f - -/* FVERROR */ -#define R367TER_FVERROR 0xf24b -#define F367TER_FREGERR_VIT 0xf24b00ff - -/* FVSTATUSVIT */ -#define R367TER_FVSTATUSVIT 0xf24c -#define F367TER_FVITERBI_ON 0xf24c0080 -#define F367TER_F1END_LOOPVIT 0xf24c0040 -#define F367TER_FVITERBI_DEPRF 0xf24c0020 -#define F367TER_FPRFVIT 0xf24c0010 -#define F367TER_FLOCKEDVIT 0xf24c0008 -#define F367TER_FVITERBI_DELOCK 0xf24c0004 -#define F367TER_FVIT_DEMODSEL 0xf24c0002 -#define F367TER_FVITERBI_COMPOUT 0xf24c0001 - -/* DEBUG_LT1 */ -#define R367TER_DEBUG_LT1 0xf24d -#define F367TER_DBG_LT1 0xf24d00ff - -/* DEBUG_LT2 */ -#define R367TER_DEBUG_LT2 0xf24e -#define F367TER_DBG_LT2 0xf24e00ff - -/* DEBUG_LT3 */ -#define R367TER_DEBUG_LT3 0xf24f -#define F367TER_DBG_LT3 0xf24f00ff - -/* TSTSFMET */ -#define R367TER_TSTSFMET 0xf250 -#define F367TER_TSTSFEC_METRIQUES 0xf25000ff - -/* SELOUT */ -#define R367TER_SELOUT 0xf252 -#define F367TER_EN_SYNC 0xf2520080 -#define F367TER_EN_TBUSDEMAP 0xf2520040 -#define F367TER_SELOUT_5 0xf2520020 -#define F367TER_SELOUT_4 0xf2520010 -#define F367TER_TSTSYNCHRO_MODE 0xf2520002 - -/* TSYNC */ -#define R367TER_TSYNC 0xf253 -#define F367TER_CURPUN_INCMODE 0xf2530080 -#define F367TER_CERR_TSTMODE 0xf2530040 -#define F367TER_SHIFTSOF_MODE 0xf2530030 -#define F367TER_SLOWPHA_MODE 0xf2530008 -#define F367TER_PXX_BYPALL 0xf2530004 -#define F367TER_FROTA45_FIRST 0xf2530002 -#define F367TER_TST_BCHERROR 0xf2530001 - -/* TSTERR */ -#define R367TER_TSTERR 0xf254 -#define F367TER_TST_LONGPKT 0xf2540080 -#define F367TER_TST_ISSYION 0xf2540040 -#define F367TER_TST_NPDON 0xf2540020 -#define F367TER_TSTERR_4 0xf2540010 -#define F367TER_TRACEBACK_MODE 0xf2540008 -#define F367TER_TST_RSPARITY 0xf2540004 -#define F367TER_METRIQUE_MODE 0xf2540003 - -/* TSFSYNC */ -#define R367TER_TSFSYNC 0xf255 -#define F367TER_EN_SFECSYNC 0xf2550080 -#define F367TER_EN_SFECDEMAP 0xf2550040 -#define F367TER_SFCERR_TSTMODE 0xf2550020 -#define F367TER_SFECPXX_BYPALL 0xf2550010 -#define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f - -/* TSTSFERR */ -#define R367TER_TSTSFERR 0xf256 -#define F367TER_TSTSTERR_7 0xf2560080 -#define F367TER_TSTSTERR_6 0xf2560040 -#define F367TER_TSTSTERR_5 0xf2560020 -#define F367TER_TSTSTERR_4 0xf2560010 -#define F367TER_SFECTRACEBACK_MODE 0xf2560008 -#define F367TER_SFEC_NCONVPROG 0xf2560004 -#define F367TER_SFECMETRIQUE_MODE 0xf2560003 - -/* TSTTSSF1 */ -#define R367TER_TSTTSSF1 0xf258 -#define F367TER_TSTERSSF 0xf2580080 -#define F367TER_TSTTSSFEN 0xf2580040 -#define F367TER_SFEC_OUTMODE 0xf2580030 -#define F367TER_XLSF_NOFTHRESHOLD 0xf2580008 -#define F367TER_TSTTSSF_STACKSEL 0xf2580007 - -/* TSTTSSF2 */ -#define R367TER_TSTTSSF2 0xf259 -#define F367TER_DILSF_DBBHEADER 0xf2590080 -#define F367TER_TSTTSSF_DISBUG 0xf2590040 -#define F367TER_TSTTSSF_NOBADSTART 0xf2590020 -#define F367TER_TSTTSSF_SELECT 0xf259001f - -/* TSTTSSF3 */ -#define R367TER_TSTTSSF3 0xf25a -#define F367TER_TSTTSSF3_7 0xf25a0080 -#define F367TER_TSTTSSF3_6 0xf25a0040 -#define F367TER_TSTTSSF3_5 0xf25a0020 -#define F367TER_TSTTSSF3_4 0xf25a0010 -#define F367TER_TSTTSSF3_3 0xf25a0008 -#define F367TER_TSTTSSF3_2 0xf25a0004 -#define F367TER_TSTTSSF3_1 0xf25a0002 -#define F367TER_DISSF_CLKENABLE 0xf25a0001 - -/* TSTTS1 */ -#define R367TER_TSTTS1 0xf25c -#define F367TER_TSTERS 0xf25c0080 -#define F367TER_TSFIFO_DSSSYNCB 0xf25c0040 -#define F367TER_TSTTS_FSPYBEFRS 0xf25c0020 -#define F367TER_NFORCE_SYNCBYTE 0xf25c0010 -#define F367TER_XL_NOFTHRESHOLD 0xf25c0008 -#define F367TER_TSTTS_FRFORCEPKT 0xf25c0004 -#define F367TER_DESCR_NOTAUTO 0xf25c0002 -#define F367TER_TSTTSEN 0xf25c0001 - -/* TSTTS2 */ -#define R367TER_TSTTS2 0xf25d -#define F367TER_DIL_DBBHEADER 0xf25d0080 -#define F367TER_TSTTS_NOBADXXX 0xf25d0040 -#define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020 -#define F367TER_TSTTS_SELECT 0xf25d001f - -/* TSTTS3 */ -#define R367TER_TSTTS3 0xf25e -#define F367TER_TSTTS_NOPKTGAIN 0xf25e0080 -#define F367TER_TSTTS_NOPKTENE 0xf25e0040 -#define F367TER_TSTTS_ISOLATION 0xf25e0020 -#define F367TER_TSTTS_DISBUG 0xf25e0010 -#define F367TER_TSTTS_NOBADSTART 0xf25e0008 -#define F367TER_TSTTS_STACKSEL 0xf25e0007 - -/* TSTTS4 */ -#define R367TER_TSTTS4 0xf25f -#define F367TER_TSTTS4_7 0xf25f0080 -#define F367TER_TSTTS4_6 0xf25f0040 -#define F367TER_TSTTS4_5 0xf25f0020 -#define F367TER_TSTTS_DISDSTATE 0xf25f0010 -#define F367TER_TSTTS_FASTNOSYNC 0xf25f0008 -#define F367TER_EXT_FECSPYIN 0xf25f0004 -#define F367TER_TSTTS_NODPZERO 0xf25f0002 -#define F367TER_TSTTS_NODIV3 0xf25f0001 - -/* TSTTSRC */ -#define R367TER_TSTTSRC 0xf26c -#define F367TER_TSTTSRC_7 0xf26c0080 -#define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040 -#define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020 -#define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010 -#define F367TER_TSTTSRC_NODIV3 0xf26c0008 -#define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004 -#define F367TER_SAT25_SDDORIGINE 0xf26c0002 -#define F367TER_TSTTSRC_INACTIVE 0xf26c0001 - -/* TSTTSRS */ -#define R367TER_TSTTSRS 0xf26d -#define F367TER_TSTTSRS_7 0xf26d0080 -#define F367TER_TSTTSRS_6 0xf26d0040 -#define F367TER_TSTTSRS_5 0xf26d0020 -#define F367TER_TSTTSRS_4 0xf26d0010 -#define F367TER_TSTTSRS_3 0xf26d0008 -#define F367TER_TSTTSRS_2 0xf26d0004 -#define F367TER_TSTRS_DISRS2 0xf26d0002 -#define F367TER_TSTRS_DISRS1 0xf26d0001 - -/* TSSTATEM */ -#define R367TER_TSSTATEM 0xf270 -#define F367TER_TSDIL_ON 0xf2700080 -#define F367TER_TSSKIPRS_ON 0xf2700040 -#define F367TER_TSRS_ON 0xf2700020 -#define F367TER_TSDESCRAMB_ON 0xf2700010 -#define F367TER_TSFRAME_MODE 0xf2700008 -#define F367TER_TS_DISABLE 0xf2700004 -#define F367TER_TSACM_MODE 0xf2700002 -#define F367TER_TSOUT_NOSYNC 0xf2700001 - -/* TSSTATEL */ -#define R367TER_TSSTATEL 0xf271 -#define F367TER_TSNOSYNCBYTE 0xf2710080 -#define F367TER_TSPARITY_ON 0xf2710040 -#define F367TER_TSSYNCOUTRS_ON 0xf2710020 -#define F367TER_TSDVBS2_MODE 0xf2710010 -#define F367TER_TSISSYI_ON 0xf2710008 -#define F367TER_TSNPD_ON 0xf2710004 -#define F367TER_TSCRC8_ON 0xf2710002 -#define F367TER_TSDSS_PACKET 0xf2710001 - -/* TSCFGH */ -#define R367TER_TSCFGH 0xf272 -#define F367TER_TSFIFO_DVBCI 0xf2720080 -#define F367TER_TSFIFO_SERIAL 0xf2720040 -#define F367TER_TSFIFO_TEIUPDATE 0xf2720020 -#define F367TER_TSFIFO_DUTY50 0xf2720010 -#define F367TER_TSFIFO_HSGNLOUT 0xf2720008 -#define F367TER_TSFIFO_ERRMODE 0xf2720006 -#define F367TER_RST_HWARE 0xf2720001 - -/* TSCFGM */ -#define R367TER_TSCFGM 0xf273 -#define F367TER_TSFIFO_MANSPEED 0xf27300c0 -#define F367TER_TSFIFO_PERMDATA 0xf2730020 -#define F367TER_TSFIFO_NONEWSGNL 0xf2730010 -#define F367TER_TSFIFO_BITSPEED 0xf2730008 -#define F367TER_NPD_SPECDVBS2 0xf2730004 -#define F367TER_TSFIFO_STOPCKDIS 0xf2730002 -#define F367TER_TSFIFO_INVDATA 0xf2730001 - -/* TSCFGL */ -#define R367TER_TSCFGL 0xf274 -#define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0 -#define F367TER_BCHERROR_MODE 0xf2740030 -#define F367TER_TSFIFO_NSGNL2dATA 0xf2740008 -#define F367TER_TSFIFO_EMBINDVB 0xf2740004 -#define F367TER_TSFIFO_DPUNACT 0xf2740002 -#define F367TER_TSFIFO_NPDOFF 0xf2740001 - -/* TSSYNC */ -#define R367TER_TSSYNC 0xf275 -#define F367TER_TSFIFO_PERMUTE 0xf2750080 -#define F367TER_TSFIFO_FISCR3B 0xf2750060 -#define F367TER_TSFIFO_SYNCMODE 0xf2750018 -#define F367TER_TSFIFO_SYNCSEL 0xf2750007 - -/* TSINSDELH */ -#define R367TER_TSINSDELH 0xf276 -#define F367TER_TSDEL_SYNCBYTE 0xf2760080 -#define F367TER_TSDEL_XXHEADER 0xf2760040 -#define F367TER_TSDEL_BBHEADER 0xf2760020 -#define F367TER_TSDEL_DATAFIELD 0xf2760010 -#define F367TER_TSINSDEL_ISCR 0xf2760008 -#define F367TER_TSINSDEL_NPD 0xf2760004 -#define F367TER_TSINSDEL_RSPARITY 0xf2760002 -#define F367TER_TSINSDEL_CRC8 0xf2760001 - -/* TSINSDELM */ -#define R367TER_TSINSDELM 0xf277 -#define F367TER_TSINS_BBPADDING 0xf2770080 -#define F367TER_TSINS_BCHFEC 0xf2770040 -#define F367TER_TSINS_LDPCFEC 0xf2770020 -#define F367TER_TSINS_EMODCOD 0xf2770010 -#define F367TER_TSINS_TOKEN 0xf2770008 -#define F367TER_TSINS_XXXERR 0xf2770004 -#define F367TER_TSINS_MATYPE 0xf2770002 -#define F367TER_TSINS_UPL 0xf2770001 - -/* TSINSDELL */ -#define R367TER_TSINSDELL 0xf278 -#define F367TER_TSINS_DFL 0xf2780080 -#define F367TER_TSINS_SYNCD 0xf2780040 -#define F367TER_TSINS_BLOCLEN 0xf2780020 -#define F367TER_TSINS_SIGPCOUNT 0xf2780010 -#define F367TER_TSINS_FIFO 0xf2780008 -#define F367TER_TSINS_REALPACK 0xf2780004 -#define F367TER_TSINS_TSCONFIG 0xf2780002 -#define F367TER_TSINS_LATENCY 0xf2780001 - -/* TSDIVN */ -#define R367TER_TSDIVN 0xf279 -#define F367TER_TSFIFO_LOWSPEED 0xf2790080 -#define F367TER_BYTE_OVERSAMPLING 0xf2790070 -#define F367TER_TSMANUAL_PACKETNBR 0xf279000f - -/* TSDIVPM */ -#define R367TER_TSDIVPM 0xf27a -#define F367TER_TSMANUAL_P_HI 0xf27a00ff - -/* TSDIVPL */ -#define R367TER_TSDIVPL 0xf27b -#define F367TER_TSMANUAL_P_LO 0xf27b00ff - -/* TSDIVQM */ -#define R367TER_TSDIVQM 0xf27c -#define F367TER_TSMANUAL_Q_HI 0xf27c00ff - -/* TSDIVQL */ -#define R367TER_TSDIVQL 0xf27d -#define F367TER_TSMANUAL_Q_LO 0xf27d00ff - -/* TSDILSTKM */ -#define R367TER_TSDILSTKM 0xf27e -#define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff - -/* TSDILSTKL */ -#define R367TER_TSDILSTKL 0xf27f -#define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff - -/* TSSPEED */ -#define R367TER_TSSPEED 0xf280 -#define F367TER_TSFIFO_OUTSPEED 0xf28000ff - -/* TSSTATUS */ -#define R367TER_TSSTATUS 0xf281 -#define F367TER_TSFIFO_LINEOK 0xf2810080 -#define F367TER_TSFIFO_ERROR 0xf2810040 -#define F367TER_TSFIFO_DATA7 0xf2810020 -#define F367TER_TSFIFO_NOSYNC 0xf2810010 -#define F367TER_ISCR_INITIALIZED 0xf2810008 -#define F367TER_ISCR_UPDATED 0xf2810004 -#define F367TER_SOFFIFO_UNREGUL 0xf2810002 -#define F367TER_DIL_READY 0xf2810001 - -/* TSSTATUS2 */ -#define R367TER_TSSTATUS2 0xf282 -#define F367TER_TSFIFO_DEMODSEL 0xf2820080 -#define F367TER_TSFIFOSPEED_STORE 0xf2820040 -#define F367TER_DILXX_RESET 0xf2820020 -#define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010 -#define F367TER_TSFIFO_UNDERSPEED 0xf2820008 -#define F367TER_BITSPEED_EVENT 0xf2820004 -#define F367TER_UL_SCRAMBDETECT 0xf2820002 -#define F367TER_ULDTV67_FALSELOCK 0xf2820001 - -/* TSBITRATEM */ -#define R367TER_TSBITRATEM 0xf283 -#define F367TER_TSFIFO_BITRATE_HI 0xf28300ff - -/* TSBITRATEL */ -#define R367TER_TSBITRATEL 0xf284 -#define F367TER_TSFIFO_BITRATE_LO 0xf28400ff - -/* TSPACKLENM */ -#define R367TER_TSPACKLENM 0xf285 -#define F367TER_TSFIFO_PACKCPT 0xf28500e0 -#define F367TER_DIL_RPLEN_HI 0xf285001f - -/* TSPACKLENL */ -#define R367TER_TSPACKLENL 0xf286 -#define F367TER_DIL_RPLEN_LO 0xf28600ff - -/* TSBLOCLENM */ -#define R367TER_TSBLOCLENM 0xf287 -#define F367TER_TSFIFO_PFLEN_HI 0xf28700ff - -/* TSBLOCLENL */ -#define R367TER_TSBLOCLENL 0xf288 -#define F367TER_TSFIFO_PFLEN_LO 0xf28800ff - -/* TSDLYH */ -#define R367TER_TSDLYH 0xf289 -#define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080 -#define F367TER_SOFFIFO_SPEEDUP 0xf2890040 -#define F367TER_SOFFIFO_STOP 0xf2890020 -#define F367TER_SOFFIFO_REGULATED 0xf2890010 -#define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f - -/* TSDLYM */ -#define R367TER_TSDLYM 0xf28a -#define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff - -/* TSDLYL */ -#define R367TER_TSDLYL 0xf28b -#define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff - -/* TSNPDAV */ -#define R367TER_TSNPDAV 0xf28c -#define F367TER_TSNPD_AVERAGE 0xf28c00ff - -/* TSBUFSTATH */ -#define R367TER_TSBUFSTATH 0xf28d -#define F367TER_TSISCR_3BYTES 0xf28d0080 -#define F367TER_TSISCR_NEWDATA 0xf28d0040 -#define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f - -/* TSBUFSTATM */ -#define R367TER_TSBUFSTATM 0xf28e -#define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff - -/* TSBUFSTATL */ -#define R367TER_TSBUFSTATL 0xf28f -#define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff - -/* TSDEBUGM */ -#define R367TER_TSDEBUGM 0xf290 -#define F367TER_TSFIFO_ILLPACKET 0xf2900080 -#define F367TER_DIL_NOSYNC 0xf2900040 -#define F367TER_DIL_ISCR 0xf2900020 -#define F367TER_DILOUT_BSYNCB 0xf2900010 -#define F367TER_TSFIFO_EMPTYPKT 0xf2900008 -#define F367TER_TSFIFO_EMPTYRD 0xf2900004 -#define F367TER_SOFFIFO_STOPM 0xf2900002 -#define F367TER_SOFFIFO_SPEEDUPM 0xf2900001 - -/* TSDEBUGL */ -#define R367TER_TSDEBUGL 0xf291 -#define F367TER_TSFIFO_PACKLENFAIL 0xf2910080 -#define F367TER_TSFIFO_SYNCBFAIL 0xf2910040 -#define F367TER_TSFIFO_VITLIBRE 0xf2910020 -#define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010 -#define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008 -#define F367TER_TSFIFO_ERROR_EVNT 0xf2910004 -#define F367TER_TSFIFO_FULL 0xf2910002 -#define F367TER_TSFIFO_OVERFLOWM 0xf2910001 - -/* TSDLYSETH */ -#define R367TER_TSDLYSETH 0xf292 -#define F367TER_SOFFIFO_OFFSET 0xf29200e0 -#define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f - -/* TSDLYSETM */ -#define R367TER_TSDLYSETM 0xf293 -#define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff - -/* TSDLYSETL */ -#define R367TER_TSDLYSETL 0xf294 -#define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff - -/* TSOBSCFG */ -#define R367TER_TSOBSCFG 0xf295 -#define F367TER_TSFIFO_OBSCFG 0xf29500ff - -/* TSOBSM */ -#define R367TER_TSOBSM 0xf296 -#define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff - -/* TSOBSL */ -#define R367TER_TSOBSL 0xf297 -#define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff - -/* ERRCTRL1 */ -#define R367TER_ERRCTRL1 0xf298 -#define F367TER_ERR_SRC1 0xf29800f0 -#define F367TER_ERRCTRL1_3 0xf2980008 -#define F367TER_NUM_EVT1 0xf2980007 - -/* ERRCNT1H */ -#define R367TER_ERRCNT1H 0xf299 -#define F367TER_ERRCNT1_OLDVALUE 0xf2990080 -#define F367TER_ERR_CNT1 0xf299007f - -/* ERRCNT1M */ -#define R367TER_ERRCNT1M 0xf29a -#define F367TER_ERR_CNT1_HI 0xf29a00ff - -/* ERRCNT1L */ -#define R367TER_ERRCNT1L 0xf29b -#define F367TER_ERR_CNT1_LO 0xf29b00ff - -/* ERRCTRL2 */ -#define R367TER_ERRCTRL2 0xf29c -#define F367TER_ERR_SRC2 0xf29c00f0 -#define F367TER_ERRCTRL2_3 0xf29c0008 -#define F367TER_NUM_EVT2 0xf29c0007 - -/* ERRCNT2H */ -#define R367TER_ERRCNT2H 0xf29d -#define F367TER_ERRCNT2_OLDVALUE 0xf29d0080 -#define F367TER_ERR_CNT2_HI 0xf29d007f - -/* ERRCNT2M */ -#define R367TER_ERRCNT2M 0xf29e -#define F367TER_ERR_CNT2_MED 0xf29e00ff - -/* ERRCNT2L */ -#define R367TER_ERRCNT2L 0xf29f -#define F367TER_ERR_CNT2_LO 0xf29f00ff - -/* FECSPY */ -#define R367TER_FECSPY 0xf2a0 -#define F367TER_SPY_ENABLE 0xf2a00080 -#define F367TER_NO_SYNCBYTE 0xf2a00040 -#define F367TER_SERIAL_MODE 0xf2a00020 -#define F367TER_UNUSUAL_PACKET 0xf2a00010 -#define F367TER_BERMETER_DATAMODE 0xf2a0000c -#define F367TER_BERMETER_LMODE 0xf2a00002 -#define F367TER_BERMETER_RESET 0xf2a00001 - -/* FSPYCFG */ -#define R367TER_FSPYCFG 0xf2a1 -#define F367TER_FECSPY_INPUT 0xf2a100c0 -#define F367TER_RST_ON_ERROR 0xf2a10020 -#define F367TER_ONE_SHOT 0xf2a10010 -#define F367TER_I2C_MOD 0xf2a1000c -#define F367TER_SPY_HYSTERESIS 0xf2a10003 - -/* FSPYDATA */ -#define R367TER_FSPYDATA 0xf2a2 -#define F367TER_SPY_STUFFING 0xf2a20080 -#define F367TER_NOERROR_PKTJITTER 0xf2a20040 -#define F367TER_SPY_CNULLPKT 0xf2a20020 -#define F367TER_SPY_OUTDATA_MODE 0xf2a2001f - -/* FSPYOUT */ -#define R367TER_FSPYOUT 0xf2a3 -#define F367TER_FSPY_DIRECT 0xf2a30080 -#define F367TER_FSPYOUT_6 0xf2a30040 -#define F367TER_SPY_OUTDATA_BUS 0xf2a30038 -#define F367TER_STUFF_MODE 0xf2a30007 - -/* FSTATUS */ -#define R367TER_FSTATUS 0xf2a4 -#define F367TER_SPY_ENDSIM 0xf2a40080 -#define F367TER_VALID_SIM 0xf2a40040 -#define F367TER_FOUND_SIGNAL 0xf2a40020 -#define F367TER_DSS_SYNCBYTE 0xf2a40010 -#define F367TER_RESULT_STATE 0xf2a4000f - -/* FGOODPACK */ -#define R367TER_FGOODPACK 0xf2a5 -#define F367TER_FGOOD_PACKET 0xf2a500ff - -/* FPACKCNT */ -#define R367TER_FPACKCNT 0xf2a6 -#define F367TER_FPACKET_COUNTER 0xf2a600ff - -/* FSPYMISC */ -#define R367TER_FSPYMISC 0xf2a7 -#define F367TER_FLABEL_COUNTER 0xf2a700ff - -/* FBERCPT4 */ -#define R367TER_FBERCPT4 0xf2a8 -#define F367TER_FBERMETER_CPT5 0xf2a800ff - -/* FBERCPT3 */ -#define R367TER_FBERCPT3 0xf2a9 -#define F367TER_FBERMETER_CPT4 0xf2a900ff - -/* FBERCPT2 */ -#define R367TER_FBERCPT2 0xf2aa -#define F367TER_FBERMETER_CPT3 0xf2aa00ff - -/* FBERCPT1 */ -#define R367TER_FBERCPT1 0xf2ab -#define F367TER_FBERMETER_CPT2 0xf2ab00ff - -/* FBERCPT0 */ -#define R367TER_FBERCPT0 0xf2ac -#define F367TER_FBERMETER_CPT1 0xf2ac00ff - -/* FBERERR2 */ -#define R367TER_FBERERR2 0xf2ad -#define F367TER_FBERMETER_ERR_HI 0xf2ad00ff - -/* FBERERR1 */ -#define R367TER_FBERERR1 0xf2ae -#define F367TER_FBERMETER_ERR_MED 0xf2ae00ff - -/* FBERERR0 */ -#define R367TER_FBERERR0 0xf2af -#define F367TER_FBERMETER_ERR_LO 0xf2af00ff - -/* FSTATESM */ -#define R367TER_FSTATESM 0xf2b0 -#define F367TER_RSTATE_F 0xf2b00080 -#define F367TER_RSTATE_E 0xf2b00040 -#define F367TER_RSTATE_D 0xf2b00020 -#define F367TER_RSTATE_C 0xf2b00010 -#define F367TER_RSTATE_B 0xf2b00008 -#define F367TER_RSTATE_A 0xf2b00004 -#define F367TER_RSTATE_9 0xf2b00002 -#define F367TER_RSTATE_8 0xf2b00001 - -/* FSTATESL */ -#define R367TER_FSTATESL 0xf2b1 -#define F367TER_RSTATE_7 0xf2b10080 -#define F367TER_RSTATE_6 0xf2b10040 -#define F367TER_RSTATE_5 0xf2b10020 -#define F367TER_RSTATE_4 0xf2b10010 -#define F367TER_RSTATE_3 0xf2b10008 -#define F367TER_RSTATE_2 0xf2b10004 -#define F367TER_RSTATE_1 0xf2b10002 -#define F367TER_RSTATE_0 0xf2b10001 - -/* FSPYBER */ -#define R367TER_FSPYBER 0xf2b2 -#define F367TER_FSPYBER_7 0xf2b20080 -#define F367TER_FSPYOBS_XORREAD 0xf2b20040 -#define F367TER_FSPYBER_OBSMODE 0xf2b20020 -#define F367TER_FSPYBER_SYNCBYTE 0xf2b20010 -#define F367TER_FSPYBER_UNSYNC 0xf2b20008 -#define F367TER_FSPYBER_CTIME 0xf2b20007 - -/* FSPYDISTM */ -#define R367TER_FSPYDISTM 0xf2b3 -#define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff - -/* FSPYDISTL */ -#define R367TER_FSPYDISTL 0xf2b4 -#define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff - -/* FSPYOBS7 */ -#define R367TER_FSPYOBS7 0xf2b8 -#define F367TER_FSPYOBS_SPYFAIL 0xf2b80080 -#define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040 -#define F367TER_FSPYOBS_ERROR 0xf2b80020 -#define F367TER_FSPYOBS_STROUT 0xf2b80010 -#define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f - -/* FSPYOBS6 */ -#define R367TER_FSPYOBS6 0xf2b9 -#define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0 -#define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f - -/* FSPYOBS5 */ -#define R367TER_FSPYOBS5 0xf2ba -#define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff - -/* FSPYOBS4 */ -#define R367TER_FSPYOBS4 0xf2bb -#define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff - -/* FSPYOBS3 */ -#define R367TER_FSPYOBS3 0xf2bc -#define F367TER_FSPYOBS_DATA1 0xf2bc00ff - -/* FSPYOBS2 */ -#define R367TER_FSPYOBS2 0xf2bd -#define F367TER_FSPYOBS_DATa0 0xf2bd00ff - -/* FSPYOBS1 */ -#define R367TER_FSPYOBS1 0xf2be -#define F367TER_FSPYOBS_DATAM1 0xf2be00ff - -/* FSPYOBS0 */ -#define R367TER_FSPYOBS0 0xf2bf -#define F367TER_FSPYOBS_DATAM2 0xf2bf00ff - -/* SFDEMAP */ -#define R367TER_SFDEMAP 0xf2c0 -#define F367TER_SFDEMAP_7 0xf2c00080 -#define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f - -/* SFERROR */ -#define R367TER_SFERROR 0xf2c1 -#define F367TER_SFEC_REGERR_VIT 0xf2c100ff - -/* SFAVSR */ -#define R367TER_SFAVSR 0xf2c2 -#define F367TER_SFEC_SUMERRORS 0xf2c20080 -#define F367TER_SERROR_MAXMODE 0xf2c20040 -#define F367TER_SN_SFEC 0xf2c20030 -#define F367TER_KDIV_MODE_SFEC 0xf2c2000c -#define F367TER_SFAVSR_1 0xf2c20002 -#define F367TER_SFAVSR_0 0xf2c20001 - -/* SFECSTATUS */ -#define R367TER_SFECSTATUS 0xf2c3 -#define F367TER_SFEC_ON 0xf2c30080 -#define F367TER_SFSTATUS_6 0xf2c30040 -#define F367TER_SFSTATUS_5 0xf2c30020 -#define F367TER_SFSTATUS_4 0xf2c30010 -#define F367TER_LOCKEDSFEC 0xf2c30008 -#define F367TER_SFEC_DELOCK 0xf2c30004 -#define F367TER_SFEC_DEMODSEL1 0xf2c30002 -#define F367TER_SFEC_OVFON 0xf2c30001 - -/* SFKDIV12 */ -#define R367TER_SFKDIV12 0xf2c4 -#define F367TER_SFECKDIV12_MAN 0xf2c40080 -#define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f - -/* SFKDIV23 */ -#define R367TER_SFKDIV23 0xf2c5 -#define F367TER_SFECKDIV23_MAN 0xf2c50080 -#define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f - -/* SFKDIV34 */ -#define R367TER_SFKDIV34 0xf2c6 -#define F367TER_SFECKDIV34_MAN 0xf2c60080 -#define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f - -/* SFKDIV56 */ -#define R367TER_SFKDIV56 0xf2c7 -#define F367TER_SFECKDIV56_MAN 0xf2c70080 -#define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f - -/* SFKDIV67 */ -#define R367TER_SFKDIV67 0xf2c8 -#define F367TER_SFECKDIV67_MAN 0xf2c80080 -#define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f - -/* SFKDIV78 */ -#define R367TER_SFKDIV78 0xf2c9 -#define F367TER_SFECKDIV78_MAN 0xf2c90080 -#define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f - -/* SFDILSTKM */ -#define R367TER_SFDILSTKM 0xf2ca -#define F367TER_SFEC_PACKCPT 0xf2ca00e0 -#define F367TER_SFEC_DILSTK_HI 0xf2ca001f - -/* SFDILSTKL */ -#define R367TER_SFDILSTKL 0xf2cb -#define F367TER_SFEC_DILSTK_LO 0xf2cb00ff - -/* SFSTATUS */ -#define R367TER_SFSTATUS 0xf2cc -#define F367TER_SFEC_LINEOK 0xf2cc0080 -#define F367TER_SFEC_ERROR 0xf2cc0040 -#define F367TER_SFEC_DATA7 0xf2cc0020 -#define F367TER_SFEC_OVERFLOW 0xf2cc0010 -#define F367TER_SFEC_DEMODSEL2 0xf2cc0008 -#define F367TER_SFEC_NOSYNC 0xf2cc0004 -#define F367TER_SFEC_UNREGULA 0xf2cc0002 -#define F367TER_SFEC_READY 0xf2cc0001 - -/* SFDLYH */ -#define R367TER_SFDLYH 0xf2cd -#define F367TER_SFEC_TSTIMEVALID 0xf2cd0080 -#define F367TER_SFEC_SPEEDUP 0xf2cd0040 -#define F367TER_SFEC_STOP 0xf2cd0020 -#define F367TER_SFEC_REGULATED 0xf2cd0010 -#define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f - -/* SFDLYM */ -#define R367TER_SFDLYM 0xf2ce -#define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff - -/* SFDLYL */ -#define R367TER_SFDLYL 0xf2cf -#define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff - -/* SFDLYSETH */ -#define R367TER_SFDLYSETH 0xf2d0 -#define F367TER_SFEC_OFFSET 0xf2d000e0 -#define F367TER_SFECDLYSETH_4 0xf2d00010 -#define F367TER_RST_SFEC 0xf2d00008 -#define F367TER_SFECDLYSETH_2 0xf2d00004 -#define F367TER_SFEC_DISABLE 0xf2d00002 -#define F367TER_SFEC_UNREGUL 0xf2d00001 - -/* SFDLYSETM */ -#define R367TER_SFDLYSETM 0xf2d1 -#define F367TER_SFECDLYSETM_7 0xf2d10080 -#define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f - -/* SFDLYSETL */ -#define R367TER_SFDLYSETL 0xf2d2 -#define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff - -/* SFOBSCFG */ -#define R367TER_SFOBSCFG 0xf2d3 -#define F367TER_SFEC_OBSCFG 0xf2d300ff - -/* SFOBSM */ -#define R367TER_SFOBSM 0xf2d4 -#define F367TER_SFEC_OBSDATA_HI 0xf2d400ff - -/* SFOBSL */ -#define R367TER_SFOBSL 0xf2d5 -#define F367TER_SFEC_OBSDATA_LO 0xf2d500ff - -/* SFECINFO */ -#define R367TER_SFECINFO 0xf2d6 -#define F367TER_SFECINFO_7 0xf2d60080 -#define F367TER_SFEC_SYNCDLSB 0xf2d60070 -#define F367TER_SFCE_S1cPHASE 0xf2d6000f - -/* SFERRCTRL */ -#define R367TER_SFERRCTRL 0xf2d8 -#define F367TER_SFEC_ERR_SOURCE 0xf2d800f0 -#define F367TER_SFERRCTRL_3 0xf2d80008 -#define F367TER_SFEC_NUM_EVENT 0xf2d80007 - -/* SFERRCNTH */ -#define R367TER_SFERRCNTH 0xf2d9 -#define F367TER_SFERRC_OLDVALUE 0xf2d90080 -#define F367TER_SFEC_ERR_CNT 0xf2d9007f - -/* SFERRCNTM */ -#define R367TER_SFERRCNTM 0xf2da -#define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff - -/* SFERRCNTL */ -#define R367TER_SFERRCNTL 0xf2db -#define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff - -/* SYMBRATEM */ -#define R367TER_SYMBRATEM 0xf2e0 -#define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff - -/* SYMBRATEL */ -#define R367TER_SYMBRATEL 0xf2e1 -#define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff - -/* SYMBSTATUS */ -#define R367TER_SYMBSTATUS 0xf2e2 -#define F367TER_SYMBDLINE2_OFF 0xf2e20080 -#define F367TER_SDDL_REINIT1 0xf2e20040 -#define F367TER_SDD_REINIT1 0xf2e20020 -#define F367TER_TOKENID_ERROR 0xf2e20010 -#define F367TER_SYMBRATE_OVERFLOW 0xf2e20008 -#define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004 -#define F367TER_TOKENID_RSTEVENT 0xf2e20002 -#define F367TER_TOKENID_RESET1 0xf2e20001 - -/* SYMBCFG */ -#define R367TER_SYMBCFG 0xf2e3 -#define F367TER_SYMBCFG_7 0xf2e30080 -#define F367TER_SYMBCFG_6 0xf2e30040 -#define F367TER_SYMBCFG_5 0xf2e30020 -#define F367TER_SYMBCFG_4 0xf2e30010 -#define F367TER_SYMRATE_FSPEED 0xf2e3000c -#define F367TER_SYMRATE_SSPEED 0xf2e30003 - -/* SYMBFIFOM */ -#define R367TER_SYMBFIFOM 0xf2e4 -#define F367TER_SYMBFIFOM_7 0xf2e40080 -#define F367TER_SYMBFIFOM_6 0xf2e40040 -#define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f - -/* SYMBFIFOL */ -#define R367TER_SYMBFIFOL 0xf2e5 -#define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff - -/* SYMBOFFSM */ -#define R367TER_SYMBOFFSM 0xf2e6 -#define F367TER_TOKENID_RESET2 0xf2e60080 -#define F367TER_SDDL_REINIT2 0xf2e60040 -#define F367TER_SDD_REINIT2 0xf2e60020 -#define F367TER_SYMBOFFSM_4 0xf2e60010 -#define F367TER_SYMBOFFSM_3 0xf2e60008 -#define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007 - -/* SYMBOFFSL */ -#define R367TER_SYMBOFFSL 0xf2e7 -#define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff - -/* DEBUG_LT4 */ -#define R367TER_DEBUG_LT4 0xf400 -#define F367TER_F_DEBUG_LT4 0xf40000ff - -/* DEBUG_LT5 */ -#define R367TER_DEBUG_LT5 0xf401 -#define F367TER_F_DEBUG_LT5 0xf40100ff - -/* DEBUG_LT6 */ -#define R367TER_DEBUG_LT6 0xf402 -#define F367TER_F_DEBUG_LT6 0xf40200ff - -/* DEBUG_LT7 */ -#define R367TER_DEBUG_LT7 0xf403 -#define F367TER_F_DEBUG_LT7 0xf40300ff - -/* DEBUG_LT8 */ -#define R367TER_DEBUG_LT8 0xf404 -#define F367TER_F_DEBUG_LT8 0xf40400ff - -/* DEBUG_LT9 */ -#define R367TER_DEBUG_LT9 0xf405 -#define F367TER_F_DEBUG_LT9 0xf40500ff - -#define STV0367TER_NBREGS 445 - -/* ID */ -#define R367CAB_ID 0xf000 -#define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff - -/* I2CRPT */ -#define R367CAB_I2CRPT 0xf001 -#define F367CAB_I2CT_ON 0xf0010080 -#define F367CAB_ENARPT_LEVEL 0xf0010070 -#define F367CAB_SCLT_DELAY 0xf0010008 -#define F367CAB_SCLT_NOD 0xf0010004 -#define F367CAB_STOP_ENABLE 0xf0010002 -#define F367CAB_SDAT_NOD 0xf0010001 - -/* TOPCTRL */ -#define R367CAB_TOPCTRL 0xf002 -#define F367CAB_STDBY 0xf0020080 -#define F367CAB_STDBY_CORE 0xf0020020 -#define F367CAB_QAM_COFDM 0xf0020010 -#define F367CAB_TS_DIS 0xf0020008 -#define F367CAB_DIR_CLK_216 0xf0020004 - -/* IOCFG0 */ -#define R367CAB_IOCFG0 0xf003 -#define F367CAB_OP0_SD 0xf0030080 -#define F367CAB_OP0_VAL 0xf0030040 -#define F367CAB_OP0_OD 0xf0030020 -#define F367CAB_OP0_INV 0xf0030010 -#define F367CAB_OP0_DACVALUE_HI 0xf003000f - -/* DAc0R */ -#define R367CAB_DAC0R 0xf004 -#define F367CAB_OP0_DACVALUE_LO 0xf00400ff - -/* IOCFG1 */ -#define R367CAB_IOCFG1 0xf005 -#define F367CAB_IP0 0xf0050040 -#define F367CAB_OP1_OD 0xf0050020 -#define F367CAB_OP1_INV 0xf0050010 -#define F367CAB_OP1_DACVALUE_HI 0xf005000f - -/* DAC1R */ -#define R367CAB_DAC1R 0xf006 -#define F367CAB_OP1_DACVALUE_LO 0xf00600ff - -/* IOCFG2 */ -#define R367CAB_IOCFG2 0xf007 -#define F367CAB_OP2_LOCK_CONF 0xf00700e0 -#define F367CAB_OP2_OD 0xf0070010 -#define F367CAB_OP2_VAL 0xf0070008 -#define F367CAB_OP1_LOCK_CONF 0xf0070007 - -/* SDFR */ -#define R367CAB_SDFR 0xf008 -#define F367CAB_OP0_FREQ 0xf00800f0 -#define F367CAB_OP1_FREQ 0xf008000f - -/* AUX_CLK */ -#define R367CAB_AUX_CLK 0xf00a -#define F367CAB_AUXFEC_CTL 0xf00a00c0 -#define F367CAB_DIS_CKX4 0xf00a0020 -#define F367CAB_CKSEL 0xf00a0018 -#define F367CAB_CKDIV_PROG 0xf00a0006 -#define F367CAB_AUXCLK_ENA 0xf00a0001 - -/* FREESYS1 */ -#define R367CAB_FREESYS1 0xf00b -#define F367CAB_FREESYS_1 0xf00b00ff - -/* FREESYS2 */ -#define R367CAB_FREESYS2 0xf00c -#define F367CAB_FREESYS_2 0xf00c00ff - -/* FREESYS3 */ -#define R367CAB_FREESYS3 0xf00d -#define F367CAB_FREESYS_3 0xf00d00ff - -/* GPIO_CFG */ -#define R367CAB_GPIO_CFG 0xf00e -#define F367CAB_GPIO7_OD 0xf00e0080 -#define F367CAB_GPIO7_CFG 0xf00e0040 -#define F367CAB_GPIO6_OD 0xf00e0020 -#define F367CAB_GPIO6_CFG 0xf00e0010 -#define F367CAB_GPIO5_OD 0xf00e0008 -#define F367CAB_GPIO5_CFG 0xf00e0004 -#define F367CAB_GPIO4_OD 0xf00e0002 -#define F367CAB_GPIO4_CFG 0xf00e0001 - -/* GPIO_CMD */ -#define R367CAB_GPIO_CMD 0xf00f -#define F367CAB_GPIO7_VAL 0xf00f0008 -#define F367CAB_GPIO6_VAL 0xf00f0004 -#define F367CAB_GPIO5_VAL 0xf00f0002 -#define F367CAB_GPIO4_VAL 0xf00f0001 - -/* TSTRES */ -#define R367CAB_TSTRES 0xf0c0 -#define F367CAB_FRES_DISPLAY 0xf0c00080 -#define F367CAB_FRES_FIFO_AD 0xf0c00020 -#define F367CAB_FRESRS 0xf0c00010 -#define F367CAB_FRESACS 0xf0c00008 -#define F367CAB_FRESFEC 0xf0c00004 -#define F367CAB_FRES_PRIF 0xf0c00002 -#define F367CAB_FRESCORE 0xf0c00001 - -/* ANACTRL */ -#define R367CAB_ANACTRL 0xf0c1 -#define F367CAB_BYPASS_XTAL 0xf0c10040 -#define F367CAB_BYPASS_PLLXN 0xf0c1000c -#define F367CAB_DIS_PAD_OSC 0xf0c10002 -#define F367CAB_STDBY_PLLXN 0xf0c10001 - -/* TSTBUS */ -#define R367CAB_TSTBUS 0xf0c2 -#define F367CAB_TS_BYTE_CLK_INV 0xf0c20080 -#define F367CAB_CFG_IP 0xf0c20070 -#define F367CAB_CFG_TST 0xf0c2000f - -/* RF_AGC1 */ -#define R367CAB_RF_AGC1 0xf0d4 -#define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff - -/* RF_AGC2 */ -#define R367CAB_RF_AGC2 0xf0d5 -#define F367CAB_REF_ADGP 0xf0d50080 -#define F367CAB_STDBY_ADCGP 0xf0d50020 -#define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003 - -/* ANADIGCTRL */ -#define R367CAB_ANADIGCTRL 0xf0d7 -#define F367CAB_SEL_CLKDEM 0xf0d70020 -#define F367CAB_EN_BUFFER_Q 0xf0d70010 -#define F367CAB_EN_BUFFER_I 0xf0d70008 -#define F367CAB_ADC_RIS_EGDE 0xf0d70004 -#define F367CAB_SGN_ADC 0xf0d70002 -#define F367CAB_SEL_AD12_SYNC 0xf0d70001 - -/* PLLMDIV */ -#define R367CAB_PLLMDIV 0xf0d8 -#define F367CAB_PLL_MDIV 0xf0d800ff - -/* PLLNDIV */ -#define R367CAB_PLLNDIV 0xf0d9 -#define F367CAB_PLL_NDIV 0xf0d900ff - -/* PLLSETUP */ -#define R367CAB_PLLSETUP 0xf0da -#define F367CAB_PLL_PDIV 0xf0da0070 -#define F367CAB_PLL_KDIV 0xf0da000f - -/* DUAL_AD12 */ -#define R367CAB_DUAL_AD12 0xf0db -#define F367CAB_FS20M 0xf0db0020 -#define F367CAB_FS50M 0xf0db0010 -#define F367CAB_INMODe0 0xf0db0008 -#define F367CAB_POFFQ 0xf0db0004 -#define F367CAB_POFFI 0xf0db0002 -#define F367CAB_INMODE1 0xf0db0001 - -/* TSTBIST */ -#define R367CAB_TSTBIST 0xf0dc -#define F367CAB_TST_BYP_CLK 0xf0dc0080 -#define F367CAB_TST_GCLKENA_STD 0xf0dc0040 -#define F367CAB_TST_GCLKENA 0xf0dc0020 -#define F367CAB_TST_MEMBIST 0xf0dc001f - -/* CTRL_1 */ -#define R367CAB_CTRL_1 0xf402 -#define F367CAB_SOFT_RST 0xf4020080 -#define F367CAB_EQU_RST 0xf4020008 -#define F367CAB_CRL_RST 0xf4020004 -#define F367CAB_TRL_RST 0xf4020002 -#define F367CAB_AGC_RST 0xf4020001 - -/* CTRL_2 */ -#define R367CAB_CTRL_2 0xf403 -#define F367CAB_DEINT_RST 0xf4030008 -#define F367CAB_RS_RST 0xf4030004 - -/* IT_STATUS1 */ -#define R367CAB_IT_STATUS1 0xf408 -#define F367CAB_SWEEP_OUT 0xf4080080 -#define F367CAB_FSM_CRL 0xf4080040 -#define F367CAB_CRL_LOCK 0xf4080020 -#define F367CAB_MFSM 0xf4080010 -#define F367CAB_TRL_LOCK 0xf4080008 -#define F367CAB_TRL_AGC_LIMIT 0xf4080004 -#define F367CAB_ADJ_AGC_LOCK 0xf4080002 -#define F367CAB_AGC_QAM_LOCK 0xf4080001 - -/* IT_STATUS2 */ -#define R367CAB_IT_STATUS2 0xf409 -#define F367CAB_TSMF_CNT 0xf4090080 -#define F367CAB_TSMF_EOF 0xf4090040 -#define F367CAB_TSMF_RDY 0xf4090020 -#define F367CAB_FEC_NOCORR 0xf4090010 -#define F367CAB_SYNCSTATE 0xf4090008 -#define F367CAB_DEINT_LOCK 0xf4090004 -#define F367CAB_FADDING_FRZ 0xf4090002 -#define F367CAB_TAPMON_ALARM 0xf4090001 - -/* IT_EN1 */ -#define R367CAB_IT_EN1 0xf40a -#define F367CAB_SWEEP_OUTE 0xf40a0080 -#define F367CAB_FSM_CRLE 0xf40a0040 -#define F367CAB_CRL_LOCKE 0xf40a0020 -#define F367CAB_MFSME 0xf40a0010 -#define F367CAB_TRL_LOCKE 0xf40a0008 -#define F367CAB_TRL_AGC_LIMITE 0xf40a0004 -#define F367CAB_ADJ_AGC_LOCKE 0xf40a0002 -#define F367CAB_AGC_LOCKE 0xf40a0001 - -/* IT_EN2 */ -#define R367CAB_IT_EN2 0xf40b -#define F367CAB_TSMF_CNTE 0xf40b0080 -#define F367CAB_TSMF_EOFE 0xf40b0040 -#define F367CAB_TSMF_RDYE 0xf40b0020 -#define F367CAB_FEC_NOCORRE 0xf40b0010 -#define F367CAB_SYNCSTATEE 0xf40b0008 -#define F367CAB_DEINT_LOCKE 0xf40b0004 -#define F367CAB_FADDING_FRZE 0xf40b0002 -#define F367CAB_TAPMON_ALARME 0xf40b0001 - -/* CTRL_STATUS */ -#define R367CAB_CTRL_STATUS 0xf40c -#define F367CAB_QAMFEC_LOCK 0xf40c0004 -#define F367CAB_TSMF_LOCK 0xf40c0002 -#define F367CAB_TSMF_ERROR 0xf40c0001 - -/* TEST_CTL */ -#define R367CAB_TEST_CTL 0xf40f -#define F367CAB_TST_BLK_SEL 0xf40f0060 -#define F367CAB_TST_BUS_SEL 0xf40f001f - -/* AGC_CTL */ -#define R367CAB_AGC_CTL 0xf410 -#define F367CAB_AGC_LCK_TH 0xf41000f0 -#define F367CAB_AGC_ACCUMRSTSEL 0xf4100007 - -/* AGC_IF_CFG */ -#define R367CAB_AGC_IF_CFG 0xf411 -#define F367CAB_AGC_IF_BWSEL 0xf41100f0 -#define F367CAB_AGC_IF_FREEZE 0xf4110002 - -/* AGC_RF_CFG */ -#define R367CAB_AGC_RF_CFG 0xf412 -#define F367CAB_AGC_RF_BWSEL 0xf4120070 -#define F367CAB_AGC_RF_FREEZE 0xf4120002 - -/* AGC_PWM_CFG */ -#define R367CAB_AGC_PWM_CFG 0xf413 -#define F367CAB_AGC_RF_PWM_TST 0xf4130080 -#define F367CAB_AGC_RF_PWM_INV 0xf4130040 -#define F367CAB_AGC_IF_PWM_TST 0xf4130008 -#define F367CAB_AGC_IF_PWM_INV 0xf4130004 -#define F367CAB_AGC_PWM_CLKDIV 0xf4130003 - -/* AGC_PWR_REF_L */ -#define R367CAB_AGC_PWR_REF_L 0xf414 -#define F367CAB_AGC_PWRREF_LO 0xf41400ff - -/* AGC_PWR_REF_H */ -#define R367CAB_AGC_PWR_REF_H 0xf415 -#define F367CAB_AGC_PWRREF_HI 0xf4150003 - -/* AGC_RF_TH_L */ -#define R367CAB_AGC_RF_TH_L 0xf416 -#define F367CAB_AGC_RF_TH_LO 0xf41600ff - -/* AGC_RF_TH_H */ -#define R367CAB_AGC_RF_TH_H 0xf417 -#define F367CAB_AGC_RF_TH_HI 0xf417000f - -/* AGC_IF_LTH_L */ -#define R367CAB_AGC_IF_LTH_L 0xf418 -#define F367CAB_AGC_IF_THLO_LO 0xf41800ff - -/* AGC_IF_LTH_H */ -#define R367CAB_AGC_IF_LTH_H 0xf419 -#define F367CAB_AGC_IF_THLO_HI 0xf419000f - -/* AGC_IF_HTH_L */ -#define R367CAB_AGC_IF_HTH_L 0xf41a -#define F367CAB_AGC_IF_THHI_LO 0xf41a00ff - -/* AGC_IF_HTH_H */ -#define R367CAB_AGC_IF_HTH_H 0xf41b -#define F367CAB_AGC_IF_THHI_HI 0xf41b000f - -/* AGC_PWR_RD_L */ -#define R367CAB_AGC_PWR_RD_L 0xf41c -#define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff - -/* AGC_PWR_RD_M */ -#define R367CAB_AGC_PWR_RD_M 0xf41d -#define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff - -/* AGC_PWR_RD_H */ -#define R367CAB_AGC_PWR_RD_H 0xf41e -#define F367CAB_AGC_PWR_WORD_HI 0xf41e0003 - -/* AGC_PWM_IFCMD_L */ -#define R367CAB_AGC_PWM_IFCMD_L 0xf420 -#define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff - -/* AGC_PWM_IFCMD_H */ -#define R367CAB_AGC_PWM_IFCMD_H 0xf421 -#define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f - -/* AGC_PWM_RFCMD_L */ -#define R367CAB_AGC_PWM_RFCMD_L 0xf422 -#define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff - -/* AGC_PWM_RFCMD_H */ -#define R367CAB_AGC_PWM_RFCMD_H 0xf423 -#define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f - -/* IQDEM_CFG */ -#define R367CAB_IQDEM_CFG 0xf424 -#define F367CAB_IQDEM_CLK_SEL 0xf4240004 -#define F367CAB_IQDEM_INVIQ 0xf4240002 -#define F367CAB_IQDEM_A2dTYPE 0xf4240001 - -/* MIX_NCO_LL */ -#define R367CAB_MIX_NCO_LL 0xf425 -#define F367CAB_MIX_NCO_INC_LL 0xf42500ff - -/* MIX_NCO_HL */ -#define R367CAB_MIX_NCO_HL 0xf426 -#define F367CAB_MIX_NCO_INC_HL 0xf42600ff - -/* MIX_NCO_HH */ -#define R367CAB_MIX_NCO_HH 0xf427 -#define F367CAB_MIX_NCO_INVCNST 0xf4270080 -#define F367CAB_MIX_NCO_INC_HH 0xf427007f - -/* SRC_NCO_LL */ -#define R367CAB_SRC_NCO_LL 0xf428 -#define F367CAB_SRC_NCO_INC_LL 0xf42800ff - -/* SRC_NCO_LH */ -#define R367CAB_SRC_NCO_LH 0xf429 -#define F367CAB_SRC_NCO_INC_LH 0xf42900ff - -/* SRC_NCO_HL */ -#define R367CAB_SRC_NCO_HL 0xf42a -#define F367CAB_SRC_NCO_INC_HL 0xf42a00ff - -/* SRC_NCO_HH */ -#define R367CAB_SRC_NCO_HH 0xf42b -#define F367CAB_SRC_NCO_INC_HH 0xf42b007f - -/* IQDEM_GAIN_SRC_L */ -#define R367CAB_IQDEM_GAIN_SRC_L 0xf42c -#define F367CAB_GAIN_SRC_LO 0xf42c00ff - -/* IQDEM_GAIN_SRC_H */ -#define R367CAB_IQDEM_GAIN_SRC_H 0xf42d -#define F367CAB_GAIN_SRC_HI 0xf42d0003 - -/* IQDEM_DCRM_CFG_LL */ -#define R367CAB_IQDEM_DCRM_CFG_LL 0xf430 -#define F367CAB_DCRM0_DCIN_L 0xf43000ff - -/* IQDEM_DCRM_CFG_LH */ -#define R367CAB_IQDEM_DCRM_CFG_LH 0xf431 -#define F367CAB_DCRM1_I_DCIN_L 0xf43100fc -#define F367CAB_DCRM0_DCIN_H 0xf4310003 - -/* IQDEM_DCRM_CFG_HL */ -#define R367CAB_IQDEM_DCRM_CFG_HL 0xf432 -#define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0 -#define F367CAB_DCRM1_I_DCIN_H 0xf432000f - -/* IQDEM_DCRM_CFG_HH */ -#define R367CAB_IQDEM_DCRM_CFG_HH 0xf433 -#define F367CAB_DCRM1_FRZ 0xf4330080 -#define F367CAB_DCRM0_FRZ 0xf4330040 -#define F367CAB_DCRM1_Q_DCIN_H 0xf433003f - -/* IQDEM_ADJ_COEFf0 */ -#define R367CAB_IQDEM_ADJ_COEFF0 0xf434 -#define F367CAB_ADJIIR_COEFF10_L 0xf43400ff - -/* IQDEM_ADJ_COEFF1 */ -#define R367CAB_IQDEM_ADJ_COEFF1 0xf435 -#define F367CAB_ADJIIR_COEFF11_L 0xf43500fc -#define F367CAB_ADJIIR_COEFF10_H 0xf4350003 - -/* IQDEM_ADJ_COEFF2 */ -#define R367CAB_IQDEM_ADJ_COEFF2 0xf436 -#define F367CAB_ADJIIR_COEFF12_L 0xf43600f0 -#define F367CAB_ADJIIR_COEFF11_H 0xf436000f - -/* IQDEM_ADJ_COEFF3 */ -#define R367CAB_IQDEM_ADJ_COEFF3 0xf437 -#define F367CAB_ADJIIR_COEFF20_L 0xf43700c0 -#define F367CAB_ADJIIR_COEFF12_H 0xf437003f - -/* IQDEM_ADJ_COEFF4 */ -#define R367CAB_IQDEM_ADJ_COEFF4 0xf438 -#define F367CAB_ADJIIR_COEFF20_H 0xf43800ff - -/* IQDEM_ADJ_COEFF5 */ -#define R367CAB_IQDEM_ADJ_COEFF5 0xf439 -#define F367CAB_ADJIIR_COEFF21_L 0xf43900ff - -/* IQDEM_ADJ_COEFF6 */ -#define R367CAB_IQDEM_ADJ_COEFF6 0xf43a -#define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc -#define F367CAB_ADJIIR_COEFF21_H 0xf43a0003 - -/* IQDEM_ADJ_COEFF7 */ -#define R367CAB_IQDEM_ADJ_COEFF7 0xf43b -#define F367CAB_ADJIIR_COEFF22_H 0xf43b000f - -/* IQDEM_ADJ_EN */ -#define R367CAB_IQDEM_ADJ_EN 0xf43c -#define F367CAB_ALLPASSFILT_EN 0xf43c0008 -#define F367CAB_ADJ_AGC_EN 0xf43c0004 -#define F367CAB_ADJ_COEFF_FRZ 0xf43c0002 -#define F367CAB_ADJ_EN 0xf43c0001 - -/* IQDEM_ADJ_AGC_REF */ -#define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d -#define F367CAB_ADJ_AGC_REF 0xf43d00ff - -/* ALLPASSFILT1 */ -#define R367CAB_ALLPASSFILT1 0xf440 -#define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff - -/* ALLPASSFILT2 */ -#define R367CAB_ALLPASSFILT2 0xf441 -#define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff - -/* ALLPASSFILT3 */ -#define R367CAB_ALLPASSFILT3 0xf442 -#define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0 -#define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f - -/* ALLPASSFILT4 */ -#define R367CAB_ALLPASSFILT4 0xf443 -#define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff - -/* ALLPASSFILT5 */ -#define R367CAB_ALLPASSFILT5 0xf444 -#define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff - -/* ALLPASSFILT6 */ -#define R367CAB_ALLPASSFILT6 0xf445 -#define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0 -#define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f - -/* ALLPASSFILT7 */ -#define R367CAB_ALLPASSFILT7 0xf446 -#define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff - -/* ALLPASSFILT8 */ -#define R367CAB_ALLPASSFILT8 0xf447 -#define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff - -/* ALLPASSFILT9 */ -#define R367CAB_ALLPASSFILT9 0xf448 -#define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc -#define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003 - -/* ALLPASSFILT10 */ -#define R367CAB_ALLPASSFILT10 0xf449 -#define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff - -/* ALLPASSFILT11 */ -#define R367CAB_ALLPASSFILT11 0xf44a -#define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff - -/* TRL_AGC_CFG */ -#define R367CAB_TRL_AGC_CFG 0xf450 -#define F367CAB_TRL_AGC_FREEZE 0xf4500080 -#define F367CAB_TRL_AGC_REF 0xf450007f - -/* TRL_LPF_CFG */ -#define R367CAB_TRL_LPF_CFG 0xf454 -#define F367CAB_NYQPOINT_INV 0xf4540040 -#define F367CAB_TRL_SHIFT 0xf4540030 -#define F367CAB_NYQ_COEFF_SEL 0xf454000c -#define F367CAB_TRL_LPF_FREEZE 0xf4540002 -#define F367CAB_TRL_LPF_CRT 0xf4540001 - -/* TRL_LPF_ACQ_GAIN */ -#define R367CAB_TRL_LPF_ACQ_GAIN 0xf455 -#define F367CAB_TRL_GDIR_ACQ 0xf4550070 -#define F367CAB_TRL_GINT_ACQ 0xf4550007 - -/* TRL_LPF_TRK_GAIN */ -#define R367CAB_TRL_LPF_TRK_GAIN 0xf456 -#define F367CAB_TRL_GDIR_TRK 0xf4560070 -#define F367CAB_TRL_GINT_TRK 0xf4560007 - -/* TRL_LPF_OUT_GAIN */ -#define R367CAB_TRL_LPF_OUT_GAIN 0xf457 -#define F367CAB_TRL_GAIN_OUT 0xf4570007 - -/* TRL_LOCKDET_LTH */ -#define R367CAB_TRL_LOCKDET_LTH 0xf458 -#define F367CAB_TRL_LCK_THLO 0xf4580007 - -/* TRL_LOCKDET_HTH */ -#define R367CAB_TRL_LOCKDET_HTH 0xf459 -#define F367CAB_TRL_LCK_THHI 0xf45900ff - -/* TRL_LOCKDET_TRGVAL */ -#define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a -#define F367CAB_TRL_LCK_TRG 0xf45a00ff - -/* IQ_QAM */ -#define R367CAB_IQ_QAM 0xf45c -#define F367CAB_IQ_INPUT 0xf45c0008 -#define F367CAB_DETECT_MODE 0xf45c0007 - -/* FSM_STATE */ -#define R367CAB_FSM_STATE 0xf460 -#define F367CAB_CRL_DFE 0xf4600080 -#define F367CAB_DFE_START 0xf4600040 -#define F367CAB_CTRLG_START 0xf4600030 -#define F367CAB_FSM_FORCESTATE 0xf460000f - -/* FSM_CTL */ -#define R367CAB_FSM_CTL 0xf461 -#define F367CAB_FEC2_EN 0xf4610040 -#define F367CAB_SIT_EN 0xf4610020 -#define F367CAB_TRL_AHEAD 0xf4610010 -#define F367CAB_TRL2_EN 0xf4610008 -#define F367CAB_FSM_EQA1_EN 0xf4610004 -#define F367CAB_FSM_BKP_DIS 0xf4610002 -#define F367CAB_FSM_FORCE_EN 0xf4610001 - -/* FSM_STS */ -#define R367CAB_FSM_STS 0xf462 -#define F367CAB_FSM_STATUS 0xf462000f - -/* FSM_SNR0_HTH */ -#define R367CAB_FSM_SNR0_HTH 0xf463 -#define F367CAB_SNR0_HTH 0xf46300ff - -/* FSM_SNR1_HTH */ -#define R367CAB_FSM_SNR1_HTH 0xf464 -#define F367CAB_SNR1_HTH 0xf46400ff - -/* FSM_SNR2_HTH */ -#define R367CAB_FSM_SNR2_HTH 0xf465 -#define F367CAB_SNR2_HTH 0xf46500ff - -/* FSM_SNR0_LTH */ -#define R367CAB_FSM_SNR0_LTH 0xf466 -#define F367CAB_SNR0_LTH 0xf46600ff - -/* FSM_SNR1_LTH */ -#define R367CAB_FSM_SNR1_LTH 0xf467 -#define F367CAB_SNR1_LTH 0xf46700ff - -/* FSM_EQA1_HTH */ -#define R367CAB_FSM_EQA1_HTH 0xf468 -#define F367CAB_SNR3_HTH_LO 0xf46800f0 -#define F367CAB_EQA1_HTH 0xf468000f - -/* FSM_TEMPO */ -#define R367CAB_FSM_TEMPO 0xf469 -#define F367CAB_SIT 0xf46900c0 -#define F367CAB_WST 0xf4690038 -#define F367CAB_ELT 0xf4690006 -#define F367CAB_SNR3_HTH_HI 0xf4690001 - -/* FSM_CONFIG */ -#define R367CAB_FSM_CONFIG 0xf46a -#define F367CAB_FEC2_DFEOFF 0xf46a0004 -#define F367CAB_PRIT_STATE 0xf46a0002 -#define F367CAB_MODMAP_STATE 0xf46a0001 - -/* EQU_I_TESTTAP_L */ -#define R367CAB_EQU_I_TESTTAP_L 0xf474 -#define F367CAB_I_TEST_TAP_L 0xf47400ff - -/* EQU_I_TESTTAP_M */ -#define R367CAB_EQU_I_TESTTAP_M 0xf475 -#define F367CAB_I_TEST_TAP_M 0xf47500ff - -/* EQU_I_TESTTAP_H */ -#define R367CAB_EQU_I_TESTTAP_H 0xf476 -#define F367CAB_I_TEST_TAP_H 0xf476001f - -/* EQU_TESTAP_CFG */ -#define R367CAB_EQU_TESTAP_CFG 0xf477 -#define F367CAB_TEST_FFE_DFE_SEL 0xf4770040 -#define F367CAB_TEST_TAP_SELECT 0xf477003f - -/* EQU_Q_TESTTAP_L */ -#define R367CAB_EQU_Q_TESTTAP_L 0xf478 -#define F367CAB_Q_TEST_TAP_L 0xf47800ff - -/* EQU_Q_TESTTAP_M */ -#define R367CAB_EQU_Q_TESTTAP_M 0xf479 -#define F367CAB_Q_TEST_TAP_M 0xf47900ff - -/* EQU_Q_TESTTAP_H */ -#define R367CAB_EQU_Q_TESTTAP_H 0xf47a -#define F367CAB_Q_TEST_TAP_H 0xf47a001f - -/* EQU_TAP_CTRL */ -#define R367CAB_EQU_TAP_CTRL 0xf47b -#define F367CAB_MTAP_FRZ 0xf47b0010 -#define F367CAB_PRE_FREEZE 0xf47b0008 -#define F367CAB_DFE_TAPMON_EN 0xf47b0004 -#define F367CAB_FFE_TAPMON_EN 0xf47b0002 -#define F367CAB_MTAP_ONLY 0xf47b0001 - -/* EQU_CTR_CRL_CONTROL_L */ -#define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c -#define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff - -/* EQU_CTR_CRL_CONTROL_H */ -#define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d -#define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff - -/* EQU_CTR_HIPOW_L */ -#define R367CAB_EQU_CTR_HIPOW_L 0xf47e -#define F367CAB_CTR_HIPOW_L 0xf47e00ff - -/* EQU_CTR_HIPOW_H */ -#define R367CAB_EQU_CTR_HIPOW_H 0xf47f -#define F367CAB_CTR_HIPOW_H 0xf47f00ff - -/* EQU_I_EQU_LO */ -#define R367CAB_EQU_I_EQU_LO 0xf480 -#define F367CAB_EQU_I_EQU_L 0xf48000ff - -/* EQU_I_EQU_HI */ -#define R367CAB_EQU_I_EQU_HI 0xf481 -#define F367CAB_EQU_I_EQU_H 0xf4810003 - -/* EQU_Q_EQU_LO */ -#define R367CAB_EQU_Q_EQU_LO 0xf482 -#define F367CAB_EQU_Q_EQU_L 0xf48200ff - -/* EQU_Q_EQU_HI */ -#define R367CAB_EQU_Q_EQU_HI 0xf483 -#define F367CAB_EQU_Q_EQU_H 0xf4830003 - -/* EQU_MAPPER */ -#define R367CAB_EQU_MAPPER 0xf484 -#define F367CAB_QUAD_AUTO 0xf4840080 -#define F367CAB_QUAD_INV 0xf4840040 -#define F367CAB_QAM_MODE 0xf4840007 - -/* EQU_SWEEP_RATE */ -#define R367CAB_EQU_SWEEP_RATE 0xf485 -#define F367CAB_SNR_PER 0xf48500c0 -#define F367CAB_SWEEP_RATE 0xf485003f - -/* EQU_SNR_LO */ -#define R367CAB_EQU_SNR_LO 0xf486 -#define F367CAB_SNR_LO 0xf48600ff - -/* EQU_SNR_HI */ -#define R367CAB_EQU_SNR_HI 0xf487 -#define F367CAB_SNR_HI 0xf48700ff - -/* EQU_GAMMA_LO */ -#define R367CAB_EQU_GAMMA_LO 0xf488 -#define F367CAB_GAMMA_LO 0xf48800ff - -/* EQU_GAMMA_HI */ -#define R367CAB_EQU_GAMMA_HI 0xf489 -#define F367CAB_GAMMA_ME 0xf48900ff - -/* EQU_ERR_GAIN */ -#define R367CAB_EQU_ERR_GAIN 0xf48a -#define F367CAB_EQA1MU 0xf48a0070 -#define F367CAB_CRL2MU 0xf48a000e -#define F367CAB_GAMMA_HI 0xf48a0001 - -/* EQU_RADIUS */ -#define R367CAB_EQU_RADIUS 0xf48b -#define F367CAB_RADIUS 0xf48b00ff - -/* EQU_FFE_MAINTAP */ -#define R367CAB_EQU_FFE_MAINTAP 0xf48c -#define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff - -/* EQU_FFE_LEAKAGE */ -#define R367CAB_EQU_FFE_LEAKAGE 0xf48e -#define F367CAB_LEAK_PER 0xf48e00f0 -#define F367CAB_EQU_OUTSEL 0xf48e0002 -#define F367CAB_PNT2dFE 0xf48e0001 - -/* EQU_FFE_MAINTAP_POS */ -#define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f -#define F367CAB_FFE_LEAK_EN 0xf48f0080 -#define F367CAB_DFE_LEAK_EN 0xf48f0040 -#define F367CAB_FFE_MAINTAP_POS 0xf48f003f - -/* EQU_GAIN_WIDE */ -#define R367CAB_EQU_GAIN_WIDE 0xf490 -#define F367CAB_DFE_GAIN_WIDE 0xf49000f0 -#define F367CAB_FFE_GAIN_WIDE 0xf490000f - -/* EQU_GAIN_NARROW */ -#define R367CAB_EQU_GAIN_NARROW 0xf491 -#define F367CAB_DFE_GAIN_NARROW 0xf49100f0 -#define F367CAB_FFE_GAIN_NARROW 0xf491000f - -/* EQU_CTR_LPF_GAIN */ -#define R367CAB_EQU_CTR_LPF_GAIN 0xf492 -#define F367CAB_CTR_GTO 0xf4920080 -#define F367CAB_CTR_GDIR 0xf4920070 -#define F367CAB_SWEEP_EN 0xf4920008 -#define F367CAB_CTR_GINT 0xf4920007 - -/* EQU_CRL_LPF_GAIN */ -#define R367CAB_EQU_CRL_LPF_GAIN 0xf493 -#define F367CAB_CRL_GTO 0xf4930080 -#define F367CAB_CRL_GDIR 0xf4930070 -#define F367CAB_SWEEP_DIR 0xf4930008 -#define F367CAB_CRL_GINT 0xf4930007 - -/* EQU_GLOBAL_GAIN */ -#define R367CAB_EQU_GLOBAL_GAIN 0xf494 -#define F367CAB_CRL_GAIN 0xf49400f8 -#define F367CAB_CTR_INC_GAIN 0xf4940004 -#define F367CAB_CTR_FRAC 0xf4940003 - -/* EQU_CRL_LD_SEN */ -#define R367CAB_EQU_CRL_LD_SEN 0xf495 -#define F367CAB_CTR_BADPOINT_EN 0xf4950080 -#define F367CAB_CTR_GAIN 0xf4950070 -#define F367CAB_LIMANEN 0xf4950008 -#define F367CAB_CRL_LD_SEN 0xf4950007 - -/* EQU_CRL_LD_VAL */ -#define R367CAB_EQU_CRL_LD_VAL 0xf496 -#define F367CAB_CRL_BISTH_LIMIT 0xf4960080 -#define F367CAB_CARE_EN 0xf4960040 -#define F367CAB_CRL_LD_PER 0xf4960030 -#define F367CAB_CRL_LD_WST 0xf496000c -#define F367CAB_CRL_LD_TFS 0xf4960003 - -/* EQU_CRL_TFR */ -#define R367CAB_EQU_CRL_TFR 0xf497 -#define F367CAB_CRL_LD_TFR 0xf49700ff - -/* EQU_CRL_BISTH_LO */ -#define R367CAB_EQU_CRL_BISTH_LO 0xf498 -#define F367CAB_CRL_BISTH_LO 0xf49800ff - -/* EQU_CRL_BISTH_HI */ -#define R367CAB_EQU_CRL_BISTH_HI 0xf499 -#define F367CAB_CRL_BISTH_HI 0xf49900ff - -/* EQU_SWEEP_RANGE_LO */ -#define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a -#define F367CAB_SWEEP_RANGE_LO 0xf49a00ff - -/* EQU_SWEEP_RANGE_HI */ -#define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b -#define F367CAB_SWEEP_RANGE_HI 0xf49b00ff - -/* EQU_CRL_LIMITER */ -#define R367CAB_EQU_CRL_LIMITER 0xf49c -#define F367CAB_BISECTOR_EN 0xf49c0080 -#define F367CAB_PHEST128_EN 0xf49c0040 -#define F367CAB_CRL_LIM 0xf49c003f - -/* EQU_MODULUS_MAP */ -#define R367CAB_EQU_MODULUS_MAP 0xf49d -#define F367CAB_PNT_DEPTH 0xf49d00e0 -#define F367CAB_MODULUS_CMP 0xf49d001f - -/* EQU_PNT_GAIN */ -#define R367CAB_EQU_PNT_GAIN 0xf49e -#define F367CAB_PNT_EN 0xf49e0080 -#define F367CAB_MODULUSMAP_EN 0xf49e0040 -#define F367CAB_PNT_GAIN 0xf49e003f - -/* FEC_AC_CTR_0 */ -#define R367CAB_FEC_AC_CTR_0 0xf4a8 -#define F367CAB_BE_BYPASS 0xf4a80020 -#define F367CAB_REFRESH47 0xf4a80010 -#define F367CAB_CT_NBST 0xf4a80008 -#define F367CAB_TEI_ENA 0xf4a80004 -#define F367CAB_DS_ENA 0xf4a80002 -#define F367CAB_TSMF_EN 0xf4a80001 - -/* FEC_AC_CTR_1 */ -#define R367CAB_FEC_AC_CTR_1 0xf4a9 -#define F367CAB_DEINT_DEPTH 0xf4a900ff - -/* FEC_AC_CTR_2 */ -#define R367CAB_FEC_AC_CTR_2 0xf4aa -#define F367CAB_DEINT_M 0xf4aa00f8 -#define F367CAB_DIS_UNLOCK 0xf4aa0004 -#define F367CAB_DESCR_MODE 0xf4aa0003 - -/* FEC_AC_CTR_3 */ -#define R367CAB_FEC_AC_CTR_3 0xf4ab -#define F367CAB_DI_UNLOCK 0xf4ab0080 -#define F367CAB_DI_FREEZE 0xf4ab0040 -#define F367CAB_MISMATCH 0xf4ab0030 -#define F367CAB_ACQ_MODE 0xf4ab000c -#define F367CAB_TRK_MODE 0xf4ab0003 - -/* FEC_STATUS */ -#define R367CAB_FEC_STATUS 0xf4ac -#define F367CAB_DEINT_SMCNTR 0xf4ac00e0 -#define F367CAB_DEINT_SYNCSTATE 0xf4ac0018 -#define F367CAB_DEINT_SYNLOST 0xf4ac0004 -#define F367CAB_DESCR_SYNCSTATE 0xf4ac0002 - -/* RS_COUNTER_0 */ -#define R367CAB_RS_COUNTER_0 0xf4ae -#define F367CAB_BK_CT_L 0xf4ae00ff - -/* RS_COUNTER_1 */ -#define R367CAB_RS_COUNTER_1 0xf4af -#define F367CAB_BK_CT_H 0xf4af00ff - -/* RS_COUNTER_2 */ -#define R367CAB_RS_COUNTER_2 0xf4b0 -#define F367CAB_CORR_CT_L 0xf4b000ff - -/* RS_COUNTER_3 */ -#define R367CAB_RS_COUNTER_3 0xf4b1 -#define F367CAB_CORR_CT_H 0xf4b100ff - -/* RS_COUNTER_4 */ -#define R367CAB_RS_COUNTER_4 0xf4b2 -#define F367CAB_UNCORR_CT_L 0xf4b200ff - -/* RS_COUNTER_5 */ -#define R367CAB_RS_COUNTER_5 0xf4b3 -#define F367CAB_UNCORR_CT_H 0xf4b300ff - -/* BERT_0 */ -#define R367CAB_BERT_0 0xf4b4 -#define F367CAB_RS_NOCORR 0xf4b40004 -#define F367CAB_CT_HOLD 0xf4b40002 -#define F367CAB_CT_CLEAR 0xf4b40001 - -/* BERT_1 */ -#define R367CAB_BERT_1 0xf4b5 -#define F367CAB_BERT_ON 0xf4b50020 -#define F367CAB_BERT_ERR_SRC 0xf4b50010 -#define F367CAB_BERT_ERR_MODE 0xf4b50008 -#define F367CAB_BERT_NBYTE 0xf4b50007 - -/* BERT_2 */ -#define R367CAB_BERT_2 0xf4b6 -#define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff - -/* BERT_3 */ -#define R367CAB_BERT_3 0xf4b7 -#define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff - -/* OUTFORMAT_0 */ -#define R367CAB_OUTFORMAT_0 0xf4b8 -#define F367CAB_CLK_POLARITY 0xf4b80080 -#define F367CAB_FEC_TYPE 0xf4b80040 -#define F367CAB_SYNC_STRIP 0xf4b80008 -#define F367CAB_TS_SWAP 0xf4b80004 -#define F367CAB_OUTFORMAT 0xf4b80003 - -/* OUTFORMAT_1 */ -#define R367CAB_OUTFORMAT_1 0xf4b9 -#define F367CAB_CI_DIVRANGE 0xf4b900ff - -/* SMOOTHER_2 */ -#define R367CAB_SMOOTHER_2 0xf4be -#define F367CAB_FIFO_BYPASS 0xf4be0020 - -/* TSMF_CTRL_0 */ -#define R367CAB_TSMF_CTRL_0 0xf4c0 -#define F367CAB_TS_NUMBER 0xf4c0001e -#define F367CAB_SEL_MODE 0xf4c00001 - -/* TSMF_CTRL_1 */ -#define R367CAB_TSMF_CTRL_1 0xf4c1 -#define F367CAB_CHECK_ERROR_BIT 0xf4c10080 -#define F367CAB_CHCK_F_SYNC 0xf4c10040 -#define F367CAB_H_MODE 0xf4c10008 -#define F367CAB_D_V_MODE 0xf4c10004 -#define F367CAB_MODE 0xf4c10003 - -/* TSMF_CTRL_3 */ -#define R367CAB_TSMF_CTRL_3 0xf4c3 -#define F367CAB_SYNC_IN_COUNT 0xf4c300f0 -#define F367CAB_SYNC_OUT_COUNT 0xf4c3000f - -/* TS_ON_ID_0 */ -#define R367CAB_TS_ON_ID_0 0xf4c4 -#define F367CAB_TS_ID_L 0xf4c400ff - -/* TS_ON_ID_1 */ -#define R367CAB_TS_ON_ID_1 0xf4c5 -#define F367CAB_TS_ID_H 0xf4c500ff - -/* TS_ON_ID_2 */ -#define R367CAB_TS_ON_ID_2 0xf4c6 -#define F367CAB_ON_ID_L 0xf4c600ff - -/* TS_ON_ID_3 */ -#define R367CAB_TS_ON_ID_3 0xf4c7 -#define F367CAB_ON_ID_H 0xf4c700ff - -/* RE_STATUS_0 */ -#define R367CAB_RE_STATUS_0 0xf4c8 -#define F367CAB_RECEIVE_STATUS_L 0xf4c800ff - -/* RE_STATUS_1 */ -#define R367CAB_RE_STATUS_1 0xf4c9 -#define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff - -/* RE_STATUS_2 */ -#define R367CAB_RE_STATUS_2 0xf4ca -#define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff - -/* RE_STATUS_3 */ -#define R367CAB_RE_STATUS_3 0xf4cb -#define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f - -/* TS_STATUS_0 */ -#define R367CAB_TS_STATUS_0 0xf4cc -#define F367CAB_TS_STATUS_L 0xf4cc00ff - -/* TS_STATUS_1 */ -#define R367CAB_TS_STATUS_1 0xf4cd -#define F367CAB_TS_STATUS_H 0xf4cd007f - -/* TS_STATUS_2 */ -#define R367CAB_TS_STATUS_2 0xf4ce -#define F367CAB_ERROR 0xf4ce0080 -#define F367CAB_EMERGENCY 0xf4ce0040 -#define F367CAB_CRE_TS 0xf4ce0030 -#define F367CAB_VER 0xf4ce000e -#define F367CAB_M_LOCK 0xf4ce0001 - -/* TS_STATUS_3 */ -#define R367CAB_TS_STATUS_3 0xf4cf -#define F367CAB_UPDATE_READY 0xf4cf0080 -#define F367CAB_END_FRAME_HEADER 0xf4cf0040 -#define F367CAB_CONTCNT 0xf4cf0020 -#define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f - -/* T_O_ID_0 */ -#define R367CAB_T_O_ID_0 0xf4d0 -#define F367CAB_ON_ID_I_L 0xf4d000ff - -/* T_O_ID_1 */ -#define R367CAB_T_O_ID_1 0xf4d1 -#define F367CAB_ON_ID_I_H 0xf4d100ff - -/* T_O_ID_2 */ -#define R367CAB_T_O_ID_2 0xf4d2 -#define F367CAB_TS_ID_I_L 0xf4d200ff - -/* T_O_ID_3 */ -#define R367CAB_T_O_ID_3 0xf4d3 -#define F367CAB_TS_ID_I_H 0xf4d300ff - -#define STV0367CAB_NBREGS 187 - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,2331 +0,0 @@ -/* - * stv0367dd: STV0367 DVB-C/T demodulator driver - * - * Copyright (C) 2011 Digital Devices GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" -#include "stv0367dd.h" -#include "stv0367dd_regs.h" - -enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; -enum { QAM_MOD_QAM4 = 0, - QAM_MOD_QAM16, - QAM_MOD_QAM32, - QAM_MOD_QAM64, - QAM_MOD_QAM128, - QAM_MOD_QAM256, - QAM_MOD_QAM512, - QAM_MOD_QAM1024 -}; - -enum {QAM_SPECT_NORMAL, QAM_SPECT_INVERTED }; - -enum { - QAM_FEC_A = 1, /* J83 Annex A */ - QAM_FEC_B = (1<<1), /* J83 Annex B */ - QAM_FEC_C = (1<<2) /* J83 Annex C */ -}; - -enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; - -struct stv_state { -#ifdef USE_API3 - struct dvb_frontend c_frontend; - struct dvb_frontend t_frontend; -#else - struct dvb_frontend frontend; -#endif - fe_modulation_t modulation; - u32 symbol_rate; - u32 bandwidth; - struct device *dev; - - struct i2c_adapter *i2c; - u8 adr; - void *priv; - - struct mutex mutex; - struct mutex ctlock; - - u32 master_clock; - u32 adc_clock; - u8 ID; - u8 I2CRPT; - u32 omode; - u8 qam_inversion; - - s32 IF; - - s32 m_FECTimeOut; - s32 m_DemodTimeOut; - s32 m_SignalTimeOut; - s32 m_DemodLockTime; - s32 m_FFTTimeOut; - s32 m_TSTimeOut; - - bool m_bFirstTimeLock; - - u8 m_Save_QAM_AGC_CTL; - - enum EDemodState demod_state; - - u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k - u8 m_OFDM_Modulation; // - u8 m_OFDM_FEC; // - u8 m_OFDM_Guard; - - u32 ucblocks; - u32 ber; -}; - -struct init_table { - u16 adr; - u8 data; -}; - -struct init_table base_init[] = { - { R367_IOCFG0, 0x80 }, - { R367_DAC0R, 0x00 }, - { R367_IOCFG1, 0x00 }, - { R367_DAC1R, 0x00 }, - { R367_IOCFG2, 0x00 }, - { R367_SDFR, 0x00 }, - { R367_AUX_CLK, 0x00 }, - { R367_FREESYS1, 0x00 }, - { R367_FREESYS2, 0x00 }, - { R367_FREESYS3, 0x00 }, - { R367_GPIO_CFG, 0x55 }, - { R367_GPIO_CMD, 0x01 }, - { R367_TSTRES, 0x00 }, - { R367_ANACTRL, 0x00 }, - { R367_TSTBUS, 0x00 }, - { R367_RF_AGC2, 0x20 }, - { R367_ANADIGCTRL, 0x0b }, - { R367_PLLMDIV, 0x01 }, - { R367_PLLNDIV, 0x08 }, - { R367_PLLSETUP, 0x18 }, - { R367_DUAL_AD12, 0x04 }, - { R367_TSTBIST, 0x00 }, - { 0x0000, 0x00 } -}; - -struct init_table qam_init[] = { - { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 - { R367_QAM_CTRL_2, 0x03 }, - { R367_QAM_IT_STATUS1, 0x2b }, - { R367_QAM_IT_STATUS2, 0x08 }, - { R367_QAM_IT_EN1, 0x00 }, - { R367_QAM_IT_EN2, 0x00 }, - { R367_QAM_CTRL_STATUS, 0x04 }, - { R367_QAM_TEST_CTL, 0x00 }, - { R367_QAM_AGC_CTL, 0x73 }, - { R367_QAM_AGC_IF_CFG, 0x50 }, - { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze - { R367_QAM_AGC_PWM_CFG, 0x03 }, - { R367_QAM_AGC_PWR_REF_L, 0x5a }, - { R367_QAM_AGC_PWR_REF_H, 0x00 }, - { R367_QAM_AGC_RF_TH_L, 0xff }, - { R367_QAM_AGC_RF_TH_H, 0x07 }, - { R367_QAM_AGC_IF_LTH_L, 0x00 }, - { R367_QAM_AGC_IF_LTH_H, 0x08 }, - { R367_QAM_AGC_IF_HTH_L, 0xff }, - { R367_QAM_AGC_IF_HTH_H, 0x07 }, - { R367_QAM_AGC_PWR_RD_L, 0xa0 }, - { R367_QAM_AGC_PWR_RD_M, 0xe9 }, - { R367_QAM_AGC_PWR_RD_H, 0x03 }, - { R367_QAM_AGC_PWM_IFCMD_L, 0xe4 }, - { R367_QAM_AGC_PWM_IFCMD_H, 0x00 }, - { R367_QAM_AGC_PWM_RFCMD_L, 0xff }, - { R367_QAM_AGC_PWM_RFCMD_H, 0x07 }, - { R367_QAM_IQDEM_CFG, 0x01 }, - { R367_QAM_MIX_NCO_LL, 0x22 }, - { R367_QAM_MIX_NCO_HL, 0x96 }, - { R367_QAM_MIX_NCO_HH, 0x55 }, - { R367_QAM_SRC_NCO_LL, 0xff }, - { R367_QAM_SRC_NCO_LH, 0x0c }, - { R367_QAM_SRC_NCO_HL, 0xf5 }, - { R367_QAM_SRC_NCO_HH, 0x20 }, - { R367_QAM_IQDEM_GAIN_SRC_L, 0x06 }, - { R367_QAM_IQDEM_GAIN_SRC_H, 0x01 }, - { R367_QAM_IQDEM_DCRM_CFG_LL, 0xfe }, - { R367_QAM_IQDEM_DCRM_CFG_LH, 0xff }, - { R367_QAM_IQDEM_DCRM_CFG_HL, 0x0f }, - { R367_QAM_IQDEM_DCRM_CFG_HH, 0x00 }, - { R367_QAM_IQDEM_ADJ_COEFF0, 0x34 }, - { R367_QAM_IQDEM_ADJ_COEFF1, 0xae }, - { R367_QAM_IQDEM_ADJ_COEFF2, 0x46 }, - { R367_QAM_IQDEM_ADJ_COEFF3, 0x77 }, - { R367_QAM_IQDEM_ADJ_COEFF4, 0x96 }, - { R367_QAM_IQDEM_ADJ_COEFF5, 0x69 }, - { R367_QAM_IQDEM_ADJ_COEFF6, 0xc7 }, - { R367_QAM_IQDEM_ADJ_COEFF7, 0x01 }, - { R367_QAM_IQDEM_ADJ_EN, 0x04 }, - { R367_QAM_IQDEM_ADJ_AGC_REF, 0x94 }, - { R367_QAM_ALLPASSFILT1, 0xc9 }, - { R367_QAM_ALLPASSFILT2, 0x2d }, - { R367_QAM_ALLPASSFILT3, 0xa3 }, - { R367_QAM_ALLPASSFILT4, 0xfb }, - { R367_QAM_ALLPASSFILT5, 0xf6 }, - { R367_QAM_ALLPASSFILT6, 0x45 }, - { R367_QAM_ALLPASSFILT7, 0x6f }, - { R367_QAM_ALLPASSFILT8, 0x7e }, - { R367_QAM_ALLPASSFILT9, 0x05 }, - { R367_QAM_ALLPASSFILT10, 0x0a }, - { R367_QAM_ALLPASSFILT11, 0x51 }, - { R367_QAM_TRL_AGC_CFG, 0x20 }, - { R367_QAM_TRL_LPF_CFG, 0x28 }, - { R367_QAM_TRL_LPF_ACQ_GAIN, 0x44 }, - { R367_QAM_TRL_LPF_TRK_GAIN, 0x22 }, - { R367_QAM_TRL_LPF_OUT_GAIN, 0x03 }, - { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, - { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, - { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, - { R367_QAM_IQ_QAM, 0x01 }, - { R367_QAM_FSM_STATE, 0xa0 }, - { R367_QAM_FSM_CTL, 0x08 }, - { R367_QAM_FSM_STS, 0x0c }, - { R367_QAM_FSM_SNR0_HTH, 0x00 }, - { R367_QAM_FSM_SNR1_HTH, 0x00 }, - { R367_QAM_FSM_SNR2_HTH, 0x00 }, - { R367_QAM_FSM_SNR0_LTH, 0x00 }, - { R367_QAM_FSM_SNR1_LTH, 0x00 }, - { R367_QAM_FSM_EQA1_HTH, 0x00 }, - { R367_QAM_FSM_TEMPO, 0x32 }, - { R367_QAM_FSM_CONFIG, 0x03 }, - { R367_QAM_EQU_I_TESTTAP_L, 0x11 }, - { R367_QAM_EQU_I_TESTTAP_M, 0x00 }, - { R367_QAM_EQU_I_TESTTAP_H, 0x00 }, - { R367_QAM_EQU_TESTAP_CFG, 0x00 }, - { R367_QAM_EQU_Q_TESTTAP_L, 0xff }, - { R367_QAM_EQU_Q_TESTTAP_M, 0x00 }, - { R367_QAM_EQU_Q_TESTTAP_H, 0x00 }, - { R367_QAM_EQU_TAP_CTRL, 0x00 }, - { R367_QAM_EQU_CTR_CRL_CONTROL_L, 0x11 }, - { R367_QAM_EQU_CTR_CRL_CONTROL_H, 0x05 }, - { R367_QAM_EQU_CTR_HIPOW_L, 0x00 }, - { R367_QAM_EQU_CTR_HIPOW_H, 0x00 }, - { R367_QAM_EQU_I_EQU_LO, 0xef }, - { R367_QAM_EQU_I_EQU_HI, 0x00 }, - { R367_QAM_EQU_Q_EQU_LO, 0xee }, - { R367_QAM_EQU_Q_EQU_HI, 0x00 }, - { R367_QAM_EQU_MAPPER, 0xc5 }, - { R367_QAM_EQU_SWEEP_RATE, 0x80 }, - { R367_QAM_EQU_SNR_LO, 0x64 }, - { R367_QAM_EQU_SNR_HI, 0x03 }, - { R367_QAM_EQU_GAMMA_LO, 0x00 }, - { R367_QAM_EQU_GAMMA_HI, 0x00 }, - { R367_QAM_EQU_ERR_GAIN, 0x36 }, - { R367_QAM_EQU_RADIUS, 0xaa }, - { R367_QAM_EQU_FFE_MAINTAP, 0x00 }, - { R367_QAM_EQU_FFE_LEAKAGE, 0x63 }, - { R367_QAM_EQU_FFE_MAINTAP_POS, 0xdf }, - { R367_QAM_EQU_GAIN_WIDE, 0x88 }, - { R367_QAM_EQU_GAIN_NARROW, 0x41 }, - { R367_QAM_EQU_CTR_LPF_GAIN, 0xd1 }, - { R367_QAM_EQU_CRL_LPF_GAIN, 0xa7 }, - { R367_QAM_EQU_GLOBAL_GAIN, 0x06 }, - { R367_QAM_EQU_CRL_LD_SEN, 0x85 }, - { R367_QAM_EQU_CRL_LD_VAL, 0xe2 }, - { R367_QAM_EQU_CRL_TFR, 0x20 }, - { R367_QAM_EQU_CRL_BISTH_LO, 0x00 }, - { R367_QAM_EQU_CRL_BISTH_HI, 0x00 }, - { R367_QAM_EQU_SWEEP_RANGE_LO, 0x00 }, - { R367_QAM_EQU_SWEEP_RANGE_HI, 0x00 }, - { R367_QAM_EQU_CRL_LIMITER, 0x40 }, - { R367_QAM_EQU_MODULUS_MAP, 0x90 }, - { R367_QAM_EQU_PNT_GAIN, 0xa7 }, - { R367_QAM_FEC_AC_CTR_0, 0x16 }, - { R367_QAM_FEC_AC_CTR_1, 0x0b }, - { R367_QAM_FEC_AC_CTR_2, 0x88 }, - { R367_QAM_FEC_AC_CTR_3, 0x02 }, - { R367_QAM_FEC_STATUS, 0x12 }, - { R367_QAM_RS_COUNTER_0, 0x7d }, - { R367_QAM_RS_COUNTER_1, 0xd0 }, - { R367_QAM_RS_COUNTER_2, 0x19 }, - { R367_QAM_RS_COUNTER_3, 0x0b }, - { R367_QAM_RS_COUNTER_4, 0xa3 }, - { R367_QAM_RS_COUNTER_5, 0x00 }, - { R367_QAM_BERT_0, 0x01 }, - { R367_QAM_BERT_1, 0x25 }, - { R367_QAM_BERT_2, 0x41 }, - { R367_QAM_BERT_3, 0x39 }, - { R367_QAM_OUTFORMAT_0, 0xc2 }, - { R367_QAM_OUTFORMAT_1, 0x22 }, - { R367_QAM_SMOOTHER_2, 0x28 }, - { R367_QAM_TSMF_CTRL_0, 0x01 }, - { R367_QAM_TSMF_CTRL_1, 0xc6 }, - { R367_QAM_TSMF_CTRL_3, 0x43 }, - { R367_QAM_TS_ON_ID_0, 0x00 }, - { R367_QAM_TS_ON_ID_1, 0x00 }, - { R367_QAM_TS_ON_ID_2, 0x00 }, - { R367_QAM_TS_ON_ID_3, 0x00 }, - { R367_QAM_RE_STATUS_0, 0x00 }, - { R367_QAM_RE_STATUS_1, 0x00 }, - { R367_QAM_RE_STATUS_2, 0x00 }, - { R367_QAM_RE_STATUS_3, 0x00 }, - { R367_QAM_TS_STATUS_0, 0x00 }, - { R367_QAM_TS_STATUS_1, 0x00 }, - { R367_QAM_TS_STATUS_2, 0xa0 }, - { R367_QAM_TS_STATUS_3, 0x00 }, - { R367_QAM_T_O_ID_0, 0x00 }, - { R367_QAM_T_O_ID_1, 0x00 }, - { R367_QAM_T_O_ID_2, 0x00 }, - { R367_QAM_T_O_ID_3, 0x00 }, - { 0x0000, 0x00 } // EOT -}; - -struct init_table ofdm_init[] = { - //{R367_OFDM_ID ,0x60}, - //{R367_OFDM_I2CRPT ,0x22}, - //{R367_OFDM_TOPCTRL ,0x02}, - //{R367_OFDM_IOCFG0 ,0x40}, - //{R367_OFDM_DAC0R ,0x00}, - //{R367_OFDM_IOCFG1 ,0x00}, - //{R367_OFDM_DAC1R ,0x00}, - //{R367_OFDM_IOCFG2 ,0x62}, - //{R367_OFDM_SDFR ,0x00}, - //{R367_OFDM_STATUS ,0xf8}, - //{R367_OFDM_AUX_CLK ,0x0a}, - //{R367_OFDM_FREESYS1 ,0x00}, - //{R367_OFDM_FREESYS2 ,0x00}, - //{R367_OFDM_FREESYS3 ,0x00}, - //{R367_OFDM_GPIO_CFG ,0x55}, - //{R367_OFDM_GPIO_CMD ,0x00}, - {R367_OFDM_AGC2MAX ,0xff}, - {R367_OFDM_AGC2MIN ,0x00}, - {R367_OFDM_AGC1MAX ,0xff}, - {R367_OFDM_AGC1MIN ,0x00}, - {R367_OFDM_AGCR ,0xbc}, - {R367_OFDM_AGC2TH ,0x00}, - //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM - {R367_OFDM_AGCCTRL1 ,0x85}, - {R367_OFDM_AGCCTRL2 ,0x1f}, - {R367_OFDM_AGC1VAL1 ,0x00}, - {R367_OFDM_AGC1VAL2 ,0x00}, - {R367_OFDM_AGC2VAL1 ,0x6f}, - {R367_OFDM_AGC2VAL2 ,0x05}, - {R367_OFDM_AGC2PGA ,0x00}, - {R367_OFDM_OVF_RATE1 ,0x00}, - {R367_OFDM_OVF_RATE2 ,0x00}, - {R367_OFDM_GAIN_SRC1 ,0x2b}, - {R367_OFDM_GAIN_SRC2 ,0x04}, - {R367_OFDM_INC_DEROT1 ,0x55}, - {R367_OFDM_INC_DEROT2 ,0x55}, - {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, - {R367_OFDM_PPM_CPAMP_INV ,0x00}, - {R367_OFDM_FREESTFE_1 ,0x00}, - {R367_OFDM_FREESTFE_2 ,0x1c}, - {R367_OFDM_DCOFFSET ,0x00}, - {R367_OFDM_EN_PROCESS ,0x05}, - {R367_OFDM_SDI_SMOOTHER ,0x80}, - {R367_OFDM_FE_LOOP_OPEN ,0x1c}, - {R367_OFDM_FREQOFF1 ,0x00}, - {R367_OFDM_FREQOFF2 ,0x00}, - {R367_OFDM_FREQOFF3 ,0x00}, - {R367_OFDM_TIMOFF1 ,0x00}, - {R367_OFDM_TIMOFF2 ,0x00}, - {R367_OFDM_EPQ ,0x02}, - {R367_OFDM_EPQAUTO ,0x01}, - {R367_OFDM_SYR_UPDATE ,0xf5}, - {R367_OFDM_CHPFREE ,0x00}, - {R367_OFDM_PPM_STATE_MAC ,0x23}, - {R367_OFDM_INR_THRESHOLD ,0xff}, - {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, - {R367_OFDM_EPQ_CFG ,0x00}, - {R367_OFDM_EPQ_STATUS ,0x01}, - {R367_OFDM_AUTORELOCK ,0x81}, - {R367_OFDM_BER_THR_VMSB ,0x00}, - {R367_OFDM_BER_THR_MSB ,0x00}, - {R367_OFDM_BER_THR_LSB ,0x00}, - {R367_OFDM_CCD ,0x83}, - {R367_OFDM_SPECTR_CFG ,0x00}, - {R367_OFDM_CHC_DUMMY ,0x18}, - {R367_OFDM_INC_CTL ,0x88}, - {R367_OFDM_INCTHRES_COR1 ,0xb4}, - {R367_OFDM_INCTHRES_COR2 ,0x96}, - {R367_OFDM_INCTHRES_DET1 ,0x0e}, - {R367_OFDM_INCTHRES_DET2 ,0x11}, - {R367_OFDM_IIR_CELLNB ,0x8d}, - {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, - {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, - {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, - {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, - {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, - {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, - {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, - {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, - {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, - {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, - {R367_OFDM_FEPATH_CFG ,0x00}, - {R367_OFDM_PMC1_FUNC ,0x65}, - {R367_OFDM_PMC1_FOR ,0x00}, - {R367_OFDM_PMC2_FUNC ,0x00}, - {R367_OFDM_STATUS_ERR_DA ,0xe0}, - {R367_OFDM_DIG_AGC_R ,0xfe}, - {R367_OFDM_COMAGC_TARMSB ,0x0b}, - {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, - {R367_OFDM_COM_AGC_CFG ,0x3e}, - {R367_OFDM_COM_AGC_GAIN1 ,0x39}, - {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, - {R367_OFDM_LOCK_DET_MSB ,0x01}, - {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, - {R367_OFDM_AUT_GAIN_EN ,0xf4}, - {R367_OFDM_AUT_CFG ,0xf0}, - {R367_OFDM_LOCKN ,0x23}, - {R367_OFDM_INT_X_3 ,0x00}, - {R367_OFDM_INT_X_2 ,0x03}, - {R367_OFDM_INT_X_1 ,0x8d}, - {R367_OFDM_INT_X_0 ,0xa0}, - {R367_OFDM_MIN_ERRX_MSB ,0x00}, - {R367_OFDM_COR_CTL ,0x00}, - {R367_OFDM_COR_STAT ,0xf6}, - {R367_OFDM_COR_INTEN ,0x00}, - {R367_OFDM_COR_INTSTAT ,0x3f}, - {R367_OFDM_COR_MODEGUARD ,0x03}, - {R367_OFDM_AGC_CTL ,0x08}, - {R367_OFDM_AGC_MANUAL1 ,0x00}, - {R367_OFDM_AGC_MANUAL2 ,0x00}, - {R367_OFDM_AGC_TARG ,0x16}, - {R367_OFDM_AGC_GAIN1 ,0x53}, - {R367_OFDM_AGC_GAIN2 ,0x1d}, - {R367_OFDM_RESERVED_1 ,0x00}, - {R367_OFDM_RESERVED_2 ,0x00}, - {R367_OFDM_RESERVED_3 ,0x00}, - {R367_OFDM_CAS_CTL ,0x44}, - {R367_OFDM_CAS_FREQ ,0xb3}, - {R367_OFDM_CAS_DAGCGAIN ,0x12}, - {R367_OFDM_SYR_CTL ,0x04}, - {R367_OFDM_SYR_STAT ,0x10}, - {R367_OFDM_SYR_NCO1 ,0x00}, - {R367_OFDM_SYR_NCO2 ,0x00}, - {R367_OFDM_SYR_OFFSET1 ,0x00}, - {R367_OFDM_SYR_OFFSET2 ,0x00}, - {R367_OFDM_FFT_CTL ,0x00}, - {R367_OFDM_SCR_CTL ,0x70}, - {R367_OFDM_PPM_CTL1 ,0xf8}, - {R367_OFDM_TRL_CTL ,0xac}, - {R367_OFDM_TRL_NOMRATE1 ,0x1e}, - {R367_OFDM_TRL_NOMRATE2 ,0x58}, - {R367_OFDM_TRL_TIME1 ,0x1d}, - {R367_OFDM_TRL_TIME2 ,0xfc}, - {R367_OFDM_CRL_CTL ,0x24}, - {R367_OFDM_CRL_FREQ1 ,0xad}, - {R367_OFDM_CRL_FREQ2 ,0x9d}, - {R367_OFDM_CRL_FREQ3 ,0xff}, - {R367_OFDM_CHC_CTL ,0x01}, - {R367_OFDM_CHC_SNR ,0xf0}, - {R367_OFDM_BDI_CTL ,0x00}, - {R367_OFDM_DMP_CTL ,0x00}, - {R367_OFDM_TPS_RCVD1 ,0x30}, - {R367_OFDM_TPS_RCVD2 ,0x02}, - {R367_OFDM_TPS_RCVD3 ,0x01}, - {R367_OFDM_TPS_RCVD4 ,0x00}, - {R367_OFDM_TPS_ID_CELL1 ,0x00}, - {R367_OFDM_TPS_ID_CELL2 ,0x00}, - {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, - {R367_OFDM_TPS_SET2 ,0x02}, - {R367_OFDM_TPS_SET3 ,0x01}, - {R367_OFDM_TPS_CTL ,0x00}, - {R367_OFDM_CTL_FFTOSNUM ,0x34}, - {R367_OFDM_TESTSELECT ,0x09}, - {R367_OFDM_MSC_REV ,0x0a}, - {R367_OFDM_PIR_CTL ,0x00}, - {R367_OFDM_SNR_CARRIER1 ,0xa1}, - {R367_OFDM_SNR_CARRIER2 ,0x9a}, - {R367_OFDM_PPM_CPAMP ,0x2c}, - {R367_OFDM_TSM_AP0 ,0x00}, - {R367_OFDM_TSM_AP1 ,0x00}, - {R367_OFDM_TSM_AP2 ,0x00}, - {R367_OFDM_TSM_AP3 ,0x00}, - {R367_OFDM_TSM_AP4 ,0x00}, - {R367_OFDM_TSM_AP5 ,0x00}, - {R367_OFDM_TSM_AP6 ,0x00}, - {R367_OFDM_TSM_AP7 ,0x00}, - //{R367_OFDM_TSTRES ,0x00}, - //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ - //{R367_OFDM_TSTBUS ,0x00}, - //{R367_OFDM_TSTRATE ,0x00}, - {R367_OFDM_CONSTMODE ,0x01}, - {R367_OFDM_CONSTCARR1 ,0x00}, - {R367_OFDM_CONSTCARR2 ,0x00}, - {R367_OFDM_ICONSTEL ,0x0a}, - {R367_OFDM_QCONSTEL ,0x15}, - {R367_OFDM_TSTBISTRES0 ,0x00}, - {R367_OFDM_TSTBISTRES1 ,0x00}, - {R367_OFDM_TSTBISTRES2 ,0x28}, - {R367_OFDM_TSTBISTRES3 ,0x00}, - //{R367_OFDM_RF_AGC1 ,0xff}, - //{R367_OFDM_RF_AGC2 ,0x83}, - //{R367_OFDM_ANADIGCTRL ,0x19}, - //{R367_OFDM_PLLMDIV ,0x0c}, - //{R367_OFDM_PLLNDIV ,0x55}, - //{R367_OFDM_PLLSETUP ,0x18}, - //{R367_OFDM_DUAL_AD12 ,0x00}, - //{R367_OFDM_TSTBIST ,0x00}, - //{R367_OFDM_PAD_COMP_CTRL ,0x00}, - //{R367_OFDM_PAD_COMP_WR ,0x00}, - //{R367_OFDM_PAD_COMP_RD ,0xe0}, - {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, - {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, - {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, - {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, - {R367_OFDM_SYR_FLAG ,0x00}, - {R367_OFDM_CRL_TARGET1 ,0x00}, - {R367_OFDM_CRL_TARGET2 ,0x00}, - {R367_OFDM_CRL_TARGET3 ,0x00}, - {R367_OFDM_CRL_TARGET4 ,0x00}, - {R367_OFDM_CRL_FLAG ,0x00}, - {R367_OFDM_TRL_TARGET1 ,0x00}, - {R367_OFDM_TRL_TARGET2 ,0x00}, - {R367_OFDM_TRL_CHC ,0x00}, - {R367_OFDM_CHC_SNR_TARG ,0x00}, - {R367_OFDM_TOP_TRACK ,0x00}, - {R367_OFDM_TRACKER_FREE1 ,0x00}, - {R367_OFDM_ERROR_CRL1 ,0x00}, - {R367_OFDM_ERROR_CRL2 ,0x00}, - {R367_OFDM_ERROR_CRL3 ,0x00}, - {R367_OFDM_ERROR_CRL4 ,0x00}, - {R367_OFDM_DEC_NCO1 ,0x2c}, - {R367_OFDM_DEC_NCO2 ,0x0f}, - {R367_OFDM_DEC_NCO3 ,0x20}, - {R367_OFDM_SNR ,0xf1}, - {R367_OFDM_SYR_FFTADJ1 ,0x00}, - {R367_OFDM_SYR_FFTADJ2 ,0x00}, - {R367_OFDM_SYR_CHCADJ1 ,0x00}, - {R367_OFDM_SYR_CHCADJ2 ,0x00}, - {R367_OFDM_SYR_OFF ,0x00}, - {R367_OFDM_PPM_OFFSET1 ,0x00}, - {R367_OFDM_PPM_OFFSET2 ,0x03}, - {R367_OFDM_TRACKER_FREE2 ,0x00}, - {R367_OFDM_DEBG_LT10 ,0x00}, - {R367_OFDM_DEBG_LT11 ,0x00}, - {R367_OFDM_DEBG_LT12 ,0x00}, - {R367_OFDM_DEBG_LT13 ,0x00}, - {R367_OFDM_DEBG_LT14 ,0x00}, - {R367_OFDM_DEBG_LT15 ,0x00}, - {R367_OFDM_DEBG_LT16 ,0x00}, - {R367_OFDM_DEBG_LT17 ,0x00}, - {R367_OFDM_DEBG_LT18 ,0x00}, - {R367_OFDM_DEBG_LT19 ,0x00}, - {R367_OFDM_DEBG_LT1A ,0x00}, - {R367_OFDM_DEBG_LT1B ,0x00}, - {R367_OFDM_DEBG_LT1C ,0x00}, - {R367_OFDM_DEBG_LT1D ,0x00}, - {R367_OFDM_DEBG_LT1E ,0x00}, - {R367_OFDM_DEBG_LT1F ,0x00}, - {R367_OFDM_RCCFGH ,0x00}, - {R367_OFDM_RCCFGM ,0x00}, - {R367_OFDM_RCCFGL ,0x00}, - {R367_OFDM_RCINSDELH ,0x00}, - {R367_OFDM_RCINSDELM ,0x00}, - {R367_OFDM_RCINSDELL ,0x00}, - {R367_OFDM_RCSTATUS ,0x00}, - {R367_OFDM_RCSPEED ,0x6f}, - {R367_OFDM_RCDEBUGM ,0xe7}, - {R367_OFDM_RCDEBUGL ,0x9b}, - {R367_OFDM_RCOBSCFG ,0x00}, - {R367_OFDM_RCOBSM ,0x00}, - {R367_OFDM_RCOBSL ,0x00}, - {R367_OFDM_RCFECSPY ,0x00}, - {R367_OFDM_RCFSPYCFG ,0x00}, - {R367_OFDM_RCFSPYDATA ,0x00}, - {R367_OFDM_RCFSPYOUT ,0x00}, - {R367_OFDM_RCFSTATUS ,0x00}, - {R367_OFDM_RCFGOODPACK ,0x00}, - {R367_OFDM_RCFPACKCNT ,0x00}, - {R367_OFDM_RCFSPYMISC ,0x00}, - {R367_OFDM_RCFBERCPT4 ,0x00}, - {R367_OFDM_RCFBERCPT3 ,0x00}, - {R367_OFDM_RCFBERCPT2 ,0x00}, - {R367_OFDM_RCFBERCPT1 ,0x00}, - {R367_OFDM_RCFBERCPT0 ,0x00}, - {R367_OFDM_RCFBERERR2 ,0x00}, - {R367_OFDM_RCFBERERR1 ,0x00}, - {R367_OFDM_RCFBERERR0 ,0x00}, - {R367_OFDM_RCFSTATESM ,0x00}, - {R367_OFDM_RCFSTATESL ,0x00}, - {R367_OFDM_RCFSPYBER ,0x00}, - {R367_OFDM_RCFSPYDISTM ,0x00}, - {R367_OFDM_RCFSPYDISTL ,0x00}, - {R367_OFDM_RCFSPYOBS7 ,0x00}, - {R367_OFDM_RCFSPYOBS6 ,0x00}, - {R367_OFDM_RCFSPYOBS5 ,0x00}, - {R367_OFDM_RCFSPYOBS4 ,0x00}, - {R367_OFDM_RCFSPYOBS3 ,0x00}, - {R367_OFDM_RCFSPYOBS2 ,0x00}, - {R367_OFDM_RCFSPYOBS1 ,0x00}, - {R367_OFDM_RCFSPYOBS0 ,0x00}, - //{R367_OFDM_TSGENERAL ,0x00}, - //{R367_OFDM_RC1SPEED ,0x6f}, - //{R367_OFDM_TSGSTATUS ,0x18}, - {R367_OFDM_FECM ,0x01}, - {R367_OFDM_VTH12 ,0xff}, - {R367_OFDM_VTH23 ,0xa1}, - {R367_OFDM_VTH34 ,0x64}, - {R367_OFDM_VTH56 ,0x40}, - {R367_OFDM_VTH67 ,0x00}, - {R367_OFDM_VTH78 ,0x2c}, - {R367_OFDM_VITCURPUN ,0x12}, - {R367_OFDM_VERROR ,0x01}, - {R367_OFDM_PRVIT ,0x3f}, - {R367_OFDM_VAVSRVIT ,0x00}, - {R367_OFDM_VSTATUSVIT ,0xbd}, - {R367_OFDM_VTHINUSE ,0xa1}, - {R367_OFDM_KDIV12 ,0x20}, - {R367_OFDM_KDIV23 ,0x40}, - {R367_OFDM_KDIV34 ,0x20}, - {R367_OFDM_KDIV56 ,0x30}, - {R367_OFDM_KDIV67 ,0x00}, - {R367_OFDM_KDIV78 ,0x30}, - {R367_OFDM_SIGPOWER ,0x54}, - {R367_OFDM_DEMAPVIT ,0x40}, - {R367_OFDM_VITSCALE ,0x00}, - {R367_OFDM_FFEC1PRG ,0x00}, - {R367_OFDM_FVITCURPUN ,0x12}, - {R367_OFDM_FVERROR ,0x01}, - {R367_OFDM_FVSTATUSVIT ,0xbd}, - {R367_OFDM_DEBUG_LT1 ,0x00}, - {R367_OFDM_DEBUG_LT2 ,0x00}, - {R367_OFDM_DEBUG_LT3 ,0x00}, - {R367_OFDM_TSTSFMET ,0x00}, - {R367_OFDM_SELOUT ,0x00}, - {R367_OFDM_TSYNC ,0x00}, - {R367_OFDM_TSTERR ,0x00}, - {R367_OFDM_TSFSYNC ,0x00}, - {R367_OFDM_TSTSFERR ,0x00}, - {R367_OFDM_TSTTSSF1 ,0x01}, - {R367_OFDM_TSTTSSF2 ,0x1f}, - {R367_OFDM_TSTTSSF3 ,0x00}, - {R367_OFDM_TSTTS1 ,0x00}, - {R367_OFDM_TSTTS2 ,0x1f}, - {R367_OFDM_TSTTS3 ,0x01}, - {R367_OFDM_TSTTS4 ,0x00}, - {R367_OFDM_TSTTSRC ,0x00}, - {R367_OFDM_TSTTSRS ,0x00}, - {R367_OFDM_TSSTATEM ,0xb0}, - {R367_OFDM_TSSTATEL ,0x40}, - {R367_OFDM_TSCFGH ,0x80}, - {R367_OFDM_TSCFGM ,0x00}, - {R367_OFDM_TSCFGL ,0x20}, - {R367_OFDM_TSSYNC ,0x00}, - {R367_OFDM_TSINSDELH ,0x00}, - {R367_OFDM_TSINSDELM ,0x00}, - {R367_OFDM_TSINSDELL ,0x00}, - {R367_OFDM_TSDIVN ,0x03}, - {R367_OFDM_TSDIVPM ,0x00}, - {R367_OFDM_TSDIVPL ,0x00}, - {R367_OFDM_TSDIVQM ,0x00}, - {R367_OFDM_TSDIVQL ,0x00}, - {R367_OFDM_TSDILSTKM ,0x00}, - {R367_OFDM_TSDILSTKL ,0x00}, - {R367_OFDM_TSSPEED ,0x6f}, - {R367_OFDM_TSSTATUS ,0x81}, - {R367_OFDM_TSSTATUS2 ,0x6a}, - {R367_OFDM_TSBITRATEM ,0x0f}, - {R367_OFDM_TSBITRATEL ,0xc6}, - {R367_OFDM_TSPACKLENM ,0x00}, - {R367_OFDM_TSPACKLENL ,0xfc}, - {R367_OFDM_TSBLOCLENM ,0x0a}, - {R367_OFDM_TSBLOCLENL ,0x80}, - {R367_OFDM_TSDLYH ,0x90}, - {R367_OFDM_TSDLYM ,0x68}, - {R367_OFDM_TSDLYL ,0x01}, - {R367_OFDM_TSNPDAV ,0x00}, - {R367_OFDM_TSBUFSTATH ,0x00}, - {R367_OFDM_TSBUFSTATM ,0x00}, - {R367_OFDM_TSBUFSTATL ,0x00}, - {R367_OFDM_TSDEBUGM ,0xcf}, - {R367_OFDM_TSDEBUGL ,0x1e}, - {R367_OFDM_TSDLYSETH ,0x00}, - {R367_OFDM_TSDLYSETM ,0x68}, - {R367_OFDM_TSDLYSETL ,0x00}, - {R367_OFDM_TSOBSCFG ,0x00}, - {R367_OFDM_TSOBSM ,0x47}, - {R367_OFDM_TSOBSL ,0x1f}, - {R367_OFDM_ERRCTRL1 ,0x95}, - {R367_OFDM_ERRCNT1H ,0x80}, - {R367_OFDM_ERRCNT1M ,0x00}, - {R367_OFDM_ERRCNT1L ,0x00}, - {R367_OFDM_ERRCTRL2 ,0x95}, - {R367_OFDM_ERRCNT2H ,0x00}, - {R367_OFDM_ERRCNT2M ,0x00}, - {R367_OFDM_ERRCNT2L ,0x00}, - {R367_OFDM_FECSPY ,0x88}, - {R367_OFDM_FSPYCFG ,0x2c}, - {R367_OFDM_FSPYDATA ,0x3a}, - {R367_OFDM_FSPYOUT ,0x06}, - {R367_OFDM_FSTATUS ,0x61}, - {R367_OFDM_FGOODPACK ,0xff}, - {R367_OFDM_FPACKCNT ,0xff}, - {R367_OFDM_FSPYMISC ,0x66}, - {R367_OFDM_FBERCPT4 ,0x00}, - {R367_OFDM_FBERCPT3 ,0x00}, - {R367_OFDM_FBERCPT2 ,0x36}, - {R367_OFDM_FBERCPT1 ,0x36}, - {R367_OFDM_FBERCPT0 ,0x14}, - {R367_OFDM_FBERERR2 ,0x00}, - {R367_OFDM_FBERERR1 ,0x03}, - {R367_OFDM_FBERERR0 ,0x28}, - {R367_OFDM_FSTATESM ,0x00}, - {R367_OFDM_FSTATESL ,0x02}, - {R367_OFDM_FSPYBER ,0x00}, - {R367_OFDM_FSPYDISTM ,0x01}, - {R367_OFDM_FSPYDISTL ,0x9f}, - {R367_OFDM_FSPYOBS7 ,0xc9}, - {R367_OFDM_FSPYOBS6 ,0x99}, - {R367_OFDM_FSPYOBS5 ,0x08}, - {R367_OFDM_FSPYOBS4 ,0xec}, - {R367_OFDM_FSPYOBS3 ,0x01}, - {R367_OFDM_FSPYOBS2 ,0x0f}, - {R367_OFDM_FSPYOBS1 ,0xf5}, - {R367_OFDM_FSPYOBS0 ,0x08}, - {R367_OFDM_SFDEMAP ,0x40}, - {R367_OFDM_SFERROR ,0x00}, - {R367_OFDM_SFAVSR ,0x30}, - {R367_OFDM_SFECSTATUS ,0xcc}, - {R367_OFDM_SFKDIV12 ,0x20}, - {R367_OFDM_SFKDIV23 ,0x40}, - {R367_OFDM_SFKDIV34 ,0x20}, - {R367_OFDM_SFKDIV56 ,0x20}, - {R367_OFDM_SFKDIV67 ,0x00}, - {R367_OFDM_SFKDIV78 ,0x20}, - {R367_OFDM_SFDILSTKM ,0x00}, - {R367_OFDM_SFDILSTKL ,0x00}, - {R367_OFDM_SFSTATUS ,0xb5}, - {R367_OFDM_SFDLYH ,0x90}, - {R367_OFDM_SFDLYM ,0x60}, - {R367_OFDM_SFDLYL ,0x01}, - {R367_OFDM_SFDLYSETH ,0xc0}, - {R367_OFDM_SFDLYSETM ,0x60}, - {R367_OFDM_SFDLYSETL ,0x00}, - {R367_OFDM_SFOBSCFG ,0x00}, - {R367_OFDM_SFOBSM ,0x47}, - {R367_OFDM_SFOBSL ,0x05}, - {R367_OFDM_SFECINFO ,0x40}, - {R367_OFDM_SFERRCTRL ,0x74}, - {R367_OFDM_SFERRCNTH ,0x80}, - {R367_OFDM_SFERRCNTM ,0x00}, - {R367_OFDM_SFERRCNTL ,0x00}, - {R367_OFDM_SYMBRATEM ,0x2f}, - {R367_OFDM_SYMBRATEL ,0x50}, - {R367_OFDM_SYMBSTATUS ,0x7f}, - {R367_OFDM_SYMBCFG ,0x00}, - {R367_OFDM_SYMBFIFOM ,0xf4}, - {R367_OFDM_SYMBFIFOL ,0x0d}, - {R367_OFDM_SYMBOFFSM ,0xf0}, - {R367_OFDM_SYMBOFFSL ,0x2d}, - //{R367_OFDM_DEBUG_LT4 ,0x00}, - //{R367_OFDM_DEBUG_LT5 ,0x00}, - //{R367_OFDM_DEBUG_LT6 ,0x00}, - //{R367_OFDM_DEBUG_LT7 ,0x00}, - //{R367_OFDM_DEBUG_LT8 ,0x00}, - //{R367_OFDM_DEBUG_LT9 ,0x00}, - { 0x0000, 0x00 } // EOT -}; - -static inline u32 MulDiv32(u32 a, u32 b, u32 c) -{ - u64 tmp64; - - tmp64 = (u64)a * (u64)b; - do_div(tmp64, c); - - return (u32) tmp64; -} - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = - {.addr = adr, .flags = 0, .buf = data, .len = len}; - - if (i2c_transfer(adap, &msg, 1) != 1) { - printk("stv0367: i2c_write error\n"); - return -1; - } - return 0; -} - -#if 0 -static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) -{ - struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, - .buf = msg, .len = len}, - { .addr = adr, .flags = I2C_M_RD, - .buf = answ, .len = alen } }; - if (i2c_transfer(adap, msgs, 2) != 2) { - printk("stv0367: i2c_read error\n"); - return -1; - } - return 0; -} -#endif - -static int writereg(struct stv_state *state, u16 reg, u8 dat) -{ - u8 mm[3] = { (reg >> 8), reg & 0xff, dat }; - - return i2c_write(state->i2c, state->adr, mm, 3); -} - -static int readreg(struct stv_state *state, u16 reg, u8 *val) -{ - u8 msg[2] = {reg >> 8, reg & 0xff}; - struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, - .buf = msg, .len = 2}, - {.addr = state->adr, .flags = I2C_M_RD, - .buf = val, .len = 1}}; - return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -} - -static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) -{ - u8 msg[2] = {reg >> 8, reg & 0xff}; - struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, - .buf = msg, .len = 2}, - {.addr = state->adr, .flags = I2C_M_RD, - .buf = val, .len = count}}; - return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -} - -static int write_init_table(struct stv_state *state, struct init_table *tab) -{ - while (1) { - if (!tab->adr) - break; - if (writereg(state, tab->adr, tab->data) < 0) - return -1; - tab++; - } - return 0; -} - -static int qam_set_modulation(struct stv_state *state) -{ - int stat = 0; - - switch(state->modulation) { - case QAM_16: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0x90); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); - writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); - break; - case QAM_32: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0xb0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); - writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); - break; - case QAM_64: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ - if(state->symbol_rate>4500000) - { - writereg(state, R367_QAM_FSM_STATE,0xb0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); - } - else if(state->symbol_rate>2500000) // 25000000 - { - writereg(state, R367_QAM_FSM_STATE,0xa0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); - } - else - { - writereg(state, R367_QAM_FSM_STATE,0xa0); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - } - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); - writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); - break; - case QAM_128: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0x90); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); - if(state->symbol_rate>4500000) // 45000000 - { - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - } - else if(state->symbol_rate>2500000) // 25000000 - { - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); - } - else - { - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); - } - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); - writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); - break; - case QAM_256: - writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); - writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ - writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ - writereg(state, R367_QAM_FSM_STATE,0xa0); - if(state->symbol_rate>4500000) // 45000000 - { - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - } - else if(state->symbol_rate>2500000) // 25000000 - { - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); - } - else - { - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); - } - writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); - writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); - writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); - writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); - break; - default: - stat = -EINVAL; - break; - } - return stat; -} - - -static int QAM_SetSymbolRate(struct stv_state *state) -{ - int status = 0; - u32 sr = state->symbol_rate; - u32 Corr = 0; - u32 Temp, Temp1, AdpClk; - - switch(state->modulation) { - default: - case QAM_16: Corr = 1032; break; - case QAM_32: Corr = 954; break; - case QAM_64: Corr = 983; break; - case QAM_128: Corr = 957; break; - case QAM_256: Corr = 948; break; - } - - // Transfer ration - Temp = (256*sr) / state->adc_clock; - writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); - - /* Symbol rate and SRC gain calculation */ - AdpClk = (state->master_clock) / 2000; /* TRL works at half the system clock */ - - Temp = state->symbol_rate; - Temp1 = sr; - - if(sr < 2097152) /* 2097152 = 2^21 */ - { - Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; - Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; - } - else if(sr < 4194304) /* 4194304 = 2**22 */ - { - Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; - Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; - } - else if(sr < 8388608) /* 8388608 = 2**23 */ - { - Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; - Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; - } - else - { - Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; - Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; - } - - ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ - //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! - //{ - // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); - //} - ///* AllPass filter is never used on this IC */ - //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! - - writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); - writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); - writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); - writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); - - writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); - writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); - return status; -} - - -static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) -{ - int status = 0; - u32 Sampled_IF; - - do { - //if (DerotFrequency < 1000000) - // DerotFrequency = state->adc_clock/4; /* ZIF operation */ - if (DerotFrequency > state->adc_clock) - DerotFrequency = DerotFrequency - state->adc_clock; // User Alias - - Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; - if(Sampled_IF > 8388607) - Sampled_IF = 8388607; - - writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); - writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); - writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); - } while(0); - - return status; -} - - - -static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -{ - int status = 0; - u32 AGCTimeOut = 25; - u32 TRLTimeOut = 100000000 / state->symbol_rate; - u32 CRLSymbols = 0; - u32 EQLTimeOut = 100; - u32 SearchRange = state->symbol_rate / 25; - u32 CRLTimeOut; - u8 Temp; - - if( state->demod_state != QAMSet ) { - writereg(state, R367_DEBUG_LT4,0x00); - writereg(state, R367_DEBUG_LT5,0x01); - writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 - writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 - writereg(state, R367_DEBUG_LT8,0x00); - writereg(state, R367_DEBUG_LT9,0x00); - - // Tuner Setup - writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ - writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ - - // Clock setup - writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ - writereg(state, R367_TOPCTRL,0x10); // Set QAM - - writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV,232); - writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ - - msleep(50); - writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ - - state->master_clock = 58000000; - state->adc_clock = 58000000; - - state->demod_state = QAMSet; - } - - state->m_bFirstTimeLock = true; - state->m_DemodLockTime = -1; - - qam_set_modulation(state); - QAM_SetSymbolRate(state); - - // Will make problems on low symbol rates ( < 2500000 ) - - switch(state->modulation) { - default: - case QAM_16: CRLSymbols = 150000; break; - case QAM_32: CRLSymbols = 250000; break; - case QAM_64: CRLSymbols = 200000; break; - case QAM_128: CRLSymbols = 250000; break; - case QAM_256: CRLSymbols = 250000; break; - } - - CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); - CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; - if( CRLTimeOut < 50 ) CRLTimeOut = 50; - - state->m_FECTimeOut = 20; - state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; - state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; - - // QAM_AGC_ACCUMRSTSEL = 0; - readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); - writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); - - // QAM_MODULUSMAP_EN = 0 - readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); - writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); - - // QAM_SWEEP_EN = 0 - readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); - writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); - - QAM_SetDerotFrequency(state, IntermediateFrequency); - - // Release TRL - writereg(state, R367_QAM_CTRL_1,0x00); - - state->IF = IntermediateFrequency; - state->demod_state = QAMStarted; - - return status; -} - -static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -{ - int status = 0; - u8 GAIN_SRC1; - u32 Derot; - u8 SYR_CTL; - u8 tmp1; - u8 tmp2; - - if ( state->demod_state != OFDMSet ) { - // QAM Disable - writereg(state, R367_DEBUG_LT4, 0x00); - writereg(state, R367_DEBUG_LT5, 0x00); - writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 - writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 - writereg(state, R367_DEBUG_LT8, 0x00); - writereg(state, R367_DEBUG_LT9, 0x00); - - // Tuner Setup - writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ - writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ - - // Clock setup - writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ - writereg(state, R367_TOPCTRL, 0x00); // Set OFDM - - writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV, 8); - writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ - - msleep(50); - writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ - - state->master_clock = 54000000; - state->adc_clock = 54000000; - - state->demod_state = OFDMSet; - } - - state->m_bFirstTimeLock = true; - state->m_DemodLockTime = -1; - - // Set inversion in GAIN_SRC1 (fixed from init) - // is in GAIN_SRC1, see below - - GAIN_SRC1 = 0xA0; - // Bandwidth - - // Fixed values for 54 MHz - switch(state->bandwidth) { - case 0: - case 8000000: - // Normrate = 44384; - writereg(state, R367_OFDM_TRL_CTL,0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); - writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); - // Gain SRC = 2774 - writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); - writereg(state, R367_OFDM_GAIN_SRC2,0xD6); - break; - case 7000000: - // Normrate = 38836; - writereg(state, R367_OFDM_TRL_CTL,0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); - writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); - // Gain SRC = 2427 - writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); - writereg(state, R367_OFDM_GAIN_SRC2,0x7B); - break; - case 6000000: - // Normrate = 33288; - writereg(state, R367_OFDM_TRL_CTL,0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); - writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); - // Gain SRC = 2080 - writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); - writereg(state, R367_OFDM_GAIN_SRC2,0x20); - break; - default: - return -EINVAL; - break; - } - - Derot = ((IntermediateFrequency / 1000) * 65536) / (state->master_clock / 1000); - - writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); - writereg(state, R367_OFDM_INC_DEROT2,(Derot)); - - readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); - SYR_CTL &= ~0x78; - writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 - - - writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 - SYR_CTL &= 0x01; - writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 - - msleep(5); - - writereg(state, R367_OFDM_COR_CTL,0x20); // Start core - - // -- Begin M.V. - // Reset FEC and Read Solomon - readreg(state, R367_OFDM_SFDLYSETH,&tmp1); - readreg(state, R367_TSGENERAL,&tmp2); - writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); - writereg(state, R367_TSGENERAL,tmp2 | 0x01); - // -- End M.V. - - state->m_SignalTimeOut = 200; - state->IF = IntermediateFrequency; - state->demod_state = OFDMStarted; - state->m_DemodTimeOut = 0; - state->m_FECTimeOut = 0; - state->m_TSTimeOut = 0; - - return status; -} - -#if 0 -static int Stop(struct stv_state *state) -{ - int status = 0; - - switch(state->demod_state) - { - case QAMStarted: - status = writereg(state, R367_QAM_CTRL_1,0x06); - state->demod_state = QAMSet; - break; - case OFDMStarted: - status = writereg(state, R367_OFDM_COR_CTL,0x00); - state->demod_state = OFDMSet; - break; - default: - break; - } - return status; -} -#endif - -static s32 Log10x100(u32 x) -{ - static u32 LookupTable[100] = { - 101157945, 103514217, 105925373, 108392691, 110917482, - 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 - 127350308, 130316678, 133352143, 136458314, 139636836, - 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 - 160324539, 164058977, 167880402, 171790839, 175792361, - 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 - 201836636, 206538016, 211348904, 216271852, 221309471, - 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 - 254097271, 260015956, 266072506, 272270131, 278612117, - 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 - 319889511, 327340695, 334965439, 342767787, 350751874, - 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 - 402717034, 412097519, 421696503, 431519077, 441570447, - 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 - 506990708, 518800039, 530884444, 543250331, 555904257, - 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 - 638263486, 653130553, 668343918, 683911647, 699841996, - 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 - 803526122, 822242650, 841395142, 860993752, 881048873, - 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 - }; - s32 y; - int i; - - if (x == 0) - return 0; - y = 800; - if (x >= 1000000000) { - x /= 10; - y += 100; - } - - while (x < 100000000) { - x *= 10; - y -= 100; - } - i = 0; - while (i < 100 && x > LookupTable[i]) - i += 1; - y += i; - return y; -} - -static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -{ - u32 RegValAvg = 0; - u8 RegVal[2]; - int status = 0, i; - - *pSignalToNoise = 0; - for (i = 0; i < 10; i += 1 ) { - readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); - RegValAvg += RegVal[0] + 256 * RegVal[1]; - } - if (RegValAvg != 0) { - s32 Power = 1; - switch(state->modulation) { - case QAM_16: - Power = 20480; - break; - case QAM_32: - Power = 23040; - break; - case QAM_64: - Power = 21504; - break; - case QAM_128: - Power = 23616; - break; - case QAM_256: - Power = 21760; - break; - default: - break; - } - *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); - } else { - *pSignalToNoise = 380; - } - return status; -} - -static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -{ - u8 CHC_SNR = 0; - - int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); - if (status >= 0) { - // Note: very unclear documentation on this. - // Datasheet states snr = CHC_SNR/4 dB -> way to high values! - // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values - // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 - // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best - *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; - } - //printk("SNR %d\n", *pSignalToNoise); - return status; -} - -#if 0 -static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -{ - *pQuality = 100; - return 0; -}; - -static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -{ - static s32 QE_SN[] = { - 51, // QPSK 1/2 - 69, // QPSK 2/3 - 79, // QPSK 3/4 - 89, // QPSK 5/6 - 97, // QPSK 7/8 - 108, // 16-QAM 1/2 - 131, // 16-QAM 2/3 - 146, // 16-QAM 3/4 - 156, // 16-QAM 5/6 - 160, // 16-QAM 7/8 - 165, // 64-QAM 1/2 - 187, // 64-QAM 2/3 - 202, // 64-QAM 3/4 - 216, // 64-QAM 5/6 - 225, // 64-QAM 7/8 - }; - u8 TPS_Received[2]; - int Constellation; - int CodeRate; - s32 SignalToNoiseRel, BERQuality; - - *pQuality = 0; - readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); - Constellation = TPS_Received[0] & 0x03; - CodeRate = TPS_Received[1] & 0x07; - - if( Constellation > 2 || CodeRate > 5 ) - return -1; - SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; - BERQuality = 100; - - if( SignalToNoiseRel < -70 ) - *pQuality = 0; - else if( SignalToNoiseRel < 30 ) { - *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; - } else - *pQuality = BERQuality; - return 0; -}; - -static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) -{ - s32 SignalToNoiseRel = 0; - s32 Quality = 0; - s32 BERQuality = 100; - - switch(state->modulation) { - case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; - case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig - case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; - case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; - case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; - } - - if( SignalToNoiseRel < -70 ) Quality = 0; - else if( SignalToNoiseRel < 30 ) - { - Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; - } - else - Quality = BERQuality; - - return Quality; -} - -static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -{ - *pQuality = 0; - switch(state->demod_state) - { - case QAMStarted: - *pQuality = DVBCQuality(state, SignalToNoise); - break; - case OFDMStarted: - return DVBT_GetQuality(state, SignalToNoise, pQuality); - } - return 0; -}; -#endif - -static int attach_init(struct stv_state *state) -{ - int stat = 0; - - stat = readreg(state, R367_ID, &state->ID); - if ( stat < 0 || state->ID != 0x60 ) - return -ENODEV; - printk("stv0367 found\n"); - - writereg(state, R367_TOPCTRL, 0x10); - write_init_table(state, base_init); - write_init_table(state, qam_init); - - writereg(state, R367_TOPCTRL, 0x00); - write_init_table(state, ofdm_init); - - writereg(state, R367_OFDM_GAIN_SRC1, 0x2A); - writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); - writereg(state, R367_OFDM_INC_DEROT1, 0x55); - writereg(state, R367_OFDM_INC_DEROT2, 0x55); - writereg(state, R367_OFDM_TRL_CTL, 0x14); - writereg(state, R367_OFDM_TRL_NOMRATE1, 0xAE); - writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); - writereg(state, R367_OFDM_FEPATH_CFG, 0x0); - - // OFDM TS Setup - - writereg(state, R367_OFDM_TSCFGH, 0x70); - writereg(state, R367_OFDM_TSCFGM, 0xC0); - writereg(state, R367_OFDM_TSCFGL, 0x20); - writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz - //writereg(state, R367_TSTBUS, 0x80); // Invert CLK - - writereg(state, R367_OFDM_TSCFGH, 0x71); - writereg(state, R367_OFDM_TSCFGH, 0x70); - - writereg(state, R367_TOPCTRL, 0x10); - - // Also needed for QAM - writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup - - writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // - - // QAM TS setup, note exact format also depends on descrambler settings - writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial - // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // - - // Clock setup - writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ - - if( state->master_clock == 58000000 ) { - writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV,232); - } else { - writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ - writereg(state, R367_PLLNDIV,8); - } - writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ - - // Tuner setup - writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ - writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ - - writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ - writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ - writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ - writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ - - writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ - - writereg(state, R367_I2CRPT, state->I2CRPT); - state->demod_state = QAMSet; - return stat; -} - -#ifdef USE_API3 -static void c_release(struct dvb_frontend* fe) -#else -static void release(struct dvb_frontend* fe) -#endif -{ - struct stv_state *state=fe->demodulator_priv; - printk("%s\n", __FUNCTION__); - kfree(state); -} - -#ifdef USE_API3 -static int c_init (struct dvb_frontend *fe) -{ - struct stv_state *state=fe->demodulator_priv; - - if (mutex_trylock(&state->ctlock)==0) - return -EBUSY; - state->omode = OM_DVBC; - return 0; -} - -static int c_sleep(struct dvb_frontend* fe) -{ - struct stv_state *state=fe->demodulator_priv; - - mutex_unlock(&state->ctlock); - return 0; -} -#endif - -static int gate_ctrl(struct dvb_frontend *fe, int enable) -{ - struct stv_state *state = fe->demodulator_priv; - u8 i2crpt = state->I2CRPT & ~0x80; - - if (enable) - i2crpt |= 0x80; - if (writereg(state, R367_I2CRPT, i2crpt) < 0) - return -1; - state->I2CRPT = i2crpt; - return 0; -} - -#if 0 -static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - return DVBFE_ALGO_SEARCH_AGAIN; -} -#endif - -#if 0 -int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -#endif - -static int ofdm_lock(struct stv_state *state) -{ - int status = 0; - u8 OFDM_Status; - s32 DemodTimeOut = 10; - s32 FECTimeOut = 0; - s32 TSTimeOut = 0; - u8 CPAMPMin = 255; - u8 CPAMPValue; - u8 SYR_STAT; - u8 FFTMode; - u8 TSStatus; - - msleep(state->m_SignalTimeOut); - readreg(state, R367_OFDM_STATUS,&OFDM_Status); - - if (!(OFDM_Status & 0x40)) - return -1; - //printk("lock 1\n"); - - readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); - FFTMode = (SYR_STAT & 0x0C) >> 2; - - switch(FFTMode) - { - case 0: // 2K - DemodTimeOut = 10; - FECTimeOut = 150; - TSTimeOut = 125; - CPAMPMin = 20; - break; - case 1: // 8K - DemodTimeOut = 55; - FECTimeOut = 600; - TSTimeOut = 500; - CPAMPMin = 80; - break; - case 2: // 4K - DemodTimeOut = 40; - FECTimeOut = 300; - TSTimeOut = 250; - CPAMPMin = 30; - break; - } - state->m_OFDM_FFTMode = FFTMode; - readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); - msleep(DemodTimeOut); - { - // Release FEC and Read Solomon Reset - u8 tmp1; - u8 tmp2; - readreg(state, R367_OFDM_SFDLYSETH,&tmp1); - readreg(state, R367_TSGENERAL,&tmp2); - writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); - writereg(state, R367_TSGENERAL,tmp2 & ~0x01); - } - msleep(FECTimeOut); - if( (OFDM_Status & 0x98) != 0x98 ) - ;//return -1; - //printk("lock 2\n"); - - { - u8 Guard = (SYR_STAT & 0x03); - if(Guard < 2) - { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER - } else { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER - } - - // apply Sfec workaround if 8K 64QAM CR!=1/2 - if( FFTMode == 1) - { - u8 tmp[2]; - readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); - if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) - { - writereg(state, R367_OFDM_SFDLYSETH,0xc0); - writereg(state, R367_OFDM_SFDLYSETM,0x60); - writereg(state, R367_OFDM_SFDLYSETL,0x00); - } - else - { - writereg(state, R367_OFDM_SFDLYSETH,0x00); - } - } - } - msleep(TSTimeOut); - readreg(state, R367_OFDM_TSSTATUS,&TSStatus); - if( (TSStatus & 0x80) != 0x80 ) - return -1; - //printk("lock 3\n"); - return status; -} - - -#ifdef USE_API3 -static int set_parameters(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) -{ - int stat; - struct stv_state *state = fe->demodulator_priv; - u32 OF = 0; - u32 IF; - - if (fe->ops.tuner_ops.set_params) - fe->ops.tuner_ops.set_params(fe, p); - - switch (state->omode) { - case OM_DVBC: - case OM_QAM_ITU_C: - state->modulation = p->u.qam.modulation; - state->symbol_rate = p->u.qam.symbol_rate; - break; - case OM_DVBT: - switch (p->u.ofdm.bandwidth) { - case BANDWIDTH_AUTO: - case BANDWIDTH_8_MHZ: - state->bandwidth = 8000000; - break; - case BANDWIDTH_7_MHZ: - state->bandwidth = 7000000; - break; - case BANDWIDTH_6_MHZ: - state->bandwidth = 6000000; - break; - default: - return -EINVAL; - } - break; - default: - return -EINVAL; - } -#else -static int set_parameters(struct dvb_frontend *fe) -{ - int stat; - struct stv_state *state = fe->demodulator_priv; - u32 OF = 0; - u32 IF; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBC_ANNEX_A: - state->omode = OM_DVBC; - /* symbol rate 0 might cause an oops */ - if (fe->dtv_property_cache.symbol_rate == 0) { - printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); - return -EINVAL; - } - break; - case SYS_DVBT: - state->omode = OM_DVBT; - break; - default: - return -EINVAL; - } - if (fe->ops.tuner_ops.set_params) - fe->ops.tuner_ops.set_params(fe); - state->modulation = fe->dtv_property_cache.modulation; - state->symbol_rate = fe->dtv_property_cache.symbol_rate; - state->bandwidth = fe->dtv_property_cache.bandwidth_hz; -#endif - fe->ops.tuner_ops.get_if_frequency(fe, &IF); - //fe->ops.tuner_ops.get_frequency(fe, &IF); - - switch(state->omode) { - case OM_DVBT: - stat = OFDM_Start(state, OF, IF); - ofdm_lock(state); - break; - case OM_DVBC: - case OM_QAM_ITU_C: - stat = QAM_Start(state, OF, IF); - break; - default: - stat = -EINVAL; - } - //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); - return stat; -} - -#if 0 -static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct stv_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) -{ - int status = STATUS_SUCCESS; - u8 OFDM_Status; - s32 DemodTimeOut = 0; - s32 FECTimeOut = 0; - s32 TSTimeOut = 0; - u8 CPAMPMin = 255; - u8 CPAMPValue; - bool SYRLock; - u8 SYR_STAT; - u8 FFTMode; - u8 TSStatus; - - readreg(state, R367_OFDM_STATUS,&OFDM_Status); - - SYRLock = (OFDM_Status & 0x40) != 0; - - if( Time > m_SignalTimeOut && !SYRLock ) - { - *pLockStatus = NEVER_LOCK; - break; - } - - if( !SYRLock ) break; - - *pLockStatus = SIGNAL_PRESENT; - - // Check Mode - - readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); - FFTMode = (SYR_STAT & 0x0C) >> 2; - - switch(FFTMode) - { - case 0: // 2K - DemodTimeOut = 10; - FECTimeOut = 150; - TSTimeOut = 125; - CPAMPMin = 20; - break; - case 1: // 8K - DemodTimeOut = 55; - FECTimeOut = 600; - TSTimeOut = 500; - CPAMPMin = 80; - break; - case 2: // 4K - DemodTimeOut = 40; - FECTimeOut = 300; - TSTimeOut = 250; - CPAMPMin = 30; - break; - } - - m_OFDM_FFTMode = FFTMode; - - if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) - { - m_DemodTimeOut = Time + DemodTimeOut; - //break; - } - - readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); - - if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) - { - break; - } - - if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) - { - // initiate retry - *pLockStatus = NEVER_LOCK; - break; - } - - if( CPAMPValue < CPAMPMin ) break; - - *pLockStatus = DEMOD_LOCK; - - if( m_FECTimeOut == 0 && m_bFirstTimeLock ) - { - // Release FEC and Read Solomon Reset - u8 tmp1; - u8 tmp2; - readreg(state, R367_OFDM_SFDLYSETH,&tmp1); - readreg(state, R367_TSGENERAL,&tmp2); - writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); - writereg(state, R367_TSGENERAL,tmp2 & ~0x01); - - m_FECTimeOut = Time + FECTimeOut; - } - - // Wait for TSP_LOCK, LK, PRF - if( (OFDM_Status & 0x98) != 0x98 ) - { - if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; - break; - } - - if( m_bFirstTimeLock && m_TSTimeOut == 0) - { - u8 Guard = (SYR_STAT & 0x03); - if(Guard < 2) - { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER - } else { - u8 tmp; - readreg(state, R367_OFDM_SYR_CTL,&tmp); - writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN - readreg(state, R367_OFDM_SYR_UPDATE,&tmp); - writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER - } - - // apply Sfec workaround if 8K 64QAM CR!=1/2 - if( FFTMode == 1) - { - u8 tmp[2]; - readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); - if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) - { - writereg(state, R367_OFDM_SFDLYSETH,0xc0); - writereg(state, R367_OFDM_SFDLYSETM,0x60); - writereg(state, R367_OFDM_SFDLYSETL,0x00); - } - else - { - writereg(state, R367_OFDM_SFDLYSETH,0x00); - } - } - - m_TSTimeOut = Time + TSTimeOut; - } - readreg(state, R367_OFDM_TSSTATUS,&TSStatus); - if( (TSStatus & 0x80) != 0x80 ) - { - if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; - break; - } - *pLockStatus = MPEG_LOCK; - m_bFirstTimeLock = false; - return status; -} - -#endif - -static int read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct stv_state *state = fe->demodulator_priv; - *status=0; - - switch(state->demod_state) { - case QAMStarted: - { - u8 FEC_Lock; - u8 QAM_Lock; - - readreg(state, R367_QAM_FSM_STS, &QAM_Lock); - QAM_Lock &= 0x0F; - if (QAM_Lock >10) - *status|=0x07; - readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); - if (FEC_Lock&2) - *status|=0x1f; - if (state->m_bFirstTimeLock) { - state->m_bFirstTimeLock = false; - // QAM_AGC_ACCUMRSTSEL to Tracking; - writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); - } - break; - } - case OFDMStarted: - { - u8 OFDM_Status; - u8 TSStatus; - - readreg(state, R367_OFDM_TSSTATUS, &TSStatus); - - readreg(state, R367_OFDM_STATUS, &OFDM_Status); - if (OFDM_Status & 0x40) - *status |= FE_HAS_SIGNAL; - - if ((OFDM_Status & 0x98) == 0x98) - *status|=0x0f; - - if (TSStatus & 0x80) - *status |= 0x1f; - break; - } - default: - break; - } - return 0; -} - -static int read_ber_ter(struct dvb_frontend *fe, u32 *ber) -{ - struct stv_state *state = fe->demodulator_priv; - u32 err; - u8 cnth, cntm, cntl; - -#if 1 - readreg(state, R367_OFDM_SFERRCNTH, &cnth); - - if (cnth & 0x80) { - *ber = state->ber; - return 0; - } - - readreg(state, R367_OFDM_SFERRCNTM, &cntm); - readreg(state, R367_OFDM_SFERRCNTL, &cntl); - - err = ((cnth & 0x7f) << 16) | (cntm << 8) | cntl; - -#if 0 - { - u64 err64; - err64 = (u64) err; - err64 *= 1000000000ULL; - err64 >>= 21; - err = err64; - } -#endif -#else - readreg(state, R367_OFDM_ERRCNT1HM, &cnth); - -#endif - *ber = state->ber = err; - return 0; -} - -static int read_ber_cab(struct dvb_frontend *fe, u32 *ber) -{ - struct stv_state *state = fe->demodulator_priv; - u32 err; - u8 cntm, cntl, ctrl; - - readreg(state, R367_QAM_BERT_1, &ctrl); - if (!(ctrl & 0x20)) { - readreg(state, R367_QAM_BERT_2, &cntl); - readreg(state, R367_QAM_BERT_3, &cntm); - err = (cntm << 8) | cntl; - //printk("err %04x\n", err); - state->ber = err; - writereg(state, R367_QAM_BERT_1, 0x27); - } - *ber = (u32) state->ber; - return 0; -} - -static int read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct stv_state *state = fe->demodulator_priv; - - if (state->demod_state == QAMStarted) - return read_ber_cab(fe, ber); - if (state->demod_state == OFDMStarted) - return read_ber_ter(fe, ber); - *ber = 0; - return 0; -} - -static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - if (fe->ops.tuner_ops.get_rf_strength) - fe->ops.tuner_ops.get_rf_strength(fe, strength); - else - *strength = 0; - return 0; -} - -static int read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct stv_state *state = fe->demodulator_priv; - s32 snr2 = 0; - - switch(state->demod_state) { - case QAMStarted: - QAM_GetSignalToNoise(state, &snr2); - break; - case OFDMStarted: - OFDM_GetSignalToNoise(state, &snr2); - break; - default: - break; - } - *snr = snr2&0xffff; - return 0; -} - -static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct stv_state *state = fe->demodulator_priv; - u8 errl, errm, errh; - u8 val; - - switch(state->demod_state) { - case QAMStarted: - readreg(state, R367_QAM_RS_COUNTER_4, &errl); - readreg(state, R367_QAM_RS_COUNTER_5, &errm); - *ucblocks = (errm << 8) | errl; - break; - case OFDMStarted: - readreg(state, R367_OFDM_SFERRCNTH, &val); - if ((val & 0x80) == 0) { - readreg(state, R367_OFDM_ERRCNT1H, &errh); - readreg(state, R367_OFDM_ERRCNT1M, &errl); - readreg(state, R367_OFDM_ERRCNT1L, &errm); - state->ucblocks = (errh <<16) | (errm << 8) | errl; - } - *ucblocks = state->ucblocks; - break; - default: - *ucblocks = 0; - break; - } - return 0; -} - -static int c_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) -{ - sets->min_delay_ms=3000; - sets->max_drift=0; - sets->step_size=0; - return 0; -} - -#ifndef USE_API3 -static int get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) -{ - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: - return c_get_tune_settings(fe, sets); - default: - /* DVB-T: Use info.frequency_stepsize. */ - return -EINVAL; - } -} -#endif - -#ifdef USE_API3 -static void t_release(struct dvb_frontend* fe) -{ - //struct stv_state *state=fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - //kfree(state); -} - -static int t_init (struct dvb_frontend *fe) -{ - struct stv_state *state=fe->demodulator_priv; - if (mutex_trylock(&state->ctlock)==0) - return -EBUSY; - state->omode = OM_DVBT; - return 0; -} - -static int t_sleep(struct dvb_frontend* fe) -{ - struct stv_state *state=fe->demodulator_priv; - mutex_unlock(&state->ctlock); - return 0; -} -#endif - -#if 0 -static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -{ - //struct stv_state *state = fe->demodulator_priv; - //printk("%s\n", __FUNCTION__); - return 0; -} - -static enum dvbfe_algo algo(struct dvb_frontend *fe) -{ - return DVBFE_ALGO_CUSTOM; -} -#endif - -#ifdef USE_API3 -static struct dvb_frontend_ops c_ops = { - .info = { - .name = "STV0367 DVB-C", - .type = FE_QAM, - .frequency_stepsize = 62500, - .frequency_min = 47000000, - .frequency_max = 862000000, - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO - }, - .release = c_release, - .init = c_init, - .sleep = c_sleep, - .i2c_gate_ctrl = gate_ctrl, - - .get_tune_settings = c_get_tune_settings, - - .read_status = read_status, - .read_ber = read_ber, - .read_signal_strength = read_signal_strength, - .read_snr = read_snr, - .read_ucblocks = read_ucblocks, - -#if 1 - .set_frontend = set_parameters, -#else - .get_frontend_algo = algo, - .search = search, -#endif -}; - -static struct dvb_frontend_ops t_ops = { - .info = { - .name = "STV0367 DVB-T", - .type = FE_OFDM, - .frequency_min = 47125000, - .frequency_max = 865000000, - .frequency_stepsize = 166667, - .frequency_tolerance = 0, - .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | - FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | - FE_CAN_FEC_AUTO | - FE_CAN_QAM_16 | FE_CAN_QAM_64 | - FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | - FE_CAN_MUTE_TS - }, - .release = t_release, - .init = t_init, - .sleep = t_sleep, - .i2c_gate_ctrl = gate_ctrl, - - .set_frontend = set_parameters, - - .read_status = read_status, - .read_ber = read_ber, - .read_signal_strength = read_signal_strength, - .read_snr = read_snr, - .read_ucblocks = read_ucblocks, -}; - -#else - -static struct dvb_frontend_ops common_ops = { - .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, - .info = { - .name = "STV0367 DVB-C DVB-T", - .frequency_stepsize = 166667, /* DVB-T only */ - .frequency_min = 47000000, /* DVB-T: 47125000 */ - .frequency_max = 865000000, /* DVB-C: 862000000 */ - .symbol_rate_min = 870000, - .symbol_rate_max = 11700000, - .caps = /* DVB-C */ - FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | - FE_CAN_FEC_AUTO | - /* DVB-T */ - FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | - FE_CAN_RECOVER | FE_CAN_MUTE_TS - }, - .release = release, - .i2c_gate_ctrl = gate_ctrl, - - .get_tune_settings = get_tune_settings, - - .set_frontend = set_parameters, - - .read_status = read_status, - .read_ber = read_ber, - .read_signal_strength = read_signal_strength, - .read_snr = read_snr, - .read_ucblocks = read_ucblocks, -}; -#endif - - -static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) -{ - u32 ulENARPTLEVEL = 5; - u32 ulQAMInversion = 2; - state->omode = OM_NONE; - state->adr = cfg->adr; - - mutex_init(&state->mutex); - mutex_init(&state->ctlock); - -#ifdef USE_API3 - memcpy(&state->c_frontend.ops, &c_ops, sizeof(struct dvb_frontend_ops)); - memcpy(&state->t_frontend.ops, &t_ops, sizeof(struct dvb_frontend_ops)); - state->c_frontend.demodulator_priv = state; - state->t_frontend.demodulator_priv = state; -#else - memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); - state->frontend.demodulator_priv = state; -#endif - - state->master_clock = 58000000; - state->adc_clock = 58000000; - state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); - state->qam_inversion = ((ulQAMInversion & 3) << 6 ); - state->demod_state = Off; -} - - -struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, - struct dvb_frontend **fe_t) -{ - struct stv_state *state = NULL; - - state = kzalloc(sizeof(struct stv_state), GFP_KERNEL); - if (!state) - return NULL; - - state->i2c = i2c; - init_state(state, cfg); - - if (attach_init(state)<0) - goto error; -#ifdef USE_API3 - *fe_t = &state->t_frontend; - return &state->c_frontend; -#else - return &state->frontend; -#endif - -error: - printk("stv0367: not found\n"); - kfree(state); - return NULL; -} - - -MODULE_DESCRIPTION("STV0367DD driver"); -MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(stv0367_attach); - - - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,17 +0,0 @@ -#ifndef _STV0367DD_H_ -#define _STV0367DD_H_ - -#include -#include - -struct stv0367_cfg { - u8 adr; - u32 xtal; - u32 ts_mode; -}; - - -extern struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, - struct stv0367_cfg *cfg, - struct dvb_frontend **fe_t); -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd_regs.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd_regs.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd_regs.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv0367dd_regs.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,3431 +0,0 @@ -// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions -// Author Manfred Völkel, Februar 2011 -// (c) 2010 DigitalDevices GmbH Germany. All rights reserved - -// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ - -/* ======================================================================= - -- Registers Declaration - -- ------------------------- - -- Each register (R367_XXXXX) is defined by its address (2 bytes). - -- - -- Each field (F367_XXXXX)is defined as follow: - -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] - ======================================================================= */ - -/* ID */ -#define R367_ID 0xF000 -#define F367_IDENTIFICATIONREG 0xF00000FF - -/* I2CRPT */ -#define R367_I2CRPT 0xF001 -#define F367_I2CT_ON 0xF0010080 -#define F367_ENARPT_LEVEL 0xF0010070 -#define F367_SCLT_DELAY 0xF0010008 -#define F367_SCLT_NOD 0xF0010004 -#define F367_STOP_ENABLE 0xF0010002 -#define F367_SDAT_NOD 0xF0010001 - -/* TOPCTRL */ -#define R367_TOPCTRL 0xF002 -#define F367_STDBY 0xF0020080 -#define F367_STDBY_FEC 0xF0020040 -#define F367_STDBY_CORE 0xF0020020 -#define F367_QAM_COFDM 0xF0020010 -#define F367_TS_DIS 0xF0020008 -#define F367_DIR_CLK_216 0xF0020004 -#define F367_TUNER_BB 0xF0020002 -#define F367_DVBT_H 0xF0020001 - -/* IOCFG0 */ -#define R367_IOCFG0 0xF003 -#define F367_OP0_SD 0xF0030080 -#define F367_OP0_VAL 0xF0030040 -#define F367_OP0_OD 0xF0030020 -#define F367_OP0_INV 0xF0030010 -#define F367_OP0_DACVALUE_HI 0xF003000F - -/* DAC0R */ -#define R367_DAC0R 0xF004 -#define F367_OP0_DACVALUE_LO 0xF00400FF - -/* IOCFG1 */ -#define R367_IOCFG1 0xF005 -#define F367_IP0 0xF0050040 -#define F367_OP1_OD 0xF0050020 -#define F367_OP1_INV 0xF0050010 -#define F367_OP1_DACVALUE_HI 0xF005000F - -/* DAC1R */ -#define R367_DAC1R 0xF006 -#define F367_OP1_DACVALUE_LO 0xF00600FF - -/* IOCFG2 */ -#define R367_IOCFG2 0xF007 -#define F367_OP2_LOCK_CONF 0xF00700E0 -#define F367_OP2_OD 0xF0070010 -#define F367_OP2_VAL 0xF0070008 -#define F367_OP1_LOCK_CONF 0xF0070007 - -/* SDFR */ -#define R367_SDFR 0xF008 -#define F367_OP0_FREQ 0xF00800F0 -#define F367_OP1_FREQ 0xF008000F - -/* STATUS */ -#define R367_OFDM_STATUS 0xF009 -#define F367_TPS_LOCK 0xF0090080 -#define F367_SYR_LOCK 0xF0090040 -#define F367_AGC_LOCK 0xF0090020 -#define F367_PRF 0xF0090010 -#define F367_LK 0xF0090008 -#define F367_PR 0xF0090007 - -/* AUX_CLK */ -#define R367_AUX_CLK 0xF00A -#define F367_AUXFEC_CTL 0xF00A00C0 -#define F367_DIS_CKX4 0xF00A0020 -#define F367_CKSEL 0xF00A0018 -#define F367_CKDIV_PROG 0xF00A0006 -#define F367_AUXCLK_ENA 0xF00A0001 - -/* FREESYS1 */ -#define R367_FREESYS1 0xF00B -#define F367_FREE_SYS1 0xF00B00FF - -/* FREESYS2 */ -#define R367_FREESYS2 0xF00C -#define F367_FREE_SYS2 0xF00C00FF - -/* FREESYS3 */ -#define R367_FREESYS3 0xF00D -#define F367_FREE_SYS3 0xF00D00FF - -/* GPIO_CFG */ -#define R367_GPIO_CFG 0xF00E -#define F367_GPIO7_NOD 0xF00E0080 -#define F367_GPIO7_CFG 0xF00E0040 -#define F367_GPIO6_NOD 0xF00E0020 -#define F367_GPIO6_CFG 0xF00E0010 -#define F367_GPIO5_NOD 0xF00E0008 -#define F367_GPIO5_CFG 0xF00E0004 -#define F367_GPIO4_NOD 0xF00E0002 -#define F367_GPIO4_CFG 0xF00E0001 - -/* GPIO_CMD */ -#define R367_GPIO_CMD 0xF00F -#define F367_GPIO7_VAL 0xF00F0008 -#define F367_GPIO6_VAL 0xF00F0004 -#define F367_GPIO5_VAL 0xF00F0002 -#define F367_GPIO4_VAL 0xF00F0001 - -/* AGC2MAX */ -#define R367_OFDM_AGC2MAX 0xF010 -#define F367_OFDM_AGC2_MAX 0xF01000FF - -/* AGC2MIN */ -#define R367_OFDM_AGC2MIN 0xF011 -#define F367_OFDM_AGC2_MIN 0xF01100FF - -/* AGC1MAX */ -#define R367_OFDM_AGC1MAX 0xF012 -#define F367_OFDM_AGC1_MAX 0xF01200FF - -/* AGC1MIN */ -#define R367_OFDM_AGC1MIN 0xF013 -#define F367_OFDM_AGC1_MIN 0xF01300FF - -/* AGCR */ -#define R367_OFDM_AGCR 0xF014 -#define F367_OFDM_RATIO_A 0xF01400E0 -#define F367_OFDM_RATIO_B 0xF0140018 -#define F367_OFDM_RATIO_C 0xF0140007 - -/* AGC2TH */ -#define R367_OFDM_AGC2TH 0xF015 -#define F367_OFDM_AGC2_THRES 0xF01500FF - -/* AGC12C */ -#define R367_OFDM_AGC12C 0xF016 -#define F367_OFDM_AGC1_IV 0xF0160080 -#define F367_OFDM_AGC1_OD 0xF0160040 -#define F367_OFDM_AGC1_LOAD 0xF0160020 -#define F367_OFDM_AGC2_IV 0xF0160010 -#define F367_OFDM_AGC2_OD 0xF0160008 -#define F367_OFDM_AGC2_LOAD 0xF0160004 -#define F367_OFDM_AGC12_MODE 0xF0160003 - -/* AGCCTRL1 */ -#define R367_OFDM_AGCCTRL1 0xF017 -#define F367_OFDM_DAGC_ON 0xF0170080 -#define F367_OFDM_INVERT_AGC12 0xF0170040 -#define F367_OFDM_AGC1_MODE 0xF0170008 -#define F367_OFDM_AGC2_MODE 0xF0170007 - -/* AGCCTRL2 */ -#define R367_OFDM_AGCCTRL2 0xF018 -#define F367_OFDM_FRZ2_CTRL 0xF0180060 -#define F367_OFDM_FRZ1_CTRL 0xF0180018 -#define F367_OFDM_TIME_CST 0xF0180007 - -/* AGC1VAL1 */ -#define R367_OFDM_AGC1VAL1 0xF019 -#define F367_OFDM_AGC1_VAL_LO 0xF01900FF - -/* AGC1VAL2 */ -#define R367_OFDM_AGC1VAL2 0xF01A -#define F367_OFDM_AGC1_VAL_HI 0xF01A000F - -/* AGC2VAL1 */ -#define R367_OFDM_AGC2VAL1 0xF01B -#define F367_OFDM_AGC2_VAL_LO 0xF01B00FF - -/* AGC2VAL2 */ -#define R367_OFDM_AGC2VAL2 0xF01C -#define F367_OFDM_AGC2_VAL_HI 0xF01C000F - -/* AGC2PGA */ -#define R367_OFDM_AGC2PGA 0xF01D -#define F367_OFDM_AGC2_PGA 0xF01D00FF - -/* OVF_RATE1 */ -#define R367_OFDM_OVF_RATE1 0xF01E -#define F367_OFDM_OVF_RATE_HI 0xF01E000F - -/* OVF_RATE2 */ -#define R367_OFDM_OVF_RATE2 0xF01F -#define F367_OFDM_OVF_RATE_LO 0xF01F00FF - -/* GAIN_SRC1 */ -#define R367_OFDM_GAIN_SRC1 0xF020 -#define F367_OFDM_INV_SPECTR 0xF0200080 -#define F367_OFDM_IQ_INVERT 0xF0200040 -#define F367_OFDM_INR_BYPASS 0xF0200020 -#define F367_OFDM_STATUS_INV_SPECRUM 0xF0200010 -#define F367_OFDM_GAIN_SRC_HI 0xF020000F - -/* GAIN_SRC2 */ -#define R367_OFDM_GAIN_SRC2 0xF021 -#define F367_OFDM_GAIN_SRC_LO 0xF02100FF - -/* INC_DEROT1 */ -#define R367_OFDM_INC_DEROT1 0xF022 -#define F367_OFDM_INC_DEROT_HI 0xF02200FF - -/* INC_DEROT2 */ -#define R367_OFDM_INC_DEROT2 0xF023 -#define F367_OFDM_INC_DEROT_LO 0xF02300FF - -/* PPM_CPAMP_DIR */ -#define R367_OFDM_PPM_CPAMP_DIR 0xF024 -#define F367_OFDM_PPM_CPAMP_DIRECT 0xF02400FF - -/* PPM_CPAMP_INV */ -#define R367_OFDM_PPM_CPAMP_INV 0xF025 -#define F367_OFDM_PPM_CPAMP_INVER 0xF02500FF - -/* FREESTFE_1 */ -#define R367_OFDM_FREESTFE_1 0xF026 -#define F367_OFDM_SYMBOL_NUMBER_INC 0xF02600C0 -#define F367_OFDM_SEL_LSB 0xF0260004 -#define F367_OFDM_AVERAGE_ON 0xF0260002 -#define F367_OFDM_DC_ADJ 0xF0260001 - -/* FREESTFE_2 */ -#define R367_OFDM_FREESTFE_2 0xF027 -#define F367_OFDM_SEL_SRCOUT 0xF02700C0 -#define F367_OFDM_SEL_SYRTHR 0xF027001F - -/* DCOFFSET */ -#define R367_OFDM_DCOFFSET 0xF028 -#define F367_OFDM_SELECT_I_Q 0xF0280080 -#define F367_OFDM_DC_OFFSET 0xF028007F - -/* EN_PROCESS */ -#define R367_OFDM_EN_PROCESS 0xF029 -#define F367_OFDM_FREE 0xF02900F0 -#define F367_OFDM_ENAB_MANUAL 0xF0290001 - -/* SDI_SMOOTHER */ -#define R367_OFDM_SDI_SMOOTHER 0xF02A -#define F367_OFDM_DIS_SMOOTH 0xF02A0080 -#define F367_OFDM_SDI_INC_SMOOTHER 0xF02A007F - -/* FE_LOOP_OPEN */ -#define R367_OFDM_FE_LOOP_OPEN 0xF02B -#define F367_OFDM_TRL_LOOP_OP 0xF02B0002 -#define F367_OFDM_CRL_LOOP_OP 0xF02B0001 - -/* FREQOFF1 */ -#define R367_OFDM_FREQOFF1 0xF02C -#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_VHI 0xF02C00FF - -/* FREQOFF2 */ -#define R367_OFDM_FREQOFF2 0xF02D -#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_HI 0xF02D00FF - -/* FREQOFF3 */ -#define R367_OFDM_FREQOFF3 0xF02E -#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_LO 0xF02E00FF - -/* TIMOFF1 */ -#define R367_OFDM_TIMOFF1 0xF02F -#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_HI 0xF02F00FF - -/* TIMOFF2 */ -#define R367_OFDM_TIMOFF2 0xF030 -#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_LO 0xF03000FF - -/* EPQ */ -#define R367_OFDM_EPQ 0xF031 -#define F367_OFDM_EPQ1 0xF03100FF - -/* EPQAUTO */ -#define R367_OFDM_EPQAUTO 0xF032 -#define F367_OFDM_EPQ2 0xF03200FF - -/* SYR_UPDATE */ -#define R367_OFDM_SYR_UPDATE 0xF033 -#define F367_OFDM_SYR_PROTV 0xF0330080 -#define F367_OFDM_SYR_PROTV_GAIN 0xF0330060 -#define F367_OFDM_SYR_FILTER 0xF0330010 -#define F367_OFDM_SYR_TRACK_THRES 0xF033000C - -/* CHPFREE */ -#define R367_OFDM_CHPFREE 0xF034 -#define F367_OFDM_CHP_FREE 0xF03400FF - -/* PPM_STATE_MAC */ -#define R367_OFDM_PPM_STATE_MAC 0xF035 -#define F367_OFDM_PPM_STATE_MACHINE_DECODER 0xF035003F - -/* INR_THRESHOLD */ -#define R367_OFDM_INR_THRESHOLD 0xF036 -#define F367_OFDM_INR_THRESH 0xF03600FF - -/* EPQ_TPS_ID_CELL */ -#define R367_OFDM_EPQ_TPS_ID_CELL 0xF037 -#define F367_OFDM_ENABLE_LGTH_TO_CF 0xF0370080 -#define F367_OFDM_DIS_TPS_RSVD 0xF0370040 -#define F367_OFDM_DIS_BCH 0xF0370020 -#define F367_OFDM_DIS_ID_CEL 0xF0370010 -#define F367_OFDM_TPS_ADJUST_SYM 0xF037000F - -/* EPQ_CFG */ -#define R367_OFDM_EPQ_CFG 0xF038 -#define F367_OFDM_EPQ_RANGE 0xF0380002 -#define F367_OFDM_EPQ_SOFT 0xF0380001 - -/* EPQ_STATUS */ -#define R367_OFDM_EPQ_STATUS 0xF039 -#define F367_OFDM_SLOPE_INC 0xF03900FC -#define F367_OFDM_TPS_FIELD 0xF0390003 - -/* AUTORELOCK */ -#define R367_OFDM_AUTORELOCK 0xF03A -#define F367_OFDM_BYPASS_BER_TEMPO 0xF03A0080 -#define F367_OFDM_BER_TEMPO 0xF03A0070 -#define F367_OFDM_BYPASS_COFDM_TEMPO 0xF03A0008 -#define F367_OFDM_COFDM_TEMPO 0xF03A0007 - -/* BER_THR_VMSB */ -#define R367_OFDM_BER_THR_VMSB 0xF03B -#define F367_OFDM_BER_THRESHOLD_HI 0xF03B00FF - -/* BER_THR_MSB */ -#define R367_OFDM_BER_THR_MSB 0xF03C -#define F367_OFDM_BER_THRESHOLD_MID 0xF03C00FF - -/* BER_THR_LSB */ -#define R367_OFDM_BER_THR_LSB 0xF03D -#define F367_OFDM_BER_THRESHOLD_LO 0xF03D00FF - -/* CCD */ -#define R367_OFDM_CCD 0xF03E -#define F367_OFDM_CCD_DETECTED 0xF03E0080 -#define F367_OFDM_CCD_RESET 0xF03E0040 -#define F367_OFDM_CCD_THRESHOLD 0xF03E000F - -/* SPECTR_CFG */ -#define R367_OFDM_SPECTR_CFG 0xF03F -#define F367_OFDM_SPECT_CFG 0xF03F0003 - -/* CONSTMU_MSB */ -#define R367_OFDM_CONSTMU_MSB 0xF040 -#define F367_OFDM_CONSTMU_FREEZE 0xF0400080 -#define F367_OFDM_CONSTNU_FORCE_EN 0xF0400040 -#define F367_OFDM_CONST_MU_MSB 0xF040003F - -/* CONSTMU_LSB */ -#define R367_OFDM_CONSTMU_LSB 0xF041 -#define F367_OFDM_CONST_MU_LSB 0xF04100FF - -/* CONSTMU_MAX_MSB */ -#define R367_OFDM_CONSTMU_MAX_MSB 0xF042 -#define F367_OFDM_CONST_MU_MAX_MSB 0xF042003F - -/* CONSTMU_MAX_LSB */ -#define R367_OFDM_CONSTMU_MAX_LSB 0xF043 -#define F367_OFDM_CONST_MU_MAX_LSB 0xF04300FF - -/* ALPHANOISE */ -#define R367_OFDM_ALPHANOISE 0xF044 -#define F367_OFDM_USE_ALLFILTER 0xF0440080 -#define F367_OFDM_INTER_ON 0xF0440040 -#define F367_OFDM_ALPHA_NOISE 0xF044001F - -/* MAXGP_MSB */ -#define R367_OFDM_MAXGP_MSB 0xF045 -#define F367_OFDM_MUFILTER_LENGTH 0xF04500F0 -#define F367_OFDM_MAX_GP_MSB 0xF045000F - -/* MAXGP_LSB */ -#define R367_OFDM_MAXGP_LSB 0xF046 -#define F367_OFDM_MAX_GP_LSB 0xF04600FF - -/* ALPHAMSB */ -#define R367_OFDM_ALPHAMSB 0xF047 -#define F367_OFDM_CHC_DATARATE 0xF04700C0 -#define F367_OFDM_ALPHA_MSB 0xF047003F - -/* ALPHALSB */ -#define R367_OFDM_ALPHALSB 0xF048 -#define F367_OFDM_ALPHA_LSB 0xF04800FF - -/* PILOT_ACCU */ -#define R367_OFDM_PILOT_ACCU 0xF049 -#define F367_OFDM_USE_SCAT4ADDAPT 0xF0490080 -#define F367_OFDM_PILOT_ACC 0xF049001F - -/* PILOTMU_ACCU */ -#define R367_OFDM_PILOTMU_ACCU 0xF04A -#define F367_OFDM_DISCARD_BAD_SP 0xF04A0080 -#define F367_OFDM_DISCARD_BAD_CP 0xF04A0040 -#define F367_OFDM_PILOT_MU_ACCU 0xF04A001F - -/* FILT_CHANNEL_EST */ -#define R367_OFDM_FILT_CHANNEL_EST 0xF04B -#define F367_OFDM_USE_FILT_PILOT 0xF04B0080 -#define F367_OFDM_FILT_CHANNEL 0xF04B007F - -/* ALPHA_NOPISE_FREQ */ -#define R367_OFDM_ALPHA_NOPISE_FREQ 0xF04C -#define F367_OFDM_NOISE_FREQ_FILT 0xF04C0040 -#define F367_OFDM_ALPHA_NOISE_FREQ 0xF04C003F - -/* RATIO_PILOT */ -#define R367_OFDM_RATIO_PILOT 0xF04D -#define F367_OFDM_RATIO_MEAN_SP 0xF04D00F0 -#define F367_OFDM_RATIO_MEAN_CP 0xF04D000F - -/* CHC_CTL */ -#define R367_OFDM_CHC_CTL 0xF04E -#define F367_OFDM_TRACK_EN 0xF04E0080 -#define F367_OFDM_NOISE_NORM_EN 0xF04E0040 -#define F367_OFDM_FORCE_CHC_RESET 0xF04E0020 -#define F367_OFDM_SHORT_TIME 0xF04E0010 -#define F367_OFDM_FORCE_STATE_EN 0xF04E0008 -#define F367_OFDM_FORCE_STATE 0xF04E0007 - -/* EPQ_ADJUST */ -#define R367_OFDM_EPQ_ADJUST 0xF04F -#define F367_OFDM_ADJUST_SCAT_IND 0xF04F00C0 -#define F367_OFDM_ONE_SYMBOL 0xF04F0010 -#define F367_OFDM_EPQ_DECAY 0xF04F000E -#define F367_OFDM_HOLD_SLOPE 0xF04F0001 - -/* EPQ_THRES */ -#define R367_OFDM_EPQ_THRES 0xF050 -#define F367_OFDM_EPQ_THR 0xF05000FF - -/* OMEGA_CTL */ -#define R367_OFDM_OMEGA_CTL 0xF051 -#define F367_OFDM_OMEGA_RST 0xF0510080 -#define F367_OFDM_FREEZE_OMEGA 0xF0510040 -#define F367_OFDM_OMEGA_SEL 0xF051003F - -/* GP_CTL */ -#define R367_OFDM_GP_CTL 0xF052 -#define F367_OFDM_CHC_STATE 0xF05200E0 -#define F367_OFDM_FREEZE_GP 0xF0520010 -#define F367_OFDM_GP_SEL 0xF052000F - -/* MUMSB */ -#define R367_OFDM_MUMSB 0xF053 -#define F367_OFDM_MU_MSB 0xF053007F - -/* MULSB */ -#define R367_OFDM_MULSB 0xF054 -#define F367_OFDM_MU_LSB 0xF05400FF - -/* GPMSB */ -#define R367_OFDM_GPMSB 0xF055 -#define F367_OFDM_CSI_THRESHOLD 0xF05500E0 -#define F367_OFDM_GP_MSB 0xF055000F - -/* GPLSB */ -#define R367_OFDM_GPLSB 0xF056 -#define F367_OFDM_GP_LSB 0xF05600FF - -/* OMEGAMSB */ -#define R367_OFDM_OMEGAMSB 0xF057 -#define F367_OFDM_OMEGA_MSB 0xF057007F - -/* OMEGALSB */ -#define R367_OFDM_OMEGALSB 0xF058 -#define F367_OFDM_OMEGA_LSB 0xF05800FF - -/* SCAT_NB */ -#define R367_OFDM_SCAT_NB 0xF059 -#define F367_OFDM_CHC_TEST 0xF05900F8 -#define F367_OFDM_SCAT_NUMB 0xF0590003 - -/* CHC_DUMMY */ -#define R367_OFDM_CHC_DUMMY 0xF05A -#define F367_OFDM_CHC_DUM 0xF05A00FF - -/* INC_CTL */ -#define R367_OFDM_INC_CTL 0xF05B -#define F367_OFDM_INC_BYPASS 0xF05B0080 -#define F367_OFDM_INC_NDEPTH 0xF05B000C -#define F367_OFDM_INC_MADEPTH 0xF05B0003 - -/* INCTHRES_COR1 */ -#define R367_OFDM_INCTHRES_COR1 0xF05C -#define F367_OFDM_INC_THRES_COR1 0xF05C00FF - -/* INCTHRES_COR2 */ -#define R367_OFDM_INCTHRES_COR2 0xF05D -#define F367_OFDM_INC_THRES_COR2 0xF05D00FF - -/* INCTHRES_DET1 */ -#define R367_OFDM_INCTHRES_DET1 0xF05E -#define F367_OFDM_INC_THRES_DET1 0xF05E003F - -/* INCTHRES_DET2 */ -#define R367_OFDM_INCTHRES_DET2 0xF05F -#define F367_OFDM_INC_THRES_DET2 0xF05F003F - -/* IIR_CELLNB */ -#define R367_OFDM_IIR_CELLNB 0xF060 -#define F367_OFDM_NRST_IIR 0xF0600080 -#define F367_OFDM_IIR_CELL_NB 0xF0600007 - -/* IIRCX_COEFF1_MSB */ -#define R367_OFDM_IIRCX_COEFF1_MSB 0xF061 -#define F367_OFDM_IIR_CX_COEFF1_MSB 0xF06100FF - -/* IIRCX_COEFF1_LSB */ -#define R367_OFDM_IIRCX_COEFF1_LSB 0xF062 -#define F367_OFDM_IIR_CX_COEFF1_LSB 0xF06200FF - -/* IIRCX_COEFF2_MSB */ -#define R367_OFDM_IIRCX_COEFF2_MSB 0xF063 -#define F367_OFDM_IIR_CX_COEFF2_MSB 0xF06300FF - -/* IIRCX_COEFF2_LSB */ -#define R367_OFDM_IIRCX_COEFF2_LSB 0xF064 -#define F367_OFDM_IIR_CX_COEFF2_LSB 0xF06400FF - -/* IIRCX_COEFF3_MSB */ -#define R367_OFDM_IIRCX_COEFF3_MSB 0xF065 -#define F367_OFDM_IIR_CX_COEFF3_MSB 0xF06500FF - -/* IIRCX_COEFF3_LSB */ -#define R367_OFDM_IIRCX_COEFF3_LSB 0xF066 -#define F367_OFDM_IIR_CX_COEFF3_LSB 0xF06600FF - -/* IIRCX_COEFF4_MSB */ -#define R367_OFDM_IIRCX_COEFF4_MSB 0xF067 -#define F367_OFDM_IIR_CX_COEFF4_MSB 0xF06700FF - -/* IIRCX_COEFF4_LSB */ -#define R367_OFDM_IIRCX_COEFF4_LSB 0xF068 -#define F367_OFDM_IIR_CX_COEFF4_LSB 0xF06800FF - -/* IIRCX_COEFF5_MSB */ -#define R367_OFDM_IIRCX_COEFF5_MSB 0xF069 -#define F367_OFDM_IIR_CX_COEFF5_MSB 0xF06900FF - -/* IIRCX_COEFF5_LSB */ -#define R367_OFDM_IIRCX_COEFF5_LSB 0xF06A -#define F367_OFDM_IIR_CX_COEFF5_LSB 0xF06A00FF - -/* FEPATH_CFG */ -#define R367_OFDM_FEPATH_CFG 0xF06B -#define F367_OFDM_DEMUX_SWAP 0xF06B0004 -#define F367_OFDM_DIGAGC_SWAP 0xF06B0002 -#define F367_OFDM_LONGPATH_IF 0xF06B0001 - -/* PMC1_FUNC */ -#define R367_OFDM_PMC1_FUNC 0xF06C -#define F367_OFDM_SOFT_RSTN 0xF06C0080 -#define F367_OFDM_PMC1_AVERAGE_TIME 0xF06C0078 -#define F367_OFDM_PMC1_WAIT_TIME 0xF06C0006 -#define F367_OFDM_PMC1_2N_SEL 0xF06C0001 - -/* PMC1_FOR */ -#define R367_OFDM_PMC1_FOR 0xF06D -#define F367_OFDM_PMC1_FORCE 0xF06D0080 -#define F367_OFDM_PMC1_FORCE_VALUE 0xF06D007C - -/* PMC2_FUNC */ -#define R367_OFDM_PMC2_FUNC 0xF06E -#define F367_OFDM_PMC2_SOFT_STN 0xF06E0080 -#define F367_OFDM_PMC2_ACCU_TIME 0xF06E0070 -#define F367_OFDM_PMC2_CMDP_MN 0xF06E0008 -#define F367_OFDM_PMC2_SWAP 0xF06E0004 - -/* STATUS_ERR_DA */ -#define R367_OFDM_STATUS_ERR_DA 0xF06F -#define F367_OFDM_COM_USEGAINTRK 0xF06F0080 -#define F367_OFDM_COM_AGCLOCK 0xF06F0040 -#define F367_OFDM_AUT_AGCLOCK 0xF06F0020 -#define F367_OFDM_MIN_ERR_X_LSB 0xF06F000F - -/* DIG_AGC_R */ -#define R367_OFDM_DIG_AGC_R 0xF070 -#define F367_OFDM_COM_SOFT_RSTN 0xF0700080 -#define F367_OFDM_COM_AGC_ON 0xF0700040 -#define F367_OFDM_COM_EARLY 0xF0700020 -#define F367_OFDM_AUT_SOFT_RESETN 0xF0700010 -#define F367_OFDM_AUT_AGC_ON 0xF0700008 -#define F367_OFDM_AUT_EARLY 0xF0700004 -#define F367_OFDM_AUT_ROT_EN 0xF0700002 -#define F367_OFDM_LOCK_SOFT_RESETN 0xF0700001 - -/* COMAGC_TARMSB */ -#define R367_OFDM_COMAGC_TARMSB 0xF071 -#define F367_OFDM_COM_AGC_TARGET_MSB 0xF07100FF - -/* COM_AGC_TAR_ENMODE */ -#define R367_OFDM_COM_AGC_TAR_ENMODE 0xF072 -#define F367_OFDM_COM_AGC_TARGET_LSB 0xF07200F0 -#define F367_OFDM_COM_ENMODE 0xF072000F - -/* COM_AGC_CFG */ -#define R367_OFDM_COM_AGC_CFG 0xF073 -#define F367_OFDM_COM_N 0xF07300F8 -#define F367_OFDM_COM_STABMODE 0xF0730006 -#define F367_OFDM_ERR_SEL 0xF0730001 - -/* COM_AGC_GAIN1 */ -#define R367_OFDM_COM_AGC_GAIN1 0xF074 -#define F367_OFDM_COM_GAIN1ACK 0xF07400F0 -#define F367_OFDM_COM_GAIN1TRK 0xF074000F - -/* AUT_AGC_TARGETMSB */ -#define R367_OFDM_AUT_AGC_TARGETMSB 0xF075 -#define F367_OFDM_AUT_AGC_TARGET_MSB 0xF07500FF - -/* LOCK_DET_MSB */ -#define R367_OFDM_LOCK_DET_MSB 0xF076 -#define F367_OFDM_LOCK_DETECT_MSB 0xF07600FF - -/* AGCTAR_LOCK_LSBS */ -#define R367_OFDM_AGCTAR_LOCK_LSBS 0xF077 -#define F367_OFDM_AUT_AGC_TARGET_LSB 0xF07700F0 -#define F367_OFDM_LOCK_DETECT_LSB 0xF077000F - -/* AUT_GAIN_EN */ -#define R367_OFDM_AUT_GAIN_EN 0xF078 -#define F367_OFDM_AUT_ENMODE 0xF07800F0 -#define F367_OFDM_AUT_GAIN2 0xF078000F - -/* AUT_CFG */ -#define R367_OFDM_AUT_CFG 0xF079 -#define F367_OFDM_AUT_N 0xF07900F8 -#define F367_OFDM_INT_CHOICE 0xF0790006 -#define F367_OFDM_INT_LOAD 0xF0790001 - -/* LOCKN */ -#define R367_OFDM_LOCKN 0xF07A -#define F367_OFDM_LOCK_N 0xF07A00F8 -#define F367_OFDM_SEL_IQNTAR 0xF07A0004 -#define F367_OFDM_LOCK_DETECT_CHOICE 0xF07A0003 - -/* INT_X_3 */ -#define R367_OFDM_INT_X_3 0xF07B -#define F367_OFDM_INT_X3 0xF07B00FF - -/* INT_X_2 */ -#define R367_OFDM_INT_X_2 0xF07C -#define F367_OFDM_INT_X2 0xF07C00FF - -/* INT_X_1 */ -#define R367_OFDM_INT_X_1 0xF07D -#define F367_OFDM_INT_X1 0xF07D00FF - -/* INT_X_0 */ -#define R367_OFDM_INT_X_0 0xF07E -#define F367_OFDM_INT_X0 0xF07E00FF - -/* MIN_ERRX_MSB */ -#define R367_OFDM_MIN_ERRX_MSB 0xF07F -#define F367_OFDM_MIN_ERR_X_MSB 0xF07F00FF - -/* COR_CTL */ -#define R367_OFDM_COR_CTL 0xF080 -#define F367_OFDM_CORE_ACTIVE 0xF0800020 -#define F367_OFDM_HOLD 0xF0800010 -#define F367_OFDM_CORE_STATE_CTL 0xF080000F - -/* COR_STAT */ -#define R367_OFDM_COR_STAT 0xF081 -#define F367_OFDM_SCATT_LOCKED 0xF0810080 -#define F367_OFDM_TPS_LOCKED 0xF0810040 -#define F367_OFDM_SYR_LOCKED_COR 0xF0810020 -#define F367_OFDM_AGC_LOCKED_STAT 0xF0810010 -#define F367_OFDM_CORE_STATE_STAT 0xF081000F - -/* COR_INTEN */ -#define R367_OFDM_COR_INTEN 0xF082 -#define F367_OFDM_INTEN 0xF0820080 -#define F367_OFDM_INTEN_SYR 0xF0820020 -#define F367_OFDM_INTEN_FFT 0xF0820010 -#define F367_OFDM_INTEN_AGC 0xF0820008 -#define F367_OFDM_INTEN_TPS1 0xF0820004 -#define F367_OFDM_INTEN_TPS2 0xF0820002 -#define F367_OFDM_INTEN_TPS3 0xF0820001 - -/* COR_INTSTAT */ -#define R367_OFDM_COR_INTSTAT 0xF083 -#define F367_OFDM_INTSTAT_SYR 0xF0830020 -#define F367_OFDM_INTSTAT_FFT 0xF0830010 -#define F367_OFDM_INTSAT_AGC 0xF0830008 -#define F367_OFDM_INTSTAT_TPS1 0xF0830004 -#define F367_OFDM_INTSTAT_TPS2 0xF0830002 -#define F367_OFDM_INTSTAT_TPS3 0xF0830001 - -/* COR_MODEGUARD */ -#define R367_OFDM_COR_MODEGUARD 0xF084 -#define F367_OFDM_FORCE 0xF0840010 -#define F367_OFDM_MODE 0xF084000C -#define F367_OFDM_GUARD 0xF0840003 - -/* AGC_CTL */ -#define R367_OFDM_AGC_CTL 0xF085 -#define F367_OFDM_AGC_TIMING_FACTOR 0xF08500E0 -#define F367_OFDM_AGC_LAST 0xF0850010 -#define F367_OFDM_AGC_GAIN 0xF085000C -#define F367_OFDM_AGC_NEG 0xF0850002 -#define F367_OFDM_AGC_SET 0xF0850001 - -/* AGC_MANUAL1 */ -#define R367_OFDM_AGC_MANUAL1 0xF086 -#define F367_OFDM_AGC_VAL_LO 0xF08600FF - -/* AGC_MANUAL2 */ -#define R367_OFDM_AGC_MANUAL2 0xF087 -#define F367_OFDM_AGC_VAL_HI 0xF087000F - -/* AGC_TARG */ -#define R367_OFDM_AGC_TARG 0xF088 -#define F367_OFDM_AGC_TARGET 0xF08800FF - -/* AGC_GAIN1 */ -#define R367_OFDM_AGC_GAIN1 0xF089 -#define F367_OFDM_AGC_GAIN_LO 0xF08900FF - -/* AGC_GAIN2 */ -#define R367_OFDM_AGC_GAIN2 0xF08A -#define F367_OFDM_AGC_LOCKED_GAIN2 0xF08A0010 -#define F367_OFDM_AGC_GAIN_HI 0xF08A000F - -/* RESERVED_1 */ -#define R367_OFDM_RESERVED_1 0xF08B -#define F367_OFDM_RESERVED1 0xF08B00FF - -/* RESERVED_2 */ -#define R367_OFDM_RESERVED_2 0xF08C -#define F367_OFDM_RESERVED2 0xF08C00FF - -/* RESERVED_3 */ -#define R367_OFDM_RESERVED_3 0xF08D -#define F367_OFDM_RESERVED3 0xF08D00FF - -/* CAS_CTL */ -#define R367_OFDM_CAS_CTL 0xF08E -#define F367_OFDM_CCS_ENABLE 0xF08E0080 -#define F367_OFDM_ACS_DISABLE 0xF08E0040 -#define F367_OFDM_DAGC_DIS 0xF08E0020 -#define F367_OFDM_DAGC_GAIN 0xF08E0018 -#define F367_OFDM_CCSMU 0xF08E0007 - -/* CAS_FREQ */ -#define R367_OFDM_CAS_FREQ 0xF08F -#define F367_OFDM_CCS_FREQ 0xF08F00FF - -/* CAS_DAGCGAIN */ -#define R367_OFDM_CAS_DAGCGAIN 0xF090 -#define F367_OFDM_CAS_DAGC_GAIN 0xF09000FF - -/* SYR_CTL */ -#define R367_OFDM_SYR_CTL 0xF091 -#define F367_OFDM_SICTH_ENABLE 0xF0910080 -#define F367_OFDM_LONG_ECHO 0xF0910078 -#define F367_OFDM_AUTO_LE_EN 0xF0910004 -#define F367_OFDM_SYR_BYPASS 0xF0910002 -#define F367_OFDM_SYR_TR_DIS 0xF0910001 - -/* SYR_STAT */ -#define R367_OFDM_SYR_STAT 0xF092 -#define F367_OFDM_SYR_LOCKED_STAT 0xF0920010 -#define F367_OFDM_SYR_MODE 0xF092000C -#define F367_OFDM_SYR_GUARD 0xF0920003 - -/* SYR_NCO1 */ -#define R367_OFDM_SYR_NCO1 0xF093 -#define F367_OFDM_SYR_NCO_LO 0xF09300FF - -/* SYR_NCO2 */ -#define R367_OFDM_SYR_NCO2 0xF094 -#define F367_OFDM_SYR_NCO_HI 0xF094003F - -/* SYR_OFFSET1 */ -#define R367_OFDM_SYR_OFFSET1 0xF095 -#define F367_OFDM_SYR_OFFSET_LO 0xF09500FF - -/* SYR_OFFSET2 */ -#define R367_OFDM_SYR_OFFSET2 0xF096 -#define F367_OFDM_SYR_OFFSET_HI 0xF096003F - -/* FFT_CTL */ -#define R367_OFDM_FFT_CTL 0xF097 -#define F367_OFDM_SHIFT_FFT_TRIG 0xF0970018 -#define F367_OFDM_FFT_TRIGGER 0xF0970004 -#define F367_OFDM_FFT_MANUAL 0xF0970002 -#define F367_OFDM_IFFT_MODE 0xF0970001 - -/* SCR_CTL */ -#define R367_OFDM_SCR_CTL 0xF098 -#define F367_OFDM_SYRADJDECAY 0xF0980070 -#define F367_OFDM_SCR_CPEDIS 0xF0980002 -#define F367_OFDM_SCR_DIS 0xF0980001 - -/* PPM_CTL1 */ -#define R367_OFDM_PPM_CTL1 0xF099 -#define F367_OFDM_PPM_MAXFREQ 0xF0990030 -#define F367_OFDM_PPM_MAXTIM 0xF0990008 -#define F367_OFDM_PPM_INVSEL 0xF0990004 -#define F367_OFDM_PPM_SCATDIS 0xF0990002 -#define F367_OFDM_PPM_BYP 0xF0990001 - -/* TRL_CTL */ -#define R367_OFDM_TRL_CTL 0xF09A -#define F367_OFDM_TRL_NOMRATE_LSB 0xF09A0080 -#define F367_OFDM_TRL_GAIN_FACTOR 0xF09A0078 -#define F367_OFDM_TRL_LOOPGAIN 0xF09A0007 - -/* TRL_NOMRATE1 */ -#define R367_OFDM_TRL_NOMRATE1 0xF09B -#define F367_OFDM_TRL_NOMRATE_LO 0xF09B00FF - -/* TRL_NOMRATE2 */ -#define R367_OFDM_TRL_NOMRATE2 0xF09C -#define F367_OFDM_TRL_NOMRATE_HI 0xF09C00FF - -/* TRL_TIME1 */ -#define R367_OFDM_TRL_TIME1 0xF09D -#define F367_OFDM_TRL_TOFFSET_LO 0xF09D00FF - -/* TRL_TIME2 */ -#define R367_OFDM_TRL_TIME2 0xF09E -#define F367_OFDM_TRL_TOFFSET_HI 0xF09E00FF - -/* CRL_CTL */ -#define R367_OFDM_CRL_CTL 0xF09F -#define F367_OFDM_CRL_DIS 0xF09F0080 -#define F367_OFDM_CRL_GAIN_FACTOR 0xF09F0078 -#define F367_OFDM_CRL_LOOPGAIN 0xF09F0007 - -/* CRL_FREQ1 */ -#define R367_OFDM_CRL_FREQ1 0xF0A0 -#define F367_OFDM_CRL_FOFFSET_LO 0xF0A000FF - -/* CRL_FREQ2 */ -#define R367_OFDM_CRL_FREQ2 0xF0A1 -#define F367_OFDM_CRL_FOFFSET_HI 0xF0A100FF - -/* CRL_FREQ3 */ -#define R367_OFDM_CRL_FREQ3 0xF0A2 -#define F367_OFDM_CRL_FOFFSET_VHI 0xF0A200FF - -/* TPS_SFRAME_CTL */ -#define R367_OFDM_TPS_SFRAME_CTL 0xF0A3 -#define F367_OFDM_TPS_SFRAME_SYNC 0xF0A30001 - -/* CHC_SNR */ -#define R367_OFDM_CHC_SNR 0xF0A4 -#define F367_OFDM_CHCSNR 0xF0A400FF - -/* BDI_CTL */ -#define R367_OFDM_BDI_CTL 0xF0A5 -#define F367_OFDM_BDI_LPSEL 0xF0A50002 -#define F367_OFDM_BDI_SERIAL 0xF0A50001 - -/* DMP_CTL */ -#define R367_OFDM_DMP_CTL 0xF0A6 -#define F367_OFDM_DMP_SCALING_FACTOR 0xF0A6001E -#define F367_OFDM_DMP_SDDIS 0xF0A60001 - -/* TPS_RCVD1 */ -#define R367_OFDM_TPS_RCVD1 0xF0A7 -#define F367_OFDM_TPS_CHANGE 0xF0A70040 -#define F367_OFDM_BCH_OK 0xF0A70020 -#define F367_OFDM_TPS_SYNC 0xF0A70010 -#define F367_OFDM_TPS_FRAME 0xF0A70003 - -/* TPS_RCVD2 */ -#define R367_OFDM_TPS_RCVD2 0xF0A8 -#define F367_OFDM_TPS_HIERMODE 0xF0A80070 -#define F367_OFDM_TPS_CONST 0xF0A80003 - -/* TPS_RCVD3 */ -#define R367_OFDM_TPS_RCVD3 0xF0A9 -#define F367_OFDM_TPS_LPCODE 0xF0A90070 -#define F367_OFDM_TPS_HPCODE 0xF0A90007 - -/* TPS_RCVD4 */ -#define R367_OFDM_TPS_RCVD4 0xF0AA -#define F367_OFDM_TPS_GUARD 0xF0AA0030 -#define F367_OFDM_TPS_MODE 0xF0AA0003 - -/* TPS_ID_CELL1 */ -#define R367_OFDM_TPS_ID_CELL1 0xF0AB -#define F367_OFDM_TPS_ID_CELL_LO 0xF0AB00FF - -/* TPS_ID_CELL2 */ -#define R367_OFDM_TPS_ID_CELL2 0xF0AC -#define F367_OFDM_TPS_ID_CELL_HI 0xF0AC00FF - -/* TPS_RCVD5_SET1 */ -#define R367_OFDM_TPS_RCVD5_SET1 0xF0AD -#define F367_OFDM_TPS_NA 0xF0AD00FC -#define F367_OFDM_TPS_SETFRAME 0xF0AD0003 - -/* TPS_SET2 */ -#define R367_OFDM_TPS_SET2 0xF0AE -#define F367_OFDM_TPS_SETHIERMODE 0xF0AE0070 -#define F367_OFDM_TPS_SETCONST 0xF0AE0003 - -/* TPS_SET3 */ -#define R367_OFDM_TPS_SET3 0xF0AF -#define F367_OFDM_TPS_SETLPCODE 0xF0AF0070 -#define F367_OFDM_TPS_SETHPCODE 0xF0AF0007 - -/* TPS_CTL */ -#define R367_OFDM_TPS_CTL 0xF0B0 -#define F367_OFDM_TPS_IMM 0xF0B00004 -#define F367_OFDM_TPS_BCHDIS 0xF0B00002 -#define F367_OFDM_TPS_UPDDIS 0xF0B00001 - -/* CTL_FFTOSNUM */ -#define R367_OFDM_CTL_FFTOSNUM 0xF0B1 -#define F367_OFDM_SYMBOL_NUMBER 0xF0B1007F - -/* TESTSELECT */ -#define R367_OFDM_TESTSELECT 0xF0B2 -#define F367_OFDM_TEST_SELECT 0xF0B2001F - -/* MSC_REV */ -#define R367_OFDM_MSC_REV 0xF0B3 -#define F367_OFDM_REV_NUMBER 0xF0B300FF - -/* PIR_CTL */ -#define R367_OFDM_PIR_CTL 0xF0B4 -#define F367_OFDM_FREEZE 0xF0B40001 - -/* SNR_CARRIER1 */ -#define R367_OFDM_SNR_CARRIER1 0xF0B5 -#define F367_OFDM_SNR_CARRIER_LO 0xF0B500FF - -/* SNR_CARRIER2 */ -#define R367_OFDM_SNR_CARRIER2 0xF0B6 -#define F367_OFDM_MEAN 0xF0B600C0 -#define F367_OFDM_SNR_CARRIER_HI 0xF0B6001F - -/* PPM_CPAMP */ -#define R367_OFDM_PPM_CPAMP 0xF0B7 -#define F367_OFDM_PPM_CPC 0xF0B700FF - -/* TSM_AP0 */ -#define R367_OFDM_TSM_AP0 0xF0B8 -#define F367_OFDM_ADDRESS_BYTE_0 0xF0B800FF - -/* TSM_AP1 */ -#define R367_OFDM_TSM_AP1 0xF0B9 -#define F367_OFDM_ADDRESS_BYTE_1 0xF0B900FF - -/* TSM_AP2 */ -#define R367_OFDM_TSM_AP2 0xF0BA -#define F367_OFDM_DATA_BYTE_0 0xF0BA00FF - -/* TSM_AP3 */ -#define R367_OFDM_TSM_AP3 0xF0BB -#define F367_OFDM_DATA_BYTE_1 0xF0BB00FF - -/* TSM_AP4 */ -#define R367_OFDM_TSM_AP4 0xF0BC -#define F367_OFDM_DATA_BYTE_2 0xF0BC00FF - -/* TSM_AP5 */ -#define R367_OFDM_TSM_AP5 0xF0BD -#define F367_OFDM_DATA_BYTE_3 0xF0BD00FF - -/* TSM_AP6 */ -#define R367_OFDM_TSM_AP6 0xF0BE -#define F367_OFDM_TSM_AP_6 0xF0BE00FF - -/* TSM_AP7 */ -#define R367_OFDM_TSM_AP7 0xF0BF -#define F367_OFDM_MEM_SELECT_BYTE 0xF0BF00FF - -/* TSTRES */ -#define R367_TSTRES 0xF0C0 -#define F367_FRES_DISPLAY 0xF0C00080 -#define F367_FRES_FIFO_AD 0xF0C00020 -#define F367_FRESRS 0xF0C00010 -#define F367_FRESACS 0xF0C00008 -#define F367_FRESFEC 0xF0C00004 -#define F367_FRES_PRIF 0xF0C00002 -#define F367_FRESCORE 0xF0C00001 - -/* ANACTRL */ -#define R367_ANACTRL 0xF0C1 -#define F367_BYPASS_XTAL 0xF0C10040 -#define F367_BYPASS_PLLXN 0xF0C1000C -#define F367_DIS_PAD_OSC 0xF0C10002 -#define F367_STDBY_PLLXN 0xF0C10001 - -/* TSTBUS */ -#define R367_TSTBUS 0xF0C2 -#define F367_TS_BYTE_CLK_INV 0xF0C20080 -#define F367_CFG_IP 0xF0C20070 -#define F367_CFG_TST 0xF0C2000F - -/* TSTRATE */ -#define R367_TSTRATE 0xF0C6 -#define F367_FORCEPHA 0xF0C60080 -#define F367_FNEWPHA 0xF0C60010 -#define F367_FROT90 0xF0C60008 -#define F367_FR 0xF0C60007 - -/* CONSTMODE */ -#define R367_OFDM_CONSTMODE 0xF0CB -#define F367_OFDM_TST_PRIF 0xF0CB00E0 -#define F367_OFDM_CAR_TYPE 0xF0CB0018 -#define F367_OFDM_CONST_MODE 0xF0CB0003 - -/* CONSTCARR1 */ -#define R367_OFDM_CONSTCARR1 0xF0CC -#define F367_OFDM_CONST_CARR_LO 0xF0CC00FF - -/* CONSTCARR2 */ -#define R367_OFDM_CONSTCARR2 0xF0CD -#define F367_OFDM_CONST_CARR_HI 0xF0CD001F - -/* ICONSTEL */ -#define R367_OFDM_ICONSTEL 0xF0CE -#define F367_OFDM_PICONSTEL 0xF0CE00FF - -/* QCONSTEL */ -#define R367_OFDM_QCONSTEL 0xF0CF -#define F367_OFDM_PQCONSTEL 0xF0CF00FF - -/* TSTBISTRES0 */ -#define R367_OFDM_TSTBISTRES0 0xF0D0 -#define F367_OFDM_BEND_PPM 0xF0D00080 -#define F367_OFDM_BBAD_PPM 0xF0D00040 -#define F367_OFDM_BEND_FFTW 0xF0D00020 -#define F367_OFDM_BBAD_FFTW 0xF0D00010 -#define F367_OFDM_BEND_FFT_BUF 0xF0D00008 -#define F367_OFDM_BBAD_FFT_BUF 0xF0D00004 -#define F367_OFDM_BEND_SYR 0xF0D00002 -#define F367_OFDM_BBAD_SYR 0xF0D00001 - -/* TSTBISTRES1 */ -#define R367_OFDM_TSTBISTRES1 0xF0D1 -#define F367_OFDM_BEND_CHC_CP 0xF0D10080 -#define F367_OFDM_BBAD_CHC_CP 0xF0D10040 -#define F367_OFDM_BEND_CHCI 0xF0D10020 -#define F367_OFDM_BBAD_CHCI 0xF0D10010 -#define F367_OFDM_BEND_BDI 0xF0D10008 -#define F367_OFDM_BBAD_BDI 0xF0D10004 -#define F367_OFDM_BEND_SDI 0xF0D10002 -#define F367_OFDM_BBAD_SDI 0xF0D10001 - -/* TSTBISTRES2 */ -#define R367_OFDM_TSTBISTRES2 0xF0D2 -#define F367_OFDM_BEND_CHC_INC 0xF0D20080 -#define F367_OFDM_BBAD_CHC_INC 0xF0D20040 -#define F367_OFDM_BEND_CHC_SPP 0xF0D20020 -#define F367_OFDM_BBAD_CHC_SPP 0xF0D20010 -#define F367_OFDM_BEND_CHC_CPP 0xF0D20008 -#define F367_OFDM_BBAD_CHC_CPP 0xF0D20004 -#define F367_OFDM_BEND_CHC_SP 0xF0D20002 -#define F367_OFDM_BBAD_CHC_SP 0xF0D20001 - -/* TSTBISTRES3 */ -#define R367_OFDM_TSTBISTRES3 0xF0D3 -#define F367_OFDM_BEND_QAM 0xF0D30080 -#define F367_OFDM_BBAD_QAM 0xF0D30040 -#define F367_OFDM_BEND_SFEC_VIT 0xF0D30020 -#define F367_OFDM_BBAD_SFEC_VIT 0xF0D30010 -#define F367_OFDM_BEND_SFEC_DLINE 0xF0D30008 -#define F367_OFDM_BBAD_SFEC_DLINE 0xF0D30004 -#define F367_OFDM_BEND_SFEC_HW 0xF0D30002 -#define F367_OFDM_BBAD_SFEC_HW 0xF0D30001 - -/* RF_AGC1 */ -#define R367_RF_AGC1 0xF0D4 -#define F367_RF_AGC1_LEVEL_HI 0xF0D400FF - -/* RF_AGC2 */ -#define R367_RF_AGC2 0xF0D5 -#define F367_REF_ADGP 0xF0D50080 -#define F367_STDBY_ADCGP 0xF0D50020 -#define F367_CHANNEL_SEL 0xF0D5001C -#define F367_RF_AGC1_LEVEL_LO 0xF0D50003 - -/* ANADIGCTRL */ -#define R367_ANADIGCTRL 0xF0D7 -#define F367_SEL_CLKDEM 0xF0D70020 -#define F367_EN_BUFFER_Q 0xF0D70010 -#define F367_EN_BUFFER_I 0xF0D70008 -#define F367_ADC_RIS_EGDE 0xF0D70004 -#define F367_SGN_ADC 0xF0D70002 -#define F367_SEL_AD12_SYNC 0xF0D70001 - -/* PLLMDIV */ -#define R367_PLLMDIV 0xF0D8 -#define F367_PLL_MDIV 0xF0D800FF - -/* PLLNDIV */ -#define R367_PLLNDIV 0xF0D9 -#define F367_PLL_NDIV 0xF0D900FF - -/* PLLSETUP */ -#define R367_PLLSETUP 0xF0DA -#define F367_PLL_PDIV 0xF0DA0070 -#define F367_PLL_KDIV 0xF0DA000F - -/* DUAL_AD12 */ -#define R367_DUAL_AD12 0xF0DB -#define F367_FS20M 0xF0DB0020 -#define F367_FS50M 0xF0DB0010 -#define F367_INMODE0 0xF0DB0008 -#define F367_POFFQ 0xF0DB0004 -#define F367_POFFI 0xF0DB0002 -#define F367_INMODE1 0xF0DB0001 - -/* TSTBIST */ -#define R367_TSTBIST 0xF0DC -#define F367_TST_BYP_CLK 0xF0DC0080 -#define F367_TST_GCLKENA_STD 0xF0DC0040 -#define F367_TST_GCLKENA 0xF0DC0020 -#define F367_TST_MEMBIST 0xF0DC001F - -/* PAD_COMP_CTRL */ -#define R367_PAD_COMP_CTRL 0xF0DD -#define F367_COMPTQ 0xF0DD0010 -#define F367_COMPEN 0xF0DD0008 -#define F367_FREEZE2 0xF0DD0004 -#define F367_SLEEP_INHBT 0xF0DD0002 -#define F367_CHIP_SLEEP 0xF0DD0001 - -/* PAD_COMP_WR */ -#define R367_PAD_COMP_WR 0xF0DE -#define F367_WR_ASRC 0xF0DE007F - -/* PAD_COMP_RD */ -#define R367_PAD_COMP_RD 0xF0DF -#define F367_COMPOK 0xF0DF0080 -#define F367_RD_ASRC 0xF0DF007F - -/* SYR_TARGET_FFTADJT_MSB */ -#define R367_OFDM_SYR_TARGET_FFTADJT_MSB 0xF100 -#define F367_OFDM_SYR_START 0xF1000080 -#define F367_OFDM_SYR_TARGET_FFTADJ_HI 0xF100000F - -/* SYR_TARGET_FFTADJT_LSB */ -#define R367_OFDM_SYR_TARGET_FFTADJT_LSB 0xF101 -#define F367_OFDM_SYR_TARGET_FFTADJ_LO 0xF10100FF - -/* SYR_TARGET_CHCADJT_MSB */ -#define R367_OFDM_SYR_TARGET_CHCADJT_MSB 0xF102 -#define F367_OFDM_SYR_TARGET_CHCADJ_HI 0xF102000F - -/* SYR_TARGET_CHCADJT_LSB */ -#define R367_OFDM_SYR_TARGET_CHCADJT_LSB 0xF103 -#define F367_OFDM_SYR_TARGET_CHCADJ_LO 0xF10300FF - -/* SYR_FLAG */ -#define R367_OFDM_SYR_FLAG 0xF104 -#define F367_OFDM_TRIG_FLG1 0xF1040080 -#define F367_OFDM_TRIG_FLG0 0xF1040040 -#define F367_OFDM_FFT_FLG1 0xF1040008 -#define F367_OFDM_FFT_FLG0 0xF1040004 -#define F367_OFDM_CHC_FLG1 0xF1040002 -#define F367_OFDM_CHC_FLG0 0xF1040001 - -/* CRL_TARGET1 */ -#define R367_OFDM_CRL_TARGET1 0xF105 -#define F367_OFDM_CRL_START 0xF1050080 -#define F367_OFDM_CRL_TARGET_VHI 0xF105000F - -/* CRL_TARGET2 */ -#define R367_OFDM_CRL_TARGET2 0xF106 -#define F367_OFDM_CRL_TARGET_HI 0xF10600FF - -/* CRL_TARGET3 */ -#define R367_OFDM_CRL_TARGET3 0xF107 -#define F367_OFDM_CRL_TARGET_LO 0xF10700FF - -/* CRL_TARGET4 */ -#define R367_OFDM_CRL_TARGET4 0xF108 -#define F367_OFDM_CRL_TARGET_VLO 0xF10800FF - -/* CRL_FLAG */ -#define R367_OFDM_CRL_FLAG 0xF109 -#define F367_OFDM_CRL_FLAG1 0xF1090002 -#define F367_OFDM_CRL_FLAG0 0xF1090001 - -/* TRL_TARGET1 */ -#define R367_OFDM_TRL_TARGET1 0xF10A -#define F367_OFDM_TRL_TARGET_HI 0xF10A00FF - -/* TRL_TARGET2 */ -#define R367_OFDM_TRL_TARGET2 0xF10B -#define F367_OFDM_TRL_TARGET_LO 0xF10B00FF - -/* TRL_CHC */ -#define R367_OFDM_TRL_CHC 0xF10C -#define F367_OFDM_TRL_START 0xF10C0080 -#define F367_OFDM_CHC_START 0xF10C0040 -#define F367_OFDM_TRL_FLAG1 0xF10C0002 -#define F367_OFDM_TRL_FLAG0 0xF10C0001 - -/* CHC_SNR_TARG */ -#define R367_OFDM_CHC_SNR_TARG 0xF10D -#define F367_OFDM_CHC_SNR_TARGET 0xF10D00FF - -/* TOP_TRACK */ -#define R367_OFDM_TOP_TRACK 0xF10E -#define F367_OFDM_TOP_START 0xF10E0080 -#define F367_OFDM_FIRST_FLAG 0xF10E0070 -#define F367_OFDM_TOP_FLAG1 0xF10E0008 -#define F367_OFDM_TOP_FLAG0 0xF10E0004 -#define F367_OFDM_CHC_FLAG1 0xF10E0002 -#define F367_OFDM_CHC_FLAG0 0xF10E0001 - -/* TRACKER_FREE1 */ -#define R367_OFDM_TRACKER_FREE1 0xF10F -#define F367_OFDM_TRACKER_FREE_1 0xF10F00FF - -/* ERROR_CRL1 */ -#define R367_OFDM_ERROR_CRL1 0xF110 -#define F367_OFDM_ERROR_CRL_VHI 0xF11000FF - -/* ERROR_CRL2 */ -#define R367_OFDM_ERROR_CRL2 0xF111 -#define F367_OFDM_ERROR_CRL_HI 0xF11100FF - -/* ERROR_CRL3 */ -#define R367_OFDM_ERROR_CRL3 0xF112 -#define F367_OFDM_ERROR_CRL_LOI 0xF11200FF - -/* ERROR_CRL4 */ -#define R367_OFDM_ERROR_CRL4 0xF113 -#define F367_OFDM_ERROR_CRL_VLO 0xF11300FF - -/* DEC_NCO1 */ -#define R367_OFDM_DEC_NCO1 0xF114 -#define F367_OFDM_DEC_NCO_VHI 0xF11400FF - -/* DEC_NCO2 */ -#define R367_OFDM_DEC_NCO2 0xF115 -#define F367_OFDM_DEC_NCO_HI 0xF11500FF - -/* DEC_NCO3 */ -#define R367_OFDM_DEC_NCO3 0xF116 -#define F367_OFDM_DEC_NCO_LO 0xF11600FF - -/* SNR */ -#define R367_OFDM_SNR 0xF117 -#define F367_OFDM_SNRATIO 0xF11700FF - -/* SYR_FFTADJ1 */ -#define R367_OFDM_SYR_FFTADJ1 0xF118 -#define F367_OFDM_SYR_FFTADJ_HI 0xF11800FF - -/* SYR_FFTADJ2 */ -#define R367_OFDM_SYR_FFTADJ2 0xF119 -#define F367_OFDM_SYR_FFTADJ_LO 0xF11900FF - -/* SYR_CHCADJ1 */ -#define R367_OFDM_SYR_CHCADJ1 0xF11A -#define F367_OFDM_SYR_CHCADJ_HI 0xF11A00FF - -/* SYR_CHCADJ2 */ -#define R367_OFDM_SYR_CHCADJ2 0xF11B -#define F367_OFDM_SYR_CHCADJ_LO 0xF11B00FF - -/* SYR_OFF */ -#define R367_OFDM_SYR_OFF 0xF11C -#define F367_OFDM_SYR_OFFSET 0xF11C00FF - -/* PPM_OFFSET1 */ -#define R367_OFDM_PPM_OFFSET1 0xF11D -#define F367_OFDM_PPM_OFFSET_HI 0xF11D00FF - -/* PPM_OFFSET2 */ -#define R367_OFDM_PPM_OFFSET2 0xF11E -#define F367_OFDM_PPM_OFFSET_LO 0xF11E00FF - -/* TRACKER_FREE2 */ -#define R367_OFDM_TRACKER_FREE2 0xF11F -#define F367_OFDM_TRACKER_FREE_2 0xF11F00FF - -/* DEBG_LT10 */ -#define R367_OFDM_DEBG_LT10 0xF120 -#define F367_OFDM_DEBUG_LT10 0xF12000FF - -/* DEBG_LT11 */ -#define R367_OFDM_DEBG_LT11 0xF121 -#define F367_OFDM_DEBUG_LT11 0xF12100FF - -/* DEBG_LT12 */ -#define R367_OFDM_DEBG_LT12 0xF122 -#define F367_OFDM_DEBUG_LT12 0xF12200FF - -/* DEBG_LT13 */ -#define R367_OFDM_DEBG_LT13 0xF123 -#define F367_OFDM_DEBUG_LT13 0xF12300FF - -/* DEBG_LT14 */ -#define R367_OFDM_DEBG_LT14 0xF124 -#define F367_OFDM_DEBUG_LT14 0xF12400FF - -/* DEBG_LT15 */ -#define R367_OFDM_DEBG_LT15 0xF125 -#define F367_OFDM_DEBUG_LT15 0xF12500FF - -/* DEBG_LT16 */ -#define R367_OFDM_DEBG_LT16 0xF126 -#define F367_OFDM_DEBUG_LT16 0xF12600FF - -/* DEBG_LT17 */ -#define R367_OFDM_DEBG_LT17 0xF127 -#define F367_OFDM_DEBUG_LT17 0xF12700FF - -/* DEBG_LT18 */ -#define R367_OFDM_DEBG_LT18 0xF128 -#define F367_OFDM_DEBUG_LT18 0xF12800FF - -/* DEBG_LT19 */ -#define R367_OFDM_DEBG_LT19 0xF129 -#define F367_OFDM_DEBUG_LT19 0xF12900FF - -/* DEBG_LT1A */ -#define R367_OFDM_DEBG_LT1A 0xF12A -#define F367_OFDM_DEBUG_LT1A 0xF12A00FF - -/* DEBG_LT1B */ -#define R367_OFDM_DEBG_LT1B 0xF12B -#define F367_OFDM_DEBUG_LT1B 0xF12B00FF - -/* DEBG_LT1C */ -#define R367_OFDM_DEBG_LT1C 0xF12C -#define F367_OFDM_DEBUG_LT1C 0xF12C00FF - -/* DEBG_LT1D */ -#define R367_OFDM_DEBG_LT1D 0xF12D -#define F367_OFDM_DEBUG_LT1D 0xF12D00FF - -/* DEBG_LT1E */ -#define R367_OFDM_DEBG_LT1E 0xF12E -#define F367_OFDM_DEBUG_LT1E 0xF12E00FF - -/* DEBG_LT1F */ -#define R367_OFDM_DEBG_LT1F 0xF12F -#define F367_OFDM_DEBUG_LT1F 0xF12F00FF - -/* RCCFGH */ -#define R367_OFDM_RCCFGH 0xF200 -#define F367_OFDM_TSRCFIFO_DVBCI 0xF2000080 -#define F367_OFDM_TSRCFIFO_SERIAL 0xF2000040 -#define F367_OFDM_TSRCFIFO_DISABLE 0xF2000020 -#define F367_OFDM_TSFIFO_2TORC 0xF2000010 -#define F367_OFDM_TSRCFIFO_HSGNLOUT 0xF2000008 -#define F367_OFDM_TSRCFIFO_ERRMODE 0xF2000006 -#define F367_OFDM_RCCFGH_0 0xF2000001 - -/* RCCFGM */ -#define R367_OFDM_RCCFGM 0xF201 -#define F367_OFDM_TSRCFIFO_MANSPEED 0xF20100C0 -#define F367_OFDM_TSRCFIFO_PERMDATA 0xF2010020 -#define F367_OFDM_TSRCFIFO_NONEWSGNL 0xF2010010 -#define F367_OFDM_RCBYTE_OVERSAMPLING 0xF201000E -#define F367_OFDM_TSRCFIFO_INVDATA 0xF2010001 - -/* RCCFGL */ -#define R367_OFDM_RCCFGL 0xF202 -#define F367_OFDM_TSRCFIFO_BCLKDEL1CK 0xF20200C0 -#define F367_OFDM_RCCFGL_5 0xF2020020 -#define F367_OFDM_TSRCFIFO_DUTY50 0xF2020010 -#define F367_OFDM_TSRCFIFO_NSGNL2DATA 0xF2020008 -#define F367_OFDM_TSRCFIFO_DISSERMUX 0xF2020004 -#define F367_OFDM_RCCFGL_1 0xF2020002 -#define F367_OFDM_TSRCFIFO_STOPCKDIS 0xF2020001 - -/* RCINSDELH */ -#define R367_OFDM_RCINSDELH 0xF203 -#define F367_OFDM_TSRCDEL_SYNCBYTE 0xF2030080 -#define F367_OFDM_TSRCDEL_XXHEADER 0xF2030040 -#define F367_OFDM_TSRCDEL_BBHEADER 0xF2030020 -#define F367_OFDM_TSRCDEL_DATAFIELD 0xF2030010 -#define F367_OFDM_TSRCINSDEL_ISCR 0xF2030008 -#define F367_OFDM_TSRCINSDEL_NPD 0xF2030004 -#define F367_OFDM_TSRCINSDEL_RSPARITY 0xF2030002 -#define F367_OFDM_TSRCINSDEL_CRC8 0xF2030001 - -/* RCINSDELM */ -#define R367_OFDM_RCINSDELM 0xF204 -#define F367_OFDM_TSRCINS_BBPADDING 0xF2040080 -#define F367_OFDM_TSRCINS_BCHFEC 0xF2040040 -#define F367_OFDM_TSRCINS_LDPCFEC 0xF2040020 -#define F367_OFDM_TSRCINS_EMODCOD 0xF2040010 -#define F367_OFDM_TSRCINS_TOKEN 0xF2040008 -#define F367_OFDM_TSRCINS_XXXERR 0xF2040004 -#define F367_OFDM_TSRCINS_MATYPE 0xF2040002 -#define F367_OFDM_TSRCINS_UPL 0xF2040001 - -/* RCINSDELL */ -#define R367_OFDM_RCINSDELL 0xF205 -#define F367_OFDM_TSRCINS_DFL 0xF2050080 -#define F367_OFDM_TSRCINS_SYNCD 0xF2050040 -#define F367_OFDM_TSRCINS_BLOCLEN 0xF2050020 -#define F367_OFDM_TSRCINS_SIGPCOUNT 0xF2050010 -#define F367_OFDM_TSRCINS_FIFO 0xF2050008 -#define F367_OFDM_TSRCINS_REALPACK 0xF2050004 -#define F367_OFDM_TSRCINS_TSCONFIG 0xF2050002 -#define F367_OFDM_TSRCINS_LATENCY 0xF2050001 - -/* RCSTATUS */ -#define R367_OFDM_RCSTATUS 0xF206 -#define F367_OFDM_TSRCFIFO_LINEOK 0xF2060080 -#define F367_OFDM_TSRCFIFO_ERROR 0xF2060040 -#define F367_OFDM_TSRCFIFO_DATA7 0xF2060020 -#define F367_OFDM_RCSTATUS_4 0xF2060010 -#define F367_OFDM_TSRCFIFO_DEMODSEL 0xF2060008 -#define F367_OFDM_TSRC1FIFOSPEED_STORE 0xF2060004 -#define F367_OFDM_RCSTATUS_1 0xF2060002 -#define F367_OFDM_TSRCSERIAL_IMPOSSIBLE 0xF2060001 - -/* RCSPEED */ -#define R367_OFDM_RCSPEED 0xF207 -#define F367_OFDM_TSRCFIFO_OUTSPEED 0xF20700FF - -/* RCDEBUGM */ -#define R367_OFDM_RCDEBUGM 0xF208 -#define F367_OFDM_SD_UNSYNC 0xF2080080 -#define F367_OFDM_ULFLOCK_DETECTM 0xF2080040 -#define F367_OFDM_SUL_SELECTOS 0xF2080020 -#define F367_OFDM_DILUL_NOSCRBLE 0xF2080010 -#define F367_OFDM_NUL_SCRB 0xF2080008 -#define F367_OFDM_UL_SCRB 0xF2080004 -#define F367_OFDM_SCRAULBAD 0xF2080002 -#define F367_OFDM_SCRAUL_UNSYNC 0xF2080001 - -/* RCDEBUGL */ -#define R367_OFDM_RCDEBUGL 0xF209 -#define F367_OFDM_RS_ERR 0xF2090080 -#define F367_OFDM_LLFLOCK_DETECTM 0xF2090040 -#define F367_OFDM_NOT_SUL_SELECTOS 0xF2090020 -#define F367_OFDM_DILLL_NOSCRBLE 0xF2090010 -#define F367_OFDM_NLL_SCRB 0xF2090008 -#define F367_OFDM_LL_SCRB 0xF2090004 -#define F367_OFDM_SCRALLBAD 0xF2090002 -#define F367_OFDM_SCRALL_UNSYNC 0xF2090001 - -/* RCOBSCFG */ -#define R367_OFDM_RCOBSCFG 0xF20A -#define F367_OFDM_TSRCFIFO_OBSCFG 0xF20A00FF - -/* RCOBSM */ -#define R367_OFDM_RCOBSM 0xF20B -#define F367_OFDM_TSRCFIFO_OBSDATA_HI 0xF20B00FF - -/* RCOBSL */ -#define R367_OFDM_RCOBSL 0xF20C -#define F367_OFDM_TSRCFIFO_OBSDATA_LO 0xF20C00FF - -/* RCFECSPY */ -#define R367_OFDM_RCFECSPY 0xF210 -#define F367_OFDM_SPYRC_ENABLE 0xF2100080 -#define F367_OFDM_RCNO_SYNCBYTE 0xF2100040 -#define F367_OFDM_RCSERIAL_MODE 0xF2100020 -#define F367_OFDM_RCUNUSUAL_PACKET 0xF2100010 -#define F367_OFDM_BERRCMETER_DATAMODE 0xF210000C -#define F367_OFDM_BERRCMETER_LMODE 0xF2100002 -#define F367_OFDM_BERRCMETER_RESET 0xF2100001 - -/* RCFSPYCFG */ -#define R367_OFDM_RCFSPYCFG 0xF211 -#define F367_OFDM_FECSPYRC_INPUT 0xF21100C0 -#define F367_OFDM_RCRST_ON_ERROR 0xF2110020 -#define F367_OFDM_RCONE_SHOT 0xF2110010 -#define F367_OFDM_RCI2C_MODE 0xF211000C -#define F367_OFDM_SPYRC_HSTERESIS 0xF2110003 - -/* RCFSPYDATA */ -#define R367_OFDM_RCFSPYDATA 0xF212 -#define F367_OFDM_SPYRC_STUFFING 0xF2120080 -#define F367_OFDM_RCNOERR_PKTJITTER 0xF2120040 -#define F367_OFDM_SPYRC_CNULLPKT 0xF2120020 -#define F367_OFDM_SPYRC_OUTDATA_MODE 0xF212001F - -/* RCFSPYOUT */ -#define R367_OFDM_RCFSPYOUT 0xF213 -#define F367_OFDM_FSPYRC_DIRECT 0xF2130080 -#define F367_OFDM_RCFSPYOUT_6 0xF2130040 -#define F367_OFDM_SPYRC_OUTDATA_BUS 0xF2130038 -#define F367_OFDM_RCSTUFF_MODE 0xF2130007 - -/* RCFSTATUS */ -#define R367_OFDM_RCFSTATUS 0xF214 -#define F367_OFDM_SPYRC_ENDSIM 0xF2140080 -#define F367_OFDM_RCVALID_SIM 0xF2140040 -#define F367_OFDM_RCFOUND_SIGNAL 0xF2140020 -#define F367_OFDM_RCDSS_SYNCBYTE 0xF2140010 -#define F367_OFDM_RCRESULT_STATE 0xF214000F - -/* RCFGOODPACK */ -#define R367_OFDM_RCFGOODPACK 0xF215 -#define F367_OFDM_RCGOOD_PACKET 0xF21500FF - -/* RCFPACKCNT */ -#define R367_OFDM_RCFPACKCNT 0xF216 -#define F367_OFDM_RCPACKET_COUNTER 0xF21600FF - -/* RCFSPYMISC */ -#define R367_OFDM_RCFSPYMISC 0xF217 -#define F367_OFDM_RCLABEL_COUNTER 0xF21700FF - -/* RCFBERCPT4 */ -#define R367_OFDM_RCFBERCPT4 0xF218 -#define F367_OFDM_FBERRCMETER_CPT_MMMMSB 0xF21800FF - -/* RCFBERCPT3 */ -#define R367_OFDM_RCFBERCPT3 0xF219 -#define F367_OFDM_FBERRCMETER_CPT_MMMSB 0xF21900FF - -/* RCFBERCPT2 */ -#define R367_OFDM_RCFBERCPT2 0xF21A -#define F367_OFDM_FBERRCMETER_CPT_MMSB 0xF21A00FF - -/* RCFBERCPT1 */ -#define R367_OFDM_RCFBERCPT1 0xF21B -#define F367_OFDM_FBERRCMETER_CPT_MSB 0xF21B00FF - -/* RCFBERCPT0 */ -#define R367_OFDM_RCFBERCPT0 0xF21C -#define F367_OFDM_FBERRCMETER_CPT_LSB 0xF21C00FF - -/* RCFBERERR2 */ -#define R367_OFDM_RCFBERERR2 0xF21D -#define F367_OFDM_FBERRCMETER_ERR_HI 0xF21D00FF - -/* RCFBERERR1 */ -#define R367_OFDM_RCFBERERR1 0xF21E -#define F367_OFDM_FBERRCMETER_ERR 0xF21E00FF - -/* RCFBERERR0 */ -#define R367_OFDM_RCFBERERR0 0xF21F -#define F367_OFDM_FBERRCMETER_ERR_LO 0xF21F00FF - -/* RCFSTATESM */ -#define R367_OFDM_RCFSTATESM 0xF220 -#define F367_OFDM_RCRSTATE_F 0xF2200080 -#define F367_OFDM_RCRSTATE_E 0xF2200040 -#define F367_OFDM_RCRSTATE_D 0xF2200020 -#define F367_OFDM_RCRSTATE_C 0xF2200010 -#define F367_OFDM_RCRSTATE_B 0xF2200008 -#define F367_OFDM_RCRSTATE_A 0xF2200004 -#define F367_OFDM_RCRSTATE_9 0xF2200002 -#define F367_OFDM_RCRSTATE_8 0xF2200001 - -/* RCFSTATESL */ -#define R367_OFDM_RCFSTATESL 0xF221 -#define F367_OFDM_RCRSTATE_7 0xF2210080 -#define F367_OFDM_RCRSTATE_6 0xF2210040 -#define F367_OFDM_RCRSTATE_5 0xF2210020 -#define F367_OFDM_RCRSTATE_4 0xF2210010 -#define F367_OFDM_RCRSTATE_3 0xF2210008 -#define F367_OFDM_RCRSTATE_2 0xF2210004 -#define F367_OFDM_RCRSTATE_1 0xF2210002 -#define F367_OFDM_RCRSTATE_0 0xF2210001 - -/* RCFSPYBER */ -#define R367_OFDM_RCFSPYBER 0xF222 -#define F367_OFDM_RCFSPYBER_7 0xF2220080 -#define F367_OFDM_SPYRCOBS_XORREAD 0xF2220040 -#define F367_OFDM_FSPYRCBER_OBSMODE 0xF2220020 -#define F367_OFDM_FSPYRCBER_SYNCBYT 0xF2220010 -#define F367_OFDM_FSPYRCBER_UNSYNC 0xF2220008 -#define F367_OFDM_FSPYRCBER_CTIME 0xF2220007 - -/* RCFSPYDISTM */ -#define R367_OFDM_RCFSPYDISTM 0xF223 -#define F367_OFDM_RCPKTTIME_DISTANCE_HI 0xF22300FF - -/* RCFSPYDISTL */ -#define R367_OFDM_RCFSPYDISTL 0xF224 -#define F367_OFDM_RCPKTTIME_DISTANCE_LO 0xF22400FF - -/* RCFSPYOBS7 */ -#define R367_OFDM_RCFSPYOBS7 0xF228 -#define F367_OFDM_RCSPYOBS_SPYFAIL 0xF2280080 -#define F367_OFDM_RCSPYOBS_SPYFAIL1 0xF2280040 -#define F367_OFDM_RCSPYOBS_ERROR 0xF2280020 -#define F367_OFDM_RCSPYOBS_STROUT 0xF2280010 -#define F367_OFDM_RCSPYOBS_RESULTSTATE1 0xF228000F - -/* RCFSPYOBS6 */ -#define R367_OFDM_RCFSPYOBS6 0xF229 -#define F367_OFDM_RCSPYOBS_RESULTSTATE0 0xF22900F0 -#define F367_OFDM_RCSPYOBS_RESULTSTATEM1 0xF229000F - -/* RCFSPYOBS5 */ -#define R367_OFDM_RCFSPYOBS5 0xF22A -#define F367_OFDM_RCSPYOBS_BYTEOFPACKET1 0xF22A00FF - -/* RCFSPYOBS4 */ -#define R367_OFDM_RCFSPYOBS4 0xF22B -#define F367_OFDM_RCSPYOBS_BYTEVALUE1 0xF22B00FF - -/* RCFSPYOBS3 */ -#define R367_OFDM_RCFSPYOBS3 0xF22C -#define F367_OFDM_RCSPYOBS_DATA1 0xF22C00FF - -/* RCFSPYOBS2 */ -#define R367_OFDM_RCFSPYOBS2 0xF22D -#define F367_OFDM_RCSPYOBS_DATA0 0xF22D00FF - -/* RCFSPYOBS1 */ -#define R367_OFDM_RCFSPYOBS1 0xF22E -#define F367_OFDM_RCSPYOBS_DATAM1 0xF22E00FF - -/* RCFSPYOBS0 */ -#define R367_OFDM_RCFSPYOBS0 0xF22F -#define F367_OFDM_RCSPYOBS_DATAM2 0xF22F00FF - -/* TSGENERAL */ -#define R367_TSGENERAL 0xF230 -#define F367_TSGENERAL_7 0xF2300080 -#define F367_TSGENERAL_6 0xF2300040 -#define F367_TSFIFO_BCLK1ALL 0xF2300020 -#define F367_TSGENERAL_4 0xF2300010 -#define F367_MUXSTREAM_OUTMODE 0xF2300008 -#define F367_TSFIFO_PERMPARAL 0xF2300006 -#define F367_RST_REEDSOLO 0xF2300001 - -/* RC1SPEED */ -#define R367_RC1SPEED 0xF231 -#define F367_TSRCFIFO1_OUTSPEED 0xF23100FF - -/* TSGSTATUS */ -#define R367_TSGSTATUS 0xF232 -#define F367_TSGSTATUS_7 0xF2320080 -#define F367_TSGSTATUS_6 0xF2320040 -#define F367_RSMEM_FULL 0xF2320020 -#define F367_RS_MULTCALC 0xF2320010 -#define F367_RSIN_OVERTIME 0xF2320008 -#define F367_TSFIFO3_DEMODSEL 0xF2320004 -#define F367_TSFIFO2_DEMODSEL 0xF2320002 -#define F367_TSFIFO1_DEMODSEL 0xF2320001 - - -/* FECM */ -#define R367_OFDM_FECM 0xF233 -#define F367_OFDM_DSS_DVB 0xF2330080 -#define F367_OFDM_DEMOD_BYPASS 0xF2330040 -#define F367_OFDM_CMP_SLOWMODE 0xF2330020 -#define F367_OFDM_DSS_SRCH 0xF2330010 -#define F367_OFDM_FECM_3 0xF2330008 -#define F367_OFDM_DIFF_MODEVIT 0xF2330004 -#define F367_OFDM_SYNCVIT 0xF2330002 -#define F367_OFDM_I2CSYM 0xF2330001 - -/* VTH12 */ -#define R367_OFDM_VTH12 0xF234 -#define F367_OFDM_VTH_12 0xF23400FF - -/* VTH23 */ -#define R367_OFDM_VTH23 0xF235 -#define F367_OFDM_VTH_23 0xF23500FF - -/* VTH34 */ -#define R367_OFDM_VTH34 0xF236 -#define F367_OFDM_VTH_34 0xF23600FF - -/* VTH56 */ -#define R367_OFDM_VTH56 0xF237 -#define F367_OFDM_VTH_56 0xF23700FF - -/* VTH67 */ -#define R367_OFDM_VTH67 0xF238 -#define F367_OFDM_VTH_67 0xF23800FF - -/* VTH78 */ -#define R367_OFDM_VTH78 0xF239 -#define F367_OFDM_VTH_78 0xF23900FF - -/* VITCURPUN */ -#define R367_OFDM_VITCURPUN 0xF23A -#define F367_OFDM_VIT_MAPPING 0xF23A00E0 -#define F367_OFDM_VIT_CURPUN 0xF23A001F - -/* VERROR */ -#define R367_OFDM_VERROR 0xF23B -#define F367_OFDM_REGERR_VIT 0xF23B00FF - -/* PRVIT */ -#define R367_OFDM_PRVIT 0xF23C -#define F367_OFDM_PRVIT_7 0xF23C0080 -#define F367_OFDM_DIS_VTHLOCK 0xF23C0040 -#define F367_OFDM_E7_8VIT 0xF23C0020 -#define F367_OFDM_E6_7VIT 0xF23C0010 -#define F367_OFDM_E5_6VIT 0xF23C0008 -#define F367_OFDM_E3_4VIT 0xF23C0004 -#define F367_OFDM_E2_3VIT 0xF23C0002 -#define F367_OFDM_E1_2VIT 0xF23C0001 - -/* VAVSRVIT */ -#define R367_OFDM_VAVSRVIT 0xF23D -#define F367_OFDM_AMVIT 0xF23D0080 -#define F367_OFDM_FROZENVIT 0xF23D0040 -#define F367_OFDM_SNVIT 0xF23D0030 -#define F367_OFDM_TOVVIT 0xF23D000C -#define F367_OFDM_HYPVIT 0xF23D0003 - -/* VSTATUSVIT */ -#define R367_OFDM_VSTATUSVIT 0xF23E -#define F367_OFDM_VITERBI_ON 0xF23E0080 -#define F367_OFDM_END_LOOPVIT 0xF23E0040 -#define F367_OFDM_VITERBI_DEPRF 0xF23E0020 -#define F367_OFDM_PRFVIT 0xF23E0010 -#define F367_OFDM_LOCKEDVIT 0xF23E0008 -#define F367_OFDM_VITERBI_DELOCK 0xF23E0004 -#define F367_OFDM_VIT_DEMODSEL 0xF23E0002 -#define F367_OFDM_VITERBI_COMPOUT 0xF23E0001 - -/* VTHINUSE */ -#define R367_OFDM_VTHINUSE 0xF23F -#define F367_OFDM_VIT_INUSE 0xF23F00FF - -/* KDIV12 */ -#define R367_OFDM_KDIV12 0xF240 -#define F367_OFDM_KDIV12_MANUAL 0xF2400080 -#define F367_OFDM_K_DIVIDER_12 0xF240007F - -/* KDIV23 */ -#define R367_OFDM_KDIV23 0xF241 -#define F367_OFDM_KDIV23_MANUAL 0xF2410080 -#define F367_OFDM_K_DIVIDER_23 0xF241007F - -/* KDIV34 */ -#define R367_OFDM_KDIV34 0xF242 -#define F367_OFDM_KDIV34_MANUAL 0xF2420080 -#define F367_OFDM_K_DIVIDER_34 0xF242007F - -/* KDIV56 */ -#define R367_OFDM_KDIV56 0xF243 -#define F367_OFDM_KDIV56_MANUAL 0xF2430080 -#define F367_OFDM_K_DIVIDER_56 0xF243007F - -/* KDIV67 */ -#define R367_OFDM_KDIV67 0xF244 -#define F367_OFDM_KDIV67_MANUAL 0xF2440080 -#define F367_OFDM_K_DIVIDER_67 0xF244007F - -/* KDIV78 */ -#define R367_OFDM_KDIV78 0xF245 -#define F367_OFDM_KDIV78_MANUAL 0xF2450080 -#define F367_OFDM_K_DIVIDER_78 0xF245007F - -/* SIGPOWER */ -#define R367_OFDM_SIGPOWER 0xF246 -#define F367_OFDM_SIGPOWER_MANUAL 0xF2460080 -#define F367_OFDM_SIG_POWER 0xF246007F - -/* DEMAPVIT */ -#define R367_OFDM_DEMAPVIT 0xF247 -#define F367_OFDM_DEMAPVIT_7 0xF2470080 -#define F367_OFDM_K_DIVIDER_VIT 0xF247007F - -/* VITSCALE */ -#define R367_OFDM_VITSCALE 0xF248 -#define F367_OFDM_NVTH_NOSRANGE 0xF2480080 -#define F367_OFDM_VERROR_MAXMODE 0xF2480040 -#define F367_OFDM_KDIV_MODE 0xF2480030 -#define F367_OFDM_NSLOWSN_LOCKED 0xF2480008 -#define F367_OFDM_DELOCK_PRFLOSS 0xF2480004 -#define F367_OFDM_DIS_RSFLOCK 0xF2480002 -#define F367_OFDM_VITSCALE_0 0xF2480001 - -/* FFEC1PRG */ -#define R367_OFDM_FFEC1PRG 0xF249 -#define F367_OFDM_FDSS_DVB 0xF2490080 -#define F367_OFDM_FDSS_SRCH 0xF2490040 -#define F367_OFDM_FFECPROG_5 0xF2490020 -#define F367_OFDM_FFECPROG_4 0xF2490010 -#define F367_OFDM_FFECPROG_3 0xF2490008 -#define F367_OFDM_FFECPROG_2 0xF2490004 -#define F367_OFDM_FTS1_DISABLE 0xF2490002 -#define F367_OFDM_FTS2_DISABLE 0xF2490001 - -/* FVITCURPUN */ -#define R367_OFDM_FVITCURPUN 0xF24A -#define F367_OFDM_FVIT_MAPPING 0xF24A00E0 -#define F367_OFDM_FVIT_CURPUN 0xF24A001F - -/* FVERROR */ -#define R367_OFDM_FVERROR 0xF24B -#define F367_OFDM_FREGERR_VIT 0xF24B00FF - -/* FVSTATUSVIT */ -#define R367_OFDM_FVSTATUSVIT 0xF24C -#define F367_OFDM_FVITERBI_ON 0xF24C0080 -#define F367_OFDM_F1END_LOOPVIT 0xF24C0040 -#define F367_OFDM_FVITERBI_DEPRF 0xF24C0020 -#define F367_OFDM_FPRFVIT 0xF24C0010 -#define F367_OFDM_FLOCKEDVIT 0xF24C0008 -#define F367_OFDM_FVITERBI_DELOCK 0xF24C0004 -#define F367_OFDM_FVIT_DEMODSEL 0xF24C0002 -#define F367_OFDM_FVITERBI_COMPOUT 0xF24C0001 - -/* DEBUG_LT1 */ -#define R367_OFDM_DEBUG_LT1 0xF24D -#define F367_OFDM_DBG_LT1 0xF24D00FF - -/* DEBUG_LT2 */ -#define R367_OFDM_DEBUG_LT2 0xF24E -#define F367_OFDM_DBG_LT2 0xF24E00FF - -/* DEBUG_LT3 */ -#define R367_OFDM_DEBUG_LT3 0xF24F -#define F367_OFDM_DBG_LT3 0xF24F00FF - - /* TSTSFMET */ -#define R367_OFDM_TSTSFMET 0xF250 -#define F367_OFDM_TSTSFEC_METRIQUES 0xF25000FF - - /* SELOUT */ -#define R367_OFDM_SELOUT 0xF252 -#define F367_OFDM_EN_SYNC 0xF2520080 -#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 -#define F367_OFDM_SELOUT_5 0xF2520020 -#define F367_OFDM_SELOUT_4 0xF2520010 -#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 - - /* TSYNC */ -#define R367_OFDM_TSYNC 0xF253 -#define F367_OFDM_CURPUN_INCMODE 0xF2530080 -#define F367_OFDM_CERR_TSTMODE 0xF2530040 -#define F367_OFDM_SHIFTSOF_MODE 0xF2530030 -#define F367_OFDM_SLOWPHA_MODE 0xF2530008 -#define F367_OFDM_PXX_BYPALL 0xF2530004 -#define F367_OFDM_FROTA45_FIRST 0xF2530002 -#define F367_OFDM_TST_BCHERROR 0xF2530001 - - /* TSTERR */ -#define R367_OFDM_TSTERR 0xF254 -#define F367_OFDM_TST_LONGPKT 0xF2540080 -#define F367_OFDM_TST_ISSYION 0xF2540040 -#define F367_OFDM_TST_NPDON 0xF2540020 -#define F367_OFDM_TSTERR_4 0xF2540010 -#define F367_OFDM_TRACEBACK_MODE 0xF2540008 -#define F367_OFDM_TST_RSPARITY 0xF2540004 -#define F367_OFDM_METRIQUE_MODE 0xF2540003 - - /* TSFSYNC */ -#define R367_OFDM_TSFSYNC 0xF255 -#define F367_OFDM_EN_SFECSYNC 0xF2550080 -#define F367_OFDM_EN_SFECDEMAP 0xF2550040 -#define F367_OFDM_SFCERR_TSTMODE 0xF2550020 -#define F367_OFDM_SFECPXX_BYPALL 0xF2550010 -#define F367_OFDM_SFECTSTSYNCHRO_MODE 0xF255000F - - /* TSTSFERR */ -#define R367_OFDM_TSTSFERR 0xF256 -#define F367_OFDM_TSTSTERR_7 0xF2560080 -#define F367_OFDM_TSTSTERR_6 0xF2560040 -#define F367_OFDM_TSTSTERR_5 0xF2560020 -#define F367_OFDM_TSTSTERR_4 0xF2560010 -#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 -#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 -#define F367_OFDM_SFECMETRIQUE_MODE 0xF2560003 - - /* TSTTSSF1 */ -#define R367_OFDM_TSTTSSF1 0xF258 -#define F367_OFDM_TSTERSSF 0xF2580080 -#define F367_OFDM_TSTTSSFEN 0xF2580040 -#define F367_OFDM_SFEC_OUTMODE 0xF2580030 -#define F367_OFDM_XLSF_NOFTHRESHOLD 0xF2580008 -#define F367_OFDM_TSTTSSF_STACKSEL 0xF2580007 - - /* TSTTSSF2 */ -#define R367_OFDM_TSTTSSF2 0xF259 -#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 -#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 -#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 -#define F367_OFDM_TSTTSSF_SELECT 0xF259001F - - /* TSTTSSF3 */ -#define R367_OFDM_TSTTSSF3 0xF25A -#define F367_OFDM_TSTTSSF3_7 0xF25A0080 -#define F367_OFDM_TSTTSSF3_6 0xF25A0040 -#define F367_OFDM_TSTTSSF3_5 0xF25A0020 -#define F367_OFDM_TSTTSSF3_4 0xF25A0010 -#define F367_OFDM_TSTTSSF3_3 0xF25A0008 -#define F367_OFDM_TSTTSSF3_2 0xF25A0004 -#define F367_OFDM_TSTTSSF3_1 0xF25A0002 -#define F367_OFDM_DISSF_CLKENABLE 0xF25A0001 - - /* TSTTS1 */ -#define R367_OFDM_TSTTS1 0xF25C -#define F367_OFDM_TSTERS 0xF25C0080 -#define F367_OFDM_TSFIFO_DSSSYNCB 0xF25C0040 -#define F367_OFDM_TSTTS_FSPYBEFRS 0xF25C0020 -#define F367_OFDM_NFORCE_SYNCBYTE 0xF25C0010 -#define F367_OFDM_XL_NOFTHRESHOLD 0xF25C0008 -#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 -#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 -#define F367_OFDM_TSTTSEN 0xF25C0001 - - /* TSTTS2 */ -#define R367_OFDM_TSTTS2 0xF25D -#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 -#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 -#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 -#define F367_OFDM_TSTTS_SELECT 0xF25D001F - - /* TSTTS3 */ -#define R367_OFDM_TSTTS3 0xF25E -#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 -#define F367_OFDM_TSTTS_NOPKTENE 0xF25E0040 -#define F367_OFDM_TSTTS_ISOLATION 0xF25E0020 -#define F367_OFDM_TSTTS_DISBUG 0xF25E0010 -#define F367_OFDM_TSTTS_NOBADSTART 0xF25E0008 -#define F367_OFDM_TSTTS_STACKSEL 0xF25E0007 - - /* TSTTS4 */ -#define R367_OFDM_TSTTS4 0xF25F -#define F367_OFDM_TSTTS4_7 0xF25F0080 -#define F367_OFDM_TSTTS4_6 0xF25F0040 -#define F367_OFDM_TSTTS4_5 0xF25F0020 -#define F367_OFDM_TSTTS_DISDSTATE 0xF25F0010 -#define F367_OFDM_TSTTS_FASTNOSYNC 0xF25F0008 -#define F367_OFDM_EXT_FECSPYIN 0xF25F0004 -#define F367_OFDM_TSTTS_NODPZERO 0xF25F0002 -#define F367_OFDM_TSTTS_NODIV3 0xF25F0001 - - /* TSTTSRC */ -#define R367_OFDM_TSTTSRC 0xF26C -#define F367_OFDM_TSTTSRC_7 0xF26C0080 -#define F367_OFDM_TSRCFIFO_DSSSYNCB 0xF26C0040 -#define F367_OFDM_TSRCFIFO_DPUNACTIVE 0xF26C0020 -#define F367_OFDM_TSRCFIFO_DELSPEEDUP 0xF26C0010 -#define F367_OFDM_TSTTSRC_NODIV3 0xF26C0008 -#define F367_OFDM_TSTTSRC_FRFORCEPKT 0xF26C0004 -#define F367_OFDM_SAT25_SDDORIGINE 0xF26C0002 -#define F367_OFDM_TSTTSRC_INACTIVE 0xF26C0001 - - /* TSTTSRS */ -#define R367_OFDM_TSTTSRS 0xF26D -#define F367_OFDM_TSTTSRS_7 0xF26D0080 -#define F367_OFDM_TSTTSRS_6 0xF26D0040 -#define F367_OFDM_TSTTSRS_5 0xF26D0020 -#define F367_OFDM_TSTTSRS_4 0xF26D0010 -#define F367_OFDM_TSTTSRS_3 0xF26D0008 -#define F367_OFDM_TSTTSRS_2 0xF26D0004 -#define F367_OFDM_TSTRS_DISRS2 0xF26D0002 -#define F367_OFDM_TSTRS_DISRS1 0xF26D0001 - -/* TSSTATEM */ -#define R367_OFDM_TSSTATEM 0xF270 -#define F367_OFDM_TSDIL_ON 0xF2700080 -#define F367_OFDM_TSSKIPRS_ON 0xF2700040 -#define F367_OFDM_TSRS_ON 0xF2700020 -#define F367_OFDM_TSDESCRAMB_ON 0xF2700010 -#define F367_OFDM_TSFRAME_MODE 0xF2700008 -#define F367_OFDM_TS_DISABLE 0xF2700004 -#define F367_OFDM_TSACM_MODE 0xF2700002 -#define F367_OFDM_TSOUT_NOSYNC 0xF2700001 - -/* TSSTATEL */ -#define R367_OFDM_TSSTATEL 0xF271 -#define F367_OFDM_TSNOSYNCBYTE 0xF2710080 -#define F367_OFDM_TSPARITY_ON 0xF2710040 -#define F367_OFDM_TSSYNCOUTRS_ON 0xF2710020 -#define F367_OFDM_TSDVBS2_MODE 0xF2710010 -#define F367_OFDM_TSISSYI_ON 0xF2710008 -#define F367_OFDM_TSNPD_ON 0xF2710004 -#define F367_OFDM_TSCRC8_ON 0xF2710002 -#define F367_OFDM_TSDSS_PACKET 0xF2710001 - -/* TSCFGH */ -#define R367_OFDM_TSCFGH 0xF272 -#define F367_OFDM_TSFIFO_DVBCI 0xF2720080 -#define F367_OFDM_TSFIFO_SERIAL 0xF2720040 -#define F367_OFDM_TSFIFO_TEIUPDATE 0xF2720020 -#define F367_OFDM_TSFIFO_DUTY50 0xF2720010 -#define F367_OFDM_TSFIFO_HSGNLOUT 0xF2720008 -#define F367_OFDM_TSFIFO_ERRMODE 0xF2720006 -#define F367_OFDM_RST_HWARE 0xF2720001 - -/* TSCFGM */ -#define R367_OFDM_TSCFGM 0xF273 -#define F367_OFDM_TSFIFO_MANSPEED 0xF27300C0 -#define F367_OFDM_TSFIFO_PERMDATA 0xF2730020 -#define F367_OFDM_TSFIFO_NONEWSGNL 0xF2730010 -#define F367_OFDM_TSFIFO_BITSPEED 0xF2730008 -#define F367_OFDM_NPD_SPECDVBS2 0xF2730004 -#define F367_OFDM_TSFIFO_STOPCKDIS 0xF2730002 -#define F367_OFDM_TSFIFO_INVDATA 0xF2730001 - -/* TSCFGL */ -#define R367_OFDM_TSCFGL 0xF274 -#define F367_OFDM_TSFIFO_BCLKDEL1CK 0xF27400C0 -#define F367_OFDM_BCHERROR_MODE 0xF2740030 -#define F367_OFDM_TSFIFO_NSGNL2DATA 0xF2740008 -#define F367_OFDM_TSFIFO_EMBINDVB 0xF2740004 -#define F367_OFDM_TSFIFO_DPUNACT 0xF2740002 -#define F367_OFDM_TSFIFO_NPDOFF 0xF2740001 - -/* TSSYNC */ -#define R367_OFDM_TSSYNC 0xF275 -#define F367_OFDM_TSFIFO_PERMUTE 0xF2750080 -#define F367_OFDM_TSFIFO_FISCR3B 0xF2750060 -#define F367_OFDM_TSFIFO_SYNCMODE 0xF2750018 -#define F367_OFDM_TSFIFO_SYNCSEL 0xF2750007 - -/* TSINSDELH */ -#define R367_OFDM_TSINSDELH 0xF276 -#define F367_OFDM_TSDEL_SYNCBYTE 0xF2760080 -#define F367_OFDM_TSDEL_XXHEADER 0xF2760040 -#define F367_OFDM_TSDEL_BBHEADER 0xF2760020 -#define F367_OFDM_TSDEL_DATAFIELD 0xF2760010 -#define F367_OFDM_TSINSDEL_ISCR 0xF2760008 -#define F367_OFDM_TSINSDEL_NPD 0xF2760004 -#define F367_OFDM_TSINSDEL_RSPARITY 0xF2760002 -#define F367_OFDM_TSINSDEL_CRC8 0xF2760001 - -/* TSINSDELM */ -#define R367_OFDM_TSINSDELM 0xF277 -#define F367_OFDM_TSINS_BBPADDING 0xF2770080 -#define F367_OFDM_TSINS_BCHFEC 0xF2770040 -#define F367_OFDM_TSINS_LDPCFEC 0xF2770020 -#define F367_OFDM_TSINS_EMODCOD 0xF2770010 -#define F367_OFDM_TSINS_TOKEN 0xF2770008 -#define F367_OFDM_TSINS_XXXERR 0xF2770004 -#define F367_OFDM_TSINS_MATYPE 0xF2770002 -#define F367_OFDM_TSINS_UPL 0xF2770001 - -/* TSINSDELL */ -#define R367_OFDM_TSINSDELL 0xF278 -#define F367_OFDM_TSINS_DFL 0xF2780080 -#define F367_OFDM_TSINS_SYNCD 0xF2780040 -#define F367_OFDM_TSINS_BLOCLEN 0xF2780020 -#define F367_OFDM_TSINS_SIGPCOUNT 0xF2780010 -#define F367_OFDM_TSINS_FIFO 0xF2780008 -#define F367_OFDM_TSINS_REALPACK 0xF2780004 -#define F367_OFDM_TSINS_TSCONFIG 0xF2780002 -#define F367_OFDM_TSINS_LATENCY 0xF2780001 - -/* TSDIVN */ -#define R367_OFDM_TSDIVN 0xF279 -#define F367_OFDM_TSFIFO_LOWSPEED 0xF2790080 -#define F367_OFDM_BYTE_OVERSAMPLING 0xF2790070 -#define F367_OFDM_TSMANUAL_PACKETNBR 0xF279000F - -/* TSDIVPM */ -#define R367_OFDM_TSDIVPM 0xF27A -#define F367_OFDM_TSMANUAL_P_HI 0xF27A00FF - -/* TSDIVPL */ -#define R367_OFDM_TSDIVPL 0xF27B -#define F367_OFDM_TSMANUAL_P_LO 0xF27B00FF - -/* TSDIVQM */ -#define R367_OFDM_TSDIVQM 0xF27C -#define F367_OFDM_TSMANUAL_Q_HI 0xF27C00FF - -/* TSDIVQL */ -#define R367_OFDM_TSDIVQL 0xF27D -#define F367_OFDM_TSMANUAL_Q_LO 0xF27D00FF - -/* TSDILSTKM */ -#define R367_OFDM_TSDILSTKM 0xF27E -#define F367_OFDM_TSFIFO_DILSTK_HI 0xF27E00FF - -/* TSDILSTKL */ -#define R367_OFDM_TSDILSTKL 0xF27F -#define F367_OFDM_TSFIFO_DILSTK_LO 0xF27F00FF - -/* TSSPEED */ -#define R367_OFDM_TSSPEED 0xF280 -#define F367_OFDM_TSFIFO_OUTSPEED 0xF28000FF - -/* TSSTATUS */ -#define R367_OFDM_TSSTATUS 0xF281 -#define F367_OFDM_TSFIFO_LINEOK 0xF2810080 -#define F367_OFDM_TSFIFO_ERROR 0xF2810040 -#define F367_OFDM_TSFIFO_DATA7 0xF2810020 -#define F367_OFDM_TSFIFO_NOSYNC 0xF2810010 -#define F367_OFDM_ISCR_INITIALIZED 0xF2810008 -#define F367_OFDM_ISCR_UPDATED 0xF2810004 -#define F367_OFDM_SOFFIFO_UNREGUL 0xF2810002 -#define F367_OFDM_DIL_READY 0xF2810001 - -/* TSSTATUS2 */ -#define R367_OFDM_TSSTATUS2 0xF282 -#define F367_OFDM_TSFIFO_DEMODSEL 0xF2820080 -#define F367_OFDM_TSFIFOSPEED_STORE 0xF2820040 -#define F367_OFDM_DILXX_RESET 0xF2820020 -#define F367_OFDM_TSSERIAL_IMPOSSIBLE 0xF2820010 -#define F367_OFDM_TSFIFO_UNDERSPEED 0xF2820008 -#define F367_OFDM_BITSPEED_EVENT 0xF2820004 -#define F367_OFDM_UL_SCRAMBDETECT 0xF2820002 -#define F367_OFDM_ULDTV67_FALSELOCK 0xF2820001 - -/* TSBITRATEM */ -#define R367_OFDM_TSBITRATEM 0xF283 -#define F367_OFDM_TSFIFO_BITRATE_HI 0xF28300FF - -/* TSBITRATEL */ -#define R367_OFDM_TSBITRATEL 0xF284 -#define F367_OFDM_TSFIFO_BITRATE_LO 0xF28400FF - -/* TSPACKLENM */ -#define R367_OFDM_TSPACKLENM 0xF285 -#define F367_OFDM_TSFIFO_PACKCPT 0xF28500E0 -#define F367_OFDM_DIL_RPLEN_HI 0xF285001F - -/* TSPACKLENL */ -#define R367_OFDM_TSPACKLENL 0xF286 -#define F367_OFDM_DIL_RPLEN_LO 0xF28600FF - -/* TSBLOCLENM */ -#define R367_OFDM_TSBLOCLENM 0xF287 -#define F367_OFDM_TSFIFO_PFLEN_HI 0xF28700FF - -/* TSBLOCLENL */ -#define R367_OFDM_TSBLOCLENL 0xF288 -#define F367_OFDM_TSFIFO_PFLEN_LO 0xF28800FF - -/* TSDLYH */ -#define R367_OFDM_TSDLYH 0xF289 -#define F367_OFDM_SOFFIFO_TSTIMEVALID 0xF2890080 -#define F367_OFDM_SOFFIFO_SPEEDUP 0xF2890040 -#define F367_OFDM_SOFFIFO_STOP 0xF2890020 -#define F367_OFDM_SOFFIFO_REGULATED 0xF2890010 -#define F367_OFDM_SOFFIFO_REALSBOFF_HI 0xF289000F - -/* TSDLYM */ -#define R367_OFDM_TSDLYM 0xF28A -#define F367_OFDM_SOFFIFO_REALSBOFF_MED 0xF28A00FF - -/* TSDLYL */ -#define R367_OFDM_TSDLYL 0xF28B -#define F367_OFDM_SOFFIFO_REALSBOFF_LO 0xF28B00FF - -/* TSNPDAV */ -#define R367_OFDM_TSNPDAV 0xF28C -#define F367_OFDM_TSNPD_AVERAGE 0xF28C00FF - -/* TSBUFSTATH */ -#define R367_OFDM_TSBUFSTATH 0xF28D -#define F367_OFDM_TSISCR_3BYTES 0xF28D0080 -#define F367_OFDM_TSISCR_NEWDATA 0xF28D0040 -#define F367_OFDM_TSISCR_BUFSTAT_HI 0xF28D003F - -/* TSBUFSTATM */ -#define R367_OFDM_TSBUFSTATM 0xF28E -#define F367_OFDM_TSISCR_BUFSTAT_MED 0xF28E00FF - -/* TSBUFSTATL */ -#define R367_OFDM_TSBUFSTATL 0xF28F -#define F367_OFDM_TSISCR_BUFSTAT_LO 0xF28F00FF - -/* TSDEBUGM */ -#define R367_OFDM_TSDEBUGM 0xF290 -#define F367_OFDM_TSFIFO_ILLPACKET 0xF2900080 -#define F367_OFDM_DIL_NOSYNC 0xF2900040 -#define F367_OFDM_DIL_ISCR 0xF2900020 -#define F367_OFDM_DILOUT_BSYNCB 0xF2900010 -#define F367_OFDM_TSFIFO_EMPTYPKT 0xF2900008 -#define F367_OFDM_TSFIFO_EMPTYRD 0xF2900004 -#define F367_OFDM_SOFFIFO_STOPM 0xF2900002 -#define F367_OFDM_SOFFIFO_SPEEDUPM 0xF2900001 - -/* TSDEBUGL */ -#define R367_OFDM_TSDEBUGL 0xF291 -#define F367_OFDM_TSFIFO_PACKLENFAIL 0xF2910080 -#define F367_OFDM_TSFIFO_SYNCBFAIL 0xF2910040 -#define F367_OFDM_TSFIFO_VITLIBRE 0xF2910020 -#define F367_OFDM_TSFIFO_BOOSTSPEEDM 0xF2910010 -#define F367_OFDM_TSFIFO_UNDERSPEEDM 0xF2910008 -#define F367_OFDM_TSFIFO_ERROR_EVNT 0xF2910004 -#define F367_OFDM_TSFIFO_FULL 0xF2910002 -#define F367_OFDM_TSFIFO_OVERFLOWM 0xF2910001 - -/* TSDLYSETH */ -#define R367_OFDM_TSDLYSETH 0xF292 -#define F367_OFDM_SOFFIFO_OFFSET 0xF29200E0 -#define F367_OFDM_SOFFIFO_SYMBOFFSET_HI 0xF292001F - -/* TSDLYSETM */ -#define R367_OFDM_TSDLYSETM 0xF293 -#define F367_OFDM_SOFFIFO_SYMBOFFSET_MED 0xF29300FF - -/* TSDLYSETL */ -#define R367_OFDM_TSDLYSETL 0xF294 -#define F367_OFDM_SOFFIFO_SYMBOFFSET_LO 0xF29400FF - -/* TSOBSCFG */ -#define R367_OFDM_TSOBSCFG 0xF295 -#define F367_OFDM_TSFIFO_OBSCFG 0xF29500FF - -/* TSOBSM */ -#define R367_OFDM_TSOBSM 0xF296 -#define F367_OFDM_TSFIFO_OBSDATA_HI 0xF29600FF - -/* TSOBSL */ -#define R367_OFDM_TSOBSL 0xF297 -#define F367_OFDM_TSFIFO_OBSDATA_LO 0xF29700FF - -/* ERRCTRL1 */ -#define R367_OFDM_ERRCTRL1 0xF298 -#define F367_OFDM_ERR_SRC1 0xF29800F0 -#define F367_OFDM_ERRCTRL1_3 0xF2980008 -#define F367_OFDM_NUM_EVT1 0xF2980007 - -/* ERRCNT1H */ -#define R367_OFDM_ERRCNT1H 0xF299 -#define F367_OFDM_ERRCNT1_OLDVALUE 0xF2990080 -#define F367_OFDM_ERR_CNT1 0xF299007F - -/* ERRCNT1M */ -#define R367_OFDM_ERRCNT1M 0xF29A -#define F367_OFDM_ERR_CNT1_HI 0xF29A00FF - -/* ERRCNT1L */ -#define R367_OFDM_ERRCNT1L 0xF29B -#define F367_OFDM_ERR_CNT1_LO 0xF29B00FF - -/* ERRCTRL2 */ -#define R367_OFDM_ERRCTRL2 0xF29C -#define F367_OFDM_ERR_SRC2 0xF29C00F0 -#define F367_OFDM_ERRCTRL2_3 0xF29C0008 -#define F367_OFDM_NUM_EVT2 0xF29C0007 - -/* ERRCNT2H */ -#define R367_OFDM_ERRCNT2H 0xF29D -#define F367_OFDM_ERRCNT2_OLDVALUE 0xF29D0080 -#define F367_OFDM_ERR_CNT2_HI 0xF29D007F - -/* ERRCNT2M */ -#define R367_OFDM_ERRCNT2M 0xF29E -#define F367_OFDM_ERR_CNT2_MED 0xF29E00FF - -/* ERRCNT2L */ -#define R367_OFDM_ERRCNT2L 0xF29F -#define F367_OFDM_ERR_CNT2_LO 0xF29F00FF - -/* FECSPY */ -#define R367_OFDM_FECSPY 0xF2A0 -#define F367_OFDM_SPY_ENABLE 0xF2A00080 -#define F367_OFDM_NO_SYNCBYTE 0xF2A00040 -#define F367_OFDM_SERIAL_MODE 0xF2A00020 -#define F367_OFDM_UNUSUAL_PACKET 0xF2A00010 -#define F367_OFDM_BERMETER_DATAMODE 0xF2A0000C -#define F367_OFDM_BERMETER_LMODE 0xF2A00002 -#define F367_OFDM_BERMETER_RESET 0xF2A00001 - -/* FSPYCFG */ -#define R367_OFDM_FSPYCFG 0xF2A1 -#define F367_OFDM_FECSPY_INPUT 0xF2A100C0 -#define F367_OFDM_RST_ON_ERROR 0xF2A10020 -#define F367_OFDM_ONE_SHOT 0xF2A10010 -#define F367_OFDM_I2C_MOD 0xF2A1000C -#define F367_OFDM_SPY_HYSTERESIS 0xF2A10003 - -/* FSPYDATA */ -#define R367_OFDM_FSPYDATA 0xF2A2 -#define F367_OFDM_SPY_STUFFING 0xF2A20080 -#define F367_OFDM_NOERROR_PKTJITTER 0xF2A20040 -#define F367_OFDM_SPY_CNULLPKT 0xF2A20020 -#define F367_OFDM_SPY_OUTDATA_MODE 0xF2A2001F - -/* FSPYOUT */ -#define R367_OFDM_FSPYOUT 0xF2A3 -#define F367_OFDM_FSPY_DIRECT 0xF2A30080 -#define F367_OFDM_FSPYOUT_6 0xF2A30040 -#define F367_OFDM_SPY_OUTDATA_BUS 0xF2A30038 -#define F367_OFDM_STUFF_MODE 0xF2A30007 - -/* FSTATUS */ -#define R367_OFDM_FSTATUS 0xF2A4 -#define F367_OFDM_SPY_ENDSIM 0xF2A40080 -#define F367_OFDM_VALID_SIM 0xF2A40040 -#define F367_OFDM_FOUND_SIGNAL 0xF2A40020 -#define F367_OFDM_DSS_SYNCBYTE 0xF2A40010 -#define F367_OFDM_RESULT_STATE 0xF2A4000F - -/* FGOODPACK */ -#define R367_OFDM_FGOODPACK 0xF2A5 -#define F367_OFDM_FGOOD_PACKET 0xF2A500FF - -/* FPACKCNT */ -#define R367_OFDM_FPACKCNT 0xF2A6 -#define F367_OFDM_FPACKET_COUNTER 0xF2A600FF - -/* FSPYMISC */ -#define R367_OFDM_FSPYMISC 0xF2A7 -#define F367_OFDM_FLABEL_COUNTER 0xF2A700FF - -/* FBERCPT4 */ -#define R367_OFDM_FBERCPT4 0xF2A8 -#define F367_OFDM_FBERMETER_CPT5 0xF2A800FF - -/* FBERCPT3 */ -#define R367_OFDM_FBERCPT3 0xF2A9 -#define F367_OFDM_FBERMETER_CPT4 0xF2A900FF - -/* FBERCPT2 */ -#define R367_OFDM_FBERCPT2 0xF2AA -#define F367_OFDM_FBERMETER_CPT3 0xF2AA00FF - -/* FBERCPT1 */ -#define R367_OFDM_FBERCPT1 0xF2AB -#define F367_OFDM_FBERMETER_CPT2 0xF2AB00FF - -/* FBERCPT0 */ -#define R367_OFDM_FBERCPT0 0xF2AC -#define F367_OFDM_FBERMETER_CPT1 0xF2AC00FF - -/* FBERERR2 */ -#define R367_OFDM_FBERERR2 0xF2AD -#define F367_OFDM_FBERMETER_ERR_HI 0xF2AD00FF - -/* FBERERR1 */ -#define R367_OFDM_FBERERR1 0xF2AE -#define F367_OFDM_FBERMETER_ERR_MED 0xF2AE00FF - -/* FBERERR0 */ -#define R367_OFDM_FBERERR0 0xF2AF -#define F367_OFDM_FBERMETER_ERR_LO 0xF2AF00FF - -/* FSTATESM */ -#define R367_OFDM_FSTATESM 0xF2B0 -#define F367_OFDM_RSTATE_F 0xF2B00080 -#define F367_OFDM_RSTATE_E 0xF2B00040 -#define F367_OFDM_RSTATE_D 0xF2B00020 -#define F367_OFDM_RSTATE_C 0xF2B00010 -#define F367_OFDM_RSTATE_B 0xF2B00008 -#define F367_OFDM_RSTATE_A 0xF2B00004 -#define F367_OFDM_RSTATE_9 0xF2B00002 -#define F367_OFDM_RSTATE_8 0xF2B00001 - -/* FSTATESL */ -#define R367_OFDM_FSTATESL 0xF2B1 -#define F367_OFDM_RSTATE_7 0xF2B10080 -#define F367_OFDM_RSTATE_6 0xF2B10040 -#define F367_OFDM_RSTATE_5 0xF2B10020 -#define F367_OFDM_RSTATE_4 0xF2B10010 -#define F367_OFDM_RSTATE_3 0xF2B10008 -#define F367_OFDM_RSTATE_2 0xF2B10004 -#define F367_OFDM_RSTATE_1 0xF2B10002 -#define F367_OFDM_RSTATE_0 0xF2B10001 - -/* FSPYBER */ -#define R367_OFDM_FSPYBER 0xF2B2 -#define F367_OFDM_FSPYBER_7 0xF2B20080 -#define F367_OFDM_FSPYOBS_XORREAD 0xF2B20040 -#define F367_OFDM_FSPYBER_OBSMODE 0xF2B20020 -#define F367_OFDM_FSPYBER_SYNCBYTE 0xF2B20010 -#define F367_OFDM_FSPYBER_UNSYNC 0xF2B20008 -#define F367_OFDM_FSPYBER_CTIME 0xF2B20007 - -/* FSPYDISTM */ -#define R367_OFDM_FSPYDISTM 0xF2B3 -#define F367_OFDM_PKTTIME_DISTANCE_HI 0xF2B300FF - -/* FSPYDISTL */ -#define R367_OFDM_FSPYDISTL 0xF2B4 -#define F367_OFDM_PKTTIME_DISTANCE_LO 0xF2B400FF - -/* FSPYOBS7 */ -#define R367_OFDM_FSPYOBS7 0xF2B8 -#define F367_OFDM_FSPYOBS_SPYFAIL 0xF2B80080 -#define F367_OFDM_FSPYOBS_SPYFAIL1 0xF2B80040 -#define F367_OFDM_FSPYOBS_ERROR 0xF2B80020 -#define F367_OFDM_FSPYOBS_STROUT 0xF2B80010 -#define F367_OFDM_FSPYOBS_RESULTSTATE1 0xF2B8000F - -/* FSPYOBS6 */ -#define R367_OFDM_FSPYOBS6 0xF2B9 -#define F367_OFDM_FSPYOBS_RESULTSTATE0 0xF2B900F0 -#define F367_OFDM_FSPYOBS_RESULTSTATEM1 0xF2B9000F - -/* FSPYOBS5 */ -#define R367_OFDM_FSPYOBS5 0xF2BA -#define F367_OFDM_FSPYOBS_BYTEOFPACKET1 0xF2BA00FF - -/* FSPYOBS4 */ -#define R367_OFDM_FSPYOBS4 0xF2BB -#define F367_OFDM_FSPYOBS_BYTEVALUE1 0xF2BB00FF - -/* FSPYOBS3 */ -#define R367_OFDM_FSPYOBS3 0xF2BC -#define F367_OFDM_FSPYOBS_DATA1 0xF2BC00FF - -/* FSPYOBS2 */ -#define R367_OFDM_FSPYOBS2 0xF2BD -#define F367_OFDM_FSPYOBS_DATA0 0xF2BD00FF - -/* FSPYOBS1 */ -#define R367_OFDM_FSPYOBS1 0xF2BE -#define F367_OFDM_FSPYOBS_DATAM1 0xF2BE00FF - -/* FSPYOBS0 */ -#define R367_OFDM_FSPYOBS0 0xF2BF -#define F367_OFDM_FSPYOBS_DATAM2 0xF2BF00FF - -/* SFDEMAP */ -#define R367_OFDM_SFDEMAP 0xF2C0 -#define F367_OFDM_SFDEMAP_7 0xF2C00080 -#define F367_OFDM_SFEC_K_DIVIDER_VIT 0xF2C0007F - -/* SFERROR */ -#define R367_OFDM_SFERROR 0xF2C1 -#define F367_OFDM_SFEC_REGERR_VIT 0xF2C100FF - -/* SFAVSR */ -#define R367_OFDM_SFAVSR 0xF2C2 -#define F367_OFDM_SFEC_SUMERRORS 0xF2C20080 -#define F367_OFDM_SERROR_MAXMODE 0xF2C20040 -#define F367_OFDM_SN_SFEC 0xF2C20030 -#define F367_OFDM_KDIV_MODE_SFEC 0xF2C2000C -#define F367_OFDM_SFAVSR_1 0xF2C20002 -#define F367_OFDM_SFAVSR_0 0xF2C20001 - -/* SFECSTATUS */ -#define R367_OFDM_SFECSTATUS 0xF2C3 -#define F367_OFDM_SFEC_ON 0xF2C30080 -#define F367_OFDM_SFSTATUS_6 0xF2C30040 -#define F367_OFDM_SFSTATUS_5 0xF2C30020 -#define F367_OFDM_SFSTATUS_4 0xF2C30010 -#define F367_OFDM_LOCKEDSFEC 0xF2C30008 -#define F367_OFDM_SFEC_DELOCK 0xF2C30004 -#define F367_OFDM_SFEC_DEMODSEL1 0xF2C30002 -#define F367_OFDM_SFEC_OVFON 0xF2C30001 - -/* SFKDIV12 */ -#define R367_OFDM_SFKDIV12 0xF2C4 -#define F367_OFDM_SFECKDIV12_MAN 0xF2C40080 -#define F367_OFDM_SFEC_K_DIVIDER_12 0xF2C4007F - -/* SFKDIV23 */ -#define R367_OFDM_SFKDIV23 0xF2C5 -#define F367_OFDM_SFECKDIV23_MAN 0xF2C50080 -#define F367_OFDM_SFEC_K_DIVIDER_23 0xF2C5007F - -/* SFKDIV34 */ -#define R367_OFDM_SFKDIV34 0xF2C6 -#define F367_OFDM_SFECKDIV34_MAN 0xF2C60080 -#define F367_OFDM_SFEC_K_DIVIDER_34 0xF2C6007F - -/* SFKDIV56 */ -#define R367_OFDM_SFKDIV56 0xF2C7 -#define F367_OFDM_SFECKDIV56_MAN 0xF2C70080 -#define F367_OFDM_SFEC_K_DIVIDER_56 0xF2C7007F - -/* SFKDIV67 */ -#define R367_OFDM_SFKDIV67 0xF2C8 -#define F367_OFDM_SFECKDIV67_MAN 0xF2C80080 -#define F367_OFDM_SFEC_K_DIVIDER_67 0xF2C8007F - -/* SFKDIV78 */ -#define R367_OFDM_SFKDIV78 0xF2C9 -#define F367_OFDM_SFECKDIV78_MAN 0xF2C90080 -#define F367_OFDM_SFEC_K_DIVIDER_78 0xF2C9007F - -/* SFDILSTKM */ -#define R367_OFDM_SFDILSTKM 0xF2CA -#define F367_OFDM_SFEC_PACKCPT 0xF2CA00E0 -#define F367_OFDM_SFEC_DILSTK_HI 0xF2CA001F - -/* SFDILSTKL */ -#define R367_OFDM_SFDILSTKL 0xF2CB -#define F367_OFDM_SFEC_DILSTK_LO 0xF2CB00FF - -/* SFSTATUS */ -#define R367_OFDM_SFSTATUS 0xF2CC -#define F367_OFDM_SFEC_LINEOK 0xF2CC0080 -#define F367_OFDM_SFEC_ERROR 0xF2CC0040 -#define F367_OFDM_SFEC_DATA7 0xF2CC0020 -#define F367_OFDM_SFEC_OVERFLOW 0xF2CC0010 -#define F367_OFDM_SFEC_DEMODSEL2 0xF2CC0008 -#define F367_OFDM_SFEC_NOSYNC 0xF2CC0004 -#define F367_OFDM_SFEC_UNREGULA 0xF2CC0002 -#define F367_OFDM_SFEC_READY 0xF2CC0001 - -/* SFDLYH */ -#define R367_OFDM_SFDLYH 0xF2CD -#define F367_OFDM_SFEC_TSTIMEVALID 0xF2CD0080 -#define F367_OFDM_SFEC_SPEEDUP 0xF2CD0040 -#define F367_OFDM_SFEC_STOP 0xF2CD0020 -#define F367_OFDM_SFEC_REGULATED 0xF2CD0010 -#define F367_OFDM_SFEC_REALSYMBOFFSET 0xF2CD000F - -/* SFDLYM */ -#define R367_OFDM_SFDLYM 0xF2CE -#define F367_OFDM_SFEC_REALSYMBOFFSET_HI 0xF2CE00FF - -/* SFDLYL */ -#define R367_OFDM_SFDLYL 0xF2CF -#define F367_OFDM_SFEC_REALSYMBOFFSET_LO 0xF2CF00FF - -/* SFDLYSETH */ -#define R367_OFDM_SFDLYSETH 0xF2D0 -#define F367_OFDM_SFEC_OFFSET 0xF2D000E0 -#define F367_OFDM_SFECDLYSETH_4 0xF2D00010 -#define F367_OFDM_RST_SFEC 0xF2D00008 -#define F367_OFDM_SFECDLYSETH_2 0xF2D00004 -#define F367_OFDM_SFEC_DISABLE 0xF2D00002 -#define F367_OFDM_SFEC_UNREGUL 0xF2D00001 - -/* SFDLYSETM */ -#define R367_OFDM_SFDLYSETM 0xF2D1 -#define F367_OFDM_SFECDLYSETM_7 0xF2D10080 -#define F367_OFDM_SFEC_SYMBOFFSET_HI 0xF2D1007F - -/* SFDLYSETL */ -#define R367_OFDM_SFDLYSETL 0xF2D2 -#define F367_OFDM_SFEC_SYMBOFFSET_LO 0xF2D200FF - -/* SFOBSCFG */ -#define R367_OFDM_SFOBSCFG 0xF2D3 -#define F367_OFDM_SFEC_OBSCFG 0xF2D300FF - -/* SFOBSM */ -#define R367_OFDM_SFOBSM 0xF2D4 -#define F367_OFDM_SFEC_OBSDATA_HI 0xF2D400FF - -/* SFOBSL */ -#define R367_OFDM_SFOBSL 0xF2D5 -#define F367_OFDM_SFEC_OBSDATA_LO 0xF2D500FF - -/* SFECINFO */ -#define R367_OFDM_SFECINFO 0xF2D6 -#define F367_OFDM_SFECINFO_7 0xF2D60080 -#define F367_OFDM_SFEC_SYNCDLSB 0xF2D60070 -#define F367_OFDM_SFCE_S1CPHASE 0xF2D6000F - -/* SFERRCTRL */ -#define R367_OFDM_SFERRCTRL 0xF2D8 -#define F367_OFDM_SFEC_ERR_SOURCE 0xF2D800F0 -#define F367_OFDM_SFERRCTRL_3 0xF2D80008 -#define F367_OFDM_SFEC_NUM_EVENT 0xF2D80007 - -/* SFERRCNTH */ -#define R367_OFDM_SFERRCNTH 0xF2D9 -#define F367_OFDM_SFERRC_OLDVALUE 0xF2D90080 -#define F367_OFDM_SFEC_ERR_CNT 0xF2D9007F - -/* SFERRCNTM */ -#define R367_OFDM_SFERRCNTM 0xF2DA -#define F367_OFDM_SFEC_ERR_CNT_HI 0xF2DA00FF - -/* SFERRCNTL */ -#define R367_OFDM_SFERRCNTL 0xF2DB -#define F367_OFDM_SFEC_ERR_CNT_LO 0xF2DB00FF - -/* SYMBRATEM */ -#define R367_OFDM_SYMBRATEM 0xF2E0 -#define F367_OFDM_DEFGEN_SYMBRATE_HI 0xF2E000FF - -/* SYMBRATEL */ -#define R367_OFDM_SYMBRATEL 0xF2E1 -#define F367_OFDM_DEFGEN_SYMBRATE_LO 0xF2E100FF - -/* SYMBSTATUS */ -#define R367_OFDM_SYMBSTATUS 0xF2E2 -#define F367_OFDM_SYMBDLINE2_OFF 0xF2E20080 -#define F367_OFDM_SDDL_REINIT1 0xF2E20040 -#define F367_OFDM_SDD_REINIT1 0xF2E20020 -#define F367_OFDM_TOKENID_ERROR 0xF2E20010 -#define F367_OFDM_SYMBRATE_OVERFLOW 0xF2E20008 -#define F367_OFDM_SYMBRATE_UNDERFLOW 0xF2E20004 -#define F367_OFDM_TOKENID_RSTEVENT 0xF2E20002 -#define F367_OFDM_TOKENID_RESET1 0xF2E20001 - -/* SYMBCFG */ -#define R367_OFDM_SYMBCFG 0xF2E3 -#define F367_OFDM_SYMBCFG_7 0xF2E30080 -#define F367_OFDM_SYMBCFG_6 0xF2E30040 -#define F367_OFDM_SYMBCFG_5 0xF2E30020 -#define F367_OFDM_SYMBCFG_4 0xF2E30010 -#define F367_OFDM_SYMRATE_FSPEED 0xF2E3000C -#define F367_OFDM_SYMRATE_SSPEED 0xF2E30003 - -/* SYMBFIFOM */ -#define R367_OFDM_SYMBFIFOM 0xF2E4 -#define F367_OFDM_SYMBFIFOM_7 0xF2E40080 -#define F367_OFDM_SYMBFIFOM_6 0xF2E40040 -#define F367_OFDM_DEFGEN_SYMFIFO_HI 0xF2E4003F - -/* SYMBFIFOL */ -#define R367_OFDM_SYMBFIFOL 0xF2E5 -#define F367_OFDM_DEFGEN_SYMFIFO_LO 0xF2E500FF - -/* SYMBOFFSM */ -#define R367_OFDM_SYMBOFFSM 0xF2E6 -#define F367_OFDM_TOKENID_RESET2 0xF2E60080 -#define F367_OFDM_SDDL_REINIT2 0xF2E60040 -#define F367_OFDM_SDD_REINIT2 0xF2E60020 -#define F367_OFDM_SYMBOFFSM_4 0xF2E60010 -#define F367_OFDM_SYMBOFFSM_3 0xF2E60008 -#define F367_OFDM_DEFGEN_SYMBOFFSET_HI 0xF2E60007 - -/* SYMBOFFSL */ -#define R367_OFDM_SYMBOFFSL 0xF2E7 -#define F367_OFDM_DEFGEN_SYMBOFFSET_LO 0xF2E700FF - -/* DEBUG_LT4 */ -#define R367_DEBUG_LT4 0xF400 -#define F367_F_DEBUG_LT4 0xF40000FF - -/* DEBUG_LT5 */ -#define R367_DEBUG_LT5 0xF401 -#define F367_F_DEBUG_LT5 0xF40100FF - -/* DEBUG_LT6 */ -#define R367_DEBUG_LT6 0xF402 -#define F367_F_DEBUG_LT6 0xF40200FF - -/* DEBUG_LT7 */ -#define R367_DEBUG_LT7 0xF403 -#define F367_F_DEBUG_LT7 0xF40300FF - -/* DEBUG_LT8 */ -#define R367_DEBUG_LT8 0xF404 -#define F367_F_DEBUG_LT8 0xF40400FF - -/* DEBUG_LT9 */ -#define R367_DEBUG_LT9 0xF405 -#define F367_F_DEBUG_LT9 0xF40500FF - -/* CTRL_1 */ -#define R367_QAM_CTRL_1 0xF402 -#define F367_QAM_SOFT_RST 0xF4020080 -#define F367_QAM_EQU_RST 0xF4020008 -#define F367_QAM_CRL_RST 0xF4020004 -#define F367_QAM_TRL_RST 0xF4020002 -#define F367_QAM_AGC_RST 0xF4020001 - -/* CTRL_2 */ -#define R367_QAM_CTRL_2 0xF403 -#define F367_QAM_DEINT_RST 0xF4030008 -#define F367_QAM_RS_RST 0xF4030004 - -/* IT_STATUS1 */ -#define R367_QAM_IT_STATUS1 0xF408 -#define F367_QAM_SWEEP_OUT 0xF4080080 -#define F367_QAM_FSM_CRL 0xF4080040 -#define F367_QAM_CRL_LOCK 0xF4080020 -#define F367_QAM_MFSM 0xF4080010 -#define F367_QAM_TRL_LOCK 0xF4080008 -#define F367_QAM_TRL_AGC_LIMIT 0xF4080004 -#define F367_QAM_ADJ_AGC_LOCK 0xF4080002 -#define F367_QAM_AGC_QAM_LOCK 0xF4080001 - -/* IT_STATUS2 */ -#define R367_QAM_IT_STATUS2 0xF409 -#define F367_QAM_TSMF_CNT 0xF4090080 -#define F367_QAM_TSMF_EOF 0xF4090040 -#define F367_QAM_TSMF_RDY 0xF4090020 -#define F367_QAM_FEC_NOCORR 0xF4090010 -#define F367_QAM_SYNCSTATE 0xF4090008 -#define F367_QAM_DEINT_LOCK 0xF4090004 -#define F367_QAM_FADDING_FRZ 0xF4090002 -#define F367_QAM_TAPMON_ALARM 0xF4090001 - -/* IT_EN1 */ -#define R367_QAM_IT_EN1 0xF40A -#define F367_QAM_SWEEP_OUTE 0xF40A0080 -#define F367_QAM_FSM_CRLE 0xF40A0040 -#define F367_QAM_CRL_LOCKE 0xF40A0020 -#define F367_QAM_MFSME 0xF40A0010 -#define F367_QAM_TRL_LOCKE 0xF40A0008 -#define F367_QAM_TRL_AGC_LIMITE 0xF40A0004 -#define F367_QAM_ADJ_AGC_LOCKE 0xF40A0002 -#define F367_QAM_AGC_LOCKE 0xF40A0001 - -/* IT_EN2 */ -#define R367_QAM_IT_EN2 0xF40B -#define F367_QAM_TSMF_CNTE 0xF40B0080 -#define F367_QAM_TSMF_EOFE 0xF40B0040 -#define F367_QAM_TSMF_RDYE 0xF40B0020 -#define F367_QAM_FEC_NOCORRE 0xF40B0010 -#define F367_QAM_SYNCSTATEE 0xF40B0008 -#define F367_QAM_DEINT_LOCKE 0xF40B0004 -#define F367_QAM_FADDING_FRZE 0xF40B0002 -#define F367_QAM_TAPMON_ALARME 0xF40B0001 - -/* CTRL_STATUS */ -#define R367_QAM_CTRL_STATUS 0xF40C -#define F367_QAM_QAMFEC_LOCK 0xF40C0004 -#define F367_QAM_TSMF_LOCK 0xF40C0002 -#define F367_QAM_TSMF_ERROR 0xF40C0001 - -/* TEST_CTL */ -#define R367_QAM_TEST_CTL 0xF40F -#define F367_QAM_TST_BLK_SEL 0xF40F0060 -#define F367_QAM_TST_BUS_SEL 0xF40F001F - -/* AGC_CTL */ -#define R367_QAM_AGC_CTL 0xF410 -#define F367_QAM_AGC_LCK_TH 0xF41000F0 -#define F367_QAM_AGC_ACCUMRSTSEL 0xF4100007 - -/* AGC_IF_CFG */ -#define R367_QAM_AGC_IF_CFG 0xF411 -#define F367_QAM_AGC_IF_BWSEL 0xF41100F0 -#define F367_QAM_AGC_IF_FREEZE 0xF4110002 - -/* AGC_RF_CFG */ -#define R367_QAM_AGC_RF_CFG 0xF412 -#define F367_QAM_AGC_RF_BWSEL 0xF4120070 -#define F367_QAM_AGC_RF_FREEZE 0xF4120002 - -/* AGC_PWM_CFG */ -#define R367_QAM_AGC_PWM_CFG 0xF413 -#define F367_QAM_AGC_RF_PWM_TST 0xF4130080 -#define F367_QAM_AGC_RF_PWM_INV 0xF4130040 -#define F367_QAM_AGC_IF_PWM_TST 0xF4130008 -#define F367_QAM_AGC_IF_PWM_INV 0xF4130004 -#define F367_QAM_AGC_PWM_CLKDIV 0xF4130003 - -/* AGC_PWR_REF_L */ -#define R367_QAM_AGC_PWR_REF_L 0xF414 -#define F367_QAM_AGC_PWRREF_LO 0xF41400FF - -/* AGC_PWR_REF_H */ -#define R367_QAM_AGC_PWR_REF_H 0xF415 -#define F367_QAM_AGC_PWRREF_HI 0xF4150003 - -/* AGC_RF_TH_L */ -#define R367_QAM_AGC_RF_TH_L 0xF416 -#define F367_QAM_AGC_RF_TH_LO 0xF41600FF - -/* AGC_RF_TH_H */ -#define R367_QAM_AGC_RF_TH_H 0xF417 -#define F367_QAM_AGC_RF_TH_HI 0xF417000F - -/* AGC_IF_LTH_L */ -#define R367_QAM_AGC_IF_LTH_L 0xF418 -#define F367_QAM_AGC_IF_THLO_LO 0xF41800FF - -/* AGC_IF_LTH_H */ -#define R367_QAM_AGC_IF_LTH_H 0xF419 -#define F367_QAM_AGC_IF_THLO_HI 0xF419000F - -/* AGC_IF_HTH_L */ -#define R367_QAM_AGC_IF_HTH_L 0xF41A -#define F367_QAM_AGC_IF_THHI_LO 0xF41A00FF - -/* AGC_IF_HTH_H */ -#define R367_QAM_AGC_IF_HTH_H 0xF41B -#define F367_QAM_AGC_IF_THHI_HI 0xF41B000F - -/* AGC_PWR_RD_L */ -#define R367_QAM_AGC_PWR_RD_L 0xF41C -#define F367_QAM_AGC_PWR_WORD_LO 0xF41C00FF - -/* AGC_PWR_RD_M */ -#define R367_QAM_AGC_PWR_RD_M 0xF41D -#define F367_QAM_AGC_PWR_WORD_ME 0xF41D00FF - -/* AGC_PWR_RD_H */ -#define R367_QAM_AGC_PWR_RD_H 0xF41E -#define F367_QAM_AGC_PWR_WORD_HI 0xF41E0003 - -/* AGC_PWM_IFCMD_L */ -#define R367_QAM_AGC_PWM_IFCMD_L 0xF420 -#define F367_QAM_AGC_IF_PWMCMD_LO 0xF42000FF - -/* AGC_PWM_IFCMD_H */ -#define R367_QAM_AGC_PWM_IFCMD_H 0xF421 -#define F367_QAM_AGC_IF_PWMCMD_HI 0xF421000F - -/* AGC_PWM_RFCMD_L */ -#define R367_QAM_AGC_PWM_RFCMD_L 0xF422 -#define F367_QAM_AGC_RF_PWMCMD_LO 0xF42200FF - -/* AGC_PWM_RFCMD_H */ -#define R367_QAM_AGC_PWM_RFCMD_H 0xF423 -#define F367_QAM_AGC_RF_PWMCMD_HI 0xF423000F - -/* IQDEM_CFG */ -#define R367_QAM_IQDEM_CFG 0xF424 -#define F367_QAM_IQDEM_CLK_SEL 0xF4240004 -#define F367_QAM_IQDEM_INVIQ 0xF4240002 -#define F367_QAM_IQDEM_A2DTYPE 0xF4240001 - -/* MIX_NCO_LL */ -#define R367_QAM_MIX_NCO_LL 0xF425 -#define F367_QAM_MIX_NCO_INC_LL 0xF42500FF - -/* MIX_NCO_HL */ -#define R367_QAM_MIX_NCO_HL 0xF426 -#define F367_QAM_MIX_NCO_INC_HL 0xF42600FF - -/* MIX_NCO_HH */ -#define R367_QAM_MIX_NCO_HH 0xF427 -#define F367_QAM_MIX_NCO_INVCNST 0xF4270080 -#define F367_QAM_MIX_NCO_INC_HH 0xF427007F - -/* SRC_NCO_LL */ -#define R367_QAM_SRC_NCO_LL 0xF428 -#define F367_QAM_SRC_NCO_INC_LL 0xF42800FF - -/* SRC_NCO_LH */ -#define R367_QAM_SRC_NCO_LH 0xF429 -#define F367_QAM_SRC_NCO_INC_LH 0xF42900FF - -/* SRC_NCO_HL */ -#define R367_QAM_SRC_NCO_HL 0xF42A -#define F367_QAM_SRC_NCO_INC_HL 0xF42A00FF - -/* SRC_NCO_HH */ -#define R367_QAM_SRC_NCO_HH 0xF42B -#define F367_QAM_SRC_NCO_INC_HH 0xF42B007F - -/* IQDEM_GAIN_SRC_L */ -#define R367_QAM_IQDEM_GAIN_SRC_L 0xF42C -#define F367_QAM_GAIN_SRC_LO 0xF42C00FF - -/* IQDEM_GAIN_SRC_H */ -#define R367_QAM_IQDEM_GAIN_SRC_H 0xF42D -#define F367_QAM_GAIN_SRC_HI 0xF42D0003 - -/* IQDEM_DCRM_CFG_LL */ -#define R367_QAM_IQDEM_DCRM_CFG_LL 0xF430 -#define F367_QAM_DCRM0_DCIN_L 0xF43000FF - -/* IQDEM_DCRM_CFG_LH */ -#define R367_QAM_IQDEM_DCRM_CFG_LH 0xF431 -#define F367_QAM_DCRM1_I_DCIN_L 0xF43100FC -#define F367_QAM_DCRM0_DCIN_H 0xF4310003 - -/* IQDEM_DCRM_CFG_HL */ -#define R367_QAM_IQDEM_DCRM_CFG_HL 0xF432 -#define F367_QAM_DCRM1_Q_DCIN_L 0xF43200F0 -#define F367_QAM_DCRM1_I_DCIN_H 0xF432000F - -/* IQDEM_DCRM_CFG_HH */ -#define R367_QAM_IQDEM_DCRM_CFG_HH 0xF433 -#define F367_QAM_DCRM1_FRZ 0xF4330080 -#define F367_QAM_DCRM0_FRZ 0xF4330040 -#define F367_QAM_DCRM1_Q_DCIN_H 0xF433003F - -/* IQDEM_ADJ_COEFF0 */ -#define R367_QAM_IQDEM_ADJ_COEFF0 0xF434 -#define F367_QAM_ADJIIR_COEFF10_L 0xF43400FF - -/* IQDEM_ADJ_COEFF1 */ -#define R367_QAM_IQDEM_ADJ_COEFF1 0xF435 -#define F367_QAM_ADJIIR_COEFF11_L 0xF43500FC -#define F367_QAM_ADJIIR_COEFF10_H 0xF4350003 - -/* IQDEM_ADJ_COEFF2 */ -#define R367_QAM_IQDEM_ADJ_COEFF2 0xF436 -#define F367_QAM_ADJIIR_COEFF12_L 0xF43600F0 -#define F367_QAM_ADJIIR_COEFF11_H 0xF436000F - -/* IQDEM_ADJ_COEFF3 */ -#define R367_QAM_IQDEM_ADJ_COEFF3 0xF437 -#define F367_QAM_ADJIIR_COEFF20_L 0xF43700C0 -#define F367_QAM_ADJIIR_COEFF12_H 0xF437003F - -/* IQDEM_ADJ_COEFF4 */ -#define R367_QAM_IQDEM_ADJ_COEFF4 0xF438 -#define F367_QAM_ADJIIR_COEFF20_H 0xF43800FF - -/* IQDEM_ADJ_COEFF5 */ -#define R367_QAM_IQDEM_ADJ_COEFF5 0xF439 -#define F367_QAM_ADJIIR_COEFF21_L 0xF43900FF - -/* IQDEM_ADJ_COEFF6 */ -#define R367_QAM_IQDEM_ADJ_COEFF6 0xF43A -#define F367_QAM_ADJIIR_COEFF22_L 0xF43A00FC -#define F367_QAM_ADJIIR_COEFF21_H 0xF43A0003 - -/* IQDEM_ADJ_COEFF7 */ -#define R367_QAM_IQDEM_ADJ_COEFF7 0xF43B -#define F367_QAM_ADJIIR_COEFF22_H 0xF43B000F - -/* IQDEM_ADJ_EN */ -#define R367_QAM_IQDEM_ADJ_EN 0xF43C -#define F367_QAM_ALLPASSFILT_EN 0xF43C0008 -#define F367_QAM_ADJ_AGC_EN 0xF43C0004 -#define F367_QAM_ADJ_COEFF_FRZ 0xF43C0002 -#define F367_QAM_ADJ_EN 0xF43C0001 - -/* IQDEM_ADJ_AGC_REF */ -#define R367_QAM_IQDEM_ADJ_AGC_REF 0xF43D -#define F367_QAM_ADJ_AGC_REF 0xF43D00FF - -/* ALLPASSFILT1 */ -#define R367_QAM_ALLPASSFILT1 0xF440 -#define F367_QAM_ALLPASSFILT_COEFF1_LO 0xF44000FF - -/* ALLPASSFILT2 */ -#define R367_QAM_ALLPASSFILT2 0xF441 -#define F367_QAM_ALLPASSFILT_COEFF1_ME 0xF44100FF - -/* ALLPASSFILT3 */ -#define R367_QAM_ALLPASSFILT3 0xF442 -#define F367_QAM_ALLPASSFILT_COEFF2_LO 0xF44200C0 -#define F367_QAM_ALLPASSFILT_COEFF1_HI 0xF442003F - -/* ALLPASSFILT4 */ -#define R367_QAM_ALLPASSFILT4 0xF443 -#define F367_QAM_ALLPASSFILT_COEFF2_MEL 0xF44300FF - -/* ALLPASSFILT5 */ -#define R367_QAM_ALLPASSFILT5 0xF444 -#define F367_QAM_ALLPASSFILT_COEFF2_MEH 0xF44400FF - -/* ALLPASSFILT6 */ -#define R367_QAM_ALLPASSFILT6 0xF445 -#define F367_QAM_ALLPASSFILT_COEFF3_LO 0xF44500F0 -#define F367_QAM_ALLPASSFILT_COEFF2_HI 0xF445000F - -/* ALLPASSFILT7 */ -#define R367_QAM_ALLPASSFILT7 0xF446 -#define F367_QAM_ALLPASSFILT_COEFF3_MEL 0xF44600FF - -/* ALLPASSFILT8 */ -#define R367_QAM_ALLPASSFILT8 0xF447 -#define F367_QAM_ALLPASSFILT_COEFF3_MEH 0xF44700FF - -/* ALLPASSFILT9 */ -#define R367_QAM_ALLPASSFILT9 0xF448 -#define F367_QAM_ALLPASSFILT_COEFF4_LO 0xF44800FC -#define F367_QAM_ALLPASSFILT_COEFF3_HI 0xF4480003 - -/* ALLPASSFILT10 */ -#define R367_QAM_ALLPASSFILT10 0xF449 -#define F367_QAM_ALLPASSFILT_COEFF4_ME 0xF44900FF - -/* ALLPASSFILT11 */ -#define R367_QAM_ALLPASSFILT11 0xF44A -#define F367_QAM_ALLPASSFILT_COEFF4_HI 0xF44A00FF - -/* TRL_AGC_CFG */ -#define R367_QAM_TRL_AGC_CFG 0xF450 -#define F367_QAM_TRL_AGC_FREEZE 0xF4500080 -#define F367_QAM_TRL_AGC_REF 0xF450007F - -/* TRL_LPF_CFG */ -#define R367_QAM_TRL_LPF_CFG 0xF454 -#define F367_QAM_NYQPOINT_INV 0xF4540040 -#define F367_QAM_TRL_SHIFT 0xF4540030 -#define F367_QAM_NYQ_COEFF_SEL 0xF454000C -#define F367_QAM_TRL_LPF_FREEZE 0xF4540002 -#define F367_QAM_TRL_LPF_CRT 0xF4540001 - -/* TRL_LPF_ACQ_GAIN */ -#define R367_QAM_TRL_LPF_ACQ_GAIN 0xF455 -#define F367_QAM_TRL_GDIR_ACQ 0xF4550070 -#define F367_QAM_TRL_GINT_ACQ 0xF4550007 - -/* TRL_LPF_TRK_GAIN */ -#define R367_QAM_TRL_LPF_TRK_GAIN 0xF456 -#define F367_QAM_TRL_GDIR_TRK 0xF4560070 -#define F367_QAM_TRL_GINT_TRK 0xF4560007 - -/* TRL_LPF_OUT_GAIN */ -#define R367_QAM_TRL_LPF_OUT_GAIN 0xF457 -#define F367_QAM_TRL_GAIN_OUT 0xF4570007 - -/* TRL_LOCKDET_LTH */ -#define R367_QAM_TRL_LOCKDET_LTH 0xF458 -#define F367_QAM_TRL_LCK_THLO 0xF4580007 - -/* TRL_LOCKDET_HTH */ -#define R367_QAM_TRL_LOCKDET_HTH 0xF459 -#define F367_QAM_TRL_LCK_THHI 0xF45900FF - -/* TRL_LOCKDET_TRGVAL */ -#define R367_QAM_TRL_LOCKDET_TRGVAL 0xF45A -#define F367_QAM_TRL_LCK_TRG 0xF45A00FF - -/* IQ_QAM */ -#define R367_QAM_IQ_QAM 0xF45C -#define F367_QAM_IQ_INPUT 0xF45C0008 -#define F367_QAM_DETECT_MODE 0xF45C0007 - -/* FSM_STATE */ -#define R367_QAM_FSM_STATE 0xF460 -#define F367_QAM_CRL_DFE 0xF4600080 -#define F367_QAM_DFE_START 0xF4600040 -#define F367_QAM_CTRLG_START 0xF4600030 -#define F367_QAM_FSM_FORCESTATE 0xF460000F - -/* FSM_CTL */ -#define R367_QAM_FSM_CTL 0xF461 -#define F367_QAM_FEC2_EN 0xF4610040 -#define F367_QAM_SIT_EN 0xF4610020 -#define F367_QAM_TRL_AHEAD 0xF4610010 -#define F367_QAM_TRL2_EN 0xF4610008 -#define F367_QAM_FSM_EQA1_EN 0xF4610004 -#define F367_QAM_FSM_BKP_DIS 0xF4610002 -#define F367_QAM_FSM_FORCE_EN 0xF4610001 - -/* FSM_STS */ -#define R367_QAM_FSM_STS 0xF462 -#define F367_QAM_FSM_STATUS 0xF462000F - -/* FSM_SNR0_HTH */ -#define R367_QAM_FSM_SNR0_HTH 0xF463 -#define F367_QAM_SNR0_HTH 0xF46300FF - -/* FSM_SNR1_HTH */ -#define R367_QAM_FSM_SNR1_HTH 0xF464 -#define F367_QAM_SNR1_HTH 0xF46400FF - -/* FSM_SNR2_HTH */ -#define R367_QAM_FSM_SNR2_HTH 0xF465 -#define F367_QAM_SNR2_HTH 0xF46500FF - -/* FSM_SNR0_LTH */ -#define R367_QAM_FSM_SNR0_LTH 0xF466 -#define F367_QAM_SNR0_LTH 0xF46600FF - -/* FSM_SNR1_LTH */ -#define R367_QAM_FSM_SNR1_LTH 0xF467 -#define F367_QAM_SNR1_LTH 0xF46700FF - -/* FSM_EQA1_HTH */ -#define R367_QAM_FSM_EQA1_HTH 0xF468 -#define F367_QAM_SNR3_HTH_LO 0xF46800F0 -#define F367_QAM_EQA1_HTH 0xF468000F - -/* FSM_TEMPO */ -#define R367_QAM_FSM_TEMPO 0xF469 -#define F367_QAM_SIT 0xF46900C0 -#define F367_QAM_WST 0xF4690038 -#define F367_QAM_ELT 0xF4690006 -#define F367_QAM_SNR3_HTH_HI 0xF4690001 - -/* FSM_CONFIG */ -#define R367_QAM_FSM_CONFIG 0xF46A -#define F367_QAM_FEC2_DFEOFF 0xF46A0004 -#define F367_QAM_PRIT_STATE 0xF46A0002 -#define F367_QAM_MODMAP_STATE 0xF46A0001 - -/* EQU_I_TESTTAP_L */ -#define R367_QAM_EQU_I_TESTTAP_L 0xF474 -#define F367_QAM_I_TEST_TAP_L 0xF47400FF - -/* EQU_I_TESTTAP_M */ -#define R367_QAM_EQU_I_TESTTAP_M 0xF475 -#define F367_QAM_I_TEST_TAP_M 0xF47500FF - -/* EQU_I_TESTTAP_H */ -#define R367_QAM_EQU_I_TESTTAP_H 0xF476 -#define F367_QAM_I_TEST_TAP_H 0xF476001F - -/* EQU_TESTAP_CFG */ -#define R367_QAM_EQU_TESTAP_CFG 0xF477 -#define F367_QAM_TEST_FFE_DFE_SEL 0xF4770040 -#define F367_QAM_TEST_TAP_SELECT 0xF477003F - -/* EQU_Q_TESTTAP_L */ -#define R367_QAM_EQU_Q_TESTTAP_L 0xF478 -#define F367_QAM_Q_TEST_TAP_L 0xF47800FF - -/* EQU_Q_TESTTAP_M */ -#define R367_QAM_EQU_Q_TESTTAP_M 0xF479 -#define F367_QAM_Q_TEST_TAP_M 0xF47900FF - -/* EQU_Q_TESTTAP_H */ -#define R367_QAM_EQU_Q_TESTTAP_H 0xF47A -#define F367_QAM_Q_TEST_TAP_H 0xF47A001F - -/* EQU_TAP_CTRL */ -#define R367_QAM_EQU_TAP_CTRL 0xF47B -#define F367_QAM_MTAP_FRZ 0xF47B0010 -#define F367_QAM_PRE_FREEZE 0xF47B0008 -#define F367_QAM_DFE_TAPMON_EN 0xF47B0004 -#define F367_QAM_FFE_TAPMON_EN 0xF47B0002 -#define F367_QAM_MTAP_ONLY 0xF47B0001 - -/* EQU_CTR_CRL_CONTROL_L */ -#define R367_QAM_EQU_CTR_CRL_CONTROL_L 0xF47C -#define F367_QAM_EQU_CTR_CRL_CONTROL_LO 0xF47C00FF - -/* EQU_CTR_CRL_CONTROL_H */ -#define R367_QAM_EQU_CTR_CRL_CONTROL_H 0xF47D -#define F367_QAM_EQU_CTR_CRL_CONTROL_HI 0xF47D00FF - -/* EQU_CTR_HIPOW_L */ -#define R367_QAM_EQU_CTR_HIPOW_L 0xF47E -#define F367_QAM_CTR_HIPOW_L 0xF47E00FF - -/* EQU_CTR_HIPOW_H */ -#define R367_QAM_EQU_CTR_HIPOW_H 0xF47F -#define F367_QAM_CTR_HIPOW_H 0xF47F00FF - -/* EQU_I_EQU_LO */ -#define R367_QAM_EQU_I_EQU_LO 0xF480 -#define F367_QAM_EQU_I_EQU_L 0xF48000FF - -/* EQU_I_EQU_HI */ -#define R367_QAM_EQU_I_EQU_HI 0xF481 -#define F367_QAM_EQU_I_EQU_H 0xF4810003 - -/* EQU_Q_EQU_LO */ -#define R367_QAM_EQU_Q_EQU_LO 0xF482 -#define F367_QAM_EQU_Q_EQU_L 0xF48200FF - -/* EQU_Q_EQU_HI */ -#define R367_QAM_EQU_Q_EQU_HI 0xF483 -#define F367_QAM_EQU_Q_EQU_H 0xF4830003 - -/* EQU_MAPPER */ -#define R367_QAM_EQU_MAPPER 0xF484 -#define F367_QAM_QUAD_AUTO 0xF4840080 -#define F367_QAM_QUAD_INV 0xF4840040 -#define F367_QAM_QAM_MODE 0xF4840007 - -/* EQU_SWEEP_RATE */ -#define R367_QAM_EQU_SWEEP_RATE 0xF485 -#define F367_QAM_SNR_PER 0xF48500C0 -#define F367_QAM_SWEEP_RATE 0xF485003F - -/* EQU_SNR_LO */ -#define R367_QAM_EQU_SNR_LO 0xF486 -#define F367_QAM_SNR_LO 0xF48600FF - -/* EQU_SNR_HI */ -#define R367_QAM_EQU_SNR_HI 0xF487 -#define F367_QAM_SNR_HI 0xF48700FF - -/* EQU_GAMMA_LO */ -#define R367_QAM_EQU_GAMMA_LO 0xF488 -#define F367_QAM_GAMMA_LO 0xF48800FF - -/* EQU_GAMMA_HI */ -#define R367_QAM_EQU_GAMMA_HI 0xF489 -#define F367_QAM_GAMMA_ME 0xF48900FF - -/* EQU_ERR_GAIN */ -#define R367_QAM_EQU_ERR_GAIN 0xF48A -#define F367_QAM_EQA1MU 0xF48A0070 -#define F367_QAM_CRL2MU 0xF48A000E -#define F367_QAM_GAMMA_HI 0xF48A0001 - -/* EQU_RADIUS */ -#define R367_QAM_EQU_RADIUS 0xF48B -#define F367_QAM_RADIUS 0xF48B00FF - -/* EQU_FFE_MAINTAP */ -#define R367_QAM_EQU_FFE_MAINTAP 0xF48C -#define F367_QAM_FFE_MAINTAP_INIT 0xF48C00FF - -/* EQU_FFE_LEAKAGE */ -#define R367_QAM_EQU_FFE_LEAKAGE 0xF48E -#define F367_QAM_LEAK_PER 0xF48E00F0 -#define F367_QAM_EQU_OUTSEL 0xF48E0002 -#define F367_QAM_PNT2DFE 0xF48E0001 - -/* EQU_FFE_MAINTAP_POS */ -#define R367_QAM_EQU_FFE_MAINTAP_POS 0xF48F -#define F367_QAM_FFE_LEAK_EN 0xF48F0080 -#define F367_QAM_DFE_LEAK_EN 0xF48F0040 -#define F367_QAM_FFE_MAINTAP_POS 0xF48F003F - -/* EQU_GAIN_WIDE */ -#define R367_QAM_EQU_GAIN_WIDE 0xF490 -#define F367_QAM_DFE_GAIN_WIDE 0xF49000F0 -#define F367_QAM_FFE_GAIN_WIDE 0xF490000F - -/* EQU_GAIN_NARROW */ -#define R367_QAM_EQU_GAIN_NARROW 0xF491 -#define F367_QAM_DFE_GAIN_NARROW 0xF49100F0 -#define F367_QAM_FFE_GAIN_NARROW 0xF491000F - -/* EQU_CTR_LPF_GAIN */ -#define R367_QAM_EQU_CTR_LPF_GAIN 0xF492 -#define F367_QAM_CTR_GTO 0xF4920080 -#define F367_QAM_CTR_GDIR 0xF4920070 -#define F367_QAM_SWEEP_EN 0xF4920008 -#define F367_QAM_CTR_GINT 0xF4920007 - -/* EQU_CRL_LPF_GAIN */ -#define R367_QAM_EQU_CRL_LPF_GAIN 0xF493 -#define F367_QAM_CRL_GTO 0xF4930080 -#define F367_QAM_CRL_GDIR 0xF4930070 -#define F367_QAM_SWEEP_DIR 0xF4930008 -#define F367_QAM_CRL_GINT 0xF4930007 - -/* EQU_GLOBAL_GAIN */ -#define R367_QAM_EQU_GLOBAL_GAIN 0xF494 -#define F367_QAM_CRL_GAIN 0xF49400F8 -#define F367_QAM_CTR_INC_GAIN 0xF4940004 -#define F367_QAM_CTR_FRAC 0xF4940003 - -/* EQU_CRL_LD_SEN */ -#define R367_QAM_EQU_CRL_LD_SEN 0xF495 -#define F367_QAM_CTR_BADPOINT_EN 0xF4950080 -#define F367_QAM_CTR_GAIN 0xF4950070 -#define F367_QAM_LIMANEN 0xF4950008 -#define F367_QAM_CRL_LD_SEN 0xF4950007 - -/* EQU_CRL_LD_VAL */ -#define R367_QAM_EQU_CRL_LD_VAL 0xF496 -#define F367_QAM_CRL_BISTH_LIMIT 0xF4960080 -#define F367_QAM_CARE_EN 0xF4960040 -#define F367_QAM_CRL_LD_PER 0xF4960030 -#define F367_QAM_CRL_LD_WST 0xF496000C -#define F367_QAM_CRL_LD_TFS 0xF4960003 - -/* EQU_CRL_TFR */ -#define R367_QAM_EQU_CRL_TFR 0xF497 -#define F367_QAM_CRL_LD_TFR 0xF49700FF - -/* EQU_CRL_BISTH_LO */ -#define R367_QAM_EQU_CRL_BISTH_LO 0xF498 -#define F367_QAM_CRL_BISTH_LO 0xF49800FF - -/* EQU_CRL_BISTH_HI */ -#define R367_QAM_EQU_CRL_BISTH_HI 0xF499 -#define F367_QAM_CRL_BISTH_HI 0xF49900FF - -/* EQU_SWEEP_RANGE_LO */ -#define R367_QAM_EQU_SWEEP_RANGE_LO 0xF49A -#define F367_QAM_SWEEP_RANGE_LO 0xF49A00FF - -/* EQU_SWEEP_RANGE_HI */ -#define R367_QAM_EQU_SWEEP_RANGE_HI 0xF49B -#define F367_QAM_SWEEP_RANGE_HI 0xF49B00FF - -/* EQU_CRL_LIMITER */ -#define R367_QAM_EQU_CRL_LIMITER 0xF49C -#define F367_QAM_BISECTOR_EN 0xF49C0080 -#define F367_QAM_PHEST128_EN 0xF49C0040 -#define F367_QAM_CRL_LIM 0xF49C003F - -/* EQU_MODULUS_MAP */ -#define R367_QAM_EQU_MODULUS_MAP 0xF49D -#define F367_QAM_PNT_DEPTH 0xF49D00E0 -#define F367_QAM_MODULUS_CMP 0xF49D001F - -/* EQU_PNT_GAIN */ -#define R367_QAM_EQU_PNT_GAIN 0xF49E -#define F367_QAM_PNT_EN 0xF49E0080 -#define F367_QAM_MODULUSMAP_EN 0xF49E0040 -#define F367_QAM_PNT_GAIN 0xF49E003F - -/* FEC_AC_CTR_0 */ -#define R367_QAM_FEC_AC_CTR_0 0xF4A8 -#define F367_QAM_BE_BYPASS 0xF4A80020 -#define F367_QAM_REFRESH47 0xF4A80010 -#define F367_QAM_CT_NBST 0xF4A80008 -#define F367_QAM_TEI_ENA 0xF4A80004 -#define F367_QAM_DS_ENA 0xF4A80002 -#define F367_QAM_TSMF_EN 0xF4A80001 - -/* FEC_AC_CTR_1 */ -#define R367_QAM_FEC_AC_CTR_1 0xF4A9 -#define F367_QAM_DEINT_DEPTH 0xF4A900FF - -/* FEC_AC_CTR_2 */ -#define R367_QAM_FEC_AC_CTR_2 0xF4AA -#define F367_QAM_DEINT_M 0xF4AA00F8 -#define F367_QAM_DIS_UNLOCK 0xF4AA0004 -#define F367_QAM_DESCR_MODE 0xF4AA0003 - -/* FEC_AC_CTR_3 */ -#define R367_QAM_FEC_AC_CTR_3 0xF4AB -#define F367_QAM_DI_UNLOCK 0xF4AB0080 -#define F367_QAM_DI_FREEZE 0xF4AB0040 -#define F367_QAM_MISMATCH 0xF4AB0030 -#define F367_QAM_ACQ_MODE 0xF4AB000C -#define F367_QAM_TRK_MODE 0xF4AB0003 - -/* FEC_STATUS */ -#define R367_QAM_FEC_STATUS 0xF4AC -#define F367_QAM_DEINT_SMCNTR 0xF4AC00E0 -#define F367_QAM_DEINT_SYNCSTATE 0xF4AC0018 -#define F367_QAM_DEINT_SYNLOST 0xF4AC0004 -#define F367_QAM_DESCR_SYNCSTATE 0xF4AC0002 - -/* RS_COUNTER_0 */ -#define R367_QAM_RS_COUNTER_0 0xF4AE -#define F367_QAM_BK_CT_L 0xF4AE00FF - -/* RS_COUNTER_1 */ -#define R367_QAM_RS_COUNTER_1 0xF4AF -#define F367_QAM_BK_CT_H 0xF4AF00FF - -/* RS_COUNTER_2 */ -#define R367_QAM_RS_COUNTER_2 0xF4B0 -#define F367_QAM_CORR_CT_L 0xF4B000FF - -/* RS_COUNTER_3 */ -#define R367_QAM_RS_COUNTER_3 0xF4B1 -#define F367_QAM_CORR_CT_H 0xF4B100FF - -/* RS_COUNTER_4 */ -#define R367_QAM_RS_COUNTER_4 0xF4B2 -#define F367_QAM_UNCORR_CT_L 0xF4B200FF - -/* RS_COUNTER_5 */ -#define R367_QAM_RS_COUNTER_5 0xF4B3 -#define F367_QAM_UNCORR_CT_H 0xF4B300FF - -/* BERT_0 */ -#define R367_QAM_BERT_0 0xF4B4 -#define F367_QAM_RS_NOCORR 0xF4B40004 -#define F367_QAM_CT_HOLD 0xF4B40002 -#define F367_QAM_CT_CLEAR 0xF4B40001 - -/* BERT_1 */ -#define R367_QAM_BERT_1 0xF4B5 -#define F367_QAM_BERT_ON 0xF4B50020 -#define F367_QAM_BERT_ERR_SRC 0xF4B50010 -#define F367_QAM_BERT_ERR_MODE 0xF4B50008 -#define F367_QAM_BERT_NBYTE 0xF4B50007 - -/* BERT_2 */ -#define R367_QAM_BERT_2 0xF4B6 -#define F367_QAM_BERT_ERRCOUNT_L 0xF4B600FF - -/* BERT_3 */ -#define R367_QAM_BERT_3 0xF4B7 -#define F367_QAM_BERT_ERRCOUNT_H 0xF4B700FF - -/* OUTFORMAT_0 */ -#define R367_QAM_OUTFORMAT_0 0xF4B8 -#define F367_QAM_CLK_POLARITY 0xF4B80080 -#define F367_QAM_FEC_TYPE 0xF4B80040 -#define F367_QAM_SYNC_STRIP 0xF4B80008 -#define F367_QAM_TS_SWAP 0xF4B80004 -#define F367_QAM_OUTFORMAT 0xF4B80003 - -/* OUTFORMAT_1 */ -#define R367_QAM_OUTFORMAT_1 0xF4B9 -#define F367_QAM_CI_DIVRANGE 0xF4B900FF - -/* SMOOTHER_2 */ -#define R367_QAM_SMOOTHER_2 0xF4BE -#define F367_QAM_FIFO_BYPASS 0xF4BE0020 - -/* TSMF_CTRL_0 */ -#define R367_QAM_TSMF_CTRL_0 0xF4C0 -#define F367_QAM_TS_NUMBER 0xF4C0001E -#define F367_QAM_SEL_MODE 0xF4C00001 - -/* TSMF_CTRL_1 */ -#define R367_QAM_TSMF_CTRL_1 0xF4C1 -#define F367_QAM_CHECK_ERROR_BIT 0xF4C10080 -#define F367_QAM_CHCK_F_SYNC 0xF4C10040 -#define F367_QAM_H_MODE 0xF4C10008 -#define F367_QAM_D_V_MODE 0xF4C10004 -#define F367_QAM_MODE 0xF4C10003 - -/* TSMF_CTRL_3 */ -#define R367_QAM_TSMF_CTRL_3 0xF4C3 -#define F367_QAM_SYNC_IN_COUNT 0xF4C300F0 -#define F367_QAM_SYNC_OUT_COUNT 0xF4C3000F - -/* TS_ON_ID_0 */ -#define R367_QAM_TS_ON_ID_0 0xF4C4 -#define F367_QAM_TS_ID_L 0xF4C400FF - -/* TS_ON_ID_1 */ -#define R367_QAM_TS_ON_ID_1 0xF4C5 -#define F367_QAM_TS_ID_H 0xF4C500FF - -/* TS_ON_ID_2 */ -#define R367_QAM_TS_ON_ID_2 0xF4C6 -#define F367_QAM_ON_ID_L 0xF4C600FF - -/* TS_ON_ID_3 */ -#define R367_QAM_TS_ON_ID_3 0xF4C7 -#define F367_QAM_ON_ID_H 0xF4C700FF - -/* RE_STATUS_0 */ -#define R367_QAM_RE_STATUS_0 0xF4C8 -#define F367_QAM_RECEIVE_STATUS_L 0xF4C800FF - -/* RE_STATUS_1 */ -#define R367_QAM_RE_STATUS_1 0xF4C9 -#define F367_QAM_RECEIVE_STATUS_LH 0xF4C900FF - -/* RE_STATUS_2 */ -#define R367_QAM_RE_STATUS_2 0xF4CA -#define F367_QAM_RECEIVE_STATUS_HL 0xF4CA00FF - -/* RE_STATUS_3 */ -#define R367_QAM_RE_STATUS_3 0xF4CB -#define F367_QAM_RECEIVE_STATUS_HH 0xF4CB003F - -/* TS_STATUS_0 */ -#define R367_QAM_TS_STATUS_0 0xF4CC -#define F367_QAM_TS_STATUS_L 0xF4CC00FF - -/* TS_STATUS_1 */ -#define R367_QAM_TS_STATUS_1 0xF4CD -#define F367_QAM_TS_STATUS_H 0xF4CD007F - -/* TS_STATUS_2 */ -#define R367_QAM_TS_STATUS_2 0xF4CE -#define F367_QAM_ERROR 0xF4CE0080 -#define F367_QAM_EMERGENCY 0xF4CE0040 -#define F367_QAM_CRE_TS 0xF4CE0030 -#define F367_QAM_VER 0xF4CE000E -#define F367_QAM_M_LOCK 0xF4CE0001 - -/* TS_STATUS_3 */ -#define R367_QAM_TS_STATUS_3 0xF4CF -#define F367_QAM_UPDATE_READY 0xF4CF0080 -#define F367_QAM_END_FRAME_HEADER 0xF4CF0040 -#define F367_QAM_CONTCNT 0xF4CF0020 -#define F367_QAM_TS_IDENTIFIER_SEL 0xF4CF000F - -/* T_O_ID_0 */ -#define R367_QAM_T_O_ID_0 0xF4D0 -#define F367_QAM_ON_ID_I_L 0xF4D000FF - -/* T_O_ID_1 */ -#define R367_QAM_T_O_ID_1 0xF4D1 -#define F367_QAM_ON_ID_I_H 0xF4D100FF - -/* T_O_ID_2 */ -#define R367_QAM_T_O_ID_2 0xF4D2 -#define F367_QAM_TS_ID_I_L 0xF4D200FF - -/* T_O_ID_3 */ -#define R367_QAM_T_O_ID_3 0xF4D3 -#define F367_QAM_TS_ID_I_H 0xF4D300FF - diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,4922 +0,0 @@ -/* - STV0900/0903 Multistandard Broadcast Frontend driver - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include "dvb_frontend.h" - -#include "stv6110x.h" /* for demodulator internal modes */ - -#include "stv090x_reg.h" -#include "stv090x.h" -#include "stv090x_priv.h" - - #define ERRCTRL1_DVBS1 0x76 -#define ERRCTRL1_DVBS2 0x67 - -static unsigned int verbose; -module_param(verbose, int, 0644); - -/* internal params node */ -struct stv090x_dev { - /* pointer for internal params, one for each pair of demods */ - struct stv090x_internal *internal; - struct stv090x_dev *next_dev; -}; - -/* first internal params */ -static struct stv090x_dev *stv090x_first_dev; - -/* find chip by i2c adapter and i2c address */ -static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap, - u8 i2c_addr) -{ - struct stv090x_dev *temp_dev = stv090x_first_dev; - - /* - Search of the last stv0900 chip or - find it by i2c adapter and i2c address */ - while ((temp_dev != NULL) && - ((temp_dev->internal->i2c_adap != i2c_adap) || - (temp_dev->internal->i2c_addr != i2c_addr))) { - - temp_dev = temp_dev->next_dev; - } - - return temp_dev; -} - -/* deallocating chip */ -static void remove_dev(struct stv090x_internal *internal) -{ - struct stv090x_dev *prev_dev = stv090x_first_dev; - struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, - internal->i2c_addr); - - if (del_dev != NULL) { - if (del_dev == stv090x_first_dev) { - stv090x_first_dev = del_dev->next_dev; - } else { - while (prev_dev->next_dev != del_dev) - prev_dev = prev_dev->next_dev; - - prev_dev->next_dev = del_dev->next_dev; - } - - kfree(del_dev); - } -} - -/* allocating new chip */ -static struct stv090x_dev *append_internal(struct stv090x_internal *internal) -{ - struct stv090x_dev *new_dev; - struct stv090x_dev *temp_dev; - - new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL); - if (new_dev != NULL) { - new_dev->internal = internal; - new_dev->next_dev = NULL; - - /* append to list */ - if (stv090x_first_dev == NULL) { - stv090x_first_dev = new_dev; - } else { - temp_dev = stv090x_first_dev; - while (temp_dev->next_dev != NULL) - temp_dev = temp_dev->next_dev; - - temp_dev->next_dev = new_dev; - } - } - - return new_dev; -} - - -/* DVBS1 and DSS C/N Lookup table */ -static const struct stv090x_tab stv090x_s1cn_tab[] = { - { 0, 8917 }, /* 0.0dB */ - { 5, 8801 }, /* 0.5dB */ - { 10, 8667 }, /* 1.0dB */ - { 15, 8522 }, /* 1.5dB */ - { 20, 8355 }, /* 2.0dB */ - { 25, 8175 }, /* 2.5dB */ - { 30, 7979 }, /* 3.0dB */ - { 35, 7763 }, /* 3.5dB */ - { 40, 7530 }, /* 4.0dB */ - { 45, 7282 }, /* 4.5dB */ - { 50, 7026 }, /* 5.0dB */ - { 55, 6781 }, /* 5.5dB */ - { 60, 6514 }, /* 6.0dB */ - { 65, 6241 }, /* 6.5dB */ - { 70, 5965 }, /* 7.0dB */ - { 75, 5690 }, /* 7.5dB */ - { 80, 5424 }, /* 8.0dB */ - { 85, 5161 }, /* 8.5dB */ - { 90, 4902 }, /* 9.0dB */ - { 95, 4654 }, /* 9.5dB */ - { 100, 4417 }, /* 10.0dB */ - { 105, 4186 }, /* 10.5dB */ - { 110, 3968 }, /* 11.0dB */ - { 115, 3757 }, /* 11.5dB */ - { 120, 3558 }, /* 12.0dB */ - { 125, 3366 }, /* 12.5dB */ - { 130, 3185 }, /* 13.0dB */ - { 135, 3012 }, /* 13.5dB */ - { 140, 2850 }, /* 14.0dB */ - { 145, 2698 }, /* 14.5dB */ - { 150, 2550 }, /* 15.0dB */ - { 160, 2283 }, /* 16.0dB */ - { 170, 2042 }, /* 17.0dB */ - { 180, 1827 }, /* 18.0dB */ - { 190, 1636 }, /* 19.0dB */ - { 200, 1466 }, /* 20.0dB */ - { 210, 1315 }, /* 21.0dB */ - { 220, 1181 }, /* 22.0dB */ - { 230, 1064 }, /* 23.0dB */ - { 240, 960 }, /* 24.0dB */ - { 250, 869 }, /* 25.0dB */ - { 260, 792 }, /* 26.0dB */ - { 270, 724 }, /* 27.0dB */ - { 280, 665 }, /* 28.0dB */ - { 290, 616 }, /* 29.0dB */ - { 300, 573 }, /* 30.0dB */ - { 310, 537 }, /* 31.0dB */ - { 320, 507 }, /* 32.0dB */ - { 330, 483 }, /* 33.0dB */ - { 400, 398 }, /* 40.0dB */ - { 450, 381 }, /* 45.0dB */ - { 500, 377 } /* 50.0dB */ -}; - -/* DVBS2 C/N Lookup table */ -static const struct stv090x_tab stv090x_s2cn_tab[] = { - { -30, 13348 }, /* -3.0dB */ - { -20, 12640 }, /* -2d.0B */ - { -10, 11883 }, /* -1.0dB */ - { 0, 11101 }, /* -0.0dB */ - { 5, 10718 }, /* 0.5dB */ - { 10, 10339 }, /* 1.0dB */ - { 15, 9947 }, /* 1.5dB */ - { 20, 9552 }, /* 2.0dB */ - { 25, 9183 }, /* 2.5dB */ - { 30, 8799 }, /* 3.0dB */ - { 35, 8422 }, /* 3.5dB */ - { 40, 8062 }, /* 4.0dB */ - { 45, 7707 }, /* 4.5dB */ - { 50, 7353 }, /* 5.0dB */ - { 55, 7025 }, /* 5.5dB */ - { 60, 6684 }, /* 6.0dB */ - { 65, 6331 }, /* 6.5dB */ - { 70, 6036 }, /* 7.0dB */ - { 75, 5727 }, /* 7.5dB */ - { 80, 5437 }, /* 8.0dB */ - { 85, 5164 }, /* 8.5dB */ - { 90, 4902 }, /* 9.0dB */ - { 95, 4653 }, /* 9.5dB */ - { 100, 4408 }, /* 10.0dB */ - { 105, 4187 }, /* 10.5dB */ - { 110, 3961 }, /* 11.0dB */ - { 115, 3751 }, /* 11.5dB */ - { 120, 3558 }, /* 12.0dB */ - { 125, 3368 }, /* 12.5dB */ - { 130, 3191 }, /* 13.0dB */ - { 135, 3017 }, /* 13.5dB */ - { 140, 2862 }, /* 14.0dB */ - { 145, 2710 }, /* 14.5dB */ - { 150, 2565 }, /* 15.0dB */ - { 160, 2300 }, /* 16.0dB */ - { 170, 2058 }, /* 17.0dB */ - { 180, 1849 }, /* 18.0dB */ - { 190, 1663 }, /* 19.0dB */ - { 200, 1495 }, /* 20.0dB */ - { 210, 1349 }, /* 21.0dB */ - { 220, 1222 }, /* 22.0dB */ - { 230, 1110 }, /* 23.0dB */ - { 240, 1011 }, /* 24.0dB */ - { 250, 925 }, /* 25.0dB */ - { 260, 853 }, /* 26.0dB */ - { 270, 789 }, /* 27.0dB */ - { 280, 734 }, /* 28.0dB */ - { 290, 690 }, /* 29.0dB */ - { 300, 650 }, /* 30.0dB */ - { 310, 619 }, /* 31.0dB */ - { 320, 593 }, /* 32.0dB */ - { 330, 571 }, /* 33.0dB */ - { 400, 498 }, /* 40.0dB */ - { 450, 484 }, /* 45.0dB */ - { 500, 481 } /* 50.0dB */ -}; - -/* RF level C/N lookup table */ -static const struct stv090x_tab stv090x_rf_tab[] = { - { -5, 0xcaa1 }, /* -5dBm */ - { -10, 0xc229 }, /* -10dBm */ - { -15, 0xbb08 }, /* -15dBm */ - { -20, 0xb4bc }, /* -20dBm */ - { -25, 0xad5a }, /* -25dBm */ - { -30, 0xa298 }, /* -30dBm */ - { -35, 0x98a8 }, /* -35dBm */ - { -40, 0x8389 }, /* -40dBm */ - { -45, 0x59be }, /* -45dBm */ - { -50, 0x3a14 }, /* -50dBm */ - { -55, 0x2d11 }, /* -55dBm */ - { -60, 0x210d }, /* -60dBm */ - { -65, 0xa14f }, /* -65dBm */ - { -70, 0x07aa } /* -70dBm */ -}; - - -static struct stv090x_reg stv0900_initval[] = { - - { STV090x_OUTCFG, 0x00 }, - { STV090x_MODECFG, 0xff }, - { STV090x_AGCRF1CFG, 0x11 }, - { STV090x_AGCRF2CFG, 0x13 }, - { STV090x_TSGENERAL1X, 0x14 }, - { STV090x_TSTTNR2, 0x21 }, - { STV090x_TSTTNR4, 0x21 }, - { STV090x_P2_DISTXCTL, 0x22 }, - { STV090x_P2_F22TX, 0xc0 }, - { STV090x_P2_F22RX, 0xc0 }, - { STV090x_P2_DISRXCTL, 0x00 }, - { STV090x_P2_DMDCFGMD, 0xF9 }, - { STV090x_P2_DEMOD, 0x08 }, - { STV090x_P2_DMDCFG3, 0xc4 }, - { STV090x_P2_CARFREQ, 0xed }, - { STV090x_P2_LDT, 0xd0 }, - { STV090x_P2_LDT2, 0xb8 }, - { STV090x_P2_TMGCFG, 0xd2 }, - { STV090x_P2_TMGTHRISE, 0x20 }, - { STV090x_P1_TMGCFG, 0xd2 }, - - { STV090x_P2_TMGTHFALL, 0x00 }, - { STV090x_P2_FECSPY, 0x88 }, - { STV090x_P2_FSPYDATA, 0x3a }, - { STV090x_P2_FBERCPT4, 0x00 }, - { STV090x_P2_FSPYBER, 0x10 }, - { STV090x_P2_ERRCTRL1, 0x35 }, - { STV090x_P2_ERRCTRL2, 0xc1 }, - { STV090x_P2_CFRICFG, 0xf8 }, - { STV090x_P2_NOSCFG, 0x1c }, - { STV090x_P2_DMDTOM, 0x20 }, - { STV090x_P2_CORRELMANT, 0x70 }, - { STV090x_P2_CORRELABS, 0x88 }, - { STV090x_P2_AGC2O, 0x5b }, - { STV090x_P2_AGC2REF, 0x38 }, - { STV090x_P2_CARCFG, 0xe4 }, - { STV090x_P2_ACLC, 0x1A }, - { STV090x_P2_BCLC, 0x09 }, - { STV090x_P2_CARHDR, 0x08 }, - { STV090x_P2_KREFTMG, 0xc1 }, - { STV090x_P2_SFRUPRATIO, 0xf0 }, - { STV090x_P2_SFRLOWRATIO, 0x70 }, - { STV090x_P2_SFRSTEP, 0x58 }, - { STV090x_P2_TMGCFG2, 0x01 }, - { STV090x_P2_CAR2CFG, 0x26 }, - { STV090x_P2_BCLC2S2Q, 0x86 }, - { STV090x_P2_BCLC2S28, 0x86 }, - { STV090x_P2_SMAPCOEF7, 0x77 }, - { STV090x_P2_SMAPCOEF6, 0x85 }, - { STV090x_P2_SMAPCOEF5, 0x77 }, - { STV090x_P2_TSCFGL, 0x20 }, - { STV090x_P2_DMDCFG2, 0x3b }, - { STV090x_P2_MODCODLST0, 0xff }, - { STV090x_P2_MODCODLST1, 0xff }, - { STV090x_P2_MODCODLST2, 0xff }, - { STV090x_P2_MODCODLST3, 0xff }, - { STV090x_P2_MODCODLST4, 0xff }, - { STV090x_P2_MODCODLST5, 0xff }, - { STV090x_P2_MODCODLST6, 0xff }, - { STV090x_P2_MODCODLST7, 0xcc }, - { STV090x_P2_MODCODLST8, 0xcc }, - { STV090x_P2_MODCODLST9, 0xcc }, - { STV090x_P2_MODCODLSTA, 0xcc }, - { STV090x_P2_MODCODLSTB, 0xcc }, - { STV090x_P2_MODCODLSTC, 0xcc }, - { STV090x_P2_MODCODLSTD, 0xcc }, - { STV090x_P2_MODCODLSTE, 0xcc }, - { STV090x_P2_MODCODLSTF, 0xcf }, - { STV090x_P1_DISTXCTL, 0x22 }, - { STV090x_P1_F22TX, 0xc0 }, - { STV090x_P1_F22RX, 0xc0 }, - { STV090x_P1_DISRXCTL, 0x00 }, - { STV090x_P1_DMDCFGMD, 0xf9 }, - { STV090x_P1_DEMOD, 0x08 }, - { STV090x_P1_DMDCFG3, 0xc4 }, - { STV090x_P1_DMDTOM, 0x20 }, - { STV090x_P1_CARFREQ, 0xed }, - { STV090x_P1_LDT, 0xd0 }, - { STV090x_P1_LDT2, 0xb8 }, - { STV090x_P1_TMGCFG, 0xd2 }, - { STV090x_P1_TMGTHRISE, 0x20 }, - { STV090x_P1_TMGTHFALL, 0x00 }, - { STV090x_P1_SFRUPRATIO, 0xf0 }, - { STV090x_P1_SFRLOWRATIO, 0x70 }, - { STV090x_P1_TSCFGL, 0x20 }, - { STV090x_P1_FECSPY, 0x88 }, - { STV090x_P1_FSPYDATA, 0x3a }, - { STV090x_P1_FBERCPT4, 0x00 }, - { STV090x_P1_FSPYBER, 0x10 }, - { STV090x_P1_ERRCTRL1, 0x35 }, - { STV090x_P1_ERRCTRL2, 0xc1 }, - { STV090x_P1_CFRICFG, 0xf8 }, - { STV090x_P1_NOSCFG, 0x1c }, - { STV090x_P1_CORRELMANT, 0x70 }, - { STV090x_P1_CORRELABS, 0x88 }, - { STV090x_P1_AGC2O, 0x5b }, - { STV090x_P1_AGC2REF, 0x38 }, - { STV090x_P1_CARCFG, 0xe4 }, - { STV090x_P1_ACLC, 0x1A }, - { STV090x_P1_BCLC, 0x09 }, - { STV090x_P1_CARHDR, 0x08 }, - { STV090x_P1_KREFTMG, 0xc1 }, - { STV090x_P1_SFRSTEP, 0x58 }, - { STV090x_P1_TMGCFG2, 0x01 }, - { STV090x_P1_CAR2CFG, 0x26 }, - { STV090x_P1_BCLC2S2Q, 0x86 }, - { STV090x_P1_BCLC2S28, 0x86 }, - { STV090x_P1_SMAPCOEF7, 0x77 }, - { STV090x_P1_SMAPCOEF6, 0x85 }, - { STV090x_P1_SMAPCOEF5, 0x77 }, - { STV090x_P1_DMDCFG2, 0x3b }, - { STV090x_P1_MODCODLST0, 0xff }, - { STV090x_P1_MODCODLST1, 0xff }, - { STV090x_P1_MODCODLST2, 0xff }, - { STV090x_P1_MODCODLST3, 0xff }, - { STV090x_P1_MODCODLST4, 0xff }, - { STV090x_P1_MODCODLST5, 0xff }, - { STV090x_P1_MODCODLST6, 0xff }, - { STV090x_P1_MODCODLST7, 0xcc }, - { STV090x_P1_MODCODLST8, 0xcc }, - { STV090x_P1_MODCODLST9, 0xcc }, - { STV090x_P1_MODCODLSTA, 0xcc }, - { STV090x_P1_MODCODLSTB, 0xcc }, - { STV090x_P1_MODCODLSTC, 0xcc }, - { STV090x_P1_MODCODLSTD, 0xcc }, - { STV090x_P1_MODCODLSTE, 0xcc }, - { STV090x_P1_MODCODLSTF, 0xcf }, - { STV090x_GENCFG, 0x1d }, - { STV090x_NBITER_NF4, 0x37 }, - { STV090x_NBITER_NF5, 0x29 }, - { STV090x_NBITER_NF6, 0x37 }, - { STV090x_NBITER_NF7, 0x33 }, - { STV090x_NBITER_NF8, 0x31 }, - { STV090x_NBITER_NF9, 0x2f }, - { STV090x_NBITER_NF10, 0x39 }, - { STV090x_NBITER_NF11, 0x3a }, - { STV090x_NBITER_NF12, 0x29 }, - { STV090x_NBITER_NF13, 0x37 }, - { STV090x_NBITER_NF14, 0x33 }, - { STV090x_NBITER_NF15, 0x2f }, - { STV090x_NBITER_NF16, 0x39 }, - { STV090x_NBITER_NF17, 0x3a }, - { STV090x_NBITERNOERR, 0x04 }, - { STV090x_GAINLLR_NF4, 0x0C }, - { STV090x_GAINLLR_NF5, 0x0F }, - { STV090x_GAINLLR_NF6, 0x11 }, - { STV090x_GAINLLR_NF7, 0x14 }, - { STV090x_GAINLLR_NF8, 0x17 }, - { STV090x_GAINLLR_NF9, 0x19 }, - { STV090x_GAINLLR_NF10, 0x20 }, - { STV090x_GAINLLR_NF11, 0x21 }, - { STV090x_GAINLLR_NF12, 0x0D }, - { STV090x_GAINLLR_NF13, 0x0F }, - { STV090x_GAINLLR_NF14, 0x13 }, - { STV090x_GAINLLR_NF15, 0x1A }, - { STV090x_GAINLLR_NF16, 0x1F }, - { STV090x_GAINLLR_NF17, 0x21 }, - { STV090x_RCCFGH, 0x20 }, - { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ - { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ - { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ - { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */ -}; - -static struct stv090x_reg stv0903_initval[] = { - { STV090x_OUTCFG, 0x00 }, - { STV090x_AGCRF1CFG, 0x11 }, - { STV090x_STOPCLK1, 0x48 }, - { STV090x_STOPCLK2, 0x14 }, - { STV090x_TSTTNR1, 0x27 }, - { STV090x_TSTTNR2, 0x21 }, - { STV090x_P1_DISTXCTL, 0x22 }, - { STV090x_P1_F22TX, 0xc0 }, - { STV090x_P1_F22RX, 0xc0 }, - { STV090x_P1_DISRXCTL, 0x00 }, - { STV090x_P1_DMDCFGMD, 0xF9 }, - { STV090x_P1_DEMOD, 0x08 }, - { STV090x_P1_DMDCFG3, 0xc4 }, - { STV090x_P1_CARFREQ, 0xed }, - { STV090x_P1_TNRCFG2, 0x82 }, - { STV090x_P1_LDT, 0xd0 }, - { STV090x_P1_LDT2, 0xb8 }, - { STV090x_P1_TMGCFG, 0xd2 }, - { STV090x_P1_TMGTHRISE, 0x20 }, - { STV090x_P1_TMGTHFALL, 0x00 }, - { STV090x_P1_SFRUPRATIO, 0xf0 }, - { STV090x_P1_SFRLOWRATIO, 0x70 }, - { STV090x_P1_TSCFGL, 0x20 }, - { STV090x_P1_FECSPY, 0x88 }, - { STV090x_P1_FSPYDATA, 0x3a }, - { STV090x_P1_FBERCPT4, 0x00 }, - { STV090x_P1_FSPYBER, 0x10 }, - { STV090x_P1_ERRCTRL1, 0x35 }, - { STV090x_P1_ERRCTRL2, 0xc1 }, - { STV090x_P1_CFRICFG, 0xf8 }, - { STV090x_P1_NOSCFG, 0x1c }, - { STV090x_P1_DMDTOM, 0x20 }, - { STV090x_P1_CORRELMANT, 0x70 }, - { STV090x_P1_CORRELABS, 0x88 }, - { STV090x_P1_AGC2O, 0x5b }, - { STV090x_P1_AGC2REF, 0x38 }, - { STV090x_P1_CARCFG, 0xe4 }, - { STV090x_P1_ACLC, 0x1A }, - { STV090x_P1_BCLC, 0x09 }, - { STV090x_P1_CARHDR, 0x08 }, - { STV090x_P1_KREFTMG, 0xc1 }, - { STV090x_P1_SFRSTEP, 0x58 }, - { STV090x_P1_TMGCFG2, 0x01 }, - { STV090x_P1_CAR2CFG, 0x26 }, - { STV090x_P1_BCLC2S2Q, 0x86 }, - { STV090x_P1_BCLC2S28, 0x86 }, - { STV090x_P1_SMAPCOEF7, 0x77 }, - { STV090x_P1_SMAPCOEF6, 0x85 }, - { STV090x_P1_SMAPCOEF5, 0x77 }, - { STV090x_P1_DMDCFG2, 0x3b }, - { STV090x_P1_MODCODLST0, 0xff }, - { STV090x_P1_MODCODLST1, 0xff }, - { STV090x_P1_MODCODLST2, 0xff }, - { STV090x_P1_MODCODLST3, 0xff }, - { STV090x_P1_MODCODLST4, 0xff }, - { STV090x_P1_MODCODLST5, 0xff }, - { STV090x_P1_MODCODLST6, 0xff }, - { STV090x_P1_MODCODLST7, 0xcc }, - { STV090x_P1_MODCODLST8, 0xcc }, - { STV090x_P1_MODCODLST9, 0xcc }, - { STV090x_P1_MODCODLSTA, 0xcc }, - { STV090x_P1_MODCODLSTB, 0xcc }, - { STV090x_P1_MODCODLSTC, 0xcc }, - { STV090x_P1_MODCODLSTD, 0xcc }, - { STV090x_P1_MODCODLSTE, 0xcc }, - { STV090x_P1_MODCODLSTF, 0xcf }, - { STV090x_GENCFG, 0x1c }, - { STV090x_NBITER_NF4, 0x37 }, - { STV090x_NBITER_NF5, 0x29 }, - { STV090x_NBITER_NF6, 0x37 }, - { STV090x_NBITER_NF7, 0x33 }, - { STV090x_NBITER_NF8, 0x31 }, - { STV090x_NBITER_NF9, 0x2f }, - { STV090x_NBITER_NF10, 0x39 }, - { STV090x_NBITER_NF11, 0x3a }, - { STV090x_NBITER_NF12, 0x29 }, - { STV090x_NBITER_NF13, 0x37 }, - { STV090x_NBITER_NF14, 0x33 }, - { STV090x_NBITER_NF15, 0x2f }, - { STV090x_NBITER_NF16, 0x39 }, - { STV090x_NBITER_NF17, 0x3a }, - { STV090x_NBITERNOERR, 0x04 }, - { STV090x_GAINLLR_NF4, 0x0C }, - { STV090x_GAINLLR_NF5, 0x0F }, - { STV090x_GAINLLR_NF6, 0x11 }, - { STV090x_GAINLLR_NF7, 0x14 }, - { STV090x_GAINLLR_NF8, 0x17 }, - { STV090x_GAINLLR_NF9, 0x19 }, - { STV090x_GAINLLR_NF10, 0x20 }, - { STV090x_GAINLLR_NF11, 0x21 }, - { STV090x_GAINLLR_NF12, 0x0D }, - { STV090x_GAINLLR_NF13, 0x0F }, - { STV090x_GAINLLR_NF14, 0x13 }, - { STV090x_GAINLLR_NF15, 0x1A }, - { STV090x_GAINLLR_NF16, 0x1F }, - { STV090x_GAINLLR_NF17, 0x21 }, - { STV090x_RCCFGH, 0x20 }, - { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ - { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ -}; - -static struct stv090x_reg stv0900_cut20_val[] = { - - { STV090x_P2_DMDCFG3, 0xe8 }, - { STV090x_P2_DMDCFG4, 0x10 }, - { STV090x_P2_CARFREQ, 0x38 }, - { STV090x_P2_CARHDR, 0x20 }, - { STV090x_P2_KREFTMG, 0x5a }, - { STV090x_P2_SMAPCOEF7, 0x06 }, - { STV090x_P2_SMAPCOEF6, 0x00 }, - { STV090x_P2_SMAPCOEF5, 0x04 }, - { STV090x_P2_NOSCFG, 0x0c }, - { STV090x_P1_DMDCFG3, 0xe8 }, - { STV090x_P1_DMDCFG4, 0x10 }, - { STV090x_P1_CARFREQ, 0x38 }, - { STV090x_P1_CARHDR, 0x20 }, - { STV090x_P1_KREFTMG, 0x5a }, - { STV090x_P1_SMAPCOEF7, 0x06 }, - { STV090x_P1_SMAPCOEF6, 0x00 }, - { STV090x_P1_SMAPCOEF5, 0x04 }, - { STV090x_P1_NOSCFG, 0x0c }, - { STV090x_GAINLLR_NF4, 0x21 }, - { STV090x_GAINLLR_NF5, 0x21 }, - { STV090x_GAINLLR_NF6, 0x20 }, - { STV090x_GAINLLR_NF7, 0x1F }, - { STV090x_GAINLLR_NF8, 0x1E }, - { STV090x_GAINLLR_NF9, 0x1E }, - { STV090x_GAINLLR_NF10, 0x1D }, - { STV090x_GAINLLR_NF11, 0x1B }, - { STV090x_GAINLLR_NF12, 0x20 }, - { STV090x_GAINLLR_NF13, 0x20 }, - { STV090x_GAINLLR_NF14, 0x20 }, - { STV090x_GAINLLR_NF15, 0x20 }, - { STV090x_GAINLLR_NF16, 0x20 }, - { STV090x_GAINLLR_NF17, 0x21 }, -}; - -static struct stv090x_reg stv0903_cut20_val[] = { - { STV090x_P1_DMDCFG3, 0xe8 }, - { STV090x_P1_DMDCFG4, 0x10 }, - { STV090x_P1_CARFREQ, 0x38 }, - { STV090x_P1_CARHDR, 0x20 }, - { STV090x_P1_KREFTMG, 0x5a }, - { STV090x_P1_SMAPCOEF7, 0x06 }, - { STV090x_P1_SMAPCOEF6, 0x00 }, - { STV090x_P1_SMAPCOEF5, 0x04 }, - { STV090x_P1_NOSCFG, 0x0c }, - { STV090x_GAINLLR_NF4, 0x21 }, - { STV090x_GAINLLR_NF5, 0x21 }, - { STV090x_GAINLLR_NF6, 0x20 }, - { STV090x_GAINLLR_NF7, 0x1F }, - { STV090x_GAINLLR_NF8, 0x1E }, - { STV090x_GAINLLR_NF9, 0x1E }, - { STV090x_GAINLLR_NF10, 0x1D }, - { STV090x_GAINLLR_NF11, 0x1B }, - { STV090x_GAINLLR_NF12, 0x20 }, - { STV090x_GAINLLR_NF13, 0x20 }, - { STV090x_GAINLLR_NF14, 0x20 }, - { STV090x_GAINLLR_NF15, 0x20 }, - { STV090x_GAINLLR_NF16, 0x20 }, - { STV090x_GAINLLR_NF17, 0x21 } -}; - -/* Cut 2.0 Long Frame Tracking CR loop */ -static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = { - /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ - { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e }, - { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e }, - { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d }, - { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, - { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, - { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, - { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, - { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, - { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d }, - { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d }, - { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d }, - { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, - { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, - { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } -}; - -/* Cut 3.0 Long Frame Tracking CR loop */ -static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = { - /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ - { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b }, - { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, - { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, - { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, - { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, - { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, - { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, - { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, - { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 }, - { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a }, - { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a }, - { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b }, - { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b }, - { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b } -}; - -/* Cut 2.0 Long Frame Tracking CR Loop */ -static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = { - /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ - { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c }, - { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c }, - { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, - { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, - { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, - { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, - { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, - { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, - { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, - { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, - { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c } -}; - -/* Cut 3.0 Long Frame Tracking CR Loop */ -static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = { - /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ - { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a }, - { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a }, - { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, - { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, - { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, - { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, - { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, - { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, - { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, - { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, - { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } -}; - -static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = { - /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ - { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e }, - { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e }, - { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e } -}; - -static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = { - /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ - { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b }, - { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b }, - { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b } -}; - -/* Cut 2.0 Short Frame Tracking CR Loop */ -static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { - /* MODCOD 2M 5M 10M 20M 30M */ - { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d }, - { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c }, - { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }, - { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d } -}; - -/* Cut 3.0 Short Frame Tracking CR Loop */ -static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { - /* MODCOD 2M 5M 10M 20M 30M */ - { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, - { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, - { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, - { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A } -}; - -static inline s32 comp2(s32 __x, s32 __width) -{ - if (__width == 32) - return __x; - else - return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x; -} - -static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) -{ - const struct stv090x_config *config = state->config; - int ret; - - u8 b0[] = { reg >> 8, reg & 0xff }; - u8 buf; - - struct i2c_msg msg[] = { - { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, - { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } - }; - - ret = i2c_transfer(state->i2c, msg, 2); - if (ret != 2) { - if (ret != -ERESTARTSYS) - dprintk(FE_ERROR, 1, - "Read error, Reg=[0x%02x], Status=%d", - reg, ret); - - return ret < 0 ? ret : -EREMOTEIO; - } - if (unlikely(*state->verbose >= FE_DEBUGREG)) - dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x", - reg, buf); - - return (unsigned int) buf; -} - -static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) -{ - const struct stv090x_config *config = state->config; - int ret; - u8 buf[2 + count]; - struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; - - buf[0] = reg >> 8; - buf[1] = reg & 0xff; - memcpy(&buf[2], data, count); - - if (unlikely(*state->verbose >= FE_DEBUGREG)) { - int i; - - printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); - for (i = 0; i < count; i++) - printk(" %02x", data[i]); - printk("\n"); - } - - ret = i2c_transfer(state->i2c, &i2c_msg, 1); - if (ret != 1) { - if (ret != -ERESTARTSYS) - dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", - reg, data[0], count, ret); - return ret < 0 ? ret : -EREMOTEIO; - } - - return 0; -} - -static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) -{ - return stv090x_write_regs(state, reg, &data, 1); -} - -static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) -{ - u32 reg; - - /* - * NOTE! A lock is used as a FSM to control the state in which - * access is serialized between two tuners on the same demod. - * This has nothing to do with a lock to protect a critical section - * which may in some other cases be confused with protecting I/O - * access to the demodulator gate. - * In case of any error, the lock is unlocked and exit within the - * relevant operations themselves. - */ - if (enable) { - if (state->config->tuner_i2c_lock) - state->config->tuner_i2c_lock(&state->frontend, 1); - else - mutex_lock(&state->internal->tuner_lock); - } - - reg = STV090x_READ_DEMOD(state, I2CRPT); - if (enable) { - dprintk(FE_DEBUG, 1, "Enable Gate"); - STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); - reg = 0xc8; - if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) - goto err; - - } else { - dprintk(FE_DEBUG, 1, "Disable Gate"); - STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); - reg = 0x4a; - if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) - goto err; - } - - if (!enable) { - if (state->config->tuner_i2c_lock) - state->config->tuner_i2c_lock(&state->frontend, 0); - else - mutex_unlock(&state->internal->tuner_lock); - } - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - if (state->config->tuner_i2c_lock) - state->config->tuner_i2c_lock(&state->frontend, 0); - else - mutex_unlock(&state->internal->tuner_lock); - return -1; -} - -static void stv090x_get_lock_tmg(struct stv090x_state *state) -{ - switch (state->algo) { - case STV090x_BLIND_SEARCH: - dprintk(FE_DEBUG, 1, "Blind Search"); - if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ - state->DemodTimeout = 1500; - state->FecTimeout = 400; - } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ - state->DemodTimeout = 1000; - state->FecTimeout = 300; - } else { /*SR >20Msps*/ - state->DemodTimeout = 700; - state->FecTimeout = 100; - } - break; - - case STV090x_COLD_SEARCH: - case STV090x_WARM_SEARCH: - default: - dprintk(FE_DEBUG, 1, "Normal Search"); - if (state->srate <= 1000000) { /*SR <=1Msps*/ - state->DemodTimeout = 4500; - state->FecTimeout = 1700; - } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ - state->DemodTimeout = 2500; - state->FecTimeout = 1100; - } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ - state->DemodTimeout = 1000; - state->FecTimeout = 550; - } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ - state->DemodTimeout = 700; - state->FecTimeout = 250; - } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ - state->DemodTimeout = 400; - state->FecTimeout = 130; - } else { /*SR >20Msps*/ - state->DemodTimeout = 300; - state->FecTimeout = 100; - } - break; - } - - if (state->algo == STV090x_WARM_SEARCH) - state->DemodTimeout /= 2; -} - -static int stv090x_set_srate(struct stv090x_state *state, u32 srate) -{ - u32 sym; - - if (srate > 60000000) { - sym = (srate << 4); /* SR * 2^16 / master_clk */ - sym /= (state->internal->mclk >> 12); - } else if (srate > 6000000) { - sym = (srate << 6); - sym /= (state->internal->mclk >> 10); - } else { - sym = (srate << 9); - sym /= (state->internal->mclk >> 7); - } - - if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ - goto err; - if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ - goto err; - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) -{ - u32 sym; - - srate = 105 * (srate / 100); - if (srate > 60000000) { - sym = (srate << 4); /* SR * 2^16 / master_clk */ - sym /= (state->internal->mclk >> 12); - } else if (srate > 6000000) { - sym = (srate << 6); - sym /= (state->internal->mclk >> 10); - } else { - sym = (srate << 9); - sym /= (state->internal->mclk >> 7); - } - - if (sym < 0x7fff) { - if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ - goto err; - if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ - goto err; - } else { - if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ - goto err; - if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ - goto err; - } - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) -{ - u32 sym; - - srate = 95 * (srate / 100); - if (srate > 60000000) { - sym = (srate << 4); /* SR * 2^16 / master_clk */ - sym /= (state->internal->mclk >> 12); - } else if (srate > 6000000) { - sym = (srate << 6); - sym /= (state->internal->mclk >> 10); - } else { - sym = (srate << 9); - sym /= (state->internal->mclk >> 7); - } - - if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ - goto err; - if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ - goto err; - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff) -{ - u32 ro; - - switch (rolloff) { - case STV090x_RO_20: - ro = 20; - break; - case STV090x_RO_25: - ro = 25; - break; - case STV090x_RO_35: - default: - ro = 35; - break; - } - - return srate + (srate * ro) / 100; -} - -static int stv090x_set_vit_thacq(struct stv090x_state *state) -{ - if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) - goto err; - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_set_vit_thtracq(struct stv090x_state *state) -{ - if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) - goto err; - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_set_viterbi(struct stv090x_state *state) -{ - switch (state->search_mode) { - case STV090x_SEARCH_AUTO: - if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ - goto err; - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ - goto err; - break; - case STV090x_SEARCH_DVBS1: - if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ - goto err; - switch (state->fec) { - case STV090x_PR12: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) - goto err; - break; - - case STV090x_PR23: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) - goto err; - break; - - case STV090x_PR34: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) - goto err; - break; - - case STV090x_PR56: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) - goto err; - break; - - case STV090x_PR78: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) - goto err; - break; - - default: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ - goto err; - break; - } - break; - case STV090x_SEARCH_DSS: - if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) - goto err; - switch (state->fec) { - case STV090x_PR12: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) - goto err; - break; - - case STV090x_PR23: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) - goto err; - break; - - case STV090x_PR67: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) - goto err; - break; - - default: - if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ - goto err; - break; - } - break; - default: - break; - } - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_stop_modcod(struct stv090x_state *state) -{ - if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) - goto err; - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_activate_modcod(struct stv090x_state *state) -{ - if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) - goto err; - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_activate_modcod_single(struct stv090x_state *state) -{ - - if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) - goto err; - - return 0; - -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) -{ - u32 reg; - - switch (state->demod) { - case STV090x_DEMODULATOR_0: - mutex_lock(&state->internal->demod_lock); - reg = stv090x_read_reg(state, STV090x_STOPCLK2); - STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); - if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; - mutex_unlock(&state->internal->demod_lock); - break; - - case STV090x_DEMODULATOR_1: - mutex_lock(&state->internal->demod_lock); - reg = stv090x_read_reg(state, STV090x_STOPCLK2); - STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); - if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; - mutex_unlock(&state->internal->demod_lock); - break; - - default: - dprintk(FE_ERROR, 1, "Wrong demodulator!"); - break; - } - return 0; -err: - mutex_unlock(&state->internal->demod_lock); - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_dvbs_track_crl(struct stv090x_state *state) -{ - if (state->internal->dev_ver >= 0x30) { - /* Set ACLC BCLC optimised value vs SR */ - if (state->srate >= 15000000) { - if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) - goto err; - } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { - if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) - goto err; - } else if (state->srate < 7000000) { - if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) - goto err; - } - - } else { - /* Cut 2.0 */ - if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) - goto err; - } - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_delivery_search(struct stv090x_state *state) -{ - u32 reg; - - switch (state->search_mode) { - case STV090x_SEARCH_DVBS1: - case STV090x_SEARCH_DSS: - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - - /* Activate Viterbi decoder in legacy search, - * do not use FRESVIT1, might impact VITERBI2 - */ - if (stv090x_vitclk_ctl(state, 0) < 0) - goto err; - - if (stv090x_dvbs_track_crl(state) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ - goto err; - - if (stv090x_set_vit_thacq(state) < 0) - goto err; - if (stv090x_set_viterbi(state) < 0) - goto err; - break; - - case STV090x_SEARCH_DVBS2: - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - - if (stv090x_vitclk_ctl(state, 1) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ - goto err; - if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) - goto err; - - if (state->internal->dev_ver <= 0x20) { - /* enable S2 carrier loop */ - if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) - goto err; - } else { - /* > Cut 3: Stop carrier 3 */ - if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) - goto err; - } - - if (state->demod_mode != STV090x_SINGLE) { - /* Cut 2: enable link during search */ - if (stv090x_activate_modcod(state) < 0) - goto err; - } else { - /* Single demodulator - * Authorize SHORT and LONG frames, - * QPSK, 8PSK, 16APSK and 32APSK - */ - if (stv090x_activate_modcod_single(state) < 0) - goto err; - } - - if (stv090x_set_vit_thtracq(state) < 0) - goto err; - break; - - case STV090x_SEARCH_AUTO: - default: - /* enable DVB-S2 and DVB-S2 in Auto MODE */ - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - - if (stv090x_vitclk_ctl(state, 0) < 0) - goto err; - - if (stv090x_dvbs_track_crl(state) < 0) - goto err; - - if (state->internal->dev_ver <= 0x20) { - /* enable S2 carrier loop */ - if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) - goto err; - } else { - /* > Cut 3: Stop carrier 3 */ - if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) - goto err; - } - - if (state->demod_mode != STV090x_SINGLE) { - /* Cut 2: enable link during search */ - if (stv090x_activate_modcod(state) < 0) - goto err; - } else { - /* Single demodulator - * Authorize SHORT and LONG frames, - * QPSK, 8PSK, 16APSK and 32APSK - */ - if (stv090x_activate_modcod_single(state) < 0) - goto err; - } - - if (stv090x_set_vit_thacq(state) < 0) - goto err; - - if (stv090x_set_viterbi(state) < 0) - goto err; - break; - } - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_start_search(struct stv090x_state *state) -{ - u32 reg, freq_abs; - s16 freq; - - /* Reset demodulator */ - reg = STV090x_READ_DEMOD(state, DMDISTATE); - STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); - if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) - goto err; - - if (state->internal->dev_ver <= 0x20) { - if (state->srate <= 5000000) { - if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) - goto err; - - /*enlarge the timing bandwidth for Low SR*/ - if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) - goto err; - } else { - /* If the symbol rate is >5 Msps - Set The carrier search up and low to auto mode */ - if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) - goto err; - /*reduce the timing bandwidth for high SR*/ - if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) - goto err; - } - } else { - /* >= Cut 3 */ - if (state->srate <= 5000000) { - /* enlarge the timing bandwidth for Low SR */ - STV090x_WRITE_DEMOD(state, RTCS2, 0x68); - } else { - /* reduce timing bandwidth for high SR */ - STV090x_WRITE_DEMOD(state, RTCS2, 0x44); - } - - /* Set CFR min and max to manual mode */ - STV090x_WRITE_DEMOD(state, CARCFG, 0x46); - - if (state->algo == STV090x_WARM_SEARCH) { - /* WARM Start - * CFR min = -1MHz, - * CFR max = +1MHz - */ - freq_abs = 1000 << 16; - freq_abs /= (state->internal->mclk / 1000); - freq = (s16) freq_abs; - } else { - /* COLD Start - * CFR min =- (SearchRange / 2 + 600KHz) - * CFR max = +(SearchRange / 2 + 600KHz) - * (600KHz for the tuner step size) - */ - freq_abs = (state->search_range / 2000) + 600; - freq_abs = freq_abs << 16; - freq_abs /= (state->internal->mclk / 1000); - freq = (s16) freq_abs; - } - - if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) - goto err; - - freq *= -1; - - if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) - goto err; - - } - - if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) - goto err; - - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) - goto err; - - if ((state->search_mode == STV090x_SEARCH_DVBS1) || - (state->search_mode == STV090x_SEARCH_DSS) || - (state->search_mode == STV090x_SEARCH_AUTO)) { - - if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) - goto err; - } - } - - if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) - goto err; - - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); - STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - reg = STV090x_READ_DEMOD(state, DMDCFG2); - STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); - if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) - goto err; - - if (state->internal->dev_ver >= 0x20) { - /*Frequency offset detector setting*/ - if (state->srate < 2000000) { - if (state->internal->dev_ver <= 0x20) { - /* Cut 2 */ - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) - goto err; - } else { - /* Cut 3 */ - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) - goto err; - } - if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) - goto err; - } else if (state->srate < 10000000) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) - goto err; - } else { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) - goto err; - } - } else { - if (state->srate < 10000000) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) - goto err; - } else { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) - goto err; - } - } - - switch (state->algo) { - case STV090x_WARM_SEARCH: - /* The symbol rate and the exact - * carrier Frequency are known - */ - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) - goto err; - break; - - case STV090x_COLD_SEARCH: - /* The symbol rate is known */ - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) - goto err; - break; - - default: - break; - } - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_get_agc2_min_level(struct stv090x_state *state) -{ - u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; - s32 i, j, steps, dir; - - if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) - goto err; - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); - STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ - goto err; - if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ - goto err; - if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ - goto err; - if (stv090x_set_srate(state, 1000000) < 0) - goto err; - - steps = state->search_range / 1000000; - if (steps <= 0) - steps = 1; - - dir = 1; - freq_step = (1000000 * 256) / (state->internal->mclk / 256); - freq_init = 0; - - for (i = 0; i < steps; i++) { - if (dir > 0) - freq_init = freq_init + (freq_step * i); - else - freq_init = freq_init - (freq_step * i); - - dir *= -1; - - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ - goto err; - msleep(10); - - agc2 = 0; - for (j = 0; j < 10; j++) { - agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | - STV090x_READ_DEMOD(state, AGC2I0); - } - agc2 /= 10; - if (agc2 < agc2_min) - agc2_min = agc2; - } - - return agc2_min; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) -{ - u8 r3, r2, r1, r0; - s32 srate, int_1, int_2, tmp_1, tmp_2; - - r3 = STV090x_READ_DEMOD(state, SFR3); - r2 = STV090x_READ_DEMOD(state, SFR2); - r1 = STV090x_READ_DEMOD(state, SFR1); - r0 = STV090x_READ_DEMOD(state, SFR0); - - srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0); - - int_1 = clk >> 16; - int_2 = srate >> 16; - - tmp_1 = clk % 0x10000; - tmp_2 = srate % 0x10000; - - srate = (int_1 * int_2) + - ((int_1 * tmp_2) >> 16) + - ((int_2 * tmp_1) >> 16); - - return srate; -} - -static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) -{ - struct dvb_frontend *fe = &state->frontend; - - int tmg_lock = 0, i; - s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; - u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; - u32 agc2th; - - if (state->internal->dev_ver >= 0x30) - agc2th = 0x2e00; - else - agc2th = 0x1f00; - - reg = STV090x_READ_DEMOD(state, DMDISTATE); - STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ - if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) - goto err; - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); - STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) - goto err; - - if (state->internal->dev_ver >= 0x30) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) - goto err; - - } else if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) - goto err; - } - - if (state->srate <= 2000000) - car_step = 1000; - else if (state->srate <= 5000000) - car_step = 2000; - else if (state->srate <= 12000000) - car_step = 3000; - else - car_step = 5000; - - steps = -1 + ((state->search_range / 1000) / car_step); - steps /= 2; - steps = (2 * steps) + 1; - if (steps < 0) - steps = 1; - else if (steps > 10) { - steps = 11; - car_step = (state->search_range / 1000) / 10; - } - cur_step = 0; - dir = 1; - freq = state->frequency; - - while ((!tmg_lock) && (cur_step < steps)) { - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) - goto err; - /* trigger acquisition */ - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) - goto err; - msleep(50); - for (i = 0; i < 10; i++) { - reg = STV090x_READ_DEMOD(state, DSTATUS); - if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) - tmg_cpt++; - agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | - STV090x_READ_DEMOD(state, AGC2I0); - } - agc2 /= 10; - srate_coarse = stv090x_get_srate(state, state->internal->mclk); - cur_step++; - dir *= -1; - if ((tmg_cpt >= 5) && (agc2 < agc2th) && - (srate_coarse < 50000000) && (srate_coarse > 850000)) - tmg_lock = 1; - else if (cur_step < steps) { - if (dir > 0) - freq += cur_step * car_step; - else - freq -= cur_step * car_step; - - /* Setup tuner */ - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_set_frequency) { - if (state->config->tuner_set_frequency(fe, freq) < 0) - goto err_gateoff; - } - - if (state->config->tuner_set_bandwidth) { - if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - msleep(50); - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_get_status) { - if (state->config->tuner_get_status(fe, ®) < 0) - goto err_gateoff; - } - - if (reg) - dprintk(FE_DEBUG, 1, "Tuner phase locked"); - else - dprintk(FE_DEBUG, 1, "Tuner unlocked"); - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - } - } - if (!tmg_lock) - srate_coarse = 0; - else - srate_coarse = stv090x_get_srate(state, state->internal->mclk); - - return srate_coarse; - -err_gateoff: - stv090x_i2c_gate_ctrl(state, 0); -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static u32 stv090x_srate_srch_fine(struct stv090x_state *state) -{ - u32 srate_coarse, freq_coarse, sym, reg; - - srate_coarse = stv090x_get_srate(state, state->internal->mclk); - freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; - freq_coarse |= STV090x_READ_DEMOD(state, CFR1); - sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ - - if (sym < state->srate) - srate_coarse = 0; - else { - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ - goto err; - if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) - goto err; - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) - goto err; - - if (state->internal->dev_ver >= 0x30) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) - goto err; - } else if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) - goto err; - } - - if (srate_coarse > 3000000) { - sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ - sym = (sym / 1000) * 65536; - sym /= (state->internal->mclk / 1000); - if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) - goto err; - sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */ - sym = (sym / 1000) * 65536; - sym /= (state->internal->mclk / 1000); - if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) - goto err; - sym = (srate_coarse / 1000) * 65536; - sym /= (state->internal->mclk / 1000); - if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) - goto err; - } else { - sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ - sym = (sym / 100) * 65536; - sym /= (state->internal->mclk / 100); - if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) - goto err; - sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */ - sym = (sym / 100) * 65536; - sym /= (state->internal->mclk / 100); - if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) - goto err; - sym = (srate_coarse / 100) * 65536; - sym /= (state->internal->mclk / 100); - if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) - goto err; - } - if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ - goto err; - } - - return srate_coarse; - -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) -{ - s32 timer = 0, lock = 0; - u32 reg; - u8 stat; - - while ((timer < timeout) && (!lock)) { - reg = STV090x_READ_DEMOD(state, DMDSTATE); - stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); - - switch (stat) { - case 0: /* searching */ - case 1: /* first PLH detected */ - default: - dprintk(FE_DEBUG, 1, "Demodulator searching .."); - lock = 0; - break; - case 2: /* DVB-S2 mode */ - case 3: /* DVB-S1/legacy mode */ - reg = STV090x_READ_DEMOD(state, DSTATUS); - lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); - break; - } - - if (!lock) - msleep(10); - else - dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK"); - - timer += 10; - } - return lock; -} - -static int stv090x_blind_search(struct stv090x_state *state) -{ - u32 agc2, reg, srate_coarse; - s32 cpt_fail, agc2_ovflw, i; - u8 k_ref, k_max, k_min; - int coarse_fail = 0; - int lock; - - k_max = 110; - k_min = 10; - - agc2 = stv090x_get_agc2_min_level(state); - - if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { - lock = 0; - } else { - - if (state->internal->dev_ver <= 0x20) { - if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) - goto err; - } else { - /* > Cut 3 */ - if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) - goto err; - } - - if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) - goto err; - - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ - goto err; - } - - k_ref = k_max; - do { - if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) - goto err; - if (stv090x_srate_srch_coarse(state) != 0) { - srate_coarse = stv090x_srate_srch_fine(state); - if (srate_coarse != 0) { - stv090x_get_lock_tmg(state); - lock = stv090x_get_dmdlock(state, - state->DemodTimeout); - } else { - lock = 0; - } - } else { - cpt_fail = 0; - agc2_ovflw = 0; - for (i = 0; i < 10; i++) { - agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | - STV090x_READ_DEMOD(state, AGC2I0); - if (agc2 >= 0xff00) - agc2_ovflw++; - reg = STV090x_READ_DEMOD(state, DSTATUS2); - if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && - (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) - - cpt_fail++; - } - if ((cpt_fail > 7) || (agc2_ovflw > 7)) - coarse_fail = 1; - - lock = 0; - } - k_ref -= 20; - } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); - } - - return lock; - -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_chk_tmg(struct stv090x_state *state) -{ - u32 reg; - s32 tmg_cpt = 0, i; - u8 freq, tmg_thh, tmg_thl; - int tmg_lock = 0; - - freq = STV090x_READ_DEMOD(state, CARFREQ); - tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); - tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); - if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) - goto err; - - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ - goto err; - msleep(10); - - for (i = 0; i < 10; i++) { - reg = STV090x_READ_DEMOD(state, DSTATUS); - if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) - tmg_cpt++; - msleep(1); - } - if (tmg_cpt >= 3) - tmg_lock = 1; - - if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ - goto err; - if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ - goto err; - - if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) - goto err; - - return tmg_lock; - -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) -{ - struct dvb_frontend *fe = &state->frontend; - - u32 reg; - s32 car_step, steps, cur_step, dir, freq, timeout_lock; - int lock = 0; - - if (state->srate >= 10000000) - timeout_lock = timeout_dmd / 3; - else - timeout_lock = timeout_dmd / 2; - - lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ - if (!lock) { - if (state->srate >= 10000000) { - if (stv090x_chk_tmg(state)) { - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) - goto err; - lock = stv090x_get_dmdlock(state, timeout_dmd); - } else { - lock = 0; - } - } else { - if (state->srate <= 4000000) - car_step = 1000; - else if (state->srate <= 7000000) - car_step = 2000; - else if (state->srate <= 10000000) - car_step = 3000; - else - car_step = 5000; - - steps = (state->search_range / 1000) / car_step; - steps /= 2; - steps = 2 * (steps + 1); - if (steps < 0) - steps = 2; - else if (steps > 12) - steps = 12; - - cur_step = 1; - dir = 1; - - if (!lock) { - freq = state->frequency; - state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; - while ((cur_step <= steps) && (!lock)) { - if (dir > 0) - freq += cur_step * car_step; - else - freq -= cur_step * car_step; - - /* Setup tuner */ - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_set_frequency) { - if (state->config->tuner_set_frequency(fe, freq) < 0) - goto err_gateoff; - } - - if (state->config->tuner_set_bandwidth) { - if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - msleep(50); - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_get_status) { - if (state->config->tuner_get_status(fe, ®) < 0) - goto err_gateoff; - } - - if (reg) - dprintk(FE_DEBUG, 1, "Tuner phase locked"); - else - dprintk(FE_DEBUG, 1, "Tuner unlocked"); - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); - if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) - goto err; - lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); - - dir *= -1; - cur_step++; - } - } - } - } - - return lock; - -err_gateoff: - stv090x_i2c_gate_ctrl(state, 0); -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) -{ - s32 timeout, inc, steps_max, srate, car_max; - - srate = state->srate; - car_max = state->search_range / 1000; - car_max += car_max / 10; - car_max = 65536 * (car_max / 2); - car_max /= (state->internal->mclk / 1000); - - if (car_max > 0x4000) - car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */ - - inc = srate; - inc /= state->internal->mclk / 1000; - inc *= 256; - inc *= 256; - inc /= 1000; - - switch (state->search_mode) { - case STV090x_SEARCH_DVBS1: - case STV090x_SEARCH_DSS: - inc *= 3; /* freq step = 3% of srate */ - timeout = 20; - break; - - case STV090x_SEARCH_DVBS2: - inc *= 4; - timeout = 25; - break; - - case STV090x_SEARCH_AUTO: - default: - inc *= 3; - timeout = 25; - break; - } - inc /= 100; - if ((inc > car_max) || (inc < 0)) - inc = car_max / 2; /* increment <= 1/8 Mclk */ - - timeout *= 27500; /* 27.5 Msps reference */ - if (srate > 0) - timeout /= (srate / 1000); - - if ((timeout > 100) || (timeout < 0)) - timeout = 100; - - steps_max = (car_max / inc) + 1; /* min steps = 3 */ - if ((steps_max > 100) || (steps_max < 0)) { - steps_max = 100; /* max steps <= 100 */ - inc = car_max / steps_max; - } - *freq_inc = inc; - *timeout_sw = timeout; - *steps = steps_max; - - return 0; -} - -static int stv090x_chk_signal(struct stv090x_state *state) -{ - s32 offst_car, agc2, car_max; - int no_signal; - - offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; - offst_car |= STV090x_READ_DEMOD(state, CFR1); - offst_car = comp2(offst_car, 16); - - agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; - agc2 |= STV090x_READ_DEMOD(state, AGC2I0); - car_max = state->search_range / 1000; - - car_max += (car_max / 10); /* 10% margin */ - car_max = (65536 * car_max / 2); - car_max /= state->internal->mclk / 1000; - - if (car_max > 0x4000) - car_max = 0x4000; - - if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) { - no_signal = 1; - dprintk(FE_DEBUG, 1, "No Signal"); - } else { - no_signal = 0; - dprintk(FE_DEBUG, 1, "Found Signal"); - } - - return no_signal; -} - -static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) -{ - int no_signal, lock = 0; - s32 cpt_step = 0, offst_freq, car_max; - u32 reg; - - car_max = state->search_range / 1000; - car_max += (car_max / 10); - car_max = (65536 * car_max / 2); - car_max /= (state->internal->mclk / 1000); - if (car_max > 0x4000) - car_max = 0x4000; - - if (zigzag) - offst_freq = 0; - else - offst_freq = -car_max + inc; - - do { - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) - goto err; - - reg = STV090x_READ_DEMOD(state, PDELCTRL1); - STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ - if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) - goto err; - - if (zigzag) { - if (offst_freq >= 0) - offst_freq = -offst_freq - 2 * inc; - else - offst_freq = -offst_freq; - } else { - offst_freq += 2 * inc; - } - - cpt_step++; - - lock = stv090x_get_dmdlock(state, timeout); - no_signal = stv090x_chk_signal(state); - - } while ((!lock) && - (!no_signal) && - ((offst_freq - inc) < car_max) && - ((offst_freq + inc) > -car_max) && - (cpt_step < steps_max)); - - reg = STV090x_READ_DEMOD(state, PDELCTRL1); - STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) - goto err; - - return lock; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_sw_algo(struct stv090x_state *state) -{ - int no_signal, zigzag, lock = 0; - u32 reg; - - s32 dvbs2_fly_wheel; - s32 inc, timeout_step, trials, steps_max; - - /* get params */ - stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); - - switch (state->search_mode) { - case STV090x_SEARCH_DVBS1: - case STV090x_SEARCH_DSS: - /* accelerate the frequency detector */ - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) - goto err; - } - - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) - goto err; - zigzag = 0; - break; - - case STV090x_SEARCH_DVBS2: - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) - goto err; - } - - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) - goto err; - zigzag = 1; - break; - - case STV090x_SEARCH_AUTO: - default: - /* accelerate the frequency detector */ - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) - goto err; - } - - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) - goto err; - zigzag = 0; - break; - } - - trials = 0; - do { - lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); - no_signal = stv090x_chk_signal(state); - trials++; - - /*run the SW search 2 times maximum*/ - if (lock || no_signal || (trials == 2)) { - /*Check if the demod is not losing lock in DVBS2*/ - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) - goto err; - } - - reg = STV090x_READ_DEMOD(state, DMDSTATE); - if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { - /*Check if the demod is not losing lock in DVBS2*/ - msleep(timeout_step); - reg = STV090x_READ_DEMOD(state, DMDFLYW); - dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); - if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */ - msleep(timeout_step); - reg = STV090x_READ_DEMOD(state, DMDFLYW); - dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); - } - if (dvbs2_fly_wheel < 0xd) { - /*FALSE lock, The demod is losing lock */ - lock = 0; - if (trials < 2) { - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) - goto err; - } - - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) - goto err; - } - } - } - } - } while ((!lock) && (trials < 2) && (!no_signal)); - - return lock; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) -{ - u32 reg; - enum stv090x_delsys delsys; - - reg = STV090x_READ_DEMOD(state, DMDSTATE); - if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) - delsys = STV090x_DVBS2; - else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { - reg = STV090x_READ_DEMOD(state, FECM); - if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) - delsys = STV090x_DSS; - else - delsys = STV090x_DVBS1; - } else { - delsys = STV090x_ERROR; - } - - return delsys; -} - -/* in Hz */ -static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) -{ - s32 derot, int_1, int_2, tmp_1, tmp_2; - - derot = STV090x_READ_DEMOD(state, CFR2) << 16; - derot |= STV090x_READ_DEMOD(state, CFR1) << 8; - derot |= STV090x_READ_DEMOD(state, CFR0); - - derot = comp2(derot, 24); - int_1 = mclk >> 12; - int_2 = derot >> 12; - - /* carrier_frequency = MasterClock * Reg / 2^24 */ - tmp_1 = mclk % 0x1000; - tmp_2 = derot % 0x1000; - - derot = (int_1 * int_2) + - ((int_1 * tmp_2) >> 12) + - ((int_2 * tmp_1) >> 12); - - return derot; -} - -static int stv090x_get_viterbi(struct stv090x_state *state) -{ - u32 reg, rate; - - reg = STV090x_READ_DEMOD(state, VITCURPUN); - rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); - - switch (rate) { - case 13: - state->fec = STV090x_PR12; - break; - - case 18: - state->fec = STV090x_PR23; - break; - - case 21: - state->fec = STV090x_PR34; - break; - - case 24: - state->fec = STV090x_PR56; - break; - - case 25: - state->fec = STV090x_PR67; - break; - - case 26: - state->fec = STV090x_PR78; - break; - - default: - state->fec = STV090x_PRERR; - break; - } - - return 0; -} - -static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) -{ - struct dvb_frontend *fe = &state->frontend; - - u8 tmg; - u32 reg; - s32 i = 0, offst_freq; - - msleep(5); - - if (state->algo == STV090x_BLIND_SEARCH) { - tmg = STV090x_READ_DEMOD(state, TMGREG2); - STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); - while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) { - tmg = STV090x_READ_DEMOD(state, TMGREG2); - msleep(5); - i += 5; - } - } - state->delsys = stv090x_get_std(state); - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_get_frequency) { - if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; - state->frequency += offst_freq; - - if (stv090x_get_viterbi(state) < 0) - goto err; - - reg = STV090x_READ_DEMOD(state, DMDMODCOD); - state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); - state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; - state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; - reg = STV090x_READ_DEMOD(state, TMGOBS); - state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); - reg = STV090x_READ_DEMOD(state, FECM); - state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); - - if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_get_frequency) { - if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) - return STV090x_RANGEOK; - else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) - return STV090x_RANGEOK; - else - return STV090x_OUTOFRANGE; /* Out of Range */ - } else { - if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) - return STV090x_RANGEOK; - else - return STV090x_OUTOFRANGE; - } - - return STV090x_OUTOFRANGE; - -err_gateoff: - stv090x_i2c_gate_ctrl(state, 0); -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) -{ - s32 offst_tmg; - - offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; - offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; - offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); - - offst_tmg = comp2(offst_tmg, 24); /* 2's complement */ - if (!offst_tmg) - offst_tmg = 1; - - offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg); - offst_tmg /= 320; - - return offst_tmg; -} - -static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) -{ - u8 aclc = 0x29; - s32 i; - struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low; - - if (state->internal->dev_ver == 0x20) { - car_loop = stv090x_s2_crl_cut20; - car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20; - car_loop_apsk_low = stv090x_s2_apsk_crl_cut20; - } else { - /* >= Cut 3 */ - car_loop = stv090x_s2_crl_cut30; - car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30; - car_loop_apsk_low = stv090x_s2_apsk_crl_cut30; - } - - if (modcod < STV090x_QPSK_12) { - i = 0; - while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod)) - i++; - - if (i >= 3) - i = 2; - - } else { - i = 0; - while ((i < 14) && (modcod != car_loop[i].modcod)) - i++; - - if (i >= 14) { - i = 0; - while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod)) - i++; - - if (i >= 11) - i = 10; - } - } - - if (modcod <= STV090x_QPSK_25) { - if (pilots) { - if (state->srate <= 3000000) - aclc = car_loop_qpsk_low[i].crl_pilots_on_2; - else if (state->srate <= 7000000) - aclc = car_loop_qpsk_low[i].crl_pilots_on_5; - else if (state->srate <= 15000000) - aclc = car_loop_qpsk_low[i].crl_pilots_on_10; - else if (state->srate <= 25000000) - aclc = car_loop_qpsk_low[i].crl_pilots_on_20; - else - aclc = car_loop_qpsk_low[i].crl_pilots_on_30; - } else { - if (state->srate <= 3000000) - aclc = car_loop_qpsk_low[i].crl_pilots_off_2; - else if (state->srate <= 7000000) - aclc = car_loop_qpsk_low[i].crl_pilots_off_5; - else if (state->srate <= 15000000) - aclc = car_loop_qpsk_low[i].crl_pilots_off_10; - else if (state->srate <= 25000000) - aclc = car_loop_qpsk_low[i].crl_pilots_off_20; - else - aclc = car_loop_qpsk_low[i].crl_pilots_off_30; - } - - } else if (modcod <= STV090x_8PSK_910) { - if (pilots) { - if (state->srate <= 3000000) - aclc = car_loop[i].crl_pilots_on_2; - else if (state->srate <= 7000000) - aclc = car_loop[i].crl_pilots_on_5; - else if (state->srate <= 15000000) - aclc = car_loop[i].crl_pilots_on_10; - else if (state->srate <= 25000000) - aclc = car_loop[i].crl_pilots_on_20; - else - aclc = car_loop[i].crl_pilots_on_30; - } else { - if (state->srate <= 3000000) - aclc = car_loop[i].crl_pilots_off_2; - else if (state->srate <= 7000000) - aclc = car_loop[i].crl_pilots_off_5; - else if (state->srate <= 15000000) - aclc = car_loop[i].crl_pilots_off_10; - else if (state->srate <= 25000000) - aclc = car_loop[i].crl_pilots_off_20; - else - aclc = car_loop[i].crl_pilots_off_30; - } - } else { /* 16APSK and 32APSK */ - if (state->srate <= 3000000) - aclc = car_loop_apsk_low[i].crl_pilots_on_2; - else if (state->srate <= 7000000) - aclc = car_loop_apsk_low[i].crl_pilots_on_5; - else if (state->srate <= 15000000) - aclc = car_loop_apsk_low[i].crl_pilots_on_10; - else if (state->srate <= 25000000) - aclc = car_loop_apsk_low[i].crl_pilots_on_20; - else - aclc = car_loop_apsk_low[i].crl_pilots_on_30; - } - - return aclc; -} - -static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) -{ - struct stv090x_short_frame_crloop *short_crl = NULL; - s32 index = 0; - u8 aclc = 0x0b; - - switch (state->modulation) { - case STV090x_QPSK: - default: - index = 0; - break; - case STV090x_8PSK: - index = 1; - break; - case STV090x_16APSK: - index = 2; - break; - case STV090x_32APSK: - index = 3; - break; - } - - if (state->internal->dev_ver >= 0x30) { - /* Cut 3.0 and up */ - short_crl = stv090x_s2_short_crl_cut30; - } else { - /* Cut 2.0 and up: we don't support cuts older than 2.0 */ - short_crl = stv090x_s2_short_crl_cut20; - } - - if (state->srate <= 3000000) - aclc = short_crl[index].crl_2; - else if (state->srate <= 7000000) - aclc = short_crl[index].crl_5; - else if (state->srate <= 15000000) - aclc = short_crl[index].crl_10; - else if (state->srate <= 25000000) - aclc = short_crl[index].crl_20; - else - aclc = short_crl[index].crl_30; - - return aclc; -} - -static int stv090x_optimize_track(struct stv090x_state *state) -{ - struct dvb_frontend *fe = &state->frontend; - - enum stv090x_rolloff rolloff; - enum stv090x_modcod modcod; - - s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0; - u32 reg; - - srate = stv090x_get_srate(state, state->internal->mclk); - srate += stv090x_get_tmgoffst(state, srate); - - switch (state->delsys) { - case STV090x_DVBS1: - case STV090x_DSS: - if (state->search_mode == STV090x_SEARCH_AUTO) { - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - } - reg = STV090x_READ_DEMOD(state, DEMOD); - STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); - STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); - if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) - goto err; - - if (state->internal->dev_ver >= 0x30) { - if (stv090x_get_viterbi(state) < 0) - goto err; - - if (state->fec == STV090x_PR12) { - if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) - goto err; - } else { - if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) - goto err; - } - } - - if (STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS1) < 0) - goto err; - break; - - case STV090x_DVBS2: - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - if (state->internal->dev_ver >= 0x30) { - if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) - goto err; - } - if (state->frame_len == STV090x_LONG_FRAME) { - reg = STV090x_READ_DEMOD(state, DMDMODCOD); - modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); - pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; - aclc = stv090x_optimize_carloop(state, modcod, pilots); - if (modcod <= STV090x_QPSK_910) { - STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); - } else if (modcod <= STV090x_8PSK_910) { - if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) - goto err; - } - if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { - if (modcod <= STV090x_16APSK_910) { - if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) - goto err; - } else { - if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) - goto err; - } - } - } else { - /*Carrier loop setting for short frame*/ - aclc = stv090x_optimize_carloop_short(state); - if (state->modulation == STV090x_QPSK) { - if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) - goto err; - } else if (state->modulation == STV090x_8PSK) { - if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) - goto err; - } else if (state->modulation == STV090x_16APSK) { - if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) - goto err; - } else if (state->modulation == STV090x_32APSK) { - if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) - goto err; - } - } - - STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS2); /* PER */ - break; - - case STV090x_ERROR: - default: - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); - STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - break; - } - - f_1 = STV090x_READ_DEMOD(state, CFR2); - f_0 = STV090x_READ_DEMOD(state, CFR1); - reg = STV090x_READ_DEMOD(state, TMGOBS); - rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); - - if (state->algo == STV090x_BLIND_SEARCH) { - STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); - reg = STV090x_READ_DEMOD(state, DMDCFGMD); - STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); - STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); - if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) - goto err; - - if (stv090x_set_srate(state, srate) < 0) - goto err; - blind_tune = 1; - - if (stv090x_dvbs_track_crl(state) < 0) - goto err; - } - - if (state->internal->dev_ver >= 0x20) { - if ((state->search_mode == STV090x_SEARCH_DVBS1) || - (state->search_mode == STV090x_SEARCH_DSS) || - (state->search_mode == STV090x_SEARCH_AUTO)) { - - if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) - goto err; - } - } - - if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) - goto err; - - /* AUTO tracking MODE */ - if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) - goto err; - /* AUTO tracking MODE */ - if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) - goto err; - - if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || - (state->srate < 10000000)) { - /* update initial carrier freq with the found freq offset */ - if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) - goto err; - state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; - - if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { - - if (state->algo != STV090x_WARM_SEARCH) { - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_set_bandwidth) { - if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - } - } - if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) - msleep(50); /* blind search: wait 50ms for SR stabilization */ - else - msleep(5); - - stv090x_get_lock_tmg(state); - - if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) - goto err; - - i = 0; - - while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { - - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) - goto err; - i++; - } - } - - } - - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) - goto err; - } - - if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) - stv090x_set_vit_thtracq(state); - - return 0; - -err_gateoff: - stv090x_i2c_gate_ctrl(state, 0); -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) -{ - s32 timer = 0, lock = 0, stat; - u32 reg; - - while ((timer < timeout) && (!lock)) { - reg = STV090x_READ_DEMOD(state, DMDSTATE); - stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); - - switch (stat) { - case 0: /* searching */ - case 1: /* first PLH detected */ - default: - lock = 0; - break; - - case 2: /* DVB-S2 mode */ - reg = STV090x_READ_DEMOD(state, PDELSTATUS1); - lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); - break; - - case 3: /* DVB-S1/legacy mode */ - reg = STV090x_READ_DEMOD(state, VSTATUSVIT); - lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); - break; - } - if (!lock) { - msleep(10); - timer += 10; - } - } - return lock; -} - -static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) -{ - u32 reg; - s32 timer = 0; - int lock; - - lock = stv090x_get_dmdlock(state, timeout_dmd); - if (lock) - lock = stv090x_get_feclock(state, timeout_fec); - - if (lock) { - lock = 0; - - while ((timer < timeout_fec) && (!lock)) { - reg = STV090x_READ_DEMOD(state, TSSTATUS); - lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); - msleep(1); - timer++; - } - } - - return lock; -} - -static int stv090x_set_s2rolloff(struct stv090x_state *state) -{ - u32 reg; - - if (state->internal->dev_ver <= 0x20) { - /* rolloff to auto mode if DVBS2 */ - reg = STV090x_READ_DEMOD(state, DEMOD); - STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); - if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) - goto err; - } else { - /* DVB-S2 rolloff to auto mode if DVBS2 */ - reg = STV090x_READ_DEMOD(state, DEMOD); - STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); - if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) - goto err; - } - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - - -static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) -{ - struct dvb_frontend *fe = &state->frontend; - enum stv090x_signal_state signal_state = STV090x_NOCARRIER; - u32 reg; - s32 agc1_power, power_iq = 0, i; - int lock = 0, low_sr = 0; - - reg = STV090x_READ_DEMOD(state, TSCFGH); - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ - if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ - goto err; - - if (state->internal->dev_ver >= 0x20) { - if (state->srate > 5000000) { - if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) - goto err; - } else { - if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) - goto err; - } - } - - stv090x_get_lock_tmg(state); - - if (state->algo == STV090x_BLIND_SEARCH) { - state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ - if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ - goto err; - if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) - goto err; - if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */ - goto err; - } else { - /* known srate */ - if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) - goto err; - - if (state->srate < 2000000) { - /* SR < 2MSPS */ - if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) - goto err; - } else { - /* SR >= 2Msps */ - if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) - goto err; - } - - if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) - goto err; - - if (state->internal->dev_ver >= 0x20) { - if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) - goto err; - if (state->algo == STV090x_COLD_SEARCH) - state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; - else if (state->algo == STV090x_WARM_SEARCH) - state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; - } - - /* if cold start or warm (Symbolrate is known) - * use a Narrow symbol rate scan range - */ - if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ - goto err; - - if (stv090x_set_srate(state, state->srate) < 0) - goto err; - - if (stv090x_set_max_srate(state, state->internal->mclk, - state->srate) < 0) - goto err; - if (stv090x_set_min_srate(state, state->internal->mclk, - state->srate) < 0) - goto err; - - if (state->srate >= 10000000) - low_sr = 0; - else - low_sr = 1; - } - - /* Setup tuner */ - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_set_bbgain) { - reg = state->config->tuner_bbgain; - if (reg == 0) - reg = 10; /* default: 10dB */ - if (state->config->tuner_set_bbgain(fe, reg) < 0) - goto err_gateoff; - } - - if (state->config->tuner_set_frequency) { - if (state->config->tuner_set_frequency(fe, state->frequency) < 0) - goto err_gateoff; - } - - if (state->config->tuner_set_bandwidth) { - if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - msleep(50); - - if (state->config->tuner_get_status) { - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - if (state->config->tuner_get_status(fe, ®) < 0) - goto err_gateoff; - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - if (reg) - dprintk(FE_DEBUG, 1, "Tuner phase locked"); - else { - dprintk(FE_DEBUG, 1, "Tuner unlocked"); - return STV090x_NOCARRIER; - } - } - - msleep(10); - agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), - STV090x_READ_DEMOD(state, AGCIQIN0)); - - if (agc1_power == 0) { - /* If AGC1 integrator value is 0 - * then read POWERI, POWERQ - */ - for (i = 0; i < 5; i++) { - power_iq += (STV090x_READ_DEMOD(state, POWERI) + - STV090x_READ_DEMOD(state, POWERQ)) >> 1; - } - power_iq /= 5; - } - - if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { - dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); - lock = 0; - signal_state = STV090x_NOAGC1; - } else { - reg = STV090x_READ_DEMOD(state, DEMOD); - STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); - - if (state->internal->dev_ver <= 0x20) { - /* rolloff to auto mode if DVBS2 */ - STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); - } else { - /* DVB-S2 rolloff to auto mode if DVBS2 */ - STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); - } - if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) - goto err; - - if (stv090x_delivery_search(state) < 0) - goto err; - - if (state->algo != STV090x_BLIND_SEARCH) { - if (stv090x_start_search(state) < 0) - goto err; - } - } - - if (signal_state == STV090x_NOAGC1) - return signal_state; - - if (state->algo == STV090x_BLIND_SEARCH) - lock = stv090x_blind_search(state); - - else if (state->algo == STV090x_COLD_SEARCH) - lock = stv090x_get_coldlock(state, state->DemodTimeout); - - else if (state->algo == STV090x_WARM_SEARCH) - lock = stv090x_get_dmdlock(state, state->DemodTimeout); - - if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { - if (!low_sr) { - if (stv090x_chk_tmg(state)) - lock = stv090x_sw_algo(state); - } - } - - if (lock) - signal_state = stv090x_get_sig_params(state); - - if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */ - stv090x_optimize_track(state); - - if (state->internal->dev_ver >= 0x20) { - /* >= Cut 2.0 :release TS reset after - * demod lock and optimized Tracking - */ - reg = STV090x_READ_DEMOD(state, TSCFGH); - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ - if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) - goto err; - - msleep(3); - - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ - if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) - goto err; - - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ - if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) - goto err; - } - - lock = stv090x_get_lock(state, state->FecTimeout, - state->FecTimeout); - if (lock) { - if (state->delsys == STV090x_DVBS2) { - stv090x_set_s2rolloff(state); - - reg = STV090x_READ_DEMOD(state, PDELCTRL2); - STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); - if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) - goto err; - /* Reset DVBS2 packet delinator error counter */ - reg = STV090x_READ_DEMOD(state, PDELCTRL2); - STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); - if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS2) < 0) /* PER */ - goto err; - } else { - if (STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS1) < 0) - goto err; - } - /* Reset the Total packet counter */ - if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) - goto err; - /* Reset the packet Error counter2 */ - if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) - goto err; - } else { - signal_state = STV090x_NODATA; - stv090x_chk_signal(state); - } - } - return signal_state; - -err_gateoff: - stv090x_i2c_gate_ctrl(state, 0); -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -#ifndef USE_API3 -static enum dvbfe_search stv090x_search(struct dvb_frontend *fe) -#else -static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -#endif -{ - struct stv090x_state *state = fe->demodulator_priv; - struct dtv_frontend_properties *props = &fe->dtv_property_cache; - -#ifndef USE_API3 - if (props->frequency == 0) -#else - return DVBFE_ALGO_SEARCH_INVALID; -#endif - - state->delsys = props->delivery_system; -#ifndef USE_API3 - state->frequency = props->frequency; - state->srate = props->symbol_rate; -#else - state->frequency = p->frequency; - state->srate = p->u.qpsk.symbol_rate; -#endif - state->search_mode = STV090x_SEARCH_AUTO; - state->algo = STV090x_COLD_SEARCH; - state->fec = STV090x_PRERR; - if (state->srate > 10000000) { - dprintk(FE_DEBUG, 1, "Search range: 10 MHz"); - state->search_range = 10000000; - } else { - dprintk(FE_DEBUG, 1, "Search range: 5 MHz"); - state->search_range = 5000000; - } - - if (stv090x_algo(state) == STV090x_RANGEOK) { - dprintk(FE_DEBUG, 1, "Search success!"); - return DVBFE_ALGO_SEARCH_SUCCESS; - } else { - dprintk(FE_DEBUG, 1, "Search failed!"); - return DVBFE_ALGO_SEARCH_FAILED; - } - - return DVBFE_ALGO_SEARCH_ERROR; -} - -static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg, dstatus; - u8 search_state; - - *status = 0; - - dstatus = STV090x_READ_DEMOD(state, DSTATUS); - if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD)) - *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; - - reg = STV090x_READ_DEMOD(state, DMDSTATE); - search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); - - switch (search_state) { - case 0: /* searching */ - case 1: /* first PLH detected */ - default: - dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)"); - break; - - case 2: /* DVB-S2 mode */ - dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); - if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { - reg = STV090x_READ_DEMOD(state, PDELSTATUS1); - if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { - *status |= FE_HAS_VITERBI; - reg = STV090x_READ_DEMOD(state, TSSTATUS); - if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) - *status |= FE_HAS_SYNC | FE_HAS_LOCK; - } - } - break; - - case 3: /* DVB-S1/legacy mode */ - dprintk(FE_DEBUG, 1, "Delivery system: DVB-S"); - if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { - reg = STV090x_READ_DEMOD(state, VSTATUSVIT); - if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { - *status |= FE_HAS_VITERBI; - reg = STV090x_READ_DEMOD(state, TSSTATUS); - if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) - *status |= FE_HAS_SYNC | FE_HAS_LOCK; - } - } - break; - } - - return 0; -} - -static int stv090x_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct stv090x_state *state = fe->demodulator_priv; - - u32 reg, h, m, l; - enum fe_status status; - - stv090x_read_status(fe, &status); - if (!(status & FE_HAS_LOCK)) { - *ber = 1 << 23; /* Max BER */ - } else { - /* Counter 1 */ - reg = STV090x_READ_DEMOD(state, ERRCNT12); - h = STV090x_GETFIELD_Px(reg, ERR_CNT12_FIELD); - - reg = STV090x_READ_DEMOD(state, ERRCNT11); - m = STV090x_GETFIELD_Px(reg, ERR_CNT11_FIELD); - - reg = STV090x_READ_DEMOD(state, ERRCNT10); - l = STV090x_GETFIELD_Px(reg, ERR_CNT10_FIELD); - - *ber = ((h << 16) | (m << 8) | l); - } - return 0; -} - -#if 0 -static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) -{ - struct stv090x_state *state = fe->demodulator_priv; - - s32 count_4, count_3, count_2, count_1, count_0, count; - u32 reg, h, m, l; - enum fe_status status; - - stv090x_read_status(fe, &status); - if (!(status & FE_HAS_LOCK)) { - *per = 1 << 23; /* Max PER */ - } else { - /* Counter 2 */ - reg = STV090x_READ_DEMOD(state, ERRCNT22); - h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); - - reg = STV090x_READ_DEMOD(state, ERRCNT21); - m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); - - reg = STV090x_READ_DEMOD(state, ERRCNT20); - l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); - - *per = ((h << 16) | (m << 8) | l); - - count_4 = STV090x_READ_DEMOD(state, FBERCPT4); - count_3 = STV090x_READ_DEMOD(state, FBERCPT3); - count_2 = STV090x_READ_DEMOD(state, FBERCPT2); - count_1 = STV090x_READ_DEMOD(state, FBERCPT1); - count_0 = STV090x_READ_DEMOD(state, FBERCPT0); - - if ((!count_4) && (!count_3)) { - count = (count_2 & 0xff) << 16; - count |= (count_1 & 0xff) << 8; - count |= count_0 & 0xff; - } else { - count = 1 << 24; - } - if (count == 0) - *per = 1; - } - if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) - goto err; - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} -#endif - -static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) -{ - int res = 0; - int min = 0, med; - - if ((val >= tab[min].read && val < tab[max].read) || - (val >= tab[max].read && val < tab[min].read)) { - while ((max - min) > 1) { - med = (max + min) / 2; - if ((val >= tab[min].read && val < tab[med].read) || - (val >= tab[med].read && val < tab[min].read)) - max = med; - else - min = med; - } - res = ((val - tab[min].read) * - (tab[max].real - tab[min].real) / - (tab[max].read - tab[min].read)) + - tab[min].real; - } else { - if (tab[min].read < tab[max].read) { - if (val < tab[min].read) - res = tab[min].real; - else if (val >= tab[max].read) - res = tab[max].real; - } else { - if (val >= tab[min].read) - res = tab[min].real; - else if (val < tab[max].read) - res = tab[max].real; - } - } - - return res; -} - -static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg; - s32 agc_0, agc_1, agc; - s32 str; - - reg = STV090x_READ_DEMOD(state, AGCIQIN1); - agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); - reg = STV090x_READ_DEMOD(state, AGCIQIN0); - agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); - agc = MAKEWORD16(agc_1, agc_0); - - str = stv090x_table_lookup(stv090x_rf_tab, - ARRAY_SIZE(stv090x_rf_tab) - 1, agc); - if (agc > stv090x_rf_tab[0].read) - str = 0; - else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) - str = -100; -#ifdef DBVALS - *strength = str; -#else - *strength = (str + 100) * 0xFFFF / 100; -#endif - return 0; -} - -static int stv090x_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct stv090x_state *state = fe->demodulator_priv; - u8 err0, err1; - - *ucblocks = 0; - switch (state->delsys) { - case STV090x_DVBS2: - err0 = STV090x_READ_DEMOD(state, UPCRCKO0); - err1 = STV090x_READ_DEMOD(state, UPCRCKO1); - *ucblocks = (err1 << 8) | err0; - default: - break; - } - return 0; -} - -static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg_0, reg_1, reg, i; - s32 val_0, val_1, val = 0; - u8 lock_f; -#ifndef DBVALS - s32 div; - u32 last; -#endif - - switch (state->delsys) { - case STV090x_DVBS2: - reg = STV090x_READ_DEMOD(state, DSTATUS); - lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); - if (lock_f) { - msleep(5); - for (i = 0; i < 16; i++) { - reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); - val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); - reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); - val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD); - val += MAKEWORD16(val_1, val_0); - msleep(1); - } - val /= 16; -#ifdef DBVALS - *cnr = stv090x_table_lookup(stv090x_s2cn_tab, - ARRAY_SIZE(stv090x_s2cn_tab) - 1, val); -#else - last = ARRAY_SIZE(stv090x_s2cn_tab) - 1; - div = stv090x_s2cn_tab[0].read - - stv090x_s2cn_tab[last].read; - *cnr = 0xFFFF - ((val * 0xFFFF) / div); -#endif - } else -#ifdef DBVALS - *cnr = -30; -#else - *cnr = 0; -#endif - break; - - case STV090x_DVBS1: - case STV090x_DSS: - reg = STV090x_READ_DEMOD(state, DSTATUS); - lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); - if (lock_f) { - msleep(5); - for (i = 0; i < 16; i++) { - reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); - val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); - reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); - val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD); - val += MAKEWORD16(val_1, val_0); - msleep(1); - } - val /= 16; -#ifdef DBVALS - *cnr = stv090x_table_lookup(stv090x_s1cn_tab, - ARRAY_SIZE(stv090x_s1cn_tab) - 1, val); -#else - last = ARRAY_SIZE(stv090x_s1cn_tab) - 1; - div = stv090x_s1cn_tab[0].read - - stv090x_s1cn_tab[last].read; - *cnr = 0xFFFF - ((val * 0xFFFF) / div); -#endif - } else - *cnr = 0; - break; - default: - break; - } - - return 0; -} - -static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg; - - reg = STV090x_READ_DEMOD(state, DISTXCTL); - switch (tone) { - case SEC_TONE_ON: - STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); - STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - break; - - case SEC_TONE_OFF: - STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); - STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - break; - default: - return -EINVAL; - } - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - - -static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe) -{ - return DVBFE_ALGO_CUSTOM; -} - -static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg, idle = 0, fifo_full = 1; - int i; - - reg = STV090x_READ_DEMOD(state, DISTXCTL); - - STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, - (state->config->diseqc_envelope_mode) ? 4 : 2); - STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - - STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - - for (i = 0; i < cmd->msg_len; i++) { - - while (fifo_full) { - reg = STV090x_READ_DEMOD(state, DISTXSTATUS); - fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); - } - - if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) - goto err; - } - reg = STV090x_READ_DEMOD(state, DISTXCTL); - STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - - i = 0; - - while ((!idle) && (i < 10)) { - reg = STV090x_READ_DEMOD(state, DISTXSTATUS); - idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); - msleep(10); - i++; - } - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg, idle = 0, fifo_full = 1; - u8 mode, value; - int i; - - reg = STV090x_READ_DEMOD(state, DISTXCTL); - - if (burst == SEC_MINI_A) { - mode = (state->config->diseqc_envelope_mode) ? 5 : 3; - value = 0x00; - } else { - mode = (state->config->diseqc_envelope_mode) ? 4 : 2; - value = 0xFF; - } - - STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); - STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - - STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - - while (fifo_full) { - reg = STV090x_READ_DEMOD(state, DISTXSTATUS); - fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); - } - - if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) - goto err; - - reg = STV090x_READ_DEMOD(state, DISTXCTL); - STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); - if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) - goto err; - - i = 0; - - while ((!idle) && (i < 10)) { - reg = STV090x_READ_DEMOD(state, DISTXSTATUS); - idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); - msleep(10); - i++; - } - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg = 0, i = 0, rx_end = 0; - - while ((rx_end != 1) && (i < 10)) { - msleep(10); - i++; - reg = STV090x_READ_DEMOD(state, DISRX_ST0); - rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); - } - - if (rx_end) { - reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); - for (i = 0; i < reply->msg_len; i++) - reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); - } - - return 0; -} - -static int stv090x_sleep(struct dvb_frontend *fe) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg; - u8 full_standby = 0; - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (state->config->tuner_sleep) { - if (state->config->tuner_sleep(fe) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep", - state->device == STV0900 ? "STV0900" : "STV0903", - state->demod); - - mutex_lock(&state->internal->demod_lock); - - switch (state->demod) { - case STV090x_DEMODULATOR_0: - /* power off ADC 1 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR1); - STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); - if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) - goto err; - /* power off DiSEqC 1 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR2); - STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); - if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) - goto err; - - /* check whether path 2 is already sleeping, that is when - ADC2 is off */ - reg = stv090x_read_reg(state, STV090x_TSTTNR3); - if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0) - full_standby = 1; - - /* stop clocks */ - reg = stv090x_read_reg(state, STV090x_STOPCLK1); - /* packet delineator 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1); - /* ADC 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1); - /* FEC clock is shared between the two paths, only stop it - when full standby is possible */ - if (full_standby) - STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); - if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) - goto err; - reg = stv090x_read_reg(state, STV090x_STOPCLK2); - /* sampling 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); - /* viterbi 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1); - /* TS clock is shared between the two paths, only stop it - when full standby is possible */ - if (full_standby) - STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); - if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; - break; - - case STV090x_DEMODULATOR_1: - /* power off ADC 2 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR3); - STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); - if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) - goto err; - /* power off DiSEqC 2 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR4); - STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); - if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) - goto err; - - /* check whether path 1 is already sleeping, that is when - ADC1 is off */ - reg = stv090x_read_reg(state, STV090x_TSTTNR1); - if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0) - full_standby = 1; - - /* stop clocks */ - reg = stv090x_read_reg(state, STV090x_STOPCLK1); - /* packet delineator 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1); - /* ADC 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1); - /* FEC clock is shared between the two paths, only stop it - when full standby is possible */ - if (full_standby) - STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); - if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) - goto err; - reg = stv090x_read_reg(state, STV090x_STOPCLK2); - /* sampling 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); - /* viterbi 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1); - /* TS clock is shared between the two paths, only stop it - when full standby is possible */ - if (full_standby) - STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); - if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; - break; - - default: - dprintk(FE_ERROR, 1, "Wrong demodulator!"); - break; - } - - if (full_standby) { - /* general power off */ - reg = stv090x_read_reg(state, STV090x_SYNTCTRL); - STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); - if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) - goto err; - } - - mutex_unlock(&state->internal->demod_lock); - return 0; - -err_gateoff: - stv090x_i2c_gate_ctrl(state, 0); -err: - mutex_unlock(&state->internal->demod_lock); - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_wakeup(struct dvb_frontend *fe) -{ - struct stv090x_state *state = fe->demodulator_priv; - u32 reg; - - dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby", - state->device == STV0900 ? "STV0900" : "STV0903", - state->demod); - - mutex_lock(&state->internal->demod_lock); - - /* general power on */ - reg = stv090x_read_reg(state, STV090x_SYNTCTRL); - STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); - if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) - goto err; - - switch (state->demod) { - case STV090x_DEMODULATOR_0: - /* power on ADC 1 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR1); - STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); - if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) - goto err; - /* power on DiSEqC 1 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR2); - STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1); - if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) - goto err; - - /* activate clocks */ - reg = stv090x_read_reg(state, STV090x_STOPCLK1); - /* packet delineator 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0); - /* ADC 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0); - /* FEC clock */ - STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); - if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) - goto err; - reg = stv090x_read_reg(state, STV090x_STOPCLK2); - /* sampling 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0); - /* viterbi 1 clock */ - STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0); - /* TS clock */ - STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); - if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; - break; - - case STV090x_DEMODULATOR_1: - /* power on ADC 2 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR3); - STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1); - if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) - goto err; - /* power on DiSEqC 2 */ - reg = stv090x_read_reg(state, STV090x_TSTTNR4); - STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1); - if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) - goto err; - - /* activate clocks */ - reg = stv090x_read_reg(state, STV090x_STOPCLK1); - /* packet delineator 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0); - /* ADC 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0); - /* FEC clock */ - STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); - if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) - goto err; - reg = stv090x_read_reg(state, STV090x_STOPCLK2); - /* sampling 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0); - /* viterbi 2 clock */ - STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0); - /* TS clock */ - STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); - if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) - goto err; - break; - - default: - dprintk(FE_ERROR, 1, "Wrong demodulator!"); - break; - } - - mutex_unlock(&state->internal->demod_lock); - return 0; -err: - mutex_unlock(&state->internal->demod_lock); - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static void stv090x_release(struct dvb_frontend *fe) -{ - struct stv090x_state *state = fe->demodulator_priv; - - state->internal->num_used--; - if (state->internal->num_used <= 0) { - - dprintk(FE_ERROR, 1, "Actually removing"); - - remove_dev(state->internal); - kfree(state->internal); - } - - kfree(state); -} - -static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) -{ - u32 reg = 0; - - reg = stv090x_read_reg(state, STV090x_GENCFG); - - switch (ldpc_mode) { - case STV090x_DUAL: - default: - if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { - /* set LDPC to dual mode */ - if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) - goto err; - - state->demod_mode = STV090x_DUAL; - - reg = stv090x_read_reg(state, STV090x_TSTRES0); - STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); - if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) - goto err; - STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); - if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) - goto err; - - if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) - goto err; - } - break; - - case STV090x_SINGLE: - if (stv090x_stop_modcod(state) < 0) - goto err; - if (stv090x_activate_modcod_single(state) < 0) - goto err; - - if (state->demod == STV090x_DEMODULATOR_1) { - if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ - goto err; - } else { - if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ - goto err; - } - - reg = stv090x_read_reg(state, STV090x_TSTRES0); - STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); - if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) - goto err; - STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); - if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) - goto err; - - reg = STV090x_READ_DEMOD(state, PDELCTRL1); - STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); - if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); - if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) - goto err; - break; - } - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -/* return (Hz), clk in Hz*/ -static u32 stv090x_get_mclk(struct stv090x_state *state) -{ - const struct stv090x_config *config = state->config; - u32 div, reg; - u8 ratio; - - div = stv090x_read_reg(state, STV090x_NCOARSE); - reg = stv090x_read_reg(state, STV090x_SYNTCTRL); - ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; - - return (div + 1) * config->xtal / ratio; /* kHz */ -} - -static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) -{ - const struct stv090x_config *config = state->config; - u32 reg, div, clk_sel; - - reg = stv090x_read_reg(state, STV090x_SYNTCTRL); - clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); - - div = ((clk_sel * mclk) / config->xtal) - 1; - - reg = stv090x_read_reg(state, STV090x_NCOARSE); - STV090x_SETFIELD(reg, M_DIV_FIELD, div); - if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) - goto err; - - state->internal->mclk = stv090x_get_mclk(state); - - /*Set the DiseqC frequency to 22KHz */ - div = state->internal->mclk / 704000; - if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) - goto err; - if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) - goto err; - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_set_tspath(struct stv090x_state *state) -{ - u32 reg; - - if (state->internal->dev_ver >= 0x20) { - switch (state->config->ts1_mode) { - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - switch (state->config->ts2_mode) { - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - default: - stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); - break; - - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ - goto err; - reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); - STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); - if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) - goto err; - reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); - STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); - if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) - goto err; - break; - } - break; - - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - default: - switch (state->config->ts2_mode) { - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - default: - if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) - goto err; - break; - - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) - goto err; - break; - } - break; - } - } else { - switch (state->config->ts1_mode) { - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - switch (state->config->ts2_mode) { - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - default: - stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); - break; - - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); - reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); - STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); - if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) - goto err; - reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); - STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); - if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) - goto err; - break; - } - break; - - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - default: - switch (state->config->ts2_mode) { - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - default: - stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); - break; - - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); - break; - } - break; - } - } - - switch (state->config->ts1_mode) { - case STV090x_TSMODE_PARALLEL_PUNCTURED: - reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); - if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) - goto err; - break; - - case STV090x_TSMODE_DVBCI: - reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); - if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) - goto err; - break; - - case STV090x_TSMODE_SERIAL_PUNCTURED: - reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); - if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) - goto err; - break; - - case STV090x_TSMODE_SERIAL_CONTINUOUS: - reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); - if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) - goto err; - break; - - default: - break; - } - - switch (state->config->ts2_mode) { - case STV090x_TSMODE_PARALLEL_PUNCTURED: - reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); - if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) - goto err; - break; - - case STV090x_TSMODE_DVBCI: - reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); - if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) - goto err; - break; - - case STV090x_TSMODE_SERIAL_PUNCTURED: - reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); - if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) - goto err; - break; - - case STV090x_TSMODE_SERIAL_CONTINUOUS: - reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); - STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); - STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); - STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); - if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) - goto err; - break; - - default: - break; - } - - if (state->config->ts1_clk > 0) { - u32 speed; - - switch (state->config->ts1_mode) { - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - default: - speed = state->internal->mclk / - (state->config->ts1_clk / 4); - if (speed < 0x08) - speed = 0x08; - if (speed > 0xFF) - speed = 0xFF; - break; - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - speed = state->internal->mclk / - (state->config->ts1_clk / 32); - if (speed < 0x20) - speed = 0x20; - if (speed > 0xFF) - speed = 0xFF; - break; - } - reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); - STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); - if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) - goto err; - } - - if (state->config->ts2_clk > 0) { - u32 speed; - - switch (state->config->ts2_mode) { - case STV090x_TSMODE_PARALLEL_PUNCTURED: - case STV090x_TSMODE_DVBCI: - default: - speed = state->internal->mclk / - (state->config->ts2_clk / 4); - if (speed < 0x08) - speed = 0x08; - if (speed > 0xFF) - speed = 0xFF; - break; - case STV090x_TSMODE_SERIAL_PUNCTURED: - case STV090x_TSMODE_SERIAL_CONTINUOUS: - speed = state->internal->mclk / - (state->config->ts2_clk / 32); - if (speed < 0x20) - speed = 0x20; - if (speed > 0xFF) - speed = 0xFF; - break; - } - reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); - STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); - if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) - goto err; - } - - - printk("TSCFGH resets\n"); - - reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); - if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); - if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) - goto err; - - reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); - if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) - goto err; - STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); - if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) - goto err; - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_init(struct dvb_frontend *fe) -{ - struct stv090x_state *state = fe->demodulator_priv; - const struct stv090x_config *config = state->config; - u32 reg; - - if (state->internal->mclk == 0) { - /* call tuner init to configure the tuner's clock output - divider directly before setting up the master clock of - the stv090x. */ - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (config->tuner_init) { - if (config->tuner_init(fe) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - - stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ - msleep(5); - if (stv090x_write_reg(state, STV090x_SYNTCTRL, - 0x20 | config->clk_mode) < 0) - goto err; - stv090x_get_mclk(state); - } - - if (stv090x_wakeup(fe) < 0) { - dprintk(FE_ERROR, 1, "Error waking device"); - goto err; - } - - if (stv090x_ldpc_mode(state, state->demod_mode) < 0) - goto err; - - reg = STV090x_READ_DEMOD(state, TNRCFG2); - STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); - if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) - goto err; - reg = STV090x_READ_DEMOD(state, DEMOD); - STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); - if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) - goto err; - - if (stv090x_i2c_gate_ctrl(state, 1) < 0) - goto err; - - if (config->tuner_set_mode) { - if (config->tuner_set_mode(fe, TUNER_WAKE) < 0) - goto err_gateoff; - } - - if (config->tuner_init) { - if (config->tuner_init(fe) < 0) - goto err_gateoff; - } - - if (stv090x_i2c_gate_ctrl(state, 0) < 0) - goto err; - -#if 0 - if (stv090x_set_tspath(state) < 0) - goto err; -#endif - return 0; - -err_gateoff: - stv090x_i2c_gate_ctrl(state, 0); -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -static int stv090x_setup(struct dvb_frontend *fe) -{ - struct stv090x_state *state = fe->demodulator_priv; - const struct stv090x_config *config = state->config; - const struct stv090x_reg *stv090x_initval = NULL; - const struct stv090x_reg *stv090x_cut20_val = NULL; - unsigned long t1_size = 0, t2_size = 0; - u32 reg = 0; - - int i; - - if (state->device == STV0900) { - dprintk(FE_DEBUG, 1, "Initializing STV0900"); - stv090x_initval = stv0900_initval; - t1_size = ARRAY_SIZE(stv0900_initval); - stv090x_cut20_val = stv0900_cut20_val; - t2_size = ARRAY_SIZE(stv0900_cut20_val); - } else if (state->device == STV0903) { - dprintk(FE_DEBUG, 1, "Initializing STV0903"); - stv090x_initval = stv0903_initval; - t1_size = ARRAY_SIZE(stv0903_initval); - stv090x_cut20_val = stv0903_cut20_val; - t2_size = ARRAY_SIZE(stv0903_cut20_val); - } - - /* STV090x init */ - - /* Stop Demod */ - if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) - goto err; - - msleep(5); - - /* Set No Tuner Mode */ - if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) - goto err; - - /* I2C repeater OFF */ - STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); - if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) - goto err; - - if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ - goto err; - msleep(5); - if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ - goto err; - if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ - goto err; - msleep(5); - - /* write initval */ - dprintk(FE_DEBUG, 1, "Setting up initial values"); - for (i = 0; i < t1_size; i++) { - if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) - goto err; - } - - state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); - if (state->internal->dev_ver >= 0x20) { - if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) - goto err; - - /* write cut20_val*/ - dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values"); - for (i = 0; i < t2_size; i++) { - if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) - goto err; - } - - } else if (state->internal->dev_ver < 0x20) { - dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!", - state->internal->dev_ver); - - goto err; - } else if (state->internal->dev_ver > 0x30) { - /* we shouldn't bail out from here */ - dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!", - state->internal->dev_ver); - } - - /* ADC1 range */ - reg = stv090x_read_reg(state, STV090x_TSTTNR1); - STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, - (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1); - if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) - goto err; - - /* ADC2 range */ - reg = stv090x_read_reg(state, STV090x_TSTTNR3); - STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, - (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1); - if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) - goto err; - - if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) - goto err; - if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) - goto err; - - if (stv090x_set_tspath(state) < 0) - goto err; - - return 0; -err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; -} - -int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value, - u8 xor_value) -{ - struct stv090x_state *state = fe->demodulator_priv; - u8 reg = 0; - - STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir); - STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value); - STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value); - - return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); -} -EXPORT_SYMBOL(stv090x_set_gpio); - -static struct dvb_frontend_ops stv090x_ops = { -#ifndef USE_API3 - .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, -#endif - .info = { - .name = "STV090x Multistandard", -#ifdef USE_API3 - .type = FE_QPSK, -#endif - .frequency_min = 950000, - .frequency_max = 2150000, - .frequency_stepsize = 0, - .frequency_tolerance = 0, - .symbol_rate_min = 1000000, - .symbol_rate_max = 45000000, - .caps = FE_CAN_INVERSION_AUTO | - FE_CAN_FEC_AUTO | - FE_CAN_QPSK | - FE_CAN_2G_MODULATION - }, - - .release = stv090x_release, - .init = stv090x_init, - - .sleep = stv090x_sleep, - .get_frontend_algo = stv090x_frontend_algo, - - .diseqc_send_master_cmd = stv090x_send_diseqc_msg, - .diseqc_send_burst = stv090x_send_diseqc_burst, - .diseqc_recv_slave_reply = stv090x_recv_slave_reply, - .set_tone = stv090x_set_tone, - - .search = stv090x_search, - .read_status = stv090x_read_status, - .read_ber = stv090x_read_ber, - .read_signal_strength = stv090x_read_signal_strength, - .read_snr = stv090x_read_cnr, - .read_ucblocks = stv090x_read_ucblocks, -}; - - -struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, - struct i2c_adapter *i2c, - enum stv090x_demodulator demod) -{ - struct stv090x_state *state = NULL; - struct stv090x_dev *temp_int; - - state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL); - if (state == NULL) - goto error; - - state->verbose = &verbose; - state->config = config; - state->i2c = i2c; - state->frontend.ops = stv090x_ops; - state->frontend.demodulator_priv = state; - state->demod = demod; - state->demod_mode = config->demod_mode; /* Single or Dual mode */ - state->device = config->device; - state->rolloff = STV090x_RO_35; /* default */ - - temp_int = find_dev(state->i2c, - state->config->address); - - if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) { - state->internal = temp_int->internal; - state->internal->num_used++; - dprintk(FE_INFO, 1, "Found Internal Structure!"); - } else { - state->internal = kmalloc(sizeof(struct stv090x_internal), - GFP_KERNEL); - if (!state->internal) - goto error; - temp_int = append_internal(state->internal); - if (!temp_int) { - kfree(state->internal); - goto error; - } - state->internal->num_used = 1; - state->internal->mclk = 0; - state->internal->dev_ver = 0; - state->internal->i2c_adap = state->i2c; - state->internal->i2c_addr = state->config->address; - dprintk(FE_INFO, 1, "Create New Internal Structure!"); - - mutex_init(&state->internal->demod_lock); - mutex_init(&state->internal->tuner_lock); - - if (stv090x_setup(&state->frontend) < 0) { - dprintk(FE_ERROR, 1, "Error setting up device"); - goto err_remove; - } - } - - /* workaround for stuck DiSEqC output */ - if (config->diseqc_envelope_mode) - stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); - - dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", - state->device == STV0900 ? "STV0900" : "STV0903", - demod, - state->internal->dev_ver); - - return &state->frontend; - -err_remove: - remove_dev(state->internal); - kfree(state->internal); -error: - kfree(state); - return NULL; -} -EXPORT_SYMBOL(stv090x_attach); -MODULE_PARM_DESC(verbose, "Set Verbosity level"); -MODULE_AUTHOR("Manu Abraham"); -MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend"); -MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,134 +0,0 @@ -/* - STV0900/0903 Multistandard Broadcast Frontend driver - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __STV090x_H -#define __STV090x_H - -enum stv090x_demodulator { - STV090x_DEMODULATOR_0 = 1, - STV090x_DEMODULATOR_1 -}; - -enum stv090x_device { - STV0903 = 0, - STV0900, -}; - -enum stv090x_mode { - STV090x_DUAL = 0, - STV090x_SINGLE -}; - -enum stv090x_tsmode { - STV090x_TSMODE_SERIAL_PUNCTURED = 1, - STV090x_TSMODE_SERIAL_CONTINUOUS, - STV090x_TSMODE_PARALLEL_PUNCTURED, - STV090x_TSMODE_DVBCI -}; - -enum stv090x_clkmode { - STV090x_CLK_INT = 0, /* Clk i/p = CLKI */ - STV090x_CLK_EXT = 2 /* Clk i/p = XTALI */ -}; - -enum stv090x_i2crpt { - STV090x_RPTLEVEL_256 = 0, - STV090x_RPTLEVEL_128 = 1, - STV090x_RPTLEVEL_64 = 2, - STV090x_RPTLEVEL_32 = 3, - STV090x_RPTLEVEL_16 = 4, - STV090x_RPTLEVEL_8 = 5, - STV090x_RPTLEVEL_4 = 6, - STV090x_RPTLEVEL_2 = 7, -}; - -enum stv090x_adc_range { - STV090x_ADC_2Vpp = 0, - STV090x_ADC_1Vpp = 1 -}; - -struct stv090x_config { - enum stv090x_device device; - enum stv090x_mode demod_mode; - enum stv090x_clkmode clk_mode; - - u32 xtal; /* default: 8000000 */ - u8 address; /* default: 0x68 */ - - u8 ts1_mode; - u8 ts2_mode; - u32 ts1_clk; - u32 ts2_clk; - - u8 ts1_tei : 1; - u8 ts2_tei : 1; - - enum stv090x_i2crpt repeater_level; - - u8 tuner_bbgain; /* default: 10db */ - enum stv090x_adc_range adc1_range; /* default: 2Vpp */ - enum stv090x_adc_range adc2_range; /* default: 2Vpp */ - - bool diseqc_envelope_mode; - - int (*tuner_init) (struct dvb_frontend *fe); - int (*tuner_sleep) (struct dvb_frontend *fe); - int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode); - int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency); - int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency); - int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth); - int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth); - int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain); - int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain); - int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk); - int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status); - void (*tuner_i2c_lock) (struct dvb_frontend *fe, int lock); -}; - -#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE)) - -extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, - struct i2c_adapter *i2c, - enum stv090x_demodulator demod); - -/* dir = 0 -> output, dir = 1 -> input/open-drain */ -extern int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, - u8 dir, u8 value, u8 xor_value); - -#else - -static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, - struct i2c_adapter *i2c, - enum stv090x_demodulator demod) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} - -static inline int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, - u8 opd, u8 value, u8 xor_value) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return -ENODEV; -} -#endif /* CONFIG_DVB_STV090x */ - -#endif /* __STV090x_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_priv.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_priv.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,279 +0,0 @@ -/* - STV0900/0903 Multistandard Broadcast Frontend driver - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __STV090x_PRIV_H -#define __STV090x_PRIV_H - -#include "dvb_frontend.h" - -#define FE_ERROR 0 -#define FE_NOTICE 1 -#define FE_INFO 2 -#define FE_DEBUG 3 -#define FE_DEBUGREG 4 - -#define dprintk(__y, __z, format, arg...) do { \ - if (__z) { \ - if ((verbose > FE_ERROR) && (verbose > __y)) \ - printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \ - else if ((verbose > FE_NOTICE) && (verbose > __y)) \ - printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \ - else if ((verbose > FE_INFO) && (verbose > __y)) \ - printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \ - else if ((verbose > FE_DEBUG) && (verbose > __y)) \ - printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \ - } else { \ - if (verbose > __y) \ - printk(format, ##arg); \ - } \ -} while (0) - -#define STV090x_READ_DEMOD(__state, __reg) (( \ - (__state)->demod == STV090x_DEMODULATOR_1) ? \ - stv090x_read_reg(__state, STV090x_P2_##__reg) : \ - stv090x_read_reg(__state, STV090x_P1_##__reg)) - -#define STV090x_WRITE_DEMOD(__state, __reg, __data) (( \ - (__state)->demod == STV090x_DEMODULATOR_1) ? \ - stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\ - stv090x_write_reg(__state, STV090x_P1_##__reg, __data)) - -#define STV090x_ADDR_OFFST(__state, __x) (( \ - (__state->demod) == STV090x_DEMODULATOR_1) ? \ - STV090x_P1_##__x : \ - STV090x_P2_##__x) - - -#define STV090x_SETFIELD(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_##bitf) - 1) <<\ - STV090x_OFFST_##bitf))) | \ - (val << STV090x_OFFST_##bitf)) - -#define STV090x_GETFIELD(val, bitf) ((val >> STV090x_OFFST_##bitf) & ((1 << STV090x_WIDTH_##bitf) - 1)) - - -#define STV090x_SETFIELD_Px(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_Px_##bitf) - 1) <<\ - STV090x_OFFST_Px_##bitf))) | \ - (val << STV090x_OFFST_Px_##bitf)) - -#define STV090x_GETFIELD_Px(val, bitf) ((val >> STV090x_OFFST_Px_##bitf) & ((1 << STV090x_WIDTH_Px_##bitf) - 1)) - -#define MAKEWORD16(__a, __b) (((__a) << 8) | (__b)) - -#define MSB(__x) ((__x >> 8) & 0xff) -#define LSB(__x) (__x & 0xff) - - -#define STV090x_IQPOWER_THRESHOLD 30 -#define STV090x_SEARCH_AGC2_TH_CUT20 700 -#define STV090x_SEARCH_AGC2_TH_CUT30 1400 - -#define STV090x_SEARCH_AGC2_TH(__ver) \ - ((__ver <= 0x20) ? \ - STV090x_SEARCH_AGC2_TH_CUT20 : \ - STV090x_SEARCH_AGC2_TH_CUT30) - -enum stv090x_signal_state { - STV090x_NOAGC1, - STV090x_NOCARRIER, - STV090x_NODATA, - STV090x_DATAOK, - STV090x_RANGEOK, - STV090x_OUTOFRANGE -}; - -enum stv090x_fec { - STV090x_PR12 = 0, - STV090x_PR23, - STV090x_PR34, - STV090x_PR45, - STV090x_PR56, - STV090x_PR67, - STV090x_PR78, - STV090x_PR89, - STV090x_PR910, - STV090x_PRERR -}; - -enum stv090x_modulation { - STV090x_QPSK, - STV090x_8PSK, - STV090x_16APSK, - STV090x_32APSK, - STV090x_UNKNOWN -}; - -enum stv090x_frame { - STV090x_LONG_FRAME, - STV090x_SHORT_FRAME -}; - -enum stv090x_pilot { - STV090x_PILOTS_OFF, - STV090x_PILOTS_ON -}; - -enum stv090x_rolloff { - STV090x_RO_35, - STV090x_RO_25, - STV090x_RO_20 -}; - -enum stv090x_inversion { - STV090x_IQ_AUTO, - STV090x_IQ_NORMAL, - STV090x_IQ_SWAP -}; - -enum stv090x_modcod { - STV090x_DUMMY_PLF = 0, - STV090x_QPSK_14, - STV090x_QPSK_13, - STV090x_QPSK_25, - STV090x_QPSK_12, - STV090x_QPSK_35, - STV090x_QPSK_23, - STV090x_QPSK_34, - STV090x_QPSK_45, - STV090x_QPSK_56, - STV090x_QPSK_89, - STV090x_QPSK_910, - STV090x_8PSK_35, - STV090x_8PSK_23, - STV090x_8PSK_34, - STV090x_8PSK_56, - STV090x_8PSK_89, - STV090x_8PSK_910, - STV090x_16APSK_23, - STV090x_16APSK_34, - STV090x_16APSK_45, - STV090x_16APSK_56, - STV090x_16APSK_89, - STV090x_16APSK_910, - STV090x_32APSK_34, - STV090x_32APSK_45, - STV090x_32APSK_56, - STV090x_32APSK_89, - STV090x_32APSK_910, - STV090x_MODCODE_UNKNOWN -}; - -enum stv090x_search { - STV090x_SEARCH_DSS = 0, - STV090x_SEARCH_DVBS1, - STV090x_SEARCH_DVBS2, - STV090x_SEARCH_AUTO -}; - -enum stv090x_algo { - STV090x_BLIND_SEARCH, - STV090x_COLD_SEARCH, - STV090x_WARM_SEARCH -}; - -enum stv090x_delsys { - STV090x_ERROR = 0, - STV090x_DVBS1 = 1, - STV090x_DVBS2, - STV090x_DSS -}; - -struct stv090x_long_frame_crloop { - enum stv090x_modcod modcod; - - u8 crl_pilots_on_2; - u8 crl_pilots_off_2; - u8 crl_pilots_on_5; - u8 crl_pilots_off_5; - u8 crl_pilots_on_10; - u8 crl_pilots_off_10; - u8 crl_pilots_on_20; - u8 crl_pilots_off_20; - u8 crl_pilots_on_30; - u8 crl_pilots_off_30; -}; - -struct stv090x_short_frame_crloop { - enum stv090x_modulation modulation; - - u8 crl_2; /* SR < 3M */ - u8 crl_5; /* 3 < SR <= 7M */ - u8 crl_10; /* 7 < SR <= 15M */ - u8 crl_20; /* 10 < SR <= 25M */ - u8 crl_30; /* 10 < SR <= 45M */ -}; - -struct stv090x_reg { - u16 addr; - u8 data; -}; - -struct stv090x_tab { - s32 real; - s32 read; -}; - -struct stv090x_internal { - struct i2c_adapter *i2c_adap; - u8 i2c_addr; - - struct mutex demod_lock; /* Lock access to shared register */ - struct mutex tuner_lock; /* Lock access to tuners */ - s32 mclk; /* Masterclock Divider factor */ - u32 dev_ver; - - int num_used; -}; - -struct stv090x_state { - enum stv090x_device device; - enum stv090x_demodulator demod; - enum stv090x_mode demod_mode; - struct stv090x_internal *internal; - - struct i2c_adapter *i2c; - const struct stv090x_config *config; - struct dvb_frontend frontend; - - u32 *verbose; /* Cached module verbosity */ - - enum stv090x_delsys delsys; - enum stv090x_fec fec; - enum stv090x_modulation modulation; - enum stv090x_modcod modcod; - enum stv090x_search search_mode; - enum stv090x_frame frame_len; - enum stv090x_pilot pilots; - enum stv090x_rolloff rolloff; - enum stv090x_inversion inversion; - enum stv090x_algo algo; - - u32 frequency; - u32 srate; - - s32 tuner_bw; - - s32 search_range; - - s32 DemodTimeout; - s32 FecTimeout; -}; - -#endif /* __STV090x_PRIV_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_reg.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_reg.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_reg.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv090x_reg.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,2371 +0,0 @@ -/* - STV0900/0903 Multistandard Broadcast Frontend driver - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __STV090x_REG_H -#define __STV090x_REG_H - -#define STV090x_MID 0xf100 -#define STV090x_OFFST_MCHIP_IDENT_FIELD 4 -#define STV090x_WIDTH_MCHIP_IDENT_FIELD 4 -#define STV090x_OFFST_MRELEASE_FIELD 0 -#define STV090x_WIDTH_MRELEASE_FIELD 4 - -#define STV090x_DACR1 0xf113 -#define STV090x_OFFST_DACR1_MODE_FIELD 5 -#define STV090x_WIDTH_DACR1_MODE_FIELD 3 -#define STV090x_OFFST_DACR1_VALUE_FIELD 0 -#define STV090x_WIDTH_DACR1_VALUE_FIELD 4 - -#define STV090x_DACR2 0xf114 -#define STV090x_OFFST_DACR2_VALUE_FIELD 0 -#define STV090x_WIDTH_DACR2_VALUE_FIELD 8 - -#define STV090x_OUTCFG 0xf11c -#define STV090x_OFFST_OUTSERRS1_HZ_FIELD 6 -#define STV090x_WIDTH_OUTSERRS1_HZ_FIELD 1 -#define STV090x_OFFST_OUTSERRS2_HZ_FIELD 5 -#define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1 -#define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4 -#define STV090x_WIDTH_OUTSERRS3_HZ_FIELD 1 -#define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3 -#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1 - -#define STV090x_MODECFG 0xf11d - -#define STV090x_IRQSTATUS3 0xf120 -#define STV090x_OFFST_SPLL_LOCK_FIELD 5 -#define STV090x_WIDTH_SPLL_LOCK_FIELD 1 -#define STV090x_OFFST_SSTREAM_LCK_3_FIELD 4 -#define STV090x_WIDTH_SSTREAM_LCK_3_FIELD 1 -#define STV090x_OFFST_SSTREAM_LCK_2_FIELD 3 -#define STV090x_WIDTH_SSTREAM_LCK_2_FIELD 1 -#define STV090x_OFFST_SSTREAM_LCK_1_FIELD 2 -#define STV090x_WIDTH_SSTREAM_LCK_1_FIELD 1 -#define STV090x_OFFST_SDVBS1_PRF_2_FIELD 1 -#define STV090x_WIDTH_SDVBS1_PRF_2_FIELD 1 -#define STV090x_OFFST_SDVBS1_PRF_1_FIELD 0 -#define STV090x_WIDTH_SDVBS1_PRF_1_FIELD 1 - -#define STV090x_IRQSTATUS2 0xf121 -#define STV090x_OFFST_SSPY_ENDSIM_3_FIELD 7 -#define STV090x_WIDTH_SSPY_ENDSIM_3_FIELD 1 -#define STV090x_OFFST_SSPY_ENDSIM_2_FIELD 6 -#define STV090x_WIDTH_SSPY_ENDSIM_2_FIELD 1 -#define STV090x_OFFST_SSPY_ENDSIM_1_FIELD 5 -#define STV090x_WIDTH_SSPY_ENDSIM_1_FIELD 1 -#define STV090x_OFFST_SPKTDEL_ERROR_2_FIELD 4 -#define STV090x_WIDTH_SPKTDEL_ERROR_2_FIELD 1 -#define STV090x_OFFST_SPKTDEL_LOCKB_2_FIELD 3 -#define STV090x_WIDTH_SPKTDEL_LOCKB_2_FIELD 1 -#define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD 2 -#define STV090x_WIDTH_SPKTDEL_LOCK_2_FIELD 1 -#define STV090x_OFFST_SPKTDEL_ERROR_1_FIELD 1 -#define STV090x_WIDTH_SPKTDEL_ERROR_1_FIELD 1 -#define STV090x_OFFST_SPKTDEL_LOCKB_1_FIELD 0 -#define STV090x_WIDTH_SPKTDEL_LOCKB_1_FIELD 1 - -#define STV090x_IRQSTATUS1 0xf122 -#define STV090x_OFFST_SPKTDEL_LOCK_1_FIELD 7 -#define STV090x_WIDTH_SPKTDEL_LOCK_1_FIELD 1 -#define STV090x_OFFST_SDEMOD_LOCKB_2_FIELD 2 -#define STV090x_WIDTH_SDEMOD_LOCKB_2_FIELD 1 -#define STV090x_OFFST_SDEMOD_LOCK_2_FIELD 1 -#define STV090x_WIDTH_SDEMOD_LOCK_2_FIELD 1 -#define STV090x_OFFST_SDEMOD_IRQ_2_FIELD 0 -#define STV090x_WIDTH_SDEMOD_IRQ_2_FIELD 1 - -#define STV090x_IRQSTATUS0 0xf123 -#define STV090x_OFFST_SDEMOD_LOCKB_1_FIELD 7 -#define STV090x_WIDTH_SDEMOD_LOCKB_1_FIELD 1 -#define STV090x_OFFST_SDEMOD_LOCK_1_FIELD 6 -#define STV090x_WIDTH_SDEMOD_LOCK_1_FIELD 1 -#define STV090x_OFFST_SDEMOD_IRQ_1_FIELD 5 -#define STV090x_WIDTH_SDEMOD_IRQ_1_FIELD 1 -#define STV090x_OFFST_SBCH_ERRFLAG_FIELD 4 -#define STV090x_WIDTH_SBCH_ERRFLAG_FIELD 1 -#define STV090x_OFFST_SDISEQC2RX_IRQ_FIELD 3 -#define STV090x_WIDTH_SDISEQC2RX_IRQ_FIELD 1 -#define STV090x_OFFST_SDISEQC2TX_IRQ_FIELD 2 -#define STV090x_WIDTH_SDISEQC2TX_IRQ_FIELD 1 -#define STV090x_OFFST_SDISEQC1RX_IRQ_FIELD 1 -#define STV090x_WIDTH_SDISEQC1RX_IRQ_FIELD 1 -#define STV090x_OFFST_SDISEQC1TX_IRQ_FIELD 0 -#define STV090x_WIDTH_SDISEQC1TX_IRQ_FIELD 1 - -#define STV090x_IRQMASK3 0xf124 -#define STV090x_OFFST_MPLL_LOCK_FIELD 5 -#define STV090x_WIDTH_MPLL_LOCK_FIELD 1 -#define STV090x_OFFST_MSTREAM_LCK_3_FIELD 4 -#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD 1 -#define STV090x_OFFST_MSTREAM_LCK_2_FIELD 3 -#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD 1 -#define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2 -#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD 1 -#define STV090x_OFFST_MDVBS1_PRF_2_FIELD 1 -#define STV090x_WIDTH_MDVBS1_PRF_2_FIELD 1 -#define STV090x_OFFST_MDVBS1_PRF_1_FIELD 0 -#define STV090x_WIDTH_MDVBS1_PRF_1_FIELD 1 - -#define STV090x_IRQMASK2 0xf125 -#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD 7 -#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD 1 -#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD 6 -#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD 1 -#define STV090x_OFFST_MSPY_ENDSIM_1_FIELD 5 -#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD 1 -#define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD 4 -#define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD 1 -#define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD 3 -#define STV090x_WIDTH_MPKTDEL_LOCKB_2_FIELD 1 -#define STV090x_OFFST_MPKTDEL_LOCK_2_FIELD 2 -#define STV090x_WIDTH_MPKTDEL_LOCK_2_FIELD 1 -#define STV090x_OFFST_MPKTDEL_ERROR_1_FIELD 1 -#define STV090x_WIDTH_MPKTDEL_ERROR_1_FIELD 1 -#define STV090x_OFFST_MPKTDEL_LOCKB_1_FIELD 0 -#define STV090x_WIDTH_MPKTDEL_LOCKB_1_FIELD 1 - -#define STV090x_IRQMASK1 0xf126 -#define STV090x_OFFST_MPKTDEL_LOCK_1_FIELD 7 -#define STV090x_WIDTH_MPKTDEL_LOCK_1_FIELD 1 -#define STV090x_OFFST_MEXTPINB2_FIELD 6 -#define STV090x_WIDTH_MEXTPINB2_FIELD 1 -#define STV090x_OFFST_MEXTPIN2_FIELD 5 -#define STV090x_WIDTH_MEXTPIN2_FIELD 1 -#define STV090x_OFFST_MEXTPINB1_FIELD 4 -#define STV090x_WIDTH_MEXTPINB1_FIELD 1 -#define STV090x_OFFST_MEXTPIN1_FIELD 3 -#define STV090x_WIDTH_MEXTPIN1_FIELD 1 -#define STV090x_OFFST_MDEMOD_LOCKB_2_FIELD 2 -#define STV090x_WIDTH_MDEMOD_LOCKB_2_FIELD 1 -#define STV090x_OFFST_MDEMOD_LOCK_2_FIELD 1 -#define STV090x_WIDTH_MDEMOD_LOCK_2_FIELD 1 -#define STV090x_OFFST_MDEMOD_IRQ_2_FIELD 0 -#define STV090x_WIDTH_MDEMOD_IRQ_2_FIELD 1 - -#define STV090x_IRQMASK0 0xf127 -#define STV090x_OFFST_MDEMOD_LOCKB_1_FIELD 7 -#define STV090x_WIDTH_MDEMOD_LOCKB_1_FIELD 1 -#define STV090x_OFFST_MDEMOD_LOCK_1_FIELD 6 -#define STV090x_WIDTH_MDEMOD_LOCK_1_FIELD 1 -#define STV090x_OFFST_MDEMOD_IRQ_1_FIELD 5 -#define STV090x_WIDTH_MDEMOD_IRQ_1_FIELD 1 -#define STV090x_OFFST_MBCH_ERRFLAG_FIELD 4 -#define STV090x_WIDTH_MBCH_ERRFLAG_FIELD 1 -#define STV090x_OFFST_MDISEQC2RX_IRQ_FIELD 3 -#define STV090x_WIDTH_MDISEQC2RX_IRQ_FIELD 1 -#define STV090x_OFFST_MDISEQC2TX_IRQ_FIELD 2 -#define STV090x_WIDTH_MDISEQC2TX_IRQ_FIELD 1 -#define STV090x_OFFST_MDISEQC1RX_IRQ_FIELD 1 -#define STV090x_WIDTH_MDISEQC1RX_IRQ_FIELD 1 -#define STV090x_OFFST_MDISEQC1TX_IRQ_FIELD 0 -#define STV090x_WIDTH_MDISEQC1TX_IRQ_FIELD 1 - -#define STV090x_I2CCFG 0xf129 -#define STV090x_OFFST_12C_FASTMODE_FIELD 3 -#define STV090x_WIDTH_12C_FASTMODE_FIELD 1 -#define STV090x_OFFST_12CADDR_INC_FIELD 0 -#define STV090x_WIDTH_12CADDR_INC_FIELD 2 - -#define STV090x_Px_I2CRPT(__x) (0xf12a + (__x - 1) * 0x1) -#define STV090x_P1_I2CRPT STV090x_Px_I2CRPT(1) -#define STV090x_P2_I2CRPT STV090x_Px_I2CRPT(2) -#define STV090x_OFFST_Px_I2CT_ON_FIELD 7 -#define STV090x_WIDTH_Px_I2CT_ON_FIELD 1 -#define STV090x_OFFST_Px_ENARPT_LEVEL_FIELD 4 -#define STV090x_WIDTH_Px_ENARPT_LEVEL_FIELD 3 -#define STV090x_OFFST_Px_SCLT_DELAY_FIELD 3 -#define STV090x_WIDTH_Px_SCLT_DELAY_FIELD 1 -#define STV090x_OFFST_Px_STOP_ENABLE_FIELD 2 -#define STV090x_WIDTH_Px_STOP_ENABLE_FIELD 1 -#define STV090x_OFFST_Px_STOP_SDAT2SDA_FIELD 1 -#define STV090x_WIDTH_Px_STOP_SDAT2SDA_FIELD 1 - -#define STV090x_CLKI2CFG 0xf140 -#define STV090x_OFFST_CLKI2_OPD_FIELD 7 -#define STV090x_WIDTH_CLKI2_OPD_FIELD 1 -#define STV090x_OFFST_CLKI2_CONFIG_FIELD 1 -#define STV090x_WIDTH_CLKI2_CONFIG_FIELD 6 -#define STV090x_OFFST_CLKI2_XOR_FIELD 0 -#define STV090x_WIDTH_CLKI2_XOR_FIELD 1 - -#define STV090x_GPIOxCFG(__x) (0xf141 + (__x - 1)) -#define STV090x_GPIO1CFG STV090x_GPIOxCFG(1) -#define STV090x_GPIO2CFG STV090x_GPIOxCFG(2) -#define STV090x_GPIO3CFG STV090x_GPIOxCFG(3) -#define STV090x_GPIO4CFG STV090x_GPIOxCFG(4) -#define STV090x_GPIO5CFG STV090x_GPIOxCFG(5) -#define STV090x_GPIO6CFG STV090x_GPIOxCFG(6) -#define STV090x_GPIO7CFG STV090x_GPIOxCFG(7) -#define STV090x_GPIO8CFG STV090x_GPIOxCFG(8) -#define STV090x_GPIO9CFG STV090x_GPIOxCFG(9) -#define STV090x_GPIO10CFG STV090x_GPIOxCFG(10) -#define STV090x_GPIO11CFG STV090x_GPIOxCFG(11) -#define STV090x_GPIO12CFG STV090x_GPIOxCFG(12) -#define STV090x_GPIO13CFG STV090x_GPIOxCFG(13) -#define STV090x_OFFST_GPIOx_OPD_FIELD 7 -#define STV090x_WIDTH_GPIOx_OPD_FIELD 1 -#define STV090x_OFFST_GPIOx_CONFIG_FIELD 1 -#define STV090x_WIDTH_GPIOx_CONFIG_FIELD 6 -#define STV090x_OFFST_GPIOx_XOR_FIELD 0 -#define STV090x_WIDTH_GPIOx_XOR_FIELD 1 - -#define STV090x_CSxCFG(__x) (0xf14e + __x * 0x1) -#define STV090x_CS0CFG STV090x_CSxCFG(0) -#define STV090x_CS1CFG STV090x_CSxCFG(1) -#define STV090x_OFFST_CSX_OPD_FIELD 7 -#define STV090x_WIDTH_CSX_OPD_FIELD 1 -#define STV090x_OFFST_CSX_CONFIG_FIELD 1 -#define STV090x_WIDTH_CSX_CONFIG_FIELD 6 -#define STV090x_OFFST_CSX_XOR_FIELD 0 -#define STV090x_WIDTH_CSX_XOR_FIELD 1 - - -#define STV090x_STDBYCFG 0xf150 -#define STV090x_OFFST_STDBY_OPD_FIELD 7 -#define STV090x_WIDTH_STDBY_OPD_FIELD 1 -#define STV090x_OFFST_STDBY_CONFIG_FIELD 1 -#define STV090x_WIDTH_STDBY_CONFIG_FIELD 6 -#define STV090x_OFFST_STDBY_XOR_FIELD 0 -#define STV090x_WIDTH_STDBY_XOR_FIELD 1 - -#define STV090x_DIRCLKCFG 0xf151 -#define STV090x_OFFST_DIRCLK_OPD_FIELD 7 -#define STV090x_WIDTH_DIRCLK_OPD_FIELD 1 -#define STV090x_OFFST_DIRCLK_CONFIG_FIELD 1 -#define STV090x_WIDTH_DIRCLK_CONFIG_FIELD 6 -#define STV090x_OFFST_DIRCLK_XOR_FIELD 0 -#define STV090x_WIDTH_DIRCLK_XOR_FIELD 1 - - -#define STV090x_AGCRFxCFG(__x) (0xf152 + (__x - 1) * 0x4) -#define STV090x_AGCRF1CFG STV090x_AGCRFxCFG(1) -#define STV090x_AGCRF2CFG STV090x_AGCRFxCFG(2) -#define STV090x_OFFST_AGCRFx_OPD_FIELD 7 -#define STV090x_WIDTH_AGCRFx_OPD_FIELD 1 -#define STV090x_OFFST_AGCRFx_CONFIG_FIELD 1 -#define STV090x_WIDTH_AGCRFx_CONFIG_FIELD 6 -#define STV090x_OFFST_AGCRFx_XOR_FIELD 0 -#define STV090x_WIDTH_AGCRFx_XOR_FIELD 1 - -#define STV090x_SDATxCFG(__x) (0xf153 + (__x - 1) * 0x4) -#define STV090x_SDAT1CFG STV090x_SDATxCFG(1) -#define STV090x_SDAT2CFG STV090x_SDATxCFG(2) -#define STV090x_OFFST_SDATx_OPD_FIELD 7 -#define STV090x_WIDTH_SDATx_OPD_FIELD 1 -#define STV090x_OFFST_SDATx_CONFIG_FIELD 1 -#define STV090x_WIDTH_SDATx_CONFIG_FIELD 6 -#define STV090x_OFFST_SDATx_XOR_FIELD 0 -#define STV090x_WIDTH_SDATx_XOR_FIELD 1 - -#define STV090x_SCLTxCFG(__x) (0xf154 + (__x - 1) * 0x4) -#define STV090x_SCLT1CFG STV090x_SCLTxCFG(1) -#define STV090x_SCLT2CFG STV090x_SCLTxCFG(2) -#define STV090x_OFFST_SCLTx_OPD_FIELD 7 -#define STV090x_WIDTH_SCLTx_OPD_FIELD 1 -#define STV090x_OFFST_SCLTx_CONFIG_FIELD 1 -#define STV090x_WIDTH_SCLTx_CONFIG_FIELD 6 -#define STV090x_OFFST_SCLTx_XOR_FIELD 0 -#define STV090x_WIDTH_SCLTx_XOR_FIELD 1 - -#define STV090x_DISEQCOxCFG(__x) (0xf155 + (__x - 1) * 0x4) -#define STV090x_DISEQCO1CFG STV090x_DISEQCOxCFG(1) -#define STV090x_DISEQCO2CFG STV090x_DISEQCOxCFG(2) -#define STV090x_OFFST_DISEQCOx_OPD_FIELD 7 -#define STV090x_WIDTH_DISEQCOx_OPD_FIELD 1 -#define STV090x_OFFST_DISEQCOx_CONFIG_FIELD 1 -#define STV090x_WIDTH_DISEQCOx_CONFIG_FIELD 6 -#define STV090x_OFFST_DISEQCOx_XOR_FIELD 0 -#define STV090x_WIDTH_DISEQCOx_XOR_FIELD 1 - -#define STV090x_CLKOUT27CFG 0xf15a -#define STV090x_OFFST_CLKOUT27_OPD_FIELD 7 -#define STV090x_WIDTH_CLKOUT27_OPD_FIELD 1 -#define STV090x_OFFST_CLKOUT27_CONFIG_FIELD 1 -#define STV090x_WIDTH_CLKOUT27_CONFIG_FIELD 6 -#define STV090x_OFFST_CLKOUT27_XOR_FIELD 0 -#define STV090x_WIDTH_CLKOUT27_XOR_FIELD 1 - -#define STV090x_ERRORxCFG(__x) (0xf15b + (__x - 1) * 0x5) -#define STV090x_ERROR1CFG STV090x_ERRORxCFG(1) -#define STV090x_ERROR2CFG STV090x_ERRORxCFG(2) -#define STV090x_ERROR3CFG STV090x_ERRORxCFG(3) -#define STV090x_OFFST_ERRORx_OPD_FIELD 7 -#define STV090x_WIDTH_ERRORx_OPD_FIELD 1 -#define STV090x_OFFST_ERRORx_CONFIG_FIELD 1 -#define STV090x_WIDTH_ERRORx_CONFIG_FIELD 6 -#define STV090x_OFFST_ERRORx_XOR_FIELD 0 -#define STV090x_WIDTH_ERRORx_XOR_FIELD 1 - -#define STV090x_DPNxCFG(__x) (0xf15c + (__x - 1) * 0x5) -#define STV090x_DPN1CFG STV090x_DPNxCFG(1) -#define STV090x_DPN2CFG STV090x_DPNxCFG(2) -#define STV090x_DPN3CFG STV090x_DPNxCFG(3) -#define STV090x_OFFST_DPNx_OPD_FIELD 7 -#define STV090x_WIDTH_DPNx_OPD_FIELD 1 -#define STV090x_OFFST_DPNx_CONFIG_FIELD 1 -#define STV090x_WIDTH_DPNx_CONFIG_FIELD 6 -#define STV090x_OFFST_DPNx_XOR_FIELD 0 -#define STV090x_WIDTH_DPNx_XOR_FIELD 1 - -#define STV090x_STROUTxCFG(__x) (0xf15d + (__x - 1) * 0x5) -#define STV090x_STROUT1CFG STV090x_STROUTxCFG(1) -#define STV090x_STROUT2CFG STV090x_STROUTxCFG(2) -#define STV090x_STROUT3CFG STV090x_STROUTxCFG(3) -#define STV090x_OFFST_STROUTx_OPD_FIELD 7 -#define STV090x_WIDTH_STROUTx_OPD_FIELD 1 -#define STV090x_OFFST_STROUTx_CONFIG_FIELD 1 -#define STV090x_WIDTH_STROUTx_CONFIG_FIELD 6 -#define STV090x_OFFST_STROUTx_XOR_FIELD 0 -#define STV090x_WIDTH_STROUTx_XOR_FIELD 1 - -#define STV090x_CLKOUTxCFG(__x) (0xf15e + (__x - 1) * 0x5) -#define STV090x_CLKOUT1CFG STV090x_CLKOUTxCFG(1) -#define STV090x_CLKOUT2CFG STV090x_CLKOUTxCFG(2) -#define STV090x_CLKOUT3CFG STV090x_CLKOUTxCFG(3) -#define STV090x_OFFST_CLKOUTx_OPD_FIELD 7 -#define STV090x_WIDTH_CLKOUTx_OPD_FIELD 1 -#define STV090x_OFFST_CLKOUTx_CONFIG_FIELD 1 -#define STV090x_WIDTH_CLKOUTx_CONFIG_FIELD 6 -#define STV090x_OFFST_CLKOUTx_XOR_FIELD 0 -#define STV090x_WIDTH_CLKOUTx_XOR_FIELD 1 - -#define STV090x_DATAxCFG(__x) (0xf15f + (__x - 71) * 0x5) -#define STV090x_DATA71CFG STV090x_DATAxCFG(71) -#define STV090x_DATA72CFG STV090x_DATAxCFG(72) -#define STV090x_DATA73CFG STV090x_DATAxCFG(73) -#define STV090x_OFFST_DATAx_OPD_FIELD 7 -#define STV090x_WIDTH_DATAx_OPD_FIELD 1 -#define STV090x_OFFST_DATAx_CONFIG_FIELD 1 -#define STV090x_WIDTH_DATAx_CONFIG_FIELD 6 -#define STV090x_OFFST_DATAx_XOR_FIELD 0 -#define STV090x_WIDTH_DATAx_XOR_FIELD 1 - -#define STV090x_NCOARSE 0xf1b3 -#define STV090x_OFFST_M_DIV_FIELD 0 -#define STV090x_WIDTH_M_DIV_FIELD 8 - -#define STV090x_SYNTCTRL 0xf1b6 -#define STV090x_OFFST_STANDBY_FIELD 7 -#define STV090x_WIDTH_STANDBY_FIELD 1 -#define STV090x_OFFST_BYPASSPLLCORE_FIELD 6 -#define STV090x_WIDTH_BYPASSPLLCORE_FIELD 1 -#define STV090x_OFFST_SELX1RATIO_FIELD 5 -#define STV090x_WIDTH_SELX1RATIO_FIELD 1 -#define STV090x_OFFST_STOP_PLL_FIELD 3 -#define STV090x_WIDTH_STOP_PLL_FIELD 1 -#define STV090x_OFFST_BYPASSPLLFSK_FIELD 2 -#define STV090x_WIDTH_BYPASSPLLFSK_FIELD 1 -#define STV090x_OFFST_SELOSCI_FIELD 1 -#define STV090x_WIDTH_SELOSCI_FIELD 1 -#define STV090x_OFFST_BYPASSPLLADC_FIELD 0 -#define STV090x_WIDTH_BYPASSPLLADC_FIELD 1 - -#define STV090x_FILTCTRL 0xf1b7 -#define STV090x_OFFST_INV_CLK135_FIELD 7 -#define STV090x_WIDTH_INV_CLK135_FIELD 1 -#define STV090x_OFFST_SEL_FSKCKDIV_FIELD 2 -#define STV090x_WIDTH_SEL_FSKCKDIV_FIELD 1 -#define STV090x_OFFST_INV_CLKFSK_FIELD 1 -#define STV090x_WIDTH_INV_CLKFSK_FIELD 1 -#define STV090x_OFFST_BYPASS_APPLI_FIELD 0 -#define STV090x_WIDTH_BYPASS_APPLI_FIELD 1 - -#define STV090x_PLLSTAT 0xf1b8 -#define STV090x_OFFST_PLLLOCK_FIELD 0 -#define STV090x_WIDTH_PLLLOCK_FIELD 1 - -#define STV090x_STOPCLK1 0xf1c2 -#define STV090x_OFFST_STOP_CLKPKDT2_FIELD 6 -#define STV090x_WIDTH_STOP_CLKPKDT2_FIELD 1 -#define STV090x_OFFST_STOP_CLKPKDT1_FIELD 5 -#define STV090x_WIDTH_STOP_CLKPKDT1_FIELD 1 -#define STV090x_OFFST_STOP_CLKFEC_FIELD 4 -#define STV090x_WIDTH_STOP_CLKFEC_FIELD 1 -#define STV090x_OFFST_STOP_CLKADCI2_FIELD 3 -#define STV090x_WIDTH_STOP_CLKADCI2_FIELD 1 -#define STV090x_OFFST_INV_CLKADCI2_FIELD 2 -#define STV090x_WIDTH_INV_CLKADCI2_FIELD 1 -#define STV090x_OFFST_STOP_CLKADCI1_FIELD 1 -#define STV090x_WIDTH_STOP_CLKADCI1_FIELD 1 -#define STV090x_OFFST_INV_CLKADCI1_FIELD 0 -#define STV090x_WIDTH_INV_CLKADCI1_FIELD 1 - -#define STV090x_STOPCLK2 0xf1c3 -#define STV090x_OFFST_STOP_CLKSAMP2_FIELD 4 -#define STV090x_WIDTH_STOP_CLKSAMP2_FIELD 1 -#define STV090x_OFFST_STOP_CLKSAMP1_FIELD 3 -#define STV090x_WIDTH_STOP_CLKSAMP1_FIELD 1 -#define STV090x_OFFST_STOP_CLKVIT2_FIELD 2 -#define STV090x_WIDTH_STOP_CLKVIT2_FIELD 1 -#define STV090x_OFFST_STOP_CLKVIT1_FIELD 1 -#define STV090x_WIDTH_STOP_CLKVIT1_FIELD 1 -#define STV090x_OFFST_STOP_CLKTS_FIELD 0 -#define STV090x_WIDTH_STOP_CLKTS_FIELD 1 - -#define STV090x_TSTTNR0 0xf1df -#define STV090x_OFFST_SEL_FSK_FIELD 7 -#define STV090x_WIDTH_SEL_FSK_FIELD 1 -#define STV090x_OFFST_FSK_PON_FIELD 2 -#define STV090x_WIDTH_FSK_PON_FIELD 1 - -#define STV090x_TSTTNR1 0xf1e0 -#define STV090x_OFFST_ADC1_PON_FIELD 1 -#define STV090x_WIDTH_ADC1_PON_FIELD 1 -#define STV090x_OFFST_ADC1_INMODE_FIELD 0 -#define STV090x_WIDTH_ADC1_INMODE_FIELD 1 - -#define STV090x_TSTTNR2 0xf1e1 -#define STV090x_OFFST_DISEQC1_PON_FIELD 5 -#define STV090x_WIDTH_DISEQC1_PON_FIELD 1 - -#define STV090x_TSTTNR3 0xf1e2 -#define STV090x_OFFST_ADC2_PON_FIELD 1 -#define STV090x_WIDTH_ADC2_PON_FIELD 1 -#define STV090x_OFFST_ADC2_INMODE_FIELD 0 -#define STV090x_WIDTH_ADC2_INMODE_FIELD 1 - -#define STV090x_TSTTNR4 0xf1e3 -#define STV090x_OFFST_DISEQC2_PON_FIELD 5 -#define STV090x_WIDTH_DISEQC2_PON_FIELD 1 - -#define STV090x_FSKTFC2 0xf170 -#define STV090x_OFFST_FSKT_KMOD_FIELD 2 -#define STV090x_WIDTH_FSKT_KMOD_FIELD 6 -#define STV090x_OFFST_FSKT_CAR_FIELD 0 -#define STV090x_WIDTH_FSKT_CAR_FIELD 2 - -#define STV090x_FSKTFC1 0xf171 -#define STV090x_OFFST_FSKTC1_CAR_FIELD 0 -#define STV090x_WIDTH_FSKTC1_CAR_FIELD 8 - -#define STV090x_FSKTFC0 0xf172 -#define STV090x_OFFST_FSKTC0_CAR_FIELD 0 -#define STV090x_WIDTH_FSKTC0_CAR_FIELD 8 - -#define STV090x_FSKTDELTAF1 0xf173 -#define STV090x_OFFST_FSKTF1_DELTAF_FIELD 0 -#define STV090x_WIDTH_FSKTF1_DELTAF_FIELD 4 - -#define STV090x_FSKTDELTAF0 0xf174 -#define STV090x_OFFST_FSKTF0_DELTAF_FIELD 0 -#define STV090x_WIDTH_FSKTF0_DELTAF_FIELD 8 - -#define STV090x_FSKTCTRL 0xf175 -#define STV090x_OFFST_FSKT_EN_SGN_FIELD 6 -#define STV090x_WIDTH_FSKT_EN_SGN_FIELD 1 -#define STV090x_OFFST_FSKT_MOD_SGN_FIELD 5 -#define STV090x_WIDTH_FSKT_MOD_SGN_FIELD 1 -#define STV090x_OFFST_FSKT_MOD_EN_FIELD 2 -#define STV090x_WIDTH_FSKT_MOD_EN_FIELD 3 -#define STV090x_OFFST_FSKT_DACMODE_FIELD 0 -#define STV090x_WIDTH_FSKT_DACMODE_FIELD 2 - -#define STV090x_FSKRFC2 0xf176 -#define STV090x_OFFST_FSKRC2_DETSGN_FIELD 6 -#define STV090x_WIDTH_FSKRC2_DETSGN_FIELD 1 -#define STV090x_OFFST_FSKRC2_OUTSGN_FIELD 5 -#define STV090x_WIDTH_FSKRC2_OUTSGN_FIELD 1 -#define STV090x_OFFST_FSKRC2_KAGC_FIELD 2 -#define STV090x_WIDTH_FSKRC2_KAGC_FIELD 3 -#define STV090x_OFFST_FSKRC2_CAR_FIELD 0 -#define STV090x_WIDTH_FSKRC2_CAR_FIELD 2 - -#define STV090x_FSKRFC1 0xf177 -#define STV090x_OFFST_FSKRC1_CAR_FIELD 0 -#define STV090x_WIDTH_FSKRC1_CAR_FIELD 8 - -#define STV090x_FSKRFC0 0xf178 -#define STV090x_OFFST_FSKRC0_CAR_FIELD 0 -#define STV090x_WIDTH_FSKRC0_CAR_FIELD 8 - -#define STV090x_FSKRK1 0xf179 -#define STV090x_OFFST_FSKR_K1_EXP_FIELD 5 -#define STV090x_WIDTH_FSKR_K1_EXP_FIELD 3 -#define STV090x_OFFST_FSKR_K1_MANT_FIELD 0 -#define STV090x_WIDTH_FSKR_K1_MANT_FIELD 5 - -#define STV090x_FSKRK2 0xf17a -#define STV090x_OFFST_FSKR_K2_EXP_FIELD 5 -#define STV090x_WIDTH_FSKR_K2_EXP_FIELD 3 -#define STV090x_OFFST_FSKR_K2_MANT_FIELD 0 -#define STV090x_WIDTH_FSKR_K2_MANT_FIELD 5 - -#define STV090x_FSKRAGCR 0xf17b -#define STV090x_OFFST_FSKR_OUTCTL_FIELD 6 -#define STV090x_WIDTH_FSKR_OUTCTL_FIELD 2 -#define STV090x_OFFST_FSKR_AGC_REF_FIELD 0 -#define STV090x_WIDTH_FSKR_AGC_REF_FIELD 6 - -#define STV090x_FSKRAGC 0xf17c -#define STV090x_OFFST_FSKR_AGC_ACCU_FIELD 0 -#define STV090x_WIDTH_FSKR_AGC_ACCU_FIELD 8 - -#define STV090x_FSKRALPHA 0xf17d -#define STV090x_OFFST_FSKR_ALPHA_EXP_FIELD 2 -#define STV090x_WIDTH_FSKR_ALPHA_EXP_FIELD 3 -#define STV090x_OFFST_FSKR_ALPHA_M_FIELD 0 -#define STV090x_WIDTH_FSKR_ALPHA_M_FIELD 2 - -#define STV090x_FSKRPLTH1 0xf17e -#define STV090x_OFFST_FSKR_BETA_FIELD 4 -#define STV090x_WIDTH_FSKR_BETA_FIELD 4 -#define STV090x_OFFST_FSKR_PLL_TRESH1_FIELD 0 -#define STV090x_WIDTH_FSKR_PLL_TRESH1_FIELD 4 - -#define STV090x_FSKRPLTH0 0xf17f -#define STV090x_OFFST_FSKR_PLL_TRESH0_FIELD 0 -#define STV090x_WIDTH_FSKR_PLL_TRESH0_FIELD 8 - -#define STV090x_FSKRDF1 0xf180 -#define STV090x_OFFST_FSKR_DELTAF1_FIELD 0 -#define STV090x_WIDTH_FSKR_DELTAF1_FIELD 5 - -#define STV090x_FSKRDF0 0xf181 -#define STV090x_OFFST_FSKR_DELTAF0_FIELD 0 -#define STV090x_WIDTH_FSKR_DELTAF0_FIELD 8 - -#define STV090x_FSKRSTEPP 0xf182 -#define STV090x_OFFST_FSKR_STEP_PLUS_FIELD 0 -#define STV090x_WIDTH_FSKR_STEP_PLUS_FIELD 8 - -#define STV090x_FSKRSTEPM 0xf183 -#define STV090x_OFFST_FSKR_STEP_MINUS_FIELD 0 -#define STV090x_WIDTH_FSKR_STEP_MINUS_FIELD 8 - -#define STV090x_FSKRDET1 0xf184 -#define STV090x_OFFST_FSKR_CARDET1_ACCU_FIELD 0 -#define STV090x_WIDTH_FSKR_CARDET1_ACCU_FIELD 4 - -#define STV090x_FSKRDET0 0xf185 -#define STV090x_OFFST_FSKR_CARDET0_ACCU_FIELD 0 -#define STV090x_WIDTH_FSKR_CARDET0_ACCU_FIELD 8 - -#define STV090x_FSKRDTH1 0xf186 -#define STV090x_OFFST_FSKR_CARLOSS_THRESH1_FIELD 4 -#define STV090x_WIDTH_FSKR_CARLOSS_THRESH1_FIELD 4 -#define STV090x_OFFST_FSKR_CARDET_THRESH1_FIELD 0 -#define STV090x_WIDTH_FSKR_CARDET_THRESH1_FIELD 4 - -#define STV090x_FSKRDTH0 0xf187 -#define STV090x_OFFST_FSKR_CARDET_THRESH0_FIELD 0 -#define STV090x_WIDTH_FSKR_CARDET_THRESH0_FIELD 8 - -#define STV090x_FSKRLOSS 0xf188 -#define STV090x_OFFST_FSKR_CARLOSS_THRESH_FIELD 0 -#define STV090x_WIDTH_FSKR_CARLOSS_THRESH_FIELD 8 - -#define STV090x_Px_DISTXCTL(__x) (0xF1A0 - (__x - 1) * 0x10) -#define STV090x_P1_DISTXCTL STV090x_Px_DISTXCTL(1) -#define STV090x_P2_DISTXCTL STV090x_Px_DISTXCTL(2) -#define STV090x_OFFST_Px_TIM_OFF_FIELD 7 -#define STV090x_WIDTH_Px_TIM_OFF_FIELD 1 -#define STV090x_OFFST_Px_DISEQC_RESET_FIELD 6 -#define STV090x_WIDTH_Px_DISEQC_RESET_FIELD 1 -#define STV090x_OFFST_Px_TIM_CMD_FIELD 4 -#define STV090x_WIDTH_Px_TIM_CMD_FIELD 2 -#define STV090x_OFFST_Px_DIS_PRECHARGE_FIELD 3 -#define STV090x_WIDTH_Px_DIS_PRECHARGE_FIELD 1 -#define STV090x_OFFST_Px_DISTX_MODE_FIELD 0 -#define STV090x_WIDTH_Px_DISTX_MODE_FIELD 3 - -#define STV090x_Px_DISRXCTL(__x) (0xf1a1 - (__x - 1) * 0x10) -#define STV090x_P1_DISRXCTL STV090x_Px_DISRXCTL(1) -#define STV090x_P2_DISRXCTL STV090x_Px_DISRXCTL(2) -#define STV090x_OFFST_Px_RECEIVER_ON_FIELD 7 -#define STV090x_WIDTH_Px_RECEIVER_ON_FIELD 1 -#define STV090x_OFFST_Px_IGNO_SHORT22K_FIELD 6 -#define STV090x_WIDTH_Px_IGNO_SHORT22K_FIELD 1 -#define STV090x_OFFST_Px_ONECHIP_TRX_FIELD 5 -#define STV090x_WIDTH_Px_ONECHIP_TRX_FIELD 1 -#define STV090x_OFFST_Px_EXT_ENVELOP_FIELD 4 -#define STV090x_WIDTH_Px_EXT_ENVELOP_FIELD 1 -#define STV090x_OFFST_Px_PIN_SELECT_FIELD 2 -#define STV090x_WIDTH_Px_PIN_SELECT_FIELD 2 -#define STV090x_OFFST_Px_IRQ_RXEND_FIELD 1 -#define STV090x_WIDTH_Px_IRQ_RXEND_FIELD 1 -#define STV090x_OFFST_Px_IRQ_4NBYTES_FIELD 0 -#define STV090x_WIDTH_Px_IRQ_4NBYTES_FIELD 1 - -#define STV090x_Px_DISRX_ST0(__x) (0xf1a4 - (__x - 1) * 0x10) -#define STV090x_P1_DISRX_ST0 STV090x_Px_DISRX_ST0(1) -#define STV090x_P2_DISRX_ST0 STV090x_Px_DISRX_ST0(2) -#define STV090x_OFFST_Px_RX_END_FIELD 7 -#define STV090x_WIDTH_Px_RX_END_FIELD 1 -#define STV090x_OFFST_Px_RX_ACTIVE_FIELD 6 -#define STV090x_WIDTH_Px_RX_ACTIVE_FIELD 1 -#define STV090x_OFFST_Px_SHORT_22KHZ_FIELD 5 -#define STV090x_WIDTH_Px_SHORT_22KHZ_FIELD 1 -#define STV090x_OFFST_Px_CONT_TONE_FIELD 4 -#define STV090x_WIDTH_Px_CONT_TONE_FIELD 1 -#define STV090x_OFFST_Px_FIFO_4BREADY_FIELD 3 -#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD 1 -#define STV090x_OFFST_Px_FIFO_EMPTY_FIELD 2 -#define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD 1 -#define STV090x_OFFST_Px_ABORT_DISRX_FIELD 0 -#define STV090x_WIDTH_Px_ABORT_DISRX_FIELD 1 - -#define STV090x_Px_DISRX_ST1(__x) (0xf1a5 - (__x - 1) * 0x10) -#define STV090x_P1_DISRX_ST1 STV090x_Px_DISRX_ST1(1) -#define STV090x_P2_DISRX_ST1 STV090x_Px_DISRX_ST1(2) -#define STV090x_OFFST_Px_RX_FAIL_FIELD 7 -#define STV090x_WIDTH_Px_RX_FAIL_FIELD 1 -#define STV090x_OFFST_Px_FIFO_PARITYFAIL_FIELD 6 -#define STV090x_WIDTH_Px_FIFO_PARITYFAIL_FIELD 1 -#define STV090x_OFFST_Px_RX_NONBYTE_FIELD 5 -#define STV090x_WIDTH_Px_RX_NONBYTE_FIELD 1 -#define STV090x_OFFST_Px_FIFO_OVERFLOW_FIELD 4 -#define STV090x_WIDTH_Px_FIFO_OVERFLOW_FIELD 1 -#define STV090x_OFFST_Px_FIFO_BYTENBR_FIELD 0 -#define STV090x_WIDTH_Px_FIFO_BYTENBR_FIELD 4 - -#define STV090x_Px_DISRXDATA(__x) (0xf1a6 - (__x - 1) * 0x10) -#define STV090x_P1_DISRXDATA STV090x_Px_DISRXDATA(1) -#define STV090x_P2_DISRXDATA STV090x_Px_DISRXDATA(2) -#define STV090x_OFFST_Px_DISRX_DATA_FIELD 0 -#define STV090x_WIDTH_Px_DISRX_DATA_FIELD 8 - -#define STV090x_Px_DISTXDATA(__x) (0xf1a7 - (__x - 1) * 0x10) -#define STV090x_P1_DISTXDATA STV090x_Px_DISTXDATA(1) -#define STV090x_P2_DISTXDATA STV090x_Px_DISTXDATA(2) -#define STV090x_OFFST_Px_DISEQC_FIFO_FIELD 0 -#define STV090x_WIDTH_Px_DISEQC_FIFO_FIELD 8 - -#define STV090x_Px_DISTXSTATUS(__x) (0xf1a8 - (__x - 1) * 0x10) -#define STV090x_P1_DISTXSTATUS STV090x_Px_DISTXSTATUS(1) -#define STV090x_P2_DISTXSTATUS STV090x_Px_DISTXSTATUS(2) -#define STV090x_OFFST_Px_TX_FAIL_FIELD 7 -#define STV090x_WIDTH_Px_TX_FAIL_FIELD 1 -#define STV090x_OFFST_Px_FIFO_FULL_FIELD 6 -#define STV090x_WIDTH_Px_FIFO_FULL_FIELD 1 -#define STV090x_OFFST_Px_TX_IDLE_FIELD 5 -#define STV090x_WIDTH_Px_TX_IDLE_FIELD 1 -#define STV090x_OFFST_Px_GAP_BURST_FIELD 4 -#define STV090x_WIDTH_Px_GAP_BURST_FIELD 1 -#define STV090x_OFFST_Px_TXFIFO_BYTES_FIELD 0 -#define STV090x_WIDTH_Px_TXFIFO_BYTES_FIELD 4 - -#define STV090x_Px_F22TX(__x) (0xf1a9 - (__x - 1) * 0x10) -#define STV090x_P1_F22TX STV090x_Px_F22TX(1) -#define STV090x_P2_F22TX STV090x_Px_F22TX(2) -#define STV090x_OFFST_Px_F22_REG_FIELD 0 -#define STV090x_WIDTH_Px_F22_REG_FIELD 8 - -#define STV090x_Px_F22RX(__x) (0xf1aa - (__x - 1) * 0x10) -#define STV090x_P1_F22RX STV090x_Px_F22RX(1) -#define STV090x_P2_F22RX STV090x_Px_F22RX(2) -#define STV090x_OFFST_Px_F22RX_REG_FIELD 0 -#define STV090x_WIDTH_Px_F22RX_REG_FIELD 8 - -#define STV090x_Px_ACRPRESC(__x) (0xf1ac - (__x - 1) * 0x10) -#define STV090x_P1_ACRPRESC STV090x_Px_ACRPRESC(1) -#define STV090x_P2_ACRPRESC STV090x_Px_ACRPRESC(2) -#define STV090x_OFFST_Px_ACR_PRESC_FIELD 0 -#define STV090x_WIDTH_Px_ACR_PRESC_FIELD 3 - -#define STV090x_Px_ACRDIV(__x) (0xf1ad - (__x - 1) * 0x10) -#define STV090x_P1_ACRDIV STV090x_Px_ACRDIV(1) -#define STV090x_P2_ACRDIV STV090x_Px_ACRDIV(2) -#define STV090x_OFFST_Px_ACR_DIV_FIELD 0 -#define STV090x_WIDTH_Px_ACR_DIV_FIELD 8 - -#define STV090x_Px_IQCONST(__x) (0xF400 - (__x - 1) * 0x200) -#define STV090x_P1_IQCONST STV090x_Px_IQCONST(1) -#define STV090x_P2_IQCONST STV090x_Px_IQCONST(2) -#define STV090x_OFFST_Px_CONSTEL_SELECT_FIELD 5 -#define STV090x_WIDTH_Px_CONSTEL_SELECT_FIELD 2 - -#define STV090x_Px_NOSCFG(__x) (0xF401 - (__x - 1) * 0x200) -#define STV090x_P1_NOSCFG STV090x_Px_NOSCFG(1) -#define STV090x_P2_NOSCFG STV090x_Px_NOSCFG(2) -#define STV090x_OFFST_Px_NOSPLH_BETA_FIELD 3 -#define STV090x_WIDTH_Px_NOSPLH_BETA_FIELD 2 -#define STV090x_OFFST_Px_NOSDATA_BETA_FIELD 0 -#define STV090x_WIDTH_Px_NOSDATA_BETA_FIELD 3 - -#define STV090x_Px_ISYMB(__x) (0xF402 - (__x - 1) * 0x200) -#define STV090x_P1_ISYMB STV090x_Px_ISYMB(1) -#define STV090x_P2_ISYMB STV090x_Px_ISYMB(2) -#define STV090x_OFFST_Px_I_SYMBOL_FIELD 0 -#define STV090x_WIDTH_Px_I_SYMBOL_FIELD 8 - -#define STV090x_Px_QSYMB(__x) (0xF403 - (__x - 1) * 0x200) -#define STV090x_P1_QSYMB STV090x_Px_QSYMB(1) -#define STV090x_P2_QSYMB STV090x_Px_QSYMB(2) -#define STV090x_OFFST_Px_Q_SYMBOL_FIELD 0 -#define STV090x_WIDTH_Px_Q_SYMBOL_FIELD 8 - -#define STV090x_Px_AGC1CFG(__x) (0xF404 - (__x - 1) * 0x200) -#define STV090x_P1_AGC1CFG STV090x_Px_AGC1CFG(1) -#define STV090x_P2_AGC1CFG STV090x_Px_AGC1CFG(2) -#define STV090x_OFFST_Px_DC_FROZEN_FIELD 7 -#define STV090x_WIDTH_Px_DC_FROZEN_FIELD 1 -#define STV090x_OFFST_Px_DC_CORRECT_FIELD 6 -#define STV090x_WIDTH_Px_DC_CORRECT_FIELD 1 -#define STV090x_OFFST_Px_AMM_FROZEN_FIELD 5 -#define STV090x_WIDTH_Px_AMM_FROZEN_FIELD 1 -#define STV090x_OFFST_Px_AMM_CORRECT_FIELD 4 -#define STV090x_WIDTH_Px_AMM_CORRECT_FIELD 1 -#define STV090x_OFFST_Px_QUAD_FROZEN_FIELD 3 -#define STV090x_WIDTH_Px_QUAD_FROZEN_FIELD 1 -#define STV090x_OFFST_Px_QUAD_CORRECT_FIELD 2 -#define STV090x_WIDTH_Px_QUAD_CORRECT_FIELD 1 - -#define STV090x_Px_AGC1CN(__x) (0xF406 - (__x - 1) * 0x200) -#define STV090x_P1_AGC1CN STV090x_Px_AGC1CN(1) -#define STV090x_P2_AGC1CN STV090x_Px_AGC1CN(2) -#define STV090x_WIDTH_Px_AGC1_LOCKED_FIELD 7 -#define STV090x_OFFST_Px_AGC1_LOCKED_FIELD 1 -#define STV090x_OFFST_Px_AGC1_MINPOWER_FIELD 4 -#define STV090x_WIDTH_Px_AGC1_MINPOWER_FIELD 1 -#define STV090x_OFFST_Px_AGCOUT_FAST_FIELD 3 -#define STV090x_WIDTH_Px_AGCOUT_FAST_FIELD 1 -#define STV090x_OFFST_Px_AGCIQ_BETA_FIELD 0 -#define STV090x_WIDTH_Px_AGCIQ_BETA_FIELD 3 - -#define STV090x_Px_AGC1REF(__x) (0xF407 - (__x - 1) * 0x200) -#define STV090x_P1_AGC1REF STV090x_Px_AGC1REF(1) -#define STV090x_P2_AGC1REF STV090x_Px_AGC1REF(2) -#define STV090x_OFFST_Px_AGCIQ_REF_FIELD 0 -#define STV090x_WIDTH_Px_AGCIQ_REF_FIELD 8 - -#define STV090x_Px_IDCCOMP(__x) (0xF408 - (__x - 1) * 0x200) -#define STV090x_P1_IDCCOMP STV090x_Px_IDCCOMP(1) -#define STV090x_P2_IDCCOMP STV090x_Px_IDCCOMP(2) -#define STV090x_OFFST_Px_IAVERAGE_ADJ_FIELD 0 -#define STV090x_WIDTH_Px_IAVERAGE_ADJ_FIELD 8 - -#define STV090x_Px_QDCCOMP(__x) (0xF409 - (__x - 1) * 0x200) -#define STV090x_P1_QDCCOMP STV090x_Px_QDCCOMP(1) -#define STV090x_P2_QDCCOMP STV090x_Px_QDCCOMP(2) -#define STV090x_OFFST_Px_QAVERAGE_ADJ_FIELD 0 -#define STV090x_WIDTH_Px_QAVERAGE_ADJ_FIELD 8 - -#define STV090x_Px_POWERI(__x) (0xF40A - (__x - 1) * 0x200) -#define STV090x_P1_POWERI STV090x_Px_POWERI(1) -#define STV090x_P2_POWERI STV090x_Px_POWERI(2) -#define STV090x_OFFST_Px_POWER_I_FIELD 0 -#define STV090x_WIDTH_Px_POWER_I_FIELD 8 - -#define STV090x_Px_POWERQ(__x) (0xF40B - (__x - 1) * 0x200) -#define STV090x_P1_POWERQ STV090x_Px_POWERQ(1) -#define STV090x_P2_POWERQ STV090x_Px_POWERQ(2) -#define STV090x_OFFST_Px_POWER_Q_FIELD 0 -#define STV090x_WIDTH_Px_POWER_Q_FIELD 8 - -#define STV090x_Px_AGC1AMM(__x) (0xF40C - (__x - 1) * 0x200) -#define STV090x_P1_AGC1AMM STV090x_Px_AGC1AMM(1) -#define STV090x_P2_AGC1AMM STV090x_Px_AGC1AMM(2) -#define STV090x_OFFST_Px_AMM_VALUE_FIELD 0 -#define STV090x_WIDTH_Px_AMM_VALUE_FIELD 8 - -#define STV090x_Px_AGC1QUAD(__x) (0xF40D - (__x - 1) * 0x200) -#define STV090x_P1_AGC1QUAD STV090x_Px_AGC1QUAD(1) -#define STV090x_P2_AGC1QUAD STV090x_Px_AGC1QUAD(2) -#define STV090x_OFFST_Px_QUAD_VALUE_FIELD 0 -#define STV090x_WIDTH_Px_QUAD_VALUE_FIELD 8 - -#define STV090x_Px_AGCIQINy(__x, __y) (0xF40F - (__x-1) * 0x200 - __y * 0x1) -#define STV090x_P1_AGCIQIN0 STV090x_Px_AGCIQINy(1, 0) -#define STV090x_P1_AGCIQIN1 STV090x_Px_AGCIQINy(1, 1) -#define STV090x_P2_AGCIQIN0 STV090x_Px_AGCIQINy(2, 0) -#define STV090x_P2_AGCIQIN1 STV090x_Px_AGCIQINy(2, 1) -#define STV090x_OFFST_Px_AGCIQ_VALUE_FIELD 0 -#define STV090x_WIDTH_Px_AGCIQ_VALUE_FIELD 8 - -#define STV090x_Px_DEMOD(__x) (0xF410 - (__x - 1) * 0x200) -#define STV090x_P1_DEMOD STV090x_Px_DEMOD(1) -#define STV090x_P2_DEMOD STV090x_Px_DEMOD(2) -#define STV090x_OFFST_Px_MANUAL_S2ROLLOFF_FIELD 7 -#define STV090x_WIDTH_Px_MANUAL_S2ROLLOFF_FIELD 1 -#define STV090x_OFFST_Px_DEMOD_STOP_FIELD 6 -#define STV090x_WIDTH_Px_DEMOD_STOP_FIELD 1 -#define STV090x_OFFST_Px_SPECINV_CONTROL_FIELD 4 -#define STV090x_WIDTH_Px_SPECINV_CONTROL_FIELD 2 -#define STV090x_OFFST_Px_FORCE_ENASAMP_FIELD 3 -#define STV090x_WIDTH_Px_FORCE_ENASAMP_FIELD 1 -#define STV090x_OFFST_Px_MANUAL_SXROLLOFF_FIELD 2 -#define STV090x_WIDTH_Px_MANUAL_SXROLLOFF_FIELD 1 -#define STV090x_OFFST_Px_ROLLOFF_CONTROL_FIELD 0 -#define STV090x_WIDTH_Px_ROLLOFF_CONTROL_FIELD 2 - -#define STV090x_Px_DMDMODCOD(__x) (0xF411 - (__x - 1) * 0x200) -#define STV090x_P1_DMDMODCOD STV090x_Px_DMDMODCOD(1) -#define STV090x_P2_DMDMODCOD STV090x_Px_DMDMODCOD(2) -#define STV090x_OFFST_Px_MANUAL_MODCOD_FIELD 7 -#define STV090x_WIDTH_Px_MANUAL_MODCOD_FIELD 1 -#define STV090x_OFFST_Px_DEMOD_MODCOD_FIELD 2 -#define STV090x_WIDTH_Px_DEMOD_MODCOD_FIELD 5 -#define STV090x_OFFST_Px_DEMOD_TYPE_FIELD 0 -#define STV090x_WIDTH_Px_DEMOD_TYPE_FIELD 2 - -#define STV090x_Px_DSTATUS(__x) (0xF412 - (__x - 1) * 0x200) -#define STV090x_P1_DSTATUS STV090x_Px_DSTATUS(1) -#define STV090x_P2_DSTATUS STV090x_Px_DSTATUS(2) -#define STV090x_OFFST_Px_CAR_LOCK_FIELD 7 -#define STV090x_WIDTH_Px_CAR_LOCK_FIELD 1 -#define STV090x_OFFST_Px_TMGLOCK_QUALITY_FIELD 5 -#define STV090x_WIDTH_Px_TMGLOCK_QUALITY_FIELD 2 -#define STV090x_OFFST_Px_LOCK_DEFINITIF_FIELD 3 -#define STV090x_WIDTH_Px_LOCK_DEFINITIF_FIELD 1 - -#define STV090x_Px_DSTATUS2(__x) (0xF413 - (__x - 1) * 0x200) -#define STV090x_P1_DSTATUS2 STV090x_Px_DSTATUS2(1) -#define STV090x_P2_DSTATUS2 STV090x_Px_DSTATUS2(2) -#define STV090x_OFFST_Px_DEMOD_DELOCK_FIELD 7 -#define STV090x_WIDTH_Px_DEMOD_DELOCK_FIELD 1 -#define STV090x_OFFST_Px_AGC1_NOSIGNALACK_FIELD 3 -#define STV090x_WIDTH_Px_AGC1_NOSIGNALACK_FIELD 1 -#define STV090x_OFFST_Px_AGC2_OVERFLOW_FIELD 2 -#define STV090x_WIDTH_Px_AGC2_OVERFLOW_FIELD 1 -#define STV090x_OFFST_Px_CFR_OVERFLOW_FIELD 1 -#define STV090x_WIDTH_Px_CFR_OVERFLOW_FIELD 1 -#define STV090x_OFFST_Px_GAMMA_OVERUNDER_FIELD 0 -#define STV090x_WIDTH_Px_GAMMA_OVERUNDER_FIELD 1 - -#define STV090x_Px_DMDCFGMD(__x) (0xF414 - (__x - 1) * 0x200) -#define STV090x_P1_DMDCFGMD STV090x_Px_DMDCFGMD(1) -#define STV090x_P2_DMDCFGMD STV090x_Px_DMDCFGMD(2) -#define STV090x_OFFST_Px_DVBS2_ENABLE_FIELD 7 -#define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD 1 -#define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD 6 -#define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD 1 -#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD 4 -#define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD 1 -#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD 3 -#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD 1 -#define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD 2 -#define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD 1 -#define STV090x_OFFST_Px_TUN_RNG_FIELD 0 -#define STV090x_WIDTH_Px_TUN_RNG_FIELD 2 - -#define STV090x_Px_DMDCFG2(__x) (0xF415 - (__x - 1) * 0x200) -#define STV090x_P1_DMDCFG2 STV090x_Px_DMDCFG2(1) -#define STV090x_P2_DMDCFG2 STV090x_Px_DMDCFG2(2) -#define STV090x_OFFST_Px_S1S2_SEQUENTIAL_FIELD 6 -#define STV090x_WIDTH_Px_S1S2_SEQUENTIAL_FIELD 1 - -#define STV090x_Px_DMDISTATE(__x) (0xF416 - (__x - 1) * 0x200) -#define STV090x_P1_DMDISTATE STV090x_Px_DMDISTATE(1) -#define STV090x_P2_DMDISTATE STV090x_Px_DMDISTATE(2) -#define STV090x_OFFST_Px_I2C_DEMOD_MODE_FIELD 0 -#define STV090x_WIDTH_Px_I2C_DEMOD_MODE_FIELD 5 - -#define STV090x_Px_DMDTOM(__x) (0xF417 - (__x - 1) * 0x200) /* check */ -#define STV090x_P1_DMDTOM STV090x_Px_DMDTOM(1) -#define STV090x_P2_DMDTOM STV090x_Px_DMDTOM(2) - -#define STV090x_Px_DMDSTATE(__x) (0xF41B - (__x - 1) * 0x200) -#define STV090x_P1_DMDSTATE STV090x_Px_DMDSTATE(1) -#define STV090x_P2_DMDSTATE STV090x_Px_DMDSTATE(2) -#define STV090x_OFFST_Px_HEADER_MODE_FIELD 5 -#define STV090x_WIDTH_Px_HEADER_MODE_FIELD 2 - -#define STV090x_Px_DMDFLYW(__x) (0xF41C - (__x - 1) * 0x200) -#define STV090x_P1_DMDFLYW STV090x_Px_DMDFLYW(1) -#define STV090x_P2_DMDFLYW STV090x_Px_DMDFLYW(2) -#define STV090x_OFFST_Px_I2C_IRQVAL_FIELD 4 -#define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD 4 -#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD 0 -#define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD 4 - -#define STV090x_Px_DSTATUS3(__x) (0xF41D - (__x - 1) * 0x200) -#define STV090x_P1_DSTATUS3 STV090x_Px_DSTATUS3(1) -#define STV090x_P2_DSTATUS3 STV090x_Px_DSTATUS3(2) -#define STV090x_OFFST_Px_DEMOD_CFGMODE_FIELD 5 -#define STV090x_WIDTH_Px_DEMOD_CFGMODE_FIELD 2 - -#define STV090x_Px_DMDCFG3(__x) (0xF41E - (__x - 1) * 0x200) -#define STV090x_P1_DMDCFG3 STV090x_Px_DMDCFG3(1) -#define STV090x_P2_DMDCFG3 STV090x_Px_DMDCFG3(2) -#define STV090x_OFFST_Px_NOSTOP_FIFOFULL_FIELD 3 -#define STV090x_WIDTH_Px_NOSTOP_FIFOFULL_FIELD 1 - -#define STV090x_Px_DMDCFG4(__x) (0xf41f - (__x - 1) * 0x200) -#define STV090x_P1_DMDCFG4 STV090x_Px_DMDCFG4(1) -#define STV090x_P2_DMDCFG4 STV090x_Px_DMDCFG4(2) - -#define STV090x_Px_CORRELMANT(__x) (0xF420 - (__x - 1) * 0x200) -#define STV090x_P1_CORRELMANT STV090x_Px_CORRELMANT(1) -#define STV090x_P2_CORRELMANT STV090x_Px_CORRELMANT(2) -#define STV090x_OFFST_Px_CORREL_MANT_FIELD 0 -#define STV090x_WIDTH_Px_CORREL_MANT_FIELD 8 - -#define STV090x_Px_CORRELABS(__x) (0xF421 - (__x - 1) * 0x200) -#define STV090x_P1_CORRELABS STV090x_Px_CORRELABS(1) -#define STV090x_P2_CORRELABS STV090x_Px_CORRELABS(2) -#define STV090x_OFFST_Px_CORREL_ABS_FIELD 0 -#define STV090x_WIDTH_Px_CORREL_ABS_FIELD 8 - -#define STV090x_Px_CORRELEXP(__x) (0xF422 - (__x - 1) * 0x200) -#define STV090x_P1_CORRELEXP STV090x_Px_CORRELEXP(1) -#define STV090x_P2_CORRELEXP STV090x_Px_CORRELEXP(2) -#define STV090x_OFFST_Px_CORREL_ABSEXP_FIELD 4 -#define STV090x_WIDTH_Px_CORREL_ABSEXP_FIELD 4 -#define STV090x_OFFST_Px_CORREL_EXP_FIELD 0 -#define STV090x_WIDTH_Px_CORREL_EXP_FIELD 4 - -#define STV090x_Px_PLHMODCOD(__x) (0xF424 - (__x - 1) * 0x200) -#define STV090x_P1_PLHMODCOD STV090x_Px_PLHMODCOD(1) -#define STV090x_P2_PLHMODCOD STV090x_Px_PLHMODCOD(2) -#define STV090x_OFFST_Px_SPECINV_DEMOD_FIELD 7 -#define STV090x_WIDTH_Px_SPECINV_DEMOD_FIELD 1 -#define STV090x_OFFST_Px_PLH_MODCOD_FIELD 2 -#define STV090x_WIDTH_Px_PLH_MODCOD_FIELD 5 -#define STV090x_OFFST_Px_PLH_TYPE_FIELD 0 -#define STV090x_WIDTH_Px_PLH_TYPE_FIELD 2 - -#define STV090x_Px_AGCK32(__x) (0xf42b - (__x - 1) * 0x200) -#define STV090x_P1_AGCK32 STV090x_Px_AGCK32(1) -#define STV090x_P2_AGCK32 STV090x_Px_AGCK32(2) - -#define STV090x_Px_AGC2O(__x) (0xF42C - (__x - 1) * 0x200) -#define STV090x_P1_AGC2O STV090x_Px_AGC2O(1) -#define STV090x_P2_AGC2O STV090x_Px_AGC2O(2) - -#define STV090x_Px_AGC2REF(__x) (0xF42D - (__x - 1) * 0x200) -#define STV090x_P1_AGC2REF STV090x_Px_AGC2REF(1) -#define STV090x_P2_AGC2REF STV090x_Px_AGC2REF(2) -#define STV090x_OFFST_Px_AGC2_REF_FIELD 0 -#define STV090x_WIDTH_Px_AGC2_REF_FIELD 8 - -#define STV090x_Px_AGC1ADJ(__x) (0xF42E - (__x - 1) * 0x200) -#define STV090x_P1_AGC1ADJ STV090x_Px_AGC1ADJ(1) -#define STV090x_P2_AGC1ADJ STV090x_Px_AGC1ADJ(2) -#define STV090x_OFFST_Px_AGC1_ADJUSTED_FIELD 0 -#define STV090x_WIDTH_Px_AGC1_ADJUSTED_FIELD 7 - -#define STV090x_Px_AGC2Iy(__x, __y) (0xF437 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_AGC2I0 STV090x_Px_AGC2Iy(1, 0) -#define STV090x_P1_AGC2I1 STV090x_Px_AGC2Iy(1, 1) -#define STV090x_P2_AGC2I0 STV090x_Px_AGC2Iy(2, 0) -#define STV090x_P2_AGC2I1 STV090x_Px_AGC2Iy(2, 1) -#define STV090x_OFFST_Px_AGC2_INTEGRATOR_FIELD 0 -#define STV090x_WIDTH_Px_AGC2_INTEGRATOR_FIELD 8 - -#define STV090x_Px_CARCFG(__x) (0xF438 - (__x - 1) * 0x200) -#define STV090x_P1_CARCFG STV090x_Px_CARCFG(1) -#define STV090x_P2_CARCFG STV090x_Px_CARCFG(2) -#define STV090x_OFFST_Px_EN_CAR2CENTER_FIELD 5 -#define STV090x_WIDTH_Px_EN_CAR2CENTER_FIELD 1 -#define STV090x_OFFST_Px_ROTATON_FIELD 2 -#define STV090x_WIDTH_Px_ROTATON_FIELD 1 -#define STV090x_OFFST_Px_PH_DET_ALGO_FIELD 0 -#define STV090x_WIDTH_Px_PH_DET_ALGO_FIELD 2 - -#define STV090x_Px_ACLC(__x) (0xF439 - (__x - 1) * 0x200) -#define STV090x_P1_ACLC STV090x_Px_ACLC(1) -#define STV090x_P2_ACLC STV090x_Px_ACLC(2) -#define STV090x_OFFST_Px_CAR_ALPHA_MANT_FIELD 4 -#define STV090x_WIDTH_Px_CAR_ALPHA_MANT_FIELD 2 -#define STV090x_OFFST_Px_CAR_ALPHA_EXP_FIELD 0 -#define STV090x_WIDTH_Px_CAR_ALPHA_EXP_FIELD 4 - -#define STV090x_Px_BCLC(__x) (0xF43A - (__x - 1) * 0x200) -#define STV090x_P1_BCLC STV090x_Px_BCLC(1) -#define STV090x_P2_BCLC STV090x_Px_BCLC(2) -#define STV090x_OFFST_Px_CAR_BETA_MANT_FIELD 4 -#define STV090x_WIDTH_Px_CAR_BETA_MANT_FIELD 2 -#define STV090x_OFFST_Px_CAR_BETA_EXP_FIELD 0 -#define STV090x_WIDTH_Px_CAR_BETA_EXP_FIELD 4 - -#define STV090x_Px_CARFREQ(__x) (0xF43D - (__x - 1) * 0x200) -#define STV090x_P1_CARFREQ STV090x_Px_CARFREQ(1) -#define STV090x_P2_CARFREQ STV090x_Px_CARFREQ(2) -#define STV090x_OFFST_Px_KC_COARSE_EXP_FIELD 4 -#define STV090x_WIDTH_Px_KC_COARSE_EXP_FIELD 4 -#define STV090x_OFFST_Px_BETA_FREQ_FIELD 0 -#define STV090x_WIDTH_Px_BETA_FREQ_FIELD 4 - -#define STV090x_Px_CARHDR(__x) (0xF43E - (__x - 1) * 0x200) -#define STV090x_P1_CARHDR STV090x_Px_CARHDR(1) -#define STV090x_P2_CARHDR STV090x_Px_CARHDR(2) -#define STV090x_OFFST_Px_FREQ_HDR_FIELD 0 -#define STV090x_WIDTH_Px_FREQ_HDR_FIELD 8 - -#define STV090x_Px_LDT(__x) (0xF43F - (__x - 1) * 0x200) -#define STV090x_P1_LDT STV090x_Px_LDT(1) -#define STV090x_P2_LDT STV090x_Px_LDT(2) -#define STV090x_OFFST_Px_CARLOCK_THRES_FIELD 0 -#define STV090x_WIDTH_Px_CARLOCK_THRES_FIELD 8 - -#define STV090x_Px_LDT2(__x) (0xF440 - (__x - 1) * 0x200) -#define STV090x_P1_LDT2 STV090x_Px_LDT2(1) -#define STV090x_P2_LDT2 STV090x_Px_LDT2(2) -#define STV090x_OFFST_Px_CARLOCK_THRES2_FIELD 0 -#define STV090x_WIDTH_Px_CARLOCK_THRES2_FIELD 8 - -#define STV090x_Px_CFRICFG(__x) (0xF441 - (__x - 1) * 0x200) -#define STV090x_P1_CFRICFG STV090x_Px_CFRICFG(1) -#define STV090x_P2_CFRICFG STV090x_Px_CFRICFG(2) -#define STV090x_OFFST_Px_NEG_CFRSTEP_FIELD 0 -#define STV090x_WIDTH_Px_NEG_CFRSTEP_FIELD 1 - -#define STV090x_Pn_CFRUPy(__x, __y) (0xF443 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_CFRUP0 STV090x_Pn_CFRUPy(1, 0) -#define STV090x_P1_CFRUP1 STV090x_Pn_CFRUPy(1, 1) -#define STV090x_P2_CFRUP0 STV090x_Pn_CFRUPy(2, 0) -#define STV090x_P2_CFRUP1 STV090x_Pn_CFRUPy(2, 1) -#define STV090x_OFFST_Px_CFR_UP_FIELD 0 -#define STV090x_WIDTH_Px_CFR_UP_FIELD 8 - -#define STV090x_Pn_CFRLOWy(__x, __y) (0xF447 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_CFRLOW0 STV090x_Pn_CFRLOWy(1, 0) -#define STV090x_P1_CFRLOW1 STV090x_Pn_CFRLOWy(1, 1) -#define STV090x_P2_CFRLOW0 STV090x_Pn_CFRLOWy(2, 0) -#define STV090x_P2_CFRLOW1 STV090x_Pn_CFRLOWy(2, 1) -#define STV090x_OFFST_Px_CFR_LOW_FIELD 0 -#define STV090x_WIDTH_Px_CFR_LOW_FIELD 8 - -#define STV090x_Pn_CFRINITy(__x, __y) (0xF449 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_CFRINIT0 STV090x_Pn_CFRINITy(1, 0) -#define STV090x_P1_CFRINIT1 STV090x_Pn_CFRINITy(1, 1) -#define STV090x_P2_CFRINIT0 STV090x_Pn_CFRINITy(2, 0) -#define STV090x_P2_CFRINIT1 STV090x_Pn_CFRINITy(2, 1) -#define STV090x_OFFST_Px_CFR_INIT_FIELD 0 -#define STV090x_WIDTH_Px_CFR_INIT_FIELD 8 - -#define STV090x_Px_CFRINC1(__x) (0xF44A - (__x - 1) * 0x200) -#define STV090x_P1_CFRINC1 STV090x_Px_CFRINC1(1) -#define STV090x_P2_CFRINC1 STV090x_Px_CFRINC1(2) -#define STV090x_OFFST_Px_CFR_INC1_FIELD 0 -#define STV090x_WIDTH_Px_CFR_INC1_FIELD 7 /* check */ - -#define STV090x_Px_CFRINC0(__x) (0xF44B - (__x - 1) * 0x200) -#define STV090x_P1_CFRINC0 STV090x_Px_CFRINC0(1) -#define STV090x_P2_CFRINC0 STV090x_Px_CFRINC0(2) -#define STV090x_OFFST_Px_CFR_INC0_FIELD 4 /* check */ -#define STV090x_WIDTH_Px_CFR_INC0_FIELD 4 - -#define STV090x_Pn_CFRy(__x, __y) (0xF44E - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_CFR0 STV090x_Pn_CFRy(1, 0) -#define STV090x_P1_CFR1 STV090x_Pn_CFRy(1, 1) -#define STV090x_P1_CFR2 STV090x_Pn_CFRy(1, 2) -#define STV090x_P2_CFR0 STV090x_Pn_CFRy(2, 0) -#define STV090x_P2_CFR1 STV090x_Pn_CFRy(2, 1) -#define STV090x_P2_CFR2 STV090x_Pn_CFRy(2, 2) -#define STV090x_OFFST_Px_CAR_FREQ_FIELD 0 -#define STV090x_WIDTH_Px_CAR_FREQ_FIELD 8 - -#define STV090x_Px_LDI(__x) (0xF44F - (__x - 1) * 0x200) -#define STV090x_P1_LDI STV090x_Px_LDI(1) -#define STV090x_P2_LDI STV090x_Px_LDI(2) -#define STV090x_OFFST_Px_LOCK_DET_INTEGR_FIELD 0 -#define STV090x_WIDTH_Px_LOCK_DET_INTEGR_FIELD 8 - -#define STV090x_Px_TMGCFG(__x) (0xF450 - (__x - 1) * 0x200) -#define STV090x_P1_TMGCFG STV090x_Px_TMGCFG(1) -#define STV090x_P2_TMGCFG STV090x_Px_TMGCFG(2) -#define STV090x_OFFST_Px_TMGLOCK_BETA_FIELD 6 -#define STV090x_WIDTH_Px_TMGLOCK_BETA_FIELD 2 -#define STV090x_OFFST_Px_DO_TIMING_FIELD 4 -#define STV090x_WIDTH_Px_DO_TIMING_FIELD 1 -#define STV090x_OFFST_Px_TMG_MINFREQ_FIELD 0 -#define STV090x_WIDTH_Px_TMG_MINFREQ_FIELD 2 - -#define STV090x_Px_RTC(__x) (0xF451 - (__x - 1) * 0x200) -#define STV090x_P1_RTC STV090x_Px_RTC(1) -#define STV090x_P2_RTC STV090x_Px_RTC(2) -#define STV090x_OFFST_Px_TMGALPHA_EXP_FIELD 4 -#define STV090x_WIDTH_Px_TMGALPHA_EXP_FIELD 4 -#define STV090x_OFFST_Px_TMGBETA_EXP_FIELD 0 -#define STV090x_WIDTH_Px_TMGBETA_EXP_FIELD 4 - -#define STV090x_Px_RTCS2(__x) (0xF452 - (__x - 1) * 0x200) -#define STV090x_P1_RTCS2 STV090x_Px_RTCS2(1) -#define STV090x_P2_RTCS2 STV090x_Px_RTCS2(2) -#define STV090x_OFFST_Px_TMGALPHAS2_EXP_FIELD 4 -#define STV090x_WIDTH_Px_TMGALPHAS2_EXP_FIELD 4 -#define STV090x_OFFST_Px_TMGBETAS2_EXP_FIELD 0 -#define STV090x_WIDTH_Px_TMGBETAS2_EXP_FIELD 4 - -#define STV090x_Px_TMGTHRISE(__x) (0xF453 - (__x - 1) * 0x200) -#define STV090x_P1_TMGTHRISE STV090x_Px_TMGTHRISE(1) -#define STV090x_P2_TMGTHRISE STV090x_Px_TMGTHRISE(2) -#define STV090x_OFFST_Px_TMGLOCK_THRISE_FIELD 0 -#define STV090x_WIDTH_Px_TMGLOCK_THRISE_FIELD 8 - -#define STV090x_Px_TMGTHFALL(__x) (0xF454 - (__x - 1) * 0x200) -#define STV090x_P1_TMGTHFALL STV090x_Px_TMGTHFALL(1) -#define STV090x_P2_TMGTHFALL STV090x_Px_TMGTHFALL(2) -#define STV090x_OFFST_Px_TMGLOCK_THFALL_FIELD 0 -#define STV090x_WIDTH_Px_TMGLOCK_THFALL_FIELD 8 - -#define STV090x_Px_SFRUPRATIO(__x) (0xF455 - (__x - 1) * 0x200) -#define STV090x_P1_SFRUPRATIO STV090x_Px_SFRUPRATIO(1) -#define STV090x_P2_SFRUPRATIO STV090x_Px_SFRUPRATIO(2) -#define STV090x_OFFST_Px_SFR_UPRATIO_FIELD 0 -#define STV090x_WIDTH_Px_SFR_UPRATIO_FIELD 8 - -#define STV090x_Px_SFRLOWRATIO(__x) (0xF456 - (__x - 1) * 0x200) -#define STV090x_P1_SFRLOWRATIO STV090x_Px_SFRLOWRATIO(1) -#define STV090x_P2_SFRLOWRATIO STV090x_Px_SFRLOWRATIO(2) -#define STV090x_OFFST_Px_SFR_LOWRATIO_FIELD 0 -#define STV090x_WIDTH_Px_SFR_LOWRATIO_FIELD 8 - -#define STV090x_Px_KREFTMG(__x) (0xF458 - (__x - 1) * 0x200) -#define STV090x_P1_KREFTMG STV090x_Px_KREFTMG(1) -#define STV090x_P2_KREFTMG STV090x_Px_KREFTMG(2) -#define STV090x_OFFST_Px_KREF_TMG_FIELD 0 -#define STV090x_WIDTH_Px_KREF_TMG_FIELD 8 - -#define STV090x_Px_SFRSTEP(__x) (0xF459 - (__x - 1) * 0x200) -#define STV090x_P1_SFRSTEP STV090x_Px_SFRSTEP(1) -#define STV090x_P2_SFRSTEP STV090x_Px_SFRSTEP(2) -#define STV090x_OFFST_Px_SFR_SCANSTEP_FIELD 4 -#define STV090x_WIDTH_Px_SFR_SCANSTEP_FIELD 4 -#define STV090x_OFFST_Px_SFR_CENTERSTEP_FIELD 0 -#define STV090x_WIDTH_Px_SFR_CENTERSTEP_FIELD 4 - -#define STV090x_Px_TMGCFG2(__x) (0xF45A - (__x - 1) * 0x200) -#define STV090x_P1_TMGCFG2 STV090x_Px_TMGCFG2(1) -#define STV090x_P2_TMGCFG2 STV090x_Px_TMGCFG2(2) -#define STV090x_OFFST_Px_SFRRATIO_FINE_FIELD 0 -#define STV090x_WIDTH_Px_SFRRATIO_FINE_FIELD 1 - -#define STV090x_Px_SFRINIT1(__x) (0xF45E - (__x - 1) * 0x200) -#define STV090x_P1_SFRINIT1 STV090x_Px_SFRINIT1(1) -#define STV090x_P2_SFRINIT1 STV090x_Px_SFRINIT1(2) -#define STV090x_OFFST_Px_SFR_INIT1_FIELD 0 -#define STV090x_WIDTH_Px_SFR_INIT1_FIELD 7 - -#define STV090x_Px_SFRINIT0(__x) (0xF45F - (__x - 1) * 0x200) -#define STV090x_P1_SFRINIT0 STV090x_Px_SFRINIT0(1) -#define STV090x_P2_SFRINIT0 STV090x_Px_SFRINIT0(2) -#define STV090x_OFFST_Px_SFR_INIT0_FIELD 0 -#define STV090x_WIDTH_Px_SFR_INIT0_FIELD 8 - -#define STV090x_Px_SFRUP1(__x) (0xF460 - (__x - 1) * 0x200) -#define STV090x_P1_SFRUP1 STV090x_Px_SFRUP1(1) -#define STV090x_P2_SFRUP1 STV090x_Px_SFRUP1(2) -#define STV090x_OFFST_Px_SYMB_FREQ_UP1_FIELD 0 -#define STV090x_WIDTH_Px_SYMB_FREQ_UP1_FIELD 7 - -#define STV090x_Px_SFRUP0(__x) (0xF461 - (__x - 1) * 0x200) -#define STV090x_P1_SFRUP0 STV090x_Px_SFRUP0(1) -#define STV090x_P2_SFRUP0 STV090x_Px_SFRUP0(2) -#define STV090x_OFFST_Px_SYMB_FREQ_UP0_FIELD 0 -#define STV090x_WIDTH_Px_SYMB_FREQ_UP0_FIELD 8 - -#define STV090x_Px_SFRLOW1(__x) (0xF462 - (__x - 1) * 0x200) -#define STV090x_P1_SFRLOW1 STV090x_Px_SFRLOW1(1) -#define STV090x_P2_SFRLOW1 STV090x_Px_SFRLOW1(2) -#define STV090x_OFFST_Px_SYMB_FREQ_LOW1_FIELD 0 -#define STV090x_WIDTH_Px_SYMB_FREQ_LOW1_FIELD 7 - -#define STV090x_Px_SFRLOW0(__x) (0xF463 - (__x - 1) * 0x200) -#define STV090x_P1_SFRLOW0 STV090x_Px_SFRLOW0(1) -#define STV090x_P2_SFRLOW0 STV090x_Px_SFRLOW0(2) -#define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD 0 -#define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD 8 - -#define STV090x_Px_SFRy(__x, __y) (0xF467 - (__x-1) * 0x200 - __y) -#define STV090x_P1_SFR0 STV090x_Px_SFRy(1, 0) -#define STV090x_P1_SFR1 STV090x_Px_SFRy(1, 1) -#define STV090x_P1_SFR2 STV090x_Px_SFRy(1, 2) -#define STV090x_P1_SFR3 STV090x_Px_SFRy(1, 3) -#define STV090x_P2_SFR0 STV090x_Px_SFRy(2, 0) -#define STV090x_P2_SFR1 STV090x_Px_SFRy(2, 1) -#define STV090x_P2_SFR2 STV090x_Px_SFRy(2, 2) -#define STV090x_P2_SFR3 STV090x_Px_SFRy(2, 3) -#define STV090x_OFFST_Px_SYMB_FREQ_FIELD 0 -#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD 8 - -#define STV090x_Px_TMGREG2(__x) (0xF468 - (__x - 1) * 0x200) -#define STV090x_P1_TMGREG2 STV090x_Px_TMGREG2(1) -#define STV090x_P2_TMGREG2 STV090x_Px_TMGREG2(2) -#define STV090x_OFFST_Px_TMGREG_FIELD 0 -#define STV090x_WIDTH_Px_TMGREG_FIELD 8 - -#define STV090x_Px_TMGREG1(__x) (0xF469 - (__x - 1) * 0x200) -#define STV090x_P1_TMGREG1 STV090x_Px_TMGREG1(1) -#define STV090x_P2_TMGREG1 STV090x_Px_TMGREG1(2) -#define STV090x_OFFST_Px_TMGREG_FIELD 0 -#define STV090x_WIDTH_Px_TMGREG_FIELD 8 - -#define STV090x_Px_TMGREG0(__x) (0xF46A - (__x - 1) * 0x200) -#define STV090x_P1_TMGREG0 STV090x_Px_TMGREG0(1) -#define STV090x_P2_TMGREG0 STV090x_Px_TMGREG0(2) -#define STV090x_OFFST_Px_TMGREG_FIELD 0 -#define STV090x_WIDTH_Px_TMGREG_FIELD 8 - -#define STV090x_Px_TMGLOCKy(__x, __y) (0xF46C - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_TMGLOCK0 STV090x_Px_TMGLOCKy(1, 0) -#define STV090x_P1_TMGLOCK1 STV090x_Px_TMGLOCKy(1, 1) -#define STV090x_P2_TMGLOCK0 STV090x_Px_TMGLOCKy(2, 0) -#define STV090x_P2_TMGLOCK1 STV090x_Px_TMGLOCKy(2, 1) -#define STV090x_OFFST_Px_TMGLOCK_LEVEL_FIELD 0 -#define STV090x_WIDTH_Px_TMGLOCK_LEVEL_FIELD 8 - -#define STV090x_Px_TMGOBS(__x) (0xF46D - (__x - 1) * 0x200) -#define STV090x_P1_TMGOBS STV090x_Px_TMGOBS(1) -#define STV090x_P2_TMGOBS STV090x_Px_TMGOBS(2) -#define STV090x_OFFST_Px_ROLLOFF_STATUS_FIELD 6 -#define STV090x_WIDTH_Px_ROLLOFF_STATUS_FIELD 2 - -#define STV090x_Px_EQUALCFG(__x) (0xF46F - (__x - 1) * 0x200) -#define STV090x_P1_EQUALCFG STV090x_Px_EQUALCFG(1) -#define STV090x_P2_EQUALCFG STV090x_Px_EQUALCFG(2) -#define STV090x_OFFST_Px_EQUAL_ON_FIELD 6 -#define STV090x_WIDTH_Px_EQUAL_ON_FIELD 1 -#define STV090x_OFFST_Px_MU_EQUALDFE_FIELD 0 -#define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD 3 - -#define STV090x_Px_EQUAIy(__x, __y) (0xf470 - (__x-1) * 0x200 + 2 * (__y-1)) -#define STV090x_P1_EQUAI1 STV090x_Px_EQUAIy(1, 1) -#define STV090x_P1_EQUAI2 STV090x_Px_EQUAIy(1, 2) -#define STV090x_P1_EQUAI3 STV090x_Px_EQUAIy(1, 3) -#define STV090x_P1_EQUAI4 STV090x_Px_EQUAIy(1, 4) -#define STV090x_P1_EQUAI5 STV090x_Px_EQUAIy(1, 5) -#define STV090x_P1_EQUAI6 STV090x_Px_EQUAIy(1, 6) -#define STV090x_P1_EQUAI7 STV090x_Px_EQUAIy(1, 7) -#define STV090x_P1_EQUAI8 STV090x_Px_EQUAIy(1, 8) - -#define STV090x_P2_EQUAI1 STV090x_Px_EQUAIy(2, 1) -#define STV090x_P2_EQUAI2 STV090x_Px_EQUAIy(2, 2) -#define STV090x_P2_EQUAI3 STV090x_Px_EQUAIy(2, 3) -#define STV090x_P2_EQUAI4 STV090x_Px_EQUAIy(2, 4) -#define STV090x_P2_EQUAI5 STV090x_Px_EQUAIy(2, 5) -#define STV090x_P2_EQUAI6 STV090x_Px_EQUAIy(2, 6) -#define STV090x_P2_EQUAI7 STV090x_Px_EQUAIy(2, 7) -#define STV090x_P2_EQUAI8 STV090x_Px_EQUAIy(2, 8) -#define STV090x_OFFST_Px_EQUA_ACCIy_FIELD 0 -#define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD 8 - -#define STV090x_Px_EQUAQy(__x, __y) (0xf471 - (__x-1) * 0x200 + 2 * (__y-1)) -#define STV090x_P1_EQUAQ1 STV090x_Px_EQUAQy(1, 1) -#define STV090x_P1_EQUAQ2 STV090x_Px_EQUAQy(1, 2) -#define STV090x_P1_EQUAQ3 STV090x_Px_EQUAQy(1, 3) -#define STV090x_P1_EQUAQ4 STV090x_Px_EQUAQy(1, 4) -#define STV090x_P1_EQUAQ5 STV090x_Px_EQUAQy(1, 5) -#define STV090x_P1_EQUAQ6 STV090x_Px_EQUAQy(1, 6) -#define STV090x_P1_EQUAQ7 STV090x_Px_EQUAQy(1, 7) -#define STV090x_P1_EQUAQ8 STV090x_Px_EQUAQy(1, 8) - -#define STV090x_P2_EQUAQ1 STV090x_Px_EQUAQy(2, 1) -#define STV090x_P2_EQUAQ2 STV090x_Px_EQUAQy(2, 2) -#define STV090x_P2_EQUAQ3 STV090x_Px_EQUAQy(2, 3) -#define STV090x_P2_EQUAQ4 STV090x_Px_EQUAQy(2, 4) -#define STV090x_P2_EQUAQ5 STV090x_Px_EQUAQy(2, 5) -#define STV090x_P2_EQUAQ6 STV090x_Px_EQUAQy(2, 6) -#define STV090x_P2_EQUAQ7 STV090x_Px_EQUAQy(2, 7) -#define STV090x_P2_EQUAQ8 STV090x_Px_EQUAQy(2, 8) -#define STV090x_OFFST_Px_EQUA_ACCQy_FIELD 0 -#define STV090x_WIDTH_Px_EQUA_ACCQy_FIELD 8 - -#define STV090x_Px_NNOSDATATy(__x, __y) (0xf481 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NNOSDATAT0 STV090x_Px_NNOSDATATy(1, 0) -#define STV090x_P1_NNOSDATAT1 STV090x_Px_NNOSDATATy(1, 1) -#define STV090x_P2_NNOSDATAT0 STV090x_Px_NNOSDATATy(2, 0) -#define STV090x_P2_NNOSDATAT1 STV090x_Px_NNOSDATATy(2, 1) -#define STV090x_OFFST_Px_NOSDATAT_NORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSDATAT_NORMED_FIELD 8 - -#define STV090x_Px_NNOSDATAy(__x, __y) (0xf483 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NNOSDATA0 STV090x_Px_NNOSDATAy(1, 0) -#define STV090x_P1_NNOSDATA1 STV090x_Px_NNOSDATAy(1, 1) -#define STV090x_P2_NNOSDATA0 STV090x_Px_NNOSDATAy(2, 0) -#define STV090x_P2_NNOSDATA1 STV090x_Px_NNOSDATAy(2, 1) -#define STV090x_OFFST_Px_NOSDATA_NORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSDATA_NORMED_FIELD 8 - -#define STV090x_Px_NNOSPLHTy(__x, __y) (0xf485 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NNOSPLHT0 STV090x_Px_NNOSPLHTy(1, 0) -#define STV090x_P1_NNOSPLHT1 STV090x_Px_NNOSPLHTy(1, 1) -#define STV090x_P2_NNOSPLHT0 STV090x_Px_NNOSPLHTy(2, 0) -#define STV090x_P2_NNOSPLHT1 STV090x_Px_NNOSPLHTy(2, 1) -#define STV090x_OFFST_Px_NOSPLHT_NORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSPLHT_NORMED_FIELD 8 - -#define STV090x_Px_NNOSPLHy(__x, __y) (0xf487 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NNOSPLH0 STV090x_Px_NNOSPLHy(1, 0) -#define STV090x_P1_NNOSPLH1 STV090x_Px_NNOSPLHy(1, 1) -#define STV090x_P2_NNOSPLH0 STV090x_Px_NNOSPLHy(2, 0) -#define STV090x_P2_NNOSPLH1 STV090x_Px_NNOSPLHy(2, 1) -#define STV090x_OFFST_Px_NOSPLH_NORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSPLH_NORMED_FIELD 8 - -#define STV090x_Px_NOSDATATy(__x, __y) (0xf489 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NOSDATAT0 STV090x_Px_NOSDATATy(1, 0) -#define STV090x_P1_NOSDATAT1 STV090x_Px_NOSDATATy(1, 1) -#define STV090x_P2_NOSDATAT0 STV090x_Px_NOSDATATy(2, 0) -#define STV090x_P2_NOSDATAT1 STV090x_Px_NOSDATATy(2, 1) -#define STV090x_OFFST_Px_NOSDATAT_UNNORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSDATAT_UNNORMED_FIELD 8 - -#define STV090x_Px_NOSDATAy(__x, __y) (0xf48b - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NOSDATA0 STV090x_Px_NOSDATAy(1, 0) -#define STV090x_P1_NOSDATA1 STV090x_Px_NOSDATAy(1, 1) -#define STV090x_P2_NOSDATA0 STV090x_Px_NOSDATAy(2, 0) -#define STV090x_P2_NOSDATA1 STV090x_Px_NOSDATAy(2, 1) -#define STV090x_OFFST_Px_NOSDATA_UNNORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSDATA_UNNORMED_FIELD 8 - -#define STV090x_Px_NOSPLHTy(__x, __y) (0xf48d - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NOSPLHT0 STV090x_Px_NOSPLHTy(1, 0) -#define STV090x_P1_NOSPLHT1 STV090x_Px_NOSPLHTy(1, 1) -#define STV090x_P2_NOSPLHT0 STV090x_Px_NOSPLHTy(2, 0) -#define STV090x_P2_NOSPLHT1 STV090x_Px_NOSPLHTy(2, 1) -#define STV090x_OFFST_Px_NOSPLHT_UNNORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSPLHT_UNNORMED_FIELD 8 - -#define STV090x_Px_NOSPLHy(__x, __y) (0xf48f - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_NOSPLH0 STV090x_Px_NOSPLHy(1, 0) -#define STV090x_P1_NOSPLH1 STV090x_Px_NOSPLHy(1, 1) -#define STV090x_P2_NOSPLH0 STV090x_Px_NOSPLHy(2, 0) -#define STV090x_P2_NOSPLH1 STV090x_Px_NOSPLHy(2, 1) -#define STV090x_OFFST_Px_NOSPLH_UNNORMED_FIELD 0 -#define STV090x_WIDTH_Px_NOSPLH_UNNORMED_FIELD 8 - -#define STV090x_Px_CAR2CFG(__x) (0xf490 - (__x - 1) * 0x200) -#define STV090x_P1_CAR2CFG STV090x_Px_CAR2CFG(1) -#define STV090x_P2_CAR2CFG STV090x_Px_CAR2CFG(2) -#define STV090x_OFFST_Px_PN4_SELECT_FIELD 6 -#define STV090x_WIDTH_Px_PN4_SELECT_FIELD 1 -#define STV090x_OFFST_Px_CFR2_STOPDVBS1_FIELD 5 -#define STV090x_WIDTH_Px_CFR2_STOPDVBS1_FIELD 1 -#define STV090x_OFFST_Px_ROTA2ON_FIELD 2 -#define STV090x_WIDTH_Px_ROTA2ON_FIELD 1 -#define STV090x_OFFST_Px_PH_DET_ALGO2_FIELD 0 -#define STV090x_WIDTH_Px_PH_DET_ALGO2_FIELD 2 - -#define STV090x_Px_ACLC2(__x) (0xf491 - (__x - 1) * 0x200) -#define STV090x_P1_ACLC2 STV090x_Px_ACLC2(1) -#define STV090x_P2_ACLC2 STV090x_Px_ACLC2(2) -#define STV090x_OFFST_Px_CAR2_ALPHA_MANT_FIELD 4 -#define STV090x_WIDTH_Px_CAR2_ALPHA_MANT_FIELD 2 -#define STV090x_OFFST_Px_CAR2_ALPHA_EXP_FIELD 0 -#define STV090x_WIDTH_Px_CAR2_ALPHA_EXP_FIELD 4 - -#define STV090x_Px_BCLC2(__x) (0xf492 - (__x - 1) * 0x200) -#define STV090x_P1_BCLC2 STV090x_Px_BCLC2(1) -#define STV090x_P2_BCLC2 STV090x_Px_BCLC2(2) -#define STV090x_OFFST_Px_CAR2_BETA_MANT_FIELD 4 -#define STV090x_WIDTH_Px_CAR2_BETA_MANT_FIELD 2 -#define STV090x_OFFST_Px_CAR2_BETA_EXP_FIELD 0 -#define STV090x_WIDTH_Px_CAR2_BETA_EXP_FIELD 4 - -#define STV090x_Px_ACLC2S2Q(__x) (0xf497 - (__x - 1) * 0x200) -#define STV090x_P1_ACLC2S2Q STV090x_Px_ACLC2S2Q(1) -#define STV090x_P2_ACLC2S2Q STV090x_Px_ACLC2S2Q(2) -#define STV090x_OFFST_Px_ENAB_SPSKSYMB_FIELD 7 -#define STV090x_WIDTH_Px_ENAB_SPSKSYMB_FIELD 1 -#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_E_FIELD 4 - -#define STV090x_Px_ACLC2S28(__x) (0xf498 - (__x - 1) * 0x200) -#define STV090x_P1_ACLC2S28 STV090x_Px_ACLC2S28(1) -#define STV090x_P2_ACLC2S28 STV090x_Px_ACLC2S28(2) -#define STV090x_OFFST_Px_CAR2S2_8_ALPH_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_8_ALPH_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_E_FIELD 4 - -#define STV090x_Px_ACLC2S216A(__x) (0xf499 - (__x - 1) * 0x200) -#define STV090x_P1_ACLC2S216A STV090x_Px_ACLC2S216A(1) -#define STV090x_P2_ACLC2S216A STV090x_Px_ACLC2S216A(2) -#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD 4 - -#define STV090x_Px_ACLC2S232A(__x) (0xf49A - (__x - 1) * 0x200) -#define STV090x_P1_ACLC2S232A STV090x_Px_ACLC2S232A(1) -#define STV090x_P2_ACLC2S232A STV090x_Px_ACLC2S232A(2) -#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_E_FIELD 4 - -#define STV090x_Px_BCLC2S2Q(__x) (0xf49c - (__x - 1) * 0x200) -#define STV090x_P1_BCLC2S2Q STV090x_Px_BCLC2S2Q(1) -#define STV090x_P2_BCLC2S2Q STV090x_Px_BCLC2S2Q(2) -#define STV090x_OFFST_Px_CAR2S2_Q_BETA_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_Q_BETA_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_E_FIELD 4 - -#define STV090x_Px_BCLC2S28(__x) (0xf49d - (__x - 1) * 0x200) -#define STV090x_P1_BCLC2S28 STV090x_Px_BCLC2S28(1) -#define STV090x_P2_BCLC2S28 STV090x_Px_BCLC2S28(2) -#define STV090x_OFFST_Px_CAR2S2_8_BETA_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_8_BETA_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD 4 - -#define STV090x_Px_BCLC2S216A(__x) (0xf49e - (__x - 1) * 0x200) -#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1) -#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(2) -#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD 4 - -#define STV090x_Px_BCLC2S232A(__x) (0xf49f - (__x - 1) * 0x200) -#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1) -#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(2) -#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4 -#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_M_FIELD 2 -#define STV090x_OFFST_Px_CAR2S2_32A_BETA_E_FIELD 0 -#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_E_FIELD 4 - -#define STV090x_Px_PLROOT2(__x) (0xf4ac - (__x - 1) * 0x200) -#define STV090x_P1_PLROOT2 STV090x_Px_PLROOT2(1) -#define STV090x_P2_PLROOT2 STV090x_Px_PLROOT2(2) -#define STV090x_OFFST_Px_PLSCRAMB_MODE_FIELD 2 -#define STV090x_WIDTH_Px_PLSCRAMB_MODE_FIELD 2 -#define STV090x_OFFST_Px_PLSCRAMB_ROOT_FIELD 0 -#define STV090x_WIDTH_Px_PLSCRAMB_ROOT_FIELD 2 - -#define STV090x_Px_PLROOT1(__x) (0xf4ad - (__x - 1) * 0x200) -#define STV090x_P1_PLROOT1 STV090x_Px_PLROOT1(1) -#define STV090x_P2_PLROOT1 STV090x_Px_PLROOT1(2) -#define STV090x_OFFST_Px_PLSCRAMB_ROOT1_FIELD 0 -#define STV090x_WIDTH_Px_PLSCRAMB_ROOT1_FIELD 8 - -#define STV090x_Px_PLROOT0(__x) (0xf4ae - (__x - 1) * 0x200) -#define STV090x_P1_PLROOT0 STV090x_Px_PLROOT0(1) -#define STV090x_P2_PLROOT0 STV090x_Px_PLROOT0(2) -#define STV090x_OFFST_Px_PLSCRAMB_ROOT0_FIELD 0 -#define STV090x_WIDTH_Px_PLSCRAMB_ROOT0_FIELD 8 - -#define STV090x_Px_MODCODLST0(__x) (0xf4b0 - (__x - 1) * 0x200) /* check */ -#define STV090x_P1_MODCODLST0 STV090x_Px_MODCODLST0(1) -#define STV090x_P2_MODCODLST0 STV090x_Px_MODCODLST0(2) - -#define STV090x_Px_MODCODLST1(__x) (0xf4b1 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST1 STV090x_Px_MODCODLST1(1) -#define STV090x_P2_MODCODLST1 STV090x_Px_MODCODLST1(2) -#define STV090x_OFFST_Px_DIS_MODCOD29_FIELD 4 -#define STV090x_WIDTH_Px_DIS_MODCOD29_FIELD 4 -#define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD 0 -#define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD 4 - -#define STV090x_Px_MODCODLST2(__x) (0xf4b2 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST2 STV090x_Px_MODCODLST2(1) -#define STV090x_P2_MODCODLST2 STV090x_Px_MODCODLST2(2) -#define STV090x_OFFST_Px_DIS_32PSK_8_9_FIELD 4 -#define STV090x_WIDTH_Px_DIS_32PSK_8_9_FIELD 4 -#define STV090x_OFFST_Px_DIS_32PSK_5_6_FIELD 0 -#define STV090x_WIDTH_Px_DIS_32PSK_5_6_FIELD 4 - -#define STV090x_Px_MODCODLST3(__x) (0xf4b3 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST3 STV090x_Px_MODCODLST3(1) -#define STV090x_P2_MODCODLST3 STV090x_Px_MODCODLST3(2) -#define STV090x_OFFST_Px_DIS_32PSK_4_5_FIELD 4 -#define STV090x_WIDTH_Px_DIS_32PSK_4_5_FIELD 4 -#define STV090x_OFFST_Px_DIS_32PSK_3_4_FIELD 0 -#define STV090x_WIDTH_Px_DIS_32PSK_3_4_FIELD 4 - -#define STV090x_Px_MODCODLST4(__x) (0xf4b4 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST4 STV090x_Px_MODCODLST4(1) -#define STV090x_P2_MODCODLST4 STV090x_Px_MODCODLST4(2) -#define STV090x_OFFST_Px_DIS_16PSK_9_10_FIELD 4 -#define STV090x_WIDTH_Px_DIS_16PSK_9_10_FIELD 4 -#define STV090x_OFFST_Px_DIS_16PSK_8_9_FIELD 0 -#define STV090x_WIDTH_Px_DIS_16PSK_8_9_FIELD 4 - -#define STV090x_Px_MODCODLST5(__x) (0xf4b5 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST5 STV090x_Px_MODCODLST5(1) -#define STV090x_P2_MODCODLST5 STV090x_Px_MODCODLST5(2) -#define STV090x_OFFST_Px_DIS_16PSK_5_6_FIELD 4 -#define STV090x_WIDTH_Px_DIS_16PSK_5_6_FIELD 4 -#define STV090x_OFFST_Px_DIS_16PSK_4_5_FIELD 0 -#define STV090x_WIDTH_Px_DIS_16PSK_4_5_FIELD 4 - -#define STV090x_Px_MODCODLST6(__x) (0xf4b6 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST6 STV090x_Px_MODCODLST6(1) -#define STV090x_P2_MODCODLST6 STV090x_Px_MODCODLST6(2) -#define STV090x_OFFST_Px_DIS_16PSK_3_4_FIELD 4 -#define STV090x_WIDTH_Px_DIS_16PSK_3_4_FIELD 4 -#define STV090x_OFFST_Px_DIS_16PSK_2_3_FIELD 0 -#define STV090x_WIDTH_Px_DIS_16PSK_2_3_FIELD 4 - -#define STV090x_Px_MODCODLST7(__x) (0xf4b7 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST7 STV090x_Px_MODCODLST7(1) -#define STV090x_P2_MODCODLST7 STV090x_Px_MODCODLST7(2) -#define STV090x_OFFST_Px_DIS_8P_9_10_FIELD 4 -#define STV090x_WIDTH_Px_DIS_8P_9_10_FIELD 4 -#define STV090x_OFFST_Px_DIS_8P_8_9_FIELD 0 -#define STV090x_WIDTH_Px_DIS_8P_8_9_FIELD 4 - -#define STV090x_Px_MODCODLST8(__x) (0xf4b8 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST8 STV090x_Px_MODCODLST8(1) -#define STV090x_P2_MODCODLST8 STV090x_Px_MODCODLST8(2) -#define STV090x_OFFST_Px_DIS_8P_5_6_FIELD 4 -#define STV090x_WIDTH_Px_DIS_8P_5_6_FIELD 4 -#define STV090x_OFFST_Px_DIS_8P_3_4_FIELD 0 -#define STV090x_WIDTH_Px_DIS_8P_3_4_FIELD 4 - -#define STV090x_Px_MODCODLST9(__x) (0xf4b9 - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLST9 STV090x_Px_MODCODLST9(1) -#define STV090x_P2_MODCODLST9 STV090x_Px_MODCODLST9(2) -#define STV090x_OFFST_Px_DIS_8P_2_3_FIELD 4 -#define STV090x_WIDTH_Px_DIS_8P_2_3_FIELD 4 -#define STV090x_OFFST_Px_DIS_8P_3_5_FIELD 0 -#define STV090x_WIDTH_Px_DIS_8P_3_5_FIELD 4 - -#define STV090x_Px_MODCODLSTA(__x) (0xf4ba - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLSTA STV090x_Px_MODCODLSTA(1) -#define STV090x_P2_MODCODLSTA STV090x_Px_MODCODLSTA(2) -#define STV090x_OFFST_Px_DIS_QP_9_10_FIELD 4 -#define STV090x_WIDTH_Px_DIS_QP_9_10_FIELD 4 -#define STV090x_OFFST_Px_DIS_QP_8_9_FIELD 0 -#define STV090x_WIDTH_Px_DIS_QP_8_9_FIELD 4 - -#define STV090x_Px_MODCODLSTB(__x) (0xf4bb - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLSTB STV090x_Px_MODCODLSTB(1) -#define STV090x_P2_MODCODLSTB STV090x_Px_MODCODLSTB(2) -#define STV090x_OFFST_Px_DIS_QP_5_6_FIELD 4 -#define STV090x_WIDTH_Px_DIS_QP_5_6_FIELD 4 -#define STV090x_OFFST_Px_DIS_QP_4_5_FIELD 0 -#define STV090x_WIDTH_Px_DIS_QP_4_5_FIELD 4 - -#define STV090x_Px_MODCODLSTC(__x) (0xf4bc - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLSTC STV090x_Px_MODCODLSTC(1) -#define STV090x_P2_MODCODLSTC STV090x_Px_MODCODLSTC(2) -#define STV090x_OFFST_Px_DIS_QP_3_4_FIELD 4 -#define STV090x_WIDTH_Px_DIS_QP_3_4_FIELD 4 -#define STV090x_OFFST_Px_DIS_QP_2_3_FIELD 0 -#define STV090x_WIDTH_Px_DIS_QP_2_3_FIELD 4 - -#define STV090x_Px_MODCODLSTD(__x) (0xf4bd - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLSTD STV090x_Px_MODCODLSTD(1) -#define STV090x_P2_MODCODLSTD STV090x_Px_MODCODLSTD(2) -#define STV090x_OFFST_Px_DIS_QP_3_5_FIELD 4 -#define STV090x_WIDTH_Px_DIS_QP_3_5_FIELD 4 -#define STV090x_OFFST_Px_DIS_QP_1_2_FIELD 0 -#define STV090x_WIDTH_Px_DIS_QP_1_2_FIELD 4 - -#define STV090x_Px_MODCODLSTE(__x) (0xf4be - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLSTE STV090x_Px_MODCODLSTE(1) -#define STV090x_P2_MODCODLSTE STV090x_Px_MODCODLSTE(2) -#define STV090x_OFFST_Px_DIS_QP_2_5_FIELD 4 -#define STV090x_WIDTH_Px_DIS_QP_2_5_FIELD 4 -#define STV090x_OFFST_Px_DIS_QP_1_3_FIELD 0 -#define STV090x_WIDTH_Px_DIS_QP_1_3_FIELD 4 - -#define STV090x_Px_MODCODLSTF(__x) (0xf4bf - (__x - 1) * 0x200) -#define STV090x_P1_MODCODLSTF STV090x_Px_MODCODLSTF(1) -#define STV090x_P2_MODCODLSTF STV090x_Px_MODCODLSTF(2) -#define STV090x_OFFST_Px_DIS_QP_1_4_FIELD 4 -#define STV090x_WIDTH_Px_DIS_QP_1_4_FIELD 4 - -#define STV090x_Px_GAUSSR0(__x) (0xf4c0 - (__x - 1) * 0x200) -#define STV090x_P1_GAUSSR0 STV090x_Px_GAUSSR0(1) -#define STV090x_P2_GAUSSR0 STV090x_Px_GAUSSR0(2) -#define STV090x_OFFST_Px_EN_CCIMODE_FIELD 7 -#define STV090x_WIDTH_Px_EN_CCIMODE_FIELD 1 -#define STV090x_OFFST_Px_R0_GAUSSIEN_FIELD 0 -#define STV090x_WIDTH_Px_R0_GAUSSIEN_FIELD 7 - -#define STV090x_Px_CCIR0(__x) (0xf4c1 - (__x - 1) * 0x200) -#define STV090x_P1_CCIR0 STV090x_Px_CCIR0(1) -#define STV090x_P2_CCIR0 STV090x_Px_CCIR0(2) -#define STV090x_OFFST_Px_CCIDETECT_PLH_FIELD 7 -#define STV090x_WIDTH_Px_CCIDETECT_PLH_FIELD 1 -#define STV090x_OFFST_Px_R0_CCI_FIELD 0 -#define STV090x_WIDTH_Px_R0_CCI_FIELD 7 - -#define STV090x_Px_CCIQUANT(__x) (0xf4c2 - (__x - 1) * 0x200) -#define STV090x_P1_CCIQUANT STV090x_Px_CCIQUANT(1) -#define STV090x_P2_CCIQUANT STV090x_Px_CCIQUANT(2) -#define STV090x_OFFST_Px_CCI_BETA_FIELD 5 -#define STV090x_WIDTH_Px_CCI_BETA_FIELD 3 -#define STV090x_OFFST_Px_CCI_QUANT_FIELD 0 -#define STV090x_WIDTH_Px_CCI_QUANT_FIELD 5 - -#define STV090x_Px_CCITHRESH(__x) (0xf4c3 - (__x - 1) * 0x200) -#define STV090x_P1_CCITHRESH STV090x_Px_CCITHRESH(1) -#define STV090x_P2_CCITHRESH STV090x_Px_CCITHRESH(2) -#define STV090x_OFFST_Px_CCI_THRESHOLD_FIELD 0 -#define STV090x_WIDTH_Px_CCI_THRESHOLD_FIELD 8 - -#define STV090x_Px_CCIACC(__x) (0xf4c4 - (__x - 1) * 0x200) -#define STV090x_P1_CCIACC STV090x_Px_CCIACC(1) -#define STV090x_P2_CCIACC STV090x_Px_CCIACC(2) -#define STV090x_OFFST_Px_CCI_VALUE_FIELD 0 -#define STV090x_WIDTH_Px_CCI_VALUE_FIELD 8 - -#define STV090x_Px_DMDRESCFG(__x) (0xF4C6 - (__x - 1) * 0x200) -#define STV090x_P1_DMDRESCFG STV090x_Px_DMDRESCFG(1) -#define STV090x_P2_DMDRESCFG STV090x_Px_DMDRESCFG(2) -#define STV090x_OFFST_Px_DMDRES_RESET_FIELD 7 -#define STV090x_WIDTH_Px_DMDRES_RESET_FIELD 1 - -#define STV090x_Px_DMDRESADR(__x) (0xF4C7 - (__x - 1) * 0x200) -#define STV090x_P1_DMDRESADR STV090x_Px_DMDRESADR(1) -#define STV090x_P2_DMDRESADR STV090x_Px_DMDRESADR(2) -#define STV090x_OFFST_Px_DMDRES_RESNBR_FIELD 0 -#define STV090x_WIDTH_Px_DMDRES_RESNBR_FIELD 4 - -#define STV090x_Px_DMDRESDATAy(__x, __y) (0xF4C8 - (__x - 1) * 0x200 + (7 - __y)) -#define STV090x_P1_DMDRESDATA0 STV090x_Px_DMDRESDATAy(1, 0) -#define STV090x_P1_DMDRESDATA1 STV090x_Px_DMDRESDATAy(1, 1) -#define STV090x_P1_DMDRESDATA2 STV090x_Px_DMDRESDATAy(1, 2) -#define STV090x_P1_DMDRESDATA3 STV090x_Px_DMDRESDATAy(1, 3) -#define STV090x_P1_DMDRESDATA4 STV090x_Px_DMDRESDATAy(1, 4) -#define STV090x_P1_DMDRESDATA5 STV090x_Px_DMDRESDATAy(1, 5) -#define STV090x_P1_DMDRESDATA6 STV090x_Px_DMDRESDATAy(1, 6) -#define STV090x_P1_DMDRESDATA7 STV090x_Px_DMDRESDATAy(1, 7) -#define STV090x_P2_DMDRESDATA0 STV090x_Px_DMDRESDATAy(2, 0) -#define STV090x_P2_DMDRESDATA1 STV090x_Px_DMDRESDATAy(2, 1) -#define STV090x_P2_DMDRESDATA2 STV090x_Px_DMDRESDATAy(2, 2) -#define STV090x_P2_DMDRESDATA3 STV090x_Px_DMDRESDATAy(2, 3) -#define STV090x_P2_DMDRESDATA4 STV090x_Px_DMDRESDATAy(2, 4) -#define STV090x_P2_DMDRESDATA5 STV090x_Px_DMDRESDATAy(2, 5) -#define STV090x_P2_DMDRESDATA6 STV090x_Px_DMDRESDATAy(2, 6) -#define STV090x_P2_DMDRESDATA7 STV090x_Px_DMDRESDATAy(2, 7) -#define STV090x_OFFST_Px_DMDRES_DATA_FIELD 0 -#define STV090x_WIDTH_Px_DMDRES_DATA_FIELD 8 - -#define STV090x_Px_FFEIy(__x, __y) (0xf4d0 - (__x - 1) * 0x200 + 0x2 * (__y - 1)) -#define STV090x_P1_FFEI1 STV090x_Px_FFEIy(1, 1) -#define STV090x_P1_FFEI2 STV090x_Px_FFEIy(1, 2) -#define STV090x_P1_FFEI3 STV090x_Px_FFEIy(1, 3) -#define STV090x_P1_FFEI4 STV090x_Px_FFEIy(1, 4) -#define STV090x_P2_FFEI1 STV090x_Px_FFEIy(2, 1) -#define STV090x_P2_FFEI2 STV090x_Px_FFEIy(2, 2) -#define STV090x_P2_FFEI3 STV090x_Px_FFEIy(2, 3) -#define STV090x_P2_FFEI4 STV090x_Px_FFEIy(2, 4) -#define STV090x_OFFST_Px_FFE_ACCIy_FIELD 0 -#define STV090x_WIDTH_Px_FFE_ACCIy_FIELD 8 - -#define STV090x_Px_FFEQy(__x, __y) (0xf4d1 - (__x - 1) * 0x200 + 0x2 * (__y - 1)) -#define STV090x_P1_FFEQ1 STV090x_Px_FFEQy(1, 1) -#define STV090x_P1_FFEQ2 STV090x_Px_FFEQy(1, 2) -#define STV090x_P1_FFEQ3 STV090x_Px_FFEQy(1, 3) -#define STV090x_P1_FFEQ4 STV090x_Px_FFEQy(1, 4) -#define STV090x_P2_FFEQ1 STV090x_Px_FFEQy(2, 1) -#define STV090x_P2_FFEQ2 STV090x_Px_FFEQy(2, 2) -#define STV090x_P2_FFEQ3 STV090x_Px_FFEQy(2, 3) -#define STV090x_P2_FFEQ4 STV090x_Px_FFEQy(2, 4) -#define STV090x_OFFST_Px_FFE_ACCQy_FIELD 0 -#define STV090x_WIDTH_Px_FFE_ACCQy_FIELD 8 - -#define STV090x_Px_FFECFG(__x) (0xf4d8 - (__x - 1) * 0x200) -#define STV090x_P1_FFECFG STV090x_Px_FFECFG(1) -#define STV090x_P2_FFECFG STV090x_Px_FFECFG(2) -#define STV090x_OFFST_Px_EQUALFFE_ON_FIELD 6 -#define STV090x_WIDTH_Px_EQUALFFE_ON_FIELD 1 - -#define STV090x_Px_SMAPCOEF7(__x) (0xf500 - (__x - 1) * 0x200) -#define STV090x_P1_SMAPCOEF7 STV090x_Px_SMAPCOEF7(1) -#define STV090x_P2_SMAPCOEF7 STV090x_Px_SMAPCOEF7(2) -#define STV090x_OFFST_Px_DIS_QSCALE_FIELD 7 -#define STV090x_WIDTH_Px_DIS_QSCALE_FIELD 1 -#define STV090x_OFFST_Px_SMAPCOEF_Q_LLR12_FIELD 0 -#define STV090x_WIDTH_Px_SMAPCOEF_Q_LLR12_FIELD 7 - -#define STV090x_Px_SMAPCOEF6(__x) (0xf501 - (__x - 1) * 0x200) -#define STV090x_P1_SMAPCOEF6 STV090x_Px_SMAPCOEF6(1) -#define STV090x_P2_SMAPCOEF6 STV090x_Px_SMAPCOEF6(2) -#define STV090x_OFFST_Px_ADJ_8PSKLLR1_FIELD 2 -#define STV090x_WIDTH_Px_ADJ_8PSKLLR1_FIELD 1 -#define STV090x_OFFST_Px_OLD_8PSKLLR1_FIELD 1 -#define STV090x_WIDTH_Px_OLD_8PSKLLR1_FIELD 1 -#define STV090x_OFFST_Px_DIS_AB8PSK_FIELD 0 -#define STV090x_WIDTH_Px_DIS_AB8PSK_FIELD 1 - -#define STV090x_Px_SMAPCOEF5(__x) (0xf502 - (__x - 1) * 0x200) -#define STV090x_P1_SMAPCOEF5 STV090x_Px_SMAPCOEF5(1) -#define STV090x_P2_SMAPCOEF5 STV090x_Px_SMAPCOEF5(2) -#define STV090x_OFFST_Px_DIS_8SCALE_FIELD 7 -#define STV090x_WIDTH_Px_DIS_8SCALE_FIELD 1 -#define STV090x_OFFST_Px_SMAPCOEF_8P_LLR23_FIELD 0 -#define STV090x_WIDTH_Px_SMAPCOEF_8P_LLR23_FIELD 7 - -#define STV090x_Px_DMDPLHSTAT(__x) (0xF520 - (__x - 1) * 0x200) -#define STV090x_P1_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(1) -#define STV090x_P2_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(2) -#define STV090x_OFFST_Px_PLH_STATISTIC_FIELD 0 -#define STV090x_WIDTH_Px_PLH_STATISTIC_FIELD 8 - -#define STV090x_Px_LOCKTIMEy(__x, __y) (0xF525 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_LOCKTIME0 STV090x_Px_LOCKTIMEy(1, 0) -#define STV090x_P1_LOCKTIME1 STV090x_Px_LOCKTIMEy(1, 1) -#define STV090x_P1_LOCKTIME2 STV090x_Px_LOCKTIMEy(1, 2) -#define STV090x_P1_LOCKTIME3 STV090x_Px_LOCKTIMEy(1, 3) -#define STV090x_P2_LOCKTIME0 STV090x_Px_LOCKTIMEy(2, 0) -#define STV090x_P2_LOCKTIME1 STV090x_Px_LOCKTIMEy(2, 1) -#define STV090x_P2_LOCKTIME2 STV090x_Px_LOCKTIMEy(2, 2) -#define STV090x_P2_LOCKTIME3 STV090x_Px_LOCKTIMEy(2, 3) -#define STV090x_OFFST_Px_DEMOD_LOCKTIME_FIELD 0 -#define STV090x_WIDTH_Px_DEMOD_LOCKTIME_FIELD 8 - -#define STV090x_Px_TNRCFG(__x) (0xf4e0 - (__x - 1) * 0x200) /* check */ -#define STV090x_P1_TNRCFG STV090x_Px_TNRCFG(1) -#define STV090x_P2_TNRCFG STV090x_Px_TNRCFG(2) - -#define STV090x_Px_TNRCFG2(__x) (0xf4e1 - (__x - 1) * 0x200) -#define STV090x_P1_TNRCFG2 STV090x_Px_TNRCFG2(1) -#define STV090x_P2_TNRCFG2 STV090x_Px_TNRCFG2(2) -#define STV090x_OFFST_Px_TUN_IQSWAP_FIELD 7 -#define STV090x_WIDTH_Px_TUN_IQSWAP_FIELD 1 - -#define STV090x_Px_VITSCALE(__x) (0xf532 - (__x - 1) * 0x200) -#define STV090x_P1_VITSCALE STV090x_Px_VITSCALE(1) -#define STV090x_P2_VITSCALE STV090x_Px_VITSCALE(2) -#define STV090x_OFFST_Px_NVTH_NOSRANGE_FIELD 7 -#define STV090x_WIDTH_Px_NVTH_NOSRANGE_FIELD 1 -#define STV090x_OFFST_Px_VERROR_MAXMODE_FIELD 6 -#define STV090x_WIDTH_Px_VERROR_MAXMODE_FIELD 1 -#define STV090x_OFFST_Px_NSLOWSN_LOCKED_FIELD 3 -#define STV090x_WIDTH_Px_NSLOWSN_LOCKED_FIELD 1 -#define STV090x_OFFST_Px_DIS_RSFLOCK_FIELD 1 -#define STV090x_WIDTH_Px_DIS_RSFLOCK_FIELD 1 - -#define STV090x_Px_FECM(__x) (0xf533 - (__x - 1) * 0x200) -#define STV090x_P1_FECM STV090x_Px_FECM(1) -#define STV090x_P2_FECM STV090x_Px_FECM(2) -#define STV090x_OFFST_Px_DSS_DVB_FIELD 7 -#define STV090x_WIDTH_Px_DSS_DVB_FIELD 1 -#define STV090x_OFFST_Px_DSS_SRCH_FIELD 4 -#define STV090x_WIDTH_Px_DSS_SRCH_FIELD 1 -#define STV090x_OFFST_Px_SYNCVIT_FIELD 1 -#define STV090x_WIDTH_Px_SYNCVIT_FIELD 1 -#define STV090x_OFFST_Px_IQINV_FIELD 0 -#define STV090x_WIDTH_Px_IQINV_FIELD 1 - -#define STV090x_Px_VTH12(__x) (0xf534 - (__x - 1) * 0x200) -#define STV090x_P1_VTH12 STV090x_Px_VTH12(1) -#define STV090x_P2_VTH12 STV090x_Px_VTH12(2) -#define STV090x_OFFST_Px_VTH12_FIELD 0 -#define STV090x_WIDTH_Px_VTH12_FIELD 8 - -#define STV090x_Px_VTH23(__x) (0xf535 - (__x - 1) * 0x200) -#define STV090x_P1_VTH23 STV090x_Px_VTH23(1) -#define STV090x_P2_VTH23 STV090x_Px_VTH23(2) -#define STV090x_OFFST_Px_VTH23_FIELD 0 -#define STV090x_WIDTH_Px_VTH23_FIELD 8 - -#define STV090x_Px_VTH34(__x) (0xf536 - (__x - 1) * 0x200) -#define STV090x_P1_VTH34 STV090x_Px_VTH34(1) -#define STV090x_P2_VTH34 STV090x_Px_VTH34(2) -#define STV090x_OFFST_Px_VTH34_FIELD 0 -#define STV090x_WIDTH_Px_VTH34_FIELD 8 - -#define STV090x_Px_VTH56(__x) (0xf537 - (__x - 1) * 0x200) -#define STV090x_P1_VTH56 STV090x_Px_VTH56(1) -#define STV090x_P2_VTH56 STV090x_Px_VTH56(2) -#define STV090x_OFFST_Px_VTH56_FIELD 0 -#define STV090x_WIDTH_Px_VTH56_FIELD 8 - -#define STV090x_Px_VTH67(__x) (0xf538 - (__x - 1) * 0x200) -#define STV090x_P1_VTH67 STV090x_Px_VTH67(1) -#define STV090x_P2_VTH67 STV090x_Px_VTH67(2) -#define STV090x_OFFST_Px_VTH67_FIELD 0 -#define STV090x_WIDTH_Px_VTH67_FIELD 8 - -#define STV090x_Px_VTH78(__x) (0xf539 - (__x - 1) * 0x200) -#define STV090x_P1_VTH78 STV090x_Px_VTH78(1) -#define STV090x_P2_VTH78 STV090x_Px_VTH78(2) -#define STV090x_OFFST_Px_VTH78_FIELD 0 -#define STV090x_WIDTH_Px_VTH78_FIELD 8 - -#define STV090x_Px_VITCURPUN(__x) (0xf53a - (__x - 1) * 0x200) -#define STV090x_P1_VITCURPUN STV090x_Px_VITCURPUN(1) -#define STV090x_P2_VITCURPUN STV090x_Px_VITCURPUN(2) -#define STV090x_OFFST_Px_VIT_CURPUN_FIELD 0 -#define STV090x_WIDTH_Px_VIT_CURPUN_FIELD 5 - -#define STV090x_Px_VERROR(__x) (0xf53b - (__x - 1) * 0x200) -#define STV090x_P1_VERROR STV090x_Px_VERROR(1) -#define STV090x_P2_VERROR STV090x_Px_VERROR(2) -#define STV090x_OFFST_Px_REGERR_VIT_FIELD 0 -#define STV090x_WIDTH_Px_REGERR_VIT_FIELD 8 - -#define STV090x_Px_PRVIT(__x) (0xf53c - (__x - 1) * 0x200) -#define STV090x_P1_PRVIT STV090x_Px_PRVIT(1) -#define STV090x_P2_PRVIT STV090x_Px_PRVIT(2) -#define STV090x_OFFST_Px_DIS_VTHLOCK_FIELD 6 -#define STV090x_WIDTH_Px_DIS_VTHLOCK_FIELD 1 -#define STV090x_OFFST_Px_E7_8VIT_FIELD 5 -#define STV090x_WIDTH_Px_E7_8VIT_FIELD 1 -#define STV090x_OFFST_Px_E6_7VIT_FIELD 4 -#define STV090x_WIDTH_Px_E6_7VIT_FIELD 1 -#define STV090x_OFFST_Px_E5_6VIT_FIELD 3 -#define STV090x_WIDTH_Px_E5_6VIT_FIELD 1 -#define STV090x_OFFST_Px_E3_4VIT_FIELD 2 -#define STV090x_WIDTH_Px_E3_4VIT_FIELD 1 -#define STV090x_OFFST_Px_E2_3VIT_FIELD 1 -#define STV090x_WIDTH_Px_E2_3VIT_FIELD 1 -#define STV090x_OFFST_Px_E1_2VIT_FIELD 0 -#define STV090x_WIDTH_Px_E1_2VIT_FIELD 1 - -#define STV090x_Px_VAVSRVIT(__x) (0xf53d - (__x - 1) * 0x200) -#define STV090x_P1_VAVSRVIT STV090x_Px_VAVSRVIT(1) -#define STV090x_P2_VAVSRVIT STV090x_Px_VAVSRVIT(2) -#define STV090x_OFFST_Px_SNVIT_FIELD 4 -#define STV090x_WIDTH_Px_SNVIT_FIELD 2 -#define STV090x_OFFST_Px_TOVVIT_FIELD 2 -#define STV090x_WIDTH_Px_TOVVIT_FIELD 2 -#define STV090x_OFFST_Px_HYPVIT_FIELD 0 -#define STV090x_WIDTH_Px_HYPVIT_FIELD 2 - -#define STV090x_Px_VSTATUSVIT(__x) (0xf53e - (__x - 1) * 0x200) -#define STV090x_P1_VSTATUSVIT STV090x_Px_VSTATUSVIT(1) -#define STV090x_P2_VSTATUSVIT STV090x_Px_VSTATUSVIT(2) -#define STV090x_OFFST_Px_PRFVIT_FIELD 4 -#define STV090x_WIDTH_Px_PRFVIT_FIELD 1 -#define STV090x_OFFST_Px_LOCKEDVIT_FIELD 3 -#define STV090x_WIDTH_Px_LOCKEDVIT_FIELD 1 - -#define STV090x_Px_VTHINUSE(__x) (0xf53f - (__x - 1) * 0x200) -#define STV090x_P1_VTHINUSE STV090x_Px_VTHINUSE(1) -#define STV090x_P2_VTHINUSE STV090x_Px_VTHINUSE(2) -#define STV090x_OFFST_Px_VIT_INUSE_FIELD 0 -#define STV090x_WIDTH_Px_VIT_INUSE_FIELD 8 - -#define STV090x_Px_KDIV12(__x) (0xf540 - (__x - 1) * 0x200) -#define STV090x_P1_KDIV12 STV090x_Px_KDIV12(1) -#define STV090x_P2_KDIV12 STV090x_Px_KDIV12(2) -#define STV090x_OFFST_Px_K_DIVIDER_12_FIELD 0 -#define STV090x_WIDTH_Px_K_DIVIDER_12_FIELD 7 - -#define STV090x_Px_KDIV23(__x) (0xf541 - (__x - 1) * 0x200) -#define STV090x_P1_KDIV23 STV090x_Px_KDIV23(1) -#define STV090x_P2_KDIV23 STV090x_Px_KDIV23(2) -#define STV090x_OFFST_Px_K_DIVIDER_23_FIELD 0 -#define STV090x_WIDTH_Px_K_DIVIDER_23_FIELD 7 - -#define STV090x_Px_KDIV34(__x) (0xf542 - (__x - 1) * 0x200) -#define STV090x_P1_KDIV34 STV090x_Px_KDIV34(1) -#define STV090x_P2_KDIV34 STV090x_Px_KDIV34(2) -#define STV090x_OFFST_Px_K_DIVIDER_34_FIELD 0 -#define STV090x_WIDTH_Px_K_DIVIDER_34_FIELD 7 - -#define STV090x_Px_KDIV56(__x) (0xf543 - (__x - 1) * 0x200) -#define STV090x_P1_KDIV56 STV090x_Px_KDIV56(1) -#define STV090x_P2_KDIV56 STV090x_Px_KDIV56(2) -#define STV090x_OFFST_Px_K_DIVIDER_56_FIELD 0 -#define STV090x_WIDTH_Px_K_DIVIDER_56_FIELD 7 - -#define STV090x_Px_KDIV67(__x) (0xf544 - (__x - 1) * 0x200) -#define STV090x_P1_KDIV67 STV090x_Px_KDIV67(1) -#define STV090x_P2_KDIV67 STV090x_Px_KDIV67(2) -#define STV090x_OFFST_Px_K_DIVIDER_67_FIELD 0 -#define STV090x_WIDTH_Px_K_DIVIDER_67_FIELD 7 - -#define STV090x_Px_KDIV78(__x) (0xf545 - (__x - 1) * 0x200) -#define STV090x_P1_KDIV78 STV090x_Px_KDIV78(1) -#define STV090x_P2_KDIV78 STV090x_Px_KDIV78(2) -#define STV090x_OFFST_Px_K_DIVIDER_78_FIELD 0 -#define STV090x_WIDTH_Px_K_DIVIDER_78_FIELD 7 - -#define STV090x_Px_PDELCTRL1(__x) (0xf550 - (__x - 1) * 0x200) -#define STV090x_P1_PDELCTRL1 STV090x_Px_PDELCTRL1(1) -#define STV090x_P2_PDELCTRL1 STV090x_Px_PDELCTRL1(2) -#define STV090x_OFFST_Px_INV_MISMASK_FIELD 7 -#define STV090x_WIDTH_Px_INV_MISMASK_FIELD 1 -#define STV090x_OFFST_Px_FILTER_EN_FIELD 5 -#define STV090x_WIDTH_Px_FILTER_EN_FIELD 1 -#define STV090x_OFFST_Px_EN_MIS00_FIELD 1 -#define STV090x_WIDTH_Px_EN_MIS00_FIELD 1 -#define STV090x_OFFST_Px_ALGOSWRST_FIELD 0 -#define STV090x_WIDTH_Px_ALGOSWRST_FIELD 1 - -#define STV090x_Px_PDELCTRL2(__x) (0xf551 - (__x - 1) * 0x200) -#define STV090x_P1_PDELCTRL2 STV090x_Px_PDELCTRL2(1) -#define STV090x_P2_PDELCTRL2 STV090x_Px_PDELCTRL2(2) -#define STV090x_OFFST_Px_FORCE_CONTINUOUS 7 -#define STV090x_WIDTH_Px_FORCE_CONTINUOUS 1 -#define STV090x_OFFST_Px_RESET_UPKO_COUNT 6 -#define STV090x_WIDTH_Px_RESET_UPKO_COUNT 1 -#define STV090x_OFFST_Px_USER_PKTDELIN_NB 5 -#define STV090x_WIDTH_Px_USER_PKTDELIN_NB 1 -#define STV090x_OFFST_Px_FORCE_LOCKED 4 -#define STV090x_WIDTH_Px_FORCE_LOCKED 1 -#define STV090x_OFFST_Px_DATA_UNBBSCRAM 3 -#define STV090x_WIDTH_Px_DATA_UNBBSCRAM 1 -#define STV090x_OFFST_Px_FORCE_LONGPACKET 2 -#define STV090x_WIDTH_Px_FORCE_LONGPACKET 1 -#define STV090x_OFFST_Px_FRAME_MODE_FIELD 1 -#define STV090x_WIDTH_Px_FRAME_MODE_FIELD 1 - -#define STV090x_Px_HYSTTHRESH(__x) (0xf554 - (__x - 1) * 0x200) -#define STV090x_P1_HYSTTHRESH STV090x_Px_HYSTTHRESH(1) -#define STV090x_P2_HYSTTHRESH STV090x_Px_HYSTTHRESH(2) -#define STV090x_OFFST_Px_UNLCK_THRESH_FIELD 4 -#define STV090x_WIDTH_Px_UNLCK_THRESH_FIELD 4 -#define STV090x_OFFST_Px_DELIN_LCK_THRESH_FIELD 0 -#define STV090x_WIDTH_Px_DELIN_LCK_THRESH_FIELD 4 - -#define STV090x_Px_ISIENTRY(__x) (0xf55e - (__x - 1) * 0x200) -#define STV090x_P1_ISIENTRY STV090x_Px_ISIENTRY(1) -#define STV090x_P2_ISIENTRY STV090x_Px_ISIENTRY(2) -#define STV090x_OFFST_Px_ISI_ENTRY_FIELD 0 -#define STV090x_WIDTH_Px_ISI_ENTRY_FIELD 8 - -#define STV090x_Px_ISIBITENA(__x) (0xf55f - (__x - 1) * 0x200) -#define STV090x_P1_ISIBITENA STV090x_Px_ISIBITENA(1) -#define STV090x_P2_ISIBITENA STV090x_Px_ISIBITENA(2) -#define STV090x_OFFST_Px_ISI_BIT_EN_FIELD 0 -#define STV090x_WIDTH_Px_ISI_BIT_EN_FIELD 8 - -#define STV090x_Px_MATSTRy(__x, __y) (0xf561 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_MATSTR0 STV090x_Px_MATSTRy(1, 0) -#define STV090x_P1_MATSTR1 STV090x_Px_MATSTRy(1, 1) -#define STV090x_P2_MATSTR0 STV090x_Px_MATSTRy(2, 0) -#define STV090x_P2_MATSTR1 STV090x_Px_MATSTRy(2, 1) -#define STV090x_OFFST_Px_MATYPE_CURRENT_FIELD 0 -#define STV090x_WIDTH_Px_MATYPE_CURRENT_FIELD 8 - -#define STV090x_Px_UPLSTRy(__x, __y) (0xf563 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_UPLSTR0 STV090x_Px_UPLSTRy(1, 0) -#define STV090x_P1_UPLSTR1 STV090x_Px_UPLSTRy(1, 1) -#define STV090x_P2_UPLSTR0 STV090x_Px_UPLSTRy(2, 0) -#define STV090x_P2_UPLSTR1 STV090x_Px_UPLSTRy(2, 1) -#define STV090x_OFFST_Px_UPL_CURRENT_FIELD 0 -#define STV090x_WIDTH_Px_UPL_CURRENT_FIELD 8 - -#define STV090x_Px_DFLSTRy(__x, __y) (0xf565 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_DFLSTR0 STV090x_Px_DFLSTRy(1, 0) -#define STV090x_P1_DFLSTR1 STV090x_Px_DFLSTRy(1, 1) -#define STV090x_P2_DFLSTR0 STV090x_Px_DFLSTRy(2, 0) -#define STV090x_P2_DFLSTR1 STV090x_Px_DFLSTRy(2, 1) -#define STV090x_OFFST_Px_DFL_CURRENT_FIELD 0 -#define STV090x_WIDTH_Px_DFL_CURRENT_FIELD 8 - -#define STV090x_Px_SYNCSTR(__x) (0xf566 - (__x - 1) * 0x200) -#define STV090x_P1_SYNCSTR STV090x_Px_SYNCSTR(1) -#define STV090x_P2_SYNCSTR STV090x_Px_SYNCSTR(2) -#define STV090x_OFFST_Px_SYNC_CURRENT_FIELD 0 -#define STV090x_WIDTH_Px_SYNC_CURRENT_FIELD 8 - -#define STV090x_Px_SYNCDSTRy(__x, __y) (0xf568 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_SYNCDSTR0 STV090x_Px_SYNCDSTRy(1, 0) -#define STV090x_P1_SYNCDSTR1 STV090x_Px_SYNCDSTRy(1, 1) -#define STV090x_P2_SYNCDSTR0 STV090x_Px_SYNCDSTRy(2, 0) -#define STV090x_P2_SYNCDSTR1 STV090x_Px_SYNCDSTRy(2, 1) -#define STV090x_OFFST_Px_SYNCD_CURRENT_FIELD 0 -#define STV090x_WIDTH_Px_SYNCD_CURRENT_FIELD 8 - -#define STV090x_Px_PDELSTATUS1(__x) (0xf569 - (__x - 1) * 0x200) -#define STV090x_P1_PDELSTATUS1 STV090x_Px_PDELSTATUS1(1) -#define STV090x_P2_PDELSTATUS1 STV090x_Px_PDELSTATUS1(2) -#define STV090x_OFFST_Px_PKTDELIN_LOCK_FIELD 1 -#define STV090x_WIDTH_Px_PKTDELIN_LOCK_FIELD 1 -#define STV090x_OFFST_Px_FIRST_LOCK_FIELD 0 -#define STV090x_WIDTH_Px_FIRST_LOCK_FIELD 1 - -#define STV090x_Px_PDELSTATUS2(__x) (0xf56a - (__x - 1) * 0x200) -#define STV090x_P1_PDELSTATUS2 STV090x_Px_PDELSTATUS2(1) -#define STV090x_P2_PDELSTATUS2 STV090x_Px_PDELSTATUS2(2) -#define STV090x_OFFST_Px_FRAME_MODCOD_FIELD 2 -#define STV090x_WIDTH_Px_FRAME_MODCOD_FIELD 5 -#define STV090x_OFFST_Px_FRAME_TYPE_FIELD 0 -#define STV090x_WIDTH_Px_FRAME_TYPE_FIELD 2 - -#define STV090x_Px_BBFCRCKO1(__x) (0xf56b - (__x - 1) * 0x200) -#define STV090x_P1_BBFCRCKO1 STV090x_Px_BBFCRCKO1(1) -#define STV090x_P2_BBFCRCKO1 STV090x_Px_BBFCRCKO1(2) -#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD 0 -#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD 8 - -#define STV090x_Px_BBFCRCKO0(__x) (0xf56c - (__x - 1) * 0x200) -#define STV090x_P1_BBFCRCKO0 STV090x_Px_BBFCRCKO0(1) -#define STV090x_P2_BBFCRCKO0 STV090x_Px_BBFCRCKO0(2) -#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD 0 -#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD 8 - -#define STV090x_Px_UPCRCKO1(__x) (0xf56d - (__x - 1) * 0x200) -#define STV090x_P1_UPCRCKO1 STV090x_Px_UPCRCKO1(1) -#define STV090x_P2_UPCRCKO1 STV090x_Px_UPCRCKO1(2) -#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD 0 -#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD 8 - -#define STV090x_Px_UPCRCKO0(__x) (0xf56e - (__x - 1) * 0x200) -#define STV090x_P1_UPCRCKO0 STV090x_Px_UPCRCKO0(1) -#define STV090x_P2_UPCRCKO0 STV090x_Px_UPCRCKO0(2) -#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD 0 -#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD 8 - -#define STV090x_NBITER_NFx(__x) (0xFA03 + (__x - 4) * 0x1) -#define STV090x_NBITER_NF4 STV090x_NBITER_NFx(4) -#define STV090x_NBITER_NF5 STV090x_NBITER_NFx(5) -#define STV090x_NBITER_NF6 STV090x_NBITER_NFx(6) -#define STV090x_NBITER_NF7 STV090x_NBITER_NFx(7) -#define STV090x_NBITER_NF8 STV090x_NBITER_NFx(8) -#define STV090x_NBITER_NF9 STV090x_NBITER_NFx(9) -#define STV090x_NBITER_NF10 STV090x_NBITER_NFx(10) -#define STV090x_NBITER_NF11 STV090x_NBITER_NFx(11) -#define STV090x_NBITER_NF12 STV090x_NBITER_NFx(12) -#define STV090x_NBITER_NF13 STV090x_NBITER_NFx(13) -#define STV090x_NBITER_NF14 STV090x_NBITER_NFx(14) -#define STV090x_NBITER_NF15 STV090x_NBITER_NFx(15) -#define STV090x_NBITER_NF16 STV090x_NBITER_NFx(16) -#define STV090x_NBITER_NF17 STV090x_NBITER_NFx(17) - -#define STV090x_NBITERNOERR 0xFA3F -#define STV090x_OFFST_NBITER_STOP_CRIT_FIELD 0 -#define STV090x_WIDTH_NBITER_STOP_CRIT_FIELD 4 - -#define STV090x_GAINLLR_NFx(__x) (0xFA43 + (__x - 4) * 0x1) -#define STV090x_GAINLLR_NF4 STV090x_GAINLLR_NFx(4) -#define STV090x_OFFST_GAINLLR_NF_QP_1_2_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_1_2_FIELD 7 - -#define STV090x_GAINLLR_NF5 STV090x_GAINLLR_NFx(5) -#define STV090x_OFFST_GAINLLR_NF_QP_3_5_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_3_5_FIELD 7 - -#define STV090x_GAINLLR_NF6 STV090x_GAINLLR_NFx(6) -#define STV090x_OFFST_GAINLLR_NF_QP_2_3_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_2_3_FIELD 7 - -#define STV090x_GAINLLR_NF7 STV090x_GAINLLR_NFx(7) -#define STV090x_OFFST_GAINLLR_NF_QP_3_4_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_3_4_FIELD 7 - -#define STV090x_GAINLLR_NF8 STV090x_GAINLLR_NFx(8) -#define STV090x_OFFST_GAINLLR_NF_QP_4_5_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_4_5_FIELD 7 - -#define STV090x_GAINLLR_NF9 STV090x_GAINLLR_NFx(9) -#define STV090x_OFFST_GAINLLR_NF_QP_5_6_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_5_6_FIELD 7 - -#define STV090x_GAINLLR_NF10 STV090x_GAINLLR_NFx(10) -#define STV090x_OFFST_GAINLLR_NF_QP_8_9_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_8_9_FIELD 7 - -#define STV090x_GAINLLR_NF11 STV090x_GAINLLR_NFx(11) -#define STV090x_OFFST_GAINLLR_NF_QP_9_10_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_QP_9_10_FIELD 7 - -#define STV090x_GAINLLR_NF12 STV090x_GAINLLR_NFx(12) -#define STV090x_OFFST_GAINLLR_NF_8P_3_5_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_8P_3_5_FIELD 7 - -#define STV090x_GAINLLR_NF13 STV090x_GAINLLR_NFx(13) -#define STV090x_OFFST_GAINLLR_NF_8P_2_3_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_8P_2_3_FIELD 7 - -#define STV090x_GAINLLR_NF14 STV090x_GAINLLR_NFx(14) -#define STV090x_OFFST_GAINLLR_NF_8P_3_4_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_8P_3_4_FIELD 7 - -#define STV090x_GAINLLR_NF15 STV090x_GAINLLR_NFx(15) -#define STV090x_OFFST_GAINLLR_NF_8P_5_6_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_8P_5_6_FIELD 7 - -#define STV090x_GAINLLR_NF16 STV090x_GAINLLR_NFx(16) -#define STV090x_OFFST_GAINLLR_NF_8P_8_9_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_8P_8_9_FIELD 7 - -#define STV090x_GAINLLR_NF17 STV090x_GAINLLR_NFx(17) -#define STV090x_OFFST_GAINLLR_NF_8P_9_10_FIELD 0 -#define STV090x_WIDTH_GAINLLR_NF_8P_9_10_FIELD 7 - -#define STV090x_GENCFG 0xFA86 -#define STV090x_OFFST_BROADCAST_FIELD 4 -#define STV090x_WIDTH_BROADCAST_FIELD 1 -#define STV090x_OFFST_PRIORITY_FIELD 1 -#define STV090x_WIDTH_PRIORITY_FIELD 1 -#define STV090x_OFFST_DDEMOD_FIELD 0 -#define STV090x_WIDTH_DDEMOD_FIELD 1 - -#define STV090x_LDPCERRx(__x) (0xFA97 - (__x * 0x1)) -#define STV090x_LDPCERR0 STV090x_LDPCERRx(0) -#define STV090x_LDPCERR1 STV090x_LDPCERRx(1) -#define STV090x_OFFST_Px_LDPC_ERRORS_COUNTER_FIELD 0 -#define STV090x_WIDTH_Px_LDPC_ERRORS_COUNTER_FIELD 8 - -#define STV090x_BCHERR 0xFA98 -#define STV090x_OFFST_Px_ERRORFLAG_FIELD 4 -#define STV090x_WIDTH_Px_ERRORFLAG_FIELD 1 -#define STV090x_OFFST_Px_BCH_ERRORS_COUNTER_FIELD 0 -#define STV090x_WIDTH_Px_BCH_ERRORS_COUNTER_FIELD 4 - -#define STV090x_Px_TSSTATEM(__x) (0xF570 - (__x - 1) * 0x200) -#define STV090x_P1_TSSTATEM STV090x_Px_TSSTATEM(1) -#define STV090x_P2_TSSTATEM STV090x_Px_TSSTATEM(2) -#define STV090x_OFFST_Px_TSDIL_ON_FIELD 7 -#define STV090x_WIDTH_Px_TSDIL_ON_FIELD 1 -#define STV090x_OFFST_Px_TSRS_ON_FIELD 5 -#define STV090x_WIDTH_Px_TSRS_ON_FIELD 1 - -#define STV090x_Px_TSCFGH(__x) (0xF572 - (__x - 1) * 0x200) -#define STV090x_P1_TSCFGH STV090x_Px_TSCFGH(1) -#define STV090x_P2_TSCFGH STV090x_Px_TSCFGH(2) -#define STV090x_OFFST_Px_TSFIFO_DVBCI_FIELD 7 -#define STV090x_WIDTH_Px_TSFIFO_DVBCI_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_SERIAL_FIELD 6 -#define STV090x_WIDTH_Px_TSFIFO_SERIAL_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_TEIUPDATE_FIELD 5 -#define STV090x_WIDTH_Px_TSFIFO_TEIUPDATE_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_DUTY50_FIELD 4 -#define STV090x_WIDTH_Px_TSFIFO_DUTY50_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_HSGNLOUT_FIELD 3 -#define STV090x_WIDTH_Px_TSFIFO_HSGNLOUT_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_ERRORMODE_FIELD 1 -#define STV090x_WIDTH_Px_TSFIFO_ERRORMODE_FIELD 2 -#define STV090x_OFFST_Px_RST_HWARE_FIELD 0 -#define STV090x_WIDTH_Px_RST_HWARE_FIELD 1 - -#define STV090x_Px_TSCFGM(__x) (0xF573 - (__x - 1) * 0x200) -#define STV090x_P1_TSCFGM STV090x_Px_TSCFGM(1) -#define STV090x_P2_TSCFGM STV090x_Px_TSCFGM(2) -#define STV090x_OFFST_Px_TSFIFO_MANSPEED_FIELD 6 -#define STV090x_WIDTH_Px_TSFIFO_MANSPEED_FIELD 2 -#define STV090x_OFFST_Px_TSFIFO_PERMDATA_FIELD 5 -#define STV090x_WIDTH_Px_TSFIFO_PERMDATA_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_INVDATA_FIELD 0 -#define STV090x_WIDTH_Px_TSFIFO_INVDATA_FIELD 1 - -#define STV090x_Px_TSCFGL(__x) (0xF574 - (__x - 1) * 0x200) -#define STV090x_P1_TSCFGL STV090x_Px_TSCFGL(1) -#define STV090x_P2_TSCFGL STV090x_Px_TSCFGL(2) -#define STV090x_OFFST_Px_TSFIFO_BCLKDEL1CK_FIELD 6 -#define STV090x_WIDTH_Px_TSFIFO_BCLKDEL1CK_FIELD 2 -#define STV090x_OFFST_Px_BCHERROR_MODE_FIELD 4 -#define STV090x_WIDTH_Px_BCHERROR_MODE_FIELD 2 -#define STV090x_OFFST_Px_TSFIFO_NSGNL2DATA_FIELD 3 -#define STV090x_WIDTH_Px_TSFIFO_NSGNL2DATA_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_EMBINDVB_FIELD 2 -#define STV090x_WIDTH_Px_TSFIFO_EMBINDVB_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_DPUNACT_FIELD 1 -#define STV090x_WIDTH_Px_TSFIFO_DPUNACT_FIELD 1 - -#define STV090x_Px_TSINSDELH(__x) (0xF576 - (__x - 1) * 0x200) -#define STV090x_P1_TSINSDELH STV090x_Px_TSINSDELH(1) -#define STV090x_P2_TSINSDELH STV090x_Px_TSINSDELH(2) -#define STV090x_OFFST_Px_TSDEL_SYNCBYTE_FIELD 7 -#define STV090x_WIDTH_Px_TSDEL_SYNCBYTE_FIELD 1 -#define STV090x_OFFST_Px_TSDEL_XXHEADER_FIELD 6 -#define STV090x_WIDTH_Px_TSDEL_XXHEADER_FIELD 1 - -#define STV090x_Px_TSSPEED(__x) (0xF580 - (__x - 1) * 0x200) -#define STV090x_P1_TSSPEED STV090x_Px_TSSPEED(1) -#define STV090x_P2_TSSPEED STV090x_Px_TSSPEED(2) -#define STV090x_OFFST_Px_TSFIFO_OUTSPEED_FIELD 0 -#define STV090x_WIDTH_Px_TSFIFO_OUTSPEED_FIELD 8 - -#define STV090x_Px_TSSTATUS(__x) (0xF581 - (__x - 1) * 0x200) -#define STV090x_P1_TSSTATUS STV090x_Px_TSSTATUS(1) -#define STV090x_P2_TSSTATUS STV090x_Px_TSSTATUS(2) -#define STV090x_OFFST_Px_TSFIFO_LINEOK_FIELD 7 -#define STV090x_WIDTH_Px_TSFIFO_LINEOK_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_ERROR_FIELD 6 -#define STV090x_WIDTH_Px_TSFIFO_ERROR_FIELD 1 - -#define STV090x_Px_TSSTATUS2(__x) (0xF582 - (__x - 1) * 0x200) -#define STV090x_P1_TSSTATUS2 STV090x_Px_TSSTATUS2(1) -#define STV090x_P2_TSSTATUS2 STV090x_Px_TSSTATUS2(2) -#define STV090x_OFFST_Px_TSFIFO_DEMODSEL_FIELD 7 -#define STV090x_WIDTH_Px_TSFIFO_DEMODSEL_FIELD 1 -#define STV090x_OFFST_Px_TSFIFOSPEED_STORE_FIELD 6 -#define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD 1 -#define STV090x_OFFST_Px_DILXX_RESET_FIELD 5 -#define STV090x_WIDTH_Px_DILXX_RESET_FIELD 1 -#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD 4 -#define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD 1 -#define STV090x_OFFST_Px_SCRAMBDETECT_FIELD 1 -#define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD 1 - -#define STV090x_Px_TSBITRATEy(__x, __y) (0xF584 - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_TSBITRATE0 STV090x_Px_TSBITRATEy(1, 0) -#define STV090x_P1_TSBITRATE1 STV090x_Px_TSBITRATEy(1, 1) -#define STV090x_P2_TSBITRATE0 STV090x_Px_TSBITRATEy(2, 0) -#define STV090x_P2_TSBITRATE1 STV090x_Px_TSBITRATEy(2, 1) -#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD 0 -#define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD 8 - -#define STV090x_Px_ERRCTRL1(__x) (0xF598 - (__x - 1) * 0x200) -#define STV090x_P1_ERRCTRL1 STV090x_Px_ERRCTRL1(1) -#define STV090x_P2_ERRCTRL1 STV090x_Px_ERRCTRL1(2) -#define STV090x_OFFST_Px_ERR_SOURCE_FIELD 4 -#define STV090x_WIDTH_Px_ERR_SOURCE_FIELD 4 -#define STV090x_OFFST_Px_NUM_EVENT_FIELD 0 -#define STV090x_WIDTH_Px_NUM_EVENT_FIELD 3 - -#define STV090x_Px_ERRCNT12(__x) (0xF599 - (__x - 1) * 0x200) -#define STV090x_P1_ERRCNT12 STV090x_Px_ERRCNT12(1) -#define STV090x_P2_ERRCNT12 STV090x_Px_ERRCNT12(2) -#define STV090x_OFFST_Px_ERRCNT1_OLDVALUE_FIELD 7 -#define STV090x_WIDTH_Px_ERRCNT1_OLDVALUE_FIELD 1 -#define STV090x_OFFST_Px_ERR_CNT12_FIELD 0 -#define STV090x_WIDTH_Px_ERR_CNT12_FIELD 7 - -#define STV090x_Px_ERRCNT11(__x) (0xF59A - (__x - 1) * 0x200) -#define STV090x_P1_ERRCNT11 STV090x_Px_ERRCNT11(1) -#define STV090x_P2_ERRCNT11 STV090x_Px_ERRCNT11(2) -#define STV090x_OFFST_Px_ERR_CNT11_FIELD 0 -#define STV090x_WIDTH_Px_ERR_CNT11_FIELD 8 - -#define STV090x_Px_ERRCNT10(__x) (0xF59B - (__x - 1) * 0x200) -#define STV090x_P1_ERRCNT10 STV090x_Px_ERRCNT10(1) -#define STV090x_P2_ERRCNT10 STV090x_Px_ERRCNT10(2) -#define STV090x_OFFST_Px_ERR_CNT10_FIELD 0 -#define STV090x_WIDTH_Px_ERR_CNT10_FIELD 8 - -#define STV090x_Px_ERRCTRL2(__x) (0xF59C - (__x - 1) * 0x200) -#define STV090x_P1_ERRCTRL2 STV090x_Px_ERRCTRL2(1) -#define STV090x_P2_ERRCTRL2 STV090x_Px_ERRCTRL2(2) -#define STV090x_OFFST_Px_ERR_SOURCE2_FIELD 4 -#define STV090x_WIDTH_Px_ERR_SOURCE2_FIELD 4 -#define STV090x_OFFST_Px_NUM_EVENT2_FIELD 0 -#define STV090x_WIDTH_Px_NUM_EVENT2_FIELD 3 - -#define STV090x_Px_ERRCNT22(__x) (0xF59D - (__x - 1) * 0x200) -#define STV090x_P1_ERRCNT22 STV090x_Px_ERRCNT22(1) -#define STV090x_P2_ERRCNT22 STV090x_Px_ERRCNT22(2) -#define STV090x_OFFST_Px_ERRCNT2_OLDVALUE_FIELD 7 -#define STV090x_WIDTH_Px_ERRCNT2_OLDVALUE_FIELD 1 -#define STV090x_OFFST_Px_ERR_CNT2_FIELD 0 -#define STV090x_WIDTH_Px_ERR_CNT2_FIELD 7 - -#define STV090x_Px_ERRCNT21(__x) (0xF59E - (__x - 1) * 0x200) -#define STV090x_P1_ERRCNT21 STV090x_Px_ERRCNT21(1) -#define STV090x_P2_ERRCNT21 STV090x_Px_ERRCNT21(2) -#define STV090x_OFFST_Px_ERR_CNT21_FIELD 0 -#define STV090x_WIDTH_Px_ERR_CNT21_FIELD 8 - -#define STV090x_Px_ERRCNT20(__x) (0xF59F - (__x - 1) * 0x200) -#define STV090x_P1_ERRCNT20 STV090x_Px_ERRCNT20(1) -#define STV090x_P2_ERRCNT20 STV090x_Px_ERRCNT20(2) -#define STV090x_OFFST_Px_ERR_CNT20_FIELD 0 -#define STV090x_WIDTH_Px_ERR_CNT20_FIELD 8 - -#define STV090x_Px_FECSPY(__x) (0xF5A0 - (__x - 1) * 0x200) -#define STV090x_P1_FECSPY STV090x_Px_FECSPY(1) -#define STV090x_P2_FECSPY STV090x_Px_FECSPY(2) -#define STV090x_OFFST_Px_SPY_ENABLE_FIELD 7 -#define STV090x_WIDTH_Px_SPY_ENABLE_FIELD 1 -#define STV090x_OFFST_Px_BERMETER_DATAMAODE_FIELD 2 -#define STV090x_WIDTH_Px_BERMETER_DATAMAODE_FIELD 2 - -#define STV090x_Px_FSPYCFG(__x) (0xF5A1 - (__x - 1) * 0x200) -#define STV090x_P1_FSPYCFG STV090x_Px_FSPYCFG(1) -#define STV090x_P2_FSPYCFG STV090x_Px_FSPYCFG(2) -#define STV090x_OFFST_Px_RST_ON_ERROR_FIELD 5 -#define STV090x_WIDTH_Px_RST_ON_ERROR_FIELD 1 -#define STV090x_OFFST_Px_ONE_SHOT_FIELD 4 -#define STV090x_WIDTH_Px_ONE_SHOT_FIELD 1 -#define STV090x_OFFST_Px_I2C_MODE_FIELD 2 -#define STV090x_WIDTH_Px_I2C_MODE_FIELD 2 - -#define STV090x_Px_FSPYDATA(__x) (0xF5A2 - (__x - 1) * 0x200) -#define STV090x_P1_FSPYDATA STV090x_Px_FSPYDATA(1) -#define STV090x_P2_FSPYDATA STV090x_Px_FSPYDATA(2) -#define STV090x_OFFST_Px_SPY_STUFFING_FIELD 7 -#define STV090x_WIDTH_Px_SPY_STUFFING_FIELD 1 -#define STV090x_OFFST_Px_SPY_CNULLPKT_FIELD 5 -#define STV090x_WIDTH_Px_SPY_CNULLPKT_FIELD 1 -#define STV090x_OFFST_Px_SPY_OUTDATA_MODE_FIELD 0 -#define STV090x_WIDTH_Px_SPY_OUTDATA_MODE_FIELD 5 - -#define STV090x_Px_FSPYOUT(__x) (0xF5A3 - (__x - 1) * 0x200) -#define STV090x_P1_FSPYOUT STV090x_Px_FSPYOUT(1) -#define STV090x_P2_FSPYOUT STV090x_Px_FSPYOUT(2) -#define STV090x_OFFST_Px_FSPY_DIRECT_FIELD 7 -#define STV090x_WIDTH_Px_FSPY_DIRECT_FIELD 1 -#define STV090x_OFFST_Px_STUFF_MODE_FIELD 0 -#define STV090x_WIDTH_Px_STUFF_MODE_FIELD 3 - -#define STV090x_Px_FSTATUS(__x) (0xF5A4 - (__x - 1) * 0x200) -#define STV090x_P1_FSTATUS STV090x_Px_FSTATUS(1) -#define STV090x_P2_FSTATUS STV090x_Px_FSTATUS(2) -#define STV090x_OFFST_Px_SPY_ENDSIM_FIELD 7 -#define STV090x_WIDTH_Px_SPY_ENDSIM_FIELD 1 -#define STV090x_OFFST_Px_VALID_SIM_FIELD 6 -#define STV090x_WIDTH_Px_VALID_SIM_FIELD 1 -#define STV090x_OFFST_Px_FOUND_SIGNAL_FIELD 5 -#define STV090x_WIDTH_Px_FOUND_SIGNAL_FIELD 1 -#define STV090x_OFFST_Px_DSS_SYNCBYTE_FIELD 4 -#define STV090x_WIDTH_Px_DSS_SYNCBYTE_FIELD 1 -#define STV090x_OFFST_Px_RESULT_STATE_FIELD 0 -#define STV090x_WIDTH_Px_RESULT_STATE_FIELD 4 - -#define STV090x_Px_FBERCPT4(__x) (0xF5A8 - (__x - 1) * 0x200) -#define STV090x_P1_FBERCPT4 STV090x_Px_FBERCPT4(1) -#define STV090x_P2_FBERCPT4 STV090x_Px_FBERCPT4(2) -#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 -#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 - -#define STV090x_Px_FBERCPT3(__x) (0xF5A9 - (__x - 1) * 0x200) -#define STV090x_P1_FBERCPT3 STV090x_Px_FBERCPT3(1) -#define STV090x_P2_FBERCPT3 STV090x_Px_FBERCPT3(2) -#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 -#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 - -#define STV090x_Px_FBERCPT2(__x) (0xF5AA - (__x - 1) * 0x200) -#define STV090x_P1_FBERCPT2 STV090x_Px_FBERCPT2(1) -#define STV090x_P2_FBERCPT2 STV090x_Px_FBERCPT2(2) -#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 -#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 - -#define STV090x_Px_FBERCPT1(__x) (0xF5AB - (__x - 1) * 0x200) -#define STV090x_P1_FBERCPT1 STV090x_Px_FBERCPT1(1) -#define STV090x_P2_FBERCPT1 STV090x_Px_FBERCPT1(2) -#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 -#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 - -#define STV090x_Px_FBERCPT0(__x) (0xF5AC - (__x - 1) * 0x200) -#define STV090x_P1_FBERCPT0 STV090x_Px_FBERCPT0(1) -#define STV090x_P2_FBERCPT0 STV090x_Px_FBERCPT0(2) -#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 -#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 - -#define STV090x_Px_FBERERRy(__x, __y) (0xF5AF - (__x - 1) * 0x200 - __y * 0x1) -#define STV090x_P1_FBERERR0 STV090x_Px_FBERERRy(1, 0) -#define STV090x_P1_FBERERR1 STV090x_Px_FBERERRy(1, 1) -#define STV090x_P1_FBERERR2 STV090x_Px_FBERERRy(1, 2) -#define STV090x_P2_FBERERR0 STV090x_Px_FBERERRy(2, 0) -#define STV090x_P2_FBERERR1 STV090x_Px_FBERERRy(2, 1) -#define STV090x_P2_FBERERR2 STV090x_Px_FBERERRy(2, 2) -#define STV090x_OFFST_Px_FBERMETER_CPT_ERR_FIELD 0 -#define STV090x_WIDTH_Px_FBERMETER_CPT_ERR_FIELD 8 - -#define STV090x_Px_FSPYBER(__x) (0xF5B2 - (__x - 1) * 0x200) -#define STV090x_P1_FSPYBER STV090x_Px_FSPYBER(1) -#define STV090x_P2_FSPYBER STV090x_Px_FSPYBER(2) -#define STV090x_OFFST_Px_FSPYBER_SYNCBYTE_FIELD 4 -#define STV090x_WIDTH_Px_FSPYBER_SYNCBYTE_FIELD 1 -#define STV090x_OFFST_Px_FSPYBER_UNSYNC_FIELD 3 -#define STV090x_WIDTH_Px_FSPYBER_UNSYNC_FIELD 1 -#define STV090x_OFFST_Px_FSPYBER_CTIME_FIELD 0 -#define STV090x_WIDTH_Px_FSPYBER_CTIME_FIELD 3 - -#define STV090x_RCCFGH 0xf600 - -#define STV090x_TSGENERAL 0xF630 -#define STV090x_OFFST_Px_MUXSTREAM_OUT_FIELD 3 -#define STV090x_WIDTH_Px_MUXSTREAM_OUT_FIELD 1 -#define STV090x_OFFST_Px_TSFIFO_PERMPARAL_FIELD 1 -#define STV090x_WIDTH_Px_TSFIFO_PERMPARAL_FIELD 2 - -#define STV090x_TSGENERAL1X 0xf670 -#define STV090x_CFGEXT 0xfa80 - -#define STV090x_TSTRES0 0xFF11 -#define STV090x_OFFST_FRESFEC_FIELD 7 -#define STV090x_WIDTH_FRESFEC_FIELD 1 - -#define STV090x_Px_TSTDISRX(__x) (0xFF67 - (__x - 1) * 0x2) -#define STV090x_P1_TSTDISRX STV090x_Px_TSTDISRX(1) -#define STV090x_P2_TSTDISRX STV090x_Px_TSTDISRX(2) -#define STV090x_OFFST_Px_TSTDISRX_SELECT_FIELD 3 -#define STV090x_WIDTH_Px_TSTDISRX_SELECT_FIELD 1 - -#endif /* __STV090x_REG_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,405 +0,0 @@ -/* - STV6110(A) Silicon tuner driver - - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" - -#include "stv6110x_reg.h" -#include "stv6110x.h" -#include "stv6110x_priv.h" - -static unsigned int verbose; -module_param(verbose, int, 0644); -MODULE_PARM_DESC(verbose, "Set Verbosity level"); - -static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data) -{ - int ret; - const struct stv6110x_config *config = stv6110x->config; - u8 b0[] = { reg }; - u8 b1[] = { 0 }; - struct i2c_msg msg[] = { - { .addr = config->addr, .flags = 0, .buf = b0, .len = 1 }, - { .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } - }; - - ret = i2c_transfer(stv6110x->i2c, msg, 2); - if (ret != 2) { - dprintk(FE_ERROR, 1, "I/O Error"); - return -EREMOTEIO; - } - *data = b1[0]; - - return 0; -} - -static int stv6110x_write_regs(struct stv6110x_state *stv6110x, int start, u8 data[], int len) -{ - int ret; - const struct stv6110x_config *config = stv6110x->config; - u8 buf[len + 1]; - struct i2c_msg msg = { - .addr = config->addr, - .flags = 0, - .buf = buf, - .len = len + 1 - }; - - if (start + len > 8) - return -EINVAL; - - buf[0] = start; - memcpy(&buf[1], data, len); - - ret = i2c_transfer(stv6110x->i2c, &msg, 1); - if (ret != 1) { - dprintk(FE_ERROR, 1, "I/O Error"); - return -EREMOTEIO; - } - - return 0; -} - -static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data) -{ - return stv6110x_write_regs(stv6110x, reg, &data, 1); -} - -static int stv6110x_init(struct dvb_frontend *fe) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - int ret; - - ret = stv6110x_write_regs(stv6110x, 0, stv6110x->regs, - ARRAY_SIZE(stv6110x->regs)); - if (ret < 0) { - dprintk(FE_ERROR, 1, "Initialization failed"); - return -1; - } - - return 0; -} - -static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - u32 rDiv, divider; - s32 pVal, pCalc, rDivOpt = 0, pCalcOpt = 1000; - u8 i; - - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16)); - - if (frequency <= 1023000) { - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0); - pVal = 40; - } else if (frequency <= 1300000) { - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1); - pVal = 40; - } else if (frequency <= 2046000) { - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0); - pVal = 20; - } else { - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1); - pVal = 20; - } - - for (rDiv = 0; rDiv <= 3; rDiv++) { - pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv); - - if ((abs((s32)(pCalc - pVal))) < (abs((s32)(pCalcOpt - pVal)))) - rDivOpt = rDiv; - - pCalcOpt = (REFCLOCK_kHz / 100) / R_DIV(rDivOpt); - } - - divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz; - divider = (divider + 5) / 10; - - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider)); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider)); - - /* VCO Auto calibration */ - STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1); - - stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]); - stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x->regs[STV6110x_TNG1]); - stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x->regs[STV6110x_TNG0]); - stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]); - - for (i = 0; i < TRIALS; i++) { - stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]); - if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x->regs[STV6110x_STAT1])) - break; - msleep(1); - } - - return 0; -} - -static int stv6110x_get_frequency(struct dvb_frontend *fe, u32 *frequency) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - - stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x->regs[STV6110x_TNG1]); - stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x->regs[STV6110x_TNG0]); - - *frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x->regs[STV6110x_TNG1]), - STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x->regs[STV6110x_TNG0]))) * REFCLOCK_kHz; - - *frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x->regs[STV6110x_TNG1]) + - STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x->regs[STV6110x_TNG1]))); - - *frequency >>= 2; - - return 0; -} - -static int stv6110x_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - u32 halfbw; - u8 i; - - halfbw = bandwidth >> 1; - - if (halfbw > 36000000) - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */ - else if (halfbw < 5000000) - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */ - else - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */ - - - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */ - STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */ - - stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]); - stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]); - - for (i = 0; i < TRIALS; i++) { - stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]); - if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x->regs[STV6110x_STAT1])) - break; - msleep(1); - } - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */ - stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]); - - return 0; -} - -static int stv6110x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - - stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x->regs[STV6110x_CTRL3]); - *bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x->regs[STV6110x_CTRL3]) + 5) * 2000000; - - return 0; -} - -static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - - /* setup divider */ - switch (refclock) { - default: - case 1: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0); - break; - case 2: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1); - break; - case 4: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2); - break; - case 8: - case 0: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3); - break; - } - stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]); - - return 0; -} - -static int stv6110x_get_bbgain(struct dvb_frontend *fe, u32 *gain) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - - stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x->regs[STV6110x_CTRL2]); - *gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x->regs[STV6110x_CTRL2]); - - return 0; -} - -static int stv6110x_set_bbgain(struct dvb_frontend *fe, u32 gain) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2); - stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]); - - return 0; -} - -static int stv6110x_set_mode(struct dvb_frontend *fe, enum tuner_mode mode) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - int ret; - - switch (mode) { - case TUNER_SLEEP: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 0); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 0); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 0); - break; - - case TUNER_WAKE: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 1); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 1); - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 1); - break; - } - - ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]); - if (ret < 0) { - dprintk(FE_ERROR, 1, "I/O Error"); - return -EIO; - } - - return 0; -} - -static int stv6110x_sleep(struct dvb_frontend *fe) -{ - if (fe->tuner_priv) - return stv6110x_set_mode(fe, TUNER_SLEEP); - - return 0; -} - -static int stv6110x_get_status(struct dvb_frontend *fe, u32 *status) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - - stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]); - - if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x->regs[STV6110x_STAT1])) - *status = TUNER_PHASELOCKED; - else - *status = 0; - - return 0; -} - - -static int stv6110x_release(struct dvb_frontend *fe) -{ - struct stv6110x_state *stv6110x = fe->tuner_priv; - - fe->tuner_priv = NULL; - kfree(stv6110x); - - return 0; -} - -static struct dvb_tuner_ops stv6110x_ops = { - .info = { - .name = "STV6110(A) Silicon Tuner", - .frequency_min = 950000, - .frequency_max = 2150000, - .frequency_step = 0, - }, - .release = stv6110x_release -}; - -static struct stv6110x_devctl stv6110x_ctl = { - .tuner_init = stv6110x_init, - .tuner_sleep = stv6110x_sleep, - .tuner_set_mode = stv6110x_set_mode, - .tuner_set_frequency = stv6110x_set_frequency, - .tuner_get_frequency = stv6110x_get_frequency, - .tuner_set_bandwidth = stv6110x_set_bandwidth, - .tuner_get_bandwidth = stv6110x_get_bandwidth, - .tuner_set_bbgain = stv6110x_set_bbgain, - .tuner_get_bbgain = stv6110x_get_bbgain, - .tuner_set_refclk = stv6110x_set_refclock, - .tuner_get_status = stv6110x_get_status, -}; - -struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, - const struct stv6110x_config *config, - struct i2c_adapter *i2c) -{ - struct stv6110x_state *stv6110x; - u8 default_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e}; - - stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL); - if (!stv6110x) - return NULL; - - stv6110x->i2c = i2c; - stv6110x->config = config; - stv6110x->devctl = &stv6110x_ctl; - memcpy(stv6110x->regs, default_regs, 8); - - /* setup divider */ - switch (stv6110x->config->clk_div) { - default: - case 1: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0); - break; - case 2: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1); - break; - case 4: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2); - break; - case 8: - case 0: - STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3); - break; - } - - fe->tuner_priv = stv6110x; - fe->ops.tuner_ops = stv6110x_ops; - - printk(KERN_INFO "%s: Attaching STV6110x\n", __func__); - return stv6110x->devctl; -} -EXPORT_SYMBOL(stv6110x_attach); - -MODULE_AUTHOR("Manu Abraham"); -MODULE_DESCRIPTION("STV6110x Silicon tuner"); -MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,73 +0,0 @@ -/* - STV6110(A) Silicon tuner driver - - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __STV6110x_H -#define __STV6110x_H - -struct stv6110x_config { - u8 addr; - u32 refclk; - u8 clk_div; /* divisor value for the output clock */ -}; - -enum tuner_mode { - TUNER_SLEEP = 1, - TUNER_WAKE, -}; - -enum tuner_status { - TUNER_PHASELOCKED = 1, -}; - -struct stv6110x_devctl { - int (*tuner_init) (struct dvb_frontend *fe); - int (*tuner_sleep) (struct dvb_frontend *fe); - int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode); - int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency); - int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency); - int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth); - int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth); - int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain); - int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain); - int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk); - int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status); -}; - - -#if defined(CONFIG_DVB_STV6110x) || (defined(CONFIG_DVB_STV6110x_MODULE) && defined(MODULE)) - -extern struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, - const struct stv6110x_config *config, - struct i2c_adapter *i2c); - -#else -static inline struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, - const struct stv6110x_config *config, - struct i2c_adapter *i2c) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} - -#endif /* CONFIG_DVB_STV6110x */ - -#endif /* __STV6110x_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_priv.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_priv.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,76 +0,0 @@ -/* - STV6110(A) Silicon tuner driver - - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __STV6110x_PRIV_H -#define __STV6110x_PRIV_H - -#define FE_ERROR 0 -#define FE_NOTICE 1 -#define FE_INFO 2 -#define FE_DEBUG 3 -#define FE_DEBUGREG 4 - -#define dprintk(__y, __z, format, arg...) do { \ - if (__z) { \ - if ((verbose > FE_ERROR) && (verbose > __y)) \ - printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \ - else if ((verbose > FE_NOTICE) && (verbose > __y)) \ - printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \ - else if ((verbose > FE_INFO) && (verbose > __y)) \ - printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \ - else if ((verbose > FE_DEBUG) && (verbose > __y)) \ - printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \ - } else { \ - if (verbose > __y) \ - printk(format, ##arg); \ - } \ -} while (0) - - -#define STV6110x_SETFIELD(mask, bitf, val) \ - (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \ - STV6110x_OFFST_##bitf))) | \ - (val << STV6110x_OFFST_##bitf)) - -#define STV6110x_GETFIELD(bitf, val) \ - ((val >> STV6110x_OFFST_##bitf) & \ - ((1 << STV6110x_WIDTH_##bitf) - 1)) - -#define MAKEWORD16(a, b) (((a) << 8) | (b)) - -#define LSB(x) ((x & 0xff)) -#define MSB(y) ((y >> 8) & 0xff) - -#define TRIALS 10 -#define R_DIV(__div) (1 << (__div + 1)) -#define REFCLOCK_kHz (stv6110x->config->refclk / 1000) -#define REFCLOCK_MHz (stv6110x->config->refclk / 1000000) - -struct stv6110x_state { - struct i2c_adapter *i2c; - const struct stv6110x_config *config; - u8 regs[8]; - - struct stv6110x_devctl *devctl; -}; - -#endif /* __STV6110x_PRIV_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_reg.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_reg.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_reg.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/stv6110x_reg.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,82 +0,0 @@ -/* - STV6110(A) Silicon tuner driver - - Copyright (C) Manu Abraham - - Copyright (C) ST Microelectronics - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ - -#ifndef __STV6110x_REG_H -#define __STV6110x_REG_H - -#define STV6110x_CTRL1 0x00 -#define STV6110x_OFFST_CTRL1_K 3 -#define STV6110x_WIDTH_CTRL1_K 5 -#define STV6110x_OFFST_CTRL1_LPT 2 -#define STV6110x_WIDTH_CTRL1_LPT 1 -#define STV6110x_OFFST_CTRL1_RX 1 -#define STV6110x_WIDTH_CTRL1_RX 1 -#define STV6110x_OFFST_CTRL1_SYN 0 -#define STV6110x_WIDTH_CTRL1_SYN 1 - -#define STV6110x_CTRL2 0x01 -#define STV6110x_OFFST_CTRL2_CO_DIV 6 -#define STV6110x_WIDTH_CTRL2_CO_DIV 2 -#define STV6110x_OFFST_CTRL2_RSVD 5 -#define STV6110x_WIDTH_CTRL2_RSVD 1 -#define STV6110x_OFFST_CTRL2_REFOUT_SEL 4 -#define STV6110x_WIDTH_CTRL2_REFOUT_SEL 1 -#define STV6110x_OFFST_CTRL2_BBGAIN 0 -#define STV6110x_WIDTH_CTRL2_BBGAIN 4 - -#define STV6110x_TNG0 0x02 -#define STV6110x_OFFST_TNG0_N_DIV_7_0 0 -#define STV6110x_WIDTH_TNG0_N_DIV_7_0 8 - -#define STV6110x_TNG1 0x03 -#define STV6110x_OFFST_TNG1_R_DIV 6 -#define STV6110x_WIDTH_TNG1_R_DIV 2 -#define STV6110x_OFFST_TNG1_PRESC32_ON 5 -#define STV6110x_WIDTH_TNG1_PRESC32_ON 1 -#define STV6110x_OFFST_TNG1_DIV4SEL 4 -#define STV6110x_WIDTH_TNG1_DIV4SEL 1 -#define STV6110x_OFFST_TNG1_N_DIV_11_8 0 -#define STV6110x_WIDTH_TNG1_N_DIV_11_8 4 - - -#define STV6110x_CTRL3 0x04 -#define STV6110x_OFFST_CTRL3_DCLOOP_OFF 7 -#define STV6110x_WIDTH_CTRL3_DCLOOP_OFF 1 -#define STV6110x_OFFST_CTRL3_RCCLK_OFF 6 -#define STV6110x_WIDTH_CTRL3_RCCLK_OFF 1 -#define STV6110x_OFFST_CTRL3_ICP 5 -#define STV6110x_WIDTH_CTRL3_ICP 1 -#define STV6110x_OFFST_CTRL3_CF 0 -#define STV6110x_WIDTH_CTRL3_CF 5 - -#define STV6110x_STAT1 0x05 -#define STV6110x_OFFST_STAT1_CALVCO_STRT 2 -#define STV6110x_WIDTH_STAT1_CALVCO_STRT 1 -#define STV6110x_OFFST_STAT1_CALRC_STRT 1 -#define STV6110x_WIDTH_STAT1_CALRC_STRT 1 -#define STV6110x_OFFST_STAT1_LOCK 0 -#define STV6110x_WIDTH_STAT1_LOCK 1 - -#define STV6110x_STAT2 0x06 -#define STV6110x_STAT3 0x07 - -#endif /* __STV6110x_REG_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,43 +0,0 @@ -/* - * NXP TDA18212HN silicon tuner driver - * - * Copyright (C) 2011 Antti Palosaari - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef TDA18212_H -#define TDA18212_H - -#include "dvb_frontend.h" - -struct tda18212_config { - u8 i2c_address; -}; - -#if defined(CONFIG_DVB_TDA18212) || \ - (defined(CONFIG_DVB_TDA18212_MODULE) && defined(MODULE)) -extern struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, struct tda18212_config *cfg); -#else -static inline struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, struct tda18212_config *cfg) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212_priv.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212_priv.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,45 +0,0 @@ -/* - * NXP TDA18212HN silicon tuner driver - * - * Copyright (C) 2011 Antti Palosaari - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef TDA18212_PRIV_H -#define TDA18212_PRIV_H - -#include "tda18212.h" - -#define LOG_PREFIX "tda18212" - -#undef dbg -#define dbg(f, arg...) \ - if (debug) \ - printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) -#undef err -#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) -#undef info -#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) -#undef warn -#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) - -struct tda18212_priv { - struct tda18212_config *cfg; - struct i2c_adapter *i2c; - u32 IF; -}; - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,937 +0,0 @@ -/* - * tda18212: Driver for the TDA18212 tuner - * - * Copyright (C) 2011 Digital Devices GmbH - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" - -#ifndef CHK_ERROR - #define CHK_ERROR(s) if ((status = s) < 0) break -#endif - -#define MASTER_PSM_AGC1 0 -#define MASTER_AGC1_6_15dB 1 - -#define SLAVE_PSM_AGC1 1 -#define SLAVE_AGC1_6_15dB 0 - -// 0 = 2 Vpp ... 2 = 1 Vpp, 7 = 0.5 Vpp -#define IF_LEVEL_DVBC 2 -#define IF_LEVEL_DVBT 2 - -enum { - ID_1 = 0x00, - ID_2 = 0x01, - ID_3 = 0x02, - THERMO_1, - THERMO_2, - POWER_STATE_1, - POWER_STATE_2, - INPUT_POWER_LEVEL, - IRQ_STATUS, - IRQ_ENABLE, - IRQ_CLEAR, - IRQ_SET, - AGC1_1, - AGC2_1, - AGCK_1, - RF_AGC_1, - IR_MIXER_1 = 0x10, - AGC5_1, - IF_AGC, - IF_1, - REFERENCE, - IF_FREQUENCY_1, - RF_FREQUENCY_1, - RF_FREQUENCY_2, - RF_FREQUENCY_3, - MSM_1, - MSM_2, - PSM_1, - DCC_1, - FLO_MAX, - IR_CAL_1, - IR_CAL_2, - IR_CAL_3 = 0x20, - IR_CAL_4, - VSYNC_MGT, - IR_MIXER_2, - AGC1_2, - AGC5_2, - RF_CAL_1, - RF_CAL_2, - RF_CAL_3, - RF_CAL_4, - RF_CAL_5, - RF_CAL_6, - RF_FILTER_1, - RF_FILTER_2, - RF_FILTER_3, - RF_BAND_PASS_FILTER, - CP_CURRENT = 0x30, - AGC_DET_OUT = 0x31, - RF_AGC_GAIN_1 = 0x32, - RF_AGC_GAIN_2 = 0x33, - IF_AGC_GAIN = 0x34, - POWER_1 = 0x35, - POWER_2 = 0x36, - MISC_1, - RFCAL_LOG_1, - RFCAL_LOG_2, - RFCAL_LOG_3, - RFCAL_LOG_4, - RFCAL_LOG_5, - RFCAL_LOG_6, - RFCAL_LOG_7, - RFCAL_LOG_8, - RFCAL_LOG_9 = 0x40, - RFCAL_LOG_10 = 0x41, - RFCAL_LOG_11 = 0x42, - RFCAL_LOG_12 = 0x43, - REG_MAX, -}; - -enum HF_Standard { - HF_None=0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, - HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, - HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, - HF_DVBC_8MHZ, HF_DVBC -}; - -struct SStandardParams { - s32 m_IFFrequency; - u32 m_BandWidth; - u8 m_IF_1; // FF IF_HP_fc:2 IF_Notch:1 LP_FC_Offset:2 LP_FC:3 - u8 m_IR_MIXER_2; // 03 :6 HI_Pass:1 DC_Notch:1 - u8 m_AGC1_1; // 0F :4 AGC1_Top:4 - u8 m_AGC2_1; // 0F :4 AGC2_Top:4 - u8 m_RF_AGC_1_Low; // EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 - u8 m_RF_AGC_1_High;// EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 - u8 m_IR_MIXER_1; // 0F :4 IR_mixer_Top:4 - u8 m_AGC5_1; // 1F :3 AGC5_Ana AGC5_Top:4 - u8 m_AGCK_1; // 0F :4 AGCK_Step:2 AGCK_Mode:2 - u8 m_PSM_1; // 20 :2 PSM_StoB:1 :5 - bool m_AGC1_Freeze; - bool m_LTO_STO_immune; -}; - -#if 0 -static struct SStandardParams m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = -{ - { 3250000, 6000000, 0x20, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_6MHZ - { 3500000, 7000000, 0x31, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_7MHZ - { 4000000, 8000000, 0x22, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_8MHZ - { 0, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, // HF_DVBT (Unused) - { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, // HF_ATSC - { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_6MHZ -// { 5000000, 7000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -// { 5000000, 8000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ - { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) - { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -}; -#else -static struct SStandardParams m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = -{ - { 4000000, 6000000, 0x41, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_6MHZ - { 4500000, 7000000, 0x42, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_7MHZ - { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_8MHZ - // ------------------------------ - { 0, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, // HF_DVBT (Unused) - { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, // HF_ATSC - { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_6MHZ -// { 5000000, 7000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -// { 5000000, 8000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ - { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) - { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -}; -#endif -struct tda_state { - struct i2c_adapter *i2c; - u8 adr; - - enum HF_Standard m_Standard; - u32 m_Frequency; - u32 IF; - - bool m_isMaster; - bool m_bPowerMeasurement; - bool m_bLTEnable; - bool m_bEnableFreeze; - - u16 m_ID; - - s32 m_SettlingTime; - - u8 m_IFLevelDVBC; - u8 m_IFLevelDVBT; - u8 m_Regs[REG_MAX]; - u8 m_LastPowerLevel; -}; - -static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) -{ - struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, - .buf = data, .len = len}}; - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -} - -static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) -{ - struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, - .buf = msg, .len = len}, - { .addr = adr, .flags = I2C_M_RD, - .buf = answ, .len = alen } }; - if (i2c_transfer(adap, msgs, 2) != 2) { - printk("tda18212dd: i2c_read error\n"); - return -1; - } - return 0; -} - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = {.addr = adr, .flags = 0, - .buf = data, .len = len}; - - if (i2c_transfer(adap, &msg, 1) != 1) { - printk("tda18212: i2c_write error\n"); - return -1; - } - return 0; -} - -static int write_regs(struct tda_state *state, - u8 SubAddr, u8 *Regs, u16 nRegs) -{ - u8 data[nRegs+1]; - - data[0] = SubAddr; - memcpy(data + 1, Regs, nRegs); - return i2c_write(state->i2c, state->adr, data, nRegs+1); -} - -static int write_reg(struct tda_state *state, u8 SubAddr,u8 Reg) -{ - u8 msg[2] = {SubAddr, Reg}; - - return i2c_write(state->i2c, state->adr, msg, 2); -} - -static int Read(struct tda_state *state, u8 * Regs) -{ - return i2c_readn(state->i2c, state->adr, Regs, REG_MAX); -} - -static int update_regs(struct tda_state *state, u8 RegFrom,u8 RegTo) -{ - return write_regs(state, RegFrom, - &state->m_Regs[RegFrom], RegTo-RegFrom+1); -} - -static int update_reg(struct tda_state *state, u8 Reg) -{ - return write_reg(state, Reg,state->m_Regs[Reg]); -} - - -static int read_regs(struct tda_state *state, - u8 SubAddr, u8 *Regs, u16 nRegs) -{ - return i2c_read(state->i2c, state->adr, - &SubAddr, 1, Regs, nRegs); -} - -static int read_reg(struct tda_state *state, - u8 SubAddr, u8 *Reg) -{ - return i2c_read(state->i2c, state->adr, - &SubAddr, 1, Reg, 1); -} - -static int read_reg1(struct tda_state *state, u8 Reg) -{ - return read_reg(state, Reg, &state->m_Regs[Reg]); -} - -static void init_state(struct tda_state *state) -{ - u32 ulIFLevelDVBC = IF_LEVEL_DVBC; - u32 ulIFLevelDVBT = IF_LEVEL_DVBT; - u32 ulPowerMeasurement = 1; - u32 ulLTEnable = 1; - u32 ulEnableFreeze = 0; - - state->m_Frequency = 0; - state->m_isMaster = true; - state->m_ID = 0; - state->m_LastPowerLevel = 0xFF; - state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07); - state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07); - state->m_bPowerMeasurement = (ulPowerMeasurement != 0); - state->m_bLTEnable = (ulLTEnable != 0); - state->m_bEnableFreeze = (ulEnableFreeze != 0); -} - -static int StartCalibration(struct tda_state *state) -{ - int status = 0; - do { - state->m_Regs[POWER_2] &= ~0x02; // RSSI CK = 31.25 kHz - CHK_ERROR(update_reg(state, POWER_2)); - - state->m_Regs[AGC1_2] = (state->m_Regs[AGC1_2] & ~0x60) | 0x40; // AGC1 Do Step = 2 - CHK_ERROR(update_reg(state, AGC1_2)); // AGC - - state->m_Regs[RF_FILTER_3] = (state->m_Regs[RF_FILTER_3] & ~0xC0) | 0x40; // AGC2 Do Step = 1 - CHK_ERROR(update_reg(state, RF_FILTER_3)); - - state->m_Regs[AGCK_1] |= 0xC0; // AGCs Assym Up Step = 3 // Datasheet sets all bits to 1! - CHK_ERROR(update_reg(state, AGCK_1)); - - state->m_Regs[AGC5_1] = (state->m_Regs[AGC5_1] & ~0x60) | 0x40; // AGCs Assym Do Step = 2 - CHK_ERROR(update_reg(state, AGC5_1)); - - state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ - CHK_ERROR(update_reg(state, IRQ_CLEAR)); - - state->m_Regs[MSM_1] = 0x3B; // Set Calibration - state->m_Regs[MSM_2] = 0x01; // Start MSM - CHK_ERROR(update_regs(state, MSM_1,MSM_2)); - state->m_Regs[MSM_2] = 0x00; - - } while(0); - return status; -} - -static int FinishCalibration(struct tda_state *state) -{ - int status = 0; - u8 RFCal_Log[12]; - - do { - u8 IRQ = 0; - int Timeout = 150; // 1.5 s - while(true) { - CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); - if ((IRQ & 0x80) != 0 ) - break; - Timeout -= 1; - if (Timeout == 0) { - status = -1; - break; - } - msleep(10); - } - CHK_ERROR(status); - - state->m_Regs[FLO_MAX] = 0x0A; - CHK_ERROR(update_reg(state, FLO_MAX)); - - state->m_Regs[AGC1_1] &= ~0xC0; - if( state->m_bLTEnable ) state->m_Regs[AGC1_1] |= 0x80; // LTEnable - - state->m_Regs[AGC1_1] |= (state->m_isMaster ? MASTER_AGC1_6_15dB : SLAVE_AGC1_6_15dB ) << 6; - CHK_ERROR(update_reg(state, AGC1_1)); - - state->m_Regs[PSM_1] &= ~0xC0; - state->m_Regs[PSM_1] |= (state->m_isMaster ? MASTER_PSM_AGC1 : SLAVE_PSM_AGC1 ) << 6; - CHK_ERROR(update_reg(state, PSM_1)); - - state->m_Regs[REFERENCE] |= 0x03; // XTOUT = 3 - CHK_ERROR(update_reg(state, REFERENCE)); - - CHK_ERROR(read_regs(state, RFCAL_LOG_1,RFCal_Log,sizeof(RFCal_Log))); - } while(0); - return status; -} - -static int PowerOn(struct tda_state *state) -{ - state->m_Regs[POWER_STATE_2] &= ~0x0F; - update_reg(state, POWER_STATE_2); - state->m_Regs[REFERENCE] |= 0x40; // Digital clock source = Sigma Delta - update_reg(state, REFERENCE); - return 0; -} - -static int Standby(struct tda_state *state) -{ - int status = 0; - - do { - state->m_Regs[REFERENCE] &= ~0x40; // Digital clock source = Quarz - CHK_ERROR(update_reg(state, REFERENCE)); - - state->m_Regs[POWER_STATE_2] &= ~0x0F; - state->m_Regs[POWER_STATE_2] |= state->m_isMaster ? 0x08 : 0x0E; - CHK_ERROR(update_reg(state, POWER_STATE_2)); - } while(0); - return status; -} - -static int attach_init(struct tda_state *state) -{ - int stat = 0; - u8 Id[2]; - u8 PowerState = 0x00; - - state->m_Standard = HF_None; - - /* first read after cold reset sometimes fails on some cards, - try twice */ - stat = read_regs(state, ID_1, Id, sizeof(Id)); - stat = read_regs(state, ID_1, Id, sizeof(Id)); - if (stat < 0) - return -1; - - state->m_ID = ((Id[0] & 0x7F) << 8) | Id[1]; - state->m_isMaster = ((Id[0] & 0x80) != 0); - if( !state->m_isMaster ) - state->m_bLTEnable = false; - - printk("tda18212dd: ChipID %04x\n", state->m_ID); - - if( state->m_ID != 18212 ) - return -1; - - stat = read_reg(state, POWER_STATE_1 ,&PowerState); - if (stat < 0) - return stat; - - printk("tda18212dd: PowerState %02x\n", PowerState); - - if (state->m_isMaster) { - if( PowerState & 0x02 ) { - // msleep for XTAL Calibration (on a PC this should be long done) - u8 IRQStatus = 0; - int Timeout = 10; - - while(Timeout > 0) { - read_reg(state, IRQ_STATUS, &IRQStatus); - if (IRQStatus & 0x20) - break; - Timeout -= 1; - msleep(10); - } - if( (IRQStatus & 0x20) == 0 ) { - stat = -ETIMEDOUT; - } - } - } else { - write_reg(state, FLO_MAX, 0x00); - write_reg(state, CP_CURRENT,0x68); - } - Read(state, state->m_Regs); - - PowerOn(state); - StartCalibration(state); - FinishCalibration(state); - Standby(state); - return stat; -} - -static int PowerMeasurement(struct tda_state *state, u8 *pPowerLevel) -{ - int status = 0; - - do { - u8 IRQ = 0; - int Timeout = 70; // 700 ms - - state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ - CHK_ERROR(update_reg(state, IRQ_CLEAR)); - - state->m_Regs[MSM_1] = 0x80; // power measurement - state->m_Regs[MSM_2] = 0x01; // Start MSM - CHK_ERROR(update_regs(state, MSM_1,MSM_2)); - state->m_Regs[MSM_2] = 0x00; - - while(true) { - CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); - if( (IRQ & 0x80) != 0 ) - break; - Timeout -= 1; - if( Timeout == 0 ) - { - status = -1; - break; - } - msleep(10); - } - CHK_ERROR(status); - - CHK_ERROR(read_reg1(state, INPUT_POWER_LEVEL)); - *pPowerLevel = state->m_Regs[INPUT_POWER_LEVEL] & 0x7F; - - - if( *pPowerLevel > 110 ) *pPowerLevel = 110; - } while(0); - /* printk("PL %d\n", *pPowerLevel); */ - return status; -} - -static int SetFrequency(struct tda_state *state, u32 Frequency, enum HF_Standard Standard) -{ - int status = 0; - struct SStandardParams *StandardParams; - u32 f = Frequency / 1000; - u8 IRQ = 0; - int Timeout = 25; // 250 ms - u32 fRatio = Frequency / 16000000; - u32 fDelta = Frequency - fRatio * 16000000; - - if( Standard < HF_DVBT_6MHZ || Standard > HF_DVBC_8MHZ ) - return -EINVAL; - StandardParams = &m_StandardTable[Standard - HF_DVBT_6MHZ]; - - if( StandardParams->m_IFFrequency == 0 ) - return -EINVAL; - state->m_Standard = HF_None; - state->m_Frequency = 0; - - do { - // IF Level - state->m_Regs[IF_AGC] = (Standard >= HF_DVBC_6MHZ) ? state->m_IFLevelDVBC : state->m_IFLevelDVBT; - CHK_ERROR(update_reg(state, IF_AGC)); - - // --------------------------------------------------------------------------------- - // Standard setup - - state->m_Regs[IF_1] = StandardParams->m_IF_1; - CHK_ERROR(update_reg(state, IF_1)); - - state->m_Regs[IR_MIXER_2] = (state->m_Regs[IR_MIXER_2] & ~0x03) | StandardParams->m_IR_MIXER_2; - CHK_ERROR(update_reg(state, IR_MIXER_2)); - - state->m_Regs[AGC1_1] = (state->m_Regs[AGC1_1] & ~0x0F) | StandardParams->m_AGC1_1; - CHK_ERROR(update_reg(state, AGC1_1)); - - state->m_Regs[AGC2_1] = (state->m_Regs[AGC2_1] & ~0x0F) | StandardParams->m_AGC2_1; - CHK_ERROR(update_reg(state, AGC2_1)); - - state->m_Regs[RF_AGC_1] &= ~0xEF; - if( Frequency < 291000000 ) - state->m_Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_Low; - else - state->m_Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_High; - CHK_ERROR(update_reg(state, RF_AGC_1)); - - state->m_Regs[IR_MIXER_1] = (state->m_Regs[IR_MIXER_1] & ~0x0F) | StandardParams->m_IR_MIXER_1; - CHK_ERROR(update_reg(state, IR_MIXER_1)); - - state->m_Regs[AGC5_1] = (state->m_Regs[AGC5_1] & ~0x1F) | StandardParams->m_AGC5_1; - CHK_ERROR(update_reg(state, AGC5_1)); - - state->m_Regs[AGCK_1] = (state->m_Regs[AGCK_1] & ~0x0F) | StandardParams->m_AGCK_1; - CHK_ERROR(update_reg(state, AGCK_1)); - - state->m_Regs[PSM_1] = (state->m_Regs[PSM_1] & ~0x20) | StandardParams->m_PSM_1; - CHK_ERROR(update_reg(state, PSM_1)); - - state->m_Regs[IF_FREQUENCY_1] = ( StandardParams->m_IFFrequency / 50000 ); - CHK_ERROR(update_reg(state, IF_FREQUENCY_1)); - - if( state->m_isMaster && StandardParams->m_LTO_STO_immune ) - { - u8 tmp; - u8 RF_Filter_Gain; - - CHK_ERROR(read_reg(state, RF_AGC_GAIN_1,&tmp)); - RF_Filter_Gain = (tmp & 0x30) >> 4; - - state->m_Regs[RF_FILTER_1] = (state->m_Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); - CHK_ERROR(update_reg(state, RF_FILTER_1)); - - state->m_Regs[RF_FILTER_1] |= 0x10; // Force - CHK_ERROR(update_reg(state, RF_FILTER_1)); - - while( RF_Filter_Gain != 0 ) - { - RF_Filter_Gain -= 1; - state->m_Regs[RF_FILTER_1] = (state->m_Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); - CHK_ERROR(update_reg(state, RF_FILTER_1)); - msleep(10); - } - CHK_ERROR(status); - - state->m_Regs[RF_AGC_1] |= 0x08; - CHK_ERROR(update_reg(state, RF_AGC_1)); - } - - // --------------------------------------------------------------------------------- - - state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ - CHK_ERROR(update_reg(state, IRQ_CLEAR)); - - CHK_ERROR(PowerOn(state)); - - state->m_Regs[RF_FREQUENCY_1] = ((f >> 16) & 0xFF); - state->m_Regs[RF_FREQUENCY_2] = ((f >> 8) & 0xFF); - state->m_Regs[RF_FREQUENCY_3] = ((f ) & 0xFF); - CHK_ERROR(update_regs(state, RF_FREQUENCY_1,RF_FREQUENCY_3)); - - state->m_Regs[MSM_1] = 0x41; // Tune - state->m_Regs[MSM_2] = 0x01; // Start MSM - CHK_ERROR(update_regs(state, MSM_1, MSM_2)); - state->m_Regs[MSM_2] = 0x00; - - while(true) - { - CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); - if( (IRQ & 0x80) != 0 ) break; - Timeout -= 1; - if (Timeout == 0) { - status = -1; - break; - } - msleep(10); - } - CHK_ERROR(status); - - // --------------------------------------------------------------------------------- - - if( state->m_isMaster && StandardParams->m_LTO_STO_immune ) - { - state->m_Regs[RF_AGC_1] &= ~0x08; - CHK_ERROR(update_reg(state, RF_AGC_1)); - - msleep(50); - - state->m_Regs[RF_FILTER_1] &= ~0x10; // remove force - CHK_ERROR(update_reg(state, RF_FILTER_1)); - } - - // --------------------------------------------------------------------------------- - // Spur reduction - - if( Frequency < 72000000 ) - { - state->m_Regs[REFERENCE] |= 0x40; // Set digital clock - } - else if( Frequency < 104000000 ) - { - state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock - } - else if( Frequency < 120000000 ) - { - state->m_Regs[REFERENCE] |= 0x40; // Set digital clock - } - else - { - if( fDelta <= 8000000 ) - { - if( fRatio & 1 ) state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock - else state->m_Regs[REFERENCE] |= 0x40; // Set digital clock - } - else - { - if( fRatio & 1 ) state->m_Regs[REFERENCE] |= 0x40; // Set digital clock - else state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock - } - - } - CHK_ERROR(update_reg(state, REFERENCE)); - - if( StandardParams->m_AGC1_Freeze && state->m_bEnableFreeze ) - { - u8 tmp; - int AGC1GainMin = 0; - int nSteps = 10; - int Step = 0; - - CHK_ERROR(read_reg(state, AGC1_2,&tmp)); - - if( (tmp & 0x80) == 0 ) - { - state->m_Regs[AGC1_2] |= 0x80; // Loop off - CHK_ERROR(update_reg(state, AGC1_2)); - state->m_Regs[AGC1_2] |= 0x10 ; // Force gain - CHK_ERROR(update_reg(state, AGC1_2)); - } - // Adapt - if( state->m_Regs[AGC1_1] & 0x40 ) // AGC1_6_15dB set - { - AGC1GainMin = 6; - nSteps = 4; - } - while( Step < nSteps ) - { - int Down = 0; - int Up = 0, i; - u8 AGC1_Gain; - - Step = Step + 1; - - for (i = 0; i < 40; i += 1) { - CHK_ERROR(read_reg(state, AGC_DET_OUT, &tmp)); - Up += (tmp & 0x02) ? 1 : -4; - Down += (tmp & 0x01) ? 14 : -1; - msleep(1); - } - CHK_ERROR(status); - AGC1_Gain = (state->m_Regs[AGC1_2] & 0x0F); - if( Up >= 15 && AGC1_Gain != 9 ) - { - state->m_Regs[AGC1_2] = ( state->m_Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain + 1); - CHK_ERROR(update_reg(state, AGC1_2)); - } - else if ( Down >= 10 && AGC1_Gain != AGC1GainMin ) - { - state->m_Regs[AGC1_2] = ( state->m_Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain - 1); - CHK_ERROR(update_reg(state, AGC1_2)); - } - else - { - Step = nSteps; - } - } - } - else - { - state->m_Regs[AGC1_2] &= ~0x10 ; // unforce gain - CHK_ERROR(update_reg(state, AGC1_2)); - state->m_Regs[AGC1_2] &= ~0x80; // Loop on - CHK_ERROR(update_reg(state, AGC1_2)); - } - - state->m_Standard = Standard; - state->m_Frequency = Frequency; - - if( state->m_bPowerMeasurement ) - PowerMeasurement(state, &state->m_LastPowerLevel); - } while(0); - - return status; -} - -static int sleep(struct dvb_frontend* fe) -{ - struct tda_state *state = fe->tuner_priv; - - Standby(state); - return 0; -} - -static int init(struct dvb_frontend* fe) -{ - //struct tda_state *state = fe->tuner_priv; - return 0; -} - -static int release(struct dvb_frontend* fe) -{ - kfree(fe->tuner_priv); - fe->tuner_priv = NULL; - return 0; -} - -#ifndef USE_API3 -static int set_params(struct dvb_frontend *fe) -{ - struct tda_state *state = fe->tuner_priv; - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - int status = 0; - int Standard; - u32 bw; - - bw = (p->bandwidth_hz + 999999) / 1000000; - state->m_Frequency = p->frequency; - if (p->delivery_system == SYS_DVBT || - p->delivery_system == SYS_DVBT2 || - p->delivery_system == SYS_ISDBT || - p->delivery_system == SYS_DVBC2) { - switch (bw) { - case 6: - Standard = HF_DVBT_6MHZ; - break; - case 7: - Standard = HF_DVBT_7MHZ; - break; - default: - case 8: - Standard = HF_DVBT_8MHZ; - break; - } - } else if (p->delivery_system == SYS_DVBC_ANNEX_A) { - switch (bw) { - case 6: - Standard = HF_DVBC_6MHZ; - break; - case 7: - Standard = HF_DVBC_7MHZ; - break; - default: - case 8: - Standard = HF_DVBC_8MHZ; - break; - } - } else - return -EINVAL; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - SetFrequency(state, state->m_Frequency, Standard); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return status; -} -#else -static int set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - struct tda_state *state = fe->tuner_priv; - int status = 0; - int Standard; - - state->m_Frequency = params->frequency; - - if (fe->ops.info.type == FE_OFDM) - switch (params->u.ofdm.bandwidth) { - case BANDWIDTH_6_MHZ: - Standard = HF_DVBT_6MHZ; - break; - case BANDWIDTH_7_MHZ: - Standard = HF_DVBT_7MHZ; - break; - default: - case BANDWIDTH_8_MHZ: - Standard = HF_DVBT_8MHZ; - break; - } - else if (fe->ops.info.type == FE_QAM) { - Standard = HF_DVBC_8MHZ; - } else - return -EINVAL; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - SetFrequency(state, state->m_Frequency, Standard); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return status; -} -#endif - -static int get_frequency(struct dvb_frontend *fe, u32 *frequency) -{ - struct tda_state *state = fe->tuner_priv; - - *frequency = state->IF; - return 0; -} - -static int get_rf_strength(struct dvb_frontend *fe, u16 *st) -{ - struct tda_state *state = fe->tuner_priv; - - *st = state->m_LastPowerLevel; - return 0; -} - -static int get_if(struct dvb_frontend *fe, u32 *frequency) -{ - struct tda_state *state = fe->tuner_priv; - - state->IF = 0; - if (state->m_Standard < HF_DVBT_6MHZ || - state->m_Standard > HF_DVBC_8MHZ) - return 0; - state->IF = m_StandardTable[state->m_Standard - HF_DVBT_6MHZ].m_IFFrequency; - *frequency = state->IF; - return 0; -} - -static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -{ - //struct tda_state *state = fe->tuner_priv; - //*bandwidth = priv->bandwidth; - return 0; -} - - -static struct dvb_tuner_ops tuner_ops = { - .info = { - .name = "NXP TDA18212", - .frequency_min = 47125000, - .frequency_max = 865000000, - .frequency_step = 62500 - }, - .init = init, - .sleep = sleep, - .set_params = set_params, - .release = release, - .get_frequency = get_frequency, - .get_if_frequency = get_if, - .get_bandwidth = get_bandwidth, - .get_rf_strength = get_rf_strength, -}; - -struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 adr) -{ - struct tda_state *state; - int stat; - - state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); - if (!state) - return NULL; - state->adr = adr; - state->i2c = i2c; - memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); - init_state(state); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - stat = attach_init(state); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - if (stat < 0) { - kfree(state); - return 0; - } - fe->tuner_priv = state; - return fe; -} - -EXPORT_SYMBOL_GPL(tda18212dd_attach); -MODULE_DESCRIPTION("TDA18212 driver"); -MODULE_AUTHOR("DD"); -MODULE_LICENSE("GPL"); - -/* - * Local variables: - * c-basic-offset: 8 - * End: - */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18212dd.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -#ifndef _TDA18212DD_H_ -#define _TDA18212DD_H_ -struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 adr); -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.c 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,1301 +0,0 @@ -/* - * tda18271c2dd: Driver for the TDA18271C2 tuner - * - * Copyright (C) 2010 Digital Devices GmbH - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 only, as published by the Free Software Foundation. - * - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "dvb_frontend.h" - -struct SStandardParam { - s32 m_IFFrequency; - u32 m_BandWidth; - u8 m_EP3_4_0; - u8 m_EB22; -}; - -struct SMap { - u32 m_Frequency; - u8 m_Param; -}; - -struct SMapI { - u32 m_Frequency; - s32 m_Param; -}; - -struct SMap2 { - u32 m_Frequency; - u8 m_Param1; - u8 m_Param2; -}; - -struct SRFBandMap { - u32 m_RF_max; - u32 m_RF1_Default; - u32 m_RF2_Default; - u32 m_RF3_Default; -}; - -enum ERegister { - ID = 0, - TM, - PL, - EP1, EP2, EP3, EP4, EP5, - CPD, CD1, CD2, CD3, - MPD, MD1, MD2, MD3, - EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10, - EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20, - EB21, EB22, EB23, - NUM_REGS -}; - -struct tda_state { - struct i2c_adapter *i2c; - u8 adr; - - u32 m_Frequency; - u32 IF; - - u8 m_IFLevelAnalog; - u8 m_IFLevelDigital; - u8 m_IFLevelDVBC; - u8 m_IFLevelDVBT; - - u8 m_EP4; - u8 m_EP3_Standby; - - bool m_bMaster; - - s32 m_SettlingTime; - - u8 m_Regs[NUM_REGS]; - - /* Tracking filter settings for band 0..6 */ - u32 m_RF1[7]; - s32 m_RF_A1[7]; - s32 m_RF_B1[7]; - u32 m_RF2[7]; - s32 m_RF_A2[7]; - s32 m_RF_B2[7]; - u32 m_RF3[7]; - - u8 m_TMValue_RFCal; /* Calibration temperatur */ - - bool m_bFMInput; /* true to use Pin 8 for FM Radio */ - -}; - -static int PowerScan(struct tda_state *state, - u8 RFBand, u32 RF_in, - u32 *pRF_Out, bool *pbcal); - -static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) -{ - struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, - .buf = data, .len = len} }; - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -} - -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -{ - struct i2c_msg msg = {.addr = adr, .flags = 0, - .buf = data, .len = len}; - - if (i2c_transfer(adap, &msg, 1) != 1) { - printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr); - return -1; - } - return 0; -} - -static int WriteRegs(struct tda_state *state, - u8 SubAddr, u8 *Regs, u16 nRegs) -{ - u8 data[nRegs+1]; - - data[0] = SubAddr; - memcpy(data + 1, Regs, nRegs); - return i2c_write(state->i2c, state->adr, data, nRegs+1); -} - -static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) -{ - u8 msg[2] = {SubAddr, Reg}; - - return i2c_write(state->i2c, state->adr, msg, 2); -} - -static int Read(struct tda_state *state, u8 * Regs) -{ - return i2c_readn(state->i2c, state->adr, Regs, 16); -} - -static int ReadExtented(struct tda_state *state, u8 * Regs) -{ - return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS); -} - -static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo) -{ - return WriteRegs(state, RegFrom, - &state->m_Regs[RegFrom], RegTo-RegFrom+1); -} -static int UpdateReg(struct tda_state *state, u8 Reg) -{ - return WriteReg(state, Reg, state->m_Regs[Reg]); -} - -#include "tda18271c2dd_maps.h" - -static void reset(struct tda_state *state) -{ - u32 ulIFLevelAnalog = 0; - u32 ulIFLevelDigital = 2; - u32 ulIFLevelDVBC = 7; - u32 ulIFLevelDVBT = 6; - u32 ulXTOut = 0; - u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */ - u32 ulSlave = 0; - u32 ulFMInput = 0; - u32 ulSettlingTime = 100; - - state->m_Frequency = 0; - state->m_SettlingTime = 100; - state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2; - state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2; - state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2; - state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2; - - state->m_EP4 = 0x20; - if (ulXTOut != 0) - state->m_EP4 |= 0x40; - - state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F; - state->m_bMaster = (ulSlave == 0); - - state->m_SettlingTime = ulSettlingTime; - - state->m_bFMInput = (ulFMInput == 2); -} - -static bool SearchMap1(struct SMap Map[], - u32 Frequency, u8 *pParam) -{ - int i = 0; - - while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency)) - i += 1; - if (Map[i].m_Frequency == 0) - return false; - *pParam = Map[i].m_Param; - return true; -} - -static bool SearchMap2(struct SMapI Map[], - u32 Frequency, s32 *pParam) -{ - int i = 0; - - while ((Map[i].m_Frequency != 0) && - (Frequency > Map[i].m_Frequency)) - i += 1; - if (Map[i].m_Frequency == 0) - return false; - *pParam = Map[i].m_Param; - return true; -} - -static bool SearchMap3(struct SMap2 Map[], u32 Frequency, - u8 *pParam1, u8 *pParam2) -{ - int i = 0; - - while ((Map[i].m_Frequency != 0) && - (Frequency > Map[i].m_Frequency)) - i += 1; - if (Map[i].m_Frequency == 0) - return false; - *pParam1 = Map[i].m_Param1; - *pParam2 = Map[i].m_Param2; - return true; -} - -static bool SearchMap4(struct SRFBandMap Map[], - u32 Frequency, u8 *pRFBand) -{ - int i = 0; - - while (i < 7 && (Frequency > Map[i].m_RF_max)) - i += 1; - if (i == 7) - return false; - *pRFBand = i; - return true; -} - -static int ThermometerRead(struct tda_state *state, u8 *pTM_Value) -{ - int status = 0; - - do { - u8 Regs[16]; - state->m_Regs[TM] |= 0x10; - status = UpdateReg(state, TM); - if (status < 0) - break; - status = Read(state, Regs); - if (status < 0) - break; - if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) || - ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) { - state->m_Regs[TM] ^= 0x20; - status = UpdateReg(state, TM); - if (status < 0) - break; - msleep(10); - status = Read(state, Regs); - if (status < 0) - break; - } - *pTM_Value = (Regs[TM] & 0x20) - ? m_Thermometer_Map_2[Regs[TM] & 0x0F] - : m_Thermometer_Map_1[Regs[TM] & 0x0F] ; - state->m_Regs[TM] &= ~0x10; /* Thermometer off */ - status = UpdateReg(state, TM); - if (status < 0) - break; - state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */ - status = UpdateReg(state, EP4); - if (status < 0) - break; - } while (0); - - return status; -} - -static int StandBy(struct tda_state *state) -{ - int status = 0; - do { - state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */ - status = UpdateReg(state, EB12); - if (status < 0) - break; - state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */ - status = UpdateReg(state, EB18); - if (status < 0) - break; - state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */ - state->m_Regs[EP3] = state->m_EP3_Standby; - status = UpdateReg(state, EP3); - if (status < 0) - break; - state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */ - status = UpdateRegs(state, EB21, EB23); - if (status < 0) - break; - } while (0); - return status; -} - -static int CalcMainPLL(struct tda_state *state, u32 freq) -{ - - u8 PostDiv; - u8 Div; - u64 OscFreq; - u32 MainDiv; - - if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) - return -EINVAL; - - OscFreq = (u64) freq * (u64) Div; - OscFreq *= (u64) 16384; - do_div(OscFreq, (u64)16000000); - MainDiv = OscFreq; - - state->m_Regs[MPD] = PostDiv & 0x77; - state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F); - state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF); - state->m_Regs[MD3] = (MainDiv & 0xFF); - - return UpdateRegs(state, MPD, MD3); -} - -static int CalcCalPLL(struct tda_state *state, u32 freq) -{ - u8 PostDiv; - u8 Div; - u64 OscFreq; - u32 CalDiv; - - if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div)) - return -EINVAL; - - OscFreq = (u64)freq * (u64)Div; - /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */ - OscFreq *= (u64)16384; - do_div(OscFreq, (u64)16000000); - CalDiv = OscFreq; - - state->m_Regs[CPD] = PostDiv; - state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF); - state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF); - state->m_Regs[CD3] = (CalDiv & 0xFF); - - return UpdateRegs(state, CPD, CD3); -} - -static int CalibrateRF(struct tda_state *state, - u8 RFBand, u32 freq, s32 *pCprog) -{ - int status = 0; - u8 Regs[NUM_REGS]; - do { - u8 BP_Filter = 0; - u8 GainTaper = 0; - u8 RFC_K = 0; - u8 RFC_M = 0; - - state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */ - status = UpdateReg(state, EP4); - if (status < 0) - break; - state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */ - status = UpdateReg(state, EB18); - if (status < 0) - break; - - /* Switching off LT (as datasheet says) causes calibration on C1 to fail */ - /* (Readout of Cprog is allways 255) */ - if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */ - state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */ - - if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) && - SearchMap1(m_GainTaper_Map, freq, &GainTaper) && - SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M))) - return -EINVAL; - - state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter; - state->m_Regs[EP2] = (RFBand << 5) | GainTaper; - - state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2); - - status = UpdateRegs(state, EP1, EP3); - if (status < 0) - break; - status = UpdateReg(state, EB13); - if (status < 0) - break; - - state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */ - status = UpdateReg(state, EB4); - if (status < 0) - break; - - state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */ - status = UpdateReg(state, EB7); - if (status < 0) - break; - - state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */ - status = UpdateReg(state, EB14); - if (status < 0) - break; - - state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */ - status = UpdateReg(state, EB20); - if (status < 0) - break; - - state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */ - status = UpdateRegs(state, EP4, EP5); - if (status < 0) - break; - - status = CalcCalPLL(state, freq); - if (status < 0) - break; - status = CalcMainPLL(state, freq + 1000000); - if (status < 0) - break; - - msleep(5); - status = UpdateReg(state, EP2); - if (status < 0) - break; - status = UpdateReg(state, EP1); - if (status < 0) - break; - status = UpdateReg(state, EP2); - if (status < 0) - break; - status = UpdateReg(state, EP1); - if (status < 0) - break; - - state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */ - status = UpdateReg(state, EB4); - if (status < 0) - break; - - state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */ - status = UpdateReg(state, EB7); - if (status < 0) - break; - msleep(10); - - state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */ - status = UpdateReg(state, EB20); - if (status < 0) - break; - msleep(60); - - state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */ - state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */ - state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */ - status = UpdateReg(state, EB18); - if (status < 0) - break; - status = UpdateRegs(state, EP3, EP4); - if (status < 0) - break; - status = UpdateReg(state, EP1); - if (status < 0) - break; - - status = ReadExtented(state, Regs); - if (status < 0) - break; - - *pCprog = Regs[EB14]; - - } while (0); - return status; -} - -static int RFTrackingFiltersInit(struct tda_state *state, - u8 RFBand) -{ - int status = 0; - - u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default; - u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default; - u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default; - bool bcal = false; - - s32 Cprog_cal1 = 0; - s32 Cprog_table1 = 0; - s32 Cprog_cal2 = 0; - s32 Cprog_table2 = 0; - s32 Cprog_cal3 = 0; - s32 Cprog_table3 = 0; - - state->m_RF_A1[RFBand] = 0; - state->m_RF_B1[RFBand] = 0; - state->m_RF_A2[RFBand] = 0; - state->m_RF_B2[RFBand] = 0; - - do { - status = PowerScan(state, RFBand, RF1, &RF1, &bcal); - if (status < 0) - break; - if (bcal) { - status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1); - if (status < 0) - break; - } - SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1); - if (!bcal) - Cprog_cal1 = Cprog_table1; - state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1; - /* state->m_RF_A1[RF_Band] = ???? */ - - if (RF2 == 0) - break; - - status = PowerScan(state, RFBand, RF2, &RF2, &bcal); - if (status < 0) - break; - if (bcal) { - status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2); - if (status < 0) - break; - } - SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2); - if (!bcal) - Cprog_cal2 = Cprog_table2; - - state->m_RF_A1[RFBand] = - (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) / - ((s32)(RF2) - (s32)(RF1)); - - if (RF3 == 0) - break; - - status = PowerScan(state, RFBand, RF3, &RF3, &bcal); - if (status < 0) - break; - if (bcal) { - status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3); - if (status < 0) - break; - } - SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3); - if (!bcal) - Cprog_cal3 = Cprog_table3; - state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2)); - state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2; - - } while (0); - - state->m_RF1[RFBand] = RF1; - state->m_RF2[RFBand] = RF2; - state->m_RF3[RFBand] = RF3; - -#if 0 - printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__, - RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2, - state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3); -#endif - - return status; -} - -static int PowerScan(struct tda_state *state, - u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal) -{ - int status = 0; - do { - u8 Gain_Taper = 0; - s32 RFC_Cprog = 0; - u8 CID_Target = 0; - u8 CountLimit = 0; - u32 freq_MainPLL; - u8 Regs[NUM_REGS]; - u8 CID_Gain; - s32 Count = 0; - int sign = 1; - bool wait = false; - - if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) && - SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) && - SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) { - - printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__); - return -EINVAL; - } - - state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper; - state->m_Regs[EB14] = (RFC_Cprog); - status = UpdateReg(state, EP2); - if (status < 0) - break; - status = UpdateReg(state, EB14); - if (status < 0) - break; - - freq_MainPLL = RF_in + 1000000; - status = CalcMainPLL(state, freq_MainPLL); - if (status < 0) - break; - msleep(5); - state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */ - status = UpdateReg(state, EP4); - if (status < 0) - break; - status = UpdateReg(state, EP2); /* Launch power measurement */ - if (status < 0) - break; - status = ReadExtented(state, Regs); - if (status < 0) - break; - CID_Gain = Regs[EB10] & 0x3F; - state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */ - - *pRF_Out = RF_in; - - while (CID_Gain < CID_Target) { - freq_MainPLL = RF_in + sign * Count + 1000000; - status = CalcMainPLL(state, freq_MainPLL); - if (status < 0) - break; - msleep(wait ? 5 : 1); - wait = false; - status = UpdateReg(state, EP2); /* Launch power measurement */ - if (status < 0) - break; - status = ReadExtented(state, Regs); - if (status < 0) - break; - CID_Gain = Regs[EB10] & 0x3F; - Count += 200000; - - if (Count < CountLimit * 100000) - continue; - if (sign < 0) - break; - - sign = -sign; - Count = 200000; - wait = true; - } - status = status; - if (status < 0) - break; - if (CID_Gain >= CID_Target) { - *pbcal = true; - *pRF_Out = freq_MainPLL - 1000000; - } else - *pbcal = false; - } while (0); - - return status; -} - -static int PowerScanInit(struct tda_state *state) -{ - int status = 0; - do { - state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12; - state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */ - status = UpdateRegs(state, EP3, EP4); - if (status < 0) - break; - state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */ - status = UpdateReg(state, EB18); - if (status < 0) - break; - state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */ - state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ - status = UpdateRegs(state, EB21, EB23); - if (status < 0) - break; - } while (0); - return status; -} - -static int CalcRFFilterCurve(struct tda_state *state) -{ - int status = 0; - do { - msleep(200); /* Temperature stabilisation */ - status = PowerScanInit(state); - if (status < 0) - break; - status = RFTrackingFiltersInit(state, 0); - if (status < 0) - break; - status = RFTrackingFiltersInit(state, 1); - if (status < 0) - break; - status = RFTrackingFiltersInit(state, 2); - if (status < 0) - break; - status = RFTrackingFiltersInit(state, 3); - if (status < 0) - break; - status = RFTrackingFiltersInit(state, 4); - if (status < 0) - break; - status = RFTrackingFiltersInit(state, 5); - if (status < 0) - break; - status = RFTrackingFiltersInit(state, 6); - if (status < 0) - break; - status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */ - if (status < 0) - break; - } while (0); - - return status; -} - -static int FixedContentsI2CUpdate(struct tda_state *state) -{ - static u8 InitRegs[] = { - 0x08, 0x80, 0xC6, - 0xDF, 0x16, 0x60, 0x80, - 0x80, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0xFC, 0x01, 0x84, 0x41, - 0x01, 0x84, 0x40, 0x07, - 0x00, 0x00, 0x96, 0x3F, - 0xC1, 0x00, 0x8F, 0x00, - 0x00, 0x8C, 0x00, 0x20, - 0xB3, 0x48, 0xB0, - }; - int status = 0; - memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1); - do { - status = UpdateRegs(state, TM, EB23); - if (status < 0) - break; - - /* AGC1 gain setup */ - state->m_Regs[EB17] = 0x00; - status = UpdateReg(state, EB17); - if (status < 0) - break; - state->m_Regs[EB17] = 0x03; - status = UpdateReg(state, EB17); - if (status < 0) - break; - state->m_Regs[EB17] = 0x43; - status = UpdateReg(state, EB17); - if (status < 0) - break; - state->m_Regs[EB17] = 0x4C; - status = UpdateReg(state, EB17); - if (status < 0) - break; - - /* IRC Cal Low band */ - state->m_Regs[EP3] = 0x1F; - state->m_Regs[EP4] = 0x66; - state->m_Regs[EP5] = 0x81; - state->m_Regs[CPD] = 0xCC; - state->m_Regs[CD1] = 0x6C; - state->m_Regs[CD2] = 0x00; - state->m_Regs[CD3] = 0x00; - state->m_Regs[MPD] = 0xC5; - state->m_Regs[MD1] = 0x77; - state->m_Regs[MD2] = 0x08; - state->m_Regs[MD3] = 0x00; - status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */ - if (status < 0) - break; - -#if 0 - state->m_Regs[EB4] = 0x61; /* missing in sw */ - status = UpdateReg(state, EB4); - if (status < 0) - break; - msleep(1); - state->m_Regs[EB4] = 0x41; - status = UpdateReg(state, EB4); - if (status < 0) - break; -#endif - - msleep(5); - status = UpdateReg(state, EP1); - if (status < 0) - break; - msleep(5); - - state->m_Regs[EP5] = 0x85; - state->m_Regs[CPD] = 0xCB; - state->m_Regs[CD1] = 0x66; - state->m_Regs[CD2] = 0x70; - status = UpdateRegs(state, EP3, CD3); - if (status < 0) - break; - msleep(5); - status = UpdateReg(state, EP2); - if (status < 0) - break; - msleep(30); - - /* IRC Cal mid band */ - state->m_Regs[EP5] = 0x82; - state->m_Regs[CPD] = 0xA8; - state->m_Regs[CD2] = 0x00; - state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */ - state->m_Regs[MD1] = 0x73; - state->m_Regs[MD2] = 0x1A; - status = UpdateRegs(state, EP3, MD3); - if (status < 0) - break; - - msleep(5); - status = UpdateReg(state, EP1); - if (status < 0) - break; - msleep(5); - - state->m_Regs[EP5] = 0x86; - state->m_Regs[CPD] = 0xA8; - state->m_Regs[CD1] = 0x66; - state->m_Regs[CD2] = 0xA0; - status = UpdateRegs(state, EP3, CD3); - if (status < 0) - break; - msleep(5); - status = UpdateReg(state, EP2); - if (status < 0) - break; - msleep(30); - - /* IRC Cal high band */ - state->m_Regs[EP5] = 0x83; - state->m_Regs[CPD] = 0x98; - state->m_Regs[CD1] = 0x65; - state->m_Regs[CD2] = 0x00; - state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */ - state->m_Regs[MD1] = 0x71; - state->m_Regs[MD2] = 0xCD; - status = UpdateRegs(state, EP3, MD3); - if (status < 0) - break; - msleep(5); - status = UpdateReg(state, EP1); - if (status < 0) - break; - msleep(5); - state->m_Regs[EP5] = 0x87; - state->m_Regs[CD1] = 0x65; - state->m_Regs[CD2] = 0x50; - status = UpdateRegs(state, EP3, CD3); - if (status < 0) - break; - msleep(5); - status = UpdateReg(state, EP2); - if (status < 0) - break; - msleep(30); - - /* Back to normal */ - state->m_Regs[EP4] = 0x64; - status = UpdateReg(state, EP4); - if (status < 0) - break; - status = UpdateReg(state, EP1); - if (status < 0) - break; - - } while (0); - return status; -} - -static int InitCal(struct tda_state *state) -{ - int status = 0; - - do { - status = FixedContentsI2CUpdate(state); - if (status < 0) - break; - status = CalcRFFilterCurve(state); - if (status < 0) - break; - status = StandBy(state); - if (status < 0) - break; - /* m_bInitDone = true; */ - } while (0); - return status; -}; - -static int RFTrackingFiltersCorrection(struct tda_state *state, - u32 Frequency) -{ - int status = 0; - s32 Cprog_table; - u8 RFBand; - u8 dCoverdT; - - if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) || - !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) || - !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT)) - - return -EINVAL; - - do { - u8 TMValue_Current; - u32 RF1 = state->m_RF1[RFBand]; - u32 RF2 = state->m_RF1[RFBand]; - u32 RF3 = state->m_RF1[RFBand]; - s32 RF_A1 = state->m_RF_A1[RFBand]; - s32 RF_B1 = state->m_RF_B1[RFBand]; - s32 RF_A2 = state->m_RF_A2[RFBand]; - s32 RF_B2 = state->m_RF_B2[RFBand]; - s32 Capprox = 0; - int TComp; - - state->m_Regs[EP3] &= ~0xE0; /* Power up */ - status = UpdateReg(state, EP3); - if (status < 0) - break; - - status = ThermometerRead(state, &TMValue_Current); - if (status < 0) - break; - - if (RF3 == 0 || Frequency < RF2) - Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table; - else - Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table; - - TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000; - - Capprox += TComp; - - if (Capprox < 0) - Capprox = 0; - else if (Capprox > 255) - Capprox = 255; - - - /* TODO Temperature compensation. There is defenitely a scale factor */ - /* missing in the datasheet, so leave it out for now. */ - state->m_Regs[EB14] = Capprox; - - status = UpdateReg(state, EB14); - if (status < 0) - break; - - } while (0); - return status; -} - -static int ChannelConfiguration(struct tda_state *state, - u32 Frequency, int Standard) -{ - - s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency; - int status = 0; - - u8 BP_Filter = 0; - u8 RF_Band = 0; - u8 GainTaper = 0; - u8 IR_Meas = 0; - - state->IF = IntermediateFrequency; - /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ - /* get values from tables */ - - if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) && - SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) && - SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) && - SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) { - - printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__); - return -EINVAL; - } - - do { - state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0; - state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */ - - /* m_EP4 default for XToutOn, CAL_Mode (0) */ - state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog); - /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */ - if (Standard <= HF_AnalogMax) - state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog; - else if (Standard <= HF_ATSC) - state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT; - else if (Standard <= HF_DVBC) - state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC; - else - state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; - - if ((Standard == HF_FM_Radio) && state->m_bFMInput) - state->m_Regs[EP4] |= 80; - - state->m_Regs[MPD] &= ~0x80; - if (Standard > HF_AnalogMax) - state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */ - - state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22; - - /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */ - if (Standard == HF_FM_Radio) - state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ - else - state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */ - - status = UpdateRegs(state, EB22, EB23); - if (status < 0) - break; - - state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */ - state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas; - state->m_Regs[EP2] = (RF_Band << 5) | GainTaper; - - state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) | - (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */ - /* AGC1_always_master = 0 */ - /* AGC_firstn = 0 */ - status = UpdateReg(state, EB1); - if (status < 0) - break; - - if (state->m_bMaster) { - status = CalcMainPLL(state, Frequency + IntermediateFrequency); - if (status < 0) - break; - status = UpdateRegs(state, TM, EP5); - if (status < 0) - break; - state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */ - status = UpdateReg(state, EB4); - if (status < 0) - break; - msleep(1); - state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ - status = UpdateReg(state, EB4); - if (status < 0) - break; - } else { - u8 PostDiv = 0; - u8 Div; - status = CalcCalPLL(state, Frequency + IntermediateFrequency); - if (status < 0) - break; - - SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div); - state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77); - status = UpdateReg(state, MPD); - if (status < 0) - break; - status = UpdateRegs(state, TM, EP5); - if (status < 0) - break; - - state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */ - status = UpdateReg(state, EB7); - if (status < 0) - break; - msleep(1); - state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */ - status = UpdateReg(state, EB7); - if (status < 0) - break; - } - msleep(20); - if (Standard != HF_FM_Radio) - state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */ - status = UpdateReg(state, EP3); - if (status < 0) - break; - - } while (0); - return status; -} - -static int sleep(struct dvb_frontend *fe) -{ - struct tda_state *state = fe->tuner_priv; - - StandBy(state); - return 0; -} - -static int init(struct dvb_frontend *fe) -{ - return 0; -} - -static int release(struct dvb_frontend *fe) -{ - kfree(fe->tuner_priv); - fe->tuner_priv = NULL; - return 0; -} - -/* - * As defined on EN 300 429 Annex A and on ITU-T J.83 annex A, the DVB-C - * roll-off factor is 0.15. - * According with the specs, the amount of the needed bandwith is given by: - * Bw = Symbol_rate * (1 + 0.15) - * As such, the maximum symbol rate supported by 6 MHz is - * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds - *NOTE: For ITU-T J.83 Annex C, the roll-off factor is 0.13. So: - * max_symbol_rate = 6 MHz / 1.13 = 5309735 Baud - * That means that an adjustment is needed for Japan, - * but, as currently DRX-K is hardcoded to Annex A, let's stick - * with 0.15 roll-off factor. - */ -#define MAX_SYMBOL_RATE_6MHz 5217391 - -#ifndef USE_API3 -static int set_params(struct dvb_frontend *fe) -#else -static int set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -#endif -{ - struct tda_state *state = fe->tuner_priv; - int status = 0; - int Standard; -#ifndef USE_API3 - u32 bw = fe->dtv_property_cache.bandwidth_hz; - u32 delsys = fe->dtv_property_cache.delivery_system; - - state->m_Frequency = fe->dtv_property_cache.frequency; - - switch (delsys) { - case SYS_DVBT: - case SYS_DVBT2: - switch (bw) { - case 6000000: - Standard = HF_DVBT_6MHZ; - break; - case 7000000: - Standard = HF_DVBT_7MHZ; - break; - case 8000000: - Standard = HF_DVBT_8MHZ; - break; - default: - return -EINVAL; - } - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: - if (bw <= 6000000) - Standard = HF_DVBC_6MHZ; - else if (bw <= 7000000) - Standard = HF_DVBC_7MHZ; - else - Standard = HF_DVBC_8MHZ; - break; - default: - return -EINVAL; - } - do { - status = RFTrackingFiltersCorrection(state, state->m_Frequency); - if (status < 0) - break; - status = ChannelConfiguration(state, state->m_Frequency, - Standard); - if (status < 0) - break; - - msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ - } while (0); -#else - state->m_Frequency = params->frequency; - - if (fe->ops.info.type == FE_OFDM) - switch (params->u.ofdm.bandwidth) { - case BANDWIDTH_6_MHZ: - Standard = HF_DVBT_6MHZ; - break; - case BANDWIDTH_7_MHZ: - Standard = HF_DVBT_7MHZ; - break; - default: - case BANDWIDTH_8_MHZ: - Standard = HF_DVBT_8MHZ; - break; - } - else if (fe->ops.info.type == FE_QAM) { - if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) - Standard = HF_DVBC_6MHZ; - else - Standard = HF_DVBC_8MHZ; - } else - return -EINVAL; - do { - status = RFTrackingFiltersCorrection(state, params->frequency); - if (status < 0) - break; - status = ChannelConfiguration(state, params->frequency, Standard); - if (status < 0) - break; - - msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ - } while (0); -#endif - return status; -} - -#if 0 -static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc) -{ - if (IFAgc < 500) { - /* Scale this from 0 to 50000 */ - *pSignalStrength = IFAgc * 100; - } else { - /* Scale range 500-1500 to 50000-80000 */ - *pSignalStrength = 50000 + (IFAgc - 500) * 30; - } - - return 0; -} -#endif - -static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency) -{ - struct tda_state *state = fe->tuner_priv; - - *frequency = state->IF; - return 0; -} - -static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -{ - /* struct tda_state *state = fe->tuner_priv; */ - /* *bandwidth = priv->bandwidth; */ - return 0; -} - - -static struct dvb_tuner_ops tuner_ops = { - .info = { - .name = "NXP TDA18271C2D", - .frequency_min = 47125000, - .frequency_max = 865000000, - .frequency_step = 62500 - }, - .init = init, - .sleep = sleep, - .set_params = set_params, - .release = release, - .get_if_frequency = get_if_frequency, - .get_bandwidth = get_bandwidth, -}; - -struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 adr) -{ - struct tda_state *state; - - state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); - if (!state) - return NULL; - - fe->tuner_priv = state; - state->adr = adr; - state->i2c = i2c; - memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); - reset(state); - InitCal(state); - - return fe; -} -EXPORT_SYMBOL_GPL(tda18271c2dd_attach); - -MODULE_DESCRIPTION("TDA18271C2 driver"); -MODULE_AUTHOR("DD"); -MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,16 +0,0 @@ -#ifndef _TDA18271C2DD_H_ -#define _TDA18271C2DD_H_ -#if defined(CONFIG_DVB_TDA18271C2DD) || (defined(CONFIG_DVB_TDA18271C2DD_MODULE) \ - && defined(MODULE)) -struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 adr); -#else -static inline struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 adr) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd_maps.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd_maps.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd_maps.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/frontends/tda18271c2dd_maps.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,814 +0,0 @@ -enum HF_S { - HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, - HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, - HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, - HF_DVBC_8MHZ, HF_DVBC -}; - -struct SStandardParam m_StandardTable[] = { - { 0, 0, 0x00, 0x00 }, /* HF_None */ - { 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */ - { 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */ - { 7100000, 8000000, 0x1E, 0x2C }, /* HF_G, */ - { 7250000, 8000000, 0x1E, 0x2C }, /* HF_I, */ - { 6900000, 8000000, 0x1E, 0x2C }, /* HF_L, */ - { 1250000, 8000000, 0x1E, 0x2C }, /* HF_L1, */ - { 5400000, 6000000, 0x1C, 0x2C }, /* HF_MN, */ - { 1250000, 500000, 0x18, 0x2C }, /* HF_FM_Radio, */ - { 0, 0, 0x00, 0x00 }, /* HF_AnalogMax (Unused) */ - { 3300000, 6000000, 0x1C, 0x58 }, /* HF_DVBT_6MHZ */ - { 3500000, 7000000, 0x1C, 0x37 }, /* HF_DVBT_7MHZ */ - { 4000000, 8000000, 0x1D, 0x37 }, /* HF_DVBT_8MHZ */ - { 0, 0, 0x00, 0x00 }, /* HF_DVBT (Unused) */ - { 5000000, 6000000, 0x1C, 0x37 }, /* HF_ATSC (center = 3.25 MHz) */ - { 4000000, 6000000, 0x1D, 0x58 }, /* HF_DVBC_6MHZ (Chicago) */ - { 4500000, 7000000, 0x1E, 0x37 }, /* HF_DVBC_7MHZ (not documented by NXP) */ - { 5000000, 8000000, 0x1F, 0x37 }, /* HF_DVBC_8MHZ */ - { 0, 0, 0x00, 0x00 }, /* HF_DVBC (Unused) */ -}; - -struct SMap m_BP_Filter_Map[] = { - { 62000000, 0x00 }, - { 84000000, 0x01 }, - { 100000000, 0x02 }, - { 140000000, 0x03 }, - { 170000000, 0x04 }, - { 180000000, 0x05 }, - { 865000000, 0x06 }, - { 0, 0x00 }, /* Table End */ -}; - -static struct SMapI m_RF_Cal_Map[] = { - { 41000000, 0x0F }, - { 43000000, 0x1C }, - { 45000000, 0x2F }, - { 46000000, 0x39 }, - { 47000000, 0x40 }, - { 47900000, 0x50 }, - { 49100000, 0x16 }, - { 50000000, 0x18 }, - { 51000000, 0x20 }, - { 53000000, 0x28 }, - { 55000000, 0x2B }, - { 56000000, 0x32 }, - { 57000000, 0x35 }, - { 58000000, 0x3E }, - { 59000000, 0x43 }, - { 60000000, 0x4E }, - { 61100000, 0x55 }, - { 63000000, 0x0F }, - { 64000000, 0x11 }, - { 65000000, 0x12 }, - { 66000000, 0x15 }, - { 67000000, 0x16 }, - { 68000000, 0x17 }, - { 70000000, 0x19 }, - { 71000000, 0x1C }, - { 72000000, 0x1D }, - { 73000000, 0x1F }, - { 74000000, 0x20 }, - { 75000000, 0x21 }, - { 76000000, 0x24 }, - { 77000000, 0x25 }, - { 78000000, 0x27 }, - { 80000000, 0x28 }, - { 81000000, 0x29 }, - { 82000000, 0x2D }, - { 83000000, 0x2E }, - { 84000000, 0x2F }, - { 85000000, 0x31 }, - { 86000000, 0x33 }, - { 87000000, 0x34 }, - { 88000000, 0x35 }, - { 89000000, 0x37 }, - { 90000000, 0x38 }, - { 91000000, 0x39 }, - { 93000000, 0x3C }, - { 94000000, 0x3E }, - { 95000000, 0x3F }, - { 96000000, 0x40 }, - { 97000000, 0x42 }, - { 99000000, 0x45 }, - { 100000000, 0x46 }, - { 102000000, 0x48 }, - { 103000000, 0x4A }, - { 105000000, 0x4D }, - { 106000000, 0x4E }, - { 107000000, 0x50 }, - { 108000000, 0x51 }, - { 110000000, 0x54 }, - { 111000000, 0x56 }, - { 112000000, 0x57 }, - { 113000000, 0x58 }, - { 114000000, 0x59 }, - { 115000000, 0x5C }, - { 116000000, 0x5D }, - { 117000000, 0x5F }, - { 119000000, 0x60 }, - { 120000000, 0x64 }, - { 121000000, 0x65 }, - { 122000000, 0x66 }, - { 123000000, 0x68 }, - { 124000000, 0x69 }, - { 125000000, 0x6C }, - { 126000000, 0x6D }, - { 127000000, 0x6E }, - { 128000000, 0x70 }, - { 129000000, 0x71 }, - { 130000000, 0x75 }, - { 131000000, 0x77 }, - { 132000000, 0x78 }, - { 133000000, 0x7B }, - { 134000000, 0x7E }, - { 135000000, 0x81 }, - { 136000000, 0x82 }, - { 137000000, 0x87 }, - { 138000000, 0x88 }, - { 139000000, 0x8D }, - { 140000000, 0x8E }, - { 141000000, 0x91 }, - { 142000000, 0x95 }, - { 143000000, 0x9A }, - { 144000000, 0x9D }, - { 145000000, 0xA1 }, - { 146000000, 0xA2 }, - { 147000000, 0xA4 }, - { 148000000, 0xA9 }, - { 149000000, 0xAE }, - { 150000000, 0xB0 }, - { 151000000, 0xB1 }, - { 152000000, 0xB7 }, - { 152600000, 0xBD }, - { 154000000, 0x20 }, - { 155000000, 0x22 }, - { 156000000, 0x24 }, - { 157000000, 0x25 }, - { 158000000, 0x27 }, - { 159000000, 0x29 }, - { 160000000, 0x2C }, - { 161000000, 0x2D }, - { 163000000, 0x2E }, - { 164000000, 0x2F }, - { 164700000, 0x30 }, - { 166000000, 0x11 }, - { 167000000, 0x12 }, - { 168000000, 0x13 }, - { 169000000, 0x14 }, - { 170000000, 0x15 }, - { 172000000, 0x16 }, - { 173000000, 0x17 }, - { 174000000, 0x18 }, - { 175000000, 0x1A }, - { 176000000, 0x1B }, - { 178000000, 0x1D }, - { 179000000, 0x1E }, - { 180000000, 0x1F }, - { 181000000, 0x20 }, - { 182000000, 0x21 }, - { 183000000, 0x22 }, - { 184000000, 0x24 }, - { 185000000, 0x25 }, - { 186000000, 0x26 }, - { 187000000, 0x27 }, - { 188000000, 0x29 }, - { 189000000, 0x2A }, - { 190000000, 0x2C }, - { 191000000, 0x2D }, - { 192000000, 0x2E }, - { 193000000, 0x2F }, - { 194000000, 0x30 }, - { 195000000, 0x33 }, - { 196000000, 0x35 }, - { 198000000, 0x36 }, - { 200000000, 0x38 }, - { 201000000, 0x3C }, - { 202000000, 0x3D }, - { 203500000, 0x3E }, - { 206000000, 0x0E }, - { 208000000, 0x0F }, - { 212000000, 0x10 }, - { 216000000, 0x11 }, - { 217000000, 0x12 }, - { 218000000, 0x13 }, - { 220000000, 0x14 }, - { 222000000, 0x15 }, - { 225000000, 0x16 }, - { 228000000, 0x17 }, - { 231000000, 0x18 }, - { 234000000, 0x19 }, - { 235000000, 0x1A }, - { 236000000, 0x1B }, - { 237000000, 0x1C }, - { 240000000, 0x1D }, - { 242000000, 0x1E }, - { 244000000, 0x1F }, - { 247000000, 0x20 }, - { 249000000, 0x21 }, - { 252000000, 0x22 }, - { 253000000, 0x23 }, - { 254000000, 0x24 }, - { 256000000, 0x25 }, - { 259000000, 0x26 }, - { 262000000, 0x27 }, - { 264000000, 0x28 }, - { 267000000, 0x29 }, - { 269000000, 0x2A }, - { 271000000, 0x2B }, - { 273000000, 0x2C }, - { 275000000, 0x2D }, - { 277000000, 0x2E }, - { 279000000, 0x2F }, - { 282000000, 0x30 }, - { 284000000, 0x31 }, - { 286000000, 0x32 }, - { 287000000, 0x33 }, - { 290000000, 0x34 }, - { 293000000, 0x35 }, - { 295000000, 0x36 }, - { 297000000, 0x37 }, - { 300000000, 0x38 }, - { 303000000, 0x39 }, - { 305000000, 0x3A }, - { 306000000, 0x3B }, - { 307000000, 0x3C }, - { 310000000, 0x3D }, - { 312000000, 0x3E }, - { 315000000, 0x3F }, - { 318000000, 0x40 }, - { 320000000, 0x41 }, - { 323000000, 0x42 }, - { 324000000, 0x43 }, - { 325000000, 0x44 }, - { 327000000, 0x45 }, - { 331000000, 0x46 }, - { 334000000, 0x47 }, - { 337000000, 0x48 }, - { 339000000, 0x49 }, - { 340000000, 0x4A }, - { 341000000, 0x4B }, - { 343000000, 0x4C }, - { 345000000, 0x4D }, - { 349000000, 0x4E }, - { 352000000, 0x4F }, - { 353000000, 0x50 }, - { 355000000, 0x51 }, - { 357000000, 0x52 }, - { 359000000, 0x53 }, - { 361000000, 0x54 }, - { 362000000, 0x55 }, - { 364000000, 0x56 }, - { 368000000, 0x57 }, - { 370000000, 0x58 }, - { 372000000, 0x59 }, - { 375000000, 0x5A }, - { 376000000, 0x5B }, - { 377000000, 0x5C }, - { 379000000, 0x5D }, - { 382000000, 0x5E }, - { 384000000, 0x5F }, - { 385000000, 0x60 }, - { 386000000, 0x61 }, - { 388000000, 0x62 }, - { 390000000, 0x63 }, - { 393000000, 0x64 }, - { 394000000, 0x65 }, - { 396000000, 0x66 }, - { 397000000, 0x67 }, - { 398000000, 0x68 }, - { 400000000, 0x69 }, - { 402000000, 0x6A }, - { 403000000, 0x6B }, - { 407000000, 0x6C }, - { 408000000, 0x6D }, - { 409000000, 0x6E }, - { 410000000, 0x6F }, - { 411000000, 0x70 }, - { 412000000, 0x71 }, - { 413000000, 0x72 }, - { 414000000, 0x73 }, - { 417000000, 0x74 }, - { 418000000, 0x75 }, - { 420000000, 0x76 }, - { 422000000, 0x77 }, - { 423000000, 0x78 }, - { 424000000, 0x79 }, - { 427000000, 0x7A }, - { 428000000, 0x7B }, - { 429000000, 0x7D }, - { 432000000, 0x7F }, - { 434000000, 0x80 }, - { 435000000, 0x81 }, - { 436000000, 0x83 }, - { 437000000, 0x84 }, - { 438000000, 0x85 }, - { 439000000, 0x86 }, - { 440000000, 0x87 }, - { 441000000, 0x88 }, - { 442000000, 0x89 }, - { 445000000, 0x8A }, - { 446000000, 0x8B }, - { 447000000, 0x8C }, - { 448000000, 0x8E }, - { 449000000, 0x8F }, - { 450000000, 0x90 }, - { 452000000, 0x91 }, - { 453000000, 0x93 }, - { 454000000, 0x94 }, - { 456000000, 0x96 }, - { 457800000, 0x98 }, - { 461000000, 0x11 }, - { 468000000, 0x12 }, - { 472000000, 0x13 }, - { 473000000, 0x14 }, - { 474000000, 0x15 }, - { 481000000, 0x16 }, - { 486000000, 0x17 }, - { 491000000, 0x18 }, - { 498000000, 0x19 }, - { 499000000, 0x1A }, - { 501000000, 0x1B }, - { 506000000, 0x1C }, - { 511000000, 0x1D }, - { 516000000, 0x1E }, - { 520000000, 0x1F }, - { 521000000, 0x20 }, - { 525000000, 0x21 }, - { 529000000, 0x22 }, - { 533000000, 0x23 }, - { 539000000, 0x24 }, - { 541000000, 0x25 }, - { 547000000, 0x26 }, - { 549000000, 0x27 }, - { 551000000, 0x28 }, - { 556000000, 0x29 }, - { 561000000, 0x2A }, - { 563000000, 0x2B }, - { 565000000, 0x2C }, - { 569000000, 0x2D }, - { 571000000, 0x2E }, - { 577000000, 0x2F }, - { 580000000, 0x30 }, - { 582000000, 0x31 }, - { 584000000, 0x32 }, - { 588000000, 0x33 }, - { 591000000, 0x34 }, - { 596000000, 0x35 }, - { 598000000, 0x36 }, - { 603000000, 0x37 }, - { 604000000, 0x38 }, - { 606000000, 0x39 }, - { 612000000, 0x3A }, - { 615000000, 0x3B }, - { 617000000, 0x3C }, - { 621000000, 0x3D }, - { 622000000, 0x3E }, - { 625000000, 0x3F }, - { 632000000, 0x40 }, - { 633000000, 0x41 }, - { 634000000, 0x42 }, - { 642000000, 0x43 }, - { 643000000, 0x44 }, - { 647000000, 0x45 }, - { 650000000, 0x46 }, - { 652000000, 0x47 }, - { 657000000, 0x48 }, - { 661000000, 0x49 }, - { 662000000, 0x4A }, - { 665000000, 0x4B }, - { 667000000, 0x4C }, - { 670000000, 0x4D }, - { 673000000, 0x4E }, - { 676000000, 0x4F }, - { 677000000, 0x50 }, - { 681000000, 0x51 }, - { 683000000, 0x52 }, - { 686000000, 0x53 }, - { 688000000, 0x54 }, - { 689000000, 0x55 }, - { 691000000, 0x56 }, - { 695000000, 0x57 }, - { 698000000, 0x58 }, - { 703000000, 0x59 }, - { 704000000, 0x5A }, - { 705000000, 0x5B }, - { 707000000, 0x5C }, - { 710000000, 0x5D }, - { 712000000, 0x5E }, - { 717000000, 0x5F }, - { 718000000, 0x60 }, - { 721000000, 0x61 }, - { 722000000, 0x62 }, - { 723000000, 0x63 }, - { 725000000, 0x64 }, - { 727000000, 0x65 }, - { 730000000, 0x66 }, - { 732000000, 0x67 }, - { 735000000, 0x68 }, - { 740000000, 0x69 }, - { 741000000, 0x6A }, - { 742000000, 0x6B }, - { 743000000, 0x6C }, - { 745000000, 0x6D }, - { 747000000, 0x6E }, - { 748000000, 0x6F }, - { 750000000, 0x70 }, - { 752000000, 0x71 }, - { 754000000, 0x72 }, - { 757000000, 0x73 }, - { 758000000, 0x74 }, - { 760000000, 0x75 }, - { 763000000, 0x76 }, - { 764000000, 0x77 }, - { 766000000, 0x78 }, - { 767000000, 0x79 }, - { 768000000, 0x7A }, - { 773000000, 0x7B }, - { 774000000, 0x7C }, - { 776000000, 0x7D }, - { 777000000, 0x7E }, - { 778000000, 0x7F }, - { 779000000, 0x80 }, - { 781000000, 0x81 }, - { 783000000, 0x82 }, - { 784000000, 0x83 }, - { 785000000, 0x84 }, - { 786000000, 0x85 }, - { 793000000, 0x86 }, - { 794000000, 0x87 }, - { 795000000, 0x88 }, - { 797000000, 0x89 }, - { 799000000, 0x8A }, - { 801000000, 0x8B }, - { 802000000, 0x8C }, - { 803000000, 0x8D }, - { 804000000, 0x8E }, - { 810000000, 0x90 }, - { 811000000, 0x91 }, - { 812000000, 0x92 }, - { 814000000, 0x93 }, - { 816000000, 0x94 }, - { 817000000, 0x96 }, - { 818000000, 0x97 }, - { 820000000, 0x98 }, - { 821000000, 0x99 }, - { 822000000, 0x9A }, - { 828000000, 0x9B }, - { 829000000, 0x9D }, - { 830000000, 0x9F }, - { 831000000, 0xA0 }, - { 833000000, 0xA1 }, - { 835000000, 0xA2 }, - { 836000000, 0xA3 }, - { 837000000, 0xA4 }, - { 838000000, 0xA6 }, - { 840000000, 0xA8 }, - { 842000000, 0xA9 }, - { 845000000, 0xAA }, - { 846000000, 0xAB }, - { 847000000, 0xAD }, - { 848000000, 0xAE }, - { 852000000, 0xAF }, - { 853000000, 0xB0 }, - { 858000000, 0xB1 }, - { 860000000, 0xB2 }, - { 861000000, 0xB3 }, - { 862000000, 0xB4 }, - { 863000000, 0xB6 }, - { 864000000, 0xB8 }, - { 865000000, 0xB9 }, - { 0, 0x00 }, /* Table End */ -}; - - -static struct SMap2 m_KM_Map[] = { - { 47900000, 3, 2 }, - { 61100000, 3, 1 }, - { 350000000, 3, 0 }, - { 720000000, 2, 1 }, - { 865000000, 3, 3 }, - { 0, 0x00 }, /* Table End */ -}; - -static struct SMap2 m_Main_PLL_Map[] = { - { 33125000, 0x57, 0xF0 }, - { 35500000, 0x56, 0xE0 }, - { 38188000, 0x55, 0xD0 }, - { 41375000, 0x54, 0xC0 }, - { 45125000, 0x53, 0xB0 }, - { 49688000, 0x52, 0xA0 }, - { 55188000, 0x51, 0x90 }, - { 62125000, 0x50, 0x80 }, - { 66250000, 0x47, 0x78 }, - { 71000000, 0x46, 0x70 }, - { 76375000, 0x45, 0x68 }, - { 82750000, 0x44, 0x60 }, - { 90250000, 0x43, 0x58 }, - { 99375000, 0x42, 0x50 }, - { 110375000, 0x41, 0x48 }, - { 124250000, 0x40, 0x40 }, - { 132500000, 0x37, 0x3C }, - { 142000000, 0x36, 0x38 }, - { 152750000, 0x35, 0x34 }, - { 165500000, 0x34, 0x30 }, - { 180500000, 0x33, 0x2C }, - { 198750000, 0x32, 0x28 }, - { 220750000, 0x31, 0x24 }, - { 248500000, 0x30, 0x20 }, - { 265000000, 0x27, 0x1E }, - { 284000000, 0x26, 0x1C }, - { 305500000, 0x25, 0x1A }, - { 331000000, 0x24, 0x18 }, - { 361000000, 0x23, 0x16 }, - { 397500000, 0x22, 0x14 }, - { 441500000, 0x21, 0x12 }, - { 497000000, 0x20, 0x10 }, - { 530000000, 0x17, 0x0F }, - { 568000000, 0x16, 0x0E }, - { 611000000, 0x15, 0x0D }, - { 662000000, 0x14, 0x0C }, - { 722000000, 0x13, 0x0B }, - { 795000000, 0x12, 0x0A }, - { 883000000, 0x11, 0x09 }, - { 994000000, 0x10, 0x08 }, - { 0, 0x00, 0x00 }, /* Table End */ -}; - -static struct SMap2 m_Cal_PLL_Map[] = { - { 33813000, 0xDD, 0xD0 }, - { 36625000, 0xDC, 0xC0 }, - { 39938000, 0xDB, 0xB0 }, - { 43938000, 0xDA, 0xA0 }, - { 48813000, 0xD9, 0x90 }, - { 54938000, 0xD8, 0x80 }, - { 62813000, 0xD3, 0x70 }, - { 67625000, 0xCD, 0x68 }, - { 73250000, 0xCC, 0x60 }, - { 79875000, 0xCB, 0x58 }, - { 87875000, 0xCA, 0x50 }, - { 97625000, 0xC9, 0x48 }, - { 109875000, 0xC8, 0x40 }, - { 125625000, 0xC3, 0x38 }, - { 135250000, 0xBD, 0x34 }, - { 146500000, 0xBC, 0x30 }, - { 159750000, 0xBB, 0x2C }, - { 175750000, 0xBA, 0x28 }, - { 195250000, 0xB9, 0x24 }, - { 219750000, 0xB8, 0x20 }, - { 251250000, 0xB3, 0x1C }, - { 270500000, 0xAD, 0x1A }, - { 293000000, 0xAC, 0x18 }, - { 319500000, 0xAB, 0x16 }, - { 351500000, 0xAA, 0x14 }, - { 390500000, 0xA9, 0x12 }, - { 439500000, 0xA8, 0x10 }, - { 502500000, 0xA3, 0x0E }, - { 541000000, 0x9D, 0x0D }, - { 586000000, 0x9C, 0x0C }, - { 639000000, 0x9B, 0x0B }, - { 703000000, 0x9A, 0x0A }, - { 781000000, 0x99, 0x09 }, - { 879000000, 0x98, 0x08 }, - { 0, 0x00, 0x00 }, /* Table End */ -}; - -static struct SMap m_GainTaper_Map[] = { - { 45400000, 0x1F }, - { 45800000, 0x1E }, - { 46200000, 0x1D }, - { 46700000, 0x1C }, - { 47100000, 0x1B }, - { 47500000, 0x1A }, - { 47900000, 0x19 }, - { 49600000, 0x17 }, - { 51200000, 0x16 }, - { 52900000, 0x15 }, - { 54500000, 0x14 }, - { 56200000, 0x13 }, - { 57800000, 0x12 }, - { 59500000, 0x11 }, - { 61100000, 0x10 }, - { 67600000, 0x0D }, - { 74200000, 0x0C }, - { 80700000, 0x0B }, - { 87200000, 0x0A }, - { 93800000, 0x09 }, - { 100300000, 0x08 }, - { 106900000, 0x07 }, - { 113400000, 0x06 }, - { 119900000, 0x05 }, - { 126500000, 0x04 }, - { 133000000, 0x03 }, - { 139500000, 0x02 }, - { 146100000, 0x01 }, - { 152600000, 0x00 }, - { 154300000, 0x1F }, - { 156100000, 0x1E }, - { 157800000, 0x1D }, - { 159500000, 0x1C }, - { 161200000, 0x1B }, - { 163000000, 0x1A }, - { 164700000, 0x19 }, - { 170200000, 0x17 }, - { 175800000, 0x16 }, - { 181300000, 0x15 }, - { 186900000, 0x14 }, - { 192400000, 0x13 }, - { 198000000, 0x12 }, - { 203500000, 0x11 }, - { 216200000, 0x14 }, - { 228900000, 0x13 }, - { 241600000, 0x12 }, - { 254400000, 0x11 }, - { 267100000, 0x10 }, - { 279800000, 0x0F }, - { 292500000, 0x0E }, - { 305200000, 0x0D }, - { 317900000, 0x0C }, - { 330700000, 0x0B }, - { 343400000, 0x0A }, - { 356100000, 0x09 }, - { 368800000, 0x08 }, - { 381500000, 0x07 }, - { 394200000, 0x06 }, - { 406900000, 0x05 }, - { 419700000, 0x04 }, - { 432400000, 0x03 }, - { 445100000, 0x02 }, - { 457800000, 0x01 }, - { 476300000, 0x19 }, - { 494800000, 0x18 }, - { 513300000, 0x17 }, - { 531800000, 0x16 }, - { 550300000, 0x15 }, - { 568900000, 0x14 }, - { 587400000, 0x13 }, - { 605900000, 0x12 }, - { 624400000, 0x11 }, - { 642900000, 0x10 }, - { 661400000, 0x0F }, - { 679900000, 0x0E }, - { 698400000, 0x0D }, - { 716900000, 0x0C }, - { 735400000, 0x0B }, - { 753900000, 0x0A }, - { 772500000, 0x09 }, - { 791000000, 0x08 }, - { 809500000, 0x07 }, - { 828000000, 0x06 }, - { 846500000, 0x05 }, - { 865000000, 0x04 }, - { 0, 0x00 }, /* Table End */ -}; - -static struct SMap m_RF_Cal_DC_Over_DT_Map[] = { - { 47900000, 0x00 }, - { 55000000, 0x00 }, - { 61100000, 0x0A }, - { 64000000, 0x0A }, - { 82000000, 0x14 }, - { 84000000, 0x19 }, - { 119000000, 0x1C }, - { 124000000, 0x20 }, - { 129000000, 0x2A }, - { 134000000, 0x32 }, - { 139000000, 0x39 }, - { 144000000, 0x3E }, - { 149000000, 0x3F }, - { 152600000, 0x40 }, - { 154000000, 0x40 }, - { 164700000, 0x41 }, - { 203500000, 0x32 }, - { 353000000, 0x19 }, - { 356000000, 0x1A }, - { 359000000, 0x1B }, - { 363000000, 0x1C }, - { 366000000, 0x1D }, - { 369000000, 0x1E }, - { 373000000, 0x1F }, - { 376000000, 0x20 }, - { 379000000, 0x21 }, - { 383000000, 0x22 }, - { 386000000, 0x23 }, - { 389000000, 0x24 }, - { 393000000, 0x25 }, - { 396000000, 0x26 }, - { 399000000, 0x27 }, - { 402000000, 0x28 }, - { 404000000, 0x29 }, - { 407000000, 0x2A }, - { 409000000, 0x2B }, - { 412000000, 0x2C }, - { 414000000, 0x2D }, - { 417000000, 0x2E }, - { 419000000, 0x2F }, - { 422000000, 0x30 }, - { 424000000, 0x31 }, - { 427000000, 0x32 }, - { 429000000, 0x33 }, - { 432000000, 0x34 }, - { 434000000, 0x35 }, - { 437000000, 0x36 }, - { 439000000, 0x37 }, - { 442000000, 0x38 }, - { 444000000, 0x39 }, - { 447000000, 0x3A }, - { 449000000, 0x3B }, - { 457800000, 0x3C }, - { 465000000, 0x0F }, - { 477000000, 0x12 }, - { 483000000, 0x14 }, - { 502000000, 0x19 }, - { 508000000, 0x1B }, - { 519000000, 0x1C }, - { 522000000, 0x1D }, - { 524000000, 0x1E }, - { 534000000, 0x1F }, - { 549000000, 0x20 }, - { 554000000, 0x22 }, - { 584000000, 0x24 }, - { 589000000, 0x26 }, - { 658000000, 0x27 }, - { 664000000, 0x2C }, - { 669000000, 0x2D }, - { 699000000, 0x2E }, - { 704000000, 0x30 }, - { 709000000, 0x31 }, - { 714000000, 0x32 }, - { 724000000, 0x33 }, - { 729000000, 0x36 }, - { 739000000, 0x38 }, - { 744000000, 0x39 }, - { 749000000, 0x3B }, - { 754000000, 0x3C }, - { 759000000, 0x3D }, - { 764000000, 0x3E }, - { 769000000, 0x3F }, - { 774000000, 0x40 }, - { 779000000, 0x41 }, - { 784000000, 0x43 }, - { 789000000, 0x46 }, - { 794000000, 0x48 }, - { 799000000, 0x4B }, - { 804000000, 0x4F }, - { 809000000, 0x54 }, - { 814000000, 0x59 }, - { 819000000, 0x5D }, - { 824000000, 0x61 }, - { 829000000, 0x68 }, - { 834000000, 0x6E }, - { 839000000, 0x75 }, - { 844000000, 0x7E }, - { 849000000, 0x82 }, - { 854000000, 0x84 }, - { 859000000, 0x8F }, - { 865000000, 0x9A }, - { 0, 0x00 }, /* Table End */ -}; - - -static struct SMap m_IR_Meas_Map[] = { - { 200000000, 0x05 }, - { 400000000, 0x06 }, - { 865000000, 0x07 }, - { 0, 0x00 }, /* Table End */ -}; - -static struct SMap2 m_CID_Target_Map[] = { - { 46000000, 0x04, 18 }, - { 52200000, 0x0A, 15 }, - { 70100000, 0x01, 40 }, - { 136800000, 0x18, 40 }, - { 156700000, 0x18, 40 }, - { 186250000, 0x0A, 40 }, - { 230000000, 0x0A, 40 }, - { 345000000, 0x18, 40 }, - { 426000000, 0x0E, 40 }, - { 489500000, 0x1E, 40 }, - { 697500000, 0x32, 40 }, - { 842000000, 0x3A, 40 }, - { 0, 0x00, 0 }, /* Table End */ -}; - -static struct SRFBandMap m_RF_Band_Map[7] = { - { 47900000, 46000000, 0, 0}, - { 61100000, 52200000, 0, 0}, - { 152600000, 70100000, 136800000, 0}, - { 164700000, 156700000, 0, 0}, - { 203500000, 186250000, 0, 0}, - { 457800000, 230000000, 345000000, 426000000}, - { 865000000, 489500000, 697500000, 842000000}, -}; - -u8 m_Thermometer_Map_1[16] = { - 60, 62, 66, 64, - 74, 72, 68, 70, - 90, 88, 84, 86, - 76, 78, 82, 80, -}; - -u8 m_Thermometer_Map_2[16] = { - 92, 94, 98, 96, - 106, 104, 100, 102, - 122, 120, 116, 118, - 108, 110, 114, 112, -}; diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/Kbuild 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/Kbuild 1970-01-01 00:00:00.000000000 +0000 @@ -1,8 +0,0 @@ -header-y += audio.h -header-y += ca.h -header-y += dmx.h -header-y += frontend.h -header-y += net.h -header-y += osd.h -header-y += version.h -header-y += video.h diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/audio.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/audio.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/audio.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/audio.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,135 +0,0 @@ -/* - * audio.h - * - * Copyright (C) 2000 Ralph Metzler - * & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Lesser Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVBAUDIO_H_ -#define _DVBAUDIO_H_ - -#include - -typedef enum { - AUDIO_SOURCE_DEMUX, /* Select the demux as the main source */ - AUDIO_SOURCE_MEMORY /* Select internal memory as the main source */ -} audio_stream_source_t; - - -typedef enum { - AUDIO_STOPPED, /* Device is stopped */ - AUDIO_PLAYING, /* Device is currently playing */ - AUDIO_PAUSED /* Device is paused */ -} audio_play_state_t; - - -typedef enum { - AUDIO_STEREO, - AUDIO_MONO_LEFT, - AUDIO_MONO_RIGHT, - AUDIO_MONO, - AUDIO_STEREO_SWAPPED -} audio_channel_select_t; - - -typedef struct audio_mixer { - unsigned int volume_left; - unsigned int volume_right; - // what else do we need? bass, pass-through, ... -} audio_mixer_t; - - -typedef struct audio_status { - int AV_sync_state; /* sync audio and video? */ - int mute_state; /* audio is muted */ - audio_play_state_t play_state; /* current playback state */ - audio_stream_source_t stream_source; /* current stream source */ - audio_channel_select_t channel_select; /* currently selected channel */ - int bypass_mode; /* pass on audio data to */ - audio_mixer_t mixer_state; /* current mixer state */ -} audio_status_t; /* separate decoder hardware */ - - -typedef -struct audio_karaoke { /* if Vocal1 or Vocal2 are non-zero, they get mixed */ - int vocal1; /* into left and right t at 70% each */ - int vocal2; /* if both, Vocal1 and Vocal2 are non-zero, Vocal1 gets*/ - int melody; /* mixed into the left channel and */ - /* Vocal2 into the right channel at 100% each. */ - /* if Melody is non-zero, the melody channel gets mixed*/ -} audio_karaoke_t; /* into left and right */ - - -typedef __u16 audio_attributes_t; -/* bits: descr. */ -/* 15-13 audio coding mode (0=ac3, 2=mpeg1, 3=mpeg2ext, 4=LPCM, 6=DTS, */ -/* 12 multichannel extension */ -/* 11-10 audio type (0=not spec, 1=language included) */ -/* 9- 8 audio application mode (0=not spec, 1=karaoke, 2=surround) */ -/* 7- 6 Quantization / DRC (mpeg audio: 1=DRC exists)(lpcm: 0=16bit, */ -/* 5- 4 Sample frequency fs (0=48kHz, 1=96kHz) */ -/* 2- 0 number of audio channels (n+1 channels) */ - - -/* for GET_CAPABILITIES and SET_FORMAT, the latter should only set one bit */ -#define AUDIO_CAP_DTS 1 -#define AUDIO_CAP_LPCM 2 -#define AUDIO_CAP_MP1 4 -#define AUDIO_CAP_MP2 8 -#define AUDIO_CAP_MP3 16 -#define AUDIO_CAP_AAC 32 -#define AUDIO_CAP_OGG 64 -#define AUDIO_CAP_SDDS 128 -#define AUDIO_CAP_AC3 256 - -#define AUDIO_STOP _IO('o', 1) -#define AUDIO_PLAY _IO('o', 2) -#define AUDIO_PAUSE _IO('o', 3) -#define AUDIO_CONTINUE _IO('o', 4) -#define AUDIO_SELECT_SOURCE _IO('o', 5) -#define AUDIO_SET_MUTE _IO('o', 6) -#define AUDIO_SET_AV_SYNC _IO('o', 7) -#define AUDIO_SET_BYPASS_MODE _IO('o', 8) -#define AUDIO_CHANNEL_SELECT _IO('o', 9) -#define AUDIO_GET_STATUS _IOR('o', 10, audio_status_t) - -#define AUDIO_GET_CAPABILITIES _IOR('o', 11, unsigned int) -#define AUDIO_CLEAR_BUFFER _IO('o', 12) -#define AUDIO_SET_ID _IO('o', 13) -#define AUDIO_SET_MIXER _IOW('o', 14, audio_mixer_t) -#define AUDIO_SET_STREAMTYPE _IO('o', 15) -#define AUDIO_SET_EXT_ID _IO('o', 16) -#define AUDIO_SET_ATTRIBUTES _IOW('o', 17, audio_attributes_t) -#define AUDIO_SET_KARAOKE _IOW('o', 18, audio_karaoke_t) - -/** - * AUDIO_GET_PTS - * - * Read the 33 bit presentation time stamp as defined - * in ITU T-REC-H.222.0 / ISO/IEC 13818-1. - * - * The PTS should belong to the currently played - * frame if possible, but may also be a value close to it - * like the PTS of the last decoded frame or the last PTS - * extracted by the PES parser. - */ -#define AUDIO_GET_PTS _IOR('o', 19, __u64) -#define AUDIO_BILINGUAL_CHANNEL_SELECT _IO('o', 20) - -#endif /* _DVBAUDIO_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ca.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ca.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ca.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ca.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,90 +0,0 @@ -/* - * ca.h - * - * Copyright (C) 2000 Ralph Metzler - * & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Lesser Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVBCA_H_ -#define _DVBCA_H_ - -/* slot interface types and info */ - -typedef struct ca_slot_info { - int num; /* slot number */ - - int type; /* CA interface this slot supports */ -#define CA_CI 1 /* CI high level interface */ -#define CA_CI_LINK 2 /* CI link layer level interface */ -#define CA_CI_PHYS 4 /* CI physical layer level interface */ -#define CA_DESCR 8 /* built-in descrambler */ -#define CA_SC 128 /* simple smart card interface */ - - unsigned int flags; -#define CA_CI_MODULE_PRESENT 1 /* module (or card) inserted */ -#define CA_CI_MODULE_READY 2 -} ca_slot_info_t; - - -/* descrambler types and info */ - -typedef struct ca_descr_info { - unsigned int num; /* number of available descramblers (keys) */ - unsigned int type; /* type of supported scrambling system */ -#define CA_ECD 1 -#define CA_NDS 2 -#define CA_DSS 4 -} ca_descr_info_t; - -typedef struct ca_caps { - unsigned int slot_num; /* total number of CA card and module slots */ - unsigned int slot_type; /* OR of all supported types */ - unsigned int descr_num; /* total number of descrambler slots (keys) */ - unsigned int descr_type; /* OR of all supported types */ -} ca_caps_t; - -/* a message to/from a CI-CAM */ -typedef struct ca_msg { - unsigned int index; - unsigned int type; - unsigned int length; - unsigned char msg[256]; -} ca_msg_t; - -typedef struct ca_descr { - unsigned int index; - unsigned int parity; /* 0 == even, 1 == odd */ - unsigned char cw[8]; -} ca_descr_t; - -typedef struct ca_pid { - unsigned int pid; - int index; /* -1 == disable*/ -} ca_pid_t; - -#define CA_RESET _IO('o', 128) -#define CA_GET_CAP _IOR('o', 129, ca_caps_t) -#define CA_GET_SLOT_INFO _IOR('o', 130, ca_slot_info_t) -#define CA_GET_DESCR_INFO _IOR('o', 131, ca_descr_info_t) -#define CA_GET_MSG _IOR('o', 132, ca_msg_t) -#define CA_SEND_MSG _IOW('o', 133, ca_msg_t) -#define CA_SET_DESCR _IOW('o', 134, ca_descr_t) -#define CA_SET_PID _IOW('o', 135, ca_pid_t) - -#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/dmx.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/dmx.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/dmx.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/dmx.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,155 +0,0 @@ -/* - * dmx.h - * - * Copyright (C) 2000 Marcus Metzler - * & Ralph Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _UAPI_DVBDMX_H_ -#define _UAPI_DVBDMX_H_ - -#include -#ifndef __KERNEL__ -#include -#endif - - -#define DMX_FILTER_SIZE 16 - -typedef enum -{ - DMX_OUT_DECODER, /* Streaming directly to decoder. */ - DMX_OUT_TAP, /* Output going to a memory buffer */ - /* (to be retrieved via the read command).*/ - DMX_OUT_TS_TAP, /* Output multiplexed into a new TS */ - /* (to be retrieved by reading from the */ - /* logical DVR device). */ - DMX_OUT_TSDEMUX_TAP /* Like TS_TAP but retrieved from the DMX device */ -} dmx_output_t; - - -typedef enum -{ - DMX_IN_FRONTEND, /* Input from a front-end device. */ - DMX_IN_DVR /* Input from the logical DVR device. */ -} dmx_input_t; - - -typedef enum dmx_ts_pes -{ - DMX_PES_AUDIO0, - DMX_PES_VIDEO0, - DMX_PES_TELETEXT0, - DMX_PES_SUBTITLE0, - DMX_PES_PCR0, - - DMX_PES_AUDIO1, - DMX_PES_VIDEO1, - DMX_PES_TELETEXT1, - DMX_PES_SUBTITLE1, - DMX_PES_PCR1, - - DMX_PES_AUDIO2, - DMX_PES_VIDEO2, - DMX_PES_TELETEXT2, - DMX_PES_SUBTITLE2, - DMX_PES_PCR2, - - DMX_PES_AUDIO3, - DMX_PES_VIDEO3, - DMX_PES_TELETEXT3, - DMX_PES_SUBTITLE3, - DMX_PES_PCR3, - - DMX_PES_OTHER -} dmx_pes_type_t; - -#define DMX_PES_AUDIO DMX_PES_AUDIO0 -#define DMX_PES_VIDEO DMX_PES_VIDEO0 -#define DMX_PES_TELETEXT DMX_PES_TELETEXT0 -#define DMX_PES_SUBTITLE DMX_PES_SUBTITLE0 -#define DMX_PES_PCR DMX_PES_PCR0 - - -typedef struct dmx_filter -{ - __u8 filter[DMX_FILTER_SIZE]; - __u8 mask[DMX_FILTER_SIZE]; - __u8 mode[DMX_FILTER_SIZE]; -} dmx_filter_t; - - -struct dmx_sct_filter_params -{ - __u16 pid; - dmx_filter_t filter; - __u32 timeout; - __u32 flags; -#define DMX_CHECK_CRC 1 -#define DMX_ONESHOT 2 -#define DMX_IMMEDIATE_START 4 -#define DMX_KERNEL_CLIENT 0x8000 -}; - - -struct dmx_pes_filter_params -{ - __u16 pid; - dmx_input_t input; - dmx_output_t output; - dmx_pes_type_t pes_type; - __u32 flags; -}; - -typedef struct dmx_caps { - __u32 caps; - int num_decoders; -} dmx_caps_t; - -typedef enum { - DMX_SOURCE_FRONT0 = 0, - DMX_SOURCE_FRONT1, - DMX_SOURCE_FRONT2, - DMX_SOURCE_FRONT3, - DMX_SOURCE_DVR0 = 16, - DMX_SOURCE_DVR1, - DMX_SOURCE_DVR2, - DMX_SOURCE_DVR3 -} dmx_source_t; - -struct dmx_stc { - unsigned int num; /* input : which STC? 0..N */ - unsigned int base; /* output: divisor for stc to get 90 kHz clock */ - __u64 stc; /* output: stc in 'base'*90 kHz units */ -}; - - -#define DMX_START _IO('o', 41) -#define DMX_STOP _IO('o', 42) -#define DMX_SET_FILTER _IOW('o', 43, struct dmx_sct_filter_params) -#define DMX_SET_PES_FILTER _IOW('o', 44, struct dmx_pes_filter_params) -#define DMX_SET_BUFFER_SIZE _IO('o', 45) -#define DMX_GET_PES_PIDS _IOR('o', 47, __u16[5]) -#define DMX_GET_CAPS _IOR('o', 48, dmx_caps_t) -#define DMX_SET_SOURCE _IOW('o', 49, dmx_source_t) -#define DMX_GET_STC _IOWR('o', 50, struct dmx_stc) -#define DMX_ADD_PID _IOW('o', 51, __u16) -#define DMX_REMOVE_PID _IOW('o', 52, __u16) - -#endif /* _UAPI_DVBDMX_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/frontend.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/frontend.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/frontend.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/frontend.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,594 +0,0 @@ -/* - * frontend.h - * - * Copyright (C) 2000 Marcus Metzler - * Ralph Metzler - * Holger Waechtler - * Andre Draszik - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVBFRONTEND_H_ -#define _DVBFRONTEND_H_ - -#include - -typedef enum fe_type { - FE_QPSK, - FE_QAM, - FE_OFDM, - FE_ATSC -} fe_type_t; - - -typedef enum fe_caps { - FE_IS_STUPID = 0, - FE_CAN_INVERSION_AUTO = 0x1, - FE_CAN_FEC_1_2 = 0x2, - FE_CAN_FEC_2_3 = 0x4, - FE_CAN_FEC_3_4 = 0x8, - FE_CAN_FEC_4_5 = 0x10, - FE_CAN_FEC_5_6 = 0x20, - FE_CAN_FEC_6_7 = 0x40, - FE_CAN_FEC_7_8 = 0x80, - FE_CAN_FEC_8_9 = 0x100, - FE_CAN_FEC_AUTO = 0x200, - FE_CAN_QPSK = 0x400, - FE_CAN_QAM_16 = 0x800, - FE_CAN_QAM_32 = 0x1000, - FE_CAN_QAM_64 = 0x2000, - FE_CAN_QAM_128 = 0x4000, - FE_CAN_QAM_256 = 0x8000, - FE_CAN_QAM_AUTO = 0x10000, - FE_CAN_TRANSMISSION_MODE_AUTO = 0x20000, - FE_CAN_BANDWIDTH_AUTO = 0x40000, - FE_CAN_GUARD_INTERVAL_AUTO = 0x80000, - FE_CAN_HIERARCHY_AUTO = 0x100000, - FE_CAN_8VSB = 0x200000, - FE_CAN_16VSB = 0x400000, - FE_HAS_EXTENDED_CAPS = 0x800000, /* We need more bitspace for newer APIs, indicate this. */ - FE_CAN_MULTISTREAM = 0x4000000, /* frontend supports multistream filtering */ - FE_CAN_TURBO_FEC = 0x8000000, /* frontend supports "turbo fec modulation" */ - FE_CAN_2G_MODULATION = 0x10000000, /* frontend supports "2nd generation modulation" (DVB-S2) */ - FE_NEEDS_BENDING = 0x20000000, /* not supported anymore, don't use (frontend requires frequency bending) */ - FE_CAN_RECOVER = 0x40000000, /* frontend can recover from a cable unplug automatically */ - FE_CAN_MUTE_TS = 0x80000000 /* frontend can stop spurious TS data output */ -} fe_caps_t; - - -struct dvb_frontend_info { - char name[128]; - fe_type_t type; /* DEPRECATED. Use DTV_ENUM_DELSYS instead */ - __u32 frequency_min; - __u32 frequency_max; - __u32 frequency_stepsize; - __u32 frequency_tolerance; - __u32 symbol_rate_min; - __u32 symbol_rate_max; - __u32 symbol_rate_tolerance; /* ppm */ - __u32 notifier_delay; /* DEPRECATED */ - fe_caps_t caps; -}; - - -/** - * Check out the DiSEqC bus spec available on http://www.eutelsat.org/ for - * the meaning of this struct... - */ -struct dvb_diseqc_master_cmd { - __u8 msg [6]; /* { framing, address, command, data [3] } */ - __u8 msg_len; /* valid values are 3...6 */ -}; - - -struct dvb_diseqc_slave_reply { - __u8 msg [4]; /* { framing, data [3] } */ - __u8 msg_len; /* valid values are 0...4, 0 means no msg */ - int timeout; /* return from ioctl after timeout ms with */ -}; /* errorcode when no message was received */ - - -typedef enum fe_sec_voltage { - SEC_VOLTAGE_13, - SEC_VOLTAGE_18, - SEC_VOLTAGE_OFF -} fe_sec_voltage_t; - - -typedef enum fe_sec_tone_mode { - SEC_TONE_ON, - SEC_TONE_OFF -} fe_sec_tone_mode_t; - - -typedef enum fe_sec_mini_cmd { - SEC_MINI_A, - SEC_MINI_B -} fe_sec_mini_cmd_t; - - -/** - * enum fe_status - enumerates the possible frontend status - * @FE_HAS_SIGNAL: found something above the noise level - * @FE_HAS_CARRIER: found a DVB signal - * @FE_HAS_VITERBI: FEC is stable - * @FE_HAS_SYNC: found sync bytes - * @FE_HAS_LOCK: everything's working - * @FE_TIMEDOUT: no lock within the last ~2 seconds - * @FE_REINIT: frontend was reinitialized, application is recommended - * to reset DiSEqC, tone and parameters - */ - -typedef enum fe_status { - FE_HAS_SIGNAL = 0x01, - FE_HAS_CARRIER = 0x02, - FE_HAS_VITERBI = 0x04, - FE_HAS_SYNC = 0x08, - FE_HAS_LOCK = 0x10, - FE_TIMEDOUT = 0x20, - FE_REINIT = 0x40, -} fe_status_t; - -typedef enum fe_spectral_inversion { - INVERSION_OFF, - INVERSION_ON, - INVERSION_AUTO -} fe_spectral_inversion_t; - - -typedef enum fe_code_rate { - FEC_NONE = 0, - FEC_1_2, - FEC_2_3, - FEC_3_4, - FEC_4_5, - FEC_5_6, - FEC_6_7, - FEC_7_8, - FEC_8_9, - FEC_AUTO, - FEC_3_5, - FEC_9_10, - FEC_2_5, -} fe_code_rate_t; - - -typedef enum fe_modulation { - QPSK, - QAM_16, - QAM_32, - QAM_64, - QAM_128, - QAM_256, - QAM_AUTO, - VSB_8, - VSB_16, - PSK_8, - APSK_16, - APSK_32, - DQPSK, - QAM_4_NR, -} fe_modulation_t; - -typedef enum fe_transmit_mode { - TRANSMISSION_MODE_2K, - TRANSMISSION_MODE_8K, - TRANSMISSION_MODE_AUTO, - TRANSMISSION_MODE_4K, - TRANSMISSION_MODE_1K, - TRANSMISSION_MODE_16K, - TRANSMISSION_MODE_32K, - TRANSMISSION_MODE_C1, - TRANSMISSION_MODE_C3780, -} fe_transmit_mode_t; - -#if defined(__DVB_CORE__) || !defined (__KERNEL__) -typedef enum fe_bandwidth { - BANDWIDTH_8_MHZ, - BANDWIDTH_7_MHZ, - BANDWIDTH_6_MHZ, - BANDWIDTH_AUTO, - BANDWIDTH_5_MHZ, - BANDWIDTH_10_MHZ, - BANDWIDTH_1_712_MHZ, -} fe_bandwidth_t; -#endif - -typedef enum fe_guard_interval { - GUARD_INTERVAL_1_32, - GUARD_INTERVAL_1_16, - GUARD_INTERVAL_1_8, - GUARD_INTERVAL_1_4, - GUARD_INTERVAL_AUTO, - GUARD_INTERVAL_1_128, - GUARD_INTERVAL_19_128, - GUARD_INTERVAL_19_256, - GUARD_INTERVAL_PN420, - GUARD_INTERVAL_PN595, - GUARD_INTERVAL_PN945, -} fe_guard_interval_t; - - -typedef enum fe_hierarchy { - HIERARCHY_NONE, - HIERARCHY_1, - HIERARCHY_2, - HIERARCHY_4, - HIERARCHY_AUTO -} fe_hierarchy_t; - -enum fe_interleaving { - INTERLEAVING_NONE, - INTERLEAVING_AUTO, - INTERLEAVING_240, - INTERLEAVING_720, -}; - -#if defined(__DVB_CORE__) || !defined (__KERNEL__) -struct dvb_qpsk_parameters { - __u32 symbol_rate; /* symbol rate in Symbols per second */ - fe_code_rate_t fec_inner; /* forward error correction (see above) */ -}; - -struct dvb_qam_parameters { - __u32 symbol_rate; /* symbol rate in Symbols per second */ - fe_code_rate_t fec_inner; /* forward error correction (see above) */ - fe_modulation_t modulation; /* modulation type (see above) */ -}; - -struct dvb_vsb_parameters { - fe_modulation_t modulation; /* modulation type (see above) */ -}; - -struct dvb_ofdm_parameters { - fe_bandwidth_t bandwidth; - fe_code_rate_t code_rate_HP; /* high priority stream code rate */ - fe_code_rate_t code_rate_LP; /* low priority stream code rate */ - fe_modulation_t constellation; /* modulation type (see above) */ - fe_transmit_mode_t transmission_mode; - fe_guard_interval_t guard_interval; - fe_hierarchy_t hierarchy_information; -}; - - -struct dvb_frontend_parameters { - __u32 frequency; /* (absolute) frequency in Hz for QAM/OFDM/ATSC */ - /* intermediate frequency in kHz for QPSK */ - fe_spectral_inversion_t inversion; - union { - struct dvb_qpsk_parameters qpsk; - struct dvb_qam_parameters qam; - struct dvb_ofdm_parameters ofdm; - struct dvb_vsb_parameters vsb; - } u; -}; - -struct dvb_frontend_event { - fe_status_t status; - struct dvb_frontend_parameters parameters; -}; -#endif - -/* S2API Commands */ -#define DTV_UNDEFINED 0 -#define DTV_TUNE 1 -#define DTV_CLEAR 2 -#define DTV_FREQUENCY 3 -#define DTV_MODULATION 4 -#define DTV_BANDWIDTH_HZ 5 -#define DTV_INVERSION 6 -#define DTV_DISEQC_MASTER 7 -#define DTV_SYMBOL_RATE 8 -#define DTV_INNER_FEC 9 -#define DTV_VOLTAGE 10 -#define DTV_TONE 11 -#define DTV_PILOT 12 -#define DTV_ROLLOFF 13 -#define DTV_DISEQC_SLAVE_REPLY 14 - -/* Basic enumeration set for querying unlimited capabilities */ -#define DTV_FE_CAPABILITY_COUNT 15 -#define DTV_FE_CAPABILITY 16 -#define DTV_DELIVERY_SYSTEM 17 - -/* ISDB-T and ISDB-Tsb */ -#define DTV_ISDBT_PARTIAL_RECEPTION 18 -#define DTV_ISDBT_SOUND_BROADCASTING 19 - -#define DTV_ISDBT_SB_SUBCHANNEL_ID 20 -#define DTV_ISDBT_SB_SEGMENT_IDX 21 -#define DTV_ISDBT_SB_SEGMENT_COUNT 22 - -#define DTV_ISDBT_LAYERA_FEC 23 -#define DTV_ISDBT_LAYERA_MODULATION 24 -#define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25 -#define DTV_ISDBT_LAYERA_TIME_INTERLEAVING 26 - -#define DTV_ISDBT_LAYERB_FEC 27 -#define DTV_ISDBT_LAYERB_MODULATION 28 -#define DTV_ISDBT_LAYERB_SEGMENT_COUNT 29 -#define DTV_ISDBT_LAYERB_TIME_INTERLEAVING 30 - -#define DTV_ISDBT_LAYERC_FEC 31 -#define DTV_ISDBT_LAYERC_MODULATION 32 -#define DTV_ISDBT_LAYERC_SEGMENT_COUNT 33 -#define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34 - -#define DTV_API_VERSION 35 - -#define DTV_CODE_RATE_HP 36 -#define DTV_CODE_RATE_LP 37 -#define DTV_GUARD_INTERVAL 38 -#define DTV_TRANSMISSION_MODE 39 -#define DTV_HIERARCHY 40 - -#define DTV_ISDBT_LAYER_ENABLED 41 - -#define DTV_STREAM_ID 42 -#define DTV_ISDBS_TS_ID_LEGACY DTV_STREAM_ID -#define DTV_DVBT2_PLP_ID_LEGACY 43 - -#define DTV_ENUM_DELSYS 44 - -/* ATSC-MH */ -#define DTV_ATSCMH_FIC_VER 45 -#define DTV_ATSCMH_PARADE_ID 46 -#define DTV_ATSCMH_NOG 47 -#define DTV_ATSCMH_TNOG 48 -#define DTV_ATSCMH_SGN 49 -#define DTV_ATSCMH_PRC 50 -#define DTV_ATSCMH_RS_FRAME_MODE 51 -#define DTV_ATSCMH_RS_FRAME_ENSEMBLE 52 -#define DTV_ATSCMH_RS_CODE_MODE_PRI 53 -#define DTV_ATSCMH_RS_CODE_MODE_SEC 54 -#define DTV_ATSCMH_SCCC_BLOCK_MODE 55 -#define DTV_ATSCMH_SCCC_CODE_MODE_A 56 -#define DTV_ATSCMH_SCCC_CODE_MODE_B 57 -#define DTV_ATSCMH_SCCC_CODE_MODE_C 58 -#define DTV_ATSCMH_SCCC_CODE_MODE_D 59 - -#define DTV_INTERLEAVING 60 -#define DTV_LNA 61 - -/* Quality parameters */ -#define DTV_STAT_SIGNAL_STRENGTH 62 -#define DTV_STAT_CNR 63 -#define DTV_STAT_PRE_ERROR_BIT_COUNT 64 -#define DTV_STAT_PRE_TOTAL_BIT_COUNT 65 -#define DTV_STAT_POST_ERROR_BIT_COUNT 66 -#define DTV_STAT_POST_TOTAL_BIT_COUNT 67 -#define DTV_STAT_ERROR_BLOCK_COUNT 68 -#define DTV_STAT_TOTAL_BLOCK_COUNT 69 - -#define DTV_MAX_COMMAND DTV_STAT_TOTAL_BLOCK_COUNT - -typedef enum fe_pilot { - PILOT_ON, - PILOT_OFF, - PILOT_AUTO, -} fe_pilot_t; - -typedef enum fe_rolloff { - ROLLOFF_35, /* Implied value in DVB-S, default for DVB-S2 */ - ROLLOFF_20, - ROLLOFF_25, - ROLLOFF_AUTO, -} fe_rolloff_t; - -typedef enum fe_delivery_system { - SYS_UNDEFINED, - SYS_DVBC_ANNEX_A, - SYS_DVBC_ANNEX_B, - SYS_DVBT, - SYS_DSS, - SYS_DVBS, - SYS_DVBS2, - SYS_DVBH, - SYS_ISDBT, - SYS_ISDBS, - SYS_ISDBC, - SYS_ATSC, - SYS_ATSCMH, - SYS_DTMB, - SYS_CMMB, - SYS_DAB, - SYS_DVBT2, - SYS_TURBO, - SYS_DVBC_ANNEX_C, - SYS_DVBC2, -} fe_delivery_system_t; - -/* backward compatibility */ -#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A -#define SYS_DMBTH SYS_DTMB /* DMB-TH is legacy name, use DTMB instead */ - -/* ATSC-MH */ - -enum atscmh_sccc_block_mode { - ATSCMH_SCCC_BLK_SEP = 0, - ATSCMH_SCCC_BLK_COMB = 1, - ATSCMH_SCCC_BLK_RES = 2, -}; - -enum atscmh_sccc_code_mode { - ATSCMH_SCCC_CODE_HLF = 0, - ATSCMH_SCCC_CODE_QTR = 1, - ATSCMH_SCCC_CODE_RES = 2, -}; - -enum atscmh_rs_frame_ensemble { - ATSCMH_RSFRAME_ENS_PRI = 0, - ATSCMH_RSFRAME_ENS_SEC = 1, -}; - -enum atscmh_rs_frame_mode { - ATSCMH_RSFRAME_PRI_ONLY = 0, - ATSCMH_RSFRAME_PRI_SEC = 1, - ATSCMH_RSFRAME_RES = 2, -}; - -enum atscmh_rs_code_mode { - ATSCMH_RSCODE_211_187 = 0, - ATSCMH_RSCODE_223_187 = 1, - ATSCMH_RSCODE_235_187 = 2, - ATSCMH_RSCODE_RES = 3, -}; - -#define NO_STREAM_ID_FILTER (~0U) -#define LNA_AUTO (~0U) - -struct dtv_cmds_h { - char *name; /* A display name for debugging purposes */ - - __u32 cmd; /* A unique ID */ - - /* Flags */ - __u32 set:1; /* Either a set or get property */ - __u32 buffer:1; /* Does this property use the buffer? */ - __u32 reserved:30; /* Align */ -}; - -/** - * Scale types for the quality parameters. - * @FE_SCALE_NOT_AVAILABLE: That QoS measure is not available. That - * could indicate a temporary or a permanent - * condition. - * @FE_SCALE_DECIBEL: The scale is measured in 0.0001 dB steps, typically - * used on signal measures. - * @FE_SCALE_RELATIVE: The scale is a relative percentual measure, - * ranging from 0 (0%) to 0xffff (100%). - * @FE_SCALE_COUNTER: The scale counts the occurrence of an event, like - * bit error, block error, lapsed time. - */ -enum fecap_scale_params { - FE_SCALE_NOT_AVAILABLE = 0, - FE_SCALE_DECIBEL, - FE_SCALE_RELATIVE, - FE_SCALE_COUNTER -}; - -/** - * struct dtv_stats - Used for reading a DTV status property - * - * @value: value of the measure. Should range from 0 to 0xffff; - * @scale: Filled with enum fecap_scale_params - the scale - * in usage for that parameter - * - * For most delivery systems, this will return a single value for each - * parameter. - * It should be noticed, however, that new OFDM delivery systems like - * ISDB can use different modulation types for each group of carriers. - * On such standards, up to 8 groups of statistics can be provided, one - * for each carrier group (called "layer" on ISDB). - * In order to be consistent with other delivery systems, the first - * value refers to the entire set of carriers ("global"). - * dtv_status:scale should use the value FE_SCALE_NOT_AVAILABLE when - * the value for the entire group of carriers or from one specific layer - * is not provided by the hardware. - * st.len should be filled with the latest filled status + 1. - * - * In other words, for ISDB, those values should be filled like: - * u.st.stat.svalue[0] = global statistics; - * u.st.stat.scale[0] = FE_SCALE_DECIBELS; - * u.st.stat.value[1] = layer A statistics; - * u.st.stat.scale[1] = FE_SCALE_NOT_AVAILABLE (if not available); - * u.st.stat.svalue[2] = layer B statistics; - * u.st.stat.scale[2] = FE_SCALE_DECIBELS; - * u.st.stat.svalue[3] = layer C statistics; - * u.st.stat.scale[3] = FE_SCALE_DECIBELS; - * u.st.len = 4; - */ -struct dtv_stats { - __u8 scale; /* enum fecap_scale_params type */ - union { - __u64 uvalue; /* for counters and relative scales */ - __s64 svalue; /* for 0.0001 dB measures */ - }; -} __attribute__ ((packed)); - - -#define MAX_DTV_STATS 4 - -struct dtv_fe_stats { - __u8 len; - struct dtv_stats stat[MAX_DTV_STATS]; -} __attribute__ ((packed)); - -struct dtv_property { - __u32 cmd; - __u32 reserved[3]; - union { - __u32 data; - struct dtv_fe_stats st; - struct { - __u8 data[32]; - __u32 len; - __u32 reserved1[3]; - void *reserved2; - } buffer; - } u; - int result; -} __attribute__ ((packed)); - -/* num of properties cannot exceed DTV_IOCTL_MAX_MSGS per ioctl */ -#define DTV_IOCTL_MAX_MSGS 64 - -struct dtv_properties { - __u32 num; - struct dtv_property *props; -}; - -#define FE_SET_PROPERTY _IOW('o', 82, struct dtv_properties) -#define FE_GET_PROPERTY _IOR('o', 83, struct dtv_properties) - - -/** - * When set, this flag will disable any zigzagging or other "normal" tuning - * behaviour. Additionally, there will be no automatic monitoring of the lock - * status, and hence no frontend events will be generated. If a frontend device - * is closed, this flag will be automatically turned off when the device is - * reopened read-write. - */ -#define FE_TUNE_MODE_ONESHOT 0x01 - - -#define FE_GET_INFO _IOR('o', 61, struct dvb_frontend_info) - -#define FE_DISEQC_RESET_OVERLOAD _IO('o', 62) -#define FE_DISEQC_SEND_MASTER_CMD _IOW('o', 63, struct dvb_diseqc_master_cmd) -#define FE_DISEQC_RECV_SLAVE_REPLY _IOR('o', 64, struct dvb_diseqc_slave_reply) -#define FE_DISEQC_SEND_BURST _IO('o', 65) /* fe_sec_mini_cmd_t */ - -#define FE_SET_TONE _IO('o', 66) /* fe_sec_tone_mode_t */ -#define FE_SET_VOLTAGE _IO('o', 67) /* fe_sec_voltage_t */ -#define FE_ENABLE_HIGH_LNB_VOLTAGE _IO('o', 68) /* int */ - -#define FE_READ_STATUS _IOR('o', 69, fe_status_t) -#define FE_READ_BER _IOR('o', 70, __u32) -#define FE_READ_SIGNAL_STRENGTH _IOR('o', 71, __u16) -#define FE_READ_SNR _IOR('o', 72, __u16) -#define FE_READ_UNCORRECTED_BLOCKS _IOR('o', 73, __u32) - -#define FE_SET_FRONTEND _IOW('o', 76, struct dvb_frontend_parameters) -#define FE_GET_FRONTEND _IOR('o', 77, struct dvb_frontend_parameters) -#define FE_SET_FRONTEND_TUNE_MODE _IO('o', 81) /* unsigned int */ -#define FE_GET_EVENT _IOR('o', 78, struct dvb_frontend_event) - -#define FE_DISHNETWORK_SEND_LEGACY_CMD _IO('o', 80) /* unsigned int */ - -#endif /*_DVBFRONTEND_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/mod.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/mod.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/mod.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/mod.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,23 +0,0 @@ -#ifndef _UAPI_DVBMOD_H_ -#define _UAPI_DVBMOD_H_ - -#include -#include "frontend.h" - -struct dvb_mod_params { - __u32 base_frequency; - __u32 attenuator; -}; - -struct dvb_mod_channel_params { - enum fe_modulation modulation; - - __u32 rate_increment; - -}; - - -#define DVB_MOD_SET _IOW('o', 208, struct dvb_mod_params) -#define DVB_MOD_CHANNEL_SET _IOW('o', 209, struct dvb_mod_channel_params) - -#endif /*_UAPI_DVBMOD_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/net.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/net.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/net.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/net.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,52 +0,0 @@ -/* - * net.h - * - * Copyright (C) 2000 Marcus Metzler - * & Ralph Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVBNET_H_ -#define _DVBNET_H_ - -#include - -struct dvb_net_if { - __u16 pid; - __u16 if_num; - __u8 feedtype; -#define DVB_NET_FEEDTYPE_MPE 0 /* multi protocol encapsulation */ -#define DVB_NET_FEEDTYPE_ULE 1 /* ultra lightweight encapsulation */ -}; - - -#define NET_ADD_IF _IOWR('o', 52, struct dvb_net_if) -#define NET_REMOVE_IF _IO('o', 53) -#define NET_GET_IF _IOWR('o', 54, struct dvb_net_if) - - -/* binary compatibility cruft: */ -struct __dvb_net_if_old { - __u16 pid; - __u16 if_num; -}; -#define __NET_ADD_IF_OLD _IOWR('o', 52, struct __dvb_net_if_old) -#define __NET_GET_IF_OLD _IOWR('o', 54, struct __dvb_net_if_old) - - -#endif /*_DVBNET_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ns.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ns.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ns.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/ns.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,68 +0,0 @@ -#ifndef _UAPI_DVBNS_H_ -#define _UAPI_DVBNS_H_ - -#include - -struct dvb_ns_params { - __u8 smac[6]; - __u8 dmac[6]; - __u8 sip[16]; - __u8 dip[16]; - __u16 sport; - __u16 dport; - __u16 sport2; - __u16 dport2; - __u8 ssrc[8]; - __u8 flags; - __u8 qos; - __u16 vlan; - __u8 ttl; -}; - -#define DVB_NS_IPV6 1 -#define DVB_NS_RTP 2 -#define DVB_NS_RTCP 4 -#define DVB_NS_RTP_TO 8 - -struct dvb_ns_rtcp { - __u8 *msg; - __u16 len; -}; - -struct dvb_ns_packet { - __u8 *buf; - __u8 count; -}; - -struct dvb_nsd_ts { - __u16 pid; - __u16 num; - __u16 input; - __u16 timeout; - __u16 len; - __u8 *ts; - __u8 mode; - __u8 table; - - __u8 filter_mask; - __u8 section; - __u16 section_id; -}; - -#define NS_SET_NET _IOW('o', 192, struct dvb_ns_params) -#define NS_START _IO('o', 193) -#define NS_STOP _IO('o', 194) -#define NS_SET_PID _IOW('o', 195, __u16) -#define NS_SET_PIDS _IOW('o', 196, __u8 *) -#define NS_SET_RTCP_MSG _IOW('o', 197, struct dvb_ns_rtcp) - -#define NSD_START_GET_TS _IOWR('o', 198, struct dvb_nsd_ts) -#define NSD_STOP_GET_TS _IOWR('o', 199, struct dvb_nsd_ts) -#define NSD_CANCEL_GET_TS _IO('o', 200) -#define NSD_POLL_GET_TS _IOWR('o', 201, struct dvb_nsd_ts) - -#define NS_SET_PACKETS _IOW('o', 202, struct dvb_ns_packet) -#define NS_INSERT_PACKETS _IOW('o', 203, __u8) -#define NS_SET_CI _IOW('o', 204, __u8) - -#endif /*_UAPI_DVBNS_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/osd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/osd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/osd.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/osd.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,144 +0,0 @@ -/* - * osd.h - * - * Copyright (C) 2001 Ralph Metzler - * & Marcus Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Lesser Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVBOSD_H_ -#define _DVBOSD_H_ - -#include - -typedef enum { - // All functions return -2 on "not open" - OSD_Close=1, // () - // Disables OSD and releases the buffers - // returns 0 on success - OSD_Open, // (x0,y0,x1,y1,BitPerPixel[2/4/8](color&0x0F),mix[0..15](color&0xF0)) - // Opens OSD with this size and bit depth - // returns 0 on success, -1 on DRAM allocation error, -2 on "already open" - OSD_Show, // () - // enables OSD mode - // returns 0 on success - OSD_Hide, // () - // disables OSD mode - // returns 0 on success - OSD_Clear, // () - // Sets all pixel to color 0 - // returns 0 on success - OSD_Fill, // (color) - // Sets all pixel to color - // returns 0 on success - OSD_SetColor, // (color,R{x0},G{y0},B{x1},opacity{y1}) - // set palette entry to , and apply - // R,G,B: 0..255 - // R=Red, G=Green, B=Blue - // opacity=0: pixel opacity 0% (only video pixel shows) - // opacity=1..254: pixel opacity as specified in header - // opacity=255: pixel opacity 100% (only OSD pixel shows) - // returns 0 on success, -1 on error - OSD_SetPalette, // (firstcolor{color},lastcolor{x0},data) - // Set a number of entries in the palette - // sets the entries "firstcolor" through "lastcolor" from the array "data" - // data has 4 byte for each color: - // R,G,B, and a opacity value: 0->transparent, 1..254->mix, 255->pixel - OSD_SetTrans, // (transparency{color}) - // Sets transparency of mixed pixel (0..15) - // returns 0 on success - OSD_SetPixel, // (x0,y0,color) - // sets pixel , to color number - // returns 0 on success, -1 on error - OSD_GetPixel, // (x0,y0) - // returns color number of pixel ,, or -1 - OSD_SetRow, // (x0,y0,x1,data) - // fills pixels x0,y through x1,y with the content of data[] - // returns 0 on success, -1 on clipping all pixel (no pixel drawn) - OSD_SetBlock, // (x0,y0,x1,y1,increment{color},data) - // fills pixels x0,y0 through x1,y1 with the content of data[] - // inc contains the width of one line in the data block, - // inc<=0 uses blockwidth as linewidth - // returns 0 on success, -1 on clipping all pixel - OSD_FillRow, // (x0,y0,x1,color) - // fills pixels x0,y through x1,y with the color - // returns 0 on success, -1 on clipping all pixel - OSD_FillBlock, // (x0,y0,x1,y1,color) - // fills pixels x0,y0 through x1,y1 with the color - // returns 0 on success, -1 on clipping all pixel - OSD_Line, // (x0,y0,x1,y1,color) - // draw a line from x0,y0 to x1,y1 with the color - // returns 0 on success - OSD_Query, // (x0,y0,x1,y1,xasp{color}}), yasp=11 - // fills parameters with the picture dimensions and the pixel aspect ratio - // returns 0 on success - OSD_Test, // () - // draws a test picture. for debugging purposes only - // returns 0 on success -// TODO: remove "test" in final version - OSD_Text, // (x0,y0,size,color,text) - OSD_SetWindow, // (x0) set window with number 0 - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _DVBVERSION_H_ -#define _DVBVERSION_H_ - -#define DVB_API_VERSION 5 -#define DVB_API_VERSION_MINOR 10 - -#endif /*_DVBVERSION_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/video.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/video.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/video.h 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/include/linux/dvb/video.h 1970-01-01 00:00:00.000000000 +0000 @@ -1,274 +0,0 @@ -/* - * video.h - * - * Copyright (C) 2000 Marcus Metzler - * & Ralph Metzler - * for convergence integrated media GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -#ifndef _UAPI_DVBVIDEO_H_ -#define _UAPI_DVBVIDEO_H_ - -#include -#ifndef __KERNEL__ -#include -#include -#endif - -typedef enum { - VIDEO_FORMAT_4_3, /* Select 4:3 format */ - VIDEO_FORMAT_16_9, /* Select 16:9 format. */ - VIDEO_FORMAT_221_1 /* 2.21:1 */ -} video_format_t; - - -typedef enum { - VIDEO_SYSTEM_PAL, - VIDEO_SYSTEM_NTSC, - VIDEO_SYSTEM_PALN, - VIDEO_SYSTEM_PALNc, - VIDEO_SYSTEM_PALM, - VIDEO_SYSTEM_NTSC60, - VIDEO_SYSTEM_PAL60, - VIDEO_SYSTEM_PALM60 -} video_system_t; - - -typedef enum { - VIDEO_PAN_SCAN, /* use pan and scan format */ - VIDEO_LETTER_BOX, /* use letterbox format */ - VIDEO_CENTER_CUT_OUT /* use center cut out format */ -} video_displayformat_t; - -typedef struct { - int w; - int h; - video_format_t aspect_ratio; -} video_size_t; - -typedef enum { - VIDEO_SOURCE_DEMUX, /* Select the demux as the main source */ - VIDEO_SOURCE_MEMORY /* If this source is selected, the stream - comes from the user through the write - system call */ -} video_stream_source_t; - - -typedef enum { - VIDEO_STOPPED, /* Video is stopped */ - VIDEO_PLAYING, /* Video is currently playing */ - VIDEO_FREEZED /* Video is freezed */ -} video_play_state_t; - - -/* Decoder commands */ -#define VIDEO_CMD_PLAY (0) -#define VIDEO_CMD_STOP (1) -#define VIDEO_CMD_FREEZE (2) -#define VIDEO_CMD_CONTINUE (3) - -/* Flags for VIDEO_CMD_FREEZE */ -#define VIDEO_CMD_FREEZE_TO_BLACK (1 << 0) - -/* Flags for VIDEO_CMD_STOP */ -#define VIDEO_CMD_STOP_TO_BLACK (1 << 0) -#define VIDEO_CMD_STOP_IMMEDIATELY (1 << 1) - -/* Play input formats: */ -/* The decoder has no special format requirements */ -#define VIDEO_PLAY_FMT_NONE (0) -/* The decoder requires full GOPs */ -#define VIDEO_PLAY_FMT_GOP (1) - -/* The structure must be zeroed before use by the application - This ensures it can be extended safely in the future. */ -struct video_command { - __u32 cmd; - __u32 flags; - union { - struct { - __u64 pts; - } stop; - - struct { - /* 0 or 1000 specifies normal speed, - 1 specifies forward single stepping, - -1 specifies backward single stepping, - >1: playback at speed/1000 of the normal speed, - <-1: reverse playback at (-speed/1000) of the normal speed. */ - __s32 speed; - __u32 format; - } play; - - struct { - __u32 data[16]; - } raw; - }; -}; - -/* FIELD_UNKNOWN can be used if the hardware does not know whether - the Vsync is for an odd, even or progressive (i.e. non-interlaced) - field. */ -#define VIDEO_VSYNC_FIELD_UNKNOWN (0) -#define VIDEO_VSYNC_FIELD_ODD (1) -#define VIDEO_VSYNC_FIELD_EVEN (2) -#define VIDEO_VSYNC_FIELD_PROGRESSIVE (3) - -struct video_event { - __s32 type; -#define VIDEO_EVENT_SIZE_CHANGED 1 -#define VIDEO_EVENT_FRAME_RATE_CHANGED 2 -#define VIDEO_EVENT_DECODER_STOPPED 3 -#define VIDEO_EVENT_VSYNC 4 - __kernel_time_t timestamp; - union { - video_size_t size; - unsigned int frame_rate; /* in frames per 1000sec */ - unsigned char vsync_field; /* unknown/odd/even/progressive */ - } u; -}; - - -struct video_status { - int video_blank; /* blank video on freeze? */ - video_play_state_t play_state; /* current state of playback */ - video_stream_source_t stream_source; /* current source (demux/memory) */ - video_format_t video_format; /* current aspect ratio of stream*/ - video_displayformat_t display_format;/* selected cropping mode */ -}; - - -struct video_still_picture { - char __user *iFrame; /* pointer to a single iframe in memory */ - __s32 size; -}; - - -typedef -struct video_highlight { - int active; /* 1=show highlight, 0=hide highlight */ - __u8 contrast1; /* 7- 4 Pattern pixel contrast */ - /* 3- 0 Background pixel contrast */ - __u8 contrast2; /* 7- 4 Emphasis pixel-2 contrast */ - /* 3- 0 Emphasis pixel-1 contrast */ - __u8 color1; /* 7- 4 Pattern pixel color */ - /* 3- 0 Background pixel color */ - __u8 color2; /* 7- 4 Emphasis pixel-2 color */ - /* 3- 0 Emphasis pixel-1 color */ - __u32 ypos; /* 23-22 auto action mode */ - /* 21-12 start y */ - /* 9- 0 end y */ - __u32 xpos; /* 23-22 button color number */ - /* 21-12 start x */ - /* 9- 0 end x */ -} video_highlight_t; - - -typedef struct video_spu { - int active; - int stream_id; -} video_spu_t; - - -typedef struct video_spu_palette { /* SPU Palette information */ - int length; - __u8 __user *palette; -} video_spu_palette_t; - - -typedef struct video_navi_pack { - int length; /* 0 ... 1024 */ - __u8 data[1024]; -} video_navi_pack_t; - - -typedef __u16 video_attributes_t; -/* bits: descr. */ -/* 15-14 Video compression mode (0=MPEG-1, 1=MPEG-2) */ -/* 13-12 TV system (0=525/60, 1=625/50) */ -/* 11-10 Aspect ratio (0=4:3, 3=16:9) */ -/* 9- 8 permitted display mode on 4:3 monitor (0=both, 1=only pan-sca */ -/* 7 line 21-1 data present in GOP (1=yes, 0=no) */ -/* 6 line 21-2 data present in GOP (1=yes, 0=no) */ -/* 5- 3 source resolution (0=720x480/576, 1=704x480/576, 2=352x480/57 */ -/* 2 source letterboxed (1=yes, 0=no) */ -/* 0 film/camera mode (0=camera, 1=film (625/50 only)) */ - - -/* bit definitions for capabilities: */ -/* can the hardware decode MPEG1 and/or MPEG2? */ -#define VIDEO_CAP_MPEG1 1 -#define VIDEO_CAP_MPEG2 2 -/* can you send a system and/or program stream to video device? - (you still have to open the video and the audio device but only - send the stream to the video device) */ -#define VIDEO_CAP_SYS 4 -#define VIDEO_CAP_PROG 8 -/* can the driver also handle SPU, NAVI and CSS encoded data? - (CSS API is not present yet) */ -#define VIDEO_CAP_SPU 16 -#define VIDEO_CAP_NAVI 32 -#define VIDEO_CAP_CSS 64 - - -#define VIDEO_STOP _IO('o', 21) -#define VIDEO_PLAY _IO('o', 22) -#define VIDEO_FREEZE _IO('o', 23) -#define VIDEO_CONTINUE _IO('o', 24) -#define VIDEO_SELECT_SOURCE _IO('o', 25) -#define VIDEO_SET_BLANK _IO('o', 26) -#define VIDEO_GET_STATUS _IOR('o', 27, struct video_status) -#define VIDEO_GET_EVENT _IOR('o', 28, struct video_event) -#define VIDEO_SET_DISPLAY_FORMAT _IO('o', 29) -#define VIDEO_STILLPICTURE _IOW('o', 30, struct video_still_picture) -#define VIDEO_FAST_FORWARD _IO('o', 31) -#define VIDEO_SLOWMOTION _IO('o', 32) -#define VIDEO_GET_CAPABILITIES _IOR('o', 33, unsigned int) -#define VIDEO_CLEAR_BUFFER _IO('o', 34) -#define VIDEO_SET_ID _IO('o', 35) -#define VIDEO_SET_STREAMTYPE _IO('o', 36) -#define VIDEO_SET_FORMAT _IO('o', 37) -#define VIDEO_SET_SYSTEM _IO('o', 38) -#define VIDEO_SET_HIGHLIGHT _IOW('o', 39, video_highlight_t) -#define VIDEO_SET_SPU _IOW('o', 50, video_spu_t) -#define VIDEO_SET_SPU_PALETTE _IOW('o', 51, video_spu_palette_t) -#define VIDEO_GET_NAVI _IOR('o', 52, video_navi_pack_t) -#define VIDEO_SET_ATTRIBUTES _IO('o', 53) -#define VIDEO_GET_SIZE _IOR('o', 55, video_size_t) -#define VIDEO_GET_FRAME_RATE _IOR('o', 56, unsigned int) - -/** - * VIDEO_GET_PTS - * - * Read the 33 bit presentation time stamp as defined - * in ITU T-REC-H.222.0 / ISO/IEC 13818-1. - * - * The PTS should belong to the currently played - * frame if possible, but may also be a value close to it - * like the PTS of the last decoded frame or the last PTS - * extracted by the PES parser. - */ -#define VIDEO_GET_PTS _IOR('o', 57, __u64) - -/* Read the number of displayed frames since the decoder was started */ -#define VIDEO_GET_FRAME_COUNT _IOR('o', 58, __u64) - -#define VIDEO_COMMAND _IOWR('o', 59, struct video_command) -#define VIDEO_TRY_COMMAND _IOWR('o', 60, struct video_command) - -#endif /* _UAPI_DVBVIDEO_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/ddbridge.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/ddbridge.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/ddbridge.diff 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/ddbridge.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,37 +0,0 @@ -diff -r 2cc595391006 a/ddbridge/ddbridge-core.c ---- a/ddbridge/ddbridge-core.c Tue Nov 05 08:03:36 2013 +0100 -+++ b/ddbridge/ddbridge-core.c Tue Nov 05 09:18:10 2013 +0100 -@@ -889,16 +889,19 @@ - return status; - } - --#ifdef CONFIG_DVB_DRXK -+#if IS_ENABLED(CONFIG_DVB_DRXK) - static int demod_attach_drxk(struct ddb_input *input) - { - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - struct dvb_frontend *fe; -- -- fe = dvb->fe = dvb_attach(drxk_attach, -- i2c, 0x29 + (input->nr&1), -- &dvb->fe2); -+ struct drxk_config config; -+ -+ memset(&config, 0, sizeof(config)); -+ config.adr = 0x29 + (input->nr & 1); -+ config.microcode_name = "drxk_a3.mc"; -+ -+ fe = dvb->fe = dvb_attach(drxk_attach, &config, i2c); - if (!fe) { - printk(KERN_ERR "No DRXK found!\n"); - return -ENODEV; -@@ -1442,7 +1445,7 @@ - if (tuner_attach_stv6110(input, 1) < 0) - return -ENODEV; - break; --#ifdef CONFIG_DVB_DRXK -+#if IS_ENABLED(CONFIG_DVB_DRXK) - case DDB_TUNER_DVBCT_TR: - if (demod_attach_drxk(input) < 0) - return -ENODEV; diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk.diff 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,31774 +0,0 @@ -diff --git a/frontends/drxk.h b/frontends/drxk.h -index 7d43cbb..9d64e4f 100644 ---- a/frontends/drxk.h -+++ b/frontends/drxk.h -@@ -1,10 +1,57 @@ --#ifndef _DRXK_H_ --#define _DRXK_H_ -- --#include --#include -- --extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, -- u8 adr, -- struct dvb_frontend **fe_t); --#endif -+#ifndef _DRXK_H_ -+#define _DRXK_H_ -+ -+#include -+#include -+ -+/** -+ * struct drxk_config - Configure the initial parameters for DRX-K -+ * -+ * @adr: I2C Address of the DRX-K -+ * @parallel_ts: True means that the device uses parallel TS, -+ * Serial otherwise. -+ * @dynamic_clk: True means that the clock will be dynamically -+ * adjusted. Static clock otherwise. -+ * @enable_merr_cfg: Enable SIO_PDR_PERR_CFG/SIO_PDR_MVAL_CFG. -+ * @single_master: Device is on the single master mode -+ * @no_i2c_bridge: Don't switch the I2C bridge to talk with tuner -+ * @antenna_gpio: GPIO bit used to control the antenna -+ * @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1 -+ * means that 1=DVBC, 0 = DVBT. Zero means the opposite. -+ * @mpeg_out_clk_strength: DRXK Mpeg output clock drive strength. -+ * @microcode_name: Name of the firmware file with the microcode -+ * -+ * On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is -+ * UIO-3. -+ */ -+struct drxk_config { -+ u8 adr; -+ bool single_master; -+ bool no_i2c_bridge; -+ bool parallel_ts; -+ bool dynamic_clk; -+ bool enable_merr_cfg; -+ -+ bool antenna_dvbt; -+ u16 antenna_gpio; -+ -+ u8 mpeg_out_clk_strength; -+ int chunk_size; -+ -+ const char *microcode_name; -+}; -+ -+#if defined(CONFIG_DVB_DRXK) || (defined(CONFIG_DVB_DRXK_MODULE) \ -+ && defined(MODULE)) -+extern struct dvb_frontend *drxk_attach(const struct drxk_config *config, -+ struct i2c_adapter *i2c); -+#else -+static inline struct dvb_frontend *drxk_attach(const struct drxk_config *config, -+ struct i2c_adapter *i2c) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+#endif -+ -+#endif -diff --git a/frontends/drxk_hard.c b/frontends/drxk_hard.c -index 53cb65b..60b868f 100644 ---- a/frontends/drxk_hard.c -+++ b/frontends/drxk_hard.c -@@ -1,5097 +1,6457 @@ --/* -- * drxk_hard: DRX-K DVB-C/T demodulator driver -- * -- * Copyright (C) 2010-2011 Digital Devices GmbH -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License -- * version 2 only, as published by the Free Software Foundation. -- * -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- * 02110-1301, USA -- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#include "dvb_frontend.h" --#include "drxk.h" --#include "drxk_hard.h" -- --static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); --static int PowerDownQAM(struct drxk_state *state); --static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); --static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode); --static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, -- s32 tunerFreqOffset); --static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); --static int DVBTStart(struct drxk_state *state); --static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, -- s32 tunerFreqOffset); --static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); --static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); --static int SwitchAntennaToQAM(struct drxk_state *state); --static int SwitchAntennaToDVBT(struct drxk_state *state); -- --static bool IsDVBT(struct drxk_state *state) --{ -- return state->m_OperationMode == OM_DVBT; --} -- --static bool IsQAM(struct drxk_state *state) --{ -- return state->m_OperationMode == OM_QAM_ITU_A || -- state->m_OperationMode == OM_QAM_ITU_B || -- state->m_OperationMode == OM_QAM_ITU_C; --} -- --bool IsA1WithPatchCode(struct drxk_state *state) --{ -- return state->m_DRXK_A1_PATCH_CODE; --} -- --bool IsA1WithRomCode(struct drxk_state *state) --{ -- return state->m_DRXK_A1_ROM_CODE; --} -- --#define NOA1ROM 0 -- --#ifndef CHK_ERROR -- #define CHK_ERROR(s) if ((status = s) < 0) break --#endif -- --#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) --#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) -- --#define DEFAULT_MER_83 165 --#define DEFAULT_MER_93 250 -- --#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH --#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) --#endif -- --#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH --#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) --#endif -- --#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH --#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06) --#endif -- --#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 --#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 -- --#ifndef DRXK_KI_RAGC_ATV --#define DRXK_KI_RAGC_ATV 4 --#endif --#ifndef DRXK_KI_IAGC_ATV --#define DRXK_KI_IAGC_ATV 6 --#endif --#ifndef DRXK_KI_DAGC_ATV --#define DRXK_KI_DAGC_ATV 7 --#endif -- --#ifndef DRXK_KI_RAGC_QAM --#define DRXK_KI_RAGC_QAM 3 --#endif --#ifndef DRXK_KI_IAGC_QAM --#define DRXK_KI_IAGC_QAM 4 --#endif --#ifndef DRXK_KI_DAGC_QAM --#define DRXK_KI_DAGC_QAM 7 --#endif --#ifndef DRXK_KI_RAGC_DVBT --#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) --#endif --#ifndef DRXK_KI_IAGC_DVBT --#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) --#endif --#ifndef DRXK_KI_DAGC_DVBT --#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) --#endif -- --#ifndef DRXK_AGC_DAC_OFFSET --#define DRXK_AGC_DAC_OFFSET (0x800) --#endif -- --#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ --#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) --#endif -- --#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ --#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) --#endif -- --#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ --#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) --#endif -- --#ifndef DRXK_QAM_SYMBOLRATE_MAX --#define DRXK_QAM_SYMBOLRATE_MAX (7233000) --#endif -- --#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 --#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 --#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 --#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 --#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 --#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 --#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 --#define DRXK_BL_ROM_OFFSET_UCODE 0 -- --#define DRXK_BLC_TIMEOUT 100 -- --#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 --#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 -- --#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 -- --#ifndef DRXK_OFDM_NE_NOTCH_WIDTH --#define DRXK_OFDM_NE_NOTCH_WIDTH (4) --#endif -- --#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) --#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) --#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) --#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) --#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) -- --static inline u32 MulDiv32(u32 a, u32 b, u32 c) --{ -- u64 tmp64; -- -- tmp64 = (u64)a * (u64)b; -- do_div(tmp64, c); -- -- return (u32) tmp64; --} -- --inline u32 Frac28a(u32 a, u32 c) --{ -- int i = 0; -- u32 Q1 = 0; -- u32 R0 = 0; -- -- R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ -- Q1 = a / c; /* integer part, only the 4 least significant bits -- will be visible in the result */ -- -- /* division using radix 16, 7 nibbles in the result */ -- for (i = 0; i < 7; i++) { -- Q1 = (Q1 << 4) | (R0 / c); -- R0 = (R0 % c) << 4; -- } -- /* rounding */ -- if ((R0 >> 3) >= c) -- Q1++; -- -- return Q1; --} -- --static u32 Log10Times100(u32 x) --{ -- static const u8 scale = 15; -- static const u8 indexWidth = 5; -- u8 i = 0; -- u32 y = 0; -- u32 d = 0; -- u32 k = 0; -- u32 r = 0; -- /* -- log2lut[n] = (1< 0; k--) { -- if (x & (((u32)1) << scale)) -- break; -- x <<= 1; -- } -- } else { -- for (k = scale; k < 31 ; k++) { -- if ((x & (((u32)(-1)) << (scale+1))) == 0) -- break; -- x >>= 1; -- } -- } -- /* -- Now x has binary point between bit[scale] and bit[scale-1] -- and 1.0 <= x < 2.0 */ -- -- /* correction for divison: log(x) = log(x/y)+log(y) */ -- y = k * ((((u32)1) << scale) * 200); -- -- /* remove integer part */ -- x &= ((((u32)1) << scale)-1); -- /* get index */ -- i = (u8) (x >> (scale - indexWidth)); -- /* compute delta (x - a) */ -- d = x & ((((u32)1) << (scale - indexWidth)) - 1); -- /* compute log, multiplication (d* (..)) must be within range ! */ -- y += log2lut[i] + -- ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); -- /* Conver to log10() */ -- y /= 108853; /* (log2(10) << scale) */ -- r = (y >> 1); -- /* rounding */ -- if (y & ((u32)1)) -- r++; -- return (r); --} -- --/****************************************************************************/ --/* I2C **********************************************************************/ --/****************************************************************************/ -- --static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) --{ -- struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, -- .buf = val, .len = 1 }}; -- return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; --} -- --static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) --{ -- struct i2c_msg msg = -- {.addr = adr, .flags = 0, .buf = data, .len = len}; -- -- if (i2c_transfer(adap, &msg, 1) != 1) { -- printk("i2c_write error\n"); -- return -1; -- } -- return 0; --} -- --static int i2c_read(struct i2c_adapter *adap, -- u8 adr, u8 *msg, int len, u8 *answ, int alen) --{ -- struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, -- .buf = msg, .len = len}, -- { .addr = adr, .flags = I2C_M_RD, -- .buf = answ, .len = alen } }; -- if (i2c_transfer(adap, msgs, 2) != 2) { -- printk("i2c_read error\n"); -- return -1; -- } -- return 0; --} -- --static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) --{ -- u8 adr=state->demod_address, mm1[4], mm2[2], len; --#ifdef I2C_LONG_ADR -- flags |= 0xC0; --#endif -- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -- mm1[0] = (((reg << 1) & 0xFF) | 0x01); -- mm1[1] = ((reg >> 16) & 0xFF); -- mm1[2] = ((reg >> 24) & 0xFF) | flags; -- mm1[3] = ((reg >> 7) & 0xFF); -- len = 4; -- } else { -- mm1[0] = ((reg << 1) & 0xFF); -- mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -- len = 2; -- } -- if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) -- return -1; -- if (data) -- *data = mm2[0] | (mm2[1] << 8); -- return 0; --} -- --static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) --{ -- return Read16(state, reg, data, 0); --} -- --static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) --{ -- u8 adr = state->demod_address, mm1[4], mm2[4], len; --#ifdef I2C_LONG_ADR -- flags |= 0xC0; --#endif -- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -- mm1[0] = (((reg << 1) & 0xFF) | 0x01); -- mm1[1] = ((reg >> 16) & 0xFF); -- mm1[2] = ((reg >> 24) & 0xFF) | flags; -- mm1[3] = ((reg >> 7) & 0xFF); -- len = 4; -- } else { -- mm1[0] = ((reg << 1) & 0xFF); -- mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -- len = 2; -- } -- if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) -- return -1; -- if (data) -- *data = mm2[0] | (mm2[1] << 8) | -- (mm2[2] << 16) | (mm2[3] << 24); -- return 0; --} -- --static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) --{ -- u8 adr = state->demod_address, mm[6], len; --#ifdef I2C_LONG_ADR -- flags |= 0xC0; --#endif -- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -- mm[0] = (((reg << 1) & 0xFF) | 0x01); -- mm[1] = ((reg >> 16) & 0xFF); -- mm[2] = ((reg >> 24) & 0xFF) | flags; -- mm[3] = ((reg >> 7) & 0xFF); -- len = 4; -- } else { -- mm[0] = ((reg << 1) & 0xFF); -- mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -- len = 2; -- } -- mm[len] = data & 0xff; -- mm[len+1] = (data >>8) & 0xff; -- if (i2c_write(state->i2c, adr, mm, len + 2) < 0) -- return -1; -- return 0; --} -- --static int Write16_0(struct drxk_state *state, u32 reg, u16 data) --{ -- return Write16(state, reg, data, 0); --} -- --static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) --{ -- u8 adr = state->demod_address, mm[8], len; --#ifdef I2C_LONG_ADR -- flags |= 0xC0; --#endif -- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -- mm[0] = (((reg << 1) & 0xFF) | 0x01); -- mm[1] = ((reg >> 16) & 0xFF); -- mm[2] = ((reg >> 24) & 0xFF) | flags; -- mm[3] = ((reg >> 7) & 0xFF); -- len = 4; -- } else { -- mm[0] = ((reg << 1) & 0xFF); -- mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -- len = 2; -- } -- mm[len] = data & 0xff; -- mm[len+1] = (data >> 8) & 0xff; -- mm[len+2] = (data >> 16) & 0xff; -- mm[len+3] = (data >> 24) & 0xff; -- if (i2c_write(state->i2c, adr, mm, len+4) < 0) -- return -1; -- return 0; --} -- --static int WriteBlock(struct drxk_state *state, u32 Address, -- const int BlockSize, const u8 pBlock[], u8 Flags) --{ -- int status = 0, BlkSize = BlockSize; --#ifdef I2C_LONG_ADR -- Flags |= 0xC0; --#endif -- while (BlkSize > 0) { -- int Chunk = BlkSize > state->m_ChunkSize ? -- state->m_ChunkSize : BlkSize ; -- u8 *AdrBuf = &state->Chunk[0]; -- u32 AdrLength = 0; -- -- if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { -- AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); -- AdrBuf[1] = ((Address >> 16) & 0xFF); -- AdrBuf[2] = ((Address >> 24) & 0xFF); -- AdrBuf[3] = ((Address >> 7) & 0xFF); -- AdrBuf[2] |= Flags; -- AdrLength = 4; -- if (Chunk == state->m_ChunkSize) -- Chunk -= 2; -- } else { -- AdrBuf[0] = ((Address << 1) & 0xFF); -- AdrBuf[1] = (((Address >> 16) & 0x0F) | -- ((Address >> 18) & 0xF0)); -- AdrLength = 2; -- } -- memcpy(&state->Chunk[AdrLength], pBlock, Chunk); -- status = i2c_write(state->i2c, state->demod_address, -- &state->Chunk[0], Chunk+AdrLength); -- if (status<0) { -- printk("I2C Write error\n"); -- break; -- } -- pBlock += Chunk; -- Address += (Chunk >> 1); -- BlkSize -= Chunk; -- } -- return status; --} -- --#ifndef DRXK_MAX_RETRIES_POWERUP --#define DRXK_MAX_RETRIES_POWERUP 20 --#endif -- --int PowerUpDevice(struct drxk_state *state) --{ -- int status; -- u8 data = 0; -- u16 retryCount = 0; -- -- status = i2c_read1(state->i2c, state->demod_address, &data); -- if (status<0) -- do { -- data = 0; -- if (i2c_write(state->i2c, -- state->demod_address, &data, 1) < 0) -- printk("powerup failed\n"); -- msleep(10); -- retryCount++ ; -- } while (i2c_read1(state->i2c, -- state->demod_address, &data) < 0 && -- (retryCount < DRXK_MAX_RETRIES_POWERUP)); -- if (retryCount >= DRXK_MAX_RETRIES_POWERUP) -- return -1; -- do { -- /* Make sure all clk domains are active */ -- CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, -- SIO_CC_PWD_MODE_LEVEL_NONE)); -- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, -- SIO_CC_UPDATE_KEY)); -- /* Enable pll lock tests */ -- CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); -- state->m_currentPowerMode = DRX_POWER_UP; -- } while (0); -- return status; --} -- -- --static int init_state(struct drxk_state *state) --{ -- u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; -- u32 ulVSBIfAgcOutputLevel = 0; -- u32 ulVSBIfAgcMinLevel = 0; -- u32 ulVSBIfAgcMaxLevel = 0x7FFF; -- u32 ulVSBIfAgcSpeed = 3; -- -- u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; -- u32 ulVSBRfAgcOutputLevel = 0; -- u32 ulVSBRfAgcMinLevel = 0; -- u32 ulVSBRfAgcMaxLevel = 0x7FFF; -- u32 ulVSBRfAgcSpeed = 3; -- u32 ulVSBRfAgcTop = 9500; -- u32 ulVSBRfAgcCutOffCurrent = 4000; -- -- u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; -- u32 ulATVIfAgcOutputLevel = 0; -- u32 ulATVIfAgcMinLevel = 0; -- u32 ulATVIfAgcMaxLevel = 0; -- u32 ulATVIfAgcSpeed = 3; -- -- u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; -- u32 ulATVRfAgcOutputLevel = 0; -- u32 ulATVRfAgcMinLevel = 0; -- u32 ulATVRfAgcMaxLevel = 0; -- u32 ulATVRfAgcTop = 9500; -- u32 ulATVRfAgcCutOffCurrent = 4000; -- u32 ulATVRfAgcSpeed = 3; -- -- u32 ulQual83 = DEFAULT_MER_83; -- u32 ulQual93 = DEFAULT_MER_93; -- -- u32 ulDVBTStaticTSClock = 1; -- u32 ulDVBCStaticTSClock = 1; -- -- u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -- u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; -- -- /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ -- /* io_pad_cfg_mode output mode is drive always */ -- /* io_pad_cfg_drive is set to power 2 (23 mA) */ -- u32 ulGPIOCfg = 0x0113; -- u32 ulGPIO = 0; -- u32 ulSerialMode = 1; -- u32 ulInvertTSClock = 0; -- u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; -- u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; -- u32 ulDVBTBitrate = 50000000; -- u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; -- -- u32 ulInsertRSByte = 0; -- -- u32 ulRfMirror = 1; -- u32 ulPowerDown = 0; -- -- u32 ulAntennaDVBT = 1; -- u32 ulAntennaDVBC = 0; -- u32 ulAntennaSwitchDVBTDVBC = 0; -- -- state->m_hasLNA = false; -- state->m_hasDVBT= false; -- state->m_hasDVBC= false; -- state->m_hasATV= false; -- state->m_hasOOB = false; -- state->m_hasAudio = false; -- -- state->m_ChunkSize = 124; -- -- state->m_oscClockFreq = 0; -- state->m_smartAntInverted = false; -- state->m_bPDownOpenBridge = false; -- -- /* real system clock frequency in kHz */ -- state->m_sysClockFreq = 151875; -- /* Timing div, 250ns/Psys */ -- /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ -- state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * -- HI_I2C_DELAY) / 1000; -- /* Clipping */ -- if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) -- state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; -- state->m_HICfgWakeUpKey = (state->demod_address << 1); -- /* port/bridge/power down ctrl */ -- state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; -- -- state->m_bPowerDown = (ulPowerDown != 0); -- -- state->m_DRXK_A1_PATCH_CODE = false; -- state->m_DRXK_A1_ROM_CODE = false; -- state->m_DRXK_A2_ROM_CODE = false; -- state->m_DRXK_A3_ROM_CODE = false; -- state->m_DRXK_A2_PATCH_CODE = false; -- state->m_DRXK_A3_PATCH_CODE = false; -- -- /* Init AGC and PGA parameters */ -- /* VSB IF */ -- state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); -- state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); -- state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); -- state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); -- state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); -- state->m_vsbPgaCfg = 140; -- -- /* VSB RF */ -- state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); -- state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); -- state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); -- state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); -- state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); -- state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); -- state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); -- state->m_vsbPreSawCfg.reference = 0x07; -- state->m_vsbPreSawCfg.usePreSaw = true; -- -- state->m_Quality83percent = DEFAULT_MER_83; -- state->m_Quality93percent = DEFAULT_MER_93; -- if (ulQual93 <= 500 && ulQual83 < ulQual93) { -- state->m_Quality83percent = ulQual83; -- state->m_Quality93percent = ulQual93; -- } -- -- /* ATV IF */ -- state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); -- state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); -- state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); -- state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); -- state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); -- -- /* ATV RF */ -- state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); -- state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); -- state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); -- state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); -- state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); -- state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); -- state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); -- state->m_atvPreSawCfg.reference = 0x04; -- state->m_atvPreSawCfg.usePreSaw = true; -- -- -- /* DVBT RF */ -- state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; -- state->m_dvbtRfAgcCfg.outputLevel = 0; -- state->m_dvbtRfAgcCfg.minOutputLevel = 0; -- state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; -- state->m_dvbtRfAgcCfg.top = 0x2100; -- state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; -- state->m_dvbtRfAgcCfg.speed = 1; -- -- -- /* DVBT IF */ -- state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; -- state->m_dvbtIfAgcCfg.outputLevel = 0; -- state->m_dvbtIfAgcCfg.minOutputLevel = 0; -- state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; -- state->m_dvbtIfAgcCfg.top = 13424; -- state->m_dvbtIfAgcCfg.cutOffCurrent = 0; -- state->m_dvbtIfAgcCfg.speed = 3; -- state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; -- state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; -- // state->m_dvbtPgaCfg = 140; -- -- state->m_dvbtPreSawCfg.reference = 4; -- state->m_dvbtPreSawCfg.usePreSaw = false; -- -- /* QAM RF */ -- state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; -- state->m_qamRfAgcCfg.outputLevel = 0; -- state->m_qamRfAgcCfg.minOutputLevel = 6023; -- state->m_qamRfAgcCfg.maxOutputLevel = 27000; -- state->m_qamRfAgcCfg.top = 0x2380; -- state->m_qamRfAgcCfg.cutOffCurrent = 4000; -- state->m_qamRfAgcCfg.speed = 3; -- -- /* QAM IF */ -- state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; -- state->m_qamIfAgcCfg.outputLevel = 0; -- state->m_qamIfAgcCfg.minOutputLevel = 0; -- state->m_qamIfAgcCfg.maxOutputLevel = 9000; -- state->m_qamIfAgcCfg.top = 0x0511; -- state->m_qamIfAgcCfg.cutOffCurrent = 0; -- state->m_qamIfAgcCfg.speed = 3; -- state->m_qamIfAgcCfg.IngainTgtMax = 5119; -- state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; -- -- state->m_qamPgaCfg = 140; -- state->m_qamPreSawCfg.reference = 4; -- state->m_qamPreSawCfg.usePreSaw = false; -- -- state->m_OperationMode = OM_NONE; -- state->m_DrxkState = DRXK_UNINITIALIZED; -- -- /* MPEG output configuration */ -- state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ -- state->m_insertRSByte = false; /* If TRUE; insert RS byte */ -- state->m_enableParallel = true; /* If TRUE; -- parallel out otherwise serial */ -- state->m_invertDATA = false; /* If TRUE; invert DATA signals */ -- state->m_invertERR = false; /* If TRUE; invert ERR signal */ -- state->m_invertSTR = false; /* If TRUE; invert STR signals */ -- state->m_invertVAL = false; /* If TRUE; invert VAL signals */ -- state->m_invertCLK = -- (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ -- state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); -- state->m_DVBCStaticCLK = -- (ulDVBCStaticTSClock != 0); -- /* If TRUE; static MPEG clockrate will be used; -- otherwise clockrate will adapt to the bitrate of the TS */ -- -- state->m_DVBTBitrate = ulDVBTBitrate; -- state->m_DVBCBitrate = ulDVBCBitrate; -- -- state->m_TSDataStrength = (ulTSDataStrength & 0x07); -- state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); -- -- /* Maximum bitrate in b/s in case static clockrate is selected */ -- state->m_mpegTsStaticBitrate = 19392658; -- state->m_disableTEIhandling = false; -- -- if (ulInsertRSByte) -- state->m_insertRSByte = true; -- -- state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -- if (ulMpegLockTimeOut < 10000) -- state->m_MpegLockTimeOut = ulMpegLockTimeOut; -- state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; -- if (ulDemodLockTimeOut < 10000) -- state->m_DemodLockTimeOut = ulDemodLockTimeOut; -- -- // QAM defaults -- state->m_Constellation = DRX_CONSTELLATION_AUTO; -- state->m_qamInterleaveMode = DRXK_QAM_I12_J17; -- state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/ -- state->m_fecRsPrescale = 1; -- -- state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; -- state->m_agcFastClipCtrlDelay = 0; -- -- state->m_GPIOCfg = (ulGPIOCfg); -- state->m_GPIO = (ulGPIO == 0 ? 0 : 1); -- -- state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1); -- state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1); -- state->m_AntennaSwitchDVBTDVBC = -- (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1); -- -- state->m_bPowerDown = false; -- state->m_currentPowerMode = DRX_POWER_DOWN; -- -- state->m_enableParallel = (ulSerialMode == 0); -- -- state->m_rfmirror = (ulRfMirror == 0); -- state->m_IfAgcPol = false; -- return 0; --} -- --static int DRXX_Open(struct drxk_state *state) --{ -- int status = 0; -- u32 jtag = 0; -- u16 bid = 0; -- u16 key = 0; -- -- do { -- /* stop lock indicator process */ -- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); -- /* Check device id */ -- CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, -- SIO_TOP_COMM_KEY_KEY)); -- CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); -- CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); -- } while(0); -- return status; --} -- --static int GetDeviceCapabilities(struct drxk_state *state) --{ -- u16 sioPdrOhwCfg = 0; -- u32 sioTopJtagidLo = 0; -- int status; -- -- do { -- /* driver 0.9.0 */ -- /* stop lock indicator process */ -- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); -- -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); -- CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); -- -- switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { -- case 0: -- /* ignore (bypass ?) */ -- break; -- case 1: -- /* 27 MHz */ -- state->m_oscClockFreq = 27000; -- break; -- case 2: -- /* 20.25 MHz */ -- state->m_oscClockFreq = 20250; -- break; -- case 3: -- /* 4 MHz */ -- state->m_oscClockFreq = 20250; -- break; -- default: -- return -1; -- } -- /* -- Determine device capabilities -- Based on pinning v14 -- */ -- CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, -- &sioTopJtagidLo, 0)); -- /* driver 0.9.0 */ -- switch((sioTopJtagidLo >> 29) & 0xF) { -- case 0: -- state->m_deviceSpin = DRXK_SPIN_A1; -- break; -- case 2: -- state->m_deviceSpin = DRXK_SPIN_A2; -- break; -- case 3: -- state->m_deviceSpin = DRXK_SPIN_A3; -- break; -- default: -- state->m_deviceSpin = DRXK_SPIN_UNKNOWN; -- status = -1; -- break; -- } -- switch ((sioTopJtagidLo>>12)&0xFF) { -- case 0x13: -- /* typeId = DRX3913K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = false; -- state->m_hasAudio = false; -- state->m_hasDVBT = true; -- state->m_hasDVBC = true; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = false; -- state->m_hasGPIO1 = false; -- state->m_hasIRQN = false; -- break; -- case 0x15: -- /* typeId = DRX3915K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = true; -- state->m_hasAudio = false; -- state->m_hasDVBT = true; -- state->m_hasDVBC = false; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = true; -- state->m_hasGPIO1 = true; -- state->m_hasIRQN = false; -- break; -- case 0x16: -- /* typeId = DRX3916K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = true; -- state->m_hasAudio = false; -- state->m_hasDVBT = true; -- state->m_hasDVBC = false; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = true; -- state->m_hasGPIO1 = true; -- state->m_hasIRQN = false; -- break; -- case 0x18: -- /* typeId = DRX3918K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = true; -- state->m_hasAudio = true; -- state->m_hasDVBT = true; -- state->m_hasDVBC = false; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = true; -- state->m_hasGPIO1 = true; -- state->m_hasIRQN = false; -- break; -- case 0x21: -- /* typeId = DRX3921K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = true; -- state->m_hasAudio = true; -- state->m_hasDVBT = true; -- state->m_hasDVBC = true; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = true; -- state->m_hasGPIO1 = true; -- state->m_hasIRQN = false; -- break; -- case 0x23: -- /* typeId = DRX3923K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = true; -- state->m_hasAudio = true; -- state->m_hasDVBT = true; -- state->m_hasDVBC = true; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = true; -- state->m_hasGPIO1 = true; -- state->m_hasIRQN = false; -- break; -- case 0x25: -- /* typeId = DRX3925K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = true; -- state->m_hasAudio = true; -- state->m_hasDVBT = true; -- state->m_hasDVBC = true; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = true; -- state->m_hasGPIO1 = true; -- state->m_hasIRQN = false; -- break; -- case 0x26: -- /* typeId = DRX3926K_TYPE_ID */ -- state->m_hasLNA = false; -- state->m_hasOOB = false; -- state->m_hasATV = true; -- state->m_hasAudio = false; -- state->m_hasDVBT = true; -- state->m_hasDVBC = true; -- state->m_hasSAWSW = true; -- state->m_hasGPIO2 = true; -- state->m_hasGPIO1 = true; -- state->m_hasIRQN = false; -- break; -- default: -- printk("DeviceID not supported = %02x\n", -- ((sioTopJtagidLo>>12)&0xFF)); -- status = -1; -- break; -- } -- } while(0); -- return status; --} -- --static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) --{ -- int status; -- bool powerdown_cmd; -- -- //printk("%s\n", __FUNCTION__); -- -- /* Write command */ -- status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); -- if (status < 0) -- return status; -- if (cmd == SIO_HI_RA_RAM_CMD_RESET) -- msleep(1); -- -- powerdown_cmd = -- (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && -- ((state->m_HICfgCtrl) & -- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == -- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); -- if (powerdown_cmd == false) { -- /* Wait until command rdy */ -- u32 retryCount = 0; -- u16 waitCmd; -- -- do { -- msleep(1); -- retryCount += 1; -- status = Read16(state, SIO_HI_RA_RAM_CMD__A, -- &waitCmd, 0); -- } while ((status < 0) && -- (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0)); -- -- if (status == 0) -- status = Read16(state, SIO_HI_RA_RAM_RES__A, -- pResult, 0); -- } -- return status; --} -- --static int HI_CfgCommand(struct drxk_state *state) --{ -- int status; -- -- mutex_lock(&state->mutex); -- do { -- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A, -- state->m_HICfgTimeout)); -- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A, -- state->m_HICfgCtrl)); -- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A, -- state->m_HICfgWakeUpKey)); -- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A, -- state->m_HICfgBridgeDelay)); -- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A, -- state->m_HICfgTimingDiv)); -- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A, -- SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); -- CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); -- -- state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -- } while(0); -- mutex_unlock(&state->mutex); -- return status; --} -- --static int InitHI(struct drxk_state *state) --{ -- state->m_HICfgWakeUpKey = (state->demod_address<<1); -- state->m_HICfgTimeout = 0x96FF; -- /* port/bridge/power down ctrl */ -- state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; -- return HI_CfgCommand(state); --} -- --static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) --{ -- int status = -1; -- u16 sioPdrMclkCfg = 0; -- u16 sioPdrMdxCfg = 0; -- -- do { -- /* stop lock indicator process */ -- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); -- -- /* MPEG TS pad configuration */ -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); -- -- if (mpegEnable == false) { -- /* Set MPEG TS pads to inputmode */ -- CHK_ERROR(Write16_0(state, -- SIO_PDR_MSTRT_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, -- SIO_PDR_MERR_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, -- SIO_PDR_MCLK_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, -- SIO_PDR_MVAL_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000)); -- } else { -- /* Enable MPEG output */ -- sioPdrMdxCfg = -- ((state->m_TSDataStrength << -- SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); -- sioPdrMclkCfg = ((state->m_TSClockkStrength << -- SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); -- -- CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, -- sioPdrMdxCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, -- 0x0000)); // Disable -- CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, -- 0x0000)); // Disable -- if (state->m_enableParallel == true) { -- /* paralel -> enable MD1 to MD7 */ -- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, -- sioPdrMdxCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, -- sioPdrMdxCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, -- sioPdrMdxCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, -- sioPdrMdxCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, -- sioPdrMdxCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, -- sioPdrMdxCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, -- sioPdrMdxCfg)); -- } else { -- sioPdrMdxCfg = ((state->m_TSDataStrength << -- SIO_PDR_MD0_CFG_DRIVE__B) | -- 0x0003); -- /* serial -> disable MD1 to MD7 */ -- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, -- 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, -- 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, -- 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, -- 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, -- 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, -- 0x0000)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, -- 0x0000)); -- } -- CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, -- sioPdrMclkCfg)); -- CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, -- sioPdrMdxCfg)); -- } -- /* Enable MB output over MPEG pads and ctl input */ -- CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); -- /* Write nomagic word to enable pdr reg write */ -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); -- } while(0); -- return status; --} -- --static int MPEGTSDisable(struct drxk_state *state) --{ -- return MPEGTSConfigurePins(state, false); --} -- --static int BLChainCmd(struct drxk_state *state, -- u16 romOffset, u16 nrOfElements, u32 timeOut) --{ -- u16 blStatus = 0; -- int status; -- unsigned long end; -- -- mutex_lock(&state->mutex); -- do { -- CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, -- SIO_BL_MODE_CHAIN)); -- CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, -- romOffset)); -- CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, -- nrOfElements)); -- CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, -- SIO_BL_ENABLE_ON)); -- end=jiffies+msecs_to_jiffies(timeOut); -- -- do { -- msleep(1); -- CHK_ERROR(Read16(state, SIO_BL_STATUS__A, -- &blStatus, 0)); -- } while ((blStatus == 0x1) && -- ((time_is_after_jiffies(end)))); -- if (blStatus == 0x1) { -- printk("SIO not ready\n"); -- mutex_unlock(&state->mutex); -- return -1; -- } -- } while(0); -- mutex_unlock(&state->mutex); -- return status; --} -- -- --static int DownloadMicrocode(struct drxk_state *state, -- const u8 pMCImage[], -- u32 Length) --{ -- const u8 *pSrc = pMCImage; -- u16 Flags; -- u16 Drain; -- u32 Address; -- u16 nBlocks; -- u16 BlockSize; -- u16 BlockCRC; -- u32 offset = 0; -- u32 i; -- int status; -- -- /* down the drain (we don care about MAGIC_WORD) */ -- Drain = (pSrc[0] << 8) | pSrc[1]; -- pSrc += sizeof(u16); offset += sizeof(u16); -- nBlocks = (pSrc[0] << 8) | pSrc[1]; -- pSrc += sizeof(u16); offset += sizeof(u16); -- -- for (i = 0; i < nBlocks; i += 1) { -- Address = (pSrc[0] << 24) | (pSrc[1] << 16) | -- (pSrc[2] << 8) | pSrc[3]; -- pSrc += sizeof(u32); offset += sizeof(u32); -- -- BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); -- pSrc += sizeof(u16); offset += sizeof(u16); -- -- Flags = (pSrc[0] << 8) | pSrc[1]; -- pSrc += sizeof(u16); offset += sizeof(u16); -- -- BlockCRC = (pSrc[0] << 8) | pSrc[1]; -- pSrc += sizeof(u16); offset += sizeof(u16); -- status = WriteBlock(state, Address, BlockSize, pSrc, 0); -- if (status<0) -- break; -- pSrc += BlockSize; -- offset += BlockSize; -- } -- return status; --} -- --static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) --{ -- int status; -- u16 data = 0; -- u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; -- u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; -- unsigned long end; -- -- if (enable == false) { -- desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; -- desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; -- } -- -- status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); -- -- if (data == desiredStatus) { -- /* tokenring already has correct status */ -- return status; -- } -- /* Disable/enable dvbt tokenring bridge */ -- status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); -- -- end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); -- do -- CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); -- while ((data != desiredStatus) && -- ((time_is_after_jiffies(end)))); -- if (data != desiredStatus) { -- printk("SIO not ready\n"); -- return -1; -- } -- return status; --} -- --static int MPEGTSStop(struct drxk_state *state) --{ -- int status = 0; -- u16 fecOcSncMode = 0; -- u16 fecOcIprMode = 0; -- -- do { -- /* Gracefull shutdown (byte boundaries) */ -- CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); -- fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; -- CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); -- -- /* Suppress MCLK during absence of data */ -- CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); -- fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; -- CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode)); -- } while (0); -- return status; --} -- --static int scu_command(struct drxk_state *state, -- u16 cmd, u8 parameterLen, -- u16 * parameter, u8 resultLen, u16 * result) --{ --#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 --#error DRXK register mapping no longer compatible with this routine! --#endif -- u16 curCmd = 0; -- int status; -- unsigned long end; -- -- if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || -- ((resultLen > 0) && (result == NULL))) -- return -1; -- -- mutex_lock(&state->mutex); -- do { -- /* assume that the command register is ready -- since it is checked afterwards */ -- u8 buffer[34]; -- int cnt = 0, ii; -- -- for (ii=parameterLen-1; ii >= 0; ii -= 1) { -- buffer[cnt++] = (parameter[ii] & 0xFF); -- buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); -- } -- buffer[cnt++] = (cmd & 0xFF); -- buffer[cnt++] = ((cmd >> 8) & 0xFF); -- -- WriteBlock(state, SCU_RAM_PARAM_0__A - -- (parameterLen-1), cnt, buffer, 0x00); -- /* Wait until SCU has processed command */ -- end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME); -- do { -- msleep(1); -- CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd)); -- } while (! (curCmd == DRX_SCU_READY) && -- (time_is_after_jiffies(end))); -- if (curCmd != DRX_SCU_READY) { -- printk("SCU not ready\n"); -- mutex_unlock(&state->mutex); -- return -1; -- } -- /* read results */ -- if ((resultLen > 0) && (result != NULL)) { -- s16 err; -- int ii; -- -- for(ii=resultLen-1; ii >= 0; ii -= 1) { -- CHK_ERROR(Read16_0(state, -- SCU_RAM_PARAM_0__A - ii, -- &result[ii])); -- } -- -- /* Check if an error was reported by SCU */ -- err = (s16)result[0]; -- -- /* check a few fixed error codes */ -- if (err == SCU_RESULT_UNKSTD) { -- printk("SCU_RESULT_UNKSTD\n"); -- mutex_unlock(&state->mutex); -- return -1; -- } else if (err == SCU_RESULT_UNKCMD) { -- printk("SCU_RESULT_UNKCMD\n"); -- mutex_unlock(&state->mutex); -- return -1; -- } -- /* here it is assumed that negative means error, -- and positive no error */ -- else if (err < 0) { -- printk("%s ERROR\n", __FUNCTION__); -- mutex_unlock(&state->mutex); -- return -1; -- } -- } -- } while(0); -- mutex_unlock(&state->mutex); -- if (status<0) -- { -- printk("%s: status = %d\n", __FUNCTION__, status); -- } -- -- return status; --} -- --static int SetIqmAf(struct drxk_state *state, bool active) --{ -- u16 data = 0; -- int status; -- -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active)); -- //printk("%s\n", __FUNCTION__); -- -- do -- { -- /* Configure IQM */ -- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));; -- if (!active) { -- data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY -- | IQM_AF_STDBY_STDBY_AMP_STANDBY -- | IQM_AF_STDBY_STDBY_PD_STANDBY -- | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY -- | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY -- ); -- // break; -- //default: -- // break; -- //} -- } else /* active */ { -- data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) -- & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) -- & (~IQM_AF_STDBY_STDBY_PD_STANDBY) -- & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) -- & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) -- ); -- // break; -- //default: -- // break; -- //} -- } -- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); -- }while(0); -- return status; --} -- --static int CtrlPowerMode(struct drxk_state *state, -- pDRXPowerMode_t mode) --{ -- int status = 0; -- u16 sioCcPwdMode = 0; -- -- //printk("%s\n", __FUNCTION__); -- /* Check arguments */ -- if (mode == NULL) -- return -1; -- -- switch (*mode) { -- case DRX_POWER_UP: -- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; -- break; -- case DRXK_POWER_DOWN_OFDM: -- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; -- break; -- case DRXK_POWER_DOWN_CORE: -- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; -- break; -- case DRXK_POWER_DOWN_PLL: -- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; -- break; -- case DRX_POWER_DOWN: -- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; -- break; -- default: -- /* Unknow sleep mode */ -- return -1; -- break; -- } -- -- /* If already in requested power mode, do nothing */ -- if (state->m_currentPowerMode == *mode) -- return 0; -- -- /* For next steps make sure to start from DRX_POWER_UP mode */ -- if (state->m_currentPowerMode != DRX_POWER_UP) -- { -- do { -- CHK_ERROR(PowerUpDevice(state)); -- CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); -- } while(0); -- } -- -- if (*mode == DRX_POWER_UP) { -- /* Restore analog & pin configuartion */ -- } else { -- /* Power down to requested mode */ -- /* Backup some register settings */ -- /* Set pins with possible pull-ups connected -- to them in input mode */ -- /* Analog power down */ -- /* ADC power down */ -- /* Power down device */ -- /* stop all comm_exec */ -- /* Stop and power down previous standard */ -- do { -- switch (state->m_OperationMode) { -- case OM_DVBT: -- CHK_ERROR(MPEGTSStop(state)); -- CHK_ERROR(PowerDownDVBT(state, false)); -- break; -- case OM_QAM_ITU_A: -- case OM_QAM_ITU_C: -- CHK_ERROR(MPEGTSStop(state)); -- CHK_ERROR(PowerDownQAM(state)); -- break; -- default: -- break; -- } -- CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); -- CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, -- sioCcPwdMode)); -- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, -- SIO_CC_UPDATE_KEY)); -- -- if (*mode != DRXK_POWER_DOWN_OFDM) { -- state->m_HICfgCtrl |= -- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -- CHK_ERROR(HI_CfgCommand(state)); -- } -- } while(0); -- } -- state->m_currentPowerMode = *mode; -- return (status); --} -- --static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) --{ -- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; -- u16 cmdResult = 0; -- u16 data = 0; -- int status; -- -- do { -- CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); -- if (data == SCU_COMM_EXEC_ACTIVE) { -- /* Send OFDM stop command */ -- CHK_ERROR(scu_command(state, -- SCU_RAM_COMMAND_STANDARD_OFDM | -- SCU_RAM_COMMAND_CMD_DEMOD_STOP, -- 0, NULL, 1, &cmdResult)); -- /* Send OFDM reset command */ -- CHK_ERROR(scu_command(state, -- SCU_RAM_COMMAND_STANDARD_OFDM | -- SCU_RAM_COMMAND_CMD_DEMOD_RESET, -- 0, NULL, 1, &cmdResult)); -- } -- -- /* Reset datapath for OFDM, processors first */ -- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, -- OFDM_SC_COMM_EXEC_STOP)); -- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, -- OFDM_LC_COMM_EXEC_STOP)); -- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, -- IQM_COMM_EXEC_B_STOP)); -- -- /* powerdown AFE */ -- CHK_ERROR(SetIqmAf(state,false)); -- -- /* powerdown to OFDM mode */ -- if (setPowerMode) { -- CHK_ERROR(CtrlPowerMode(state,&powerMode)); -- } -- } while(0); -- return status; --} -- --static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode) --{ -- int status = 0; -- -- /* -- Stop and power down previous standard -- TODO investigate total power down instead of partial -- power down depending on "previous" standard. -- */ -- do { -- /* disable HW lock indicator */ -- CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); -- -- if (state->m_OperationMode != oMode) { -- switch (state->m_OperationMode) { -- // OM_NONE was added for start up -- case OM_NONE: -- break; -- case OM_DVBT: -- CHK_ERROR(MPEGTSStop(state)); -- CHK_ERROR(PowerDownDVBT(state,true)); -- state->m_OperationMode = OM_NONE; -- break; -- case OM_QAM_ITU_B: -- status = -1; -- break; -- case OM_QAM_ITU_A: /* fallthrough */ -- case OM_QAM_ITU_C: -- CHK_ERROR(MPEGTSStop(state)); -- CHK_ERROR(PowerDownQAM(state)); -- state->m_OperationMode = OM_NONE; -- break; -- default: -- status = -1; -- } -- CHK_ERROR(status); -- -- /* -- Power up new standard -- */ -- switch (oMode) -- { -- case OM_DVBT: -- state->m_OperationMode = oMode; -- CHK_ERROR(SetDVBTStandard(state, oMode)); -- break; -- case OM_QAM_ITU_B: -- status = -1; -- break; -- case OM_QAM_ITU_A: /* fallthrough */ -- case OM_QAM_ITU_C: -- state->m_OperationMode = oMode; -- CHK_ERROR(SetQAMStandard(state,oMode)); -- break; -- default: -- status = -1; -- } -- } -- CHK_ERROR(status); -- } while(0); -- return 0; --} -- --static int Start(struct drxk_state *state, s32 offsetFreq, -- s32 IntermediateFrequency) --{ -- int status; -- -- do { -- u16 IFreqkHz; -- s32 OffsetkHz = offsetFreq / 1000; -- -- if (state->m_DrxkState != DRXK_STOPPED && -- state->m_DrxkState != DRXK_DTV_STARTED) { -- status = -1; -- break; -- } -- state->m_bMirrorFreqSpect = --#ifndef USE_API3 -- (state->props.inversion == INVERSION_ON); --#else -- (state->param.inversion == INVERSION_ON); --#endif -- if (IntermediateFrequency < 0) { -- state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; -- IntermediateFrequency = -IntermediateFrequency; -- } -- -- switch(state->m_OperationMode) { -- case OM_QAM_ITU_A: -- case OM_QAM_ITU_C: -- IFreqkHz = (IntermediateFrequency / 1000); -- CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz)); -- state->m_DrxkState = DRXK_DTV_STARTED; -- break; -- case OM_DVBT: -- IFreqkHz = (IntermediateFrequency / 1000); -- CHK_ERROR(MPEGTSStop(state)); -- CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz)); -- CHK_ERROR(DVBTStart(state)); -- state->m_DrxkState = DRXK_DTV_STARTED; -- break; -- default: -- break; -- } -- } while(0); -- return status; --} -- --static int ShutDown(struct drxk_state *state) --{ -- MPEGTSStop(state); -- return 0; --} -- --static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time) --{ -- int status; -- -- if (pLockStatus == NULL) -- return -1; -- -- *pLockStatus = NOT_LOCKED; -- -- /* define the SCU command code */ -- switch (state->m_OperationMode) { -- case OM_QAM_ITU_A: -- case OM_QAM_ITU_B: -- case OM_QAM_ITU_C: -- status = GetQAMLockStatus(state, pLockStatus); -- break; -- case OM_DVBT: -- status = GetDVBTLockStatus(state, pLockStatus); -- break; -- default: -- break; -- } -- return status; --} -- --static int MPEGTSStart(struct drxk_state *state) --{ -- int status = 0; -- -- u16 fecOcSncMode = 0; -- -- do { -- /* Allow OC to sync again */ -- CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); -- fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; -- CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); -- CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); -- } while (0); -- return status; --} -- --static int MPEGTSDtoInit(struct drxk_state *state) --{ -- int status = -1; -- -- do { -- /* Rate integration settings */ -- CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); -- CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); -- CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); -- CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); -- CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); -- CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); -- CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); -- CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); -- -- /* Additional configuration */ -- CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); -- CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); -- CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); -- } while (0); -- return status; --} -- --static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode) --{ -- int status = -1; -- -- u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ -- u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ -- u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ -- u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ -- u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ -- u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ -- u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ -- u16 fecOcTmdMode = 0; -- u16 fecOcTmdIntUpdRate = 0; -- u32 maxBitRate = 0; -- bool staticCLK = false; -- -- do { -- /* Check insertion of the Reed-Solomon parity bytes */ -- CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); -- CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, -- &fecOcRegIprMode)); -- fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); -- fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); -- if (state->m_insertRSByte == true) { -- /* enable parity symbol forward */ -- fecOcRegMode |= FEC_OC_MODE_PARITY__M; -- /* MVAL disable during parity bytes */ -- fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; -- /* TS burst length to 204 */ -- fecOcDtoBurstLen = 204 ; -- } -- -- /* Check serial or parrallel output */ -- fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); -- if (state->m_enableParallel == false) { -- /* MPEG data output is serial -> set ipr_mode[0] */ -- fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; -- } -- -- switch (oMode) { -- case OM_DVBT: -- maxBitRate = state->m_DVBTBitrate; -- fecOcTmdMode = 3; -- fecOcRcnCtlRate = 0xC00000; -- staticCLK = state->m_DVBTStaticCLK; -- break; -- case OM_QAM_ITU_A: /* fallthrough */ -- case OM_QAM_ITU_C: -- fecOcTmdMode = 0x0004; -- fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ -- maxBitRate = state->m_DVBCBitrate; -- staticCLK = state->m_DVBCStaticCLK; -- break; -- default: -- status = -1; -- } /* switch (standard) */ -- CHK_ERROR(status); -- -- /* Configure DTO's */ -- if (staticCLK ) { -- u32 bitRate = 0; -- -- /* Rational DTO for MCLK source (static MCLK rate), -- Dynamic DTO for optimal grouping -- (avoid intra-packet gaps), -- DTO offset enable to sync TS burst with MSTRT */ -- fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | -- FEC_OC_DTO_MODE_OFFSET_ENABLE__M); -- fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | -- FEC_OC_FCT_MODE_VIRT_ENA__M); -- -- /* Check user defined bitrate */ -- bitRate = maxBitRate; -- if (bitRate > 75900000UL) -- { /* max is 75.9 Mb/s */ -- bitRate = 75900000UL; -- } -- /* Rational DTO period: -- dto_period = (Fsys / bitrate) - 2 -- -- Result should be floored, -- to make sure >= requested bitrate -- */ -- fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) -- * 1000) / bitRate); -- if (fecOcDtoPeriod <= 2) -- fecOcDtoPeriod = 0; -- else -- fecOcDtoPeriod -= 2; -- fecOcTmdIntUpdRate = 8; -- } else { -- /* (commonAttr->staticCLK == false) => dynamic mode */ -- fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; -- fecOcFctMode = FEC_OC_FCT_MODE__PRE; -- fecOcTmdIntUpdRate = 5; -- } -- -- /* Write appropriate registers with requested configuration */ -- CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, -- fecOcDtoBurstLen)); -- CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, -- fecOcDtoPeriod)); -- CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, -- fecOcDtoMode)); -- CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, -- fecOcFctMode)); -- CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, -- fecOcRegMode)); -- CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, -- fecOcRegIprMode)); -- -- /* Rate integration settings */ -- CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, -- fecOcRcnCtlRate ,0)); -- CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, -- fecOcTmdIntUpdRate)); -- CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, -- fecOcTmdMode)); -- } while (0); -- return status; --} -- --static int MPEGTSConfigurePolarity(struct drxk_state *state) --{ -- int status; -- u16 fecOcRegIprInvert = 0; -- -- /* Data mask for the output data byte */ -- u16 InvertDataMask = -- FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | -- FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | -- FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | -- FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; -- -- /* Control selective inversion of output bits */ -- fecOcRegIprInvert &= (~(InvertDataMask)); -- if (state->m_invertDATA == true) -- fecOcRegIprInvert |= InvertDataMask; -- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); -- if (state->m_invertERR == true) -- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; -- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); -- if (state->m_invertSTR == true) -- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; -- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); -- if (state->m_invertVAL == true) -- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; -- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); -- if (state->m_invertCLK == true) -- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; -- status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); -- return status; --} -- --#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 -- --static int SetAgcRf(struct drxk_state *state, -- struct SCfgAgc *pAgcCfg, bool isDTV) --{ -- int status = 0; -- struct SCfgAgc *pIfAgcSettings; -- -- if (pAgcCfg == NULL) -- return -1; -- -- do { -- u16 data = 0; -- -- switch (pAgcCfg->ctrlMode) { -- case DRXK_AGC_CTRL_AUTO: -- -- /* Enable RF AGC DAC */ -- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); -- data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; -- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); -- -- CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, -- &data, 0)); -- -- /* Enable SCU RF AGC loop */ -- data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; -- -- /* Polarity */ -- if (state->m_RfAgcPol) -- data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -- else -- data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_CONFIG__A, data)); -- -- /* Set speed (using complementary reduction value) */ -- CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, -- &data, 0)); -- -- data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; -- data |= (~(pAgcCfg->speed << -- SCU_RAM_AGC_KI_RED_RAGC_RED__B) -- & SCU_RAM_AGC_KI_RED_RAGC_RED__M); -- -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_KI_RED__A, data)); -- -- if (IsDVBT(state)) -- pIfAgcSettings = &state->m_dvbtIfAgcCfg; -- else if (IsQAM(state)) -- pIfAgcSettings = &state->m_qamIfAgcCfg; -- else -- pIfAgcSettings = &state->m_atvIfAgcCfg; -- if (pIfAgcSettings == NULL) -- return -1; -- -- /* Set TOP, only if IF-AGC is in AUTO mode */ -- if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- pAgcCfg->top)); -- -- /* Cut-Off current */ -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_RF_IACCU_HI_CO__A, -- pAgcCfg->cutOffCurrent)); -- -- /* Max. output level */ -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, -- pAgcCfg->maxOutputLevel)); -- -- break; -- -- case DRXK_AGC_CTRL_USER: -- /* Enable RF AGC DAC */ -- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); -- data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; -- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); -- -- /* Disable SCU RF AGC loop */ -- CHK_ERROR(Read16_0(state, -- SCU_RAM_AGC_CONFIG__A, &data)); -- data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; -- if (state->m_RfAgcPol) -- data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -- else -- data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, -- data)); -- -- /* SCU c.o.c. to 0, enabling full control range */ -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, -- 0)); -- -- /* Write value to output pin */ -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, -- pAgcCfg->outputLevel)); -- break; -- -- case DRXK_AGC_CTRL_OFF: -- /* Disable RF AGC DAC */ -- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); -- data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; -- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); -- -- /* Disable SCU RF AGC loop */ -- CHK_ERROR(Read16_0(state, -- SCU_RAM_AGC_CONFIG__A, &data)); -- data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_CONFIG__A, data)); -- break; -- -- default: -- return -1; -- -- } /* switch (agcsettings->ctrlMode) */ -- } while(0); -- return status; --} -- --#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 -- --static int SetAgcIf (struct drxk_state *state, -- struct SCfgAgc *pAgcCfg, bool isDTV) --{ -- u16 data = 0; -- int status = 0; -- struct SCfgAgc *pRfAgcSettings; -- -- do { -- switch (pAgcCfg->ctrlMode) { -- case DRXK_AGC_CTRL_AUTO: -- -- /* Enable IF AGC DAC */ -- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); -- data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; -- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); -- -- CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, -- &data)); -- -- /* Enable SCU IF AGC loop */ -- data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; -- -- /* Polarity */ -- if (state->m_IfAgcPol) -- data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -- else -- data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_CONFIG__A, data)); -- -- /* Set speed (using complementary reduction value) */ -- CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, -- &data)); -- data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; -- data |= (~(pAgcCfg->speed << -- SCU_RAM_AGC_KI_RED_IAGC_RED__B) -- & SCU_RAM_AGC_KI_RED_IAGC_RED__M); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A , -- data)); -- -- if (IsQAM(state)) -- pRfAgcSettings = &state->m_qamRfAgcCfg; -- else -- pRfAgcSettings = &state->m_atvRfAgcCfg; -- if (pRfAgcSettings == NULL) -- return -1; -- /* Restore TOP */ -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- pRfAgcSettings->top)); -- break; -- -- case DRXK_AGC_CTRL_USER: -- -- /* Enable IF AGC DAC */ -- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); -- data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; -- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); -- -- CHK_ERROR(Read16_0(state, -- SCU_RAM_AGC_CONFIG__A, &data)); -- -- /* Disable SCU IF AGC loop */ -- data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; -- -- /* Polarity */ -- if (state->m_IfAgcPol) -- data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -- else -- data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_CONFIG__A, data)); -- -- /* Write value to output pin */ -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- pAgcCfg->outputLevel)); -- break; -- -- case DRXK_AGC_CTRL_OFF: -- -- /* Disable If AGC DAC */ -- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); -- data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; -- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); -- -- /* Disable SCU IF AGC loop */ -- CHK_ERROR(Read16_0(state, -- SCU_RAM_AGC_CONFIG__A, &data)); -- data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; -- CHK_ERROR(Write16_0(state, -- SCU_RAM_AGC_CONFIG__A, data)); -- break; -- } /* switch (agcSettingsIf->ctrlMode) */ -- -- /* always set the top to support -- configurations without if-loop */ -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, -- pAgcCfg->top)); -- -- -- } while(0); -- return status; --} -- --static int ReadIFAgc(struct drxk_state *state, u32 *pValue) --{ -- u16 agcDacLvl; -- int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); -- -- *pValue = 0; -- -- if (status==0) { -- u16 Level = 0; -- if (agcDacLvl > DRXK_AGC_DAC_OFFSET) -- Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; -- if (Level < 14000) -- *pValue = (14000 - Level) / 4 ; -- else -- *pValue = 0; -- } -- return status; --} -- --static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) --{ -- int status = 0; -- -- do { -- /* MER calculation */ -- u16 qamSlErrPower = 0; /* accum. error between -- raw and sliced symbols */ -- u32 qamSlSigPower = 0; /* used for MER, depends of -- QAM constellation */ -- u32 qamSlMer = 0; /* QAM MER */ -- -- /* get the register value needed for MER */ -- CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower)); -- --#ifndef USE_API3 -- switch(state->props.modulation) { --#else -- switch(state->param.u.qam.modulation) { --#endif -- case QAM_16: -- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; -- break; -- case QAM_32: -- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; -- break; -- case QAM_64: -- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; -- break; -- case QAM_128: -- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; -- break; -- default: -- case QAM_256: -- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; -- break; -- } -- -- if (qamSlErrPower > 0) { -- qamSlMer = Log10Times100(qamSlSigPower) - -- Log10Times100((u32) qamSlErrPower); -- } -- *pSignalToNoise = qamSlMer; -- } while(0); -- return status; --} -- --static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) --{ -- int status = 0; -- -- u16 regData = 0; -- u32 EqRegTdSqrErrI = 0; -- u32 EqRegTdSqrErrQ = 0; -- u16 EqRegTdSqrErrExp = 0; -- u16 EqRegTdTpsPwrOfs = 0; -- u16 EqRegTdReqSmbCnt = 0; -- u32 tpsCnt = 0; -- u32 SqrErrIQ = 0; -- u32 a = 0; -- u32 b = 0; -- u32 c = 0; -- u32 iMER = 0; -- u16 transmissionParams = 0; -- -- do { -- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, -- &EqRegTdTpsPwrOfs)); -- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, -- &EqRegTdReqSmbCnt)); -- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, -- &EqRegTdSqrErrExp)); -- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, -- ®Data)); -- /* Extend SQR_ERR_I operational range */ -- EqRegTdSqrErrI = (u32) regData; -- if ((EqRegTdSqrErrExp > 11) && -- (EqRegTdSqrErrI < 0x00000FFFUL)) { -- EqRegTdSqrErrI += 0x00010000UL; -- } -- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A, -- ®Data)); -- /* Extend SQR_ERR_Q operational range */ -- EqRegTdSqrErrQ = (u32)regData; -- if ((EqRegTdSqrErrExp > 11) && -- (EqRegTdSqrErrQ < 0x00000FFFUL)) -- EqRegTdSqrErrQ += 0x00010000UL; -- -- CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A, -- &transmissionParams)); -- -- /* Check input data for MER */ -- -- /* MER calculation (in 0.1 dB) without math.h */ -- if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) -- iMER = 0; -- else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { -- /* No error at all, this must be the HW reset value -- * Apparently no first measurement yet -- * Set MER to 0.0 */ -- iMER = 0; -- } else { -- SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << -- EqRegTdSqrErrExp; -- if ((transmissionParams & -- OFDM_SC_RA_RAM_OP_PARAM_MODE__M) -- == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) -- tpsCnt = 17; -- else -- tpsCnt = 68; -- -- /* IMER = 100 * log10 (x) -- where x = (EqRegTdTpsPwrOfs^2 * -- EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ -- -- => IMER = a + b -c -- where a = 100 * log10 (EqRegTdTpsPwrOfs^2) -- b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) -- c = 100 * log10 (SqrErrIQ) -- */ -- -- /* log(x) x = 9bits * 9bits->18 bits */ -- a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs); -- /* log(x) x = 16bits * 7bits->23 bits */ -- b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt); -- /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ -- c = Log10Times100(SqrErrIQ); -- -- iMER = a + b; -- /* No negative MER, clip to zero */ -- if (iMER > c) -- iMER -= c; -- else -- iMER = 0; -- } -- *pSignalToNoise = iMER; -- } while(0); -- -- return status; --} -- --static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) --{ -- *pSignalToNoise = 0; -- switch(state->m_OperationMode) { -- case OM_DVBT: -- return GetDVBTSignalToNoise(state, pSignalToNoise); -- case OM_QAM_ITU_A: -- case OM_QAM_ITU_C: -- return GetQAMSignalToNoise(state, pSignalToNoise); -- default: -- break; -- } -- return 0; --} -- --#if 0 --static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) --{ -- /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ -- int status = 0; -- -- static s32 QE_SN[] = -- { -- 51, // QPSK 1/2 -- 69, // QPSK 2/3 -- 79, // QPSK 3/4 -- 89, // QPSK 5/6 -- 97, // QPSK 7/8 -- 108, // 16-QAM 1/2 -- 131, // 16-QAM 2/3 -- 146, // 16-QAM 3/4 -- 156, // 16-QAM 5/6 -- 160, // 16-QAM 7/8 -- 165, // 64-QAM 1/2 -- 187, // 64-QAM 2/3 -- 202, // 64-QAM 3/4 -- 216, // 64-QAM 5/6 -- 225, // 64-QAM 7/8 -- }; -- -- *pQuality = 0; -- -- do { -- s32 SignalToNoise = 0; -- u16 Constellation = 0; -- u16 CodeRate = 0; -- u32 SignalToNoiseRel; -- u32 BERQuality; -- -- CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise)); -- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A, -- &Constellation)); -- Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; -- -- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A, -- &CodeRate)); -- CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; -- -- if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || -- CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) -- break; -- SignalToNoiseRel = SignalToNoise - -- QE_SN[Constellation * 5 + CodeRate]; -- BERQuality = 100; -- -- if (SignalToNoiseRel < -70) *pQuality = 0; -- else if (SignalToNoiseRel < 30) -- *pQuality = ((SignalToNoiseRel + 70) * -- BERQuality) / 100; -- else -- *pQuality = BERQuality; -- } while(0); -- return 0; --}; -- --static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) --{ -- int status = 0; -- *pQuality = 0; -- -- do { -- u32 SignalToNoise = 0; -- u32 BERQuality = 100; -- u32 SignalToNoiseRel = 0; -- -- CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); -- --#ifndef USE_API3 -- switch(state->props.modulation) { --#else -- switch(state->param.u.qam.modulation) { --#endif -- case QAM_16: -- SignalToNoiseRel = SignalToNoise - 200; -- break; -- case QAM_32: -- SignalToNoiseRel = SignalToNoise - 230; -- break; /* Not in NorDig */ -- case QAM_64: -- SignalToNoiseRel = SignalToNoise - 260; -- break; -- case QAM_128: -- SignalToNoiseRel = SignalToNoise - 290; -- break; -- default: -- case QAM_256: -- SignalToNoiseRel = SignalToNoise - 320; -- break; -- } -- -- if (SignalToNoiseRel < -70) -- *pQuality = 0; -- else if (SignalToNoiseRel < 30) -- *pQuality = ((SignalToNoiseRel + 70) * -- BERQuality) / 100; -- else -- *pQuality = BERQuality; -- } while(0); -- -- return status; --} -- --static int GetQuality(struct drxk_state *state, s32 *pQuality) --{ -- switch(state->m_OperationMode) { -- case OM_DVBT: -- return GetDVBTQuality(state, pQuality); -- case OM_QAM_ITU_A: -- return GetDVBCQuality(state, pQuality); -- default: -- break; -- } -- -- return 0; --} --#endif -- --/* Free data ram in SIO HI */ --#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 --#define SIO_HI_RA_RAM_USR_END__A 0x420060 -- --#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) --#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) --#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ --#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE -- --#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) --#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) --#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) -- --static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) --{ -- int status; -- -- if (state->m_DrxkState == DRXK_UNINITIALIZED) -- return -1; -- if (state->m_DrxkState == DRXK_POWERED_DOWN) -- return -1; -- -- do { -- CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, -- SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); -- if (bEnableBridge) { -- CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, -- SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); -- } else { -- CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, -- SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); -- } -- -- CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0)); -- } while(0); -- return status; --} -- --static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg) --{ -- int status; -- -- if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M)) -- return -1; -- -- status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); -- return status; --} -- --static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, -- u16 romOffset, u16 nrOfElements, u32 timeOut) --{ -- u16 blStatus = 0; -- u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF); -- u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF); -- int status ; -- unsigned long end; -- -- mutex_lock(&state->mutex); -- do { -- CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); -- CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); -- CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); -- CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); -- CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements)); -- CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); -- -- end=jiffies+msecs_to_jiffies(timeOut); -- do { -- CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus)); -- } while ((blStatus == 0x1) && -- time_is_after_jiffies(end)); -- if (blStatus == 0x1) { -- printk("SIO not ready\n"); -- mutex_unlock(&state->mutex); -- return -1; -- } -- } while(0); -- mutex_unlock(&state->mutex); -- return status; -- --} -- --static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) --{ -- u16 data = 0; -- int status; -- -- do { -- /* Start measurement */ -- CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, -- IQM_AF_COMM_EXEC_ACTIVE)); -- CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1)); -- -- *count = 0; -- CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data)); -- if (data == 127) -- *count = *count+1; -- CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data)); -- if (data == 127) -- *count = *count+1; -- CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data)); -- if (data == 127) -- *count = *count+1; -- } while(0); -- return status; --} -- --static int ADCSynchronization(struct drxk_state *state) --{ -- u16 count = 0; -- int status; -- -- do { -- CHK_ERROR(ADCSyncMeasurement(state, &count)); -- -- if (count==1) { -- /* Try sampling on a diffrent edge */ -- u16 clkNeg = 0; -- -- CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg)); -- if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == -- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { -- clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -- clkNeg |= -- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; -- } else { -- clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -- clkNeg |= -- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; -- } -- CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg)); -- CHK_ERROR(ADCSyncMeasurement(state, &count)); -- } -- -- if (count < 2) -- status = -1; -- } while (0); -- return status; --} -- --static int SetFrequencyShifter(struct drxk_state *state, -- u16 intermediateFreqkHz, -- s32 tunerFreqOffset, -- bool isDTV) --{ -- bool selectPosImage = false; -- u32 rfFreqResidual = tunerFreqOffset; -- u32 fmFrequencyShift = 0; -- bool tunerMirror = !state->m_bMirrorFreqSpect; -- u32 adcFreq; -- bool adcFlip; -- int status; -- u32 ifFreqActual; -- u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3); -- u32 frequencyShift; -- bool imageToSelect; -- -- /* -- Program frequency shifter -- No need to account for mirroring on RF -- */ -- if (isDTV) { -- if ((state->m_OperationMode == OM_QAM_ITU_A) || -- (state->m_OperationMode == OM_QAM_ITU_C) || -- (state->m_OperationMode == OM_DVBT)) -- selectPosImage = true; -- else -- selectPosImage = false; -- } -- if (tunerMirror) -- /* tuner doesn't mirror */ -- ifFreqActual = intermediateFreqkHz + -- rfFreqResidual + fmFrequencyShift; -- else -- /* tuner mirrors */ -- ifFreqActual = intermediateFreqkHz - -- rfFreqResidual - fmFrequencyShift; -- if (ifFreqActual > samplingFrequency / 2) { -- /* adc mirrors */ -- adcFreq = samplingFrequency - ifFreqActual; -- adcFlip = true; -- } else { -- /* adc doesn't mirror */ -- adcFreq = ifFreqActual; -- adcFlip = false; -- } -- -- frequencyShift = adcFreq; -- imageToSelect = state->m_rfmirror ^ tunerMirror ^ -- adcFlip ^ selectPosImage; -- state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency); -- -- if (imageToSelect) -- state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; -- -- /* Program frequency shifter with tuner offset compensation */ -- /* frequencyShift += tunerFreqOffset; TODO */ -- status = Write32(state, IQM_FS_RATE_OFS_LO__A , -- state->m_IqmFsRateOfs, 0); -- return status; --} -- --static int InitAGC(struct drxk_state *state, bool isDTV) --{ -- u16 ingainTgt = 0; -- u16 ingainTgtMin = 0; -- u16 ingainTgtMax = 0; -- u16 clpCyclen = 0; -- u16 clpSumMin = 0; -- u16 clpDirTo = 0; -- u16 snsSumMin = 0; -- u16 snsSumMax = 0; -- u16 clpSumMax = 0; -- u16 snsDirTo = 0; -- u16 kiInnergainMin = 0; -- u16 ifIaccuHiTgt = 0; -- u16 ifIaccuHiTgtMin = 0; -- u16 ifIaccuHiTgtMax = 0; -- u16 data = 0; -- u16 fastClpCtrlDelay = 0; -- u16 clpCtrlMode = 0; -- int status = 0; -- -- do { -- /* Common settings */ -- snsSumMax = 1023; -- ifIaccuHiTgtMin = 2047; -- clpCyclen = 500; -- clpSumMax = 1023; -- -- if (IsQAM(state)) { -- /* Standard specific settings */ -- clpSumMin = 8; -- clpDirTo = (u16) - 9; -- clpCtrlMode = 0; -- snsSumMin = 8; -- snsDirTo = (u16) - 9; -- kiInnergainMin = (u16) - 1030; -- } else -- status = -1; -- CHK_ERROR((status)); -- if (IsQAM(state)) { -- ifIaccuHiTgtMax = 0x2380; -- ifIaccuHiTgt = 0x2380; -- ingainTgtMin = 0x0511; -- ingainTgt = 0x0511; -- ingainTgtMax = 5119; -- fastClpCtrlDelay = -- state->m_qamIfAgcCfg.FastClipCtrlDelay; -- } else { -- ifIaccuHiTgtMax = 0x1200; -- ifIaccuHiTgt = 0x1200; -- ingainTgtMin = 13424; -- ingainTgt = 13424; -- ingainTgtMax = 30000; -- fastClpCtrlDelay = -- state->m_dvbtIfAgcCfg.FastClipCtrlDelay; -- } -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, -- fastClpCtrlDelay)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, -- clpCtrlMode)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, -- ingainTgt)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, -- ingainTgtMin)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, -- ingainTgtMax)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, -- ifIaccuHiTgtMin)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- ifIaccuHiTgtMax)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, -- clpSumMax)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, -- snsSumMax)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, -- kiInnergainMin)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, -- ifIaccuHiTgt)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, -- clpCyclen)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, -- 1023)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, -- (u16) -1023)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, -- 50)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, -- 20)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, -- clpSumMin)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, -- snsSumMin)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, -- clpDirTo)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, -- snsDirTo)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); -- -- /* Initialize inner-loop KI gain factors */ -- CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); -- if (IsQAM(state)) { -- data = 0x0657; -- data &= ~SCU_RAM_AGC_KI_RF__M; -- data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); -- data &= ~SCU_RAM_AGC_KI_IF__M; -- data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); -- } -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); -- } while(0); -- return status; --} -- --static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr) --{ -- int status; -- -- do { -- if (packetErr == NULL) { -- CHK_ERROR(Write16_0(state, -- SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, -- 0)); -- } else { -- CHK_ERROR(Read16_0(state, -- SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, -- packetErr)); -- } -- } while (0); -- return status; --} -- --static int DVBTScCommand(struct drxk_state *state, -- u16 cmd, u16 subcmd, -- u16 param0, u16 param1, u16 param2, -- u16 param3, u16 param4) --{ -- u16 curCmd = 0; -- u16 errCode = 0; -- u16 retryCnt = 0; -- u16 scExec = 0; -- int status; -- -- status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); -- if (scExec != 1) { -- /* SC is not running */ -- return -1; -- } -- -- /* Wait until sc is ready to receive command */ -- retryCnt =0; -- do { -- msleep(1); -- status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); -- retryCnt++; -- } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); -- if (retryCnt >= DRXK_MAX_RETRIES) -- return -1; -- /* Write sub-command */ -- switch (cmd) { -- /* All commands using sub-cmd */ -- case OFDM_SC_RA_RAM_CMD_PROC_START: -- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: -- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: -- status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); -- break; -- default: -- /* Do nothing */ -- break; -- } /* switch (cmd->cmd) */ -- -- /* Write needed parameters and the command */ -- switch (cmd) { -- /* All commands using 5 parameters */ -- /* All commands using 4 parameters */ -- /* All commands using 3 parameters */ -- /* All commands using 2 parameters */ -- case OFDM_SC_RA_RAM_CMD_PROC_START: -- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: -- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: -- status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); -- /* All commands using 1 parameters */ -- case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: -- case OFDM_SC_RA_RAM_CMD_USER_IO: -- status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); -- /* All commands using 0 parameters */ -- case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: -- case OFDM_SC_RA_RAM_CMD_NULL: -- /* Write command */ -- status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); -- break; -- default: -- /* Unknown command */ -- return -EINVAL; -- } /* switch (cmd->cmd) */ -- -- /* Wait until sc is ready processing command */ -- retryCnt = 0; -- do{ -- msleep(1); -- status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); -- retryCnt++; -- } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); -- if (retryCnt >= DRXK_MAX_RETRIES) -- return -1; -- -- /* Check for illegal cmd */ -- status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); -- if (errCode == 0xFFFF) -- { -- /* illegal command */ -- return -EINVAL; -- } -- -- /* Retreive results parameters from SC */ -- switch (cmd) { -- /* All commands yielding 5 results */ -- /* All commands yielding 4 results */ -- /* All commands yielding 3 results */ -- /* All commands yielding 2 results */ -- /* All commands yielding 1 result */ -- case OFDM_SC_RA_RAM_CMD_USER_IO: -- case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: -- status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); -- /* All commands yielding 0 results */ -- case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: -- case OFDM_SC_RA_RAM_CMD_SET_TIMER: -- case OFDM_SC_RA_RAM_CMD_PROC_START: -- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: -- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: -- case OFDM_SC_RA_RAM_CMD_NULL: -- break; -- default: -- /* Unknown command */ -- return -EINVAL; -- break; -- } /* switch (cmd->cmd) */ -- return status; --} -- --static int PowerUpDVBT (struct drxk_state *state) --{ -- DRXPowerMode_t powerMode = DRX_POWER_UP; -- int status; -- -- do { -- CHK_ERROR(CtrlPowerMode(state, &powerMode)); -- } while (0); -- return status; --} -- --static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled) --{ -- int status; -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- if (*enabled == true) -- { -- status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); -- } -- else -- { -- status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); -- } -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- -- return status; --} -- #define DEFAULT_FR_THRES_8K 4000 --static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled) --{ -- -- int status; -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- -- if (*enabled == true) -- { -- /* write mask to 1 */ -- status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, -- DEFAULT_FR_THRES_8K); -- } -- else -- { -- /* write mask to 0 */ -- status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); -- } -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- -- return status; --} -- --static int DVBTCtrlSetEchoThreshold (struct drxk_state *state, -- struct DRXKCfgDvbtEchoThres_t* echoThres) --{ -- u16 data = 0; -- int status; -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- -- do { -- CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); -- -- switch (echoThres->fftMode) -- { -- case DRX_FFTMODE_2K: -- data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M; -- data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) & -- (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); -- break; -- case DRX_FFTMODE_8K: -- data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M; -- data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & -- (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); -- break; -- default: -- return -1; -- break; -- } -- -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); -- } while (0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); -- } -- -- return status; --} -- --static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, -- enum DRXKCfgDvbtSqiSpeed* speed) --{ -- int status; -- -- switch (*speed) { -- case DRXK_DVBT_SQI_SPEED_FAST: -- case DRXK_DVBT_SQI_SPEED_MEDIUM: -- case DRXK_DVBT_SQI_SPEED_SLOW: -- break; -- default: -- return -EINVAL; -- } -- status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, -- (u16) *speed); -- return status; --} -- --/*============================================================================*/ -- --/** --* \brief Activate DVBT specific presets --* \param demod instance of demodulator. --* \return DRXStatus_t. --* --* Called in DVBTSetStandard --* --*/ --static int DVBTActivatePresets (struct drxk_state *state) --{ -- int status; -- -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- -- struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K}; -- struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K}; -- -- do { -- bool setincenable = false; -- bool setfrenable = true; -- CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable)); -- CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable)); -- CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); -- CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, -- state->m_dvbtIfAgcCfg.IngainTgtMax)); -- } while (0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- -- return status; --} --/*============================================================================*/ -- --/** --* \brief Initialize channelswitch-independent settings for DVBT. --* \param demod instance of demodulator. --* \return DRXStatus_t. --* --* For ROM code channel filter taps are loaded from the bootloader. For microcode --* the DVB-T taps from the drxk_filters.h are used. --*/ --static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode) --{ -- u16 cmdResult = 0; -- u16 data = 0; -- int status; -- -- //printk("%s\n", __FUNCTION__); -- -- PowerUpDVBT(state); -- -- do { -- /* added antenna switch */ -- SwitchAntennaToDVBT(state); -- /* send OFDM reset command */ -- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); -- -- /* send OFDM setenv command */ -- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult)); -- -- /* reset datapath for OFDM, processors first */ -- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); -- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); -- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP )); -- -- /* IQM setup */ -- /* synchronize on ofdstate->m_festart */ -- CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); -- /* window size for clipping ADC detection */ -- CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); -- /* window size for for sense pre-SAW detection */ -- CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); -- /* sense threshold for sense pre-SAW detection */ -- CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); -- CHK_ERROR(SetIqmAf(state,true)); -- -- CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); -- -- /* Impulse noise cruncher setup */ -- CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ -- CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ -- CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ -- -- CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); -- CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ -- CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ -- CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); -- CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); -- -- /* virtual clipping threshold for clipping ADC detection */ -- CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); -- CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ -- -- CHK_ERROR(BLChainCmd(state, -- DRXK_BL_ROM_OFFSET_TAPS_DVBT, -- DRXK_BLCC_NR_ELEMENTS_TAPS, -- DRXK_BLC_TIMEOUT)); -- -- CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ -- CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); -- /* enable power measurement interrupt */ -- CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); -- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); -- -- /* IQM will not be reset from here, sync ADC and update/init AGC */ -- CHK_ERROR(ADCSynchronization(state)); -- CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); -- -- /* Halt SCU to enable safe non-atomic accesses */ -- CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); -- -- CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ; -- CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true)); -- -- /* Set Noise Estimation notch width and enable DC fix */ -- CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data)); -- data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data)); -- -- /* Activate SCU to enable SCU commands */ -- CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); -- -- if (!state->m_DRXK_A3_ROM_CODE) -- { -- /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ -- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, -- state->m_dvbtIfAgcCfg.FastClipCtrlDelay)); -- } -- -- /* OFDM_SC setup */ --#ifdef COMPILE_FOR_NONRT -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); --#endif -- -- /* FEC setup */ -- CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ -- -- --#ifdef COMPILE_FOR_NONRT -- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400)); --#else -- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000)); --#endif -- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001)); -- -- /* Setup MPEG bus */ -- CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT)); -- /* Set DVBT Presets */ -- CHK_ERROR (DVBTActivatePresets (state)); -- -- } while (0); -- -- if (status<0) -- { -- printk("%s status - %08x\n",__FUNCTION__,status); -- } -- -- return status; --} -- --/*============================================================================*/ --/** --* \brief Start dvbt demodulating for channel. --* \param demod instance of demodulator. --* \return DRXStatus_t. --*/ --static int DVBTStart(struct drxk_state *state) --{ -- u16 param1; -- -- int status; --// DRXKOfdmScCmd_t scCmd; -- -- //printk("%s\n",__FUNCTION__); -- /* Start correct processes to get in lock */ -- /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ -- do { -- param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; -- CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0)); -- /* Start FEC OC */ -- CHK_ERROR(MPEGTSStart(state)); -- CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); -- } while (0); -- return (status); --} -- -- --/*============================================================================*/ -- --/** --* \brief Set up dvbt demodulator for channel. --* \param demod instance of demodulator. --* \return DRXStatus_t. --* // original DVBTSetChannel() --*/ --static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) --{ -- u16 cmdResult = 0; -- u16 transmissionParams = 0; -- u16 operationMode = 0; -- u32 iqmRcRateOfs = 0; -- u32 bandwidth = 0; -- u16 param1; -- int status; -- -- //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset); -- do { -- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | -- SCU_RAM_COMMAND_CMD_DEMOD_STOP, -- 0,NULL,1,&cmdResult)); -- -- /* Halt SCU to enable safe non-atomic accesses */ -- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); -- -- /* Stop processors */ -- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); -- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); -- -- /* Mandatory fix, always stop CP, required to set spl offset back to -- hardware default (is set to 0 by ucode during pilot detection */ -- CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP)); -- -- /*== Write channel settings to device =====================================*/ -- -- /* mode */ --#ifndef USE_API3 -- switch(state->props.transmission_mode) { --#else -- switch(state->param.u.ofdm.transmission_mode) { --#endif -- case TRANSMISSION_MODE_AUTO: -- default: -- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; -- /* fall through , try first guess DRX_FFTMODE_8K */ -- case TRANSMISSION_MODE_8K: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; -- break; -- case TRANSMISSION_MODE_2K: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; -- break; -- } -- -- /* guard */ --#ifndef USE_API3 -- switch(state->props.guard_interval) { --#else -- switch(state->param.u.ofdm.guard_interval) { --#endif -- default: -- case GUARD_INTERVAL_AUTO: -- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; -- /* fall through , try first guess DRX_GUARD_1DIV4 */ -- case GUARD_INTERVAL_1_4: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; -- break; -- case GUARD_INTERVAL_1_32: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; -- break; -- case GUARD_INTERVAL_1_16: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; -- break; -- case GUARD_INTERVAL_1_8: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; -- break; -- } -- -- /* hierarchy */ --#ifndef USE_API3 -- switch(state->props.hierarchy) { --#else -- switch(state->param.u.ofdm.hierarchy_information) { --#endif -- case HIERARCHY_AUTO: -- case HIERARCHY_NONE: -- default: -- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; -- /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ -- // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; -- //break; -- case HIERARCHY_1: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; -- break; -- case HIERARCHY_2: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; -- break; -- case HIERARCHY_4: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; -- break; -- } -- -- -- /* constellation */ --#ifndef USE_API3 -- switch(state->props.modulation) { --#else -- switch(state->param.u.ofdm.constellation) { --#endif -- case QAM_AUTO: -- default: -- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; -- /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ -- case QAM_64: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; -- break; -- case QPSK: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; -- break; -- case QAM_16: -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; -- break; -- } --#if 0 -- // No hierachical channels support in BDA -- /* Priority (only for hierarchical channels) */ -- switch (channel->priority) { -- case DRX_PRIORITY_LOW : -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; -- WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO); -- break; -- case DRX_PRIORITY_HIGH : -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; -- WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); -- break; -- case DRX_PRIORITY_UNKNOWN : /* fall through */ -- default: -- return (DRX_STS_INVALID_ARG); -- break; -- } --#else -- // Set Priorty high -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; -- CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); --#endif -- -- /* coderate */ --#ifndef USE_API3 -- switch(state->props.code_rate_HP) { --#else -- switch(state->param.u.ofdm.code_rate_HP) { --#endif -- case FEC_AUTO: -- default: -- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; -- /* fall through , try first guess DRX_CODERATE_2DIV3 */ -- case FEC_2_3 : -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; -- break; -- case FEC_1_2 : -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; -- break; -- case FEC_3_4 : -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; -- break; -- case FEC_5_6 : -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; -- break; -- case FEC_7_8 : -- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; -- break; -- } -- -- /* SAW filter selection: normaly not necesarry, but if wanted -- the application can select a SAW filter via the driver by using UIOs */ -- /* First determine real bandwidth (Hz) */ -- /* Also set delay for impulse noise cruncher */ -- /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed -- by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC -- functions */ --#ifndef USE_API3 -- switch(state->props.bandwidth_hz) { --#else -- switch(state->param.u.ofdm.bandwidth) { --#endif --#ifndef USE_API3 -- case 0: -- case 8000000: --#else -- case BANDWIDTH_AUTO: -- case BANDWIDTH_8_MHZ: --#endif -- bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052)); -- /* cochannel protection for PAL 8 MHz */ -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); -- break; --#ifndef USE_API3 -- case 7000000: --#else -- case BANDWIDTH_7_MHZ: --#endif -- bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491)); -- /* cochannel protection for PAL 7 MHz */ -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); -- break; --#ifndef USE_API3 -- case 6000000: --#else -- case BANDWIDTH_6_MHZ: --#endif -- bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073)); -- /* cochannel protection for NTSC 6 MHz */ -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14)); -- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); -- break; -- } -- -- if (iqmRcRateOfs == 0) -- { -- /* Now compute IQM_RC_RATE_OFS -- (((SysFreq/BandWidth)/2)/2) -1) * 2^23) -- => -- ((SysFreq / BandWidth) * (2^21)) - (2^23) -- */ -- /* (SysFreq / BandWidth) * (2^28) */ -- /* assert (MAX(sysClk)/MIN(bandwidth) < 16) -- => assert(MAX(sysClk) < 16*MIN(bandwidth)) -- => assert(109714272 > 48000000) = true so Frac 28 can be used */ -- iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth); -- /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ -- if ((iqmRcRateOfs & 0x7fL) >= 0x40) -- { -- iqmRcRateOfs += 0x80L; -- } -- iqmRcRateOfs = iqmRcRateOfs >> 7 ; -- /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ -- iqmRcRateOfs = iqmRcRateOfs - (1<<23); -- } -- -- iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<m_DRXK_A3_ROM_CODE) -- CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed)); -- -- } while(0); -- if (status<0) { -- //printk("%s status - %08x\n",__FUNCTION__,status); -- } -- -- return status; --} -- -- --/*============================================================================*/ -- --/** --* \brief Retreive lock status . --* \param demod Pointer to demodulator instance. --* \param lockStat Pointer to lock status structure. --* \return DRXStatus_t. --* --*/ --static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) --{ -- int status; -- const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | -- OFDM_SC_RA_RAM_LOCK_FEC__M ); -- const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); -- const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ; -- -- u16 ScRaRamLock = 0; -- u16 ScCommExec = 0; -- -- /* driver 0.9.0 */ -- /* Check if SC is running */ -- status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); -- if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) -- { -- /* SC not active; return DRX_NOT_LOCKED */ -- *pLockStatus = NOT_LOCKED; -- return status; -- } -- -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- -- status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); -- -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock)); -- -- if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { -- *pLockStatus = MPEG_LOCK; -- } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) { -- *pLockStatus = FEC_LOCK; -- } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) { -- *pLockStatus = DEMOD_LOCK; -- } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) { -- *pLockStatus = NEVER_LOCK; -- } else { -- *pLockStatus = NOT_LOCKED; -- } -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- -- return status; --} -- --static int PowerUpQAM (struct drxk_state *state) --{ -- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; -- -- -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- do -- { -- CHK_ERROR(CtrlPowerMode(state, &powerMode)); -- -- }while(0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); -- } -- return status; --} -- -- --/// Power Down QAM --static int PowerDownQAM(struct drxk_state *state) --{ -- u16 data = 0; -- u16 cmdResult; -- -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- do -- { -- CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); -- if (data == SCU_COMM_EXEC_ACTIVE) -- { -- /* -- STOP demodulator -- QAM and HW blocks -- */ -- /* stop all comstate->m_exec */ -- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); -- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult)); -- } -- /* powerdown AFE */ -- CHK_ERROR(SetIqmAf(state, false)); -- } -- while(0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- return status; --} --/*============================================================================*/ -- --/** --* \brief Setup of the QAM Measurement intervals for signal quality --* \param demod instance of demod. --* \param constellation current constellation. --* \return DRXStatus_t. --* --* NOTE: --* Take into account that for certain settings the errorcounters can overflow. --* The implementation does not check this. --* --*/ --static int SetQAMMeasurement(struct drxk_state *state, -- enum EDrxkConstellation constellation, -- u32 symbolRate) --{ -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode)); -- -- u32 fecBitsDesired = 0; /* BER accounting period */ -- u32 fecRsPeriodTotal = 0; /* Total period */ -- u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ -- u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ -- int status = 0; -- -- fecRsPrescale = 1; -- -- do { -- -- /* fecBitsDesired = symbolRate [kHz] * -- FrameLenght [ms] * -- (constellation + 1) * -- SyncLoss (== 1) * -- ViterbiLoss (==1) -- */ -- switch (constellation) -- { -- case DRX_CONSTELLATION_QAM16: -- fecBitsDesired = 4 * symbolRate; -- break; -- case DRX_CONSTELLATION_QAM32: -- fecBitsDesired = 5 * symbolRate; -- break; -- case DRX_CONSTELLATION_QAM64: -- fecBitsDesired = 6 * symbolRate; -- break; -- case DRX_CONSTELLATION_QAM128: -- fecBitsDesired = 7 * symbolRate; -- break; -- case DRX_CONSTELLATION_QAM256: -- fecBitsDesired = 8 * symbolRate; -- break; -- default: -- status = -EINVAL; -- } -- CHK_ERROR(status); -- -- fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ -- fecBitsDesired *= 500; /* meas. period [ms] */ -- -- /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ -- /* fecRsPeriodTotal = fecBitsDesired / 1632 */ -- fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/ -- -- /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ -- fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); -- if (fecRsPrescale == 0) { -- /* Divide by zero (though impossible) */ -- status = -1; -- } -- CHK_ERROR(status); -- fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) / -- fecRsPrescale; -- -- /* write corresponding registers */ -- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod)); -- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale)); -- CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); -- -- } while (0); -- -- if (status<0) { -- printk("%s: status - %08x\n",__FUNCTION__,status); -- } -- return status; --} -- --static int SetQAM16 (struct drxk_state *state) --{ -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- do -- { -- /* QAM Equalizer Setup */ -- /* Equalizer */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); -- /* Decision Feedback Equalizer */ -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); -- -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); -- -- /* QAM Slicer Settings */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16)); -- -- /* QAM Loop Controller Coeficients */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); -- -- -- /* QAM State Machine (FSM) Thresholds */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); -- -- -- /* QAM FSM Tracking Parameters */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127)); -- }while(0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- return status; --} -- --/*============================================================================*/ -- --/** --* \brief QAM32 specific setup --* \param demod instance of demod. --* \return DRXStatus_t. --*/ --static int SetQAM32 (struct drxk_state *state) --{ -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- do -- { -- /* QAM Equalizer Setup */ -- /* Equalizer */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); -- -- /* Decision Feedback Equalizer */ -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); -- -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); -- -- /* QAM Slicer Settings */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32)); -- -- -- /* QAM Loop Controller Coeficients */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); -- -- -- /* QAM State Machine (FSM) Thresholds */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); -- -- -- /* QAM FSM Tracking Parameters */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86)); -- }while(0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- return status; --} -- --/*============================================================================*/ -- --/** --* \brief QAM64 specific setup --* \param demod instance of demod. --* \return DRXStatus_t. --*/ --static int SetQAM64 (struct drxk_state *state) --{ -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- do -- { -- /* QAM Equalizer Setup */ -- /* Equalizer */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); -- -- /* Decision Feedback Equalizer */ -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); -- -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); -- -- /* QAM Slicer Settings */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64)); -- -- -- /* QAM Loop Controller Coeficients */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); -- -- -- /* QAM State Machine (FSM) Thresholds */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); -- -- -- /* QAM FSM Tracking Parameters */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80)); -- }while(0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- return status; --} -- --/*============================================================================*/ -- --/** --* \brief QAM128 specific setup --* \param demod: instance of demod. --* \return DRXStatus_t. --*/ --static int SetQAM128(struct drxk_state *state) --{ -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- do -- { -- /* QAM Equalizer Setup */ -- /* Equalizer */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); -- -- /* Decision Feedback Equalizer */ -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); -- -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); -- -- -- /* QAM Slicer Settings */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128)); -- -- -- /* QAM Loop Controller Coeficients */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); -- -- -- /* QAM State Machine (FSM) Thresholds */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); -- -- /* QAM FSM Tracking Parameters */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23)); -- }while(0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- return status; --} -- --/*============================================================================*/ -- --/** --* \brief QAM256 specific setup --* \param demod: instance of demod. --* \return DRXStatus_t. --*/ --static int SetQAM256(struct drxk_state *state) --{ -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- do -- { -- /* QAM Equalizer Setup */ -- /* Equalizer */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); -- -- /* Decision Feedback Equalizer */ -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); -- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); -- -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); -- -- /* QAM Slicer Settings */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256)); -- -- -- /* QAM Loop Controller Coeficients */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); -- -- -- /* QAM State Machine (FSM) Thresholds */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); -- -- -- /* QAM FSM Tracking Parameters */ -- -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0)); -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8)); -- }while(0); -- -- if (status<0) -- { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- } -- return status; --} -- -- --/*============================================================================*/ --/** --* \brief Reset QAM block. --* \param demod: instance of demod. --* \param channel: pointer to channel data. --* \return DRXStatus_t. --*/ --static int QAMResetQAM(struct drxk_state *state) --{ -- int status; -- u16 cmdResult; -- -- //printk("%s\n", __FUNCTION__); -- do -- { -- /* Stop QAM comstate->m_exec */ -- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); -- -- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); -- } while (0); -- -- /* All done, all OK */ -- return status; --} -- --/*============================================================================*/ -- --/** --* \brief Set QAM symbolrate. --* \param demod: instance of demod. --* \param channel: pointer to channel data. --* \return DRXStatus_t. --*/ --static int QAMSetSymbolrate(struct drxk_state *state) --{ -- u32 adcFrequency = 0; -- u32 symbFreq = 0; -- u32 iqmRcRate = 0; -- u16 ratesel = 0; -- u32 lcSymbRate = 0; -- int status; -- u32 srate = --#ifndef USE_API3 -- state->props.symbol_rate; --#else -- state->param.u.qam.symbol_rate; --#endif -- -- do -- { -- /* Select & calculate correct IQM rate */ -- adcFrequency = (state->m_sysClockFreq * 1000) / 3; -- ratesel = 0; -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate)); -- //printk("SR %d\n", state->param.u.qam.symbol_rate); -- if (srate <= 1188750) -- { -- ratesel = 3; -- } -- else if (srate <= 2377500) -- { -- ratesel = 2; -- } -- else if (srate <= 4755000) -- { -- ratesel = 1; -- } -- CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel)); -- -- /* -- IqmRcRate = ((Fadc / (symbolrate * (4<> 7) - -- (1 << 23); -- CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0)); -- state->m_iqmRcRate = iqmRcRate; -- /* -- LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) -- */ -- symbFreq = srate; -- if (adcFrequency == 0) -- { -- /* Divide by zero */ -- return -1; -- } -- lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + -- (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16); -- if (lcSymbRate > 511) -- { -- lcSymbRate = 511; -- } -- CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate)); -- } while (0); -- -- return status; --} -- --/*============================================================================*/ -- --/** --* \brief Get QAM lock status. --* \param demod: instance of demod. --* \param channel: pointer to channel data. --* \return DRXStatus_t. --*/ -- --static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) --{ -- int status; -- u16 Result[2] = {0,0}; -- -- status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result); -- if (status<0) -- { -- printk("%s status = %08x\n",__FUNCTION__,status); -- } -- if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) -- { -- /* 0x0000 NOT LOCKED */ -- *pLockStatus = NOT_LOCKED; -- } -- else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) -- { -- /* 0x4000 DEMOD LOCKED */ -- *pLockStatus = DEMOD_LOCK; -- } -- else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) -- { -- /* 0x8000 DEMOD + FEC LOCKED (system lock) */ -- *pLockStatus = MPEG_LOCK; -- } -- else -- { -- /* 0xC000 NEVER LOCKED */ -- /* (system will never be able to lock to the signal) */ -- /* TODO: check this, intermediate & standard specific lock states are not -- taken into account here */ -- *pLockStatus = NEVER_LOCK; -- } -- return status; --} -- --#define QAM_MIRROR__M 0x03 --#define QAM_MIRROR_NORMAL 0x00 --#define QAM_MIRRORED 0x01 --#define QAM_MIRROR_AUTO_ON 0x02 --#define QAM_LOCKRANGE__M 0x10 --#define QAM_LOCKRANGE_NORMAL 0x10 -- --static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) --{ -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- int status = 0; -- u8 parameterLen; -- u16 setEnvParameters[5]; -- u16 setParamParameters[4]={0,0,0,0}; -- u16 cmdResult; -- -- //printk("%s\n", __FUNCTION__); -- -- do { -- /* -- STEP 1: reset demodulator -- resets FEC DI and FEC RS -- resets QAM block -- resets SCU variables -- */ -- CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP)); -- CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP)); -- CHK_ERROR(QAMResetQAM(state)); -- -- /* -- STEP 2: configure demodulator -- -set env -- -set params; resets IQM,QAM,FEC HW; initializes some SCU variables -- */ -- CHK_ERROR(QAMSetSymbolrate(state)); -- -- /* Env parameters */ -- setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ -- if (state->m_OperationMode == OM_QAM_ITU_C) -- { -- setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ -- } -- setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); --// check for LOCKRANGE Extented -- // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; -- parameterLen = 4; -- -- /* Set params */ --#ifndef USE_API3 -- switch(state->props.modulation) --#else -- switch(state->param.u.qam.modulation) --#endif -- { -- case QAM_256: -- state->m_Constellation = DRX_CONSTELLATION_QAM256; -- break; -- case QAM_AUTO: -- case QAM_64: -- state->m_Constellation = DRX_CONSTELLATION_QAM64; -- break; -- case QAM_16: -- state->m_Constellation = DRX_CONSTELLATION_QAM16; -- break; -- case QAM_32: -- state->m_Constellation = DRX_CONSTELLATION_QAM32; -- break; -- case QAM_128: -- state->m_Constellation = DRX_CONSTELLATION_QAM128; -- break; -- default: -- status = -EINVAL; -- break; -- } -- CHK_ERROR(status); -- setParamParameters[0] = state->m_Constellation; /* constellation */ -- setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ -- -- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult)); -- -- -- /* STEP 3: enable the system in a mode where the ADC provides valid signal -- setup constellation independent registers */ --// CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); -- CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true)); -- -- /* Setup BER measurement */ -- CHK_ERROR(SetQAMMeasurement (state, -- state->m_Constellation, --#ifndef USE_API3 -- state->props.symbol_rate)); --#else -- state->param.u.qam.symbol_rate)); --#endif -- -- /* Reset default values */ -- CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE)); -- CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); -- -- /* Reset default LC values */ -- CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); -- -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); -- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); -- -- /* Mirroring, QAM-block starting point not inverted */ -- CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS)); -- -- /* Halt SCU to enable safe non-atomic accesses */ -- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); -- -- /* STEP 4: constellation specific setup */ --#ifndef USE_API3 -- switch (state->props.modulation) --#else -- switch (state->param.u.qam.modulation) --#endif -- { -- case QAM_16: -- CHK_ERROR(SetQAM16(state)); -- break; -- case QAM_32: -- CHK_ERROR(SetQAM32(state)); -- break; -- case QAM_AUTO: -- case QAM_64: -- CHK_ERROR(SetQAM64(state)); -- break; -- case QAM_128: -- CHK_ERROR(SetQAM128(state)); -- break; -- case QAM_256: -- //printk("SETQAM256\n"); -- CHK_ERROR(SetQAM256(state)); -- break; -- default: -- return -1; -- break; -- } /* switch */ -- /* Activate SCU to enable SCU commands */ -- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); -- -- -- /* Re-configure MPEG output, requires knowledge of channel bitrate */ --// extAttr->currentChannel.constellation = channel->constellation; --// extAttr->currentChannel.symbolrate = channel->symbolrate; -- CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); -- -- /* Start processes */ -- CHK_ERROR(MPEGTSStart(state)); -- CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); -- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); -- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); -- -- /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ -- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | -- SCU_RAM_COMMAND_CMD_DEMOD_START,0, -- NULL,1,&cmdResult)); -- -- /* update global DRXK data container */ --//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; -- -- /* All done, all OK */ -- } while(0); -- -- if (status<0) { -- printk("%s %d\n", __FUNCTION__, status); -- } -- return status; --} -- --static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode) --{ --#ifdef DRXK_QAM_TAPS --#define DRXK_QAMA_TAPS_SELECT --#include "drxk_filters.h" --#undef DRXK_QAMA_TAPS_SELECT --#else -- int status; --#endif -- -- //printk("%s\n", __FUNCTION__); -- do -- { -- /* added antenna switch */ -- SwitchAntennaToQAM(state); -- -- /* Ensure correct power-up mode */ -- CHK_ERROR(PowerUpQAM(state)); -- /* Reset QAM block */ -- CHK_ERROR(QAMResetQAM(state)); -- -- /* Setup IQM */ -- -- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); -- CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); -- -- /* Upload IQM Channel Filter settings by -- boot loader from ROM table */ -- switch (oMode) -- { -- case OM_QAM_ITU_A: -- CHK_ERROR(BLChainCmd(state, -- DRXK_BL_ROM_OFFSET_TAPS_ITU_A, -- DRXK_BLCC_NR_ELEMENTS_TAPS, -- DRXK_BLC_TIMEOUT)); -- break; -- case OM_QAM_ITU_C: -- CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, -- DRXK_BL_ROM_OFFSET_TAPS_ITU_C, -- DRXK_BLDC_NR_ELEMENTS_TAPS, -- DRXK_BLC_TIMEOUT)); -- CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, -- DRXK_BL_ROM_OFFSET_TAPS_ITU_C, -- DRXK_BLDC_NR_ELEMENTS_TAPS, -- DRXK_BLC_TIMEOUT)); -- break; -- default: -- status=-EINVAL; -- } -- CHK_ERROR (status); -- -- CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, -- (1 << IQM_CF_OUT_ENA_QAM__B))); -- CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); -- CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, -- ((1 << IQM_CF_MIDTAP_RE__B) | -- (1 << IQM_CF_MIDTAP_IM__B)))); -- -- CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); -- CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); -- CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); -- CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); -- CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); -- -- CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); -- CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); -- CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); -- CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); -- -- /* IQM Impulse Noise Processing Unit */ -- CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); -- CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); -- CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); -- CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); -- CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); -- CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); -- CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); -- -- /* turn on IQMAF. Must be done before setAgc**() */ -- CHK_ERROR(SetIqmAf(state, true)); -- CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); -- -- /* IQM will not be reset from here, sync ADC and update/init AGC */ -- CHK_ERROR(ADCSynchronization (state)); -- -- /* Set the FSM step period */ -- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); -- -- /* Halt SCU to enable safe non-atomic accesses */ -- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); -- -- /* No more resets of the IQM, current standard correctly set => -- now AGCs can be configured. */ -- -- CHK_ERROR(InitAGC(state,true)); -- CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); -- -- /* Configure AGC's */ -- CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); -- CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true)); -- -- /* Activate SCU to enable SCU commands */ -- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); -- } while (0); -- return status; --} -- --static int WriteGPIO(struct drxk_state *state) --{ -- int status; -- u16 value = 0; -- -- do { -- /* stop lock indicator process */ -- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); -- -- /* Write magic word to enable pdr reg write */ -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, -- SIO_TOP_COMM_KEY_KEY)); -- -- if (state->m_hasSAWSW) { -- /* write to io pad configuration register - output mode */ -- CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, -- state->m_GPIOCfg)); -- -- /* use corresponding bit in io data output registar */ -- CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value)); -- if (state->m_GPIO == 0) { -- value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ -- } else { -- value |= 0x8000; /* write one to 15th bit - 1st UIO */ -- } -- /* write back to io data output register */ -- CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value)); -- -- } -- /* Write magic word to disable pdr reg write */ -- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); -- } while (0); -- return status; --} -- --static int SwitchAntennaToQAM(struct drxk_state *state) --{ -- int status = -1; -- -- if (state->m_AntennaSwitchDVBTDVBC != 0) { -- if (state->m_GPIO != state->m_AntennaDVBC) { -- state->m_GPIO = state->m_AntennaDVBC; -- status = WriteGPIO(state); -- } -- } -- return status; --} -- --static int SwitchAntennaToDVBT(struct drxk_state *state) --{ -- int status = -1; -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); -- if (state->m_AntennaSwitchDVBTDVBC != 0) { -- if (state->m_GPIO != state->m_AntennaDVBT) { -- state->m_GPIO = state->m_AntennaDVBT; -- status = WriteGPIO(state); -- } -- } -- return status; --} -- -- --static int PowerDownDevice(struct drxk_state *state) --{ -- /* Power down to requested mode */ -- /* Backup some register settings */ -- /* Set pins with possible pull-ups connected to them in input mode */ -- /* Analog power down */ -- /* ADC power down */ -- /* Power down device */ -- int status; -- do { -- if (state->m_bPDownOpenBridge) { -- // Open I2C bridge before power down of DRXK -- CHK_ERROR(ConfigureI2CBridge(state, true)); -- } -- // driver 0.9.0 -- CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); -- -- CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK)); -- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY)); -- state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -- CHK_ERROR(HI_CfgCommand(state)); -- } -- while(0); -- -- if (status<0) { -- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); -- return -1; -- } -- return 0; --} -- --static int load_microcode(struct drxk_state *state, char *mc_name) --{ -- const struct firmware *fw = NULL; -- int err=0; -- -- err = request_firmware(&fw, mc_name, state->i2c->dev.parent); -- if (err < 0) { -- printk(KERN_ERR -- ": Could not load firmware file %s.\n", mc_name); -- printk(KERN_INFO -- ": Copy %s to your hotplug directory!\n", mc_name); -- return err; -- } -- err=DownloadMicrocode(state, fw->data, fw->size); -- release_firmware(fw); -- return err; --} -- --static int init_drxk(struct drxk_state *state) --{ -- int status; -- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; -- u16 driverVersion; -- -- //printk("init_drxk\n"); -- if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { -- do { -- CHK_ERROR(PowerUpDevice(state)); -- CHK_ERROR (DRXX_Open(state)); -- /* Soft reset of OFDM-, sys- and osc-clockdomain */ -- CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, -- SIO_CC_SOFT_RST_OFDM__M | -- SIO_CC_SOFT_RST_SYS__M | -- SIO_CC_SOFT_RST_OSC__M)); -- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); -- /* TODO is this needed, if yes how much delay in worst case scenario */ -- msleep(1); -- state->m_DRXK_A3_PATCH_CODE = true; -- CHK_ERROR(GetDeviceCapabilities(state)); -- -- /* Bridge delay, uses oscilator clock */ -- /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ -- /* SDA brdige delay */ -- state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000; -- /* Clipping */ -- if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) -- { -- state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; -- } -- /* SCL bridge delay, same as SDA for now */ -- state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; -- -- CHK_ERROR(InitHI(state)); -- /* disable various processes */ --#if NOA1ROM -- if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) ) --#endif -- { -- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); -- } -- -- /* disable MPEG port */ -- CHK_ERROR(MPEGTSDisable(state)); -- -- /* Stop AUD and SCU */ -- CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP)); -- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP)); -- -- /* enable token-ring bus through OFDM block for possible ucode upload */ -- CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); -- -- /* include boot loader section */ -- CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE)); -- CHK_ERROR(BLChainCmd(state, 0, 6, 100)); -- --#if 0 -- if (state->m_DRXK_A3_PATCH_CODE) -- CHK_ERROR(DownloadMicrocode(state, -- DRXK_A3_microcode, -- DRXK_A3_microcode_length)); --#else -- load_microcode(state, "drxk_a3.mc"); --#endif --#if NOA1ROM -- if (state->m_DRXK_A2_PATCH_CODE) -- CHK_ERROR(DownloadMicrocode(state, -- DRXK_A2_microcode, -- DRXK_A2_microcode_length)); --#endif -- /* disable token-ring bus through OFDM block for possible ucode upload */ -- CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); -- -- /* Run SCU for a little while to initialize microcode version numbers */ -- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); -- CHK_ERROR (DRXX_Open(state)); -- // added for test -- msleep(30); -- -- powerMode = DRXK_POWER_DOWN_OFDM; -- CHK_ERROR(CtrlPowerMode(state, &powerMode)); -- -- /* Stamp driver version number in SCU data RAM in BCD code -- Done to enable field application engineers to retreive drxdriver version -- via I2C from SCU RAM. -- Not using SCU command interface for SCU register access since no -- microcode may be present. -- */ -- driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) + -- (((DRXK_VERSION_MAJOR/10) % 10) << 8) + -- ((DRXK_VERSION_MAJOR%10) << 4) + -- (DRXK_VERSION_MINOR%10); -- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion )); -- driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) + -- (((DRXK_VERSION_PATCH/100) % 10) << 8) + -- (((DRXK_VERSION_PATCH/10) % 10) << 4) + -- (DRXK_VERSION_PATCH%10); -- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion )); -- -- printk("DRXK driver version:%d.%d.%d\n", -- DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH); -- -- /* Dirty fix of default values for ROM/PATCH microcode -- Dirty because this fix makes it impossible to setup suitable values -- before calling DRX_Open. This solution requires changes to RF AGC speed -- to be done via the CTRL function after calling DRX_Open */ -- -- // m_dvbtRfAgcCfg.speed=3; -- -- /* Reset driver debug flags to 0 */ -- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0)); -- /* driver 0.9.0 */ -- /* Setup FEC OC: -- NOTE: No more full FEC resets allowed afterwards!! */ -- CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP)); -- // MPEGTS functions are still the same -- CHK_ERROR(MPEGTSDtoInit(state)); -- CHK_ERROR(MPEGTSStop(state)); -- CHK_ERROR(MPEGTSConfigurePolarity(state)); -- CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput)); -- // added: configure GPIO -- CHK_ERROR(WriteGPIO(state)); -- -- state->m_DrxkState = DRXK_STOPPED; -- -- if (state->m_bPowerDown) { -- CHK_ERROR(PowerDownDevice(state)); -- state->m_DrxkState = DRXK_POWERED_DOWN; -- } -- else -- state->m_DrxkState = DRXK_STOPPED; -- } while(0); -- //printk("%s=%d\n", __FUNCTION__, status); -- } -- else -- { -- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n")); -- } -- -- return 0; --} -- --static void drxk_c_release(struct dvb_frontend* fe) --{ -- struct drxk_state *state=fe->demodulator_priv; -- printk("%s\n", __FUNCTION__); -- kfree(state); --} -- --static int drxk_c_init (struct dvb_frontend *fe) --{ -- struct drxk_state *state=fe->demodulator_priv; -- -- if (mutex_trylock(&state->ctlock)==0) -- return -EBUSY; -- SetOperationMode(state, OM_QAM_ITU_A); -- return 0; --} -- --static int drxk_c_sleep(struct dvb_frontend* fe) --{ -- struct drxk_state *state=fe->demodulator_priv; -- -- ShutDown(state); -- mutex_unlock(&state->ctlock); -- return 0; --} -- --static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable) --{ -- struct drxk_state *state = fe->demodulator_priv; -- -- //printk("drxk_gate %d\n", enable); -- return ConfigureI2CBridge(state, enable ? true : false); --} -- --#ifndef USE_API3 --static int drxk_set_parameters (struct dvb_frontend *fe) --#else --static int drxk_set_parameters (struct dvb_frontend *fe, -- struct dvb_frontend_parameters *p) --#endif --{ --#ifndef USE_API3 -- struct dtv_frontend_properties *p = &fe->dtv_property_cache; -- u32 delsys = p->delivery_system, old_delsys; --#endif -- struct drxk_state *state = fe->demodulator_priv; -- u32 IF; -- -- //printk("%s\n", __FUNCTION__); -- -- if (fe->ops.i2c_gate_ctrl) -- fe->ops.i2c_gate_ctrl(fe, 1); -- if (fe->ops.tuner_ops.set_params) --#ifndef USE_API3 -- fe->ops.tuner_ops.set_params(fe); --#else -- fe->ops.tuner_ops.set_params(fe, p); --#endif -- if (fe->ops.i2c_gate_ctrl) -- fe->ops.i2c_gate_ctrl(fe, 0); --#ifndef USE_API3 --#else -- state->param=*p; --#endif -- fe->ops.tuner_ops.get_if_frequency(fe, &IF); /* WTF is a frequency frequency? */ -- Start(state, 0, IF); -- -- //printk("%s IF=%d done\n", __FUNCTION__, IF); -- return 0; --} -- --static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) --{ -- //struct drxk_state *state = fe->demodulator_priv; -- //printk("%s\n", __FUNCTION__); -- return 0; --} -- --static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) --{ -- struct drxk_state *state = fe->demodulator_priv; -- u32 stat; -- -- *status=0; -- GetLockStatus(state, &stat, 0); -- if (stat==MPEG_LOCK) -- *status|=0x1f; -- if (stat==FEC_LOCK) -- *status|=0x0f; -- if (stat==DEMOD_LOCK) -- *status|=0x07; -- return 0; --} -- --static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) --{ -- //struct drxk_state *state = fe->demodulator_priv; -- *ber=0; -- return 0; --} -- --static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) --{ -- struct drxk_state *state = fe->demodulator_priv; -- u32 val; -- -- ReadIFAgc(state, &val); -- *strength = val & 0xffff;; -- return 0; --} -- --static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) --{ -- struct drxk_state *state = fe->demodulator_priv; -- s32 snr2; -- -- GetSignalToNoise(state, &snr2); -- *snr = snr2&0xffff; -- return 0; --} -- --static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) --{ -- struct drxk_state *state = fe->demodulator_priv; -- u16 err; -- -- DVBTQAMGetAccPktErr(state, &err); -- *ucblocks = (u32) err; -- return 0; --} -- --static int drxk_c_get_tune_settings(struct dvb_frontend *fe, -- struct dvb_frontend_tune_settings *sets) --{ -- sets->min_delay_ms=3000; -- sets->max_drift=0; -- sets->step_size=0; -- return 0; --} -- --static void drxk_t_release(struct dvb_frontend* fe) --{ -- //struct drxk_state *state=fe->demodulator_priv; -- //printk("%s\n", __FUNCTION__); -- //kfree(state); --} -- --static int drxk_t_init (struct dvb_frontend *fe) --{ -- struct drxk_state *state=fe->demodulator_priv; -- if (mutex_trylock(&state->ctlock)==0) -- return -EBUSY; -- //printk("%s\n", __FUNCTION__); -- SetOperationMode(state, OM_DVBT); -- //printk("%s done\n", __FUNCTION__); -- return 0; --} -- --static int drxk_t_sleep(struct dvb_frontend* fe) --{ -- struct drxk_state *state=fe->demodulator_priv; -- mutex_unlock(&state->ctlock); -- return 0; --} -- --static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) --{ -- //struct drxk_state *state = fe->demodulator_priv; -- //printk("%s\n", __FUNCTION__); -- return 0; --} -- --static struct dvb_frontend_ops drxk_c_ops = { -- .info = { -- .name = "DRXK DVB-C", -- .type = FE_QAM, -- .frequency_stepsize = 62500, -- .frequency_min = 47000000, -- .frequency_max = 862000000, -- .symbol_rate_min = 870000, -- .symbol_rate_max = 11700000, -- .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -- FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO -- }, -- .release = drxk_c_release, -- .init = drxk_c_init, -- .sleep = drxk_c_sleep, -- .i2c_gate_ctrl = drxk_gate_ctrl, -- -- .set_frontend = drxk_set_parameters, -- .get_frontend = drxk_c_get_frontend, -- .get_tune_settings = drxk_c_get_tune_settings, -- -- .read_status = drxk_read_status, -- .read_ber = drxk_read_ber, -- .read_signal_strength = drxk_read_signal_strength, -- .read_snr = drxk_read_snr, -- .read_ucblocks = drxk_read_ucblocks, --}; -- --static struct dvb_frontend_ops drxk_t_ops = { -- .info = { -- .name = "DRXK DVB-T", -- .type = FE_OFDM, -- .frequency_min = 47125000, -- .frequency_max = 865000000, -- .frequency_stepsize = 166667, -- .frequency_tolerance = 0, -- .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | -- FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | -- FE_CAN_FEC_AUTO | -- FE_CAN_QAM_16 | FE_CAN_QAM_64 | -- FE_CAN_QAM_AUTO | -- FE_CAN_TRANSMISSION_MODE_AUTO | -- FE_CAN_GUARD_INTERVAL_AUTO | -- FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | -- FE_CAN_MUTE_TS -- }, -- .release = drxk_t_release, -- .init = drxk_t_init, -- .sleep = drxk_t_sleep, -- .i2c_gate_ctrl = drxk_gate_ctrl, -- -- .set_frontend = drxk_set_parameters, -- .get_frontend = drxk_t_get_frontend, -- -- .read_status = drxk_read_status, -- .read_ber = drxk_read_ber, -- .read_signal_strength = drxk_read_signal_strength, -- .read_snr = drxk_read_snr, -- .read_ucblocks = drxk_read_ucblocks, --}; -- --struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, -- struct dvb_frontend **fe_t) --{ -- struct drxk_state *state = NULL; -- -- state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL); -- if (!state) -- return NULL; -- -- state->i2c=i2c; -- state->demod_address=adr; -- -- mutex_init(&state->mutex); -- mutex_init(&state->ctlock); -- -- memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops)); -- memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops)); -- state->c_frontend.demodulator_priv=state; -- state->t_frontend.demodulator_priv=state; -- -- init_state(state); -- if (init_drxk(state)<0) -- goto error; -- *fe_t = &state->t_frontend; -- return &state->c_frontend; -- --error: -- printk("drxk: not found\n"); -- kfree(state); -- return NULL; --} -- --MODULE_DESCRIPTION("DRX-K driver"); --MODULE_AUTHOR("Ralph Metzler"); --MODULE_LICENSE("GPL"); -- --EXPORT_SYMBOL(drxk_attach); -+/* -+ * drxk_hard: DRX-K DVB-C/T demodulator driver -+ * -+ * Copyright (C) 2010-2011 Digital Devices GmbH -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dvb_frontend.h" -+#include "drxk.h" -+#include "drxk_hard.h" -+ -+static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); -+static int PowerDownQAM(struct drxk_state *state); -+static int SetDVBTStandard(struct drxk_state *state, -+ enum OperationMode oMode); -+static int SetQAMStandard(struct drxk_state *state, -+ enum OperationMode oMode); -+static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset); -+static int SetDVBTStandard(struct drxk_state *state, -+ enum OperationMode oMode); -+static int DVBTStart(struct drxk_state *state); -+static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset); -+static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); -+static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); -+static int SwitchAntennaToQAM(struct drxk_state *state); -+static int SwitchAntennaToDVBT(struct drxk_state *state); -+ -+static bool IsDVBT(struct drxk_state *state) -+{ -+ return state->m_OperationMode == OM_DVBT; -+} -+ -+static bool IsQAM(struct drxk_state *state) -+{ -+ return state->m_OperationMode == OM_QAM_ITU_A || -+ state->m_OperationMode == OM_QAM_ITU_B || -+ state->m_OperationMode == OM_QAM_ITU_C; -+} -+ -+bool IsA1WithPatchCode(struct drxk_state *state) -+{ -+ return state->m_DRXK_A1_PATCH_CODE; -+} -+ -+bool IsA1WithRomCode(struct drxk_state *state) -+{ -+ return state->m_DRXK_A1_ROM_CODE; -+} -+ -+#define NOA1ROM 0 -+ -+#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) -+#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) -+ -+#define DEFAULT_MER_83 165 -+#define DEFAULT_MER_93 250 -+ -+#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH -+#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) -+#endif -+ -+#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH -+#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) -+#endif -+ -+#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 -+#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 -+ -+#ifndef DRXK_KI_RAGC_ATV -+#define DRXK_KI_RAGC_ATV 4 -+#endif -+#ifndef DRXK_KI_IAGC_ATV -+#define DRXK_KI_IAGC_ATV 6 -+#endif -+#ifndef DRXK_KI_DAGC_ATV -+#define DRXK_KI_DAGC_ATV 7 -+#endif -+ -+#ifndef DRXK_KI_RAGC_QAM -+#define DRXK_KI_RAGC_QAM 3 -+#endif -+#ifndef DRXK_KI_IAGC_QAM -+#define DRXK_KI_IAGC_QAM 4 -+#endif -+#ifndef DRXK_KI_DAGC_QAM -+#define DRXK_KI_DAGC_QAM 7 -+#endif -+#ifndef DRXK_KI_RAGC_DVBT -+#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) -+#endif -+#ifndef DRXK_KI_IAGC_DVBT -+#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) -+#endif -+#ifndef DRXK_KI_DAGC_DVBT -+#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) -+#endif -+ -+#ifndef DRXK_AGC_DAC_OFFSET -+#define DRXK_AGC_DAC_OFFSET (0x800) -+#endif -+ -+#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ -+#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) -+#endif -+ -+#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ -+#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) -+#endif -+ -+#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ -+#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) -+#endif -+ -+#ifndef DRXK_QAM_SYMBOLRATE_MAX -+#define DRXK_QAM_SYMBOLRATE_MAX (7233000) -+#endif -+ -+#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 -+#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 -+#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 -+#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 -+#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 -+#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 -+#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 -+#define DRXK_BL_ROM_OFFSET_UCODE 0 -+ -+#define DRXK_BLC_TIMEOUT 100 -+ -+#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 -+#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 -+ -+#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 -+ -+#ifndef DRXK_OFDM_NE_NOTCH_WIDTH -+#define DRXK_OFDM_NE_NOTCH_WIDTH (4) -+#endif -+ -+#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) -+#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) -+#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) -+#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) -+#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) -+ -+static unsigned int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "enable debug messages"); -+ -+#define dprintk(level, fmt, arg...) do { \ -+if (debug >= level) \ -+ printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \ -+} while (0) -+ -+ -+static inline u32 MulDiv32(u32 a, u32 b, u32 c) -+{ -+ u64 tmp64; -+ -+ tmp64 = (u64) a * (u64) b; -+ do_div(tmp64, c); -+ -+ return (u32) tmp64; -+} -+ -+inline u32 Frac28a(u32 a, u32 c) -+{ -+ int i = 0; -+ u32 Q1 = 0; -+ u32 R0 = 0; -+ -+ R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ -+ Q1 = a / c; /* integer part, only the 4 least significant bits -+ will be visible in the result */ -+ -+ /* division using radix 16, 7 nibbles in the result */ -+ for (i = 0; i < 7; i++) { -+ Q1 = (Q1 << 4) | (R0 / c); -+ R0 = (R0 % c) << 4; -+ } -+ /* rounding */ -+ if ((R0 >> 3) >= c) -+ Q1++; -+ -+ return Q1; -+} -+ -+static u32 Log10Times100(u32 x) -+{ -+ static const u8 scale = 15; -+ static const u8 indexWidth = 5; -+ u8 i = 0; -+ u32 y = 0; -+ u32 d = 0; -+ u32 k = 0; -+ u32 r = 0; -+ /* -+ log2lut[n] = (1< 0; k--) { -+ if (x & (((u32) 1) << scale)) -+ break; -+ x <<= 1; -+ } -+ } else { -+ for (k = scale; k < 31; k++) { -+ if ((x & (((u32) (-1)) << (scale + 1))) == 0) -+ break; -+ x >>= 1; -+ } -+ } -+ /* -+ Now x has binary point between bit[scale] and bit[scale-1] -+ and 1.0 <= x < 2.0 */ -+ -+ /* correction for divison: log(x) = log(x/y)+log(y) */ -+ y = k * ((((u32) 1) << scale) * 200); -+ -+ /* remove integer part */ -+ x &= ((((u32) 1) << scale) - 1); -+ /* get index */ -+ i = (u8) (x >> (scale - indexWidth)); -+ /* compute delta (x - a) */ -+ d = x & ((((u32) 1) << (scale - indexWidth)) - 1); -+ /* compute log, multiplication (d* (..)) must be within range ! */ -+ y += log2lut[i] + -+ ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); -+ /* Conver to log10() */ -+ y /= 108853; /* (log2(10) << scale) */ -+ r = (y >> 1); -+ /* rounding */ -+ if (y & ((u32) 1)) -+ r++; -+ return r; -+} -+ -+/****************************************************************************/ -+/* I2C **********************************************************************/ -+/****************************************************************************/ -+ -+static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) -+{ -+ struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, -+ .buf = val, .len = 1} -+ }; -+ -+ return i2c_transfer(adapter, msgs, 1); -+} -+ -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ int status; -+ struct i2c_msg msg = { -+ .addr = adr, .flags = 0, .buf = data, .len = len }; -+ -+ dprintk(3, ":"); -+ if (debug > 2) { -+ int i; -+ for (i = 0; i < len; i++) -+ printk(KERN_CONT " %02x", data[i]); -+ printk(KERN_CONT "\n"); -+ } -+ status = i2c_transfer(adap, &msg, 1); -+ if (status >= 0 && status != 1) -+ status = -EIO; -+ -+ if (status < 0) -+ printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr); -+ -+ return status; -+} -+ -+static int i2c_read(struct i2c_adapter *adap, -+ u8 adr, u8 *msg, int len, u8 *answ, int alen) -+{ -+ int status; -+ struct i2c_msg msgs[2] = { -+ {.addr = adr, .flags = 0, -+ .buf = msg, .len = len}, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = answ, .len = alen} -+ }; -+ -+ status = i2c_transfer(adap, msgs, 2); -+ if (status != 2) { -+ if (debug > 2) -+ printk(KERN_CONT ": ERROR!\n"); -+ if (status >= 0) -+ status = -EIO; -+ -+ printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr); -+ return status; -+ } -+ if (debug > 2) { -+ int i; -+ dprintk(2, ": read from"); -+ for (i = 0; i < len; i++) -+ printk(KERN_CONT " %02x", msg[i]); -+ printk(KERN_CONT ", value = "); -+ for (i = 0; i < alen; i++) -+ printk(KERN_CONT " %02x", answ[i]); -+ printk(KERN_CONT "\n"); -+ } -+ return 0; -+} -+ -+static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) -+{ -+ int status; -+ u8 adr = state->demod_address, mm1[4], mm2[2], len; -+ -+ if (state->single_master) -+ flags |= 0xC0; -+ -+ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -+ mm1[0] = (((reg << 1) & 0xFF) | 0x01); -+ mm1[1] = ((reg >> 16) & 0xFF); -+ mm1[2] = ((reg >> 24) & 0xFF) | flags; -+ mm1[3] = ((reg >> 7) & 0xFF); -+ len = 4; -+ } else { -+ mm1[0] = ((reg << 1) & 0xFF); -+ mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -+ len = 2; -+ } -+ dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); -+ status = i2c_read(state->i2c, adr, mm1, len, mm2, 2); -+ if (status < 0) -+ return status; -+ if (data) -+ *data = mm2[0] | (mm2[1] << 8); -+ -+ return 0; -+} -+ -+static int read16(struct drxk_state *state, u32 reg, u16 *data) -+{ -+ return read16_flags(state, reg, data, 0); -+} -+ -+static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) -+{ -+ int status; -+ u8 adr = state->demod_address, mm1[4], mm2[4], len; -+ -+ if (state->single_master) -+ flags |= 0xC0; -+ -+ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -+ mm1[0] = (((reg << 1) & 0xFF) | 0x01); -+ mm1[1] = ((reg >> 16) & 0xFF); -+ mm1[2] = ((reg >> 24) & 0xFF) | flags; -+ mm1[3] = ((reg >> 7) & 0xFF); -+ len = 4; -+ } else { -+ mm1[0] = ((reg << 1) & 0xFF); -+ mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -+ len = 2; -+ } -+ dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); -+ status = i2c_read(state->i2c, adr, mm1, len, mm2, 4); -+ if (status < 0) -+ return status; -+ if (data) -+ *data = mm2[0] | (mm2[1] << 8) | -+ (mm2[2] << 16) | (mm2[3] << 24); -+ -+ return 0; -+} -+ -+static int read32(struct drxk_state *state, u32 reg, u32 *data) -+{ -+ return read32_flags(state, reg, data, 0); -+} -+ -+static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) -+{ -+ u8 adr = state->demod_address, mm[6], len; -+ -+ if (state->single_master) -+ flags |= 0xC0; -+ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -+ mm[0] = (((reg << 1) & 0xFF) | 0x01); -+ mm[1] = ((reg >> 16) & 0xFF); -+ mm[2] = ((reg >> 24) & 0xFF) | flags; -+ mm[3] = ((reg >> 7) & 0xFF); -+ len = 4; -+ } else { -+ mm[0] = ((reg << 1) & 0xFF); -+ mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -+ len = 2; -+ } -+ mm[len] = data & 0xff; -+ mm[len + 1] = (data >> 8) & 0xff; -+ -+ dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); -+ return i2c_write(state->i2c, adr, mm, len + 2); -+} -+ -+static int write16(struct drxk_state *state, u32 reg, u16 data) -+{ -+ return write16_flags(state, reg, data, 0); -+} -+ -+static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) -+{ -+ u8 adr = state->demod_address, mm[8], len; -+ -+ if (state->single_master) -+ flags |= 0xC0; -+ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { -+ mm[0] = (((reg << 1) & 0xFF) | 0x01); -+ mm[1] = ((reg >> 16) & 0xFF); -+ mm[2] = ((reg >> 24) & 0xFF) | flags; -+ mm[3] = ((reg >> 7) & 0xFF); -+ len = 4; -+ } else { -+ mm[0] = ((reg << 1) & 0xFF); -+ mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); -+ len = 2; -+ } -+ mm[len] = data & 0xff; -+ mm[len + 1] = (data >> 8) & 0xff; -+ mm[len + 2] = (data >> 16) & 0xff; -+ mm[len + 3] = (data >> 24) & 0xff; -+ dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); -+ -+ return i2c_write(state->i2c, adr, mm, len + 4); -+} -+ -+static int write32(struct drxk_state *state, u32 reg, u32 data) -+{ -+ return write32_flags(state, reg, data, 0); -+} -+ -+static int write_block(struct drxk_state *state, u32 Address, -+ const int BlockSize, const u8 pBlock[]) -+{ -+ int status = 0, BlkSize = BlockSize; -+ u8 Flags = 0; -+ -+ if (state->single_master) -+ Flags |= 0xC0; -+ -+ while (BlkSize > 0) { -+ int Chunk = BlkSize > state->m_ChunkSize ? -+ state->m_ChunkSize : BlkSize; -+ u8 *AdrBuf = &state->Chunk[0]; -+ u32 AdrLength = 0; -+ -+ if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { -+ AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); -+ AdrBuf[1] = ((Address >> 16) & 0xFF); -+ AdrBuf[2] = ((Address >> 24) & 0xFF); -+ AdrBuf[3] = ((Address >> 7) & 0xFF); -+ AdrBuf[2] |= Flags; -+ AdrLength = 4; -+ if (Chunk == state->m_ChunkSize) -+ Chunk -= 2; -+ } else { -+ AdrBuf[0] = ((Address << 1) & 0xFF); -+ AdrBuf[1] = (((Address >> 16) & 0x0F) | -+ ((Address >> 18) & 0xF0)); -+ AdrLength = 2; -+ } -+ memcpy(&state->Chunk[AdrLength], pBlock, Chunk); -+ dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags); -+ if (debug > 1) { -+ int i; -+ if (pBlock) -+ for (i = 0; i < Chunk; i++) -+ printk(KERN_CONT " %02x", pBlock[i]); -+ printk(KERN_CONT "\n"); -+ } -+ status = i2c_write(state->i2c, state->demod_address, -+ &state->Chunk[0], Chunk + AdrLength); -+ if (status < 0) { -+ printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n", -+ __func__, Address); -+ break; -+ } -+ pBlock += Chunk; -+ Address += (Chunk >> 1); -+ BlkSize -= Chunk; -+ } -+ return status; -+} -+ -+#ifndef DRXK_MAX_RETRIES_POWERUP -+#define DRXK_MAX_RETRIES_POWERUP 20 -+#endif -+ -+int PowerUpDevice(struct drxk_state *state) -+{ -+ int status; -+ u8 data = 0; -+ u16 retryCount = 0; -+ -+ dprintk(1, "\n"); -+ -+ status = i2c_read1(state->i2c, state->demod_address, &data); -+ if (status < 0) { -+ do { -+ data = 0; -+ status = i2c_write(state->i2c, state->demod_address, -+ &data, 1); -+ msleep(10); -+ retryCount++; -+ if (status < 0) -+ continue; -+ status = i2c_read1(state->i2c, state->demod_address, -+ &data); -+ } while (status < 0 && -+ (retryCount < DRXK_MAX_RETRIES_POWERUP)); -+ if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP) -+ goto error; -+ } -+ -+ /* Make sure all clk domains are active */ -+ status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); -+ if (status < 0) -+ goto error; -+ /* Enable pll lock tests */ -+ status = write16(state, SIO_CC_PLL_LOCK__A, 1); -+ if (status < 0) -+ goto error; -+ -+ state->m_currentPowerMode = DRX_POWER_UP; -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+ -+static int init_state(struct drxk_state *state) -+{ -+ /* -+ * FIXME: most (all?) of the values bellow should be moved into -+ * struct drxk_config, as they are probably board-specific -+ */ -+ u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; -+ u32 ulVSBIfAgcOutputLevel = 0; -+ u32 ulVSBIfAgcMinLevel = 0; -+ u32 ulVSBIfAgcMaxLevel = 0x7FFF; -+ u32 ulVSBIfAgcSpeed = 3; -+ -+ u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; -+ u32 ulVSBRfAgcOutputLevel = 0; -+ u32 ulVSBRfAgcMinLevel = 0; -+ u32 ulVSBRfAgcMaxLevel = 0x7FFF; -+ u32 ulVSBRfAgcSpeed = 3; -+ u32 ulVSBRfAgcTop = 9500; -+ u32 ulVSBRfAgcCutOffCurrent = 4000; -+ -+ u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; -+ u32 ulATVIfAgcOutputLevel = 0; -+ u32 ulATVIfAgcMinLevel = 0; -+ u32 ulATVIfAgcMaxLevel = 0; -+ u32 ulATVIfAgcSpeed = 3; -+ -+ u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; -+ u32 ulATVRfAgcOutputLevel = 0; -+ u32 ulATVRfAgcMinLevel = 0; -+ u32 ulATVRfAgcMaxLevel = 0; -+ u32 ulATVRfAgcTop = 9500; -+ u32 ulATVRfAgcCutOffCurrent = 4000; -+ u32 ulATVRfAgcSpeed = 3; -+ -+ u32 ulQual83 = DEFAULT_MER_83; -+ u32 ulQual93 = DEFAULT_MER_93; -+ -+ u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -+ u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; -+ -+ /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ -+ /* io_pad_cfg_mode output mode is drive always */ -+ /* io_pad_cfg_drive is set to power 2 (23 mA) */ -+ u32 ulGPIOCfg = 0x0113; -+ u32 ulInvertTSClock = 0; -+ u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; -+ u32 ulDVBTBitrate = 50000000; -+ u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; -+ -+ u32 ulInsertRSByte = 0; -+ -+ u32 ulRfMirror = 1; -+ u32 ulPowerDown = 0; -+ -+ dprintk(1, "\n"); -+ -+ state->m_hasLNA = false; -+ state->m_hasDVBT = false; -+ state->m_hasDVBC = false; -+ state->m_hasATV = false; -+ state->m_hasOOB = false; -+ state->m_hasAudio = false; -+ -+ if (!state->m_ChunkSize) -+ state->m_ChunkSize = 124; -+ -+ state->m_oscClockFreq = 0; -+ state->m_smartAntInverted = false; -+ state->m_bPDownOpenBridge = false; -+ -+ /* real system clock frequency in kHz */ -+ state->m_sysClockFreq = 151875; -+ /* Timing div, 250ns/Psys */ -+ /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ -+ state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * -+ HI_I2C_DELAY) / 1000; -+ /* Clipping */ -+ if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) -+ state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; -+ state->m_HICfgWakeUpKey = (state->demod_address << 1); -+ /* port/bridge/power down ctrl */ -+ state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; -+ -+ state->m_bPowerDown = (ulPowerDown != 0); -+ -+ state->m_DRXK_A1_PATCH_CODE = false; -+ state->m_DRXK_A1_ROM_CODE = false; -+ state->m_DRXK_A2_ROM_CODE = false; -+ state->m_DRXK_A3_ROM_CODE = false; -+ state->m_DRXK_A2_PATCH_CODE = false; -+ state->m_DRXK_A3_PATCH_CODE = false; -+ -+ /* Init AGC and PGA parameters */ -+ /* VSB IF */ -+ state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); -+ state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); -+ state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); -+ state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); -+ state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); -+ state->m_vsbPgaCfg = 140; -+ -+ /* VSB RF */ -+ state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); -+ state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); -+ state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); -+ state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); -+ state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); -+ state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); -+ state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); -+ state->m_vsbPreSawCfg.reference = 0x07; -+ state->m_vsbPreSawCfg.usePreSaw = true; -+ -+ state->m_Quality83percent = DEFAULT_MER_83; -+ state->m_Quality93percent = DEFAULT_MER_93; -+ if (ulQual93 <= 500 && ulQual83 < ulQual93) { -+ state->m_Quality83percent = ulQual83; -+ state->m_Quality93percent = ulQual93; -+ } -+ -+ /* ATV IF */ -+ state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); -+ state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); -+ state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); -+ state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); -+ state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); -+ -+ /* ATV RF */ -+ state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); -+ state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); -+ state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); -+ state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); -+ state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); -+ state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); -+ state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); -+ state->m_atvPreSawCfg.reference = 0x04; -+ state->m_atvPreSawCfg.usePreSaw = true; -+ -+ -+ /* DVBT RF */ -+ state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; -+ state->m_dvbtRfAgcCfg.outputLevel = 0; -+ state->m_dvbtRfAgcCfg.minOutputLevel = 0; -+ state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; -+ state->m_dvbtRfAgcCfg.top = 0x2100; -+ state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; -+ state->m_dvbtRfAgcCfg.speed = 1; -+ -+ -+ /* DVBT IF */ -+ state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; -+ state->m_dvbtIfAgcCfg.outputLevel = 0; -+ state->m_dvbtIfAgcCfg.minOutputLevel = 0; -+ state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; -+ state->m_dvbtIfAgcCfg.top = 13424; -+ state->m_dvbtIfAgcCfg.cutOffCurrent = 0; -+ state->m_dvbtIfAgcCfg.speed = 3; -+ state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; -+ state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; -+ /* state->m_dvbtPgaCfg = 140; */ -+ -+ state->m_dvbtPreSawCfg.reference = 4; -+ state->m_dvbtPreSawCfg.usePreSaw = false; -+ -+ /* QAM RF */ -+ state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; -+ state->m_qamRfAgcCfg.outputLevel = 0; -+ state->m_qamRfAgcCfg.minOutputLevel = 6023; -+ state->m_qamRfAgcCfg.maxOutputLevel = 27000; -+ state->m_qamRfAgcCfg.top = 0x2380; -+ state->m_qamRfAgcCfg.cutOffCurrent = 4000; -+ state->m_qamRfAgcCfg.speed = 3; -+ -+ /* QAM IF */ -+ state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; -+ state->m_qamIfAgcCfg.outputLevel = 0; -+ state->m_qamIfAgcCfg.minOutputLevel = 0; -+ state->m_qamIfAgcCfg.maxOutputLevel = 9000; -+ state->m_qamIfAgcCfg.top = 0x0511; -+ state->m_qamIfAgcCfg.cutOffCurrent = 0; -+ state->m_qamIfAgcCfg.speed = 3; -+ state->m_qamIfAgcCfg.IngainTgtMax = 5119; -+ state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; -+ -+ state->m_qamPgaCfg = 140; -+ state->m_qamPreSawCfg.reference = 4; -+ state->m_qamPreSawCfg.usePreSaw = false; -+ -+ state->m_OperationMode = OM_NONE; -+ state->m_DrxkState = DRXK_UNINITIALIZED; -+ -+ /* MPEG output configuration */ -+ state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ -+ state->m_insertRSByte = false; /* If TRUE; insert RS byte */ -+ state->m_invertDATA = false; /* If TRUE; invert DATA signals */ -+ state->m_invertERR = false; /* If TRUE; invert ERR signal */ -+ state->m_invertSTR = false; /* If TRUE; invert STR signals */ -+ state->m_invertVAL = false; /* If TRUE; invert VAL signals */ -+ state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ -+ -+ /* If TRUE; static MPEG clockrate will be used; -+ otherwise clockrate will adapt to the bitrate of the TS */ -+ -+ state->m_DVBTBitrate = ulDVBTBitrate; -+ state->m_DVBCBitrate = ulDVBCBitrate; -+ -+ state->m_TSDataStrength = (ulTSDataStrength & 0x07); -+ -+ /* Maximum bitrate in b/s in case static clockrate is selected */ -+ state->m_mpegTsStaticBitrate = 19392658; -+ state->m_disableTEIhandling = false; -+ -+ if (ulInsertRSByte) -+ state->m_insertRSByte = true; -+ -+ state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -+ if (ulMpegLockTimeOut < 10000) -+ state->m_MpegLockTimeOut = ulMpegLockTimeOut; -+ state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; -+ if (ulDemodLockTimeOut < 10000) -+ state->m_DemodLockTimeOut = ulDemodLockTimeOut; -+ -+ /* QAM defaults */ -+ state->m_Constellation = DRX_CONSTELLATION_AUTO; -+ state->m_qamInterleaveMode = DRXK_QAM_I12_J17; -+ state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */ -+ state->m_fecRsPrescale = 1; -+ -+ state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; -+ state->m_agcFastClipCtrlDelay = 0; -+ -+ state->m_GPIOCfg = (ulGPIOCfg); -+ -+ state->m_bPowerDown = false; -+ state->m_currentPowerMode = DRX_POWER_DOWN; -+ -+ state->m_rfmirror = (ulRfMirror == 0); -+ state->m_IfAgcPol = false; -+ return 0; -+} -+ -+static int DRXX_Open(struct drxk_state *state) -+{ -+ int status = 0; -+ u32 jtag = 0; -+ u16 bid = 0; -+ u16 key = 0; -+ -+ dprintk(1, "\n"); -+ /* stop lock indicator process */ -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ if (status < 0) -+ goto error; -+ /* Check device id */ -+ status = read16(state, SIO_TOP_COMM_KEY__A, &key); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); -+ if (status < 0) -+ goto error; -+ status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); -+ if (status < 0) -+ goto error; -+ status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_TOP_COMM_KEY__A, key); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int GetDeviceCapabilities(struct drxk_state *state) -+{ -+ u16 sioPdrOhwCfg = 0; -+ u32 sioTopJtagidLo = 0; -+ int status; -+ const char *spin = ""; -+ -+ dprintk(1, "\n"); -+ -+ /* driver 0.9.0 */ -+ /* stop lock indicator process */ -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); -+ if (status < 0) -+ goto error; -+ status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); -+ if (status < 0) -+ goto error; -+ -+ switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { -+ case 0: -+ /* ignore (bypass ?) */ -+ break; -+ case 1: -+ /* 27 MHz */ -+ state->m_oscClockFreq = 27000; -+ break; -+ case 2: -+ /* 20.25 MHz */ -+ state->m_oscClockFreq = 20250; -+ break; -+ case 3: -+ /* 4 MHz */ -+ state->m_oscClockFreq = 20250; -+ break; -+ default: -+ printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n"); -+ return -EINVAL; -+ } -+ /* -+ Determine device capabilities -+ Based on pinning v14 -+ */ -+ status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); -+ if (status < 0) -+ goto error; -+ -+printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo); -+ -+ /* driver 0.9.0 */ -+ switch ((sioTopJtagidLo >> 29) & 0xF) { -+ case 0: -+ state->m_deviceSpin = DRXK_SPIN_A1; -+ spin = "A1"; -+ break; -+ case 2: -+ state->m_deviceSpin = DRXK_SPIN_A2; -+ spin = "A2"; -+ break; -+ case 3: -+ state->m_deviceSpin = DRXK_SPIN_A3; -+ spin = "A3"; -+ break; -+ default: -+ state->m_deviceSpin = DRXK_SPIN_UNKNOWN; -+ status = -EINVAL; -+ printk(KERN_ERR "drxk: Spin %d unknown\n", -+ (sioTopJtagidLo >> 29) & 0xF); -+ goto error2; -+ } -+ switch ((sioTopJtagidLo >> 12) & 0xFF) { -+ case 0x13: -+ /* typeId = DRX3913K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = false; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = false; -+ state->m_hasGPIO1 = false; -+ state->m_hasIRQN = false; -+ break; -+ case 0x15: -+ /* typeId = DRX3915K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = false; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; -+ break; -+ case 0x16: -+ /* typeId = DRX3916K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = false; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; -+ break; -+ case 0x18: -+ /* typeId = DRX3918K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = false; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; -+ break; -+ case 0x21: -+ /* typeId = DRX3921K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; -+ break; -+ case 0x23: -+ /* typeId = DRX3923K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; -+ break; -+ case 0x25: -+ /* typeId = DRX3925K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; -+ break; -+ case 0x26: -+ /* typeId = DRX3926K_TYPE_ID */ -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; -+ break; -+ default: -+ printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n", -+ ((sioTopJtagidLo >> 12) & 0xFF)); -+ status = -EINVAL; -+ goto error2; -+ } -+ -+ printk(KERN_INFO -+ "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", -+ ((sioTopJtagidLo >> 12) & 0xFF), spin, -+ state->m_oscClockFreq / 1000, -+ state->m_oscClockFreq % 1000); -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+error2: -+ return status; -+} -+ -+static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) -+{ -+ int status; -+ bool powerdown_cmd; -+ -+ dprintk(1, "\n"); -+ -+ /* Write command */ -+ status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); -+ if (status < 0) -+ goto error; -+ if (cmd == SIO_HI_RA_RAM_CMD_RESET) -+ msleep(1); -+ -+ powerdown_cmd = -+ (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && -+ ((state->m_HICfgCtrl) & -+ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == -+ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); -+ if (powerdown_cmd == false) { -+ /* Wait until command rdy */ -+ u32 retryCount = 0; -+ u16 waitCmd; -+ -+ do { -+ msleep(1); -+ retryCount += 1; -+ status = read16(state, SIO_HI_RA_RAM_CMD__A, -+ &waitCmd); -+ } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES) -+ && (waitCmd != 0)); -+ if (status < 0) -+ goto error; -+ status = read16(state, SIO_HI_RA_RAM_RES__A, pResult); -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static int HI_CfgCommand(struct drxk_state *state) -+{ -+ int status; -+ -+ dprintk(1, "\n"); -+ -+ mutex_lock(&state->mutex); -+ -+ status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); -+ if (status < 0) -+ goto error; -+ status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); -+ if (status < 0) -+ goto error; -+ -+ state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -+error: -+ mutex_unlock(&state->mutex); -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int InitHI(struct drxk_state *state) -+{ -+ dprintk(1, "\n"); -+ -+ state->m_HICfgWakeUpKey = (state->demod_address << 1); -+ state->m_HICfgTimeout = 0x96FF; -+ /* port/bridge/power down ctrl */ -+ state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; -+ -+ return HI_CfgCommand(state); -+} -+ -+static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) -+{ -+ int status = -1; -+ u16 sioPdrMclkCfg = 0; -+ u16 sioPdrMdxCfg = 0; -+ u16 err_cfg = 0; -+ -+ dprintk(1, ": mpeg %s, %s mode\n", -+ mpegEnable ? "enable" : "disable", -+ state->m_enableParallel ? "parallel" : "serial"); -+ -+ /* stop lock indicator process */ -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ if (status < 0) -+ goto error; -+ -+ /* MPEG TS pad configuration */ -+ status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); -+ if (status < 0) -+ goto error; -+ -+ if (mpegEnable == false) { -+ /* Set MPEG TS pads to inputmode */ -+ status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ } else { -+ /* Enable MPEG output */ -+ sioPdrMdxCfg = -+ ((state->m_TSDataStrength << -+ SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); -+ sioPdrMclkCfg = ((state->m_TSClockkStrength << -+ SIO_PDR_MCLK_CFG_DRIVE__B) | -+ 0x0003); -+ -+ status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ -+ if (state->enable_merr_cfg) -+ err_cfg = sioPdrMdxCfg; -+ -+ status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); -+ if (status < 0) -+ goto error; -+ -+ if (state->m_enableParallel == true) { -+ /* paralel -> enable MD1 to MD7 */ -+ status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ } else { -+ sioPdrMdxCfg = ((state->m_TSDataStrength << -+ SIO_PDR_MD0_CFG_DRIVE__B) -+ | 0x0003); -+ /* serial -> disable MD1 to MD7 */ -+ status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ } -+ status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg); -+ if (status < 0) -+ goto error; -+ } -+ /* Enable MB output over MPEG pads and ctl input */ -+ status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); -+ if (status < 0) -+ goto error; -+ /* Write nomagic word to enable pdr reg write */ -+ status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int MPEGTSDisable(struct drxk_state *state) -+{ -+ dprintk(1, "\n"); -+ -+ return MPEGTSConfigurePins(state, false); -+} -+ -+static int BLChainCmd(struct drxk_state *state, -+ u16 romOffset, u16 nrOfElements, u32 timeOut) -+{ -+ u16 blStatus = 0; -+ int status; -+ unsigned long end; -+ -+ dprintk(1, "\n"); -+ mutex_lock(&state->mutex); -+ status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); -+ if (status < 0) -+ goto error; -+ -+ end = jiffies + msecs_to_jiffies(timeOut); -+ do { -+ msleep(1); -+ status = read16(state, SIO_BL_STATUS__A, &blStatus); -+ if (status < 0) -+ goto error; -+ } while ((blStatus == 0x1) && -+ ((time_is_after_jiffies(end)))); -+ -+ if (blStatus == 0x1) { -+ printk(KERN_ERR "drxk: SIO not ready\n"); -+ status = -EINVAL; -+ goto error2; -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+error2: -+ mutex_unlock(&state->mutex); -+ return status; -+} -+ -+ -+static int DownloadMicrocode(struct drxk_state *state, -+ const u8 pMCImage[], u32 Length) -+{ -+ const u8 *pSrc = pMCImage; -+ u32 Address; -+ u16 nBlocks; -+ u16 BlockSize; -+ u32 offset = 0; -+ u32 i; -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ -+ /* down the drain (we don't care about MAGIC_WORD) */ -+#if 0 -+ /* For future reference */ -+ Drain = (pSrc[0] << 8) | pSrc[1]; -+#endif -+ pSrc += sizeof(u16); -+ offset += sizeof(u16); -+ nBlocks = (pSrc[0] << 8) | pSrc[1]; -+ pSrc += sizeof(u16); -+ offset += sizeof(u16); -+ -+ for (i = 0; i < nBlocks; i += 1) { -+ Address = (pSrc[0] << 24) | (pSrc[1] << 16) | -+ (pSrc[2] << 8) | pSrc[3]; -+ pSrc += sizeof(u32); -+ offset += sizeof(u32); -+ -+ BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); -+ pSrc += sizeof(u16); -+ offset += sizeof(u16); -+ -+#if 0 -+ /* For future reference */ -+ Flags = (pSrc[0] << 8) | pSrc[1]; -+#endif -+ pSrc += sizeof(u16); -+ offset += sizeof(u16); -+ -+#if 0 -+ /* For future reference */ -+ BlockCRC = (pSrc[0] << 8) | pSrc[1]; -+#endif -+ pSrc += sizeof(u16); -+ offset += sizeof(u16); -+ -+ if (offset + BlockSize > Length) { -+ printk(KERN_ERR "drxk: Firmware is corrupted.\n"); -+ return -EINVAL; -+ } -+ -+ status = write_block(state, Address, BlockSize, pSrc); -+ if (status < 0) { -+ printk(KERN_ERR "drxk: Error %d while loading firmware\n", status); -+ break; -+ } -+ pSrc += BlockSize; -+ offset += BlockSize; -+ } -+ return status; -+} -+ -+static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) -+{ -+ int status; -+ u16 data = 0; -+ u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; -+ u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; -+ unsigned long end; -+ -+ dprintk(1, "\n"); -+ -+ if (enable == false) { -+ desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; -+ desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; -+ } -+ -+ status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); -+ if (status >= 0 && data == desiredStatus) { -+ /* tokenring already has correct status */ -+ return status; -+ } -+ /* Disable/enable dvbt tokenring bridge */ -+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); -+ -+ end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); -+ do { -+ status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); -+ if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end)) -+ break; -+ msleep(1); -+ } while (1); -+ if (data != desiredStatus) { -+ printk(KERN_ERR "drxk: SIO not ready\n"); -+ return -EINVAL; -+ } -+ return status; -+} -+ -+static int MPEGTSStop(struct drxk_state *state) -+{ -+ int status = 0; -+ u16 fecOcSncMode = 0; -+ u16 fecOcIprMode = 0; -+ -+ dprintk(1, "\n"); -+ -+ /* Gracefull shutdown (byte boundaries) */ -+ status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); -+ if (status < 0) -+ goto error; -+ fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; -+ status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); -+ if (status < 0) -+ goto error; -+ -+ /* Suppress MCLK during absence of data */ -+ status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode); -+ if (status < 0) -+ goto error; -+ fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; -+ status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode); -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static int scu_command(struct drxk_state *state, -+ u16 cmd, u8 parameterLen, -+ u16 *parameter, u8 resultLen, u16 *result) -+{ -+#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 -+#error DRXK register mapping no longer compatible with this routine! -+#endif -+ u16 curCmd = 0; -+ int status = -EINVAL; -+ unsigned long end; -+ u8 buffer[34]; -+ int cnt = 0, ii; -+ const char *p; -+ char errname[30]; -+ -+ dprintk(1, "\n"); -+ -+ if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || -+ ((resultLen > 0) && (result == NULL))) { -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+ } -+ -+ mutex_lock(&state->mutex); -+ -+ /* assume that the command register is ready -+ since it is checked afterwards */ -+ for (ii = parameterLen - 1; ii >= 0; ii -= 1) { -+ buffer[cnt++] = (parameter[ii] & 0xFF); -+ buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); -+ } -+ buffer[cnt++] = (cmd & 0xFF); -+ buffer[cnt++] = ((cmd >> 8) & 0xFF); -+ -+ write_block(state, SCU_RAM_PARAM_0__A - -+ (parameterLen - 1), cnt, buffer); -+ /* Wait until SCU has processed command */ -+ end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); -+ do { -+ msleep(1); -+ status = read16(state, SCU_RAM_COMMAND__A, &curCmd); -+ if (status < 0) -+ goto error; -+ } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); -+ if (curCmd != DRX_SCU_READY) { -+ printk(KERN_ERR "drxk: SCU not ready\n"); -+ status = -EIO; -+ goto error2; -+ } -+ /* read results */ -+ if ((resultLen > 0) && (result != NULL)) { -+ s16 err; -+ int ii; -+ -+ for (ii = resultLen - 1; ii >= 0; ii -= 1) { -+ status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); -+ if (status < 0) -+ goto error; -+ } -+ -+ /* Check if an error was reported by SCU */ -+ err = (s16)result[0]; -+ if (err >= 0) -+ goto error; -+ -+ /* check for the known error codes */ -+ switch (err) { -+ case SCU_RESULT_UNKCMD: -+ p = "SCU_RESULT_UNKCMD"; -+ break; -+ case SCU_RESULT_UNKSTD: -+ p = "SCU_RESULT_UNKSTD"; -+ break; -+ case SCU_RESULT_SIZE: -+ p = "SCU_RESULT_SIZE"; -+ break; -+ case SCU_RESULT_INVPAR: -+ p = "SCU_RESULT_INVPAR"; -+ break; -+ default: /* Other negative values are errors */ -+ sprintf(errname, "ERROR: %d\n", err); -+ p = errname; -+ } -+ printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd); -+ print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt); -+ status = -EINVAL; -+ goto error2; -+ } -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+error2: -+ mutex_unlock(&state->mutex); -+ return status; -+} -+ -+static int SetIqmAf(struct drxk_state *state, bool active) -+{ -+ u16 data = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ -+ /* Configure IQM */ -+ status = read16(state, IQM_AF_STDBY__A, &data); -+ if (status < 0) -+ goto error; -+ -+ if (!active) { -+ data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY -+ | IQM_AF_STDBY_STDBY_AMP_STANDBY -+ | IQM_AF_STDBY_STDBY_PD_STANDBY -+ | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY -+ | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY); -+ } else { -+ data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) -+ & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) -+ & (~IQM_AF_STDBY_STDBY_PD_STANDBY) -+ & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) -+ & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) -+ ); -+ } -+ status = write16(state, IQM_AF_STDBY__A, data); -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode) -+{ -+ int status = 0; -+ u16 sioCcPwdMode = 0; -+ -+ dprintk(1, "\n"); -+ -+ /* Check arguments */ -+ if (mode == NULL) -+ return -EINVAL; -+ -+ switch (*mode) { -+ case DRX_POWER_UP: -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; -+ break; -+ case DRXK_POWER_DOWN_OFDM: -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; -+ break; -+ case DRXK_POWER_DOWN_CORE: -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; -+ break; -+ case DRXK_POWER_DOWN_PLL: -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; -+ break; -+ case DRX_POWER_DOWN: -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; -+ break; -+ default: -+ /* Unknow sleep mode */ -+ return -EINVAL; -+ } -+ -+ /* If already in requested power mode, do nothing */ -+ if (state->m_currentPowerMode == *mode) -+ return 0; -+ -+ /* For next steps make sure to start from DRX_POWER_UP mode */ -+ if (state->m_currentPowerMode != DRX_POWER_UP) { -+ status = PowerUpDevice(state); -+ if (status < 0) -+ goto error; -+ status = DVBTEnableOFDMTokenRing(state, true); -+ if (status < 0) -+ goto error; -+ } -+ -+ if (*mode == DRX_POWER_UP) { -+ /* Restore analog & pin configuartion */ -+ } else { -+ /* Power down to requested mode */ -+ /* Backup some register settings */ -+ /* Set pins with possible pull-ups connected -+ to them in input mode */ -+ /* Analog power down */ -+ /* ADC power down */ -+ /* Power down device */ -+ /* stop all comm_exec */ -+ /* Stop and power down previous standard */ -+ switch (state->m_OperationMode) { -+ case OM_DVBT: -+ status = MPEGTSStop(state); -+ if (status < 0) -+ goto error; -+ status = PowerDownDVBT(state, false); -+ if (status < 0) -+ goto error; -+ break; -+ case OM_QAM_ITU_A: -+ case OM_QAM_ITU_C: -+ status = MPEGTSStop(state); -+ if (status < 0) -+ goto error; -+ status = PowerDownQAM(state); -+ if (status < 0) -+ goto error; -+ break; -+ default: -+ break; -+ } -+ status = DVBTEnableOFDMTokenRing(state, false); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); -+ if (status < 0) -+ goto error; -+ -+ if (*mode != DRXK_POWER_DOWN_OFDM) { -+ state->m_HICfgCtrl |= -+ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -+ status = HI_CfgCommand(state); -+ if (status < 0) -+ goto error; -+ } -+ } -+ state->m_currentPowerMode = *mode; -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) -+{ -+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; -+ u16 cmdResult = 0; -+ u16 data = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ -+ status = read16(state, SCU_COMM_EXEC__A, &data); -+ if (status < 0) -+ goto error; -+ if (data == SCU_COMM_EXEC_ACTIVE) { -+ /* Send OFDM stop command */ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ /* Send OFDM reset command */ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ } -+ -+ /* Reset datapath for OFDM, processors first */ -+ status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); -+ if (status < 0) -+ goto error; -+ -+ /* powerdown AFE */ -+ status = SetIqmAf(state, false); -+ if (status < 0) -+ goto error; -+ -+ /* powerdown to OFDM mode */ -+ if (setPowerMode) { -+ status = CtrlPowerMode(state, &powerMode); -+ if (status < 0) -+ goto error; -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int SetOperationMode(struct drxk_state *state, -+ enum OperationMode oMode) -+{ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ /* -+ Stop and power down previous standard -+ TODO investigate total power down instead of partial -+ power down depending on "previous" standard. -+ */ -+ -+ /* disable HW lock indicator */ -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ if (status < 0) -+ goto error; -+ -+ /* Device is already at the required mode */ -+ if (state->m_OperationMode == oMode) -+ return 0; -+ -+ switch (state->m_OperationMode) { -+ /* OM_NONE was added for start up */ -+ case OM_NONE: -+ break; -+ case OM_DVBT: -+ status = MPEGTSStop(state); -+ if (status < 0) -+ goto error; -+ status = PowerDownDVBT(state, true); -+ if (status < 0) -+ goto error; -+ state->m_OperationMode = OM_NONE; -+ break; -+ case OM_QAM_ITU_A: /* fallthrough */ -+ case OM_QAM_ITU_C: -+ status = MPEGTSStop(state); -+ if (status < 0) -+ goto error; -+ status = PowerDownQAM(state); -+ if (status < 0) -+ goto error; -+ state->m_OperationMode = OM_NONE; -+ break; -+ case OM_QAM_ITU_B: -+ default: -+ status = -EINVAL; -+ goto error; -+ } -+ -+ /* -+ Power up new standard -+ */ -+ switch (oMode) { -+ case OM_DVBT: -+ dprintk(1, ": DVB-T\n"); -+ state->m_OperationMode = oMode; -+ status = SetDVBTStandard(state, oMode); -+ if (status < 0) -+ goto error; -+ break; -+ case OM_QAM_ITU_A: /* fallthrough */ -+ case OM_QAM_ITU_C: -+ dprintk(1, ": DVB-C Annex %c\n", -+ (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C'); -+ state->m_OperationMode = oMode; -+ status = SetQAMStandard(state, oMode); -+ if (status < 0) -+ goto error; -+ break; -+ case OM_QAM_ITU_B: -+ default: -+ status = -EINVAL; -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int Start(struct drxk_state *state, s32 offsetFreq, -+ s32 IntermediateFrequency) -+{ -+ int status = -EINVAL; -+ -+ u16 IFreqkHz; -+ s32 OffsetkHz = offsetFreq / 1000; -+ -+ dprintk(1, "\n"); -+ if (state->m_DrxkState != DRXK_STOPPED && -+ state->m_DrxkState != DRXK_DTV_STARTED) -+ goto error; -+ -+ state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON); -+ -+ if (IntermediateFrequency < 0) { -+ state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; -+ IntermediateFrequency = -IntermediateFrequency; -+ } -+ -+ switch (state->m_OperationMode) { -+ case OM_QAM_ITU_A: -+ case OM_QAM_ITU_C: -+ IFreqkHz = (IntermediateFrequency / 1000); -+ status = SetQAM(state, IFreqkHz, OffsetkHz); -+ if (status < 0) -+ goto error; -+ state->m_DrxkState = DRXK_DTV_STARTED; -+ break; -+ case OM_DVBT: -+ IFreqkHz = (IntermediateFrequency / 1000); -+ status = MPEGTSStop(state); -+ if (status < 0) -+ goto error; -+ status = SetDVBT(state, IFreqkHz, OffsetkHz); -+ if (status < 0) -+ goto error; -+ status = DVBTStart(state); -+ if (status < 0) -+ goto error; -+ state->m_DrxkState = DRXK_DTV_STARTED; -+ break; -+ default: -+ break; -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int ShutDown(struct drxk_state *state) -+{ -+ dprintk(1, "\n"); -+ -+ MPEGTSStop(state); -+ return 0; -+} -+ -+static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, -+ u32 Time) -+{ -+ int status = -EINVAL; -+ -+ dprintk(1, "\n"); -+ -+ if (pLockStatus == NULL) -+ goto error; -+ -+ *pLockStatus = NOT_LOCKED; -+ -+ /* define the SCU command code */ -+ switch (state->m_OperationMode) { -+ case OM_QAM_ITU_A: -+ case OM_QAM_ITU_B: -+ case OM_QAM_ITU_C: -+ status = GetQAMLockStatus(state, pLockStatus); -+ break; -+ case OM_DVBT: -+ status = GetDVBTLockStatus(state, pLockStatus); -+ break; -+ default: -+ break; -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int MPEGTSStart(struct drxk_state *state) -+{ -+ int status; -+ -+ u16 fecOcSncMode = 0; -+ -+ /* Allow OC to sync again */ -+ status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); -+ if (status < 0) -+ goto error; -+ fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; -+ status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int MPEGTSDtoInit(struct drxk_state *state) -+{ -+ int status; -+ -+ dprintk(1, "\n"); -+ -+ /* Rate integration settings */ -+ status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); -+ if (status < 0) -+ goto error; -+ -+ /* Additional configuration */ -+ status = write16(state, FEC_OC_OCR_INVERT__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_SNC_LWM__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_SNC_HWM__A, 12); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static int MPEGTSDtoSetup(struct drxk_state *state, -+ enum OperationMode oMode) -+{ -+ int status; -+ -+ u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ -+ u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ -+ u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ -+ u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcTmdMode = 0; -+ u16 fecOcTmdIntUpdRate = 0; -+ u32 maxBitRate = 0; -+ bool staticCLK = false; -+ -+ dprintk(1, "\n"); -+ -+ /* Check insertion of the Reed-Solomon parity bytes */ -+ status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); -+ if (status < 0) -+ goto error; -+ status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); -+ if (status < 0) -+ goto error; -+ fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); -+ fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); -+ if (state->m_insertRSByte == true) { -+ /* enable parity symbol forward */ -+ fecOcRegMode |= FEC_OC_MODE_PARITY__M; -+ /* MVAL disable during parity bytes */ -+ fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; -+ /* TS burst length to 204 */ -+ fecOcDtoBurstLen = 204; -+ } -+ -+ /* Check serial or parrallel output */ -+ fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); -+ if (state->m_enableParallel == false) { -+ /* MPEG data output is serial -> set ipr_mode[0] */ -+ fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; -+ } -+ -+ switch (oMode) { -+ case OM_DVBT: -+ maxBitRate = state->m_DVBTBitrate; -+ fecOcTmdMode = 3; -+ fecOcRcnCtlRate = 0xC00000; -+ staticCLK = state->m_DVBTStaticCLK; -+ break; -+ case OM_QAM_ITU_A: /* fallthrough */ -+ case OM_QAM_ITU_C: -+ fecOcTmdMode = 0x0004; -+ fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ -+ maxBitRate = state->m_DVBCBitrate; -+ staticCLK = state->m_DVBCStaticCLK; -+ break; -+ default: -+ status = -EINVAL; -+ } /* switch (standard) */ -+ if (status < 0) -+ goto error; -+ -+ /* Configure DTO's */ -+ if (staticCLK) { -+ u32 bitRate = 0; -+ -+ /* Rational DTO for MCLK source (static MCLK rate), -+ Dynamic DTO for optimal grouping -+ (avoid intra-packet gaps), -+ DTO offset enable to sync TS burst with MSTRT */ -+ fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | -+ FEC_OC_DTO_MODE_OFFSET_ENABLE__M); -+ fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | -+ FEC_OC_FCT_MODE_VIRT_ENA__M); -+ -+ /* Check user defined bitrate */ -+ bitRate = maxBitRate; -+ if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */ -+ bitRate = 75900000UL; -+ } -+ /* Rational DTO period: -+ dto_period = (Fsys / bitrate) - 2 -+ -+ Result should be floored, -+ to make sure >= requested bitrate -+ */ -+ fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) -+ * 1000) / bitRate); -+ if (fecOcDtoPeriod <= 2) -+ fecOcDtoPeriod = 0; -+ else -+ fecOcDtoPeriod -= 2; -+ fecOcTmdIntUpdRate = 8; -+ } else { -+ /* (commonAttr->staticCLK == false) => dynamic mode */ -+ fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; -+ fecOcFctMode = FEC_OC_FCT_MODE__PRE; -+ fecOcTmdIntUpdRate = 5; -+ } -+ -+ /* Write appropriate registers with requested configuration */ -+ status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_MODE__A, fecOcRegMode); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); -+ if (status < 0) -+ goto error; -+ -+ /* Rate integration settings */ -+ status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int MPEGTSConfigurePolarity(struct drxk_state *state) -+{ -+ u16 fecOcRegIprInvert = 0; -+ -+ /* Data mask for the output data byte */ -+ u16 InvertDataMask = -+ FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | -+ FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | -+ FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | -+ FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; -+ -+ dprintk(1, "\n"); -+ -+ /* Control selective inversion of output bits */ -+ fecOcRegIprInvert &= (~(InvertDataMask)); -+ if (state->m_invertDATA == true) -+ fecOcRegIprInvert |= InvertDataMask; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); -+ if (state->m_invertERR == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); -+ if (state->m_invertSTR == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); -+ if (state->m_invertVAL == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); -+ if (state->m_invertCLK == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; -+ -+ return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); -+} -+ -+#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 -+ -+static int SetAgcRf(struct drxk_state *state, -+ struct SCfgAgc *pAgcCfg, bool isDTV) -+{ -+ int status = -EINVAL; -+ u16 data = 0; -+ struct SCfgAgc *pIfAgcSettings; -+ -+ dprintk(1, "\n"); -+ -+ if (pAgcCfg == NULL) -+ goto error; -+ -+ switch (pAgcCfg->ctrlMode) { -+ case DRXK_AGC_CTRL_AUTO: -+ /* Enable RF AGC DAC */ -+ status = read16(state, IQM_AF_STDBY__A, &data); -+ if (status < 0) -+ goto error; -+ data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; -+ status = write16(state, IQM_AF_STDBY__A, data); -+ if (status < 0) -+ goto error; -+ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); -+ if (status < 0) -+ goto error; -+ -+ /* Enable SCU RF AGC loop */ -+ data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; -+ -+ /* Polarity */ -+ if (state->m_RfAgcPol) -+ data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -+ else -+ data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -+ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* Set speed (using complementary reduction value) */ -+ status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); -+ if (status < 0) -+ goto error; -+ -+ data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; -+ data |= (~(pAgcCfg->speed << -+ SCU_RAM_AGC_KI_RED_RAGC_RED__B) -+ & SCU_RAM_AGC_KI_RED_RAGC_RED__M); -+ -+ status = write16(state, SCU_RAM_AGC_KI_RED__A, data); -+ if (status < 0) -+ goto error; -+ -+ if (IsDVBT(state)) -+ pIfAgcSettings = &state->m_dvbtIfAgcCfg; -+ else if (IsQAM(state)) -+ pIfAgcSettings = &state->m_qamIfAgcCfg; -+ else -+ pIfAgcSettings = &state->m_atvIfAgcCfg; -+ if (pIfAgcSettings == NULL) { -+ status = -EINVAL; -+ goto error; -+ } -+ -+ /* Set TOP, only if IF-AGC is in AUTO mode */ -+ if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top); -+ if (status < 0) -+ goto error; -+ -+ /* Cut-Off current */ -+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent); -+ if (status < 0) -+ goto error; -+ -+ /* Max. output level */ -+ status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); -+ if (status < 0) -+ goto error; -+ -+ break; -+ -+ case DRXK_AGC_CTRL_USER: -+ /* Enable RF AGC DAC */ -+ status = read16(state, IQM_AF_STDBY__A, &data); -+ if (status < 0) -+ goto error; -+ data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; -+ status = write16(state, IQM_AF_STDBY__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* Disable SCU RF AGC loop */ -+ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); -+ if (status < 0) -+ goto error; -+ data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; -+ if (state->m_RfAgcPol) -+ data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -+ else -+ data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -+ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* SCU c.o.c. to 0, enabling full control range */ -+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); -+ if (status < 0) -+ goto error; -+ -+ /* Write value to output pin */ -+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); -+ if (status < 0) -+ goto error; -+ break; -+ -+ case DRXK_AGC_CTRL_OFF: -+ /* Disable RF AGC DAC */ -+ status = read16(state, IQM_AF_STDBY__A, &data); -+ if (status < 0) -+ goto error; -+ data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; -+ status = write16(state, IQM_AF_STDBY__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* Disable SCU RF AGC loop */ -+ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); -+ if (status < 0) -+ goto error; -+ data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; -+ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); -+ if (status < 0) -+ goto error; -+ break; -+ -+ default: -+ status = -EINVAL; -+ -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 -+ -+static int SetAgcIf(struct drxk_state *state, -+ struct SCfgAgc *pAgcCfg, bool isDTV) -+{ -+ u16 data = 0; -+ int status = 0; -+ struct SCfgAgc *pRfAgcSettings; -+ -+ dprintk(1, "\n"); -+ -+ switch (pAgcCfg->ctrlMode) { -+ case DRXK_AGC_CTRL_AUTO: -+ -+ /* Enable IF AGC DAC */ -+ status = read16(state, IQM_AF_STDBY__A, &data); -+ if (status < 0) -+ goto error; -+ data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; -+ status = write16(state, IQM_AF_STDBY__A, data); -+ if (status < 0) -+ goto error; -+ -+ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); -+ if (status < 0) -+ goto error; -+ -+ /* Enable SCU IF AGC loop */ -+ data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; -+ -+ /* Polarity */ -+ if (state->m_IfAgcPol) -+ data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -+ else -+ data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -+ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* Set speed (using complementary reduction value) */ -+ status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); -+ if (status < 0) -+ goto error; -+ data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; -+ data |= (~(pAgcCfg->speed << -+ SCU_RAM_AGC_KI_RED_IAGC_RED__B) -+ & SCU_RAM_AGC_KI_RED_IAGC_RED__M); -+ -+ status = write16(state, SCU_RAM_AGC_KI_RED__A, data); -+ if (status < 0) -+ goto error; -+ -+ if (IsQAM(state)) -+ pRfAgcSettings = &state->m_qamRfAgcCfg; -+ else -+ pRfAgcSettings = &state->m_atvRfAgcCfg; -+ if (pRfAgcSettings == NULL) -+ return -1; -+ /* Restore TOP */ -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); -+ if (status < 0) -+ goto error; -+ break; -+ -+ case DRXK_AGC_CTRL_USER: -+ -+ /* Enable IF AGC DAC */ -+ status = read16(state, IQM_AF_STDBY__A, &data); -+ if (status < 0) -+ goto error; -+ data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; -+ status = write16(state, IQM_AF_STDBY__A, data); -+ if (status < 0) -+ goto error; -+ -+ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); -+ if (status < 0) -+ goto error; -+ -+ /* Disable SCU IF AGC loop */ -+ data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; -+ -+ /* Polarity */ -+ if (state->m_IfAgcPol) -+ data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -+ else -+ data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -+ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* Write value to output pin */ -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); -+ if (status < 0) -+ goto error; -+ break; -+ -+ case DRXK_AGC_CTRL_OFF: -+ -+ /* Disable If AGC DAC */ -+ status = read16(state, IQM_AF_STDBY__A, &data); -+ if (status < 0) -+ goto error; -+ data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; -+ status = write16(state, IQM_AF_STDBY__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* Disable SCU IF AGC loop */ -+ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); -+ if (status < 0) -+ goto error; -+ data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; -+ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); -+ if (status < 0) -+ goto error; -+ break; -+ } /* switch (agcSettingsIf->ctrlMode) */ -+ -+ /* always set the top to support -+ configurations without if-loop */ -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int ReadIFAgc(struct drxk_state *state, u32 *pValue) -+{ -+ u16 agcDacLvl; -+ int status; -+ u16 Level = 0; -+ -+ dprintk(1, "\n"); -+ -+ status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl); -+ if (status < 0) { -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+ } -+ -+ *pValue = 0; -+ -+ if (agcDacLvl > DRXK_AGC_DAC_OFFSET) -+ Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; -+ if (Level < 14000) -+ *pValue = (14000 - Level) / 4; -+ else -+ *pValue = 0; -+ -+ return status; -+} -+ -+static int GetQAMSignalToNoise(struct drxk_state *state, -+ s32 *pSignalToNoise) -+{ -+ int status = 0; -+ u16 qamSlErrPower = 0; /* accum. error between -+ raw and sliced symbols */ -+ u32 qamSlSigPower = 0; /* used for MER, depends of -+ QAM modulation */ -+ u32 qamSlMer = 0; /* QAM MER */ -+ -+ dprintk(1, "\n"); -+ -+ /* MER calculation */ -+ -+ /* get the register value needed for MER */ -+ status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower); -+ if (status < 0) { -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return -EINVAL; -+ } -+ -+ switch (state->props.modulation) { -+ case QAM_16: -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; -+ break; -+ case QAM_32: -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; -+ break; -+ case QAM_64: -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; -+ break; -+ case QAM_128: -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; -+ break; -+ default: -+ case QAM_256: -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; -+ break; -+ } -+ -+ if (qamSlErrPower > 0) { -+ qamSlMer = Log10Times100(qamSlSigPower) - -+ Log10Times100((u32) qamSlErrPower); -+ } -+ *pSignalToNoise = qamSlMer; -+ -+ return status; -+} -+ -+static int GetDVBTSignalToNoise(struct drxk_state *state, -+ s32 *pSignalToNoise) -+{ -+ int status; -+ u16 regData = 0; -+ u32 EqRegTdSqrErrI = 0; -+ u32 EqRegTdSqrErrQ = 0; -+ u16 EqRegTdSqrErrExp = 0; -+ u16 EqRegTdTpsPwrOfs = 0; -+ u16 EqRegTdReqSmbCnt = 0; -+ u32 tpsCnt = 0; -+ u32 SqrErrIQ = 0; -+ u32 a = 0; -+ u32 b = 0; -+ u32 c = 0; -+ u32 iMER = 0; -+ u16 transmissionParams = 0; -+ -+ dprintk(1, "\n"); -+ -+ status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); -+ if (status < 0) -+ goto error; -+ status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); -+ if (status < 0) -+ goto error; -+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); -+ if (status < 0) -+ goto error; -+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data); -+ if (status < 0) -+ goto error; -+ /* Extend SQR_ERR_I operational range */ -+ EqRegTdSqrErrI = (u32) regData; -+ if ((EqRegTdSqrErrExp > 11) && -+ (EqRegTdSqrErrI < 0x00000FFFUL)) { -+ EqRegTdSqrErrI += 0x00010000UL; -+ } -+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data); -+ if (status < 0) -+ goto error; -+ /* Extend SQR_ERR_Q operational range */ -+ EqRegTdSqrErrQ = (u32) regData; -+ if ((EqRegTdSqrErrExp > 11) && -+ (EqRegTdSqrErrQ < 0x00000FFFUL)) -+ EqRegTdSqrErrQ += 0x00010000UL; -+ -+ status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); -+ if (status < 0) -+ goto error; -+ -+ /* Check input data for MER */ -+ -+ /* MER calculation (in 0.1 dB) without math.h */ -+ if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) -+ iMER = 0; -+ else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { -+ /* No error at all, this must be the HW reset value -+ * Apparently no first measurement yet -+ * Set MER to 0.0 */ -+ iMER = 0; -+ } else { -+ SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << -+ EqRegTdSqrErrExp; -+ if ((transmissionParams & -+ OFDM_SC_RA_RAM_OP_PARAM_MODE__M) -+ == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) -+ tpsCnt = 17; -+ else -+ tpsCnt = 68; -+ -+ /* IMER = 100 * log10 (x) -+ where x = (EqRegTdTpsPwrOfs^2 * -+ EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ -+ -+ => IMER = a + b -c -+ where a = 100 * log10 (EqRegTdTpsPwrOfs^2) -+ b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) -+ c = 100 * log10 (SqrErrIQ) -+ */ -+ -+ /* log(x) x = 9bits * 9bits->18 bits */ -+ a = Log10Times100(EqRegTdTpsPwrOfs * -+ EqRegTdTpsPwrOfs); -+ /* log(x) x = 16bits * 7bits->23 bits */ -+ b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt); -+ /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ -+ c = Log10Times100(SqrErrIQ); -+ -+ iMER = a + b; -+ /* No negative MER, clip to zero */ -+ if (iMER > c) -+ iMER -= c; -+ else -+ iMER = 0; -+ } -+ *pSignalToNoise = iMER; -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) -+{ -+ dprintk(1, "\n"); -+ -+ *pSignalToNoise = 0; -+ switch (state->m_OperationMode) { -+ case OM_DVBT: -+ return GetDVBTSignalToNoise(state, pSignalToNoise); -+ case OM_QAM_ITU_A: -+ case OM_QAM_ITU_C: -+ return GetQAMSignalToNoise(state, pSignalToNoise); -+ default: -+ break; -+ } -+ return 0; -+} -+ -+#if 0 -+static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) -+{ -+ /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ -+ static s32 QE_SN[] = { -+ 51, /* QPSK 1/2 */ -+ 69, /* QPSK 2/3 */ -+ 79, /* QPSK 3/4 */ -+ 89, /* QPSK 5/6 */ -+ 97, /* QPSK 7/8 */ -+ 108, /* 16-QAM 1/2 */ -+ 131, /* 16-QAM 2/3 */ -+ 146, /* 16-QAM 3/4 */ -+ 156, /* 16-QAM 5/6 */ -+ 160, /* 16-QAM 7/8 */ -+ 165, /* 64-QAM 1/2 */ -+ 187, /* 64-QAM 2/3 */ -+ 202, /* 64-QAM 3/4 */ -+ 216, /* 64-QAM 5/6 */ -+ 225, /* 64-QAM 7/8 */ -+ }; -+ -+ *pQuality = 0; -+ -+ do { -+ s32 SignalToNoise = 0; -+ u16 Constellation = 0; -+ u16 CodeRate = 0; -+ u32 SignalToNoiseRel; -+ u32 BERQuality; -+ -+ status = GetDVBTSignalToNoise(state, &SignalToNoise); -+ if (status < 0) -+ break; -+ status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation); -+ if (status < 0) -+ break; -+ Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; -+ -+ status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate); -+ if (status < 0) -+ break; -+ CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; -+ -+ if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || -+ CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) -+ break; -+ SignalToNoiseRel = SignalToNoise - -+ QE_SN[Constellation * 5 + CodeRate]; -+ BERQuality = 100; -+ -+ if (SignalToNoiseRel < -70) -+ *pQuality = 0; -+ else if (SignalToNoiseRel < 30) -+ *pQuality = ((SignalToNoiseRel + 70) * -+ BERQuality) / 100; -+ else -+ *pQuality = BERQuality; -+ } while (0); -+ return 0; -+}; -+ -+static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) -+{ -+ int status = 0; -+ *pQuality = 0; -+ -+ dprintk(1, "\n"); -+ -+ do { -+ u32 SignalToNoise = 0; -+ u32 BERQuality = 100; -+ u32 SignalToNoiseRel = 0; -+ -+ status = GetQAMSignalToNoise(state, &SignalToNoise); -+ if (status < 0) -+ break; -+ -+ switch (state->props.modulation) { -+ case QAM_16: -+ SignalToNoiseRel = SignalToNoise - 200; -+ break; -+ case QAM_32: -+ SignalToNoiseRel = SignalToNoise - 230; -+ break; /* Not in NorDig */ -+ case QAM_64: -+ SignalToNoiseRel = SignalToNoise - 260; -+ break; -+ case QAM_128: -+ SignalToNoiseRel = SignalToNoise - 290; -+ break; -+ default: -+ case QAM_256: -+ SignalToNoiseRel = SignalToNoise - 320; -+ break; -+ } -+ -+ if (SignalToNoiseRel < -70) -+ *pQuality = 0; -+ else if (SignalToNoiseRel < 30) -+ *pQuality = ((SignalToNoiseRel + 70) * -+ BERQuality) / 100; -+ else -+ *pQuality = BERQuality; -+ } while (0); -+ -+ return status; -+} -+ -+static int GetQuality(struct drxk_state *state, s32 *pQuality) -+{ -+ dprintk(1, "\n"); -+ -+ switch (state->m_OperationMode) { -+ case OM_DVBT: -+ return GetDVBTQuality(state, pQuality); -+ case OM_QAM_ITU_A: -+ return GetDVBCQuality(state, pQuality); -+ default: -+ break; -+ } -+ -+ return 0; -+} -+#endif -+ -+/* Free data ram in SIO HI */ -+#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 -+#define SIO_HI_RA_RAM_USR_END__A 0x420060 -+ -+#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) -+#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) -+#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ -+#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE -+ -+#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) -+#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) -+#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) -+ -+static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) -+{ -+ int status = -EINVAL; -+ -+ dprintk(1, "\n"); -+ -+ if (state->m_DrxkState == DRXK_UNINITIALIZED) -+ goto error; -+ if (state->m_DrxkState == DRXK_POWERED_DOWN) -+ goto error; -+ -+ if (state->no_i2c_bridge) -+ return 0; -+ -+ status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); -+ if (status < 0) -+ goto error; -+ if (bEnableBridge) { -+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); -+ if (status < 0) -+ goto error; -+ } else { -+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); -+ if (status < 0) -+ goto error; -+ } -+ -+ status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0); -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int SetPreSaw(struct drxk_state *state, -+ struct SCfgPreSaw *pPreSawCfg) -+{ -+ int status = -EINVAL; -+ -+ dprintk(1, "\n"); -+ -+ if ((pPreSawCfg == NULL) -+ || (pPreSawCfg->reference > IQM_AF_PDREF__M)) -+ goto error; -+ -+ status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, -+ u16 romOffset, u16 nrOfElements, u32 timeOut) -+{ -+ u16 blStatus = 0; -+ u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF); -+ u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF); -+ int status; -+ unsigned long end; -+ -+ dprintk(1, "\n"); -+ -+ mutex_lock(&state->mutex); -+ status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_TGT_HDR__A, blockbank); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_TGT_ADDR__A, offset); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); -+ if (status < 0) -+ goto error; -+ -+ end = jiffies + msecs_to_jiffies(timeOut); -+ do { -+ status = read16(state, SIO_BL_STATUS__A, &blStatus); -+ if (status < 0) -+ goto error; -+ } while ((blStatus == 0x1) && time_is_after_jiffies(end)); -+ if (blStatus == 0x1) { -+ printk(KERN_ERR "drxk: SIO not ready\n"); -+ status = -EINVAL; -+ goto error2; -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+error2: -+ mutex_unlock(&state->mutex); -+ return status; -+ -+} -+ -+static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) -+{ -+ u16 data = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ -+ /* Start measurement */ -+ status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_START_LOCK__A, 1); -+ if (status < 0) -+ goto error; -+ -+ *count = 0; -+ status = read16(state, IQM_AF_PHASE0__A, &data); -+ if (status < 0) -+ goto error; -+ if (data == 127) -+ *count = *count + 1; -+ status = read16(state, IQM_AF_PHASE1__A, &data); -+ if (status < 0) -+ goto error; -+ if (data == 127) -+ *count = *count + 1; -+ status = read16(state, IQM_AF_PHASE2__A, &data); -+ if (status < 0) -+ goto error; -+ if (data == 127) -+ *count = *count + 1; -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int ADCSynchronization(struct drxk_state *state) -+{ -+ u16 count = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ -+ status = ADCSyncMeasurement(state, &count); -+ if (status < 0) -+ goto error; -+ -+ if (count == 1) { -+ /* Try sampling on a diffrent edge */ -+ u16 clkNeg = 0; -+ -+ status = read16(state, IQM_AF_CLKNEG__A, &clkNeg); -+ if (status < 0) -+ goto error; -+ if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == -+ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { -+ clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -+ clkNeg |= -+ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; -+ } else { -+ clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -+ clkNeg |= -+ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; -+ } -+ status = write16(state, IQM_AF_CLKNEG__A, clkNeg); -+ if (status < 0) -+ goto error; -+ status = ADCSyncMeasurement(state, &count); -+ if (status < 0) -+ goto error; -+ } -+ -+ if (count < 2) -+ status = -EINVAL; -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int SetFrequencyShifter(struct drxk_state *state, -+ u16 intermediateFreqkHz, -+ s32 tunerFreqOffset, bool isDTV) -+{ -+ bool selectPosImage = false; -+ u32 rfFreqResidual = tunerFreqOffset; -+ u32 fmFrequencyShift = 0; -+ bool tunerMirror = !state->m_bMirrorFreqSpect; -+ u32 adcFreq; -+ bool adcFlip; -+ int status; -+ u32 ifFreqActual; -+ u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3); -+ u32 frequencyShift; -+ bool imageToSelect; -+ -+ dprintk(1, "\n"); -+ -+ /* -+ Program frequency shifter -+ No need to account for mirroring on RF -+ */ -+ if (isDTV) { -+ if ((state->m_OperationMode == OM_QAM_ITU_A) || -+ (state->m_OperationMode == OM_QAM_ITU_C) || -+ (state->m_OperationMode == OM_DVBT)) -+ selectPosImage = true; -+ else -+ selectPosImage = false; -+ } -+ if (tunerMirror) -+ /* tuner doesn't mirror */ -+ ifFreqActual = intermediateFreqkHz + -+ rfFreqResidual + fmFrequencyShift; -+ else -+ /* tuner mirrors */ -+ ifFreqActual = intermediateFreqkHz - -+ rfFreqResidual - fmFrequencyShift; -+ if (ifFreqActual > samplingFrequency / 2) { -+ /* adc mirrors */ -+ adcFreq = samplingFrequency - ifFreqActual; -+ adcFlip = true; -+ } else { -+ /* adc doesn't mirror */ -+ adcFreq = ifFreqActual; -+ adcFlip = false; -+ } -+ -+ frequencyShift = adcFreq; -+ imageToSelect = state->m_rfmirror ^ tunerMirror ^ -+ adcFlip ^ selectPosImage; -+ state->m_IqmFsRateOfs = -+ Frac28a((frequencyShift), samplingFrequency); -+ -+ if (imageToSelect) -+ state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; -+ -+ /* Program frequency shifter with tuner offset compensation */ -+ /* frequencyShift += tunerFreqOffset; TODO */ -+ status = write32(state, IQM_FS_RATE_OFS_LO__A, -+ state->m_IqmFsRateOfs); -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int InitAGC(struct drxk_state *state, bool isDTV) -+{ -+ u16 ingainTgt = 0; -+ u16 ingainTgtMin = 0; -+ u16 ingainTgtMax = 0; -+ u16 clpCyclen = 0; -+ u16 clpSumMin = 0; -+ u16 clpDirTo = 0; -+ u16 snsSumMin = 0; -+ u16 snsSumMax = 0; -+ u16 clpSumMax = 0; -+ u16 snsDirTo = 0; -+ u16 kiInnergainMin = 0; -+ u16 ifIaccuHiTgt = 0; -+ u16 ifIaccuHiTgtMin = 0; -+ u16 ifIaccuHiTgtMax = 0; -+ u16 data = 0; -+ u16 fastClpCtrlDelay = 0; -+ u16 clpCtrlMode = 0; -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ -+ /* Common settings */ -+ snsSumMax = 1023; -+ ifIaccuHiTgtMin = 2047; -+ clpCyclen = 500; -+ clpSumMax = 1023; -+ -+ /* AGCInit() not available for DVBT; init done in microcode */ -+ if (!IsQAM(state)) { -+ printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode); -+ return -EINVAL; -+ } -+ -+ /* FIXME: Analog TV AGC require different settings */ -+ -+ /* Standard specific settings */ -+ clpSumMin = 8; -+ clpDirTo = (u16) -9; -+ clpCtrlMode = 0; -+ snsSumMin = 8; -+ snsDirTo = (u16) -9; -+ kiInnergainMin = (u16) -1030; -+ ifIaccuHiTgtMax = 0x2380; -+ ifIaccuHiTgt = 0x2380; -+ ingainTgtMin = 0x0511; -+ ingainTgt = 0x0511; -+ ingainTgtMax = 5119; -+ fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay; -+ -+ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); -+ if (status < 0) -+ goto error; -+ -+ /* Initialize inner-loop KI gain factors */ -+ status = read16(state, SCU_RAM_AGC_KI__A, &data); -+ if (status < 0) -+ goto error; -+ -+ data = 0x0657; -+ data &= ~SCU_RAM_AGC_KI_RF__M; -+ data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); -+ data &= ~SCU_RAM_AGC_KI_IF__M; -+ data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); -+ -+ status = write16(state, SCU_RAM_AGC_KI__A, data); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr) -+{ -+ int status; -+ -+ dprintk(1, "\n"); -+ if (packetErr == NULL) -+ status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); -+ else -+ status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int DVBTScCommand(struct drxk_state *state, -+ u16 cmd, u16 subcmd, -+ u16 param0, u16 param1, u16 param2, -+ u16 param3, u16 param4) -+{ -+ u16 curCmd = 0; -+ u16 errCode = 0; -+ u16 retryCnt = 0; -+ u16 scExec = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec); -+ if (scExec != 1) { -+ /* SC is not running */ -+ status = -EINVAL; -+ } -+ if (status < 0) -+ goto error; -+ -+ /* Wait until sc is ready to receive command */ -+ retryCnt = 0; -+ do { -+ msleep(1); -+ status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); -+ retryCnt++; -+ } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); -+ if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) -+ goto error; -+ -+ /* Write sub-command */ -+ switch (cmd) { -+ /* All commands using sub-cmd */ -+ case OFDM_SC_RA_RAM_CMD_PROC_START: -+ case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: -+ case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: -+ status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); -+ if (status < 0) -+ goto error; -+ break; -+ default: -+ /* Do nothing */ -+ break; -+ } -+ -+ /* Write needed parameters and the command */ -+ switch (cmd) { -+ /* All commands using 5 parameters */ -+ /* All commands using 4 parameters */ -+ /* All commands using 3 parameters */ -+ /* All commands using 2 parameters */ -+ case OFDM_SC_RA_RAM_CMD_PROC_START: -+ case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: -+ case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: -+ status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); -+ /* All commands using 1 parameters */ -+ case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: -+ case OFDM_SC_RA_RAM_CMD_USER_IO: -+ status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); -+ /* All commands using 0 parameters */ -+ case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: -+ case OFDM_SC_RA_RAM_CMD_NULL: -+ /* Write command */ -+ status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); -+ break; -+ default: -+ /* Unknown command */ -+ status = -EINVAL; -+ } -+ if (status < 0) -+ goto error; -+ -+ /* Wait until sc is ready processing command */ -+ retryCnt = 0; -+ do { -+ msleep(1); -+ status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); -+ retryCnt++; -+ } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); -+ if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) -+ goto error; -+ -+ /* Check for illegal cmd */ -+ status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); -+ if (errCode == 0xFFFF) { -+ /* illegal command */ -+ status = -EINVAL; -+ } -+ if (status < 0) -+ goto error; -+ -+ /* Retreive results parameters from SC */ -+ switch (cmd) { -+ /* All commands yielding 5 results */ -+ /* All commands yielding 4 results */ -+ /* All commands yielding 3 results */ -+ /* All commands yielding 2 results */ -+ /* All commands yielding 1 result */ -+ case OFDM_SC_RA_RAM_CMD_USER_IO: -+ case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: -+ status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); -+ /* All commands yielding 0 results */ -+ case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: -+ case OFDM_SC_RA_RAM_CMD_SET_TIMER: -+ case OFDM_SC_RA_RAM_CMD_PROC_START: -+ case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: -+ case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: -+ case OFDM_SC_RA_RAM_CMD_NULL: -+ break; -+ default: -+ /* Unknown command */ -+ status = -EINVAL; -+ break; -+ } /* switch (cmd->cmd) */ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int PowerUpDVBT(struct drxk_state *state) -+{ -+ enum DRXPowerMode powerMode = DRX_POWER_UP; -+ int status; -+ -+ dprintk(1, "\n"); -+ status = CtrlPowerMode(state, &powerMode); -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled) -+{ -+ int status; -+ -+ dprintk(1, "\n"); -+ if (*enabled == true) -+ status = write16(state, IQM_CF_BYPASSDET__A, 0); -+ else -+ status = write16(state, IQM_CF_BYPASSDET__A, 1); -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+#define DEFAULT_FR_THRES_8K 4000 -+static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled) -+{ -+ -+ int status; -+ -+ dprintk(1, "\n"); -+ if (*enabled == true) { -+ /* write mask to 1 */ -+ status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, -+ DEFAULT_FR_THRES_8K); -+ } else { -+ /* write mask to 0 */ -+ status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); -+ } -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static int DVBTCtrlSetEchoThreshold(struct drxk_state *state, -+ struct DRXKCfgDvbtEchoThres_t *echoThres) -+{ -+ u16 data = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); -+ if (status < 0) -+ goto error; -+ -+ switch (echoThres->fftMode) { -+ case DRX_FFTMODE_2K: -+ data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; -+ data |= ((echoThres->threshold << -+ OFDM_SC_RA_RAM_ECHO_THRES_2K__B) -+ & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); -+ break; -+ case DRX_FFTMODE_8K: -+ data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; -+ data |= ((echoThres->threshold << -+ OFDM_SC_RA_RAM_ECHO_THRES_8K__B) -+ & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, -+ enum DRXKCfgDvbtSqiSpeed *speed) -+{ -+ int status = -EINVAL; -+ -+ dprintk(1, "\n"); -+ -+ switch (*speed) { -+ case DRXK_DVBT_SQI_SPEED_FAST: -+ case DRXK_DVBT_SQI_SPEED_MEDIUM: -+ case DRXK_DVBT_SQI_SPEED_SLOW: -+ break; -+ default: -+ goto error; -+ } -+ status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, -+ (u16) *speed); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief Activate DVBT specific presets -+* \param demod instance of demodulator. -+* \return DRXStatus_t. -+* -+* Called in DVBTSetStandard -+* -+*/ -+static int DVBTActivatePresets(struct drxk_state *state) -+{ -+ int status; -+ bool setincenable = false; -+ bool setfrenable = true; -+ -+ struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K }; -+ struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K }; -+ -+ dprintk(1, "\n"); -+ status = DVBTCtrlSetIncEnable(state, &setincenable); -+ if (status < 0) -+ goto error; -+ status = DVBTCtrlSetFrEnable(state, &setfrenable); -+ if (status < 0) -+ goto error; -+ status = DVBTCtrlSetEchoThreshold(state, &echoThres2k); -+ if (status < 0) -+ goto error; -+ status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief Initialize channelswitch-independent settings for DVBT. -+* \param demod instance of demodulator. -+* \return DRXStatus_t. -+* -+* For ROM code channel filter taps are loaded from the bootloader. For microcode -+* the DVB-T taps from the drxk_filters.h are used. -+*/ -+static int SetDVBTStandard(struct drxk_state *state, -+ enum OperationMode oMode) -+{ -+ u16 cmdResult = 0; -+ u16 data = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ -+ PowerUpDVBT(state); -+ /* added antenna switch */ -+ SwitchAntennaToDVBT(state); -+ /* send OFDM reset command */ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ -+ /* send OFDM setenv command */ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ -+ /* reset datapath for OFDM, processors first */ -+ status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); -+ if (status < 0) -+ goto error; -+ -+ /* IQM setup */ -+ /* synchronize on ofdstate->m_festart */ -+ status = write16(state, IQM_AF_UPD_SEL__A, 1); -+ if (status < 0) -+ goto error; -+ /* window size for clipping ADC detection */ -+ status = write16(state, IQM_AF_CLP_LEN__A, 0); -+ if (status < 0) -+ goto error; -+ /* window size for for sense pre-SAW detection */ -+ status = write16(state, IQM_AF_SNS_LEN__A, 0); -+ if (status < 0) -+ goto error; -+ /* sense threshold for sense pre-SAW detection */ -+ status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); -+ if (status < 0) -+ goto error; -+ status = SetIqmAf(state, true); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, IQM_AF_AGC_RF__A, 0); -+ if (status < 0) -+ goto error; -+ -+ /* Impulse noise cruncher setup */ -+ status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, IQM_RC_STRETCH__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_SCALE__A, 1600); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_SCALE_SH__A, 0); -+ if (status < 0) -+ goto error; -+ -+ /* virtual clipping threshold for clipping ADC detection */ -+ status = write16(state, IQM_AF_CLP_TH__A, 448); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ -+ if (status < 0) -+ goto error; -+ -+ status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); -+ if (status < 0) -+ goto error; -+ /* enable power measurement interrupt */ -+ status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); -+ if (status < 0) -+ goto error; -+ -+ /* IQM will not be reset from here, sync ADC and update/init AGC */ -+ status = ADCSynchronization(state); -+ if (status < 0) -+ goto error; -+ status = SetPreSaw(state, &state->m_dvbtPreSawCfg); -+ if (status < 0) -+ goto error; -+ -+ /* Halt SCU to enable safe non-atomic accesses */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); -+ if (status < 0) -+ goto error; -+ -+ status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true); -+ if (status < 0) -+ goto error; -+ status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true); -+ if (status < 0) -+ goto error; -+ -+ /* Set Noise Estimation notch width and enable DC fix */ -+ status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); -+ if (status < 0) -+ goto error; -+ data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; -+ status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); -+ if (status < 0) -+ goto error; -+ -+ /* Activate SCU to enable SCU commands */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ -+ if (!state->m_DRXK_A3_ROM_CODE) { -+ /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ -+ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay); -+ if (status < 0) -+ goto error; -+ } -+ -+ /* OFDM_SC setup */ -+#ifdef COMPILE_FOR_NONRT -+ status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); -+ if (status < 0) -+ goto error; -+#endif -+ -+ /* FEC setup */ -+ status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ -+ if (status < 0) -+ goto error; -+ -+ -+#ifdef COMPILE_FOR_NONRT -+ status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); -+ if (status < 0) -+ goto error; -+#else -+ status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); -+ if (status < 0) -+ goto error; -+#endif -+ status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); -+ if (status < 0) -+ goto error; -+ -+ /* Setup MPEG bus */ -+ status = MPEGTSDtoSetup(state, OM_DVBT); -+ if (status < 0) -+ goto error; -+ /* Set DVBT Presets */ -+ status = DVBTActivatePresets(state); -+ if (status < 0) -+ goto error; -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+/*============================================================================*/ -+/** -+* \brief Start dvbt demodulating for channel. -+* \param demod instance of demodulator. -+* \return DRXStatus_t. -+*/ -+static int DVBTStart(struct drxk_state *state) -+{ -+ u16 param1; -+ int status; -+ /* DRXKOfdmScCmd_t scCmd; */ -+ -+ dprintk(1, "\n"); -+ /* Start correct processes to get in lock */ -+ /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ -+ param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; -+ status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0); -+ if (status < 0) -+ goto error; -+ /* Start FEC OC */ -+ status = MPEGTSStart(state); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+ -+/*============================================================================*/ -+ -+/** -+* \brief Set up dvbt demodulator for channel. -+* \param demod instance of demodulator. -+* \return DRXStatus_t. -+* // original DVBTSetChannel() -+*/ -+static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset) -+{ -+ u16 cmdResult = 0; -+ u16 transmissionParams = 0; -+ u16 operationMode = 0; -+ u32 iqmRcRateOfs = 0; -+ u32 bandwidth = 0; -+ u16 param1; -+ int status; -+ -+ dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset); -+ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ -+ /* Halt SCU to enable safe non-atomic accesses */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); -+ if (status < 0) -+ goto error; -+ -+ /* Stop processors */ -+ status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ -+ /* Mandatory fix, always stop CP, required to set spl offset back to -+ hardware default (is set to 0 by ucode during pilot detection */ -+ status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ -+ /*== Write channel settings to device =====================================*/ -+ -+ /* mode */ -+ switch (state->props.transmission_mode) { -+ case TRANSMISSION_MODE_AUTO: -+ default: -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; -+ /* fall through , try first guess DRX_FFTMODE_8K */ -+ case TRANSMISSION_MODE_8K: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; -+ break; -+ case TRANSMISSION_MODE_2K: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; -+ break; -+ } -+ -+ /* guard */ -+ switch (state->props.guard_interval) { -+ default: -+ case GUARD_INTERVAL_AUTO: -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; -+ /* fall through , try first guess DRX_GUARD_1DIV4 */ -+ case GUARD_INTERVAL_1_4: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; -+ break; -+ case GUARD_INTERVAL_1_32: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; -+ break; -+ case GUARD_INTERVAL_1_16: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; -+ break; -+ case GUARD_INTERVAL_1_8: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; -+ break; -+ } -+ -+ /* hierarchy */ -+ switch (state->props.hierarchy) { -+ case HIERARCHY_AUTO: -+ case HIERARCHY_NONE: -+ default: -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; -+ /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ -+ /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ -+ /* break; */ -+ case HIERARCHY_1: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; -+ break; -+ case HIERARCHY_2: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; -+ break; -+ case HIERARCHY_4: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; -+ break; -+ } -+ -+ -+ /* modulation */ -+ switch (state->props.modulation) { -+ case QAM_AUTO: -+ default: -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; -+ /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ -+ case QAM_64: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; -+ break; -+ case QPSK: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; -+ break; -+ case QAM_16: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; -+ break; -+ } -+#if 0 -+ /* No hierachical channels support in BDA */ -+ /* Priority (only for hierarchical channels) */ -+ switch (channel->priority) { -+ case DRX_PRIORITY_LOW: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; -+ WR16(devAddr, OFDM_EC_SB_PRIOR__A, -+ OFDM_EC_SB_PRIOR_LO); -+ break; -+ case DRX_PRIORITY_HIGH: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; -+ WR16(devAddr, OFDM_EC_SB_PRIOR__A, -+ OFDM_EC_SB_PRIOR_HI)); -+ break; -+ case DRX_PRIORITY_UNKNOWN: /* fall through */ -+ default: -+ status = -EINVAL; -+ goto error; -+ } -+#else -+ /* Set Priorty high */ -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; -+ status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); -+ if (status < 0) -+ goto error; -+#endif -+ -+ /* coderate */ -+ switch (state->props.code_rate_HP) { -+ case FEC_AUTO: -+ default: -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; -+ /* fall through , try first guess DRX_CODERATE_2DIV3 */ -+ case FEC_2_3: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; -+ break; -+ case FEC_1_2: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; -+ break; -+ case FEC_3_4: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; -+ break; -+ case FEC_5_6: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; -+ break; -+ case FEC_7_8: -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; -+ break; -+ } -+ -+ /* SAW filter selection: normaly not necesarry, but if wanted -+ the application can select a SAW filter via the driver by using UIOs */ -+ /* First determine real bandwidth (Hz) */ -+ /* Also set delay for impulse noise cruncher */ -+ /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed -+ by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC -+ functions */ -+ switch (state->props.bandwidth_hz) { -+ case 0: -+ state->props.bandwidth_hz = 8000000; -+ /* fall though */ -+ case 8000000: -+ bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; -+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); -+ if (status < 0) -+ goto error; -+ /* cochannel protection for PAL 8 MHz */ -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); -+ if (status < 0) -+ goto error; -+ break; -+ case 7000000: -+ bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; -+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); -+ if (status < 0) -+ goto error; -+ /* cochannel protection for PAL 7 MHz */ -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); -+ if (status < 0) -+ goto error; -+ break; -+ case 6000000: -+ bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; -+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); -+ if (status < 0) -+ goto error; -+ /* cochannel protection for NTSC 6 MHz */ -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); -+ if (status < 0) -+ goto error; -+ break; -+ default: -+ status = -EINVAL; -+ goto error; -+ } -+ -+ if (iqmRcRateOfs == 0) { -+ /* Now compute IQM_RC_RATE_OFS -+ (((SysFreq/BandWidth)/2)/2) -1) * 2^23) -+ => -+ ((SysFreq / BandWidth) * (2^21)) - (2^23) -+ */ -+ /* (SysFreq / BandWidth) * (2^28) */ -+ /* assert (MAX(sysClk)/MIN(bandwidth) < 16) -+ => assert(MAX(sysClk) < 16*MIN(bandwidth)) -+ => assert(109714272 > 48000000) = true so Frac 28 can be used */ -+ iqmRcRateOfs = Frac28a((u32) -+ ((state->m_sysClockFreq * -+ 1000) / 3), bandwidth); -+ /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ -+ if ((iqmRcRateOfs & 0x7fL) >= 0x40) -+ iqmRcRateOfs += 0x80L; -+ iqmRcRateOfs = iqmRcRateOfs >> 7; -+ /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ -+ iqmRcRateOfs = iqmRcRateOfs - (1 << 23); -+ } -+ -+ iqmRcRateOfs &= -+ ((((u32) IQM_RC_RATE_OFS_HI__M) << -+ IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); -+ status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs); -+ if (status < 0) -+ goto error; -+ -+ /* Bandwidth setting done */ -+ -+#if 0 -+ status = DVBTSetFrequencyShift(demod, channel, tunerOffset); -+ if (status < 0) -+ goto error; -+#endif -+ status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); -+ if (status < 0) -+ goto error; -+ -+ /*== Start SC, write channel settings to SC ===============================*/ -+ -+ /* Activate SCU to enable SCU commands */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ -+ /* Enable SC after setting all other parameters */ -+ status = write16(state, OFDM_SC_COMM_STATE__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, OFDM_SC_COMM_EXEC__A, 1); -+ if (status < 0) -+ goto error; -+ -+ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ -+ /* Write SC parameter registers, set all AUTO flags in operation mode */ -+ param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | -+ OFDM_SC_RA_RAM_OP_AUTO_GUARD__M | -+ OFDM_SC_RA_RAM_OP_AUTO_CONST__M | -+ OFDM_SC_RA_RAM_OP_AUTO_HIER__M | -+ OFDM_SC_RA_RAM_OP_AUTO_RATE__M); -+ status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, -+ 0, transmissionParams, param1, 0, 0, 0); -+ if (status < 0) -+ goto error; -+ -+ if (!state->m_DRXK_A3_ROM_CODE) -+ status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+ -+/*============================================================================*/ -+ -+/** -+* \brief Retreive lock status . -+* \param demod Pointer to demodulator instance. -+* \param lockStat Pointer to lock status structure. -+* \return DRXStatus_t. -+* -+*/ -+static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) -+{ -+ int status; -+ const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | -+ OFDM_SC_RA_RAM_LOCK_FEC__M); -+ const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); -+ const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; -+ -+ u16 ScRaRamLock = 0; -+ u16 ScCommExec = 0; -+ -+ dprintk(1, "\n"); -+ -+ *pLockStatus = NOT_LOCKED; -+ /* driver 0.9.0 */ -+ /* Check if SC is running */ -+ status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); -+ if (status < 0) -+ goto end; -+ if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) -+ goto end; -+ -+ status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); -+ if (status < 0) -+ goto end; -+ -+ if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) -+ *pLockStatus = MPEG_LOCK; -+ else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) -+ *pLockStatus = FEC_LOCK; -+ else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) -+ *pLockStatus = DEMOD_LOCK; -+ else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) -+ *pLockStatus = NEVER_LOCK; -+end: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static int PowerUpQAM(struct drxk_state *state) -+{ -+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; -+ int status; -+ -+ dprintk(1, "\n"); -+ status = CtrlPowerMode(state, &powerMode); -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+ -+/** Power Down QAM */ -+static int PowerDownQAM(struct drxk_state *state) -+{ -+ u16 data = 0; -+ u16 cmdResult; -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ status = read16(state, SCU_COMM_EXEC__A, &data); -+ if (status < 0) -+ goto error; -+ if (data == SCU_COMM_EXEC_ACTIVE) { -+ /* -+ STOP demodulator -+ QAM and HW blocks -+ */ -+ /* stop all comstate->m_exec */ -+ status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ } -+ /* powerdown AFE */ -+ status = SetIqmAf(state, false); -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief Setup of the QAM Measurement intervals for signal quality -+* \param demod instance of demod. -+* \param modulation current modulation. -+* \return DRXStatus_t. -+* -+* NOTE: -+* Take into account that for certain settings the errorcounters can overflow. -+* The implementation does not check this. -+* -+*/ -+static int SetQAMMeasurement(struct drxk_state *state, -+ enum EDrxkConstellation modulation, -+ u32 symbolRate) -+{ -+ u32 fecBitsDesired = 0; /* BER accounting period */ -+ u32 fecRsPeriodTotal = 0; /* Total period */ -+ u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ -+ u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ -+ fecRsPrescale = 1; -+ /* fecBitsDesired = symbolRate [kHz] * -+ FrameLenght [ms] * -+ (modulation + 1) * -+ SyncLoss (== 1) * -+ ViterbiLoss (==1) -+ */ -+ switch (modulation) { -+ case DRX_CONSTELLATION_QAM16: -+ fecBitsDesired = 4 * symbolRate; -+ break; -+ case DRX_CONSTELLATION_QAM32: -+ fecBitsDesired = 5 * symbolRate; -+ break; -+ case DRX_CONSTELLATION_QAM64: -+ fecBitsDesired = 6 * symbolRate; -+ break; -+ case DRX_CONSTELLATION_QAM128: -+ fecBitsDesired = 7 * symbolRate; -+ break; -+ case DRX_CONSTELLATION_QAM256: -+ fecBitsDesired = 8 * symbolRate; -+ break; -+ default: -+ status = -EINVAL; -+ } -+ if (status < 0) -+ goto error; -+ -+ fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ -+ fecBitsDesired *= 500; /* meas. period [ms] */ -+ -+ /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ -+ /* fecRsPeriodTotal = fecBitsDesired / 1632 */ -+ fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */ -+ -+ /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ -+ fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); -+ if (fecRsPrescale == 0) { -+ /* Divide by zero (though impossible) */ -+ status = -EINVAL; -+ if (status < 0) -+ goto error; -+ } -+ fecRsPeriod = -+ ((u16) fecRsPeriodTotal + -+ (fecRsPrescale >> 1)) / fecRsPrescale; -+ -+ /* write corresponding registers */ -+ status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int SetQAM16(struct drxk_state *state) -+{ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ /* QAM Equalizer Setup */ -+ /* Equalizer */ -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); -+ if (status < 0) -+ goto error; -+ /* Decision Feedback Equalizer */ -+ status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, QAM_SY_SYNC_HWM__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_AWM__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_LWM__A, 3); -+ if (status < 0) -+ goto error; -+ -+ /* QAM Slicer Settings */ -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); -+ if (status < 0) -+ goto error; -+ -+ /* QAM Loop Controller Coeficients */ -+ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM State Machine (FSM) Thresholds */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM FSM Tracking Parameters */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); -+ if (status < 0) -+ goto error; -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief QAM32 specific setup -+* \param demod instance of demod. -+* \return DRXStatus_t. -+*/ -+static int SetQAM32(struct drxk_state *state) -+{ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ -+ /* QAM Equalizer Setup */ -+ /* Equalizer */ -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); -+ if (status < 0) -+ goto error; -+ -+ /* Decision Feedback Equalizer */ -+ status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, QAM_SY_SYNC_HWM__A, 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_AWM__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_LWM__A, 3); -+ if (status < 0) -+ goto error; -+ -+ /* QAM Slicer Settings */ -+ -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM Loop Controller Coeficients */ -+ -+ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM State Machine (FSM) Thresholds */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM FSM Tracking Parameters */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief QAM64 specific setup -+* \param demod instance of demod. -+* \return DRXStatus_t. -+*/ -+static int SetQAM64(struct drxk_state *state) -+{ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ /* QAM Equalizer Setup */ -+ /* Equalizer */ -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); -+ if (status < 0) -+ goto error; -+ -+ /* Decision Feedback Equalizer */ -+ status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, QAM_SY_SYNC_HWM__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_AWM__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_LWM__A, 3); -+ if (status < 0) -+ goto error; -+ -+ /* QAM Slicer Settings */ -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM Loop Controller Coeficients */ -+ -+ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM State Machine (FSM) Thresholds */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM FSM Tracking Parameters */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief QAM128 specific setup -+* \param demod: instance of demod. -+* \return DRXStatus_t. -+*/ -+static int SetQAM128(struct drxk_state *state) -+{ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ /* QAM Equalizer Setup */ -+ /* Equalizer */ -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); -+ if (status < 0) -+ goto error; -+ -+ /* Decision Feedback Equalizer */ -+ status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, QAM_SY_SYNC_HWM__A, 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_AWM__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_LWM__A, 3); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM Slicer Settings */ -+ -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM Loop Controller Coeficients */ -+ -+ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM State Machine (FSM) Thresholds */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); -+ if (status < 0) -+ goto error; -+ -+ /* QAM FSM Tracking Parameters */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief QAM256 specific setup -+* \param demod: instance of demod. -+* \return DRXStatus_t. -+*/ -+static int SetQAM256(struct drxk_state *state) -+{ -+ int status = 0; -+ -+ dprintk(1, "\n"); -+ /* QAM Equalizer Setup */ -+ /* Equalizer */ -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); -+ if (status < 0) -+ goto error; -+ -+ /* Decision Feedback Equalizer */ -+ status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, QAM_SY_SYNC_HWM__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_AWM__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_SYNC_LWM__A, 3); -+ if (status < 0) -+ goto error; -+ -+ /* QAM Slicer Settings */ -+ -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM Loop Controller Coeficients */ -+ -+ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM State Machine (FSM) Thresholds */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); -+ if (status < 0) -+ goto error; -+ -+ -+ /* QAM FSM Tracking Parameters */ -+ -+ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+ -+/*============================================================================*/ -+/** -+* \brief Reset QAM block. -+* \param demod: instance of demod. -+* \param channel: pointer to channel data. -+* \return DRXStatus_t. -+*/ -+static int QAMResetQAM(struct drxk_state *state) -+{ -+ int status; -+ u16 cmdResult; -+ -+ dprintk(1, "\n"); -+ /* Stop QAM comstate->m_exec */ -+ status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief Set QAM symbolrate. -+* \param demod: instance of demod. -+* \param channel: pointer to channel data. -+* \return DRXStatus_t. -+*/ -+static int QAMSetSymbolrate(struct drxk_state *state) -+{ -+ u32 adcFrequency = 0; -+ u32 symbFreq = 0; -+ u32 iqmRcRate = 0; -+ u16 ratesel = 0; -+ u32 lcSymbRate = 0; -+ int status; -+ -+ dprintk(1, "\n"); -+ /* Select & calculate correct IQM rate */ -+ adcFrequency = (state->m_sysClockFreq * 1000) / 3; -+ ratesel = 0; -+ /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ -+ if (state->props.symbol_rate <= 1188750) -+ ratesel = 3; -+ else if (state->props.symbol_rate <= 2377500) -+ ratesel = 2; -+ else if (state->props.symbol_rate <= 4755000) -+ ratesel = 1; -+ status = write16(state, IQM_FD_RATESEL__A, ratesel); -+ if (status < 0) -+ goto error; -+ -+ /* -+ IqmRcRate = ((Fadc / (symbolrate * (4<props.symbol_rate * (1 << ratesel); -+ if (symbFreq == 0) { -+ /* Divide by zero */ -+ status = -EINVAL; -+ goto error; -+ } -+ iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + -+ (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - -+ (1 << 23); -+ status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate); -+ if (status < 0) -+ goto error; -+ state->m_iqmRcRate = iqmRcRate; -+ /* -+ LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) -+ */ -+ symbFreq = state->props.symbol_rate; -+ if (adcFrequency == 0) { -+ /* Divide by zero */ -+ status = -EINVAL; -+ goto error; -+ } -+ lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + -+ (Frac28a((symbFreq % adcFrequency), adcFrequency) >> -+ 16); -+ if (lcSymbRate > 511) -+ lcSymbRate = 511; -+ status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+/*============================================================================*/ -+ -+/** -+* \brief Get QAM lock status. -+* \param demod: instance of demod. -+* \param channel: pointer to channel data. -+* \return DRXStatus_t. -+*/ -+ -+static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) -+{ -+ int status; -+ u16 Result[2] = { 0, 0 }; -+ -+ dprintk(1, "\n"); -+ *pLockStatus = NOT_LOCKED; -+ status = scu_command(state, -+ SCU_RAM_COMMAND_STANDARD_QAM | -+ SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, -+ Result); -+ if (status < 0) -+ printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status); -+ -+ if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { -+ /* 0x0000 NOT LOCKED */ -+ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { -+ /* 0x4000 DEMOD LOCKED */ -+ *pLockStatus = DEMOD_LOCK; -+ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { -+ /* 0x8000 DEMOD + FEC LOCKED (system lock) */ -+ *pLockStatus = MPEG_LOCK; -+ } else { -+ /* 0xC000 NEVER LOCKED */ -+ /* (system will never be able to lock to the signal) */ -+ /* TODO: check this, intermediate & standard specific lock states are not -+ taken into account here */ -+ *pLockStatus = NEVER_LOCK; -+ } -+ return status; -+} -+ -+#define QAM_MIRROR__M 0x03 -+#define QAM_MIRROR_NORMAL 0x00 -+#define QAM_MIRRORED 0x01 -+#define QAM_MIRROR_AUTO_ON 0x02 -+#define QAM_LOCKRANGE__M 0x10 -+#define QAM_LOCKRANGE_NORMAL 0x10 -+ -+static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset) -+{ -+ int status; -+ u16 setParamParameters[4] = { 0, 0, 0, 0 }; -+ u16 cmdResult; -+ -+ dprintk(1, "\n"); -+ /* -+ * STEP 1: reset demodulator -+ * resets FEC DI and FEC RS -+ * resets QAM block -+ * resets SCU variables -+ */ -+ status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = QAMResetQAM(state); -+ if (status < 0) -+ goto error; -+ -+ /* -+ * STEP 2: configure demodulator -+ * -set params; resets IQM,QAM,FEC HW; initializes some -+ * SCU variables -+ */ -+ status = QAMSetSymbolrate(state); -+ if (status < 0) -+ goto error; -+ -+ /* Set params */ -+ switch (state->props.modulation) { -+ case QAM_256: -+ state->m_Constellation = DRX_CONSTELLATION_QAM256; -+ break; -+ case QAM_AUTO: -+ case QAM_64: -+ state->m_Constellation = DRX_CONSTELLATION_QAM64; -+ break; -+ case QAM_16: -+ state->m_Constellation = DRX_CONSTELLATION_QAM16; -+ break; -+ case QAM_32: -+ state->m_Constellation = DRX_CONSTELLATION_QAM32; -+ break; -+ case QAM_128: -+ state->m_Constellation = DRX_CONSTELLATION_QAM128; -+ break; -+ default: -+ status = -EINVAL; -+ break; -+ } -+ if (status < 0) -+ goto error; -+ setParamParameters[0] = state->m_Constellation; /* modulation */ -+ setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ -+ if (state->m_OperationMode == OM_QAM_ITU_C) -+ setParamParameters[2] = QAM_TOP_ANNEX_C; -+ else -+ setParamParameters[2] = QAM_TOP_ANNEX_A; -+ setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); -+ /* Env parameters */ -+ /* check for LOCKRANGE Extented */ -+ /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */ -+ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult); -+ if (status < 0) { -+ /* Fall-back to the simpler call */ -+ if (state->m_OperationMode == OM_QAM_ITU_C) -+ setParamParameters[0] = QAM_TOP_ANNEX_C; -+ else -+ setParamParameters[0] = QAM_TOP_ANNEX_A; -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ -+ setParamParameters[0] = state->m_Constellation; /* modulation */ -+ setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult); -+ } -+ if (status < 0) -+ goto error; -+ -+ /* -+ * STEP 3: enable the system in a mode where the ADC provides valid -+ * signal setup modulation independent registers -+ */ -+#if 0 -+ status = SetFrequency(channel, tunerFreqOffset)); -+ if (status < 0) -+ goto error; -+#endif -+ status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); -+ if (status < 0) -+ goto error; -+ -+ /* Setup BER measurement */ -+ status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate); -+ if (status < 0) -+ goto error; -+ -+ /* Reset default values */ -+ status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); -+ if (status < 0) -+ goto error; -+ -+ /* Reset default LC values */ -+ status = write16(state, QAM_LC_RATE_LIMIT__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_LPF_FACTORP__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_LPF_FACTORI__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_MODE__A, 7); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, QAM_LC_QUAL_TAB0__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB1__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB2__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB3__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB4__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB5__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB6__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB8__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB9__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB10__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB12__A, 2); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB15__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB16__A, 3); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB20__A, 4); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_LC_QUAL_TAB25__A, 4); -+ if (status < 0) -+ goto error; -+ -+ /* Mirroring, QAM-block starting point not inverted */ -+ status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); -+ if (status < 0) -+ goto error; -+ -+ /* Halt SCU to enable safe non-atomic accesses */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); -+ if (status < 0) -+ goto error; -+ -+ /* STEP 4: modulation specific setup */ -+ switch (state->props.modulation) { -+ case QAM_16: -+ status = SetQAM16(state); -+ break; -+ case QAM_32: -+ status = SetQAM32(state); -+ break; -+ case QAM_AUTO: -+ case QAM_64: -+ status = SetQAM64(state); -+ break; -+ case QAM_128: -+ status = SetQAM128(state); -+ break; -+ case QAM_256: -+ status = SetQAM256(state); -+ break; -+ default: -+ status = -EINVAL; -+ break; -+ } -+ if (status < 0) -+ goto error; -+ -+ /* Activate SCU to enable SCU commands */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ -+ /* Re-configure MPEG output, requires knowledge of channel bitrate */ -+ /* extAttr->currentChannel.modulation = channel->modulation; */ -+ /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ -+ status = MPEGTSDtoSetup(state, state->m_OperationMode); -+ if (status < 0) -+ goto error; -+ -+ /* Start processes */ -+ status = MPEGTSStart(state); -+ if (status < 0) -+ goto error; -+ status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); -+ if (status < 0) -+ goto error; -+ -+ /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); -+ if (status < 0) -+ goto error; -+ -+ /* update global DRXK data container */ -+/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ -+ -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int SetQAMStandard(struct drxk_state *state, -+ enum OperationMode oMode) -+{ -+ int status; -+#ifdef DRXK_QAM_TAPS -+#define DRXK_QAMA_TAPS_SELECT -+#include "drxk_filters.h" -+#undef DRXK_QAMA_TAPS_SELECT -+#endif -+ -+ dprintk(1, "\n"); -+ -+ /* added antenna switch */ -+ SwitchAntennaToQAM(state); -+ -+ /* Ensure correct power-up mode */ -+ status = PowerUpQAM(state); -+ if (status < 0) -+ goto error; -+ /* Reset QAM block */ -+ status = QAMResetQAM(state); -+ if (status < 0) -+ goto error; -+ -+ /* Setup IQM */ -+ -+ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); -+ if (status < 0) -+ goto error; -+ -+ /* Upload IQM Channel Filter settings by -+ boot loader from ROM table */ -+ switch (oMode) { -+ case OM_QAM_ITU_A: -+ status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); -+ break; -+ case OM_QAM_ITU_C: -+ status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); -+ if (status < 0) -+ goto error; -+ status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); -+ break; -+ default: -+ status = -EINVAL; -+ } -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_SYMMETRIC__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, IQM_RC_STRETCH__A, 21); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_CLP_LEN__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_CLP_TH__A, 448); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_SNS_LEN__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, IQM_FS_ADJ_SEL__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_RC_ADJ_SEL__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_ADJ_SEL__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_UPD_SEL__A, 0); -+ if (status < 0) -+ goto error; -+ -+ /* IQM Impulse Noise Processing Unit */ -+ status = write16(state, IQM_CF_CLP_VAL__A, 500); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_DATATH__A, 1000); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_BYPASSDET__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_DET_LCT__A, 0); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_WND_LEN__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_CF_PKDTH__A, 1); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_INC_BYPASS__A, 1); -+ if (status < 0) -+ goto error; -+ -+ /* turn on IQMAF. Must be done before setAgc**() */ -+ status = SetIqmAf(state, true); -+ if (status < 0) -+ goto error; -+ status = write16(state, IQM_AF_START_LOCK__A, 0x01); -+ if (status < 0) -+ goto error; -+ -+ /* IQM will not be reset from here, sync ADC and update/init AGC */ -+ status = ADCSynchronization(state); -+ if (status < 0) -+ goto error; -+ -+ /* Set the FSM step period */ -+ status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); -+ if (status < 0) -+ goto error; -+ -+ /* Halt SCU to enable safe non-atomic accesses */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); -+ if (status < 0) -+ goto error; -+ -+ /* No more resets of the IQM, current standard correctly set => -+ now AGCs can be configured. */ -+ -+ status = InitAGC(state, true); -+ if (status < 0) -+ goto error; -+ status = SetPreSaw(state, &(state->m_qamPreSawCfg)); -+ if (status < 0) -+ goto error; -+ -+ /* Configure AGC's */ -+ status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true); -+ if (status < 0) -+ goto error; -+ status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true); -+ if (status < 0) -+ goto error; -+ -+ /* Activate SCU to enable SCU commands */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int WriteGPIO(struct drxk_state *state) -+{ -+ int status; -+ u16 value = 0; -+ -+ dprintk(1, "\n"); -+ /* stop lock indicator process */ -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ if (status < 0) -+ goto error; -+ -+ /* Write magic word to enable pdr reg write */ -+ status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); -+ if (status < 0) -+ goto error; -+ -+ if (state->m_hasSAWSW) { -+ if (state->UIO_mask & 0x0001) { /* UIO-1 */ -+ /* write to io pad configuration register - output mode */ -+ status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); -+ if (status < 0) -+ goto error; -+ -+ /* use corresponding bit in io data output registar */ -+ status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); -+ if (status < 0) -+ goto error; -+ if ((state->m_GPIO & 0x0001) == 0) -+ value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ -+ else -+ value |= 0x8000; /* write one to 15th bit - 1st UIO */ -+ /* write back to io data output register */ -+ status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); -+ if (status < 0) -+ goto error; -+ } -+ if (state->UIO_mask & 0x0002) { /* UIO-2 */ -+ /* write to io pad configuration register - output mode */ -+ status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg); -+ if (status < 0) -+ goto error; -+ -+ /* use corresponding bit in io data output registar */ -+ status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); -+ if (status < 0) -+ goto error; -+ if ((state->m_GPIO & 0x0002) == 0) -+ value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ -+ else -+ value |= 0x4000; /* write one to 14th bit - 2st UIO */ -+ /* write back to io data output register */ -+ status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); -+ if (status < 0) -+ goto error; -+ } -+ if (state->UIO_mask & 0x0004) { /* UIO-3 */ -+ /* write to io pad configuration register - output mode */ -+ status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg); -+ if (status < 0) -+ goto error; -+ -+ /* use corresponding bit in io data output registar */ -+ status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); -+ if (status < 0) -+ goto error; -+ if ((state->m_GPIO & 0x0004) == 0) -+ value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ -+ else -+ value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ -+ /* write back to io data output register */ -+ status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); -+ if (status < 0) -+ goto error; -+ } -+ } -+ /* Write magic word to disable pdr reg write */ -+ status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int SwitchAntennaToQAM(struct drxk_state *state) -+{ -+ int status = 0; -+ bool gpio_state; -+ -+ dprintk(1, "\n"); -+ -+ if (!state->antenna_gpio) -+ return 0; -+ -+ gpio_state = state->m_GPIO & state->antenna_gpio; -+ -+ if (state->antenna_dvbt ^ gpio_state) { -+ /* Antenna is on DVB-T mode. Switch */ -+ if (state->antenna_dvbt) -+ state->m_GPIO &= ~state->antenna_gpio; -+ else -+ state->m_GPIO |= state->antenna_gpio; -+ status = WriteGPIO(state); -+ } -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+static int SwitchAntennaToDVBT(struct drxk_state *state) -+{ -+ int status = 0; -+ bool gpio_state; -+ -+ dprintk(1, "\n"); -+ -+ if (!state->antenna_gpio) -+ return 0; -+ -+ gpio_state = state->m_GPIO & state->antenna_gpio; -+ -+ if (!(state->antenna_dvbt ^ gpio_state)) { -+ /* Antenna is on DVB-C mode. Switch */ -+ if (state->antenna_dvbt) -+ state->m_GPIO |= state->antenna_gpio; -+ else -+ state->m_GPIO &= ~state->antenna_gpio; -+ status = WriteGPIO(state); -+ } -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+} -+ -+ -+static int PowerDownDevice(struct drxk_state *state) -+{ -+ /* Power down to requested mode */ -+ /* Backup some register settings */ -+ /* Set pins with possible pull-ups connected to them in input mode */ -+ /* Analog power down */ -+ /* ADC power down */ -+ /* Power down device */ -+ int status; -+ -+ dprintk(1, "\n"); -+ if (state->m_bPDownOpenBridge) { -+ /* Open I2C bridge before power down of DRXK */ -+ status = ConfigureI2CBridge(state, true); -+ if (status < 0) -+ goto error; -+ } -+ /* driver 0.9.0 */ -+ status = DVBTEnableOFDMTokenRing(state, false); -+ if (status < 0) -+ goto error; -+ -+ status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); -+ if (status < 0) -+ goto error; -+ state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -+ status = HI_CfgCommand(state); -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static int load_microcode(struct drxk_state *state, const char *mc_name) -+{ -+ const struct firmware *fw = NULL; -+ int err = 0; -+ -+ dprintk(1, "\n"); -+ -+ err = request_firmware(&fw, mc_name, state->i2c->dev.parent); -+ if (err < 0) { -+ printk(KERN_ERR -+ "drxk: Could not load firmware file %s.\n", mc_name); -+ printk(KERN_INFO -+ "drxk: Copy %s to your hotplug directory!\n", mc_name); -+ return err; -+ } -+ err = DownloadMicrocode(state, fw->data, fw->size); -+ release_firmware(fw); -+ return err; -+} -+ -+static int init_drxk(struct drxk_state *state) -+{ -+ int status = 0; -+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; -+ u16 driverVersion; -+ -+ dprintk(1, "\n"); -+ if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { -+ status = PowerUpDevice(state); -+ if (status < 0) -+ goto error; -+ status = DRXX_Open(state); -+ if (status < 0) -+ goto error; -+ /* Soft reset of OFDM-, sys- and osc-clockdomain */ -+ status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M); -+ if (status < 0) -+ goto error; -+ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); -+ if (status < 0) -+ goto error; -+ /* TODO is this needed, if yes how much delay in worst case scenario */ -+ msleep(1); -+ state->m_DRXK_A3_PATCH_CODE = true; -+ status = GetDeviceCapabilities(state); -+ if (status < 0) -+ goto error; -+ -+ /* Bridge delay, uses oscilator clock */ -+ /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ -+ /* SDA brdige delay */ -+ state->m_HICfgBridgeDelay = -+ (u16) ((state->m_oscClockFreq / 1000) * -+ HI_I2C_BRIDGE_DELAY) / 1000; -+ /* Clipping */ -+ if (state->m_HICfgBridgeDelay > -+ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { -+ state->m_HICfgBridgeDelay = -+ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; -+ } -+ /* SCL bridge delay, same as SDA for now */ -+ state->m_HICfgBridgeDelay += -+ state->m_HICfgBridgeDelay << -+ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; -+ -+ status = InitHI(state); -+ if (status < 0) -+ goto error; -+ /* disable various processes */ -+#if NOA1ROM -+ if (!(state->m_DRXK_A1_ROM_CODE) -+ && !(state->m_DRXK_A2_ROM_CODE)) -+#endif -+ { -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ if (status < 0) -+ goto error; -+ } -+ -+ /* disable MPEG port */ -+ status = MPEGTSDisable(state); -+ if (status < 0) -+ goto error; -+ -+ /* Stop AUD and SCU */ -+ status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ -+ /* enable token-ring bus through OFDM block for possible ucode upload */ -+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON); -+ if (status < 0) -+ goto error; -+ -+ /* include boot loader section */ -+ status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ status = BLChainCmd(state, 0, 6, 100); -+ if (status < 0) -+ goto error; -+ -+ if (state->microcode_name) -+ load_microcode(state, state->microcode_name); -+ -+ /* disable token-ring bus through OFDM block for possible ucode upload */ -+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); -+ if (status < 0) -+ goto error; -+ -+ /* Run SCU for a little while to initialize microcode version numbers */ -+ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); -+ if (status < 0) -+ goto error; -+ status = DRXX_Open(state); -+ if (status < 0) -+ goto error; -+ /* added for test */ -+ msleep(30); -+ -+ powerMode = DRXK_POWER_DOWN_OFDM; -+ status = CtrlPowerMode(state, &powerMode); -+ if (status < 0) -+ goto error; -+ -+ /* Stamp driver version number in SCU data RAM in BCD code -+ Done to enable field application engineers to retreive drxdriver version -+ via I2C from SCU RAM. -+ Not using SCU command interface for SCU register access since no -+ microcode may be present. -+ */ -+ driverVersion = -+ (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + -+ (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + -+ ((DRXK_VERSION_MAJOR % 10) << 4) + -+ (DRXK_VERSION_MINOR % 10); -+ status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion); -+ if (status < 0) -+ goto error; -+ driverVersion = -+ (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + -+ (((DRXK_VERSION_PATCH / 100) % 10) << 8) + -+ (((DRXK_VERSION_PATCH / 10) % 10) << 4) + -+ (DRXK_VERSION_PATCH % 10); -+ status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion); -+ if (status < 0) -+ goto error; -+ -+ printk(KERN_INFO "DRXK driver version %d.%d.%d\n", -+ DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, -+ DRXK_VERSION_PATCH); -+ -+ /* Dirty fix of default values for ROM/PATCH microcode -+ Dirty because this fix makes it impossible to setup suitable values -+ before calling DRX_Open. This solution requires changes to RF AGC speed -+ to be done via the CTRL function after calling DRX_Open */ -+ -+ /* m_dvbtRfAgcCfg.speed = 3; */ -+ -+ /* Reset driver debug flags to 0 */ -+ status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); -+ if (status < 0) -+ goto error; -+ /* driver 0.9.0 */ -+ /* Setup FEC OC: -+ NOTE: No more full FEC resets allowed afterwards!! */ -+ status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); -+ if (status < 0) -+ goto error; -+ /* MPEGTS functions are still the same */ -+ status = MPEGTSDtoInit(state); -+ if (status < 0) -+ goto error; -+ status = MPEGTSStop(state); -+ if (status < 0) -+ goto error; -+ status = MPEGTSConfigurePolarity(state); -+ if (status < 0) -+ goto error; -+ status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput); -+ if (status < 0) -+ goto error; -+ /* added: configure GPIO */ -+ status = WriteGPIO(state); -+ if (status < 0) -+ goto error; -+ -+ state->m_DrxkState = DRXK_STOPPED; -+ -+ if (state->m_bPowerDown) { -+ status = PowerDownDevice(state); -+ if (status < 0) -+ goto error; -+ state->m_DrxkState = DRXK_POWERED_DOWN; -+ } else -+ state->m_DrxkState = DRXK_STOPPED; -+ } -+error: -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ -+ return status; -+} -+ -+static void drxk_release(struct dvb_frontend *fe) -+{ -+ struct drxk_state *state = fe->demodulator_priv; -+ -+ dprintk(1, "\n"); -+ kfree(state); -+} -+ -+static int drxk_sleep(struct dvb_frontend *fe) -+{ -+ struct drxk_state *state = fe->demodulator_priv; -+ -+ dprintk(1, "\n"); -+ ShutDown(state); -+ return 0; -+} -+ -+static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) -+{ -+ struct drxk_state *state = fe->demodulator_priv; -+ -+ dprintk(1, "%s\n", enable ? "enable" : "disable"); -+ return ConfigureI2CBridge(state, enable ? true : false); -+} -+ -+static int drxk_set_parameters(struct dvb_frontend *fe) -+{ -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ u32 delsys = p->delivery_system, old_delsys; -+ struct drxk_state *state = fe->demodulator_priv; -+ u32 IF; -+ -+ dprintk(1, "\n"); -+ -+ if (!fe->ops.tuner_ops.get_if_frequency) { -+ printk(KERN_ERR -+ "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); -+ return -EINVAL; -+ } -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ -+ old_delsys = state->props.delivery_system; -+ state->props = *p; -+ -+ if (old_delsys != delsys) { -+ ShutDown(state); -+ switch (delsys) { -+ case SYS_DVBC_ANNEX_A: -+ case SYS_DVBC_ANNEX_C: -+ if (!state->m_hasDVBC) -+ return -EINVAL; -+ state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; -+ if (state->m_itut_annex_c) -+ SetOperationMode(state, OM_QAM_ITU_C); -+ else -+ SetOperationMode(state, OM_QAM_ITU_A); -+ break; -+ case SYS_DVBT: -+ if (!state->m_hasDVBT) -+ return -EINVAL; -+ SetOperationMode(state, OM_DVBT); -+ break; -+ default: -+ return -EINVAL; -+ } -+ } -+ -+ fe->ops.tuner_ops.get_if_frequency(fe, &IF); -+ Start(state, 0, IF); -+ -+ /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ -+ -+ return 0; -+} -+ -+static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) -+{ -+ struct drxk_state *state = fe->demodulator_priv; -+ u32 stat; -+ -+ dprintk(1, "\n"); -+ *status = 0; -+ GetLockStatus(state, &stat, 0); -+ if (stat == MPEG_LOCK) -+ *status |= 0x1f; -+ if (stat == FEC_LOCK) -+ *status |= 0x0f; -+ if (stat == DEMOD_LOCK) -+ *status |= 0x07; -+ return 0; -+} -+ -+static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) -+{ -+ dprintk(1, "\n"); -+ -+ *ber = 0; -+ return 0; -+} -+ -+static int drxk_read_signal_strength(struct dvb_frontend *fe, -+ u16 *strength) -+{ -+ struct drxk_state *state = fe->demodulator_priv; -+ u32 val = 0; -+ -+ dprintk(1, "\n"); -+ ReadIFAgc(state, &val); -+ *strength = val & 0xffff; -+ return 0; -+} -+ -+static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) -+{ -+ struct drxk_state *state = fe->demodulator_priv; -+ s32 snr2; -+ -+ dprintk(1, "\n"); -+ GetSignalToNoise(state, &snr2); -+ *snr = snr2 & 0xffff; -+ return 0; -+} -+ -+static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -+{ -+ struct drxk_state *state = fe->demodulator_priv; -+ u16 err; -+ -+ dprintk(1, "\n"); -+ DVBTQAMGetAccPktErr(state, &err); -+ *ucblocks = (u32) err; -+ return 0; -+} -+ -+static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings -+ *sets) -+{ -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ -+ dprintk(1, "\n"); -+ switch (p->delivery_system) { -+ case SYS_DVBC_ANNEX_A: -+ case SYS_DVBC_ANNEX_C: -+ case SYS_DVBT: -+ sets->min_delay_ms = 3000; -+ sets->max_drift = 0; -+ sets->step_size = 0; -+ return 0; -+ default: -+ return -EINVAL; -+ } -+} -+ -+static struct dvb_frontend_ops drxk_ops = { -+ /* .delsys will be filled dynamically */ -+ .info = { -+ .name = "DRXK", -+ .frequency_min = 47000000, -+ .frequency_max = 865000000, -+ /* For DVB-C */ -+ .symbol_rate_min = 870000, -+ .symbol_rate_max = 11700000, -+ /* For DVB-T */ -+ .frequency_stepsize = 166667, -+ -+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | -+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | -+ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS | -+ FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | -+ FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO -+ }, -+ -+ .release = drxk_release, -+ .sleep = drxk_sleep, -+ .i2c_gate_ctrl = drxk_gate_ctrl, -+ -+ .set_frontend = drxk_set_parameters, -+ .get_tune_settings = drxk_get_tune_settings, -+ -+ .read_status = drxk_read_status, -+ .read_ber = drxk_read_ber, -+ .read_signal_strength = drxk_read_signal_strength, -+ .read_snr = drxk_read_snr, -+ .read_ucblocks = drxk_read_ucblocks, -+}; -+ -+struct dvb_frontend *drxk_attach(const struct drxk_config *config, -+ struct i2c_adapter *i2c) -+{ -+ int n; -+ -+ struct drxk_state *state = NULL; -+ u8 adr = config->adr; -+ -+ dprintk(1, "\n"); -+ state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); -+ if (!state) -+ return NULL; -+ -+ state->i2c = i2c; -+ state->demod_address = adr; -+ state->single_master = config->single_master; -+ state->microcode_name = config->microcode_name; -+ state->no_i2c_bridge = config->no_i2c_bridge; -+ state->antenna_gpio = config->antenna_gpio; -+ state->antenna_dvbt = config->antenna_dvbt; -+ state->m_ChunkSize = config->chunk_size; -+ state->enable_merr_cfg = config->enable_merr_cfg; -+ -+ if (config->dynamic_clk) { -+ state->m_DVBTStaticCLK = 0; -+ state->m_DVBCStaticCLK = 0; -+ } else { -+ state->m_DVBTStaticCLK = 1; -+ state->m_DVBCStaticCLK = 1; -+ } -+ -+ -+ if (config->mpeg_out_clk_strength) -+ state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07; -+ else -+ state->m_TSClockkStrength = 0x06; -+ -+ if (config->parallel_ts) -+ state->m_enableParallel = true; -+ else -+ state->m_enableParallel = false; -+ -+ /* NOTE: as more UIO bits will be used, add them to the mask */ -+ state->UIO_mask = config->antenna_gpio; -+ -+ /* Default gpio to DVB-C */ -+ if (!state->antenna_dvbt && state->antenna_gpio) -+ state->m_GPIO |= state->antenna_gpio; -+ else -+ state->m_GPIO &= ~state->antenna_gpio; -+ -+ mutex_init(&state->mutex); -+ -+ memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); -+ state->frontend.demodulator_priv = state; -+ -+ init_state(state); -+ if (init_drxk(state) < 0) -+ goto error; -+ -+ /* Initialize the supported delivery systems */ -+ n = 0; -+ if (state->m_hasDVBC) { -+ state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; -+ state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; -+ strlcat(state->frontend.ops.info.name, " DVB-C", -+ sizeof(state->frontend.ops.info.name)); -+ } -+ if (state->m_hasDVBT) { -+ state->frontend.ops.delsys[n++] = SYS_DVBT; -+ strlcat(state->frontend.ops.info.name, " DVB-T", -+ sizeof(state->frontend.ops.info.name)); -+ } -+ -+ printk(KERN_INFO "drxk: frontend initialized.\n"); -+ return &state->frontend; -+ -+error: -+ printk(KERN_ERR "drxk: not found\n"); -+ kfree(state); -+ return NULL; -+} -+EXPORT_SYMBOL(drxk_attach); -+ -+MODULE_DESCRIPTION("DRX-K driver"); -+MODULE_AUTHOR("Ralph Metzler"); -+MODULE_LICENSE("GPL"); -diff --git a/frontends/drxk_hard.h b/frontends/drxk_hard.h -index 78e8e7a..4bbf841 100644 ---- a/frontends/drxk_hard.h -+++ b/frontends/drxk_hard.h -@@ -1,343 +1,349 @@ --#include "drxk_map.h" -- --#define DRXK_VERSION_MAJOR 0 --#define DRXK_VERSION_MINOR 9 --#define DRXK_VERSION_PATCH 4300 -- --#define HI_I2C_DELAY 42 --#define HI_I2C_BRIDGE_DELAY 350 --#define DRXK_MAX_RETRIES 100 -- --#define DRIVER_4400 1 -- --#define DRXX_JTAGID 0x039210D9 --#define DRXX_J_JTAGID 0x239310D9 --#define DRXX_K_JTAGID 0x039210D9 -- --#define DRX_UNKNOWN 254 --#define DRX_AUTO 255 -- --#define DRX_SCU_READY 0 --#define DRXK_MAX_WAITTIME (200) --#define SCU_RESULT_OK 0 --#define SCU_RESULT_UNKSTD -2 --#define SCU_RESULT_UNKCMD -1 -- --#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT --#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) --#endif -- --#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ --#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ --#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ --#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ --#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ --#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ --#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ --#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ -- --#define IQM_CF_OUT_ENA_OFDM__M 0x4 --#define IQM_FS_ADJ_SEL_B_QAM 0x1 --#define IQM_FS_ADJ_SEL_B_OFF 0x0 --#define IQM_FS_ADJ_SEL_B_VSB 0x2 --#define IQM_RC_ADJ_SEL_B_OFF 0x0 --#define IQM_RC_ADJ_SEL_B_QAM 0x1 --#define IQM_RC_ADJ_SEL_B_VSB 0x2 -- --enum OperationMode { -- OM_NONE, -- OM_QAM_ITU_A, -- OM_QAM_ITU_B, -- OM_QAM_ITU_C, -- OM_DVBT --}; -- --typedef enum { -- DRX_POWER_UP = 0, -- DRX_POWER_MODE_1, -- DRX_POWER_MODE_2, -- DRX_POWER_MODE_3, -- DRX_POWER_MODE_4, -- DRX_POWER_MODE_5, -- DRX_POWER_MODE_6, -- DRX_POWER_MODE_7, -- DRX_POWER_MODE_8, -- -- DRX_POWER_MODE_9, -- DRX_POWER_MODE_10, -- DRX_POWER_MODE_11, -- DRX_POWER_MODE_12, -- DRX_POWER_MODE_13, -- DRX_POWER_MODE_14, -- DRX_POWER_MODE_15, -- DRX_POWER_MODE_16, -- DRX_POWER_DOWN = 255 --}DRXPowerMode_t, *pDRXPowerMode_t; -- -- --/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ --#ifndef DRXK_POWER_DOWN_OFDM --#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 --#endif -- --/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ --#ifndef DRXK_POWER_DOWN_CORE --#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 --#endif -- --/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ --#ifndef DRXK_POWER_DOWN_PLL --#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 --#endif -- -- --enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; --enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; --enum EDrxkCoefArrayIndex { -- DRXK_COEF_IDX_MN = 0, -- DRXK_COEF_IDX_FM , -- DRXK_COEF_IDX_L , -- DRXK_COEF_IDX_LP , -- DRXK_COEF_IDX_BG , -- DRXK_COEF_IDX_DK , -- DRXK_COEF_IDX_I , -- DRXK_COEF_IDX_MAX --}; --enum EDrxkSifAttenuation { -- DRXK_SIF_ATTENUATION_0DB, -- DRXK_SIF_ATTENUATION_3DB, -- DRXK_SIF_ATTENUATION_6DB, -- DRXK_SIF_ATTENUATION_9DB --}; --enum EDrxkConstellation { -- DRX_CONSTELLATION_BPSK = 0, -- DRX_CONSTELLATION_QPSK, -- DRX_CONSTELLATION_PSK8, -- DRX_CONSTELLATION_QAM16, -- DRX_CONSTELLATION_QAM32, -- DRX_CONSTELLATION_QAM64, -- DRX_CONSTELLATION_QAM128, -- DRX_CONSTELLATION_QAM256, -- DRX_CONSTELLATION_QAM512, -- DRX_CONSTELLATION_QAM1024, -- DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, -- DRX_CONSTELLATION_AUTO = DRX_AUTO --}; --enum EDrxkInterleaveMode { -- DRXK_QAM_I12_J17 = 16, -- DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN --}; --enum { -- DRXK_SPIN_A1 = 0, -- DRXK_SPIN_A2, -- DRXK_SPIN_A3, -- DRXK_SPIN_UNKNOWN --}; -- --enum DRXKCfgDvbtSqiSpeed { -- DRXK_DVBT_SQI_SPEED_FAST = 0, -- DRXK_DVBT_SQI_SPEED_MEDIUM, -- DRXK_DVBT_SQI_SPEED_SLOW, -- DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN --} ; -- --enum DRXFftmode_t { -- DRX_FFTMODE_2K = 0, -- DRX_FFTMODE_4K, -- DRX_FFTMODE_8K, -- DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, -- DRX_FFTMODE_AUTO = DRX_AUTO --}; -- --enum DRXMPEGStrWidth_t { -- DRX_MPEG_STR_WIDTH_1, -- DRX_MPEG_STR_WIDTH_8 --}; -- --enum DRXQamLockRange_t { -- DRX_QAM_LOCKRANGE_NORMAL, -- DRX_QAM_LOCKRANGE_EXTENDED --}; -- --struct DRXKCfgDvbtEchoThres_t { -- u16 threshold; -- enum DRXFftmode_t fftMode; --} ; -- --struct SCfgAgc --{ -- enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ -- u16 outputLevel; /* range dependent on AGC */ -- u16 minOutputLevel; /* range dependent on AGC */ -- u16 maxOutputLevel; /* range dependent on AGC */ -- u16 speed; /* range dependent on AGC */ -- u16 top; /* rf-agc take over point */ -- u16 cutOffCurrent; /* rf-agc is accelerated if output current -- is below cut-off current */ -- u16 IngainTgtMax; -- u16 FastClipCtrlDelay; --}; -- --struct SCfgPreSaw --{ -- u16 reference; /* pre SAW reference value, range 0 .. 31 */ -- bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ --}; -- --struct DRXKOfdmScCmd_t --{ -- u16 cmd; /**< Command number */ -- u16 subcmd; /**< Sub-command parameter*/ -- u16 param0; /**< General purpous param */ -- u16 param1; /**< General purpous param */ -- u16 param2; /**< General purpous param */ -- u16 param3; /**< General purpous param */ -- u16 param4; /**< General purpous param */ --}; -- --struct drxk_state { -- struct dvb_frontend c_frontend; -- struct dvb_frontend t_frontend; --#ifndef USE_API3 -- struct dtv_frontend_properties props; --#else -- struct dvb_frontend_parameters param; --#endif -- struct device *dev; -- -- struct i2c_adapter *i2c; -- u8 demod_address; -- void *priv; -- -- struct mutex mutex; -- struct mutex ctlock; -- -- u32 m_Instance; ///< Channel 1,2,3 or 4 -- -- int m_ChunkSize; -- u8 Chunk[256]; -- -- bool m_hasLNA; -- bool m_hasDVBT; -- bool m_hasDVBC; -- bool m_hasAudio; -- bool m_hasATV; -- bool m_hasOOB; -- bool m_hasSAWSW; /**< TRUE if mat_tx is available */ -- bool m_hasGPIO1; /**< TRUE if mat_rx is available */ -- bool m_hasGPIO2; /**< TRUE if GPIO is available */ -- bool m_hasIRQN; /**< TRUE if IRQN is available */ -- u16 m_oscClockFreq; -- u16 m_HICfgTimingDiv; -- u16 m_HICfgBridgeDelay; -- u16 m_HICfgWakeUpKey; -- u16 m_HICfgTimeout; -- u16 m_HICfgCtrl; -- s32 m_sysClockFreq ; ///< system clock frequency in kHz -- -- enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started) -- enum OperationMode m_OperationMode; ///< digital standards -- struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC -- struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC -- u16 m_vsbPgaCfg; ///< settings for VSB PGA -- struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense -- s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication -- s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication -- bool m_smartAntInverted; -- bool m_bDebugEnableBridge; -- bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed -- bool m_bPowerDown; ///< Power down when not used -- -- u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint) -- -- bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ -- bool m_insertRSByte; /**< If TRUE, insert RS byte */ -- bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ -- bool m_invertDATA; /**< If TRUE, invert DATA signals */ -- bool m_invertERR; /**< If TRUE, invert ERR signal */ -- bool m_invertSTR; /**< If TRUE, invert STR signals */ -- bool m_invertVAL; /**< If TRUE, invert VAL signals */ -- bool m_invertCLK; /**< If TRUE, invert CLK signals */ -- bool m_DVBCStaticCLK; -- bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will -- be used, otherwise clockrate will -- adapt to the bitrate of the TS */ -- u32 m_DVBTBitrate; -- u32 m_DVBCBitrate; -- -- u8 m_TSDataStrength; -- u8 m_TSClockkStrength; -- -- enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/ -- u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case -- static clockrate is selected */ -- -- //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start -- s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) -- s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) -- -- bool m_disableTEIhandling; -- -- bool m_RfAgcPol; -- bool m_IfAgcPol; -- -- struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC -- struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC -- struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense -- bool m_phaseCorrectionBypass; -- s16 m_atvTopVidPeak; -- u16 m_atvTopNoiseTh; -- enum EDrxkSifAttenuation m_sifAttenuation; -- bool m_enableCVBSOutput; -- bool m_enableSIFOutput; -- bool m_bMirrorFreqSpect; -- enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel -- u32 m_CurrSymbolRate; ///< Current QAM symbol rate -- struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC -- struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC -- u16 m_qamPgaCfg; ///< settings for QAM PGA -- struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense -- enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode -- u16 m_fecRsPlen; -- u16 m_fecRsPrescale; -- -- enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; -- -- u16 m_GPIO; -- u16 m_GPIOCfg; -- -- struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC -- struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC -- struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense -- -- u16 m_agcFastClipCtrlDelay; -- bool m_adcCompPassed; -- u16 m_adcCompCoef[64]; -- u16 m_adcState; -- -- u8 *m_microcode; -- int m_microcode_length; -- bool m_DRXK_A1_PATCH_CODE; -- bool m_DRXK_A1_ROM_CODE; -- bool m_DRXK_A2_ROM_CODE; -- bool m_DRXK_A3_ROM_CODE; -- bool m_DRXK_A2_PATCH_CODE; -- bool m_DRXK_A3_PATCH_CODE; -- -- bool m_rfmirror; -- u8 m_deviceSpin; -- u32 m_iqmRcRate; -- -- u16 m_AntennaDVBC; -- u16 m_AntennaDVBT; -- u16 m_AntennaSwitchDVBTDVBC; -- -- DRXPowerMode_t m_currentPowerMode; --}; -- --#define NEVER_LOCK 0 --#define NOT_LOCKED 1 --#define DEMOD_LOCK 2 --#define FEC_LOCK 3 --#define MPEG_LOCK 4 -- -+#include "drxk_map.h" -+ -+#define DRXK_VERSION_MAJOR 0 -+#define DRXK_VERSION_MINOR 9 -+#define DRXK_VERSION_PATCH 4300 -+ -+#define HI_I2C_DELAY 42 -+#define HI_I2C_BRIDGE_DELAY 350 -+#define DRXK_MAX_RETRIES 100 -+ -+#define DRIVER_4400 1 -+ -+#define DRXX_JTAGID 0x039210D9 -+#define DRXX_J_JTAGID 0x239310D9 -+#define DRXX_K_JTAGID 0x039210D9 -+ -+#define DRX_UNKNOWN 254 -+#define DRX_AUTO 255 -+ -+#define DRX_SCU_READY 0 -+#define DRXK_MAX_WAITTIME (200) -+#define SCU_RESULT_OK 0 -+#define SCU_RESULT_SIZE -4 -+#define SCU_RESULT_INVPAR -3 -+#define SCU_RESULT_UNKSTD -2 -+#define SCU_RESULT_UNKCMD -1 -+ -+#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT -+#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) -+#endif -+ -+#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ -+#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ -+#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ -+#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ -+#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ -+#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ -+#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ -+#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ -+ -+#define IQM_CF_OUT_ENA_OFDM__M 0x4 -+#define IQM_FS_ADJ_SEL_B_QAM 0x1 -+#define IQM_FS_ADJ_SEL_B_OFF 0x0 -+#define IQM_FS_ADJ_SEL_B_VSB 0x2 -+#define IQM_RC_ADJ_SEL_B_OFF 0x0 -+#define IQM_RC_ADJ_SEL_B_QAM 0x1 -+#define IQM_RC_ADJ_SEL_B_VSB 0x2 -+ -+enum OperationMode { -+ OM_NONE, -+ OM_QAM_ITU_A, -+ OM_QAM_ITU_B, -+ OM_QAM_ITU_C, -+ OM_DVBT -+}; -+ -+enum DRXPowerMode { -+ DRX_POWER_UP = 0, -+ DRX_POWER_MODE_1, -+ DRX_POWER_MODE_2, -+ DRX_POWER_MODE_3, -+ DRX_POWER_MODE_4, -+ DRX_POWER_MODE_5, -+ DRX_POWER_MODE_6, -+ DRX_POWER_MODE_7, -+ DRX_POWER_MODE_8, -+ -+ DRX_POWER_MODE_9, -+ DRX_POWER_MODE_10, -+ DRX_POWER_MODE_11, -+ DRX_POWER_MODE_12, -+ DRX_POWER_MODE_13, -+ DRX_POWER_MODE_14, -+ DRX_POWER_MODE_15, -+ DRX_POWER_MODE_16, -+ DRX_POWER_DOWN = 255 -+}; -+ -+ -+/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ -+#ifndef DRXK_POWER_DOWN_OFDM -+#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 -+#endif -+ -+/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ -+#ifndef DRXK_POWER_DOWN_CORE -+#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 -+#endif -+ -+/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ -+#ifndef DRXK_POWER_DOWN_PLL -+#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 -+#endif -+ -+ -+enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; -+enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; -+enum EDrxkCoefArrayIndex { -+ DRXK_COEF_IDX_MN = 0, -+ DRXK_COEF_IDX_FM , -+ DRXK_COEF_IDX_L , -+ DRXK_COEF_IDX_LP , -+ DRXK_COEF_IDX_BG , -+ DRXK_COEF_IDX_DK , -+ DRXK_COEF_IDX_I , -+ DRXK_COEF_IDX_MAX -+}; -+enum EDrxkSifAttenuation { -+ DRXK_SIF_ATTENUATION_0DB, -+ DRXK_SIF_ATTENUATION_3DB, -+ DRXK_SIF_ATTENUATION_6DB, -+ DRXK_SIF_ATTENUATION_9DB -+}; -+enum EDrxkConstellation { -+ DRX_CONSTELLATION_BPSK = 0, -+ DRX_CONSTELLATION_QPSK, -+ DRX_CONSTELLATION_PSK8, -+ DRX_CONSTELLATION_QAM16, -+ DRX_CONSTELLATION_QAM32, -+ DRX_CONSTELLATION_QAM64, -+ DRX_CONSTELLATION_QAM128, -+ DRX_CONSTELLATION_QAM256, -+ DRX_CONSTELLATION_QAM512, -+ DRX_CONSTELLATION_QAM1024, -+ DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, -+ DRX_CONSTELLATION_AUTO = DRX_AUTO -+}; -+enum EDrxkInterleaveMode { -+ DRXK_QAM_I12_J17 = 16, -+ DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN -+}; -+enum { -+ DRXK_SPIN_A1 = 0, -+ DRXK_SPIN_A2, -+ DRXK_SPIN_A3, -+ DRXK_SPIN_UNKNOWN -+}; -+ -+enum DRXKCfgDvbtSqiSpeed { -+ DRXK_DVBT_SQI_SPEED_FAST = 0, -+ DRXK_DVBT_SQI_SPEED_MEDIUM, -+ DRXK_DVBT_SQI_SPEED_SLOW, -+ DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN -+} ; -+ -+enum DRXFftmode_t { -+ DRX_FFTMODE_2K = 0, -+ DRX_FFTMODE_4K, -+ DRX_FFTMODE_8K, -+ DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, -+ DRX_FFTMODE_AUTO = DRX_AUTO -+}; -+ -+enum DRXMPEGStrWidth_t { -+ DRX_MPEG_STR_WIDTH_1, -+ DRX_MPEG_STR_WIDTH_8 -+}; -+ -+enum DRXQamLockRange_t { -+ DRX_QAM_LOCKRANGE_NORMAL, -+ DRX_QAM_LOCKRANGE_EXTENDED -+}; -+ -+struct DRXKCfgDvbtEchoThres_t { -+ u16 threshold; -+ enum DRXFftmode_t fftMode; -+} ; -+ -+struct SCfgAgc { -+ enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ -+ u16 outputLevel; /* range dependent on AGC */ -+ u16 minOutputLevel; /* range dependent on AGC */ -+ u16 maxOutputLevel; /* range dependent on AGC */ -+ u16 speed; /* range dependent on AGC */ -+ u16 top; /* rf-agc take over point */ -+ u16 cutOffCurrent; /* rf-agc is accelerated if output current -+ is below cut-off current */ -+ u16 IngainTgtMax; -+ u16 FastClipCtrlDelay; -+}; -+ -+struct SCfgPreSaw { -+ u16 reference; /* pre SAW reference value, range 0 .. 31 */ -+ bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ -+}; -+ -+struct DRXKOfdmScCmd_t { -+ u16 cmd; /**< Command number */ -+ u16 subcmd; /**< Sub-command parameter*/ -+ u16 param0; /**< General purpous param */ -+ u16 param1; /**< General purpous param */ -+ u16 param2; /**< General purpous param */ -+ u16 param3; /**< General purpous param */ -+ u16 param4; /**< General purpous param */ -+}; -+ -+struct drxk_state { -+ struct dvb_frontend frontend; -+ struct dtv_frontend_properties props; -+ struct device *dev; -+ -+ struct i2c_adapter *i2c; -+ u8 demod_address; -+ void *priv; -+ -+ struct mutex mutex; -+ -+ u32 m_Instance; /**< Channel 1,2,3 or 4 */ -+ -+ int m_ChunkSize; -+ u8 Chunk[256]; -+ -+ bool m_hasLNA; -+ bool m_hasDVBT; -+ bool m_hasDVBC; -+ bool m_hasAudio; -+ bool m_hasATV; -+ bool m_hasOOB; -+ bool m_hasSAWSW; /**< TRUE if mat_tx is available */ -+ bool m_hasGPIO1; /**< TRUE if mat_rx is available */ -+ bool m_hasGPIO2; /**< TRUE if GPIO is available */ -+ bool m_hasIRQN; /**< TRUE if IRQN is available */ -+ u16 m_oscClockFreq; -+ u16 m_HICfgTimingDiv; -+ u16 m_HICfgBridgeDelay; -+ u16 m_HICfgWakeUpKey; -+ u16 m_HICfgTimeout; -+ u16 m_HICfgCtrl; -+ s32 m_sysClockFreq; /**< system clock frequency in kHz */ -+ -+ enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */ -+ enum OperationMode m_OperationMode; /**< digital standards */ -+ struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */ -+ struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */ -+ u16 m_vsbPgaCfg; /**< settings for VSB PGA */ -+ struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */ -+ s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */ -+ s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */ -+ bool m_smartAntInverted; -+ bool m_bDebugEnableBridge; -+ bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */ -+ bool m_bPowerDown; /**< Power down when not used */ -+ -+ u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */ -+ -+ bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ -+ bool m_insertRSByte; /**< If TRUE, insert RS byte */ -+ bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ -+ bool m_invertDATA; /**< If TRUE, invert DATA signals */ -+ bool m_invertERR; /**< If TRUE, invert ERR signal */ -+ bool m_invertSTR; /**< If TRUE, invert STR signals */ -+ bool m_invertVAL; /**< If TRUE, invert VAL signals */ -+ bool m_invertCLK; /**< If TRUE, invert CLK signals */ -+ bool m_DVBCStaticCLK; -+ bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will -+ be used, otherwise clockrate will -+ adapt to the bitrate of the TS */ -+ u32 m_DVBTBitrate; -+ u32 m_DVBCBitrate; -+ -+ u8 m_TSDataStrength; -+ u8 m_TSClockkStrength; -+ -+ bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */ -+ -+ enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */ -+ u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case -+ static clockrate is selected */ -+ -+ /* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */ -+ s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ -+ s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ -+ -+ bool m_disableTEIhandling; -+ -+ bool m_RfAgcPol; -+ bool m_IfAgcPol; -+ -+ struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */ -+ struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */ -+ struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */ -+ bool m_phaseCorrectionBypass; -+ s16 m_atvTopVidPeak; -+ u16 m_atvTopNoiseTh; -+ enum EDrxkSifAttenuation m_sifAttenuation; -+ bool m_enableCVBSOutput; -+ bool m_enableSIFOutput; -+ bool m_bMirrorFreqSpect; -+ enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */ -+ u32 m_CurrSymbolRate; /**< Current QAM symbol rate */ -+ struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */ -+ struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */ -+ u16 m_qamPgaCfg; /**< settings for QAM PGA */ -+ struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */ -+ enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */ -+ u16 m_fecRsPlen; -+ u16 m_fecRsPrescale; -+ -+ enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; -+ -+ u16 m_GPIO; -+ u16 m_GPIOCfg; -+ -+ struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */ -+ struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */ -+ struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */ -+ -+ u16 m_agcFastClipCtrlDelay; -+ bool m_adcCompPassed; -+ u16 m_adcCompCoef[64]; -+ u16 m_adcState; -+ -+ u8 *m_microcode; -+ int m_microcode_length; -+ bool m_DRXK_A1_PATCH_CODE; -+ bool m_DRXK_A1_ROM_CODE; -+ bool m_DRXK_A2_ROM_CODE; -+ bool m_DRXK_A3_ROM_CODE; -+ bool m_DRXK_A2_PATCH_CODE; -+ bool m_DRXK_A3_PATCH_CODE; -+ -+ bool m_rfmirror; -+ u8 m_deviceSpin; -+ u32 m_iqmRcRate; -+ -+ enum DRXPowerMode m_currentPowerMode; -+ -+ /* -+ * Configurable parameters at the driver. They stores the values found -+ * at struct drxk_config. -+ */ -+ -+ u16 UIO_mask; /* Bits used by UIO */ -+ -+ bool enable_merr_cfg; -+ bool single_master; -+ bool no_i2c_bridge; -+ bool antenna_dvbt; -+ u16 antenna_gpio; -+ -+ const char *microcode_name; -+}; -+ -+#define NEVER_LOCK 0 -+#define NOT_LOCKED 1 -+#define DEMOD_LOCK 2 -+#define FEC_LOCK 3 -+#define MPEG_LOCK 4 -+ -diff --git a/frontends/drxk_map.h b/frontends/drxk_map.h -index 02895aa..23e16c1 100644 ---- a/frontends/drxk_map.h -+++ b/frontends/drxk_map.h -@@ -1,16438 +1,451 @@ --#ifndef __DRXK_MAP__H__ --#define __DRXK_MAP__H__ 1 -- --#define AUD_COMM_EXEC__A 0x1000000 --#define AUD_COMM_EXEC__W 2 --#define AUD_COMM_EXEC__M 0x3 --#define AUD_COMM_EXEC__PRE 0x0 --#define AUD_COMM_EXEC_STOP 0x0 -- --#define FEC_COMM_EXEC__A 0x1C00000 --#define FEC_COMM_EXEC__W 2 --#define FEC_COMM_EXEC__M 0x3 --#define FEC_COMM_EXEC__PRE 0x0 --#define FEC_COMM_EXEC_STOP 0x0 --#define FEC_COMM_EXEC_ACTIVE 0x1 --#define FEC_COMM_EXEC_HOLD 0x2 -- --#define FEC_COMM_MB__A 0x1C00002 --#define FEC_COMM_MB__W 16 --#define FEC_COMM_MB__M 0xFFFF --#define FEC_COMM_MB__PRE 0x0 --#define FEC_COMM_INT_REQ__A 0x1C00003 --#define FEC_COMM_INT_REQ__W 16 --#define FEC_COMM_INT_REQ__M 0xFFFF --#define FEC_COMM_INT_REQ__PRE 0x0 --#define FEC_COMM_INT_REQ_OC_REQ__B 0 --#define FEC_COMM_INT_REQ_OC_REQ__W 1 --#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 --#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 --#define FEC_COMM_INT_REQ_RS_REQ__B 1 --#define FEC_COMM_INT_REQ_RS_REQ__W 1 --#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 --#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 --#define FEC_COMM_INT_REQ_DI_REQ__B 2 --#define FEC_COMM_INT_REQ_DI_REQ__W 1 --#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 --#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 -- --#define FEC_COMM_INT_STA__A 0x1C00005 --#define FEC_COMM_INT_STA__W 16 --#define FEC_COMM_INT_STA__M 0xFFFF --#define FEC_COMM_INT_STA__PRE 0x0 --#define FEC_COMM_INT_MSK__A 0x1C00006 --#define FEC_COMM_INT_MSK__W 16 --#define FEC_COMM_INT_MSK__M 0xFFFF --#define FEC_COMM_INT_MSK__PRE 0x0 --#define FEC_COMM_INT_STM__A 0x1C00007 --#define FEC_COMM_INT_STM__W 16 --#define FEC_COMM_INT_STM__M 0xFFFF --#define FEC_COMM_INT_STM__PRE 0x0 -- -- -- --#define FEC_TOP_COMM_EXEC__A 0x1C10000 --#define FEC_TOP_COMM_EXEC__W 2 --#define FEC_TOP_COMM_EXEC__M 0x3 --#define FEC_TOP_COMM_EXEC__PRE 0x0 --#define FEC_TOP_COMM_EXEC_STOP 0x0 --#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 --#define FEC_TOP_COMM_EXEC_HOLD 0x2 -- --#define FEC_TOP_ANNEX__A 0x1C10010 --#define FEC_TOP_ANNEX__W 2 --#define FEC_TOP_ANNEX__M 0x3 --#define FEC_TOP_ANNEX__PRE 0x0 --#define FEC_TOP_ANNEX_A 0x0 --#define FEC_TOP_ANNEX_B 0x1 --#define FEC_TOP_ANNEX_C 0x2 --#define FEC_TOP_ANNEX_D 0x3 -- -- -- --#define FEC_DI_COMM_EXEC__A 0x1C20000 --#define FEC_DI_COMM_EXEC__W 2 --#define FEC_DI_COMM_EXEC__M 0x3 --#define FEC_DI_COMM_EXEC__PRE 0x0 --#define FEC_DI_COMM_EXEC_STOP 0x0 --#define FEC_DI_COMM_EXEC_ACTIVE 0x1 --#define FEC_DI_COMM_EXEC_HOLD 0x2 -- --#define FEC_DI_COMM_MB__A 0x1C20002 --#define FEC_DI_COMM_MB__W 2 --#define FEC_DI_COMM_MB__M 0x3 --#define FEC_DI_COMM_MB__PRE 0x0 --#define FEC_DI_COMM_MB_CTL__B 0 --#define FEC_DI_COMM_MB_CTL__W 1 --#define FEC_DI_COMM_MB_CTL__M 0x1 --#define FEC_DI_COMM_MB_CTL__PRE 0x0 --#define FEC_DI_COMM_MB_CTL_OFF 0x0 --#define FEC_DI_COMM_MB_CTL_ON 0x1 --#define FEC_DI_COMM_MB_OBS__B 1 --#define FEC_DI_COMM_MB_OBS__W 1 --#define FEC_DI_COMM_MB_OBS__M 0x2 --#define FEC_DI_COMM_MB_OBS__PRE 0x0 --#define FEC_DI_COMM_MB_OBS_OFF 0x0 --#define FEC_DI_COMM_MB_OBS_ON 0x2 -- --#define FEC_DI_COMM_INT_REQ__A 0x1C20003 --#define FEC_DI_COMM_INT_REQ__W 1 --#define FEC_DI_COMM_INT_REQ__M 0x1 --#define FEC_DI_COMM_INT_REQ__PRE 0x0 --#define FEC_DI_COMM_INT_STA__A 0x1C20005 --#define FEC_DI_COMM_INT_STA__W 2 --#define FEC_DI_COMM_INT_STA__M 0x3 --#define FEC_DI_COMM_INT_STA__PRE 0x0 -- --#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 --#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 --#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 --#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 -- --#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 --#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 --#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 --#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 -- --#define FEC_DI_COMM_INT_MSK__A 0x1C20006 --#define FEC_DI_COMM_INT_MSK__W 2 --#define FEC_DI_COMM_INT_MSK__M 0x3 --#define FEC_DI_COMM_INT_MSK__PRE 0x0 --#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 --#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 --#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 --#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 --#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 --#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 --#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 --#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 -- --#define FEC_DI_COMM_INT_STM__A 0x1C20007 --#define FEC_DI_COMM_INT_STM__W 2 --#define FEC_DI_COMM_INT_STM__M 0x3 --#define FEC_DI_COMM_INT_STM__PRE 0x0 --#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 --#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 --#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 --#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 --#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 --#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 --#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 --#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 -- -- --#define FEC_DI_STATUS__A 0x1C20010 --#define FEC_DI_STATUS__W 1 --#define FEC_DI_STATUS__M 0x1 --#define FEC_DI_STATUS__PRE 0x0 --#define FEC_DI_MODE__A 0x1C20011 --#define FEC_DI_MODE__W 3 --#define FEC_DI_MODE__M 0x7 --#define FEC_DI_MODE__PRE 0x0 -- --#define FEC_DI_MODE_NO_SYNC__B 0 --#define FEC_DI_MODE_NO_SYNC__W 1 --#define FEC_DI_MODE_NO_SYNC__M 0x1 --#define FEC_DI_MODE_NO_SYNC__PRE 0x0 -- --#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 --#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 --#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 --#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 -- --#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 --#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 --#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 --#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 -- -- --#define FEC_DI_CONTROL_WORD__A 0x1C20012 --#define FEC_DI_CONTROL_WORD__W 4 --#define FEC_DI_CONTROL_WORD__M 0xF --#define FEC_DI_CONTROL_WORD__PRE 0x0 -- --#define FEC_DI_RESTART__A 0x1C20013 --#define FEC_DI_RESTART__W 1 --#define FEC_DI_RESTART__M 0x1 --#define FEC_DI_RESTART__PRE 0x0 -- --#define FEC_DI_TIMEOUT_LO__A 0x1C20014 --#define FEC_DI_TIMEOUT_LO__W 16 --#define FEC_DI_TIMEOUT_LO__M 0xFFFF --#define FEC_DI_TIMEOUT_LO__PRE 0x0 -- --#define FEC_DI_TIMEOUT_HI__A 0x1C20015 --#define FEC_DI_TIMEOUT_HI__W 8 --#define FEC_DI_TIMEOUT_HI__M 0xFF --#define FEC_DI_TIMEOUT_HI__PRE 0xA -- --#define FEC_DI_INPUT_CTL__A 0x1C20016 --#define FEC_DI_INPUT_CTL__W 1 --#define FEC_DI_INPUT_CTL__M 0x1 --#define FEC_DI_INPUT_CTL__PRE 0x0 -- -- -- --#define FEC_RS_COMM_EXEC__A 0x1C30000 --#define FEC_RS_COMM_EXEC__W 2 --#define FEC_RS_COMM_EXEC__M 0x3 --#define FEC_RS_COMM_EXEC__PRE 0x0 --#define FEC_RS_COMM_EXEC_STOP 0x0 --#define FEC_RS_COMM_EXEC_ACTIVE 0x1 --#define FEC_RS_COMM_EXEC_HOLD 0x2 -- --#define FEC_RS_COMM_MB__A 0x1C30002 --#define FEC_RS_COMM_MB__W 2 --#define FEC_RS_COMM_MB__M 0x3 --#define FEC_RS_COMM_MB__PRE 0x0 --#define FEC_RS_COMM_MB_CTL__B 0 --#define FEC_RS_COMM_MB_CTL__W 1 --#define FEC_RS_COMM_MB_CTL__M 0x1 --#define FEC_RS_COMM_MB_CTL__PRE 0x0 --#define FEC_RS_COMM_MB_CTL_OFF 0x0 --#define FEC_RS_COMM_MB_CTL_ON 0x1 --#define FEC_RS_COMM_MB_OBS__B 1 --#define FEC_RS_COMM_MB_OBS__W 1 --#define FEC_RS_COMM_MB_OBS__M 0x2 --#define FEC_RS_COMM_MB_OBS__PRE 0x0 --#define FEC_RS_COMM_MB_OBS_OFF 0x0 --#define FEC_RS_COMM_MB_OBS_ON 0x2 -- --#define FEC_RS_COMM_INT_REQ__A 0x1C30003 --#define FEC_RS_COMM_INT_REQ__W 1 --#define FEC_RS_COMM_INT_REQ__M 0x1 --#define FEC_RS_COMM_INT_REQ__PRE 0x0 --#define FEC_RS_COMM_INT_STA__A 0x1C30005 --#define FEC_RS_COMM_INT_STA__W 2 --#define FEC_RS_COMM_INT_STA__M 0x3 --#define FEC_RS_COMM_INT_STA__PRE 0x0 -- --#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 --#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 --#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 --#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 -- --#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 --#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 --#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 --#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 -- --#define FEC_RS_COMM_INT_MSK__A 0x1C30006 --#define FEC_RS_COMM_INT_MSK__W 2 --#define FEC_RS_COMM_INT_MSK__M 0x3 --#define FEC_RS_COMM_INT_MSK__PRE 0x0 --#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 --#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 --#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 --#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 --#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 --#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 --#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 --#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 -- --#define FEC_RS_COMM_INT_STM__A 0x1C30007 --#define FEC_RS_COMM_INT_STM__W 2 --#define FEC_RS_COMM_INT_STM__M 0x3 --#define FEC_RS_COMM_INT_STM__PRE 0x0 --#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 --#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 --#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 --#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 --#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 --#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 --#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 --#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 -- --#define FEC_RS_STATUS__A 0x1C30010 --#define FEC_RS_STATUS__W 1 --#define FEC_RS_STATUS__M 0x1 --#define FEC_RS_STATUS__PRE 0x0 --#define FEC_RS_MODE__A 0x1C30011 --#define FEC_RS_MODE__W 1 --#define FEC_RS_MODE__M 0x1 --#define FEC_RS_MODE__PRE 0x0 -- --#define FEC_RS_MODE_BYPASS__B 0 --#define FEC_RS_MODE_BYPASS__W 1 --#define FEC_RS_MODE_BYPASS__M 0x1 --#define FEC_RS_MODE_BYPASS__PRE 0x0 -- --#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 --#define FEC_RS_MEASUREMENT_PERIOD__W 16 --#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF --#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993 -- --#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 --#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 --#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF --#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993 -- --#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 --#define FEC_RS_MEASUREMENT_PRESCALE__W 16 --#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF --#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 -- --#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 --#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 --#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF --#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 -- --#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 --#define FEC_RS_NR_BIT_ERRORS__W 16 --#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF --#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF -- --#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 --#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 --#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF --#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF -- --#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 --#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 --#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 --#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 -- --#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015 --#define FEC_RS_NR_SYMBOL_ERRORS__W 16 --#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF --#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF -- --#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 --#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 --#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF --#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF -- --#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 --#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 --#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 --#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 -- --#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016 --#define FEC_RS_NR_PACKET_ERRORS__W 16 --#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF --#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF -- --#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 --#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 --#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF --#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF -- --#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 --#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 --#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 --#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 -- --#define FEC_RS_NR_FAILURES__A 0x1C30017 --#define FEC_RS_NR_FAILURES__W 16 --#define FEC_RS_NR_FAILURES__M 0xFFFF --#define FEC_RS_NR_FAILURES__PRE 0x0 -- --#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 --#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 --#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF --#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 -- --#define FEC_RS_NR_FAILURES_EXP__B 12 --#define FEC_RS_NR_FAILURES_EXP__W 4 --#define FEC_RS_NR_FAILURES_EXP__M 0xF000 --#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 -- -- -- --#define FEC_OC_COMM_EXEC__A 0x1C40000 --#define FEC_OC_COMM_EXEC__W 2 --#define FEC_OC_COMM_EXEC__M 0x3 --#define FEC_OC_COMM_EXEC__PRE 0x0 --#define FEC_OC_COMM_EXEC_STOP 0x0 --#define FEC_OC_COMM_EXEC_ACTIVE 0x1 --#define FEC_OC_COMM_EXEC_HOLD 0x2 -- --#define FEC_OC_COMM_MB__A 0x1C40002 --#define FEC_OC_COMM_MB__W 2 --#define FEC_OC_COMM_MB__M 0x3 --#define FEC_OC_COMM_MB__PRE 0x0 --#define FEC_OC_COMM_MB_CTL__B 0 --#define FEC_OC_COMM_MB_CTL__W 1 --#define FEC_OC_COMM_MB_CTL__M 0x1 --#define FEC_OC_COMM_MB_CTL__PRE 0x0 --#define FEC_OC_COMM_MB_CTL_OFF 0x0 --#define FEC_OC_COMM_MB_CTL_ON 0x1 --#define FEC_OC_COMM_MB_OBS__B 1 --#define FEC_OC_COMM_MB_OBS__W 1 --#define FEC_OC_COMM_MB_OBS__M 0x2 --#define FEC_OC_COMM_MB_OBS__PRE 0x0 --#define FEC_OC_COMM_MB_OBS_OFF 0x0 --#define FEC_OC_COMM_MB_OBS_ON 0x2 -- --#define FEC_OC_COMM_INT_REQ__A 0x1C40003 --#define FEC_OC_COMM_INT_REQ__W 1 --#define FEC_OC_COMM_INT_REQ__M 0x1 --#define FEC_OC_COMM_INT_REQ__PRE 0x0 --#define FEC_OC_COMM_INT_STA__A 0x1C40005 --#define FEC_OC_COMM_INT_STA__W 8 --#define FEC_OC_COMM_INT_STA__M 0xFF --#define FEC_OC_COMM_INT_STA__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 --#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 --#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 --#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 --#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 --#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 --#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 --#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 --#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 --#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 --#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 --#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 --#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 --#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 --#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 --#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 --#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 --#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 --#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 --#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 --#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 --#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 --#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 --#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 --#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 -- --#define FEC_OC_COMM_INT_MSK__A 0x1C40006 --#define FEC_OC_COMM_INT_MSK__W 8 --#define FEC_OC_COMM_INT_MSK__M 0xFF --#define FEC_OC_COMM_INT_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 --#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 --#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 --#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 --#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 --#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 --#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 --#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 --#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 --#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 --#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 --#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 --#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 --#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 --#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 --#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 --#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 --#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 -- --#define FEC_OC_COMM_INT_STM__A 0x1C40007 --#define FEC_OC_COMM_INT_STM__W 8 --#define FEC_OC_COMM_INT_STM__M 0xFF --#define FEC_OC_COMM_INT_STM__PRE 0x0 --#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 --#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 --#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 --#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 --#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 --#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 --#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 --#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 --#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 --#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 --#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 --#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 --#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 --#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 --#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 --#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 --#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 --#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 --#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 --#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 --#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 --#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 --#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 --#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 --#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 --#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 -- --#define FEC_OC_STATUS__A 0x1C40010 --#define FEC_OC_STATUS__W 5 --#define FEC_OC_STATUS__M 0x1F --#define FEC_OC_STATUS__PRE 0x0 -- --#define FEC_OC_STATUS_DPR_STATUS__B 0 --#define FEC_OC_STATUS_DPR_STATUS__W 1 --#define FEC_OC_STATUS_DPR_STATUS__M 0x1 --#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 -- --#define FEC_OC_STATUS_SNC_STATUS__B 1 --#define FEC_OC_STATUS_SNC_STATUS__W 2 --#define FEC_OC_STATUS_SNC_STATUS__M 0x6 --#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 --#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0 --#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2 --#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4 -- --#define FEC_OC_STATUS_FIFO_FULL__B 3 --#define FEC_OC_STATUS_FIFO_FULL__W 1 --#define FEC_OC_STATUS_FIFO_FULL__M 0x8 --#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 -- --#define FEC_OC_STATUS_FIFO_EMPTY__B 4 --#define FEC_OC_STATUS_FIFO_EMPTY__W 1 --#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 --#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 -- --#define FEC_OC_MODE__A 0x1C40011 --#define FEC_OC_MODE__W 4 --#define FEC_OC_MODE__M 0xF --#define FEC_OC_MODE__PRE 0x0 -- --#define FEC_OC_MODE_PARITY__B 0 --#define FEC_OC_MODE_PARITY__W 1 --#define FEC_OC_MODE_PARITY__M 0x1 --#define FEC_OC_MODE_PARITY__PRE 0x0 -- --#define FEC_OC_MODE_TRANSPARENT__B 1 --#define FEC_OC_MODE_TRANSPARENT__W 1 --#define FEC_OC_MODE_TRANSPARENT__M 0x2 --#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 -- --#define FEC_OC_MODE_CLEAR__B 2 --#define FEC_OC_MODE_CLEAR__W 1 --#define FEC_OC_MODE_CLEAR__M 0x4 --#define FEC_OC_MODE_CLEAR__PRE 0x0 -- --#define FEC_OC_MODE_RETAIN_FRAMING__B 3 --#define FEC_OC_MODE_RETAIN_FRAMING__W 1 --#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 --#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 -- --#define FEC_OC_DPR_MODE__A 0x1C40012 --#define FEC_OC_DPR_MODE__W 2 --#define FEC_OC_DPR_MODE__M 0x3 --#define FEC_OC_DPR_MODE__PRE 0x0 -- --#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 --#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 --#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 --#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 -- --#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 --#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 --#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 --#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 -- -- --#define FEC_OC_DPR_UNLOCK__A 0x1C40013 --#define FEC_OC_DPR_UNLOCK__W 1 --#define FEC_OC_DPR_UNLOCK__M 0x1 --#define FEC_OC_DPR_UNLOCK__PRE 0x0 --#define FEC_OC_DTO_MODE__A 0x1C40014 --#define FEC_OC_DTO_MODE__W 3 --#define FEC_OC_DTO_MODE__M 0x7 --#define FEC_OC_DTO_MODE__PRE 0x0 -- --#define FEC_OC_DTO_MODE_DYNAMIC__B 0 --#define FEC_OC_DTO_MODE_DYNAMIC__W 1 --#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 --#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 -- --#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 --#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 --#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 --#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 -- --#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 --#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 --#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 --#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 -- -- --#define FEC_OC_DTO_PERIOD__A 0x1C40015 --#define FEC_OC_DTO_PERIOD__W 8 --#define FEC_OC_DTO_PERIOD__M 0xFF --#define FEC_OC_DTO_PERIOD__PRE 0x0 --#define FEC_OC_DTO_RATE_LO__A 0x1C40016 --#define FEC_OC_DTO_RATE_LO__W 16 --#define FEC_OC_DTO_RATE_LO__M 0xFFFF --#define FEC_OC_DTO_RATE_LO__PRE 0x0 -- --#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 --#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 --#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF --#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 -- --#define FEC_OC_DTO_RATE_HI__A 0x1C40017 --#define FEC_OC_DTO_RATE_HI__W 10 --#define FEC_OC_DTO_RATE_HI__M 0x3FF --#define FEC_OC_DTO_RATE_HI__PRE 0xC0 -- --#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 --#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 --#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF --#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 -- --#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 --#define FEC_OC_DTO_BURST_LEN__W 8 --#define FEC_OC_DTO_BURST_LEN__M 0xFF --#define FEC_OC_DTO_BURST_LEN__PRE 0xBC -- --#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 --#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 --#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF --#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC -- --#define FEC_OC_FCT_MODE__A 0x1C4001A --#define FEC_OC_FCT_MODE__W 2 --#define FEC_OC_FCT_MODE__M 0x3 --#define FEC_OC_FCT_MODE__PRE 0x0 -- --#define FEC_OC_FCT_MODE_RAT_ENA__B 0 --#define FEC_OC_FCT_MODE_RAT_ENA__W 1 --#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 --#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 -- --#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 --#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 --#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 --#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 -- --#define FEC_OC_FCT_USAGE__A 0x1C4001B --#define FEC_OC_FCT_USAGE__W 3 --#define FEC_OC_FCT_USAGE__M 0x7 --#define FEC_OC_FCT_USAGE__PRE 0x7 -- --#define FEC_OC_FCT_USAGE_USAGE__B 0 --#define FEC_OC_FCT_USAGE_USAGE__W 3 --#define FEC_OC_FCT_USAGE_USAGE__M 0x7 --#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7 -- --#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C --#define FEC_OC_FCT_OCCUPATION__W 12 --#define FEC_OC_FCT_OCCUPATION__M 0xFFF --#define FEC_OC_FCT_OCCUPATION__PRE 0x0 -- --#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 --#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 --#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF --#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 -- --#define FEC_OC_TMD_MODE__A 0x1C4001E --#define FEC_OC_TMD_MODE__W 3 --#define FEC_OC_TMD_MODE__M 0x7 --#define FEC_OC_TMD_MODE__PRE 0x4 -- --#define FEC_OC_TMD_MODE_MODE__B 0 --#define FEC_OC_TMD_MODE_MODE__W 3 --#define FEC_OC_TMD_MODE_MODE__M 0x7 --#define FEC_OC_TMD_MODE_MODE__PRE 0x4 -- --#define FEC_OC_TMD_COUNT__A 0x1C4001F --#define FEC_OC_TMD_COUNT__W 10 --#define FEC_OC_TMD_COUNT__M 0x3FF --#define FEC_OC_TMD_COUNT__PRE 0x1F4 -- --#define FEC_OC_TMD_COUNT_COUNT__B 0 --#define FEC_OC_TMD_COUNT_COUNT__W 10 --#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF --#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 -- --#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 --#define FEC_OC_TMD_HI_MARGIN__W 11 --#define FEC_OC_TMD_HI_MARGIN__M 0x7FF --#define FEC_OC_TMD_HI_MARGIN__PRE 0x500 -- --#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 --#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 --#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF --#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500 -- --#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 --#define FEC_OC_TMD_LO_MARGIN__W 11 --#define FEC_OC_TMD_LO_MARGIN__M 0x7FF --#define FEC_OC_TMD_LO_MARGIN__PRE 0x300 -- --#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 --#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 --#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF --#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300 -- --#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022 --#define FEC_OC_TMD_CTL_UPD_RATE__W 4 --#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF --#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 -- --#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 --#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 --#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF --#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 -- --#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 --#define FEC_OC_TMD_INT_UPD_RATE__W 4 --#define FEC_OC_TMD_INT_UPD_RATE__M 0xF --#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 -- --#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 --#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 --#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF --#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 -- --#define FEC_OC_AVR_PARM_A__A 0x1C40026 --#define FEC_OC_AVR_PARM_A__W 4 --#define FEC_OC_AVR_PARM_A__M 0xF --#define FEC_OC_AVR_PARM_A__PRE 0x6 -- --#define FEC_OC_AVR_PARM_A_PARM__B 0 --#define FEC_OC_AVR_PARM_A_PARM__W 4 --#define FEC_OC_AVR_PARM_A_PARM__M 0xF --#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 -- --#define FEC_OC_AVR_PARM_B__A 0x1C40027 --#define FEC_OC_AVR_PARM_B__W 4 --#define FEC_OC_AVR_PARM_B__M 0xF --#define FEC_OC_AVR_PARM_B__PRE 0x4 -- --#define FEC_OC_AVR_PARM_B_PARM__B 0 --#define FEC_OC_AVR_PARM_B_PARM__W 4 --#define FEC_OC_AVR_PARM_B_PARM__M 0xF --#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 -- --#define FEC_OC_AVR_AVG_LO__A 0x1C40028 --#define FEC_OC_AVR_AVG_LO__W 16 --#define FEC_OC_AVR_AVG_LO__M 0xFFFF --#define FEC_OC_AVR_AVG_LO__PRE 0x0 -- --#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 --#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 --#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF --#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 -- --#define FEC_OC_AVR_AVG_HI__A 0x1C40029 --#define FEC_OC_AVR_AVG_HI__W 6 --#define FEC_OC_AVR_AVG_HI__M 0x3F --#define FEC_OC_AVR_AVG_HI__PRE 0x0 -- --#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 --#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 --#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F --#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 -- --#define FEC_OC_RCN_MODE__A 0x1C4002C --#define FEC_OC_RCN_MODE__W 5 --#define FEC_OC_RCN_MODE__M 0x1F --#define FEC_OC_RCN_MODE__PRE 0x1F -- --#define FEC_OC_RCN_MODE_MODE__B 0 --#define FEC_OC_RCN_MODE_MODE__W 5 --#define FEC_OC_RCN_MODE_MODE__M 0x1F --#define FEC_OC_RCN_MODE_MODE__PRE 0x1F -- --#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D --#define FEC_OC_RCN_OCC_SETTLE__W 11 --#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF --#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400 -- --#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 --#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 --#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF --#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400 -- --#define FEC_OC_RCN_GAIN__A 0x1C4002E --#define FEC_OC_RCN_GAIN__W 4 --#define FEC_OC_RCN_GAIN__M 0xF --#define FEC_OC_RCN_GAIN__PRE 0xC -- --#define FEC_OC_RCN_GAIN_GAIN__B 0 --#define FEC_OC_RCN_GAIN_GAIN__W 4 --#define FEC_OC_RCN_GAIN_GAIN__M 0xF --#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC -- --#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 --#define FEC_OC_RCN_CTL_RATE_LO__W 16 --#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF --#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 -- --#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 --#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 --#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF --#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 -- --#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031 --#define FEC_OC_RCN_CTL_RATE_HI__W 8 --#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF --#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 -- --#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 --#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 --#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF --#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 -- --#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 --#define FEC_OC_RCN_CTL_STEP_LO__W 16 --#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF --#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 -- --#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 --#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 --#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF --#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 -- --#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 --#define FEC_OC_RCN_CTL_STEP_HI__W 8 --#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF --#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 -- --#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 --#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 --#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF --#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 -- --#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034 --#define FEC_OC_RCN_DTO_OFS_LO__W 16 --#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF --#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 -- --#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 --#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 --#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF --#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 -- --#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035 --#define FEC_OC_RCN_DTO_OFS_HI__W 8 --#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF --#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 -- --#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 --#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 --#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF --#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 -- --#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036 --#define FEC_OC_RCN_DTO_RATE_LO__W 16 --#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF --#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 -- --#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 --#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 --#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF --#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 -- --#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037 --#define FEC_OC_RCN_DTO_RATE_HI__W 8 --#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF --#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 -- --#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 --#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 --#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF --#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 -- --#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038 --#define FEC_OC_RCN_RATE_CLIP_LO__W 16 --#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF --#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 -- --#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 --#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 --#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF --#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 -- --#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039 --#define FEC_OC_RCN_RATE_CLIP_HI__W 8 --#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF --#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 -- --#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 --#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 --#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF --#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 -- --#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A --#define FEC_OC_RCN_DYN_RATE_LO__W 16 --#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF --#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 -- --#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 --#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 --#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF --#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 -- --#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B --#define FEC_OC_RCN_DYN_RATE_HI__W 8 --#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF --#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 -- --#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 --#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 --#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF --#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 -- --#define FEC_OC_SNC_MODE__A 0x1C40040 --#define FEC_OC_SNC_MODE__W 5 --#define FEC_OC_SNC_MODE__M 0x1F --#define FEC_OC_SNC_MODE__PRE 0x0 -- --#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 --#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 --#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 --#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 -- --#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 --#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 --#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 --#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 -- --#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 --#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 --#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 --#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 -- --#define FEC_OC_SNC_MODE_SHUTDOWN__B 4 --#define FEC_OC_SNC_MODE_SHUTDOWN__W 1 --#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 --#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0 -- --#define FEC_OC_SNC_LWM__A 0x1C40041 --#define FEC_OC_SNC_LWM__W 4 --#define FEC_OC_SNC_LWM__M 0xF --#define FEC_OC_SNC_LWM__PRE 0x3 -- --#define FEC_OC_SNC_LWM_MARK__B 0 --#define FEC_OC_SNC_LWM_MARK__W 4 --#define FEC_OC_SNC_LWM_MARK__M 0xF --#define FEC_OC_SNC_LWM_MARK__PRE 0x3 -- --#define FEC_OC_SNC_HWM__A 0x1C40042 --#define FEC_OC_SNC_HWM__W 4 --#define FEC_OC_SNC_HWM__M 0xF --#define FEC_OC_SNC_HWM__PRE 0x5 -- --#define FEC_OC_SNC_HWM_MARK__B 0 --#define FEC_OC_SNC_HWM_MARK__W 4 --#define FEC_OC_SNC_HWM_MARK__M 0xF --#define FEC_OC_SNC_HWM_MARK__PRE 0x5 -- --#define FEC_OC_SNC_UNLOCK__A 0x1C40043 --#define FEC_OC_SNC_UNLOCK__W 1 --#define FEC_OC_SNC_UNLOCK__M 0x1 --#define FEC_OC_SNC_UNLOCK__PRE 0x0 -- --#define FEC_OC_SNC_UNLOCK_RESTART__B 0 --#define FEC_OC_SNC_UNLOCK_RESTART__W 1 --#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 --#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 -- --#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044 --#define FEC_OC_SNC_LOCK_COUNT__W 12 --#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF --#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 -- --#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 --#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 --#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF --#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 -- --#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045 --#define FEC_OC_SNC_FAIL_COUNT__W 12 --#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF --#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 -- --#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 --#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 --#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF --#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 -- --#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 --#define FEC_OC_SNC_FAIL_PERIOD__W 16 --#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF --#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 -- --#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 --#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 --#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF --#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 -- --#define FEC_OC_EMS_MODE__A 0x1C40047 --#define FEC_OC_EMS_MODE__W 2 --#define FEC_OC_EMS_MODE__M 0x3 --#define FEC_OC_EMS_MODE__PRE 0x0 -- --#define FEC_OC_EMS_MODE_MODE__B 0 --#define FEC_OC_EMS_MODE_MODE__W 2 --#define FEC_OC_EMS_MODE_MODE__M 0x3 --#define FEC_OC_EMS_MODE_MODE__PRE 0x0 -- --#define FEC_OC_IPR_MODE__A 0x1C40048 --#define FEC_OC_IPR_MODE__W 12 --#define FEC_OC_IPR_MODE__M 0xFFF --#define FEC_OC_IPR_MODE__PRE 0x0 -- --#define FEC_OC_IPR_MODE_SERIAL__B 0 --#define FEC_OC_IPR_MODE_SERIAL__W 1 --#define FEC_OC_IPR_MODE_SERIAL__M 0x1 --#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 -- --#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 --#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 --#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 --#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 --#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 --#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 --#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 --#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 --#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 --#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 --#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 --#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 --#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 --#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 --#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 --#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 --#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 --#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 --#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 --#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 --#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 --#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 --#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 --#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 --#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 --#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 --#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 --#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 --#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 --#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 --#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 -- --#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 --#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 --#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 --#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 -- --#define FEC_OC_IPR_INVERT__A 0x1C40049 --#define FEC_OC_IPR_INVERT__W 12 --#define FEC_OC_IPR_INVERT__M 0xFFF --#define FEC_OC_IPR_INVERT__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD0__B 0 --#define FEC_OC_IPR_INVERT_MD0__W 1 --#define FEC_OC_IPR_INVERT_MD0__M 0x1 --#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD1__B 1 --#define FEC_OC_IPR_INVERT_MD1__W 1 --#define FEC_OC_IPR_INVERT_MD1__M 0x2 --#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD2__B 2 --#define FEC_OC_IPR_INVERT_MD2__W 1 --#define FEC_OC_IPR_INVERT_MD2__M 0x4 --#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD3__B 3 --#define FEC_OC_IPR_INVERT_MD3__W 1 --#define FEC_OC_IPR_INVERT_MD3__M 0x8 --#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD4__B 4 --#define FEC_OC_IPR_INVERT_MD4__W 1 --#define FEC_OC_IPR_INVERT_MD4__M 0x10 --#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD5__B 5 --#define FEC_OC_IPR_INVERT_MD5__W 1 --#define FEC_OC_IPR_INVERT_MD5__M 0x20 --#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD6__B 6 --#define FEC_OC_IPR_INVERT_MD6__W 1 --#define FEC_OC_IPR_INVERT_MD6__M 0x40 --#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MD7__B 7 --#define FEC_OC_IPR_INVERT_MD7__W 1 --#define FEC_OC_IPR_INVERT_MD7__M 0x80 --#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MERR__B 8 --#define FEC_OC_IPR_INVERT_MERR__W 1 --#define FEC_OC_IPR_INVERT_MERR__M 0x100 --#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MSTRT__B 9 --#define FEC_OC_IPR_INVERT_MSTRT__W 1 --#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 --#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MVAL__B 10 --#define FEC_OC_IPR_INVERT_MVAL__W 1 --#define FEC_OC_IPR_INVERT_MVAL__M 0x400 --#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 -- --#define FEC_OC_IPR_INVERT_MCLK__B 11 --#define FEC_OC_IPR_INVERT_MCLK__W 1 --#define FEC_OC_IPR_INVERT_MCLK__M 0x800 --#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 -- --#define FEC_OC_OCR_MODE__A 0x1C40050 --#define FEC_OC_OCR_MODE__W 4 --#define FEC_OC_OCR_MODE__M 0xF --#define FEC_OC_OCR_MODE__PRE 0x0 -- --#define FEC_OC_OCR_MODE_MB_SELECT__B 0 --#define FEC_OC_OCR_MODE_MB_SELECT__W 1 --#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 --#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 -- --#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 --#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 --#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 --#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 -- --#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 --#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 --#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 --#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 -- --#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 --#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 --#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 --#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 -- --#define FEC_OC_OCR_RATE__A 0x1C40051 --#define FEC_OC_OCR_RATE__W 4 --#define FEC_OC_OCR_RATE__M 0xF --#define FEC_OC_OCR_RATE__PRE 0x0 -- --#define FEC_OC_OCR_RATE_RATE__B 0 --#define FEC_OC_OCR_RATE_RATE__W 4 --#define FEC_OC_OCR_RATE_RATE__M 0xF --#define FEC_OC_OCR_RATE_RATE__PRE 0x0 -- --#define FEC_OC_OCR_INVERT__A 0x1C40052 --#define FEC_OC_OCR_INVERT__W 12 --#define FEC_OC_OCR_INVERT__M 0xFFF --#define FEC_OC_OCR_INVERT__PRE 0x800 -- --#define FEC_OC_OCR_INVERT_INVERT__B 0 --#define FEC_OC_OCR_INVERT_INVERT__W 12 --#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF --#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 -- --#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053 --#define FEC_OC_OCR_GRAB_COUNT__W 16 --#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF --#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 --#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 --#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF --#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054 --#define FEC_OC_OCR_GRAB_SYNC__W 8 --#define FEC_OC_OCR_GRAB_SYNC__M 0xFF --#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 --#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 --#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 --#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 --#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 --#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 --#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 --#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 --#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 --#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055 --#define FEC_OC_OCR_GRAB_RD0__W 10 --#define FEC_OC_OCR_GRAB_RD0__M 0x3FF --#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 --#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 --#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF --#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056 --#define FEC_OC_OCR_GRAB_RD1__W 10 --#define FEC_OC_OCR_GRAB_RD1__M 0x3FF --#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 --#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 --#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF --#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057 --#define FEC_OC_OCR_GRAB_RD2__W 10 --#define FEC_OC_OCR_GRAB_RD2__M 0x3FF --#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 --#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 --#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF --#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058 --#define FEC_OC_OCR_GRAB_RD3__W 10 --#define FEC_OC_OCR_GRAB_RD3__M 0x3FF --#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 --#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 --#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF --#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059 --#define FEC_OC_OCR_GRAB_RD4__W 10 --#define FEC_OC_OCR_GRAB_RD4__M 0x3FF --#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 --#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 --#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF --#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A --#define FEC_OC_OCR_GRAB_RD5__W 10 --#define FEC_OC_OCR_GRAB_RD5__M 0x3FF --#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 -- --#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 --#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 --#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF --#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 -- -- -- --#define FEC_DI_RAM__A 0x1C50000 -- -- -- --#define FEC_RS_RAM__A 0x1C60000 -- -- -- --#define FEC_OC_RAM__A 0x1C70000 -- -- -- -- -- --#define IQM_COMM_EXEC__A 0x1800000 --#define IQM_COMM_EXEC__W 2 --#define IQM_COMM_EXEC__M 0x3 --#define IQM_COMM_EXEC__PRE 0x0 --#define IQM_COMM_EXEC_B__B 0 --#define IQM_COMM_EXEC_B__W 2 --#define IQM_COMM_EXEC_B__M 0x3 --#define IQM_COMM_EXEC_B__PRE 0x0 --#define IQM_COMM_EXEC_B_STOP 0x0 --#define IQM_COMM_EXEC_B_ACTIVE 0x1 --#define IQM_COMM_EXEC_B_HOLD 0x2 -- --#define IQM_COMM_MB__A 0x1800002 --#define IQM_COMM_MB__W 16 --#define IQM_COMM_MB__M 0xFFFF --#define IQM_COMM_MB__PRE 0x0 --#define IQM_COMM_MB_B__B 0 --#define IQM_COMM_MB_B__W 16 --#define IQM_COMM_MB_B__M 0xFFFF --#define IQM_COMM_MB_B__PRE 0x0 -- --#define IQM_COMM_INT_REQ__A 0x1800003 --#define IQM_COMM_INT_REQ__W 3 --#define IQM_COMM_INT_REQ__M 0x7 --#define IQM_COMM_INT_REQ__PRE 0x0 -- --#define IQM_COMM_INT_REQ_AF_REQ__B 0 --#define IQM_COMM_INT_REQ_AF_REQ__W 1 --#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 --#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 -- --#define IQM_COMM_INT_REQ_CF_REQ__B 1 --#define IQM_COMM_INT_REQ_CF_REQ__W 1 --#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 --#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 -- --#define IQM_COMM_INT_REQ_CW_REQ__B 2 --#define IQM_COMM_INT_REQ_CW_REQ__W 1 --#define IQM_COMM_INT_REQ_CW_REQ__M 0x4 --#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0 -- --#define IQM_COMM_INT_STA__A 0x1800005 --#define IQM_COMM_INT_STA__W 16 --#define IQM_COMM_INT_STA__M 0xFFFF --#define IQM_COMM_INT_STA__PRE 0x0 --#define IQM_COMM_INT_STA_B__B 0 --#define IQM_COMM_INT_STA_B__W 16 --#define IQM_COMM_INT_STA_B__M 0xFFFF --#define IQM_COMM_INT_STA_B__PRE 0x0 -- --#define IQM_COMM_INT_MSK__A 0x1800006 --#define IQM_COMM_INT_MSK__W 16 --#define IQM_COMM_INT_MSK__M 0xFFFF --#define IQM_COMM_INT_MSK__PRE 0x0 --#define IQM_COMM_INT_MSK_B__B 0 --#define IQM_COMM_INT_MSK_B__W 16 --#define IQM_COMM_INT_MSK_B__M 0xFFFF --#define IQM_COMM_INT_MSK_B__PRE 0x0 -- --#define IQM_COMM_INT_STM__A 0x1800007 --#define IQM_COMM_INT_STM__W 16 --#define IQM_COMM_INT_STM__M 0xFFFF --#define IQM_COMM_INT_STM__PRE 0x0 --#define IQM_COMM_INT_STM_B__B 0 --#define IQM_COMM_INT_STM_B__W 16 --#define IQM_COMM_INT_STM_B__M 0xFFFF --#define IQM_COMM_INT_STM_B__PRE 0x0 -- -- -- --#define IQM_FS_COMM_EXEC__A 0x1820000 --#define IQM_FS_COMM_EXEC__W 2 --#define IQM_FS_COMM_EXEC__M 0x3 --#define IQM_FS_COMM_EXEC__PRE 0x0 --#define IQM_FS_COMM_EXEC_STOP 0x0 --#define IQM_FS_COMM_EXEC_ACTIVE 0x1 --#define IQM_FS_COMM_EXEC_HOLD 0x2 -- --#define IQM_FS_COMM_MB__A 0x1820002 --#define IQM_FS_COMM_MB__W 4 --#define IQM_FS_COMM_MB__M 0xF --#define IQM_FS_COMM_MB__PRE 0x0 --#define IQM_FS_COMM_MB_CTL__B 0 --#define IQM_FS_COMM_MB_CTL__W 1 --#define IQM_FS_COMM_MB_CTL__M 0x1 --#define IQM_FS_COMM_MB_CTL__PRE 0x0 --#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 --#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 --#define IQM_FS_COMM_MB_OBS__B 1 --#define IQM_FS_COMM_MB_OBS__W 1 --#define IQM_FS_COMM_MB_OBS__M 0x2 --#define IQM_FS_COMM_MB_OBS__PRE 0x0 --#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 --#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 --#define IQM_FS_COMM_MB_CTL_MUX__B 2 --#define IQM_FS_COMM_MB_CTL_MUX__W 1 --#define IQM_FS_COMM_MB_CTL_MUX__M 0x4 --#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0 --#define IQM_FS_COMM_MB_OBS_MUX__B 3 --#define IQM_FS_COMM_MB_OBS_MUX__W 1 --#define IQM_FS_COMM_MB_OBS_MUX__M 0x8 --#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0 -- --#define IQM_FS_RATE_OFS_LO__A 0x1820010 --#define IQM_FS_RATE_OFS_LO__W 16 --#define IQM_FS_RATE_OFS_LO__M 0xFFFF --#define IQM_FS_RATE_OFS_LO__PRE 0x0 --#define IQM_FS_RATE_OFS_LO_B__B 0 --#define IQM_FS_RATE_OFS_LO_B__W 16 --#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF --#define IQM_FS_RATE_OFS_LO_B__PRE 0x0 -- --#define IQM_FS_RATE_OFS_HI__A 0x1820011 --#define IQM_FS_RATE_OFS_HI__W 12 --#define IQM_FS_RATE_OFS_HI__M 0xFFF --#define IQM_FS_RATE_OFS_HI__PRE 0x0 --#define IQM_FS_RATE_OFS_HI_B__B 0 --#define IQM_FS_RATE_OFS_HI_B__W 12 --#define IQM_FS_RATE_OFS_HI_B__M 0xFFF --#define IQM_FS_RATE_OFS_HI_B__PRE 0x0 -- --#define IQM_FS_RATE_LO__A 0x1820012 --#define IQM_FS_RATE_LO__W 16 --#define IQM_FS_RATE_LO__M 0xFFFF --#define IQM_FS_RATE_LO__PRE 0x0 --#define IQM_FS_RATE_LO_B__B 0 --#define IQM_FS_RATE_LO_B__W 16 --#define IQM_FS_RATE_LO_B__M 0xFFFF --#define IQM_FS_RATE_LO_B__PRE 0x0 -- --#define IQM_FS_RATE_HI__A 0x1820013 --#define IQM_FS_RATE_HI__W 12 --#define IQM_FS_RATE_HI__M 0xFFF --#define IQM_FS_RATE_HI__PRE 0x0 --#define IQM_FS_RATE_HI_B__B 0 --#define IQM_FS_RATE_HI_B__W 12 --#define IQM_FS_RATE_HI_B__M 0xFFF --#define IQM_FS_RATE_HI_B__PRE 0x0 -- --#define IQM_FS_ADJ_SEL__A 0x1820014 --#define IQM_FS_ADJ_SEL__W 2 --#define IQM_FS_ADJ_SEL__M 0x3 --#define IQM_FS_ADJ_SEL__PRE 0x0 -- --#define IQM_FS_ADJ_SEL_B__B 0 --#define IQM_FS_ADJ_SEL_B__W 2 --#define IQM_FS_ADJ_SEL_B__M 0x3 --#define IQM_FS_ADJ_SEL_B__PRE 0x0 --#define IQM_FS_ADJ_SEL_B_OFF 0x0 --#define IQM_FS_ADJ_SEL_B_QAM 0x1 --#define IQM_FS_ADJ_SEL_B_VSB 0x2 -- -- -- --#define IQM_FD_COMM_EXEC__A 0x1830000 --#define IQM_FD_COMM_EXEC__W 2 --#define IQM_FD_COMM_EXEC__M 0x3 --#define IQM_FD_COMM_EXEC__PRE 0x0 --#define IQM_FD_COMM_EXEC_STOP 0x0 --#define IQM_FD_COMM_EXEC_ACTIVE 0x1 --#define IQM_FD_COMM_EXEC_HOLD 0x2 -- --#define IQM_FD_COMM_MB__A 0x1830002 --#define IQM_FD_COMM_MB__W 2 --#define IQM_FD_COMM_MB__M 0x3 --#define IQM_FD_COMM_MB__PRE 0x0 --#define IQM_FD_COMM_MB_CTL__B 0 --#define IQM_FD_COMM_MB_CTL__W 1 --#define IQM_FD_COMM_MB_CTL__M 0x1 --#define IQM_FD_COMM_MB_CTL__PRE 0x0 --#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 --#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 --#define IQM_FD_COMM_MB_OBS__B 1 --#define IQM_FD_COMM_MB_OBS__W 1 --#define IQM_FD_COMM_MB_OBS__M 0x2 --#define IQM_FD_COMM_MB_OBS__PRE 0x0 --#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 --#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 -- --#define IQM_FD_RATESEL__A 0x1830010 --#define IQM_FD_RATESEL__W 2 --#define IQM_FD_RATESEL__M 0x3 --#define IQM_FD_RATESEL__PRE 0x0 --#define IQM_FD_RATESEL_B__B 0 --#define IQM_FD_RATESEL_B__W 2 --#define IQM_FD_RATESEL_B__M 0x3 --#define IQM_FD_RATESEL_B__PRE 0x0 --#define IQM_FD_RATESEL_B_DS0 0x0 --#define IQM_FD_RATESEL_B_DS1 0x1 --#define IQM_FD_RATESEL_B_DS2 0x2 --#define IQM_FD_RATESEL_B_DS3 0x3 -- -- -- --#define IQM_RC_COMM_EXEC__A 0x1840000 --#define IQM_RC_COMM_EXEC__W 2 --#define IQM_RC_COMM_EXEC__M 0x3 --#define IQM_RC_COMM_EXEC__PRE 0x0 --#define IQM_RC_COMM_EXEC_STOP 0x0 --#define IQM_RC_COMM_EXEC_ACTIVE 0x1 --#define IQM_RC_COMM_EXEC_HOLD 0x2 -- --#define IQM_RC_COMM_MB__A 0x1840002 --#define IQM_RC_COMM_MB__W 2 --#define IQM_RC_COMM_MB__M 0x3 --#define IQM_RC_COMM_MB__PRE 0x0 --#define IQM_RC_COMM_MB_CTL__B 0 --#define IQM_RC_COMM_MB_CTL__W 1 --#define IQM_RC_COMM_MB_CTL__M 0x1 --#define IQM_RC_COMM_MB_CTL__PRE 0x0 --#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 --#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 --#define IQM_RC_COMM_MB_OBS__B 1 --#define IQM_RC_COMM_MB_OBS__W 1 --#define IQM_RC_COMM_MB_OBS__M 0x2 --#define IQM_RC_COMM_MB_OBS__PRE 0x0 --#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 --#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 -- --#define IQM_RC_RATE_OFS_LO__A 0x1840010 --#define IQM_RC_RATE_OFS_LO__W 16 --#define IQM_RC_RATE_OFS_LO__M 0xFFFF --#define IQM_RC_RATE_OFS_LO__PRE 0x0 --#define IQM_RC_RATE_OFS_LO_B__B 0 --#define IQM_RC_RATE_OFS_LO_B__W 16 --#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF --#define IQM_RC_RATE_OFS_LO_B__PRE 0x0 -- --#define IQM_RC_RATE_OFS_HI__A 0x1840011 --#define IQM_RC_RATE_OFS_HI__W 8 --#define IQM_RC_RATE_OFS_HI__M 0xFF --#define IQM_RC_RATE_OFS_HI__PRE 0x0 --#define IQM_RC_RATE_OFS_HI_B__B 0 --#define IQM_RC_RATE_OFS_HI_B__W 8 --#define IQM_RC_RATE_OFS_HI_B__M 0xFF --#define IQM_RC_RATE_OFS_HI_B__PRE 0x0 -- --#define IQM_RC_RATE_LO__A 0x1840012 --#define IQM_RC_RATE_LO__W 16 --#define IQM_RC_RATE_LO__M 0xFFFF --#define IQM_RC_RATE_LO__PRE 0x0 --#define IQM_RC_RATE_LO_B__B 0 --#define IQM_RC_RATE_LO_B__W 16 --#define IQM_RC_RATE_LO_B__M 0xFFFF --#define IQM_RC_RATE_LO_B__PRE 0x0 -- --#define IQM_RC_RATE_HI__A 0x1840013 --#define IQM_RC_RATE_HI__W 8 --#define IQM_RC_RATE_HI__M 0xFF --#define IQM_RC_RATE_HI__PRE 0x0 --#define IQM_RC_RATE_HI_B__B 0 --#define IQM_RC_RATE_HI_B__W 8 --#define IQM_RC_RATE_HI_B__M 0xFF --#define IQM_RC_RATE_HI_B__PRE 0x0 -- --#define IQM_RC_ADJ_SEL__A 0x1840014 --#define IQM_RC_ADJ_SEL__W 2 --#define IQM_RC_ADJ_SEL__M 0x3 --#define IQM_RC_ADJ_SEL__PRE 0x0 -- --#define IQM_RC_ADJ_SEL_B__B 0 --#define IQM_RC_ADJ_SEL_B__W 2 --#define IQM_RC_ADJ_SEL_B__M 0x3 --#define IQM_RC_ADJ_SEL_B__PRE 0x0 --#define IQM_RC_ADJ_SEL_B_OFF 0x0 --#define IQM_RC_ADJ_SEL_B_QAM 0x1 --#define IQM_RC_ADJ_SEL_B_VSB 0x2 -- --#define IQM_RC_CROUT_ENA__A 0x1840015 --#define IQM_RC_CROUT_ENA__W 1 --#define IQM_RC_CROUT_ENA__M 0x1 --#define IQM_RC_CROUT_ENA__PRE 0x0 -- --#define IQM_RC_CROUT_ENA_ENA__B 0 --#define IQM_RC_CROUT_ENA_ENA__W 1 --#define IQM_RC_CROUT_ENA_ENA__M 0x1 --#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 -- --#define IQM_RC_STRETCH__A 0x1840016 --#define IQM_RC_STRETCH__W 5 --#define IQM_RC_STRETCH__M 0x1F --#define IQM_RC_STRETCH__PRE 0x0 -- --#define IQM_RC_STRETCH_B__B 0 --#define IQM_RC_STRETCH_B__W 5 --#define IQM_RC_STRETCH_B__M 0x1F --#define IQM_RC_STRETCH_B__PRE 0x0 -- -- -- --#define IQM_RT_COMM_EXEC__A 0x1850000 --#define IQM_RT_COMM_EXEC__W 2 --#define IQM_RT_COMM_EXEC__M 0x3 --#define IQM_RT_COMM_EXEC__PRE 0x0 --#define IQM_RT_COMM_EXEC_STOP 0x0 --#define IQM_RT_COMM_EXEC_ACTIVE 0x1 --#define IQM_RT_COMM_EXEC_HOLD 0x2 -- --#define IQM_RT_COMM_MB__A 0x1850002 --#define IQM_RT_COMM_MB__W 2 --#define IQM_RT_COMM_MB__M 0x3 --#define IQM_RT_COMM_MB__PRE 0x0 --#define IQM_RT_COMM_MB_CTL__B 0 --#define IQM_RT_COMM_MB_CTL__W 1 --#define IQM_RT_COMM_MB_CTL__M 0x1 --#define IQM_RT_COMM_MB_CTL__PRE 0x0 --#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 --#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 --#define IQM_RT_COMM_MB_OBS__B 1 --#define IQM_RT_COMM_MB_OBS__W 1 --#define IQM_RT_COMM_MB_OBS__M 0x2 --#define IQM_RT_COMM_MB_OBS__PRE 0x0 --#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 --#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 -- --#define IQM_RT_ACTIVE__A 0x1850010 --#define IQM_RT_ACTIVE__W 2 --#define IQM_RT_ACTIVE__M 0x3 --#define IQM_RT_ACTIVE__PRE 0x0 -- --#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 --#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 --#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 --#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 --#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 --#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 -- --#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 --#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 --#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 --#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 --#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 --#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 -- -- --#define IQM_RT_LO_INCR__A 0x1850011 --#define IQM_RT_LO_INCR__W 12 --#define IQM_RT_LO_INCR__M 0xFFF --#define IQM_RT_LO_INCR__PRE 0x588 --#define IQM_RT_LO_INCR_FM 0x0 --#define IQM_RT_LO_INCR_MN 0x588 -- --#define IQM_RT_ROT_BP__A 0x1850012 --#define IQM_RT_ROT_BP__W 3 --#define IQM_RT_ROT_BP__M 0x7 --#define IQM_RT_ROT_BP__PRE 0x0 -- --#define IQM_RT_ROT_BP_ROT_OFF__B 0 --#define IQM_RT_ROT_BP_ROT_OFF__W 1 --#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 --#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 --#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 --#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 -- --#define IQM_RT_ROT_BP_ROT_BPF__B 1 --#define IQM_RT_ROT_BP_ROT_BPF__W 1 --#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 --#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 -- --#define IQM_RT_ROT_BP_MIX_BP__B 2 --#define IQM_RT_ROT_BP_MIX_BP__W 1 --#define IQM_RT_ROT_BP_MIX_BP__M 0x4 --#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0 -- -- --#define IQM_RT_LP_BP__A 0x1850013 --#define IQM_RT_LP_BP__W 1 --#define IQM_RT_LP_BP__M 0x1 --#define IQM_RT_LP_BP__PRE 0x0 -- --#define IQM_RT_DELAY__A 0x1850014 --#define IQM_RT_DELAY__W 7 --#define IQM_RT_DELAY__M 0x7F --#define IQM_RT_DELAY__PRE 0x45 -- -- -- --#define IQM_CF_COMM_EXEC__A 0x1860000 --#define IQM_CF_COMM_EXEC__W 2 --#define IQM_CF_COMM_EXEC__M 0x3 --#define IQM_CF_COMM_EXEC__PRE 0x0 --#define IQM_CF_COMM_EXEC_STOP 0x0 --#define IQM_CF_COMM_EXEC_ACTIVE 0x1 --#define IQM_CF_COMM_EXEC_HOLD 0x2 -- --#define IQM_CF_COMM_MB__A 0x1860002 --#define IQM_CF_COMM_MB__W 2 --#define IQM_CF_COMM_MB__M 0x3 --#define IQM_CF_COMM_MB__PRE 0x0 --#define IQM_CF_COMM_MB_CTL__B 0 --#define IQM_CF_COMM_MB_CTL__W 1 --#define IQM_CF_COMM_MB_CTL__M 0x1 --#define IQM_CF_COMM_MB_CTL__PRE 0x0 --#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 --#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 --#define IQM_CF_COMM_MB_OBS__B 1 --#define IQM_CF_COMM_MB_OBS__W 1 --#define IQM_CF_COMM_MB_OBS__M 0x2 --#define IQM_CF_COMM_MB_OBS__PRE 0x0 --#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 --#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 -- --#define IQM_CF_COMM_INT_REQ__A 0x1860003 --#define IQM_CF_COMM_INT_REQ__W 1 --#define IQM_CF_COMM_INT_REQ__M 0x1 --#define IQM_CF_COMM_INT_REQ__PRE 0x0 --#define IQM_CF_COMM_INT_STA__A 0x1860005 --#define IQM_CF_COMM_INT_STA__W 2 --#define IQM_CF_COMM_INT_STA__M 0x3 --#define IQM_CF_COMM_INT_STA__PRE 0x0 --#define IQM_CF_COMM_INT_STA_PM__B 0 --#define IQM_CF_COMM_INT_STA_PM__W 1 --#define IQM_CF_COMM_INT_STA_PM__M 0x1 --#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 --#define IQM_CF_COMM_INT_STA_INC__B 1 --#define IQM_CF_COMM_INT_STA_INC__W 1 --#define IQM_CF_COMM_INT_STA_INC__M 0x2 --#define IQM_CF_COMM_INT_STA_INC__PRE 0x0 -- --#define IQM_CF_COMM_INT_MSK__A 0x1860006 --#define IQM_CF_COMM_INT_MSK__W 2 --#define IQM_CF_COMM_INT_MSK__M 0x3 --#define IQM_CF_COMM_INT_MSK__PRE 0x0 --#define IQM_CF_COMM_INT_MSK_PM__B 0 --#define IQM_CF_COMM_INT_MSK_PM__W 1 --#define IQM_CF_COMM_INT_MSK_PM__M 0x1 --#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 --#define IQM_CF_COMM_INT_MSK_INC__B 1 --#define IQM_CF_COMM_INT_MSK_INC__W 1 --#define IQM_CF_COMM_INT_MSK_INC__M 0x2 --#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0 -- --#define IQM_CF_COMM_INT_STM__A 0x1860007 --#define IQM_CF_COMM_INT_STM__W 2 --#define IQM_CF_COMM_INT_STM__M 0x3 --#define IQM_CF_COMM_INT_STM__PRE 0x0 --#define IQM_CF_COMM_INT_STM_PM__B 0 --#define IQM_CF_COMM_INT_STM_PM__W 1 --#define IQM_CF_COMM_INT_STM_PM__M 0x1 --#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 --#define IQM_CF_COMM_INT_STM_INC__B 1 --#define IQM_CF_COMM_INT_STM_INC__W 1 --#define IQM_CF_COMM_INT_STM_INC__M 0x2 --#define IQM_CF_COMM_INT_STM_INC__PRE 0x0 -- --#define IQM_CF_SYMMETRIC__A 0x1860010 --#define IQM_CF_SYMMETRIC__W 2 --#define IQM_CF_SYMMETRIC__M 0x3 --#define IQM_CF_SYMMETRIC__PRE 0x0 -- --#define IQM_CF_SYMMETRIC_RE__B 0 --#define IQM_CF_SYMMETRIC_RE__W 1 --#define IQM_CF_SYMMETRIC_RE__M 0x1 --#define IQM_CF_SYMMETRIC_RE__PRE 0x0 -- --#define IQM_CF_SYMMETRIC_IM__B 1 --#define IQM_CF_SYMMETRIC_IM__W 1 --#define IQM_CF_SYMMETRIC_IM__M 0x2 --#define IQM_CF_SYMMETRIC_IM__PRE 0x0 -- --#define IQM_CF_MIDTAP__A 0x1860011 --#define IQM_CF_MIDTAP__W 3 --#define IQM_CF_MIDTAP__M 0x7 --#define IQM_CF_MIDTAP__PRE 0x3 -- --#define IQM_CF_MIDTAP_RE__B 0 --#define IQM_CF_MIDTAP_RE__W 1 --#define IQM_CF_MIDTAP_RE__M 0x1 --#define IQM_CF_MIDTAP_RE__PRE 0x1 -- --#define IQM_CF_MIDTAP_IM__B 1 --#define IQM_CF_MIDTAP_IM__W 1 --#define IQM_CF_MIDTAP_IM__M 0x2 --#define IQM_CF_MIDTAP_IM__PRE 0x2 -- --#define IQM_CF_MIDTAP_SCALE__B 2 --#define IQM_CF_MIDTAP_SCALE__W 1 --#define IQM_CF_MIDTAP_SCALE__M 0x4 --#define IQM_CF_MIDTAP_SCALE__PRE 0x0 -- --#define IQM_CF_OUT_ENA__A 0x1860012 --#define IQM_CF_OUT_ENA__W 3 --#define IQM_CF_OUT_ENA__M 0x7 --#define IQM_CF_OUT_ENA__PRE 0x0 -- --#define IQM_CF_OUT_ENA_ATV__B 0 --#define IQM_CF_OUT_ENA_ATV__W 1 --#define IQM_CF_OUT_ENA_ATV__M 0x1 --#define IQM_CF_OUT_ENA_ATV__PRE 0x0 -- --#define IQM_CF_OUT_ENA_QAM__B 1 --#define IQM_CF_OUT_ENA_QAM__W 1 --#define IQM_CF_OUT_ENA_QAM__M 0x2 --#define IQM_CF_OUT_ENA_QAM__PRE 0x0 -- --#define IQM_CF_OUT_ENA_OFDM__B 2 --#define IQM_CF_OUT_ENA_OFDM__W 1 --#define IQM_CF_OUT_ENA_OFDM__M 0x4 --#define IQM_CF_OUT_ENA_OFDM__PRE 0x0 -- --#define IQM_CF_ADJ_SEL__A 0x1860013 --#define IQM_CF_ADJ_SEL__W 2 --#define IQM_CF_ADJ_SEL__M 0x3 --#define IQM_CF_ADJ_SEL__PRE 0x0 -- --#define IQM_CF_ADJ_SEL_B__B 0 --#define IQM_CF_ADJ_SEL_B__W 2 --#define IQM_CF_ADJ_SEL_B__M 0x3 --#define IQM_CF_ADJ_SEL_B__PRE 0x0 -- --#define IQM_CF_SCALE__A 0x1860014 --#define IQM_CF_SCALE__W 14 --#define IQM_CF_SCALE__M 0x3FFF --#define IQM_CF_SCALE__PRE 0x400 --#define IQM_CF_SCALE_B__B 0 --#define IQM_CF_SCALE_B__W 14 --#define IQM_CF_SCALE_B__M 0x3FFF --#define IQM_CF_SCALE_B__PRE 0x400 -- --#define IQM_CF_SCALE_SH__A 0x1860015 --#define IQM_CF_SCALE_SH__W 2 --#define IQM_CF_SCALE_SH__M 0x3 --#define IQM_CF_SCALE_SH__PRE 0x0 -- --#define IQM_CF_SCALE_SH_B__B 0 --#define IQM_CF_SCALE_SH_B__W 2 --#define IQM_CF_SCALE_SH_B__M 0x3 --#define IQM_CF_SCALE_SH_B__PRE 0x0 -- --#define IQM_CF_AMP__A 0x1860016 --#define IQM_CF_AMP__W 14 --#define IQM_CF_AMP__M 0x3FFF --#define IQM_CF_AMP__PRE 0x0 -- --#define IQM_CF_AMP_B__B 0 --#define IQM_CF_AMP_B__W 14 --#define IQM_CF_AMP_B__M 0x3FFF --#define IQM_CF_AMP_B__PRE 0x0 -- --#define IQM_CF_POW_MEAS_LEN__A 0x1860017 --#define IQM_CF_POW_MEAS_LEN__W 3 --#define IQM_CF_POW_MEAS_LEN__M 0x7 --#define IQM_CF_POW_MEAS_LEN__PRE 0x2 -- --#define IQM_CF_POW_MEAS_LEN_B__B 0 --#define IQM_CF_POW_MEAS_LEN_B__W 3 --#define IQM_CF_POW_MEAS_LEN_B__M 0x7 --#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2 -- --#define IQM_CF_POW__A 0x1860018 --#define IQM_CF_POW__W 16 --#define IQM_CF_POW__M 0xFFFF --#define IQM_CF_POW__PRE 0x2 --#define IQM_CF_POW_B__B 0 --#define IQM_CF_POW_B__W 16 --#define IQM_CF_POW_B__M 0xFFFF --#define IQM_CF_POW_B__PRE 0x2 -- --#define IQM_CF_DS_ENA__A 0x1860019 --#define IQM_CF_DS_ENA__W 3 --#define IQM_CF_DS_ENA__M 0x7 --#define IQM_CF_DS_ENA__PRE 0x4 -- --#define IQM_CF_DS_ENA_ATV__B 0 --#define IQM_CF_DS_ENA_ATV__W 1 --#define IQM_CF_DS_ENA_ATV__M 0x1 --#define IQM_CF_DS_ENA_ATV__PRE 0x0 -- --#define IQM_CF_DS_ENA_QAM__B 1 --#define IQM_CF_DS_ENA_QAM__W 1 --#define IQM_CF_DS_ENA_QAM__M 0x2 --#define IQM_CF_DS_ENA_QAM__PRE 0x0 -- --#define IQM_CF_DS_ENA_VSB__B 2 --#define IQM_CF_DS_ENA_VSB__W 1 --#define IQM_CF_DS_ENA_VSB__M 0x4 --#define IQM_CF_DS_ENA_VSB__PRE 0x4 -- -- --#define IQM_CF_POW_UPD__A 0x186001A --#define IQM_CF_POW_UPD__W 1 --#define IQM_CF_POW_UPD__M 0x1 --#define IQM_CF_POW_UPD__PRE 0x0 --#define IQM_CF_TAP_RE0__A 0x1860020 --#define IQM_CF_TAP_RE0__W 7 --#define IQM_CF_TAP_RE0__M 0x7F --#define IQM_CF_TAP_RE0__PRE 0x2 --#define IQM_CF_TAP_RE0_B__B 0 --#define IQM_CF_TAP_RE0_B__W 7 --#define IQM_CF_TAP_RE0_B__M 0x7F --#define IQM_CF_TAP_RE0_B__PRE 0x2 -- --#define IQM_CF_TAP_RE1__A 0x1860021 --#define IQM_CF_TAP_RE1__W 7 --#define IQM_CF_TAP_RE1__M 0x7F --#define IQM_CF_TAP_RE1__PRE 0x2 --#define IQM_CF_TAP_RE1_B__B 0 --#define IQM_CF_TAP_RE1_B__W 7 --#define IQM_CF_TAP_RE1_B__M 0x7F --#define IQM_CF_TAP_RE1_B__PRE 0x2 -- --#define IQM_CF_TAP_RE2__A 0x1860022 --#define IQM_CF_TAP_RE2__W 7 --#define IQM_CF_TAP_RE2__M 0x7F --#define IQM_CF_TAP_RE2__PRE 0x2 --#define IQM_CF_TAP_RE2_B__B 0 --#define IQM_CF_TAP_RE2_B__W 7 --#define IQM_CF_TAP_RE2_B__M 0x7F --#define IQM_CF_TAP_RE2_B__PRE 0x2 -- --#define IQM_CF_TAP_RE3__A 0x1860023 --#define IQM_CF_TAP_RE3__W 7 --#define IQM_CF_TAP_RE3__M 0x7F --#define IQM_CF_TAP_RE3__PRE 0x2 --#define IQM_CF_TAP_RE3_B__B 0 --#define IQM_CF_TAP_RE3_B__W 7 --#define IQM_CF_TAP_RE3_B__M 0x7F --#define IQM_CF_TAP_RE3_B__PRE 0x2 -- --#define IQM_CF_TAP_RE4__A 0x1860024 --#define IQM_CF_TAP_RE4__W 7 --#define IQM_CF_TAP_RE4__M 0x7F --#define IQM_CF_TAP_RE4__PRE 0x2 --#define IQM_CF_TAP_RE4_B__B 0 --#define IQM_CF_TAP_RE4_B__W 7 --#define IQM_CF_TAP_RE4_B__M 0x7F --#define IQM_CF_TAP_RE4_B__PRE 0x2 -- --#define IQM_CF_TAP_RE5__A 0x1860025 --#define IQM_CF_TAP_RE5__W 7 --#define IQM_CF_TAP_RE5__M 0x7F --#define IQM_CF_TAP_RE5__PRE 0x2 --#define IQM_CF_TAP_RE5_B__B 0 --#define IQM_CF_TAP_RE5_B__W 7 --#define IQM_CF_TAP_RE5_B__M 0x7F --#define IQM_CF_TAP_RE5_B__PRE 0x2 -- --#define IQM_CF_TAP_RE6__A 0x1860026 --#define IQM_CF_TAP_RE6__W 7 --#define IQM_CF_TAP_RE6__M 0x7F --#define IQM_CF_TAP_RE6__PRE 0x2 --#define IQM_CF_TAP_RE6_B__B 0 --#define IQM_CF_TAP_RE6_B__W 7 --#define IQM_CF_TAP_RE6_B__M 0x7F --#define IQM_CF_TAP_RE6_B__PRE 0x2 -- --#define IQM_CF_TAP_RE7__A 0x1860027 --#define IQM_CF_TAP_RE7__W 9 --#define IQM_CF_TAP_RE7__M 0x1FF --#define IQM_CF_TAP_RE7__PRE 0x2 --#define IQM_CF_TAP_RE7_B__B 0 --#define IQM_CF_TAP_RE7_B__W 9 --#define IQM_CF_TAP_RE7_B__M 0x1FF --#define IQM_CF_TAP_RE7_B__PRE 0x2 -- --#define IQM_CF_TAP_RE8__A 0x1860028 --#define IQM_CF_TAP_RE8__W 9 --#define IQM_CF_TAP_RE8__M 0x1FF --#define IQM_CF_TAP_RE8__PRE 0x2 --#define IQM_CF_TAP_RE8_B__B 0 --#define IQM_CF_TAP_RE8_B__W 9 --#define IQM_CF_TAP_RE8_B__M 0x1FF --#define IQM_CF_TAP_RE8_B__PRE 0x2 -- --#define IQM_CF_TAP_RE9__A 0x1860029 --#define IQM_CF_TAP_RE9__W 9 --#define IQM_CF_TAP_RE9__M 0x1FF --#define IQM_CF_TAP_RE9__PRE 0x2 --#define IQM_CF_TAP_RE9_B__B 0 --#define IQM_CF_TAP_RE9_B__W 9 --#define IQM_CF_TAP_RE9_B__M 0x1FF --#define IQM_CF_TAP_RE9_B__PRE 0x2 -- --#define IQM_CF_TAP_RE10__A 0x186002A --#define IQM_CF_TAP_RE10__W 9 --#define IQM_CF_TAP_RE10__M 0x1FF --#define IQM_CF_TAP_RE10__PRE 0x2 --#define IQM_CF_TAP_RE10_B__B 0 --#define IQM_CF_TAP_RE10_B__W 9 --#define IQM_CF_TAP_RE10_B__M 0x1FF --#define IQM_CF_TAP_RE10_B__PRE 0x2 -- --#define IQM_CF_TAP_RE11__A 0x186002B --#define IQM_CF_TAP_RE11__W 9 --#define IQM_CF_TAP_RE11__M 0x1FF --#define IQM_CF_TAP_RE11__PRE 0x2 --#define IQM_CF_TAP_RE11_B__B 0 --#define IQM_CF_TAP_RE11_B__W 9 --#define IQM_CF_TAP_RE11_B__M 0x1FF --#define IQM_CF_TAP_RE11_B__PRE 0x2 -- --#define IQM_CF_TAP_RE12__A 0x186002C --#define IQM_CF_TAP_RE12__W 9 --#define IQM_CF_TAP_RE12__M 0x1FF --#define IQM_CF_TAP_RE12__PRE 0x2 --#define IQM_CF_TAP_RE12_B__B 0 --#define IQM_CF_TAP_RE12_B__W 9 --#define IQM_CF_TAP_RE12_B__M 0x1FF --#define IQM_CF_TAP_RE12_B__PRE 0x2 -- --#define IQM_CF_TAP_RE13__A 0x186002D --#define IQM_CF_TAP_RE13__W 9 --#define IQM_CF_TAP_RE13__M 0x1FF --#define IQM_CF_TAP_RE13__PRE 0x2 --#define IQM_CF_TAP_RE13_B__B 0 --#define IQM_CF_TAP_RE13_B__W 9 --#define IQM_CF_TAP_RE13_B__M 0x1FF --#define IQM_CF_TAP_RE13_B__PRE 0x2 -- --#define IQM_CF_TAP_RE14__A 0x186002E --#define IQM_CF_TAP_RE14__W 9 --#define IQM_CF_TAP_RE14__M 0x1FF --#define IQM_CF_TAP_RE14__PRE 0x2 --#define IQM_CF_TAP_RE14_B__B 0 --#define IQM_CF_TAP_RE14_B__W 9 --#define IQM_CF_TAP_RE14_B__M 0x1FF --#define IQM_CF_TAP_RE14_B__PRE 0x2 -- --#define IQM_CF_TAP_RE15__A 0x186002F --#define IQM_CF_TAP_RE15__W 9 --#define IQM_CF_TAP_RE15__M 0x1FF --#define IQM_CF_TAP_RE15__PRE 0x2 --#define IQM_CF_TAP_RE15_B__B 0 --#define IQM_CF_TAP_RE15_B__W 9 --#define IQM_CF_TAP_RE15_B__M 0x1FF --#define IQM_CF_TAP_RE15_B__PRE 0x2 -- --#define IQM_CF_TAP_RE16__A 0x1860030 --#define IQM_CF_TAP_RE16__W 9 --#define IQM_CF_TAP_RE16__M 0x1FF --#define IQM_CF_TAP_RE16__PRE 0x2 --#define IQM_CF_TAP_RE16_B__B 0 --#define IQM_CF_TAP_RE16_B__W 9 --#define IQM_CF_TAP_RE16_B__M 0x1FF --#define IQM_CF_TAP_RE16_B__PRE 0x2 -- --#define IQM_CF_TAP_RE17__A 0x1860031 --#define IQM_CF_TAP_RE17__W 9 --#define IQM_CF_TAP_RE17__M 0x1FF --#define IQM_CF_TAP_RE17__PRE 0x2 --#define IQM_CF_TAP_RE17_B__B 0 --#define IQM_CF_TAP_RE17_B__W 9 --#define IQM_CF_TAP_RE17_B__M 0x1FF --#define IQM_CF_TAP_RE17_B__PRE 0x2 -- --#define IQM_CF_TAP_RE18__A 0x1860032 --#define IQM_CF_TAP_RE18__W 9 --#define IQM_CF_TAP_RE18__M 0x1FF --#define IQM_CF_TAP_RE18__PRE 0x2 --#define IQM_CF_TAP_RE18_B__B 0 --#define IQM_CF_TAP_RE18_B__W 9 --#define IQM_CF_TAP_RE18_B__M 0x1FF --#define IQM_CF_TAP_RE18_B__PRE 0x2 -- --#define IQM_CF_TAP_RE19__A 0x1860033 --#define IQM_CF_TAP_RE19__W 9 --#define IQM_CF_TAP_RE19__M 0x1FF --#define IQM_CF_TAP_RE19__PRE 0x2 --#define IQM_CF_TAP_RE19_B__B 0 --#define IQM_CF_TAP_RE19_B__W 9 --#define IQM_CF_TAP_RE19_B__M 0x1FF --#define IQM_CF_TAP_RE19_B__PRE 0x2 -- --#define IQM_CF_TAP_RE20__A 0x1860034 --#define IQM_CF_TAP_RE20__W 9 --#define IQM_CF_TAP_RE20__M 0x1FF --#define IQM_CF_TAP_RE20__PRE 0x2 --#define IQM_CF_TAP_RE20_B__B 0 --#define IQM_CF_TAP_RE20_B__W 9 --#define IQM_CF_TAP_RE20_B__M 0x1FF --#define IQM_CF_TAP_RE20_B__PRE 0x2 -- --#define IQM_CF_TAP_RE21__A 0x1860035 --#define IQM_CF_TAP_RE21__W 11 --#define IQM_CF_TAP_RE21__M 0x7FF --#define IQM_CF_TAP_RE21__PRE 0x2 --#define IQM_CF_TAP_RE21_B__B 0 --#define IQM_CF_TAP_RE21_B__W 11 --#define IQM_CF_TAP_RE21_B__M 0x7FF --#define IQM_CF_TAP_RE21_B__PRE 0x2 -- --#define IQM_CF_TAP_RE22__A 0x1860036 --#define IQM_CF_TAP_RE22__W 11 --#define IQM_CF_TAP_RE22__M 0x7FF --#define IQM_CF_TAP_RE22__PRE 0x2 --#define IQM_CF_TAP_RE22_B__B 0 --#define IQM_CF_TAP_RE22_B__W 11 --#define IQM_CF_TAP_RE22_B__M 0x7FF --#define IQM_CF_TAP_RE22_B__PRE 0x2 -- --#define IQM_CF_TAP_RE23__A 0x1860037 --#define IQM_CF_TAP_RE23__W 11 --#define IQM_CF_TAP_RE23__M 0x7FF --#define IQM_CF_TAP_RE23__PRE 0x2 --#define IQM_CF_TAP_RE23_B__B 0 --#define IQM_CF_TAP_RE23_B__W 11 --#define IQM_CF_TAP_RE23_B__M 0x7FF --#define IQM_CF_TAP_RE23_B__PRE 0x2 -- --#define IQM_CF_TAP_RE24__A 0x1860038 --#define IQM_CF_TAP_RE24__W 11 --#define IQM_CF_TAP_RE24__M 0x7FF --#define IQM_CF_TAP_RE24__PRE 0x2 --#define IQM_CF_TAP_RE24_B__B 0 --#define IQM_CF_TAP_RE24_B__W 11 --#define IQM_CF_TAP_RE24_B__M 0x7FF --#define IQM_CF_TAP_RE24_B__PRE 0x2 -- --#define IQM_CF_TAP_RE25__A 0x1860039 --#define IQM_CF_TAP_RE25__W 11 --#define IQM_CF_TAP_RE25__M 0x7FF --#define IQM_CF_TAP_RE25__PRE 0x2 --#define IQM_CF_TAP_RE25_B__B 0 --#define IQM_CF_TAP_RE25_B__W 11 --#define IQM_CF_TAP_RE25_B__M 0x7FF --#define IQM_CF_TAP_RE25_B__PRE 0x2 -- --#define IQM_CF_TAP_RE26__A 0x186003A --#define IQM_CF_TAP_RE26__W 11 --#define IQM_CF_TAP_RE26__M 0x7FF --#define IQM_CF_TAP_RE26__PRE 0x2 --#define IQM_CF_TAP_RE26_B__B 0 --#define IQM_CF_TAP_RE26_B__W 11 --#define IQM_CF_TAP_RE26_B__M 0x7FF --#define IQM_CF_TAP_RE26_B__PRE 0x2 -- --#define IQM_CF_TAP_RE27__A 0x186003B --#define IQM_CF_TAP_RE27__W 11 --#define IQM_CF_TAP_RE27__M 0x7FF --#define IQM_CF_TAP_RE27__PRE 0x2 --#define IQM_CF_TAP_RE27_B__B 0 --#define IQM_CF_TAP_RE27_B__W 11 --#define IQM_CF_TAP_RE27_B__M 0x7FF --#define IQM_CF_TAP_RE27_B__PRE 0x2 -- --#define IQM_CF_TAP_IM0__A 0x1860040 --#define IQM_CF_TAP_IM0__W 7 --#define IQM_CF_TAP_IM0__M 0x7F --#define IQM_CF_TAP_IM0__PRE 0x2 --#define IQM_CF_TAP_IM0_B__B 0 --#define IQM_CF_TAP_IM0_B__W 7 --#define IQM_CF_TAP_IM0_B__M 0x7F --#define IQM_CF_TAP_IM0_B__PRE 0x2 -- --#define IQM_CF_TAP_IM1__A 0x1860041 --#define IQM_CF_TAP_IM1__W 7 --#define IQM_CF_TAP_IM1__M 0x7F --#define IQM_CF_TAP_IM1__PRE 0x2 --#define IQM_CF_TAP_IM1_B__B 0 --#define IQM_CF_TAP_IM1_B__W 7 --#define IQM_CF_TAP_IM1_B__M 0x7F --#define IQM_CF_TAP_IM1_B__PRE 0x2 -- --#define IQM_CF_TAP_IM2__A 0x1860042 --#define IQM_CF_TAP_IM2__W 7 --#define IQM_CF_TAP_IM2__M 0x7F --#define IQM_CF_TAP_IM2__PRE 0x2 --#define IQM_CF_TAP_IM2_B__B 0 --#define IQM_CF_TAP_IM2_B__W 7 --#define IQM_CF_TAP_IM2_B__M 0x7F --#define IQM_CF_TAP_IM2_B__PRE 0x2 -- --#define IQM_CF_TAP_IM3__A 0x1860043 --#define IQM_CF_TAP_IM3__W 7 --#define IQM_CF_TAP_IM3__M 0x7F --#define IQM_CF_TAP_IM3__PRE 0x2 --#define IQM_CF_TAP_IM3_B__B 0 --#define IQM_CF_TAP_IM3_B__W 7 --#define IQM_CF_TAP_IM3_B__M 0x7F --#define IQM_CF_TAP_IM3_B__PRE 0x2 -- --#define IQM_CF_TAP_IM4__A 0x1860044 --#define IQM_CF_TAP_IM4__W 7 --#define IQM_CF_TAP_IM4__M 0x7F --#define IQM_CF_TAP_IM4__PRE 0x2 --#define IQM_CF_TAP_IM4_B__B 0 --#define IQM_CF_TAP_IM4_B__W 7 --#define IQM_CF_TAP_IM4_B__M 0x7F --#define IQM_CF_TAP_IM4_B__PRE 0x2 -- --#define IQM_CF_TAP_IM5__A 0x1860045 --#define IQM_CF_TAP_IM5__W 7 --#define IQM_CF_TAP_IM5__M 0x7F --#define IQM_CF_TAP_IM5__PRE 0x2 --#define IQM_CF_TAP_IM5_B__B 0 --#define IQM_CF_TAP_IM5_B__W 7 --#define IQM_CF_TAP_IM5_B__M 0x7F --#define IQM_CF_TAP_IM5_B__PRE 0x2 -- --#define IQM_CF_TAP_IM6__A 0x1860046 --#define IQM_CF_TAP_IM6__W 7 --#define IQM_CF_TAP_IM6__M 0x7F --#define IQM_CF_TAP_IM6__PRE 0x2 --#define IQM_CF_TAP_IM6_B__B 0 --#define IQM_CF_TAP_IM6_B__W 7 --#define IQM_CF_TAP_IM6_B__M 0x7F --#define IQM_CF_TAP_IM6_B__PRE 0x2 -- --#define IQM_CF_TAP_IM7__A 0x1860047 --#define IQM_CF_TAP_IM7__W 9 --#define IQM_CF_TAP_IM7__M 0x1FF --#define IQM_CF_TAP_IM7__PRE 0x2 --#define IQM_CF_TAP_IM7_B__B 0 --#define IQM_CF_TAP_IM7_B__W 9 --#define IQM_CF_TAP_IM7_B__M 0x1FF --#define IQM_CF_TAP_IM7_B__PRE 0x2 -- --#define IQM_CF_TAP_IM8__A 0x1860048 --#define IQM_CF_TAP_IM8__W 9 --#define IQM_CF_TAP_IM8__M 0x1FF --#define IQM_CF_TAP_IM8__PRE 0x2 --#define IQM_CF_TAP_IM8_B__B 0 --#define IQM_CF_TAP_IM8_B__W 9 --#define IQM_CF_TAP_IM8_B__M 0x1FF --#define IQM_CF_TAP_IM8_B__PRE 0x2 -- --#define IQM_CF_TAP_IM9__A 0x1860049 --#define IQM_CF_TAP_IM9__W 9 --#define IQM_CF_TAP_IM9__M 0x1FF --#define IQM_CF_TAP_IM9__PRE 0x2 --#define IQM_CF_TAP_IM9_B__B 0 --#define IQM_CF_TAP_IM9_B__W 9 --#define IQM_CF_TAP_IM9_B__M 0x1FF --#define IQM_CF_TAP_IM9_B__PRE 0x2 -- --#define IQM_CF_TAP_IM10__A 0x186004A --#define IQM_CF_TAP_IM10__W 9 --#define IQM_CF_TAP_IM10__M 0x1FF --#define IQM_CF_TAP_IM10__PRE 0x2 --#define IQM_CF_TAP_IM10_B__B 0 --#define IQM_CF_TAP_IM10_B__W 9 --#define IQM_CF_TAP_IM10_B__M 0x1FF --#define IQM_CF_TAP_IM10_B__PRE 0x2 -- --#define IQM_CF_TAP_IM11__A 0x186004B --#define IQM_CF_TAP_IM11__W 9 --#define IQM_CF_TAP_IM11__M 0x1FF --#define IQM_CF_TAP_IM11__PRE 0x2 --#define IQM_CF_TAP_IM11_B__B 0 --#define IQM_CF_TAP_IM11_B__W 9 --#define IQM_CF_TAP_IM11_B__M 0x1FF --#define IQM_CF_TAP_IM11_B__PRE 0x2 -- --#define IQM_CF_TAP_IM12__A 0x186004C --#define IQM_CF_TAP_IM12__W 9 --#define IQM_CF_TAP_IM12__M 0x1FF --#define IQM_CF_TAP_IM12__PRE 0x2 --#define IQM_CF_TAP_IM12_B__B 0 --#define IQM_CF_TAP_IM12_B__W 9 --#define IQM_CF_TAP_IM12_B__M 0x1FF --#define IQM_CF_TAP_IM12_B__PRE 0x2 -- --#define IQM_CF_TAP_IM13__A 0x186004D --#define IQM_CF_TAP_IM13__W 9 --#define IQM_CF_TAP_IM13__M 0x1FF --#define IQM_CF_TAP_IM13__PRE 0x2 --#define IQM_CF_TAP_IM13_B__B 0 --#define IQM_CF_TAP_IM13_B__W 9 --#define IQM_CF_TAP_IM13_B__M 0x1FF --#define IQM_CF_TAP_IM13_B__PRE 0x2 -- --#define IQM_CF_TAP_IM14__A 0x186004E --#define IQM_CF_TAP_IM14__W 9 --#define IQM_CF_TAP_IM14__M 0x1FF --#define IQM_CF_TAP_IM14__PRE 0x2 --#define IQM_CF_TAP_IM14_B__B 0 --#define IQM_CF_TAP_IM14_B__W 9 --#define IQM_CF_TAP_IM14_B__M 0x1FF --#define IQM_CF_TAP_IM14_B__PRE 0x2 -- --#define IQM_CF_TAP_IM15__A 0x186004F --#define IQM_CF_TAP_IM15__W 9 --#define IQM_CF_TAP_IM15__M 0x1FF --#define IQM_CF_TAP_IM15__PRE 0x2 --#define IQM_CF_TAP_IM15_B__B 0 --#define IQM_CF_TAP_IM15_B__W 9 --#define IQM_CF_TAP_IM15_B__M 0x1FF --#define IQM_CF_TAP_IM15_B__PRE 0x2 -- --#define IQM_CF_TAP_IM16__A 0x1860050 --#define IQM_CF_TAP_IM16__W 9 --#define IQM_CF_TAP_IM16__M 0x1FF --#define IQM_CF_TAP_IM16__PRE 0x2 --#define IQM_CF_TAP_IM16_B__B 0 --#define IQM_CF_TAP_IM16_B__W 9 --#define IQM_CF_TAP_IM16_B__M 0x1FF --#define IQM_CF_TAP_IM16_B__PRE 0x2 -- --#define IQM_CF_TAP_IM17__A 0x1860051 --#define IQM_CF_TAP_IM17__W 9 --#define IQM_CF_TAP_IM17__M 0x1FF --#define IQM_CF_TAP_IM17__PRE 0x2 --#define IQM_CF_TAP_IM17_B__B 0 --#define IQM_CF_TAP_IM17_B__W 9 --#define IQM_CF_TAP_IM17_B__M 0x1FF --#define IQM_CF_TAP_IM17_B__PRE 0x2 -- --#define IQM_CF_TAP_IM18__A 0x1860052 --#define IQM_CF_TAP_IM18__W 9 --#define IQM_CF_TAP_IM18__M 0x1FF --#define IQM_CF_TAP_IM18__PRE 0x2 --#define IQM_CF_TAP_IM18_B__B 0 --#define IQM_CF_TAP_IM18_B__W 9 --#define IQM_CF_TAP_IM18_B__M 0x1FF --#define IQM_CF_TAP_IM18_B__PRE 0x2 -- --#define IQM_CF_TAP_IM19__A 0x1860053 --#define IQM_CF_TAP_IM19__W 9 --#define IQM_CF_TAP_IM19__M 0x1FF --#define IQM_CF_TAP_IM19__PRE 0x2 --#define IQM_CF_TAP_IM19_B__B 0 --#define IQM_CF_TAP_IM19_B__W 9 --#define IQM_CF_TAP_IM19_B__M 0x1FF --#define IQM_CF_TAP_IM19_B__PRE 0x2 -- --#define IQM_CF_TAP_IM20__A 0x1860054 --#define IQM_CF_TAP_IM20__W 9 --#define IQM_CF_TAP_IM20__M 0x1FF --#define IQM_CF_TAP_IM20__PRE 0x2 --#define IQM_CF_TAP_IM20_B__B 0 --#define IQM_CF_TAP_IM20_B__W 9 --#define IQM_CF_TAP_IM20_B__M 0x1FF --#define IQM_CF_TAP_IM20_B__PRE 0x2 -- --#define IQM_CF_TAP_IM21__A 0x1860055 --#define IQM_CF_TAP_IM21__W 11 --#define IQM_CF_TAP_IM21__M 0x7FF --#define IQM_CF_TAP_IM21__PRE 0x2 --#define IQM_CF_TAP_IM21_B__B 0 --#define IQM_CF_TAP_IM21_B__W 11 --#define IQM_CF_TAP_IM21_B__M 0x7FF --#define IQM_CF_TAP_IM21_B__PRE 0x2 -- --#define IQM_CF_TAP_IM22__A 0x1860056 --#define IQM_CF_TAP_IM22__W 11 --#define IQM_CF_TAP_IM22__M 0x7FF --#define IQM_CF_TAP_IM22__PRE 0x2 --#define IQM_CF_TAP_IM22_B__B 0 --#define IQM_CF_TAP_IM22_B__W 11 --#define IQM_CF_TAP_IM22_B__M 0x7FF --#define IQM_CF_TAP_IM22_B__PRE 0x2 -- --#define IQM_CF_TAP_IM23__A 0x1860057 --#define IQM_CF_TAP_IM23__W 11 --#define IQM_CF_TAP_IM23__M 0x7FF --#define IQM_CF_TAP_IM23__PRE 0x2 --#define IQM_CF_TAP_IM23_B__B 0 --#define IQM_CF_TAP_IM23_B__W 11 --#define IQM_CF_TAP_IM23_B__M 0x7FF --#define IQM_CF_TAP_IM23_B__PRE 0x2 -- --#define IQM_CF_TAP_IM24__A 0x1860058 --#define IQM_CF_TAP_IM24__W 11 --#define IQM_CF_TAP_IM24__M 0x7FF --#define IQM_CF_TAP_IM24__PRE 0x2 --#define IQM_CF_TAP_IM24_B__B 0 --#define IQM_CF_TAP_IM24_B__W 11 --#define IQM_CF_TAP_IM24_B__M 0x7FF --#define IQM_CF_TAP_IM24_B__PRE 0x2 -- --#define IQM_CF_TAP_IM25__A 0x1860059 --#define IQM_CF_TAP_IM25__W 11 --#define IQM_CF_TAP_IM25__M 0x7FF --#define IQM_CF_TAP_IM25__PRE 0x2 --#define IQM_CF_TAP_IM25_B__B 0 --#define IQM_CF_TAP_IM25_B__W 11 --#define IQM_CF_TAP_IM25_B__M 0x7FF --#define IQM_CF_TAP_IM25_B__PRE 0x2 -- --#define IQM_CF_TAP_IM26__A 0x186005A --#define IQM_CF_TAP_IM26__W 11 --#define IQM_CF_TAP_IM26__M 0x7FF --#define IQM_CF_TAP_IM26__PRE 0x2 --#define IQM_CF_TAP_IM26_B__B 0 --#define IQM_CF_TAP_IM26_B__W 11 --#define IQM_CF_TAP_IM26_B__M 0x7FF --#define IQM_CF_TAP_IM26_B__PRE 0x2 -- --#define IQM_CF_TAP_IM27__A 0x186005B --#define IQM_CF_TAP_IM27__W 11 --#define IQM_CF_TAP_IM27__M 0x7FF --#define IQM_CF_TAP_IM27__PRE 0x2 --#define IQM_CF_TAP_IM27_B__B 0 --#define IQM_CF_TAP_IM27_B__W 11 --#define IQM_CF_TAP_IM27_B__M 0x7FF --#define IQM_CF_TAP_IM27_B__PRE 0x2 -- -- --#define IQM_CF_CLP_VAL__A 0x1860060 --#define IQM_CF_CLP_VAL__W 9 --#define IQM_CF_CLP_VAL__M 0x1FF --#define IQM_CF_CLP_VAL__PRE 0x3C -- --#define IQM_CF_DATATH__A 0x1860061 --#define IQM_CF_DATATH__W 10 --#define IQM_CF_DATATH__M 0x3FF --#define IQM_CF_DATATH__PRE 0x180 -- --#define IQM_CF_PKDTH__A 0x1860062 --#define IQM_CF_PKDTH__W 5 --#define IQM_CF_PKDTH__M 0x1F --#define IQM_CF_PKDTH__PRE 0x1 -- --#define IQM_CF_WND_LEN__A 0x1860063 --#define IQM_CF_WND_LEN__W 4 --#define IQM_CF_WND_LEN__M 0xF --#define IQM_CF_WND_LEN__PRE 0x1 -- --#define IQM_CF_DET_LCT__A 0x1860064 --#define IQM_CF_DET_LCT__W 1 --#define IQM_CF_DET_LCT__M 0x1 --#define IQM_CF_DET_LCT__PRE 0x1 -- --#define IQM_CF_SNS_LEN__A 0x1860065 --#define IQM_CF_SNS_LEN__W 16 --#define IQM_CF_SNS_LEN__M 0xFFFF --#define IQM_CF_SNS_LEN__PRE 0x0 -- --#define IQM_CF_SNS_SENSE__A 0x1860066 --#define IQM_CF_SNS_SENSE__W 16 --#define IQM_CF_SNS_SENSE__M 0xFFFF --#define IQM_CF_SNS_SENSE__PRE 0x0 -- --#define IQM_CF_BYPASSDET__A 0x1860067 --#define IQM_CF_BYPASSDET__W 1 --#define IQM_CF_BYPASSDET__M 0x1 --#define IQM_CF_BYPASSDET__PRE 0x0 -- --#define IQM_CF_UPD_ENA__A 0x1860068 --#define IQM_CF_UPD_ENA__W 1 --#define IQM_CF_UPD_ENA__M 0x1 --#define IQM_CF_UPD_ENA__PRE 0x0 --#define IQM_CF_UPD_ENA_DISABLE 0x0 --#define IQM_CF_UPD_ENA_ENABLE 0x1 -- -- -- --#define IQM_AF_COMM_EXEC__A 0x1870000 --#define IQM_AF_COMM_EXEC__W 2 --#define IQM_AF_COMM_EXEC__M 0x3 --#define IQM_AF_COMM_EXEC__PRE 0x0 --#define IQM_AF_COMM_EXEC_STOP 0x0 --#define IQM_AF_COMM_EXEC_ACTIVE 0x1 --#define IQM_AF_COMM_EXEC_HOLD 0x2 -- --#define IQM_AF_COMM_MB__A 0x1870002 --#define IQM_AF_COMM_MB__W 8 --#define IQM_AF_COMM_MB__M 0xFF --#define IQM_AF_COMM_MB__PRE 0x0 --#define IQM_AF_COMM_MB_CTL__B 0 --#define IQM_AF_COMM_MB_CTL__W 1 --#define IQM_AF_COMM_MB_CTL__M 0x1 --#define IQM_AF_COMM_MB_CTL__PRE 0x0 --#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 --#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 --#define IQM_AF_COMM_MB_OBS__B 1 --#define IQM_AF_COMM_MB_OBS__W 1 --#define IQM_AF_COMM_MB_OBS__M 0x2 --#define IQM_AF_COMM_MB_OBS__PRE 0x0 --#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 --#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 --#define IQM_AF_COMM_MB_MUX_CTRL__B 2 --#define IQM_AF_COMM_MB_MUX_CTRL__W 3 --#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C --#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 --#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 --#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 --#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 --#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC --#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 --#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14 --#define IQM_AF_COMM_MB_MUX_OBS__B 5 --#define IQM_AF_COMM_MB_MUX_OBS__W 3 --#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 --#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 --#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 --#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 --#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 --#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 --#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 --#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0 -- --#define IQM_AF_COMM_INT_REQ__A 0x1870003 --#define IQM_AF_COMM_INT_REQ__W 1 --#define IQM_AF_COMM_INT_REQ__M 0x1 --#define IQM_AF_COMM_INT_REQ__PRE 0x0 --#define IQM_AF_COMM_INT_STA__A 0x1870005 --#define IQM_AF_COMM_INT_STA__W 3 --#define IQM_AF_COMM_INT_STA__M 0x7 --#define IQM_AF_COMM_INT_STA__PRE 0x0 --#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 --#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 --#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 --#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 --#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 --#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 --#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 --#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 --#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2 --#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1 --#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4 --#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0 -- --#define IQM_AF_COMM_INT_MSK__A 0x1870006 --#define IQM_AF_COMM_INT_MSK__W 3 --#define IQM_AF_COMM_INT_MSK__M 0x7 --#define IQM_AF_COMM_INT_MSK__PRE 0x0 --#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 --#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 --#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 --#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 --#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 --#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 --#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 --#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 --#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2 --#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1 --#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4 --#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0 -- --#define IQM_AF_COMM_INT_STM__A 0x1870007 --#define IQM_AF_COMM_INT_STM__W 3 --#define IQM_AF_COMM_INT_STM__M 0x7 --#define IQM_AF_COMM_INT_STM__PRE 0x0 --#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 --#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 --#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 --#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 --#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 --#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 --#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 --#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 --#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2 --#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1 --#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4 --#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0 -- -- --#define IQM_AF_FDB_SEL__A 0x1870010 --#define IQM_AF_FDB_SEL__W 2 --#define IQM_AF_FDB_SEL__M 0x3 --#define IQM_AF_FDB_SEL__PRE 0x0 --#define IQM_AF_CLKNEG__A 0x1870012 --#define IQM_AF_CLKNEG__W 2 --#define IQM_AF_CLKNEG__M 0x3 --#define IQM_AF_CLKNEG__PRE 0x0 -- --#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 --#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 --#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 --#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 --#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 --#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 -- --#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 --#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 --#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 --#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 --#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 --#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 -- -- --#define IQM_AF_MON_IN_MUX__A 0x1870013 --#define IQM_AF_MON_IN_MUX__W 2 --#define IQM_AF_MON_IN_MUX__M 0x3 --#define IQM_AF_MON_IN_MUX__PRE 0x0 -- --#define IQM_AF_MON_IN5__A 0x1870014 --#define IQM_AF_MON_IN5__W 10 --#define IQM_AF_MON_IN5__M 0x3FF --#define IQM_AF_MON_IN5__PRE 0x0 -- --#define IQM_AF_MON_IN4__A 0x1870015 --#define IQM_AF_MON_IN4__W 10 --#define IQM_AF_MON_IN4__M 0x3FF --#define IQM_AF_MON_IN4__PRE 0x0 -- --#define IQM_AF_MON_IN3__A 0x1870016 --#define IQM_AF_MON_IN3__W 10 --#define IQM_AF_MON_IN3__M 0x3FF --#define IQM_AF_MON_IN3__PRE 0x0 -- --#define IQM_AF_MON_IN2__A 0x1870017 --#define IQM_AF_MON_IN2__W 10 --#define IQM_AF_MON_IN2__M 0x3FF --#define IQM_AF_MON_IN2__PRE 0x0 -- --#define IQM_AF_MON_IN1__A 0x1870018 --#define IQM_AF_MON_IN1__W 10 --#define IQM_AF_MON_IN1__M 0x3FF --#define IQM_AF_MON_IN1__PRE 0x0 -- --#define IQM_AF_MON_IN0__A 0x1870019 --#define IQM_AF_MON_IN0__W 10 --#define IQM_AF_MON_IN0__M 0x3FF --#define IQM_AF_MON_IN0__PRE 0x0 -- --#define IQM_AF_MON_IN_VAL__A 0x187001A --#define IQM_AF_MON_IN_VAL__W 1 --#define IQM_AF_MON_IN_VAL__M 0x1 --#define IQM_AF_MON_IN_VAL__PRE 0x0 -- --#define IQM_AF_START_LOCK__A 0x187001B --#define IQM_AF_START_LOCK__W 1 --#define IQM_AF_START_LOCK__M 0x1 --#define IQM_AF_START_LOCK__PRE 0x0 -- --#define IQM_AF_PHASE0__A 0x187001C --#define IQM_AF_PHASE0__W 7 --#define IQM_AF_PHASE0__M 0x7F --#define IQM_AF_PHASE0__PRE 0x0 -- --#define IQM_AF_PHASE1__A 0x187001D --#define IQM_AF_PHASE1__W 7 --#define IQM_AF_PHASE1__M 0x7F --#define IQM_AF_PHASE1__PRE 0x0 -- --#define IQM_AF_PHASE2__A 0x187001E --#define IQM_AF_PHASE2__W 7 --#define IQM_AF_PHASE2__M 0x7F --#define IQM_AF_PHASE2__PRE 0x0 -- --#define IQM_AF_SCU_PHASE__A 0x187001F --#define IQM_AF_SCU_PHASE__W 2 --#define IQM_AF_SCU_PHASE__M 0x3 --#define IQM_AF_SCU_PHASE__PRE 0x0 -- --#define IQM_AF_SYNC_SEL__A 0x1870020 --#define IQM_AF_SYNC_SEL__W 2 --#define IQM_AF_SYNC_SEL__M 0x3 --#define IQM_AF_SYNC_SEL__PRE 0x0 --#define IQM_AF_ADC_CONF__A 0x1870021 --#define IQM_AF_ADC_CONF__W 4 --#define IQM_AF_ADC_CONF__M 0xF --#define IQM_AF_ADC_CONF__PRE 0x0 -- --#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 --#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 --#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 --#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 --#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 --#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 -- --#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 --#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 --#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 --#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 --#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 --#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 -- --#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 -- --#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 --#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 -- -- --#define IQM_AF_CLP_CLIP__A 0x1870022 --#define IQM_AF_CLP_CLIP__W 16 --#define IQM_AF_CLP_CLIP__M 0xFFFF --#define IQM_AF_CLP_CLIP__PRE 0x0 -- --#define IQM_AF_CLP_LEN__A 0x1870023 --#define IQM_AF_CLP_LEN__W 16 --#define IQM_AF_CLP_LEN__M 0xFFFF --#define IQM_AF_CLP_LEN__PRE 0x0 -- --#define IQM_AF_CLP_TH__A 0x1870024 --#define IQM_AF_CLP_TH__W 9 --#define IQM_AF_CLP_TH__M 0x1FF --#define IQM_AF_CLP_TH__PRE 0x0 -- --#define IQM_AF_DCF_BYPASS__A 0x1870025 --#define IQM_AF_DCF_BYPASS__W 1 --#define IQM_AF_DCF_BYPASS__M 0x1 --#define IQM_AF_DCF_BYPASS__PRE 0x0 --#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 --#define IQM_AF_DCF_BYPASS_BYPASS 0x1 -- -- --#define IQM_AF_SNS_LEN__A 0x1870026 --#define IQM_AF_SNS_LEN__W 16 --#define IQM_AF_SNS_LEN__M 0xFFFF --#define IQM_AF_SNS_LEN__PRE 0x0 -- --#define IQM_AF_SNS_SENSE__A 0x1870027 --#define IQM_AF_SNS_SENSE__W 16 --#define IQM_AF_SNS_SENSE__M 0xFFFF --#define IQM_AF_SNS_SENSE__PRE 0x0 -- --#define IQM_AF_AGC_IF__A 0x1870028 --#define IQM_AF_AGC_IF__W 15 --#define IQM_AF_AGC_IF__M 0x7FFF --#define IQM_AF_AGC_IF__PRE 0x0 -- --#define IQM_AF_AGC_RF__A 0x1870029 --#define IQM_AF_AGC_RF__W 15 --#define IQM_AF_AGC_RF__M 0x7FFF --#define IQM_AF_AGC_RF__PRE 0x0 -- --#define IQM_AF_PDREF__A 0x187002B --#define IQM_AF_PDREF__W 5 --#define IQM_AF_PDREF__M 0x1F --#define IQM_AF_PDREF__PRE 0x0 --#define IQM_AF_STDBY__A 0x187002C --#define IQM_AF_STDBY__W 6 --#define IQM_AF_STDBY__M 0x3F --#define IQM_AF_STDBY__PRE 0x3E -- --#define IQM_AF_STDBY_STDBY_BIAS__B 0 --#define IQM_AF_STDBY_STDBY_BIAS__W 1 --#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 --#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 --#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 --#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 -- --#define IQM_AF_STDBY_STDBY_ADC__B 1 --#define IQM_AF_STDBY_STDBY_ADC__W 1 --#define IQM_AF_STDBY_STDBY_ADC__M 0x2 --#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2 --#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0 --#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 -- --#define IQM_AF_STDBY_STDBY_AMP__B 2 --#define IQM_AF_STDBY_STDBY_AMP__W 1 --#define IQM_AF_STDBY_STDBY_AMP__M 0x4 --#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4 --#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0 --#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 -- --#define IQM_AF_STDBY_STDBY_PD__B 3 --#define IQM_AF_STDBY_STDBY_PD__W 1 --#define IQM_AF_STDBY_STDBY_PD__M 0x8 --#define IQM_AF_STDBY_STDBY_PD__PRE 0x8 --#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0 --#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 -- --#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 --#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 --#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 --#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10 --#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0 --#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 -- --#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 --#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 --#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 --#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20 --#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0 --#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 -- -- --#define IQM_AF_AMUX__A 0x187002D --#define IQM_AF_AMUX__W 1 --#define IQM_AF_AMUX__M 0x1 --#define IQM_AF_AMUX__PRE 0x0 --#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 --#define IQM_AF_AMUX_SIGNAL2ADC 0x1 -- -- --#define IQM_AF_TST_AFEMAIN__A 0x187002E --#define IQM_AF_TST_AFEMAIN__W 8 --#define IQM_AF_TST_AFEMAIN__M 0xFF --#define IQM_AF_TST_AFEMAIN__PRE 0x0 -- --#define IQM_AF_UPD_SEL__A 0x187002F --#define IQM_AF_UPD_SEL__W 1 --#define IQM_AF_UPD_SEL__M 0x1 --#define IQM_AF_UPD_SEL__PRE 0x0 -- --#define IQM_AF_INC_DATATH__A 0x1870030 --#define IQM_AF_INC_DATATH__W 9 --#define IQM_AF_INC_DATATH__M 0x1FF --#define IQM_AF_INC_DATATH__PRE 0x180 -- --#define IQM_AF_INC_PKDTH__A 0x1870031 --#define IQM_AF_INC_PKDTH__W 5 --#define IQM_AF_INC_PKDTH__M 0x1F --#define IQM_AF_INC_PKDTH__PRE 0x3 -- --#define IQM_AF_INC_WND_LEN__A 0x1870032 --#define IQM_AF_INC_WND_LEN__W 4 --#define IQM_AF_INC_WND_LEN__M 0xF --#define IQM_AF_INC_WND_LEN__PRE 0xA -- --#define IQM_AF_INC_DLY__A 0x1870033 --#define IQM_AF_INC_DLY__W 7 --#define IQM_AF_INC_DLY__M 0x7F --#define IQM_AF_INC_DLY__PRE 0x14 -- --#define IQM_AF_INC_LCT__A 0x1870034 --#define IQM_AF_INC_LCT__W 1 --#define IQM_AF_INC_LCT__M 0x1 --#define IQM_AF_INC_LCT__PRE 0x1 -- --#define IQM_AF_INC_CLP_VAL__A 0x1870035 --#define IQM_AF_INC_CLP_VAL__W 9 --#define IQM_AF_INC_CLP_VAL__M 0x1FF --#define IQM_AF_INC_CLP_VAL__PRE 0x3C -- --#define IQM_AF_INC_BYPASS__A 0x1870036 --#define IQM_AF_INC_BYPASS__W 1 --#define IQM_AF_INC_BYPASS__M 0x1 --#define IQM_AF_INC_BYPASS__PRE 0x1 -- --#define IQM_AF_INC_MODE_SEL__A 0x1870037 --#define IQM_AF_INC_MODE_SEL__W 2 --#define IQM_AF_INC_MODE_SEL__M 0x3 --#define IQM_AF_INC_MODE_SEL__PRE 0x1 -- --#define IQM_AF_INC_A_DLY__A 0x1870038 --#define IQM_AF_INC_A_DLY__W 6 --#define IQM_AF_INC_A_DLY__M 0x3F --#define IQM_AF_INC_A_DLY__PRE 0xF -- --#define IQM_AF_ISNS_LEN__A 0x1870039 --#define IQM_AF_ISNS_LEN__W 16 --#define IQM_AF_ISNS_LEN__M 0xFFFF --#define IQM_AF_ISNS_LEN__PRE 0x0 -- --#define IQM_AF_ISNS_SENSE__A 0x187003A --#define IQM_AF_ISNS_SENSE__W 16 --#define IQM_AF_ISNS_SENSE__M 0xFFFF --#define IQM_AF_ISNS_SENSE__PRE 0x0 --#define IQM_AF_CMP_STATE__A 0x187003B --#define IQM_AF_CMP_STATE__W 7 --#define IQM_AF_CMP_STATE__M 0x7F --#define IQM_AF_CMP_STATE__PRE 0x0 -- --#define IQM_AF_CMP_STATE_STATE__B 0 --#define IQM_AF_CMP_STATE_STATE__W 2 --#define IQM_AF_CMP_STATE_STATE__M 0x3 --#define IQM_AF_CMP_STATE_STATE__PRE 0x0 -- --#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2 --#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1 --#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4 --#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0 -- --#define IQM_AF_CMP_STATE_FILTERGAIN__B 3 --#define IQM_AF_CMP_STATE_FILTERGAIN__W 2 --#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18 --#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0 --#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0 --#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8 --#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10 --#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18 -- --#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5 --#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1 --#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20 --#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0 -- --#define IQM_AF_CMP_STATE_SEG64__B 6 --#define IQM_AF_CMP_STATE_SEG64__W 1 --#define IQM_AF_CMP_STATE_SEG64__M 0x40 --#define IQM_AF_CMP_STATE_SEG64__PRE 0x0 --#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0 --#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40 -- -- --#define IQM_AF_CMP_DC_OUT__A 0x187003C --#define IQM_AF_CMP_DC_OUT__W 12 --#define IQM_AF_CMP_DC_OUT__M 0xFFF --#define IQM_AF_CMP_DC_OUT__PRE 0x0 --#define IQM_AF_CMP_DC_IN__A 0x187003D --#define IQM_AF_CMP_DC_IN__W 13 --#define IQM_AF_CMP_DC_IN__M 0x1FFF --#define IQM_AF_CMP_DC_IN__PRE 0x0 -- --#define IQM_AF_CMP_DC_IN_DC__B 0 --#define IQM_AF_CMP_DC_IN_DC__W 12 --#define IQM_AF_CMP_DC_IN_DC__M 0xFFF --#define IQM_AF_CMP_DC_IN_DC__PRE 0x0 --#define IQM_AF_CMP_DC_IN_DC_EN__B 12 --#define IQM_AF_CMP_DC_IN_DC_EN__W 1 --#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000 --#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0 --#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0 --#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000 -- -- --#define IQM_AF_CMP_AMP__A 0x187003E --#define IQM_AF_CMP_AMP__W 10 --#define IQM_AF_CMP_AMP__M 0x3FF --#define IQM_AF_CMP_AMP__PRE 0x0 --#define IQM_AF_CMP_DN_AVG__A 0x187003F --#define IQM_AF_CMP_DN_AVG__W 8 --#define IQM_AF_CMP_DN_AVG__M 0xFF --#define IQM_AF_CMP_DN_AVG__PRE 0x0 -- --#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0 --#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8 --#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF --#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0 -- -- --#define IQM_AF_CMP_ACTIVE__A 0x1870040 --#define IQM_AF_CMP_ACTIVE__W 1 --#define IQM_AF_CMP_ACTIVE__M 0x1 --#define IQM_AF_CMP_ACTIVE__PRE 0x0 --#define IQM_AF_CMP_MEM0__A 0x1870080 --#define IQM_AF_CMP_MEM0__W 13 --#define IQM_AF_CMP_MEM0__M 0x1FFF --#define IQM_AF_CMP_MEM0__PRE 0x0 -- --#define IQM_AF_CMP_MEM0_COEF__B 0 --#define IQM_AF_CMP_MEM0_COEF__W 13 --#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM0_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM1__A 0x1870081 --#define IQM_AF_CMP_MEM1__W 13 --#define IQM_AF_CMP_MEM1__M 0x1FFF --#define IQM_AF_CMP_MEM1__PRE 0x0 -- --#define IQM_AF_CMP_MEM1_COEF__B 0 --#define IQM_AF_CMP_MEM1_COEF__W 13 --#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM1_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM2__A 0x1870082 --#define IQM_AF_CMP_MEM2__W 13 --#define IQM_AF_CMP_MEM2__M 0x1FFF --#define IQM_AF_CMP_MEM2__PRE 0x0 -- --#define IQM_AF_CMP_MEM2_COEF__B 0 --#define IQM_AF_CMP_MEM2_COEF__W 13 --#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM2_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM3__A 0x1870083 --#define IQM_AF_CMP_MEM3__W 13 --#define IQM_AF_CMP_MEM3__M 0x1FFF --#define IQM_AF_CMP_MEM3__PRE 0x0 -- --#define IQM_AF_CMP_MEM3_COEF__B 0 --#define IQM_AF_CMP_MEM3_COEF__W 13 --#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM3_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM4__A 0x1870084 --#define IQM_AF_CMP_MEM4__W 13 --#define IQM_AF_CMP_MEM4__M 0x1FFF --#define IQM_AF_CMP_MEM4__PRE 0x0 -- --#define IQM_AF_CMP_MEM4_COEF__B 0 --#define IQM_AF_CMP_MEM4_COEF__W 13 --#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM4_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM5__A 0x1870085 --#define IQM_AF_CMP_MEM5__W 13 --#define IQM_AF_CMP_MEM5__M 0x1FFF --#define IQM_AF_CMP_MEM5__PRE 0x0 -- --#define IQM_AF_CMP_MEM5_COEF__B 0 --#define IQM_AF_CMP_MEM5_COEF__W 13 --#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM5_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM6__A 0x1870086 --#define IQM_AF_CMP_MEM6__W 13 --#define IQM_AF_CMP_MEM6__M 0x1FFF --#define IQM_AF_CMP_MEM6__PRE 0x0 -- --#define IQM_AF_CMP_MEM6_COEF__B 0 --#define IQM_AF_CMP_MEM6_COEF__W 13 --#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM6_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM7__A 0x1870087 --#define IQM_AF_CMP_MEM7__W 13 --#define IQM_AF_CMP_MEM7__M 0x1FFF --#define IQM_AF_CMP_MEM7__PRE 0x0 -- --#define IQM_AF_CMP_MEM7_COEF__B 0 --#define IQM_AF_CMP_MEM7_COEF__W 13 --#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM7_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM8__A 0x1870088 --#define IQM_AF_CMP_MEM8__W 13 --#define IQM_AF_CMP_MEM8__M 0x1FFF --#define IQM_AF_CMP_MEM8__PRE 0x0 -- --#define IQM_AF_CMP_MEM8_COEF__B 0 --#define IQM_AF_CMP_MEM8_COEF__W 13 --#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM8_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM9__A 0x1870089 --#define IQM_AF_CMP_MEM9__W 13 --#define IQM_AF_CMP_MEM9__M 0x1FFF --#define IQM_AF_CMP_MEM9__PRE 0x0 -- --#define IQM_AF_CMP_MEM9_COEF__B 0 --#define IQM_AF_CMP_MEM9_COEF__W 13 --#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM9_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM10__A 0x187008A --#define IQM_AF_CMP_MEM10__W 13 --#define IQM_AF_CMP_MEM10__M 0x1FFF --#define IQM_AF_CMP_MEM10__PRE 0x0 -- --#define IQM_AF_CMP_MEM10_COEF__B 0 --#define IQM_AF_CMP_MEM10_COEF__W 13 --#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM10_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM11__A 0x187008B --#define IQM_AF_CMP_MEM11__W 13 --#define IQM_AF_CMP_MEM11__M 0x1FFF --#define IQM_AF_CMP_MEM11__PRE 0x0 -- --#define IQM_AF_CMP_MEM11_COEF__B 0 --#define IQM_AF_CMP_MEM11_COEF__W 13 --#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM11_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM12__A 0x187008C --#define IQM_AF_CMP_MEM12__W 13 --#define IQM_AF_CMP_MEM12__M 0x1FFF --#define IQM_AF_CMP_MEM12__PRE 0x0 -- --#define IQM_AF_CMP_MEM12_COEF__B 0 --#define IQM_AF_CMP_MEM12_COEF__W 13 --#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM12_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM13__A 0x187008D --#define IQM_AF_CMP_MEM13__W 13 --#define IQM_AF_CMP_MEM13__M 0x1FFF --#define IQM_AF_CMP_MEM13__PRE 0x0 -- --#define IQM_AF_CMP_MEM13_COEF__B 0 --#define IQM_AF_CMP_MEM13_COEF__W 13 --#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM13_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM14__A 0x187008E --#define IQM_AF_CMP_MEM14__W 13 --#define IQM_AF_CMP_MEM14__M 0x1FFF --#define IQM_AF_CMP_MEM14__PRE 0x0 -- --#define IQM_AF_CMP_MEM14_COEF__B 0 --#define IQM_AF_CMP_MEM14_COEF__W 13 --#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM14_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM15__A 0x187008F --#define IQM_AF_CMP_MEM15__W 13 --#define IQM_AF_CMP_MEM15__M 0x1FFF --#define IQM_AF_CMP_MEM15__PRE 0x0 -- --#define IQM_AF_CMP_MEM15_COEF__B 0 --#define IQM_AF_CMP_MEM15_COEF__W 13 --#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM15_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM16__A 0x1870090 --#define IQM_AF_CMP_MEM16__W 13 --#define IQM_AF_CMP_MEM16__M 0x1FFF --#define IQM_AF_CMP_MEM16__PRE 0x0 -- --#define IQM_AF_CMP_MEM16_COEF__B 0 --#define IQM_AF_CMP_MEM16_COEF__W 13 --#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM16_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM17__A 0x1870091 --#define IQM_AF_CMP_MEM17__W 13 --#define IQM_AF_CMP_MEM17__M 0x1FFF --#define IQM_AF_CMP_MEM17__PRE 0x0 -- --#define IQM_AF_CMP_MEM17_COEF__B 0 --#define IQM_AF_CMP_MEM17_COEF__W 13 --#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM17_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM18__A 0x1870092 --#define IQM_AF_CMP_MEM18__W 13 --#define IQM_AF_CMP_MEM18__M 0x1FFF --#define IQM_AF_CMP_MEM18__PRE 0x0 -- --#define IQM_AF_CMP_MEM18_COEF__B 0 --#define IQM_AF_CMP_MEM18_COEF__W 13 --#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM18_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM19__A 0x1870093 --#define IQM_AF_CMP_MEM19__W 13 --#define IQM_AF_CMP_MEM19__M 0x1FFF --#define IQM_AF_CMP_MEM19__PRE 0x0 -- --#define IQM_AF_CMP_MEM19_COEF__B 0 --#define IQM_AF_CMP_MEM19_COEF__W 13 --#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM19_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM20__A 0x1870094 --#define IQM_AF_CMP_MEM20__W 13 --#define IQM_AF_CMP_MEM20__M 0x1FFF --#define IQM_AF_CMP_MEM20__PRE 0x0 -- --#define IQM_AF_CMP_MEM20_COEF__B 0 --#define IQM_AF_CMP_MEM20_COEF__W 13 --#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM20_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM21__A 0x1870095 --#define IQM_AF_CMP_MEM21__W 13 --#define IQM_AF_CMP_MEM21__M 0x1FFF --#define IQM_AF_CMP_MEM21__PRE 0x0 -- --#define IQM_AF_CMP_MEM21_COEF__B 0 --#define IQM_AF_CMP_MEM21_COEF__W 13 --#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM21_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM22__A 0x1870096 --#define IQM_AF_CMP_MEM22__W 13 --#define IQM_AF_CMP_MEM22__M 0x1FFF --#define IQM_AF_CMP_MEM22__PRE 0x0 -- --#define IQM_AF_CMP_MEM22_COEF__B 0 --#define IQM_AF_CMP_MEM22_COEF__W 13 --#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM22_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM23__A 0x1870097 --#define IQM_AF_CMP_MEM23__W 13 --#define IQM_AF_CMP_MEM23__M 0x1FFF --#define IQM_AF_CMP_MEM23__PRE 0x0 -- --#define IQM_AF_CMP_MEM23_COEF__B 0 --#define IQM_AF_CMP_MEM23_COEF__W 13 --#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM23_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM24__A 0x1870098 --#define IQM_AF_CMP_MEM24__W 13 --#define IQM_AF_CMP_MEM24__M 0x1FFF --#define IQM_AF_CMP_MEM24__PRE 0x0 -- --#define IQM_AF_CMP_MEM24_COEF__B 0 --#define IQM_AF_CMP_MEM24_COEF__W 13 --#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM24_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM25__A 0x1870099 --#define IQM_AF_CMP_MEM25__W 13 --#define IQM_AF_CMP_MEM25__M 0x1FFF --#define IQM_AF_CMP_MEM25__PRE 0x0 -- --#define IQM_AF_CMP_MEM25_COEF__B 0 --#define IQM_AF_CMP_MEM25_COEF__W 13 --#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM25_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM26__A 0x187009A --#define IQM_AF_CMP_MEM26__W 13 --#define IQM_AF_CMP_MEM26__M 0x1FFF --#define IQM_AF_CMP_MEM26__PRE 0x0 -- --#define IQM_AF_CMP_MEM26_COEF__B 0 --#define IQM_AF_CMP_MEM26_COEF__W 13 --#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM26_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM27__A 0x187009B --#define IQM_AF_CMP_MEM27__W 13 --#define IQM_AF_CMP_MEM27__M 0x1FFF --#define IQM_AF_CMP_MEM27__PRE 0x0 -- --#define IQM_AF_CMP_MEM27_COEF__B 0 --#define IQM_AF_CMP_MEM27_COEF__W 13 --#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM27_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM28__A 0x187009C --#define IQM_AF_CMP_MEM28__W 13 --#define IQM_AF_CMP_MEM28__M 0x1FFF --#define IQM_AF_CMP_MEM28__PRE 0x0 -- --#define IQM_AF_CMP_MEM28_COEF__B 0 --#define IQM_AF_CMP_MEM28_COEF__W 13 --#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM28_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM29__A 0x187009D --#define IQM_AF_CMP_MEM29__W 13 --#define IQM_AF_CMP_MEM29__M 0x1FFF --#define IQM_AF_CMP_MEM29__PRE 0x0 -- --#define IQM_AF_CMP_MEM29_COEF__B 0 --#define IQM_AF_CMP_MEM29_COEF__W 13 --#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM29_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM30__A 0x187009E --#define IQM_AF_CMP_MEM30__W 13 --#define IQM_AF_CMP_MEM30__M 0x1FFF --#define IQM_AF_CMP_MEM30__PRE 0x0 -- --#define IQM_AF_CMP_MEM30_COEF__B 0 --#define IQM_AF_CMP_MEM30_COEF__W 13 --#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM30_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM31__A 0x187009F --#define IQM_AF_CMP_MEM31__W 13 --#define IQM_AF_CMP_MEM31__M 0x1FFF --#define IQM_AF_CMP_MEM31__PRE 0x0 -- --#define IQM_AF_CMP_MEM31_COEF__B 0 --#define IQM_AF_CMP_MEM31_COEF__W 13 --#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM31_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM32__A 0x18700A0 --#define IQM_AF_CMP_MEM32__W 13 --#define IQM_AF_CMP_MEM32__M 0x1FFF --#define IQM_AF_CMP_MEM32__PRE 0x0 -- --#define IQM_AF_CMP_MEM32_COEF__B 0 --#define IQM_AF_CMP_MEM32_COEF__W 13 --#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM32_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM33__A 0x18700A1 --#define IQM_AF_CMP_MEM33__W 13 --#define IQM_AF_CMP_MEM33__M 0x1FFF --#define IQM_AF_CMP_MEM33__PRE 0x0 -- --#define IQM_AF_CMP_MEM33_COEF__B 0 --#define IQM_AF_CMP_MEM33_COEF__W 13 --#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM33_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM34__A 0x18700A2 --#define IQM_AF_CMP_MEM34__W 13 --#define IQM_AF_CMP_MEM34__M 0x1FFF --#define IQM_AF_CMP_MEM34__PRE 0x0 -- --#define IQM_AF_CMP_MEM34_COEF__B 0 --#define IQM_AF_CMP_MEM34_COEF__W 13 --#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM34_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM35__A 0x18700A3 --#define IQM_AF_CMP_MEM35__W 13 --#define IQM_AF_CMP_MEM35__M 0x1FFF --#define IQM_AF_CMP_MEM35__PRE 0x0 -- --#define IQM_AF_CMP_MEM35_COEF__B 0 --#define IQM_AF_CMP_MEM35_COEF__W 13 --#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM35_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM36__A 0x18700A4 --#define IQM_AF_CMP_MEM36__W 13 --#define IQM_AF_CMP_MEM36__M 0x1FFF --#define IQM_AF_CMP_MEM36__PRE 0x0 -- --#define IQM_AF_CMP_MEM36_COEF__B 0 --#define IQM_AF_CMP_MEM36_COEF__W 13 --#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM36_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM37__A 0x18700A5 --#define IQM_AF_CMP_MEM37__W 13 --#define IQM_AF_CMP_MEM37__M 0x1FFF --#define IQM_AF_CMP_MEM37__PRE 0x0 -- --#define IQM_AF_CMP_MEM37_COEF__B 0 --#define IQM_AF_CMP_MEM37_COEF__W 13 --#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM37_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM38__A 0x18700A6 --#define IQM_AF_CMP_MEM38__W 13 --#define IQM_AF_CMP_MEM38__M 0x1FFF --#define IQM_AF_CMP_MEM38__PRE 0x0 -- --#define IQM_AF_CMP_MEM38_COEF__B 0 --#define IQM_AF_CMP_MEM38_COEF__W 13 --#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM38_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM39__A 0x18700A7 --#define IQM_AF_CMP_MEM39__W 13 --#define IQM_AF_CMP_MEM39__M 0x1FFF --#define IQM_AF_CMP_MEM39__PRE 0x0 -- --#define IQM_AF_CMP_MEM39_COEF__B 0 --#define IQM_AF_CMP_MEM39_COEF__W 13 --#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM39_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM40__A 0x18700A8 --#define IQM_AF_CMP_MEM40__W 13 --#define IQM_AF_CMP_MEM40__M 0x1FFF --#define IQM_AF_CMP_MEM40__PRE 0x0 -- --#define IQM_AF_CMP_MEM40_COEF__B 0 --#define IQM_AF_CMP_MEM40_COEF__W 13 --#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM40_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM41__A 0x18700A9 --#define IQM_AF_CMP_MEM41__W 13 --#define IQM_AF_CMP_MEM41__M 0x1FFF --#define IQM_AF_CMP_MEM41__PRE 0x0 -- --#define IQM_AF_CMP_MEM41_COEF__B 0 --#define IQM_AF_CMP_MEM41_COEF__W 13 --#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM41_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM42__A 0x18700AA --#define IQM_AF_CMP_MEM42__W 13 --#define IQM_AF_CMP_MEM42__M 0x1FFF --#define IQM_AF_CMP_MEM42__PRE 0x0 -- --#define IQM_AF_CMP_MEM42_COEF__B 0 --#define IQM_AF_CMP_MEM42_COEF__W 13 --#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM42_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM43__A 0x18700AB --#define IQM_AF_CMP_MEM43__W 13 --#define IQM_AF_CMP_MEM43__M 0x1FFF --#define IQM_AF_CMP_MEM43__PRE 0x0 -- --#define IQM_AF_CMP_MEM43_COEF__B 0 --#define IQM_AF_CMP_MEM43_COEF__W 13 --#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM43_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM44__A 0x18700AC --#define IQM_AF_CMP_MEM44__W 13 --#define IQM_AF_CMP_MEM44__M 0x1FFF --#define IQM_AF_CMP_MEM44__PRE 0x0 -- --#define IQM_AF_CMP_MEM44_COEF__B 0 --#define IQM_AF_CMP_MEM44_COEF__W 13 --#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM44_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM45__A 0x18700AD --#define IQM_AF_CMP_MEM45__W 13 --#define IQM_AF_CMP_MEM45__M 0x1FFF --#define IQM_AF_CMP_MEM45__PRE 0x0 -- --#define IQM_AF_CMP_MEM45_COEF__B 0 --#define IQM_AF_CMP_MEM45_COEF__W 13 --#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM45_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM46__A 0x18700AE --#define IQM_AF_CMP_MEM46__W 13 --#define IQM_AF_CMP_MEM46__M 0x1FFF --#define IQM_AF_CMP_MEM46__PRE 0x0 -- --#define IQM_AF_CMP_MEM46_COEF__B 0 --#define IQM_AF_CMP_MEM46_COEF__W 13 --#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM46_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM47__A 0x18700AF --#define IQM_AF_CMP_MEM47__W 13 --#define IQM_AF_CMP_MEM47__M 0x1FFF --#define IQM_AF_CMP_MEM47__PRE 0x0 -- --#define IQM_AF_CMP_MEM47_COEF__B 0 --#define IQM_AF_CMP_MEM47_COEF__W 13 --#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM47_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM48__A 0x18700B0 --#define IQM_AF_CMP_MEM48__W 13 --#define IQM_AF_CMP_MEM48__M 0x1FFF --#define IQM_AF_CMP_MEM48__PRE 0x0 -- --#define IQM_AF_CMP_MEM48_COEF__B 0 --#define IQM_AF_CMP_MEM48_COEF__W 13 --#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM48_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM49__A 0x18700B1 --#define IQM_AF_CMP_MEM49__W 13 --#define IQM_AF_CMP_MEM49__M 0x1FFF --#define IQM_AF_CMP_MEM49__PRE 0x0 -- --#define IQM_AF_CMP_MEM49_COEF__B 0 --#define IQM_AF_CMP_MEM49_COEF__W 13 --#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM49_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM50__A 0x18700B2 --#define IQM_AF_CMP_MEM50__W 13 --#define IQM_AF_CMP_MEM50__M 0x1FFF --#define IQM_AF_CMP_MEM50__PRE 0x0 -- --#define IQM_AF_CMP_MEM50_COEF__B 0 --#define IQM_AF_CMP_MEM50_COEF__W 13 --#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM50_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM51__A 0x18700B3 --#define IQM_AF_CMP_MEM51__W 13 --#define IQM_AF_CMP_MEM51__M 0x1FFF --#define IQM_AF_CMP_MEM51__PRE 0x0 -- --#define IQM_AF_CMP_MEM51_COEF__B 0 --#define IQM_AF_CMP_MEM51_COEF__W 13 --#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM51_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM52__A 0x18700B4 --#define IQM_AF_CMP_MEM52__W 13 --#define IQM_AF_CMP_MEM52__M 0x1FFF --#define IQM_AF_CMP_MEM52__PRE 0x0 -- --#define IQM_AF_CMP_MEM52_COEF__B 0 --#define IQM_AF_CMP_MEM52_COEF__W 13 --#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM52_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM53__A 0x18700B5 --#define IQM_AF_CMP_MEM53__W 13 --#define IQM_AF_CMP_MEM53__M 0x1FFF --#define IQM_AF_CMP_MEM53__PRE 0x0 -- --#define IQM_AF_CMP_MEM53_COEF__B 0 --#define IQM_AF_CMP_MEM53_COEF__W 13 --#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM53_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM54__A 0x18700B6 --#define IQM_AF_CMP_MEM54__W 13 --#define IQM_AF_CMP_MEM54__M 0x1FFF --#define IQM_AF_CMP_MEM54__PRE 0x0 -- --#define IQM_AF_CMP_MEM54_COEF__B 0 --#define IQM_AF_CMP_MEM54_COEF__W 13 --#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM54_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM55__A 0x18700B7 --#define IQM_AF_CMP_MEM55__W 13 --#define IQM_AF_CMP_MEM55__M 0x1FFF --#define IQM_AF_CMP_MEM55__PRE 0x0 -- --#define IQM_AF_CMP_MEM55_COEF__B 0 --#define IQM_AF_CMP_MEM55_COEF__W 13 --#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM55_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM56__A 0x18700B8 --#define IQM_AF_CMP_MEM56__W 13 --#define IQM_AF_CMP_MEM56__M 0x1FFF --#define IQM_AF_CMP_MEM56__PRE 0x0 -- --#define IQM_AF_CMP_MEM56_COEF__B 0 --#define IQM_AF_CMP_MEM56_COEF__W 13 --#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM56_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM57__A 0x18700B9 --#define IQM_AF_CMP_MEM57__W 13 --#define IQM_AF_CMP_MEM57__M 0x1FFF --#define IQM_AF_CMP_MEM57__PRE 0x0 -- --#define IQM_AF_CMP_MEM57_COEF__B 0 --#define IQM_AF_CMP_MEM57_COEF__W 13 --#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM57_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM58__A 0x18700BA --#define IQM_AF_CMP_MEM58__W 13 --#define IQM_AF_CMP_MEM58__M 0x1FFF --#define IQM_AF_CMP_MEM58__PRE 0x0 -- --#define IQM_AF_CMP_MEM58_COEF__B 0 --#define IQM_AF_CMP_MEM58_COEF__W 13 --#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM58_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM59__A 0x18700BB --#define IQM_AF_CMP_MEM59__W 13 --#define IQM_AF_CMP_MEM59__M 0x1FFF --#define IQM_AF_CMP_MEM59__PRE 0x0 -- --#define IQM_AF_CMP_MEM59_COEF__B 0 --#define IQM_AF_CMP_MEM59_COEF__W 13 --#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM59_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM60__A 0x18700BC --#define IQM_AF_CMP_MEM60__W 13 --#define IQM_AF_CMP_MEM60__M 0x1FFF --#define IQM_AF_CMP_MEM60__PRE 0x0 -- --#define IQM_AF_CMP_MEM60_COEF__B 0 --#define IQM_AF_CMP_MEM60_COEF__W 13 --#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM60_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM61__A 0x18700BD --#define IQM_AF_CMP_MEM61__W 13 --#define IQM_AF_CMP_MEM61__M 0x1FFF --#define IQM_AF_CMP_MEM61__PRE 0x0 -- --#define IQM_AF_CMP_MEM61_COEF__B 0 --#define IQM_AF_CMP_MEM61_COEF__W 13 --#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM61_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM62__A 0x18700BE --#define IQM_AF_CMP_MEM62__W 13 --#define IQM_AF_CMP_MEM62__M 0x1FFF --#define IQM_AF_CMP_MEM62__PRE 0x0 -- --#define IQM_AF_CMP_MEM62_COEF__B 0 --#define IQM_AF_CMP_MEM62_COEF__W 13 --#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM62_COEF__PRE 0x0 -- --#define IQM_AF_CMP_MEM63__A 0x18700BF --#define IQM_AF_CMP_MEM63__W 13 --#define IQM_AF_CMP_MEM63__M 0x1FFF --#define IQM_AF_CMP_MEM63__PRE 0x0 -- --#define IQM_AF_CMP_MEM63_COEF__B 0 --#define IQM_AF_CMP_MEM63_COEF__W 13 --#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF --#define IQM_AF_CMP_MEM63_COEF__PRE 0x0 -- -- -- --#define IQM_RT_RAM__A 0x1880000 -- --#define IQM_RT_RAM_DLY__B 0 --#define IQM_RT_RAM_DLY__W 13 --#define IQM_RT_RAM_DLY__M 0x1FFF --#define IQM_RT_RAM_DLY__PRE 0x0 -- -- -- -- -- --#define OFDM_CE_COMM_EXEC__A 0x2C00000 --#define OFDM_CE_COMM_EXEC__W 3 --#define OFDM_CE_COMM_EXEC__M 0x7 --#define OFDM_CE_COMM_EXEC__PRE 0x0 --#define OFDM_CE_COMM_EXEC_STOP 0x0 --#define OFDM_CE_COMM_EXEC_ACTIVE 0x1 --#define OFDM_CE_COMM_EXEC_HOLD 0x2 --#define OFDM_CE_COMM_EXEC_STEP 0x3 --#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4 --#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6 -- --#define OFDM_CE_COMM_STATE__A 0x2C00001 --#define OFDM_CE_COMM_STATE__W 16 --#define OFDM_CE_COMM_STATE__M 0xFFFF --#define OFDM_CE_COMM_STATE__PRE 0x0 --#define OFDM_CE_COMM_MB__A 0x2C00002 --#define OFDM_CE_COMM_MB__W 16 --#define OFDM_CE_COMM_MB__M 0xFFFF --#define OFDM_CE_COMM_MB__PRE 0x0 --#define OFDM_CE_COMM_INT_REQ__A 0x2C00004 --#define OFDM_CE_COMM_INT_REQ__W 16 --#define OFDM_CE_COMM_INT_REQ__M 0xFFFF --#define OFDM_CE_COMM_INT_REQ__PRE 0x0 --#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2 --#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1 --#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4 --#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0 -- --#define OFDM_CE_COMM_INT_STA__A 0x2C00005 --#define OFDM_CE_COMM_INT_STA__W 16 --#define OFDM_CE_COMM_INT_STA__M 0xFFFF --#define OFDM_CE_COMM_INT_STA__PRE 0x0 --#define OFDM_CE_COMM_INT_MSK__A 0x2C00006 --#define OFDM_CE_COMM_INT_MSK__W 16 --#define OFDM_CE_COMM_INT_MSK__M 0xFFFF --#define OFDM_CE_COMM_INT_MSK__PRE 0x0 --#define OFDM_CE_COMM_INT_STM__A 0x2C00007 --#define OFDM_CE_COMM_INT_STM__W 16 --#define OFDM_CE_COMM_INT_STM__M 0xFFFF --#define OFDM_CE_COMM_INT_STM__PRE 0x0 --#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0 --#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16 --#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF --#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0 -- -- -- --#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000 --#define OFDM_CE_TOP_COMM_EXEC__W 3 --#define OFDM_CE_TOP_COMM_EXEC__M 0x7 --#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0 --#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0 --#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1 --#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2 --#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3 -- --#define OFDM_CE_TOP_COMM_MB__A 0x2C10002 --#define OFDM_CE_TOP_COMM_MB__W 4 --#define OFDM_CE_TOP_COMM_MB__M 0xF --#define OFDM_CE_TOP_COMM_MB__PRE 0x0 --#define OFDM_CE_TOP_COMM_MB_CTL__B 0 --#define OFDM_CE_TOP_COMM_MB_CTL__W 1 --#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1 --#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0 --#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0 --#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1 --#define OFDM_CE_TOP_COMM_MB_OBS__B 1 --#define OFDM_CE_TOP_COMM_MB_OBS__W 1 --#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2 --#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0 --#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0 --#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2 --#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2 --#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2 --#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC --#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0 --#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0 --#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4 --#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8 --#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC -- --#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004 --#define OFDM_CE_TOP_COMM_INT_REQ__W 1 --#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1 --#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005 --#define OFDM_CE_TOP_COMM_INT_STA__W 3 --#define OFDM_CE_TOP_COMM_INT_STA__M 0x7 --#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0 --#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1 --#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1 --#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1 --#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1 --#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2 --#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2 --#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1 --#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4 --#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0 -- --#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006 --#define OFDM_CE_TOP_COMM_INT_MSK__W 3 --#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7 --#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4 --#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0 -- --#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007 --#define OFDM_CE_TOP_COMM_INT_STM__W 3 --#define OFDM_CE_TOP_COMM_INT_STM__M 0x7 --#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0 --#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1 --#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1 --#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1 --#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1 --#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2 --#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0 --#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2 --#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1 --#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4 --#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0 -- -- --#define OFDM_CE_TOP_MODE_2K__A 0x2C10010 --#define OFDM_CE_TOP_MODE_2K__W 1 --#define OFDM_CE_TOP_MODE_2K__M 0x1 --#define OFDM_CE_TOP_MODE_2K__PRE 0x0 -- --#define OFDM_CE_TOP_TAPSET__A 0x2C10011 --#define OFDM_CE_TOP_TAPSET__W 4 --#define OFDM_CE_TOP_TAPSET__M 0xF --#define OFDM_CE_TOP_TAPSET__PRE 0x1 --#define OFDM_CE_TOP_AVG_POW__A 0x2C10012 --#define OFDM_CE_TOP_AVG_POW__W 8 --#define OFDM_CE_TOP_AVG_POW__M 0xFF --#define OFDM_CE_TOP_AVG_POW__PRE 0x65 --#define OFDM_CE_TOP_MAX_POW__A 0x2C10013 --#define OFDM_CE_TOP_MAX_POW__W 8 --#define OFDM_CE_TOP_MAX_POW__M 0xFF --#define OFDM_CE_TOP_MAX_POW__PRE 0x80 --#define OFDM_CE_TOP_ATT__A 0x2C10014 --#define OFDM_CE_TOP_ATT__W 8 --#define OFDM_CE_TOP_ATT__M 0xFF --#define OFDM_CE_TOP_ATT__PRE 0x70 --#define OFDM_CE_TOP_NRED__A 0x2C10015 --#define OFDM_CE_TOP_NRED__W 6 --#define OFDM_CE_TOP_NRED__M 0x3F --#define OFDM_CE_TOP_NRED__PRE 0x9 -- --#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020 --#define OFDM_CE_TOP_PU_SIGN__W 1 --#define OFDM_CE_TOP_PU_SIGN__M 0x1 --#define OFDM_CE_TOP_PU_SIGN__PRE 0x0 -- --#define OFDM_CE_TOP_PU_MIX__A 0x2C10021 --#define OFDM_CE_TOP_PU_MIX__W 1 --#define OFDM_CE_TOP_PU_MIX__M 0x1 --#define OFDM_CE_TOP_PU_MIX__PRE 0x0 --#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030 --#define OFDM_CE_TOP_PB_PILOT_REQ__W 15 --#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF --#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0 --#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12 --#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3 --#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 --#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0 --#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0 --#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12 --#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF --#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0 -- -- --#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031 --#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1 --#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1 --#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0 -- --#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032 --#define OFDM_CE_TOP_PB_FREEZE__W 1 --#define OFDM_CE_TOP_PB_FREEZE__M 0x1 --#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0 -- --#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038 --#define OFDM_CE_TOP_PB_PILOT_EXP__W 4 --#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF --#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0 -- --#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039 --#define OFDM_CE_TOP_PB_PILOT_REAL__W 10 --#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF --#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0 -- --#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A --#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10 --#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF --#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0 -- --#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B --#define OFDM_CE_TOP_PB_SMBNR__W 5 --#define OFDM_CE_TOP_PB_SMBNR__M 0x1F --#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0 -- --#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040 --#define OFDM_CE_TOP_NE_PILOT_REQ__W 12 --#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF --#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 --#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0 -- -- --#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042 --#define OFDM_CE_TOP_NE_PILOT_DATA__W 10 --#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF --#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0 --#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043 --#define OFDM_CE_TOP_NE_ERR_SELECT__W 5 --#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F --#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7 -- --#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4 --#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1 --#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10 --#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0 -- --#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3 --#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1 --#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8 --#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0 -- --#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2 --#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1 --#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4 --#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4 -- --#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1 --#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1 --#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2 --#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2 -- --#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0 --#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1 --#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1 --#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1 -- -- --#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044 --#define OFDM_CE_TOP_NE_TD_CAL__W 9 --#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF --#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8 -- --#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045 --#define OFDM_CE_TOP_NE_FD_CAL__W 9 --#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF --#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9 -- --#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046 --#define OFDM_CE_TOP_NE_MIXAVG__W 3 --#define OFDM_CE_TOP_NE_MIXAVG__M 0x7 --#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6 -- --#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047 --#define OFDM_CE_TOP_NE_NUPD_OFS__W 4 --#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF --#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4 --#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048 --#define OFDM_CE_TOP_NE_TD_POW__W 15 --#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF --#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0 -- --#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10 --#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5 --#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00 --#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0 -- --#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0 --#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10 --#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF --#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0 -- --#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049 --#define OFDM_CE_TOP_NE_FD_POW__W 15 --#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF --#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0 -- --#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10 --#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5 --#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00 --#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0 -- --#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0 --#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10 --#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF --#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0 -- -- --#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A --#define OFDM_CE_TOP_NE_NEXP_AVG__W 8 --#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF --#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0 -- --#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B --#define OFDM_CE_TOP_NE_OFFSET__W 9 --#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF --#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0 -- --#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C --#define OFDM_CE_TOP_NE_NUPD_TRH__W 5 --#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F --#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14 -- --#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050 --#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8 --#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF --#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0 -- --#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051 --#define OFDM_CE_TOP_PE_TIMESHIFT__W 14 --#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF --#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0 -- --#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052 --#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16 --#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF --#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0 -- --#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053 --#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16 --#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF --#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0 -- --#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054 --#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16 --#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF --#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0 -- --#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055 --#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16 --#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF --#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0 -- --#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056 --#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16 --#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF --#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0 -- --#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057 --#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16 --#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF --#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0 -- --#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058 --#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16 --#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF --#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0 -- --#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059 --#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16 --#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF --#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0 -- --#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A --#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5 --#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F --#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0 -- --#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B --#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5 --#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F --#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0 -- --#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060 --#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1 --#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1 --#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0 -- --#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061 --#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1 --#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1 --#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064 --#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10 --#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF --#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100 -- --#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065 --#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1 --#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1 --#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066 --#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5 --#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F --#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE -- --#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067 --#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10 --#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF --#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068 --#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10 --#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF --#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069 --#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1 --#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1 --#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A --#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5 --#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F --#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA -- --#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B --#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10 --#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF --#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0 --#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C --#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15 --#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF --#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0 -- --#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10 --#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5 --#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 --#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0 -- --#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0 --#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10 --#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF --#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0 -- --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15 --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0 -- --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0 -- --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF --#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15 --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10 --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5 --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0 --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10 --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF --#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15 --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10 --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5 --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0 -- --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0 --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10 --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF --#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0 -- -- --#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072 --#define OFDM_CE_TOP_TI_SYM_CNT__W 6 --#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F --#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20 -- --#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073 --#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1 --#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1 --#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1 -- --#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074 --#define OFDM_CE_TOP_TI_SHIFT__W 2 --#define OFDM_CE_TOP_TI_SHIFT__M 0x3 --#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0 -- --#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075 --#define OFDM_CE_TOP_TI_SLOW__W 1 --#define OFDM_CE_TOP_TI_SLOW__M 0x1 --#define OFDM_CE_TOP_TI_SLOW__PRE 0x1 -- --#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076 --#define OFDM_CE_TOP_TI_MGAIN__W 8 --#define OFDM_CE_TOP_TI_MGAIN__M 0xFF --#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0 -- --#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077 --#define OFDM_CE_TOP_TI_ACCU1__W 8 --#define OFDM_CE_TOP_TI_ACCU1__M 0xFF --#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0 -- --#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0 --#define OFDM_CE_TOP_NI_PER_LEFT__W 5 --#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F --#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE -- --#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1 --#define OFDM_CE_TOP_NI_PER_RIGHT__W 5 --#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F --#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7 -- --#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2 --#define OFDM_CE_TOP_NI_POS_LR__W 9 --#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF --#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0 -- --#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090 --#define OFDM_CE_TOP_FI_SHT_INCR__W 9 --#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF --#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E -- --#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091 --#define OFDM_CE_TOP_FI_EXP_NORM__W 4 --#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF --#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC -- --#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092 --#define OFDM_CE_TOP_FI_SUPR_VAL__W 1 --#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1 --#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0 -- --#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0 --#define OFDM_CE_TOP_IR_INPUTSEL__W 1 --#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1 --#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0 -- --#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1 --#define OFDM_CE_TOP_IR_STARTPOS__W 8 --#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF --#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0 -- --#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2 --#define OFDM_CE_TOP_IR_NEXP_THRES__W 8 --#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF --#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF -- --#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3 --#define OFDM_CE_TOP_IR_LENGTH__W 4 --#define OFDM_CE_TOP_IR_LENGTH__M 0xF --#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9 -- --#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4 --#define OFDM_CE_TOP_IR_FREQ__W 11 --#define OFDM_CE_TOP_IR_FREQ__M 0x7FF --#define OFDM_CE_TOP_IR_FREQ__PRE 0x0 -- --#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5 --#define OFDM_CE_TOP_IR_FREQINC__W 11 --#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF --#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4 -- --#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6 --#define OFDM_CE_TOP_IR_KAISINC__W 15 --#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF --#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100 -- --#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7 --#define OFDM_CE_TOP_IR_CTL__W 3 --#define OFDM_CE_TOP_IR_CTL__M 0x7 --#define OFDM_CE_TOP_IR_CTL__PRE 0x0 -- --#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8 --#define OFDM_CE_TOP_IR_REAL__W 16 --#define OFDM_CE_TOP_IR_REAL__M 0xFFFF --#define OFDM_CE_TOP_IR_REAL__PRE 0x0 -- --#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9 --#define OFDM_CE_TOP_IR_IMAG__W 16 --#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF --#define OFDM_CE_TOP_IR_IMAG__PRE 0x0 -- --#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA --#define OFDM_CE_TOP_IR_INDEX__W 12 --#define OFDM_CE_TOP_IR_INDEX__M 0xFFF --#define OFDM_CE_TOP_IR_INDEX__PRE 0x0 -- -- -- --#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000 --#define OFDM_CE_FR_COMM_EXEC__W 3 --#define OFDM_CE_FR_COMM_EXEC__M 0x7 --#define OFDM_CE_FR_COMM_EXEC__PRE 0x0 --#define OFDM_CE_FR_COMM_EXEC_STOP 0x0 --#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1 --#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2 --#define OFDM_CE_FR_COMM_EXEC_STEP 0x3 -- -- --#define OFDM_CE_FR_TREAL00__A 0x2C20010 --#define OFDM_CE_FR_TREAL00__W 11 --#define OFDM_CE_FR_TREAL00__M 0x7FF --#define OFDM_CE_FR_TREAL00__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG00__A 0x2C20011 --#define OFDM_CE_FR_TIMAG00__W 11 --#define OFDM_CE_FR_TIMAG00__M 0x7FF --#define OFDM_CE_FR_TIMAG00__PRE 0x0 -- --#define OFDM_CE_FR_TREAL01__A 0x2C20012 --#define OFDM_CE_FR_TREAL01__W 11 --#define OFDM_CE_FR_TREAL01__M 0x7FF --#define OFDM_CE_FR_TREAL01__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG01__A 0x2C20013 --#define OFDM_CE_FR_TIMAG01__W 11 --#define OFDM_CE_FR_TIMAG01__M 0x7FF --#define OFDM_CE_FR_TIMAG01__PRE 0x0 -- --#define OFDM_CE_FR_TREAL02__A 0x2C20014 --#define OFDM_CE_FR_TREAL02__W 11 --#define OFDM_CE_FR_TREAL02__M 0x7FF --#define OFDM_CE_FR_TREAL02__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG02__A 0x2C20015 --#define OFDM_CE_FR_TIMAG02__W 11 --#define OFDM_CE_FR_TIMAG02__M 0x7FF --#define OFDM_CE_FR_TIMAG02__PRE 0x0 -- --#define OFDM_CE_FR_TREAL03__A 0x2C20016 --#define OFDM_CE_FR_TREAL03__W 11 --#define OFDM_CE_FR_TREAL03__M 0x7FF --#define OFDM_CE_FR_TREAL03__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG03__A 0x2C20017 --#define OFDM_CE_FR_TIMAG03__W 11 --#define OFDM_CE_FR_TIMAG03__M 0x7FF --#define OFDM_CE_FR_TIMAG03__PRE 0x0 -- --#define OFDM_CE_FR_TREAL04__A 0x2C20018 --#define OFDM_CE_FR_TREAL04__W 11 --#define OFDM_CE_FR_TREAL04__M 0x7FF --#define OFDM_CE_FR_TREAL04__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG04__A 0x2C20019 --#define OFDM_CE_FR_TIMAG04__W 11 --#define OFDM_CE_FR_TIMAG04__M 0x7FF --#define OFDM_CE_FR_TIMAG04__PRE 0x0 -- --#define OFDM_CE_FR_TREAL05__A 0x2C2001A --#define OFDM_CE_FR_TREAL05__W 11 --#define OFDM_CE_FR_TREAL05__M 0x7FF --#define OFDM_CE_FR_TREAL05__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG05__A 0x2C2001B --#define OFDM_CE_FR_TIMAG05__W 11 --#define OFDM_CE_FR_TIMAG05__M 0x7FF --#define OFDM_CE_FR_TIMAG05__PRE 0x0 -- --#define OFDM_CE_FR_TREAL06__A 0x2C2001C --#define OFDM_CE_FR_TREAL06__W 11 --#define OFDM_CE_FR_TREAL06__M 0x7FF --#define OFDM_CE_FR_TREAL06__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG06__A 0x2C2001D --#define OFDM_CE_FR_TIMAG06__W 11 --#define OFDM_CE_FR_TIMAG06__M 0x7FF --#define OFDM_CE_FR_TIMAG06__PRE 0x0 -- --#define OFDM_CE_FR_TREAL07__A 0x2C2001E --#define OFDM_CE_FR_TREAL07__W 11 --#define OFDM_CE_FR_TREAL07__M 0x7FF --#define OFDM_CE_FR_TREAL07__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG07__A 0x2C2001F --#define OFDM_CE_FR_TIMAG07__W 11 --#define OFDM_CE_FR_TIMAG07__M 0x7FF --#define OFDM_CE_FR_TIMAG07__PRE 0x0 -- --#define OFDM_CE_FR_TREAL08__A 0x2C20020 --#define OFDM_CE_FR_TREAL08__W 11 --#define OFDM_CE_FR_TREAL08__M 0x7FF --#define OFDM_CE_FR_TREAL08__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG08__A 0x2C20021 --#define OFDM_CE_FR_TIMAG08__W 11 --#define OFDM_CE_FR_TIMAG08__M 0x7FF --#define OFDM_CE_FR_TIMAG08__PRE 0x0 -- --#define OFDM_CE_FR_TREAL09__A 0x2C20022 --#define OFDM_CE_FR_TREAL09__W 11 --#define OFDM_CE_FR_TREAL09__M 0x7FF --#define OFDM_CE_FR_TREAL09__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG09__A 0x2C20023 --#define OFDM_CE_FR_TIMAG09__W 11 --#define OFDM_CE_FR_TIMAG09__M 0x7FF --#define OFDM_CE_FR_TIMAG09__PRE 0x0 -- --#define OFDM_CE_FR_TREAL10__A 0x2C20024 --#define OFDM_CE_FR_TREAL10__W 11 --#define OFDM_CE_FR_TREAL10__M 0x7FF --#define OFDM_CE_FR_TREAL10__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG10__A 0x2C20025 --#define OFDM_CE_FR_TIMAG10__W 11 --#define OFDM_CE_FR_TIMAG10__M 0x7FF --#define OFDM_CE_FR_TIMAG10__PRE 0x0 -- --#define OFDM_CE_FR_TREAL11__A 0x2C20026 --#define OFDM_CE_FR_TREAL11__W 11 --#define OFDM_CE_FR_TREAL11__M 0x7FF --#define OFDM_CE_FR_TREAL11__PRE 0x52 -- --#define OFDM_CE_FR_TIMAG11__A 0x2C20027 --#define OFDM_CE_FR_TIMAG11__W 11 --#define OFDM_CE_FR_TIMAG11__M 0x7FF --#define OFDM_CE_FR_TIMAG11__PRE 0x0 -- --#define OFDM_CE_FR_MID_TAP__A 0x2C20028 --#define OFDM_CE_FR_MID_TAP__W 11 --#define OFDM_CE_FR_MID_TAP__M 0x7FF --#define OFDM_CE_FR_MID_TAP__PRE 0x51 -- --#define OFDM_CE_FR_SQS_G00__A 0x2C20029 --#define OFDM_CE_FR_SQS_G00__W 8 --#define OFDM_CE_FR_SQS_G00__M 0xFF --#define OFDM_CE_FR_SQS_G00__PRE 0xB -- --#define OFDM_CE_FR_SQS_G01__A 0x2C2002A --#define OFDM_CE_FR_SQS_G01__W 8 --#define OFDM_CE_FR_SQS_G01__M 0xFF --#define OFDM_CE_FR_SQS_G01__PRE 0xB -- --#define OFDM_CE_FR_SQS_G02__A 0x2C2002B --#define OFDM_CE_FR_SQS_G02__W 8 --#define OFDM_CE_FR_SQS_G02__M 0xFF --#define OFDM_CE_FR_SQS_G02__PRE 0xB -- --#define OFDM_CE_FR_SQS_G03__A 0x2C2002C --#define OFDM_CE_FR_SQS_G03__W 8 --#define OFDM_CE_FR_SQS_G03__M 0xFF --#define OFDM_CE_FR_SQS_G03__PRE 0xB -- --#define OFDM_CE_FR_SQS_G04__A 0x2C2002D --#define OFDM_CE_FR_SQS_G04__W 8 --#define OFDM_CE_FR_SQS_G04__M 0xFF --#define OFDM_CE_FR_SQS_G04__PRE 0xB -- --#define OFDM_CE_FR_SQS_G05__A 0x2C2002E --#define OFDM_CE_FR_SQS_G05__W 8 --#define OFDM_CE_FR_SQS_G05__M 0xFF --#define OFDM_CE_FR_SQS_G05__PRE 0xB -- --#define OFDM_CE_FR_SQS_G06__A 0x2C2002F --#define OFDM_CE_FR_SQS_G06__W 8 --#define OFDM_CE_FR_SQS_G06__M 0xFF --#define OFDM_CE_FR_SQS_G06__PRE 0xB -- --#define OFDM_CE_FR_SQS_G07__A 0x2C20030 --#define OFDM_CE_FR_SQS_G07__W 8 --#define OFDM_CE_FR_SQS_G07__M 0xFF --#define OFDM_CE_FR_SQS_G07__PRE 0xB -- --#define OFDM_CE_FR_SQS_G08__A 0x2C20031 --#define OFDM_CE_FR_SQS_G08__W 8 --#define OFDM_CE_FR_SQS_G08__M 0xFF --#define OFDM_CE_FR_SQS_G08__PRE 0xB -- --#define OFDM_CE_FR_SQS_G09__A 0x2C20032 --#define OFDM_CE_FR_SQS_G09__W 8 --#define OFDM_CE_FR_SQS_G09__M 0xFF --#define OFDM_CE_FR_SQS_G09__PRE 0xB -- --#define OFDM_CE_FR_SQS_G10__A 0x2C20033 --#define OFDM_CE_FR_SQS_G10__W 8 --#define OFDM_CE_FR_SQS_G10__M 0xFF --#define OFDM_CE_FR_SQS_G10__PRE 0xB -- --#define OFDM_CE_FR_SQS_G11__A 0x2C20034 --#define OFDM_CE_FR_SQS_G11__W 8 --#define OFDM_CE_FR_SQS_G11__M 0xFF --#define OFDM_CE_FR_SQS_G11__PRE 0xB -- --#define OFDM_CE_FR_SQS_G12__A 0x2C20035 --#define OFDM_CE_FR_SQS_G12__W 8 --#define OFDM_CE_FR_SQS_G12__M 0xFF --#define OFDM_CE_FR_SQS_G12__PRE 0x5 -- --#define OFDM_CE_FR_RIO_G00__A 0x2C20036 --#define OFDM_CE_FR_RIO_G00__W 9 --#define OFDM_CE_FR_RIO_G00__M 0x1FF --#define OFDM_CE_FR_RIO_G00__PRE 0x1FF -- --#define OFDM_CE_FR_RIO_G01__A 0x2C20037 --#define OFDM_CE_FR_RIO_G01__W 9 --#define OFDM_CE_FR_RIO_G01__M 0x1FF --#define OFDM_CE_FR_RIO_G01__PRE 0x190 -- --#define OFDM_CE_FR_RIO_G02__A 0x2C20038 --#define OFDM_CE_FR_RIO_G02__W 9 --#define OFDM_CE_FR_RIO_G02__M 0x1FF --#define OFDM_CE_FR_RIO_G02__PRE 0x10B -- --#define OFDM_CE_FR_RIO_G03__A 0x2C20039 --#define OFDM_CE_FR_RIO_G03__W 9 --#define OFDM_CE_FR_RIO_G03__M 0x1FF --#define OFDM_CE_FR_RIO_G03__PRE 0xC8 -- --#define OFDM_CE_FR_RIO_G04__A 0x2C2003A --#define OFDM_CE_FR_RIO_G04__W 9 --#define OFDM_CE_FR_RIO_G04__M 0x1FF --#define OFDM_CE_FR_RIO_G04__PRE 0xA0 -- --#define OFDM_CE_FR_RIO_G05__A 0x2C2003B --#define OFDM_CE_FR_RIO_G05__W 9 --#define OFDM_CE_FR_RIO_G05__M 0x1FF --#define OFDM_CE_FR_RIO_G05__PRE 0x85 -- --#define OFDM_CE_FR_RIO_G06__A 0x2C2003C --#define OFDM_CE_FR_RIO_G06__W 9 --#define OFDM_CE_FR_RIO_G06__M 0x1FF --#define OFDM_CE_FR_RIO_G06__PRE 0x72 -- --#define OFDM_CE_FR_RIO_G07__A 0x2C2003D --#define OFDM_CE_FR_RIO_G07__W 9 --#define OFDM_CE_FR_RIO_G07__M 0x1FF --#define OFDM_CE_FR_RIO_G07__PRE 0x64 -- --#define OFDM_CE_FR_RIO_G08__A 0x2C2003E --#define OFDM_CE_FR_RIO_G08__W 9 --#define OFDM_CE_FR_RIO_G08__M 0x1FF --#define OFDM_CE_FR_RIO_G08__PRE 0x59 -- --#define OFDM_CE_FR_RIO_G09__A 0x2C2003F --#define OFDM_CE_FR_RIO_G09__W 9 --#define OFDM_CE_FR_RIO_G09__M 0x1FF --#define OFDM_CE_FR_RIO_G09__PRE 0x50 -- --#define OFDM_CE_FR_RIO_G10__A 0x2C20040 --#define OFDM_CE_FR_RIO_G10__W 9 --#define OFDM_CE_FR_RIO_G10__M 0x1FF --#define OFDM_CE_FR_RIO_G10__PRE 0x49 --#define OFDM_CE_FR_MODE__A 0x2C20041 --#define OFDM_CE_FR_MODE__W 9 --#define OFDM_CE_FR_MODE__M 0x1FF --#define OFDM_CE_FR_MODE__PRE 0xDE -- --#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0 --#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1 --#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1 --#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0 -- --#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1 --#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1 --#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2 --#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2 -- --#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2 --#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1 --#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4 --#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4 -- --#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3 --#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1 --#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8 --#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8 -- --#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4 --#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1 --#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10 --#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10 -- --#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5 --#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1 --#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20 --#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0 -- --#define OFDM_CE_FR_MODE_MID_MODE__B 6 --#define OFDM_CE_FR_MODE_MID_MODE__W 1 --#define OFDM_CE_FR_MODE_MID_MODE__M 0x40 --#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40 -- --#define OFDM_CE_FR_MODE_NOISE_MODE__B 7 --#define OFDM_CE_FR_MODE_NOISE_MODE__W 1 --#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80 --#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80 -- --#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8 --#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1 --#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100 --#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0 -- -- --#define OFDM_CE_FR_SQS_TRH__A 0x2C20042 --#define OFDM_CE_FR_SQS_TRH__W 8 --#define OFDM_CE_FR_SQS_TRH__M 0xFF --#define OFDM_CE_FR_SQS_TRH__PRE 0x80 -- --#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043 --#define OFDM_CE_FR_RIO_GAIN__W 3 --#define OFDM_CE_FR_RIO_GAIN__M 0x7 --#define OFDM_CE_FR_RIO_GAIN__PRE 0x7 --#define OFDM_CE_FR_BYPASS__A 0x2C20044 --#define OFDM_CE_FR_BYPASS__W 10 --#define OFDM_CE_FR_BYPASS__M 0x3FF --#define OFDM_CE_FR_BYPASS__PRE 0x13B -- --#define OFDM_CE_FR_BYPASS_RUN_IN__B 0 --#define OFDM_CE_FR_BYPASS_RUN_IN__W 4 --#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF --#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB -- --#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4 --#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5 --#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 --#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130 -- --#define OFDM_CE_FR_BYPASS_TOTAL__B 9 --#define OFDM_CE_FR_BYPASS_TOTAL__W 1 --#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200 --#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0 -- -- --#define OFDM_CE_FR_PM_SET__A 0x2C20045 --#define OFDM_CE_FR_PM_SET__W 4 --#define OFDM_CE_FR_PM_SET__M 0xF --#define OFDM_CE_FR_PM_SET__PRE 0xD -- --#define OFDM_CE_FR_ERR_SH__A 0x2C20046 --#define OFDM_CE_FR_ERR_SH__W 4 --#define OFDM_CE_FR_ERR_SH__M 0xF --#define OFDM_CE_FR_ERR_SH__PRE 0x4 -- --#define OFDM_CE_FR_MAN_SH__A 0x2C20047 --#define OFDM_CE_FR_MAN_SH__W 4 --#define OFDM_CE_FR_MAN_SH__M 0xF --#define OFDM_CE_FR_MAN_SH__PRE 0x7 -- --#define OFDM_CE_FR_TAP_SH__A 0x2C20048 --#define OFDM_CE_FR_TAP_SH__W 3 --#define OFDM_CE_FR_TAP_SH__M 0x7 --#define OFDM_CE_FR_TAP_SH__PRE 0x3 -- --#define OFDM_CE_FR_CLIP__A 0x2C20049 --#define OFDM_CE_FR_CLIP__W 9 --#define OFDM_CE_FR_CLIP__M 0x1FF --#define OFDM_CE_FR_CLIP__PRE 0x49 -- --#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A --#define OFDM_CE_FR_LEAK_UPD__W 3 --#define OFDM_CE_FR_LEAK_UPD__M 0x7 --#define OFDM_CE_FR_LEAK_UPD__PRE 0x0 -- --#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B --#define OFDM_CE_FR_LEAK_SH__W 3 --#define OFDM_CE_FR_LEAK_SH__M 0x7 --#define OFDM_CE_FR_LEAK_SH__PRE 0x1 -- -- -- --#define OFDM_CE_NE_RAM__A 0x2C30000 -- -- -- --#define OFDM_CE_PB_RAM__A 0x2C40000 -- -- -- -- -- --#define OFDM_CP_COMM_EXEC__A 0x2800000 --#define OFDM_CP_COMM_EXEC__W 3 --#define OFDM_CP_COMM_EXEC__M 0x7 --#define OFDM_CP_COMM_EXEC__PRE 0x0 --#define OFDM_CP_COMM_EXEC_STOP 0x0 --#define OFDM_CP_COMM_EXEC_ACTIVE 0x1 --#define OFDM_CP_COMM_EXEC_HOLD 0x2 --#define OFDM_CP_COMM_EXEC_STEP 0x3 --#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4 --#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6 -- --#define OFDM_CP_COMM_STATE__A 0x2800001 --#define OFDM_CP_COMM_STATE__W 16 --#define OFDM_CP_COMM_STATE__M 0xFFFF --#define OFDM_CP_COMM_STATE__PRE 0x0 --#define OFDM_CP_COMM_MB__A 0x2800002 --#define OFDM_CP_COMM_MB__W 16 --#define OFDM_CP_COMM_MB__M 0xFFFF --#define OFDM_CP_COMM_MB__PRE 0x0 --#define OFDM_CP_COMM_INT_REQ__A 0x2800004 --#define OFDM_CP_COMM_INT_REQ__W 16 --#define OFDM_CP_COMM_INT_REQ__M 0xFFFF --#define OFDM_CP_COMM_INT_REQ__PRE 0x0 --#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1 --#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1 --#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2 --#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0 -- --#define OFDM_CP_COMM_INT_STA__A 0x2800005 --#define OFDM_CP_COMM_INT_STA__W 16 --#define OFDM_CP_COMM_INT_STA__M 0xFFFF --#define OFDM_CP_COMM_INT_STA__PRE 0x0 --#define OFDM_CP_COMM_INT_MSK__A 0x2800006 --#define OFDM_CP_COMM_INT_MSK__W 16 --#define OFDM_CP_COMM_INT_MSK__M 0xFFFF --#define OFDM_CP_COMM_INT_MSK__PRE 0x0 --#define OFDM_CP_COMM_INT_STM__A 0x2800007 --#define OFDM_CP_COMM_INT_STM__W 16 --#define OFDM_CP_COMM_INT_STM__M 0xFFFF --#define OFDM_CP_COMM_INT_STM__PRE 0x0 --#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0 --#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16 --#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF --#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0 -- -- -- --#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000 --#define OFDM_CP_TOP_COMM_EXEC__W 3 --#define OFDM_CP_TOP_COMM_EXEC__M 0x7 --#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0 --#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0 --#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1 --#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2 --#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3 -- --#define OFDM_CP_TOP_COMM_MB__A 0x2810002 --#define OFDM_CP_TOP_COMM_MB__W 3 --#define OFDM_CP_TOP_COMM_MB__M 0x7 --#define OFDM_CP_TOP_COMM_MB__PRE 0x0 --#define OFDM_CP_TOP_COMM_MB_CTL__B 0 --#define OFDM_CP_TOP_COMM_MB_CTL__W 1 --#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1 --#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0 --#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0 --#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1 --#define OFDM_CP_TOP_COMM_MB_OBS__B 1 --#define OFDM_CP_TOP_COMM_MB_OBS__W 1 --#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2 --#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0 --#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0 --#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2 --#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2 --#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1 --#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4 --#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0 --#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0 --#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4 -- --#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004 --#define OFDM_CP_TOP_COMM_INT_REQ__W 1 --#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1 --#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0 --#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005 --#define OFDM_CP_TOP_COMM_INT_STA__W 1 --#define OFDM_CP_TOP_COMM_INT_STA__M 0x1 --#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0 --#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0 --#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1 --#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1 --#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0 -- --#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006 --#define OFDM_CP_TOP_COMM_INT_MSK__W 1 --#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1 --#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0 --#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0 --#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1 --#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1 --#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0 -- --#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007 --#define OFDM_CP_TOP_COMM_INT_STM__W 1 --#define OFDM_CP_TOP_COMM_INT_STM__M 0x1 --#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0 --#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0 --#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1 --#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1 --#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0 -- -- --#define OFDM_CP_TOP_MODE_2K__A 0x2810010 --#define OFDM_CP_TOP_MODE_2K__W 1 --#define OFDM_CP_TOP_MODE_2K__M 0x1 --#define OFDM_CP_TOP_MODE_2K__PRE 0x0 -- --#define OFDM_CP_TOP_INTERVAL__A 0x2810011 --#define OFDM_CP_TOP_INTERVAL__W 4 --#define OFDM_CP_TOP_INTERVAL__M 0xF --#define OFDM_CP_TOP_INTERVAL__PRE 0x5 --#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012 --#define OFDM_CP_TOP_DETECT_ENA__W 2 --#define OFDM_CP_TOP_DETECT_ENA__M 0x3 --#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0 -- --#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0 --#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1 --#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1 --#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0 -- --#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1 --#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1 --#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2 --#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0 -- --#define OFDM_CP_TOP_FIX__A 0x2810013 --#define OFDM_CP_TOP_FIX__W 4 --#define OFDM_CP_TOP_FIX__M 0xF --#define OFDM_CP_TOP_FIX__PRE 0xF -- --#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0 --#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1 --#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1 --#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1 --#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0 --#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1 -- --#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1 --#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1 --#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2 --#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2 --#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0 --#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2 -- --#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2 --#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1 --#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4 --#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4 --#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0 --#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4 -- --#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3 --#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1 --#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8 --#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8 --#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0 --#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8 -- --#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021 --#define OFDM_CP_TOP_BR_SMB_NR__W 4 --#define OFDM_CP_TOP_BR_SMB_NR__M 0xF --#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0 -- --#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0 --#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2 --#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3 --#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0 -- --#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2 --#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1 --#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4 --#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0 -- --#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3 --#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1 --#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8 --#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0 -- -- --#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022 --#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2 --#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3 --#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0 -- --#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023 --#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4 --#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF --#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8 -- --#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024 --#define OFDM_CP_TOP_BR_STR_DEL__W 10 --#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF --#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA -- --#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025 --#define OFDM_CP_TOP_BR_EXP_ADJ__W 5 --#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F --#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10 -- --#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030 --#define OFDM_CP_TOP_RT_ANG_INC0__W 16 --#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF --#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0 -- --#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031 --#define OFDM_CP_TOP_RT_ANG_INC1__W 8 --#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF --#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0 -- --#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032 --#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5 --#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F --#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5 -- --#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033 --#define OFDM_CP_TOP_RT_DETECT_TRH__W 2 --#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3 --#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3 -- --#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034 --#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3 --#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7 --#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0 -- --#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035 --#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1 --#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1 --#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0 -- --#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036 --#define OFDM_CP_TOP_RT_SPD_MOD__W 2 --#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3 --#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0 -- --#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037 --#define OFDM_CP_TOP_RT_SPD_SMB__W 2 --#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3 --#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0 --#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038 --#define OFDM_CP_TOP_RT_CPD_MODE__W 3 --#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7 --#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0 -- --#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0 --#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2 --#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3 --#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0 -- --#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2 --#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1 --#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4 --#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0 -- -- --#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039 --#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3 --#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7 --#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0 -- --#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A --#define OFDM_CP_TOP_RT_CPD_BIN__W 5 --#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F --#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0 -- --#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B --#define OFDM_CP_TOP_RT_CPD_MAX__W 4 --#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF --#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0 --#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C --#define OFDM_CP_TOP_RT_SUPR_VAL__W 2 --#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3 --#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0 -- --#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0 --#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1 --#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1 --#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0 -- --#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1 --#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1 --#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2 --#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0 -- -- --#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D --#define OFDM_CP_TOP_RT_EXP_AVE__W 5 --#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F --#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0 -- --#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E --#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5 --#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F --#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3 -- --#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040 --#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8 --#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF --#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0 -- --#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041 --#define OFDM_CP_TOP_AC_AVER_POW__W 8 --#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF --#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F -- --#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042 --#define OFDM_CP_TOP_AC_MAX_POW__W 8 --#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF --#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A -- --#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043 --#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6 --#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F --#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31 -- --#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044 --#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5 --#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F --#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10 -- --#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045 --#define OFDM_CP_TOP_AC_GAIN_MAN__W 16 --#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF --#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0 -- --#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046 --#define OFDM_CP_TOP_AC_GAIN_EXP__W 5 --#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F --#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0 -- --#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047 --#define OFDM_CP_TOP_AC_AMP_MODE__W 2 --#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3 --#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2 --#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0 --#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1 --#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2 -- --#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048 --#define OFDM_CP_TOP_AC_AMP_FIX__W 14 --#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF --#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0 -- --#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0 --#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10 --#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF --#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0 -- --#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10 --#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4 --#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00 --#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0 -- --#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049 --#define OFDM_CP_TOP_AC_AMP_READ__W 14 --#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF --#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0 -- --#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0 --#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10 --#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF --#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0 -- --#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10 --#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4 --#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00 --#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0 -- -- --#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A --#define OFDM_CP_TOP_AC_ANG_MODE__W 2 --#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3 --#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3 --#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0 --#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1 --#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2 --#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3 -- -- --#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B --#define OFDM_CP_TOP_AC_ANG_OFFS__W 16 --#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF --#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0 -- --#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C --#define OFDM_CP_TOP_AC_ANG_READ__W 16 --#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF --#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0 -- --#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060 --#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8 --#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF --#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0 -- --#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061 --#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8 --#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF --#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0 -- --#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062 --#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8 --#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF --#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0 -- --#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063 --#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8 --#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF --#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050 --#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15 --#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF --#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0 --#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051 --#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5 --#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F --#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2 --#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3 --#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C --#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1 --#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1 --#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2 --#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0 --#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1 --#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1 --#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0 -- -- --#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052 --#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15 --#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF --#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0 --#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053 --#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11 --#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF --#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10 --#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1 --#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400 --#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8 --#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2 --#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300 --#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5 --#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3 --#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0 --#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2 --#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3 --#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C --#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1 --#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1 --#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2 --#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0 -- --#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0 --#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1 --#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1 --#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0 -- -- -- --#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000 -- -- -- --#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000 -- -- -- --#define OFDM_CP_DL_0_RAM__A 0x2840000 -- -- -- --#define OFDM_CP_DL_1_RAM__A 0x2850000 -- -- -- --#define OFDM_CP_DL_2_RAM__A 0x2860000 -- -- -- -- -- --#define OFDM_EC_COMM_EXEC__A 0x3400000 --#define OFDM_EC_COMM_EXEC__W 3 --#define OFDM_EC_COMM_EXEC__M 0x7 --#define OFDM_EC_COMM_EXEC__PRE 0x0 --#define OFDM_EC_COMM_EXEC_STOP 0x0 --#define OFDM_EC_COMM_EXEC_ACTIVE 0x1 --#define OFDM_EC_COMM_EXEC_HOLD 0x2 --#define OFDM_EC_COMM_EXEC_STEP 0x3 --#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4 --#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6 -- --#define OFDM_EC_COMM_STATE__A 0x3400001 --#define OFDM_EC_COMM_STATE__W 16 --#define OFDM_EC_COMM_STATE__M 0xFFFF --#define OFDM_EC_COMM_STATE__PRE 0x0 --#define OFDM_EC_COMM_MB__A 0x3400002 --#define OFDM_EC_COMM_MB__W 16 --#define OFDM_EC_COMM_MB__M 0xFFFF --#define OFDM_EC_COMM_MB__PRE 0x0 --#define OFDM_EC_COMM_INT_REQ__A 0x3400004 --#define OFDM_EC_COMM_INT_REQ__W 16 --#define OFDM_EC_COMM_INT_REQ__M 0xFFFF --#define OFDM_EC_COMM_INT_REQ__PRE 0x0 --#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4 --#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1 --#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10 --#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0 --#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5 --#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1 --#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20 --#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0 -- --#define OFDM_EC_COMM_INT_STA__A 0x3400005 --#define OFDM_EC_COMM_INT_STA__W 16 --#define OFDM_EC_COMM_INT_STA__M 0xFFFF --#define OFDM_EC_COMM_INT_STA__PRE 0x0 --#define OFDM_EC_COMM_INT_MSK__A 0x3400006 --#define OFDM_EC_COMM_INT_MSK__W 16 --#define OFDM_EC_COMM_INT_MSK__M 0xFFFF --#define OFDM_EC_COMM_INT_MSK__PRE 0x0 --#define OFDM_EC_COMM_INT_STM__A 0x3400007 --#define OFDM_EC_COMM_INT_STM__W 16 --#define OFDM_EC_COMM_INT_STM__M 0xFFFF --#define OFDM_EC_COMM_INT_STM__PRE 0x0 --#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0 --#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16 --#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF --#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0 -- -- -- --#define OFDM_EC_SB_COMM_EXEC__A 0x3410000 --#define OFDM_EC_SB_COMM_EXEC__W 3 --#define OFDM_EC_SB_COMM_EXEC__M 0x7 --#define OFDM_EC_SB_COMM_EXEC__PRE 0x0 --#define OFDM_EC_SB_COMM_EXEC_STOP 0x0 --#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1 --#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2 --#define OFDM_EC_SB_COMM_EXEC_STEP 0x3 -- --#define OFDM_EC_SB_COMM_STATE__A 0x3410001 --#define OFDM_EC_SB_COMM_STATE__W 4 --#define OFDM_EC_SB_COMM_STATE__M 0xF --#define OFDM_EC_SB_COMM_STATE__PRE 0x0 --#define OFDM_EC_SB_COMM_MB__A 0x3410002 --#define OFDM_EC_SB_COMM_MB__W 2 --#define OFDM_EC_SB_COMM_MB__M 0x3 --#define OFDM_EC_SB_COMM_MB__PRE 0x0 --#define OFDM_EC_SB_COMM_MB_CTL__B 0 --#define OFDM_EC_SB_COMM_MB_CTL__W 1 --#define OFDM_EC_SB_COMM_MB_CTL__M 0x1 --#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0 --#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0 --#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1 --#define OFDM_EC_SB_COMM_MB_OBS__B 1 --#define OFDM_EC_SB_COMM_MB_OBS__W 1 --#define OFDM_EC_SB_COMM_MB_OBS__M 0x2 --#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0 --#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0 --#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2 -- -- --#define OFDM_EC_SB_TR_MODE__A 0x3410010 --#define OFDM_EC_SB_TR_MODE__W 1 --#define OFDM_EC_SB_TR_MODE__M 0x1 --#define OFDM_EC_SB_TR_MODE__PRE 0x0 --#define OFDM_EC_SB_TR_MODE_8K 0x0 --#define OFDM_EC_SB_TR_MODE_2K 0x1 -- -- --#define OFDM_EC_SB_CONST__A 0x3410011 --#define OFDM_EC_SB_CONST__W 2 --#define OFDM_EC_SB_CONST__M 0x3 --#define OFDM_EC_SB_CONST__PRE 0x2 --#define OFDM_EC_SB_CONST_QPSK 0x0 --#define OFDM_EC_SB_CONST_16QAM 0x1 --#define OFDM_EC_SB_CONST_64QAM 0x2 -- -- --#define OFDM_EC_SB_ALPHA__A 0x3410012 --#define OFDM_EC_SB_ALPHA__W 3 --#define OFDM_EC_SB_ALPHA__M 0x7 --#define OFDM_EC_SB_ALPHA__PRE 0x0 --#define OFDM_EC_SB_ALPHA_NH 0x0 --#define OFDM_EC_SB_ALPHA_H1 0x1 --#define OFDM_EC_SB_ALPHA_H2 0x2 --#define OFDM_EC_SB_ALPHA_H4 0x3 -- -- --#define OFDM_EC_SB_PRIOR__A 0x3410013 --#define OFDM_EC_SB_PRIOR__W 1 --#define OFDM_EC_SB_PRIOR__M 0x1 --#define OFDM_EC_SB_PRIOR__PRE 0x0 --#define OFDM_EC_SB_PRIOR_HI 0x0 --#define OFDM_EC_SB_PRIOR_LO 0x1 -- -- --#define OFDM_EC_SB_CSI_HI__A 0x3410014 --#define OFDM_EC_SB_CSI_HI__W 5 --#define OFDM_EC_SB_CSI_HI__M 0x1F --#define OFDM_EC_SB_CSI_HI__PRE 0x18 --#define OFDM_EC_SB_CSI_HI_MAX 0x1F --#define OFDM_EC_SB_CSI_HI_MIN 0x0 --#define OFDM_EC_SB_CSI_HI_TAG 0x0 -- -- --#define OFDM_EC_SB_CSI_LO__A 0x3410015 --#define OFDM_EC_SB_CSI_LO__W 5 --#define OFDM_EC_SB_CSI_LO__M 0x1F --#define OFDM_EC_SB_CSI_LO__PRE 0xC --#define OFDM_EC_SB_CSI_LO_MAX 0x1F --#define OFDM_EC_SB_CSI_LO_MIN 0x0 --#define OFDM_EC_SB_CSI_LO_TAG 0x0 -- -- --#define OFDM_EC_SB_SMB_TGL__A 0x3410016 --#define OFDM_EC_SB_SMB_TGL__W 1 --#define OFDM_EC_SB_SMB_TGL__M 0x1 --#define OFDM_EC_SB_SMB_TGL__PRE 0x1 --#define OFDM_EC_SB_SMB_TGL_OFF 0x0 --#define OFDM_EC_SB_SMB_TGL_ON 0x1 -- -- --#define OFDM_EC_SB_SNR_HI__A 0x3410017 --#define OFDM_EC_SB_SNR_HI__W 7 --#define OFDM_EC_SB_SNR_HI__M 0x7F --#define OFDM_EC_SB_SNR_HI__PRE 0x7F --#define OFDM_EC_SB_SNR_HI_MAX 0x7F --#define OFDM_EC_SB_SNR_HI_MIN 0x0 --#define OFDM_EC_SB_SNR_HI_TAG 0x0 -- -- --#define OFDM_EC_SB_SNR_MID__A 0x3410018 --#define OFDM_EC_SB_SNR_MID__W 7 --#define OFDM_EC_SB_SNR_MID__M 0x7F --#define OFDM_EC_SB_SNR_MID__PRE 0x7F --#define OFDM_EC_SB_SNR_MID_MAX 0x7F --#define OFDM_EC_SB_SNR_MID_MIN 0x0 --#define OFDM_EC_SB_SNR_MID_TAG 0x0 -- -- --#define OFDM_EC_SB_SNR_LO__A 0x3410019 --#define OFDM_EC_SB_SNR_LO__W 7 --#define OFDM_EC_SB_SNR_LO__M 0x7F --#define OFDM_EC_SB_SNR_LO__PRE 0x7F --#define OFDM_EC_SB_SNR_LO_MAX 0x7F --#define OFDM_EC_SB_SNR_LO_MIN 0x0 --#define OFDM_EC_SB_SNR_LO_TAG 0x0 -- -- --#define OFDM_EC_SB_SCALE_MSB__A 0x341001A --#define OFDM_EC_SB_SCALE_MSB__W 6 --#define OFDM_EC_SB_SCALE_MSB__M 0x3F --#define OFDM_EC_SB_SCALE_MSB__PRE 0x30 --#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F -- -- --#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B --#define OFDM_EC_SB_SCALE_BIT2__W 6 --#define OFDM_EC_SB_SCALE_BIT2__M 0x3F --#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC --#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F -- -- --#define OFDM_EC_SB_SCALE_LSB__A 0x341001C --#define OFDM_EC_SB_SCALE_LSB__W 6 --#define OFDM_EC_SB_SCALE_LSB__M 0x3F --#define OFDM_EC_SB_SCALE_LSB__PRE 0x3 --#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F -- -- --#define OFDM_EC_SB_CSI_OFS0__A 0x341001D --#define OFDM_EC_SB_CSI_OFS0__W 4 --#define OFDM_EC_SB_CSI_OFS0__M 0xF --#define OFDM_EC_SB_CSI_OFS0__PRE 0x1 -- --#define OFDM_EC_SB_CSI_OFS1__A 0x341001E --#define OFDM_EC_SB_CSI_OFS1__W 4 --#define OFDM_EC_SB_CSI_OFS1__M 0xF --#define OFDM_EC_SB_CSI_OFS1__PRE 0x1 -- --#define OFDM_EC_SB_CSI_OFS2__A 0x341001F --#define OFDM_EC_SB_CSI_OFS2__W 4 --#define OFDM_EC_SB_CSI_OFS2__M 0xF --#define OFDM_EC_SB_CSI_OFS2__PRE 0x1 -- --#define OFDM_EC_SB_MAX0__A 0x3410020 --#define OFDM_EC_SB_MAX0__W 6 --#define OFDM_EC_SB_MAX0__M 0x3F --#define OFDM_EC_SB_MAX0__PRE 0x3F -- --#define OFDM_EC_SB_MAX1__A 0x3410021 --#define OFDM_EC_SB_MAX1__W 6 --#define OFDM_EC_SB_MAX1__M 0x3F --#define OFDM_EC_SB_MAX1__PRE 0x3F --#define OFDM_EC_SB_MAX1_INIT 0x3F -- -- --#define OFDM_EC_SB_MAX2__A 0x3410022 --#define OFDM_EC_SB_MAX2__W 6 --#define OFDM_EC_SB_MAX2__M 0x3F --#define OFDM_EC_SB_MAX2__PRE 0x3F -- --#define OFDM_EC_SB_CSI_DIS__A 0x3410023 --#define OFDM_EC_SB_CSI_DIS__W 1 --#define OFDM_EC_SB_CSI_DIS__M 0x1 --#define OFDM_EC_SB_CSI_DIS__PRE 0x0 -- -- -- --#define OFDM_EC_VD_COMM_EXEC__A 0x3420000 --#define OFDM_EC_VD_COMM_EXEC__W 3 --#define OFDM_EC_VD_COMM_EXEC__M 0x7 --#define OFDM_EC_VD_COMM_EXEC__PRE 0x0 --#define OFDM_EC_VD_COMM_EXEC_STOP 0x0 --#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1 --#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2 --#define OFDM_EC_VD_COMM_EXEC_STEP 0x3 -- --#define OFDM_EC_VD_COMM_STATE__A 0x3420001 --#define OFDM_EC_VD_COMM_STATE__W 4 --#define OFDM_EC_VD_COMM_STATE__M 0xF --#define OFDM_EC_VD_COMM_STATE__PRE 0x0 --#define OFDM_EC_VD_COMM_MB__A 0x3420002 --#define OFDM_EC_VD_COMM_MB__W 2 --#define OFDM_EC_VD_COMM_MB__M 0x3 --#define OFDM_EC_VD_COMM_MB__PRE 0x0 --#define OFDM_EC_VD_COMM_MB_CTL__B 0 --#define OFDM_EC_VD_COMM_MB_CTL__W 1 --#define OFDM_EC_VD_COMM_MB_CTL__M 0x1 --#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0 --#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0 --#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1 --#define OFDM_EC_VD_COMM_MB_OBS__B 1 --#define OFDM_EC_VD_COMM_MB_OBS__W 1 --#define OFDM_EC_VD_COMM_MB_OBS__M 0x2 --#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0 --#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0 --#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2 -- --#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003 --#define OFDM_EC_VD_COMM_INT_REQ__W 1 --#define OFDM_EC_VD_COMM_INT_REQ__M 0x1 --#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0 --#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005 --#define OFDM_EC_VD_COMM_INT_STA__W 1 --#define OFDM_EC_VD_COMM_INT_STA__M 0x1 --#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0 --#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0 --#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1 --#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1 --#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0 -- --#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006 --#define OFDM_EC_VD_COMM_INT_MSK__W 1 --#define OFDM_EC_VD_COMM_INT_MSK__M 0x1 --#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0 --#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0 --#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1 --#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1 --#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0 -- --#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007 --#define OFDM_EC_VD_COMM_INT_STM__W 1 --#define OFDM_EC_VD_COMM_INT_STM__M 0x1 --#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0 --#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0 --#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1 --#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1 --#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0 -- -- --#define OFDM_EC_VD_FORCE__A 0x3420010 --#define OFDM_EC_VD_FORCE__W 2 --#define OFDM_EC_VD_FORCE__M 0x3 --#define OFDM_EC_VD_FORCE__PRE 0x2 --#define OFDM_EC_VD_FORCE_FREE 0x0 --#define OFDM_EC_VD_FORCE_PROP 0x1 --#define OFDM_EC_VD_FORCE_FORCED 0x2 --#define OFDM_EC_VD_FORCE_FIXED 0x3 -- -- --#define OFDM_EC_VD_SET_CODERATE__A 0x3420011 --#define OFDM_EC_VD_SET_CODERATE__W 3 --#define OFDM_EC_VD_SET_CODERATE__M 0x7 --#define OFDM_EC_VD_SET_CODERATE__PRE 0x1 --#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0 --#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1 --#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2 --#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3 --#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4 -- -- --#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012 --#define OFDM_EC_VD_REQ_SMB_CNT__W 16 --#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF --#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1 -- --#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013 --#define OFDM_EC_VD_REQ_BIT_CNT__W 16 --#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF --#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF -- --#define OFDM_EC_VD_RLK_ENA__A 0x3420014 --#define OFDM_EC_VD_RLK_ENA__W 1 --#define OFDM_EC_VD_RLK_ENA__M 0x1 --#define OFDM_EC_VD_RLK_ENA__PRE 0x1 --#define OFDM_EC_VD_RLK_ENA_OFF 0x0 --#define OFDM_EC_VD_RLK_ENA_ON 0x1 -- -- --#define OFDM_EC_VD_VAL__A 0x3420015 --#define OFDM_EC_VD_VAL__W 2 --#define OFDM_EC_VD_VAL__M 0x3 --#define OFDM_EC_VD_VAL__PRE 0x0 --#define OFDM_EC_VD_VAL_CODE 0x1 --#define OFDM_EC_VD_VAL_CNT 0x2 -- -- --#define OFDM_EC_VD_GET_CODERATE__A 0x3420016 --#define OFDM_EC_VD_GET_CODERATE__W 3 --#define OFDM_EC_VD_GET_CODERATE__M 0x7 --#define OFDM_EC_VD_GET_CODERATE__PRE 0x0 --#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0 --#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1 --#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2 --#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3 --#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4 -- -- --#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 --#define OFDM_EC_VD_ERR_BIT_CNT__W 16 --#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF --#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF -- --#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 --#define OFDM_EC_VD_IN_BIT_CNT__W 16 --#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF --#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0 -- --#define OFDM_EC_VD_STS__A 0x3420019 --#define OFDM_EC_VD_STS__W 1 --#define OFDM_EC_VD_STS__M 0x1 --#define OFDM_EC_VD_STS__PRE 0x0 --#define OFDM_EC_VD_STS_NO_LOCK 0x0 --#define OFDM_EC_VD_STS_IN_LOCK 0x1 -- -- --#define OFDM_EC_VD_RLK_CNT__A 0x342001A --#define OFDM_EC_VD_RLK_CNT__W 16 --#define OFDM_EC_VD_RLK_CNT__M 0xFFFF --#define OFDM_EC_VD_RLK_CNT__PRE 0x0 -- -- -- --#define OFDM_EC_SY_COMM_EXEC__A 0x3430000 --#define OFDM_EC_SY_COMM_EXEC__W 2 --#define OFDM_EC_SY_COMM_EXEC__M 0x3 --#define OFDM_EC_SY_COMM_EXEC__PRE 0x0 --#define OFDM_EC_SY_COMM_EXEC_STOP 0x0 --#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1 --#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2 --#define OFDM_EC_SY_COMM_EXEC_STEP 0x3 -- --#define OFDM_EC_SY_COMM_MB__A 0x3430002 --#define OFDM_EC_SY_COMM_MB__W 2 --#define OFDM_EC_SY_COMM_MB__M 0x3 --#define OFDM_EC_SY_COMM_MB__PRE 0x0 --#define OFDM_EC_SY_COMM_MB_CTL__B 0 --#define OFDM_EC_SY_COMM_MB_CTL__W 1 --#define OFDM_EC_SY_COMM_MB_CTL__M 0x1 --#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0 --#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0 --#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1 --#define OFDM_EC_SY_COMM_MB_OBS__B 1 --#define OFDM_EC_SY_COMM_MB_OBS__W 1 --#define OFDM_EC_SY_COMM_MB_OBS__M 0x2 --#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0 --#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0 --#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2 -- --#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003 --#define OFDM_EC_SY_COMM_INT_REQ__W 1 --#define OFDM_EC_SY_COMM_INT_REQ__M 0x1 --#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0 --#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005 --#define OFDM_EC_SY_COMM_INT_STA__W 3 --#define OFDM_EC_SY_COMM_INT_STA__M 0x7 --#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0 -- --#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0 --#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1 --#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1 --#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 -- --#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1 --#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1 --#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 --#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 -- --#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2 --#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1 --#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 --#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 -- --#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006 --#define OFDM_EC_SY_COMM_INT_MSK__W 3 --#define OFDM_EC_SY_COMM_INT_MSK__M 0x7 --#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0 --#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0 --#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1 --#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 --#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 --#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 --#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 --#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 --#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 --#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 --#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 --#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 --#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 -- --#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007 --#define OFDM_EC_SY_COMM_INT_STM__W 3 --#define OFDM_EC_SY_COMM_INT_STM__M 0x7 --#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0 --#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0 --#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1 --#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1 --#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 --#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1 --#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1 --#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 --#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 --#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 --#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 --#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 --#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 -- --#define OFDM_EC_SY_STATUS__A 0x3430010 --#define OFDM_EC_SY_STATUS__W 2 --#define OFDM_EC_SY_STATUS__M 0x3 --#define OFDM_EC_SY_STATUS__PRE 0x0 --#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0 --#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2 --#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3 --#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0 --#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0 --#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1 --#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2 -- -- --#define OFDM_EC_SY_TIMEOUT__A 0x3430011 --#define OFDM_EC_SY_TIMEOUT__W 16 --#define OFDM_EC_SY_TIMEOUT__M 0xFFFF --#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98 -- --#define OFDM_EC_SY_SYNC_LWM__A 0x3430012 --#define OFDM_EC_SY_SYNC_LWM__W 4 --#define OFDM_EC_SY_SYNC_LWM__M 0xF --#define OFDM_EC_SY_SYNC_LWM__PRE 0x2 -- --#define OFDM_EC_SY_SYNC_AWM__A 0x3430013 --#define OFDM_EC_SY_SYNC_AWM__W 4 --#define OFDM_EC_SY_SYNC_AWM__M 0xF --#define OFDM_EC_SY_SYNC_AWM__PRE 0x3 -- --#define OFDM_EC_SY_SYNC_HWM__A 0x3430014 --#define OFDM_EC_SY_SYNC_HWM__W 4 --#define OFDM_EC_SY_SYNC_HWM__M 0xF --#define OFDM_EC_SY_SYNC_HWM__PRE 0x5 -- --#define OFDM_EC_SY_UNLOCK__A 0x3430015 --#define OFDM_EC_SY_UNLOCK__W 1 --#define OFDM_EC_SY_UNLOCK__M 0x1 --#define OFDM_EC_SY_UNLOCK__PRE 0x0 -- -- -- --#define OFDM_EC_SB_BD0_RAM__A 0x3440000 -- -- -- --#define OFDM_EC_SB_BD1_RAM__A 0x3450000 -- -- -- --#define OFDM_EC_SB_SD_RAM__A 0x3460000 -- -- -- --#define OFDM_EC_VD_RE_RAM__A 0x3470000 -- -- -- --#define OFDM_EC_VD_TB0_RAM__A 0x3480000 -- -- -- --#define OFDM_EC_VD_TB1_RAM__A 0x3490000 -- -- -- --#define OFDM_EC_VD_TB2_RAM__A 0x34A0000 -- -- -- --#define OFDM_EC_VD_TB3_RAM__A 0x34B0000 -- -- -- -- -- --#define OFDM_EQ_COMM_EXEC__A 0x3000000 --#define OFDM_EQ_COMM_EXEC__W 3 --#define OFDM_EQ_COMM_EXEC__M 0x7 --#define OFDM_EQ_COMM_EXEC__PRE 0x0 --#define OFDM_EQ_COMM_EXEC_STOP 0x0 --#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1 --#define OFDM_EQ_COMM_EXEC_HOLD 0x2 --#define OFDM_EQ_COMM_EXEC_STEP 0x3 --#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4 --#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6 -- --#define OFDM_EQ_COMM_STATE__A 0x3000001 --#define OFDM_EQ_COMM_STATE__W 16 --#define OFDM_EQ_COMM_STATE__M 0xFFFF --#define OFDM_EQ_COMM_STATE__PRE 0x0 --#define OFDM_EQ_COMM_MB__A 0x3000002 --#define OFDM_EQ_COMM_MB__W 16 --#define OFDM_EQ_COMM_MB__M 0xFFFF --#define OFDM_EQ_COMM_MB__PRE 0x0 --#define OFDM_EQ_COMM_INT_REQ__A 0x3000004 --#define OFDM_EQ_COMM_INT_REQ__W 16 --#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF --#define OFDM_EQ_COMM_INT_REQ__PRE 0x0 --#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3 --#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1 --#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8 --#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0 -- --#define OFDM_EQ_COMM_INT_STA__A 0x3000005 --#define OFDM_EQ_COMM_INT_STA__W 16 --#define OFDM_EQ_COMM_INT_STA__M 0xFFFF --#define OFDM_EQ_COMM_INT_STA__PRE 0x0 --#define OFDM_EQ_COMM_INT_MSK__A 0x3000006 --#define OFDM_EQ_COMM_INT_MSK__W 16 --#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF --#define OFDM_EQ_COMM_INT_MSK__PRE 0x0 --#define OFDM_EQ_COMM_INT_STM__A 0x3000007 --#define OFDM_EQ_COMM_INT_STM__W 16 --#define OFDM_EQ_COMM_INT_STM__M 0xFFFF --#define OFDM_EQ_COMM_INT_STM__PRE 0x0 --#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0 --#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16 --#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF --#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0 -- -- -- --#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000 --#define OFDM_EQ_TOP_COMM_EXEC__W 3 --#define OFDM_EQ_TOP_COMM_EXEC__M 0x7 --#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0 --#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0 --#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1 --#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2 --#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3 -- --#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001 --#define OFDM_EQ_TOP_COMM_STATE__W 4 --#define OFDM_EQ_TOP_COMM_STATE__M 0xF --#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0 --#define OFDM_EQ_TOP_COMM_MB__A 0x3010002 --#define OFDM_EQ_TOP_COMM_MB__W 6 --#define OFDM_EQ_TOP_COMM_MB__M 0x3F --#define OFDM_EQ_TOP_COMM_MB__PRE 0x0 --#define OFDM_EQ_TOP_COMM_MB_CTL__B 0 --#define OFDM_EQ_TOP_COMM_MB_CTL__W 1 --#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1 --#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0 --#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0 --#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1 --#define OFDM_EQ_TOP_COMM_MB_OBS__B 1 --#define OFDM_EQ_TOP_COMM_MB_OBS__W 1 --#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2 --#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0 --#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0 --#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2 --#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2 --#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2 --#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC --#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0 --#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0 --#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4 --#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20 --#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30 -- --#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004 --#define OFDM_EQ_TOP_COMM_INT_REQ__W 1 --#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1 --#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0 --#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005 --#define OFDM_EQ_TOP_COMM_INT_STA__W 2 --#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3 --#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0 --#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0 --#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1 --#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1 --#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0 --#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1 --#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1 --#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2 --#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0 -- --#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006 --#define OFDM_EQ_TOP_COMM_INT_MSK__W 2 --#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3 --#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0 --#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0 --#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1 --#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1 --#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0 --#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1 --#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1 --#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2 --#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0 -- --#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007 --#define OFDM_EQ_TOP_COMM_INT_STM__W 2 --#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3 --#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0 --#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0 --#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1 --#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1 --#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0 --#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1 --#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1 --#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2 --#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0 -- --#define OFDM_EQ_TOP_IS_MODE__A 0x3010014 --#define OFDM_EQ_TOP_IS_MODE__W 4 --#define OFDM_EQ_TOP_IS_MODE__M 0xF --#define OFDM_EQ_TOP_IS_MODE__PRE 0x0 -- --#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0 --#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1 --#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1 --#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1 -- --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2 -- --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4 -- --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0 --#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8 -- -- --#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015 --#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10 --#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF --#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114 -- --#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016 --#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5 --#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F --#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5 -- --#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017 --#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5 --#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F --#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10 --#define OFDM_EQ_TOP_DV_MODE__A 0x301001E --#define OFDM_EQ_TOP_DV_MODE__W 4 --#define OFDM_EQ_TOP_DV_MODE__M 0xF --#define OFDM_EQ_TOP_DV_MODE__PRE 0xF -- --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1 -- --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0 --#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2 -- --#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2 --#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1 --#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4 --#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4 --#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0 --#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4 -- --#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3 --#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1 --#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8 --#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8 --#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0 --#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8 -- -- --#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F --#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16 --#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF --#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0 --#define OFDM_EQ_TOP_SN_MODE__A 0x3010028 --#define OFDM_EQ_TOP_SN_MODE__W 8 --#define OFDM_EQ_TOP_SN_MODE__M 0xFF --#define OFDM_EQ_TOP_SN_MODE__PRE 0x18 -- --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1 -- --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2 -- --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4 -- --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8 -- --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10 -- --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0 --#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20 -- --#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6 --#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1 --#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40 --#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0 --#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0 --#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40 -- --#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7 --#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1 --#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80 --#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0 --#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0 --#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80 -- -- --#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029 --#define OFDM_EQ_TOP_SN_PFIX__W 8 --#define OFDM_EQ_TOP_SN_PFIX__M 0xFF --#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0 -- --#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A --#define OFDM_EQ_TOP_SN_CEGAIN__W 8 --#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF --#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30 -- --#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B --#define OFDM_EQ_TOP_SN_OFFSET__W 6 --#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F --#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39 -- --#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C --#define OFDM_EQ_TOP_SN_NULLIFY__W 6 --#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F --#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0 --#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D --#define OFDM_EQ_TOP_SN_SQUASH__W 10 --#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF --#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7 -- --#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0 --#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6 --#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F --#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7 -- --#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6 --#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4 --#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0 --#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0 -- --#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032 --#define OFDM_EQ_TOP_RC_SEL_CAR__W 8 --#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF --#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2 --#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0 --#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1 --#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1 --#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1 -- --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1 --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2 --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6 --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2 --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2 --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4 --#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6 -- --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3 --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2 --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18 --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8 --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10 --#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18 -- --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5 --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2 --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60 --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20 --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40 --#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60 -- --#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7 --#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1 --#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80 --#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0 --#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80 -- --#define OFDM_EQ_TOP_RC_STS__A 0x3010033 --#define OFDM_EQ_TOP_RC_STS__W 16 --#define OFDM_EQ_TOP_RC_STS__M 0xFFFF --#define OFDM_EQ_TOP_RC_STS__PRE 0x0 -- --#define OFDM_EQ_TOP_RC_STS_DIFF__B 0 --#define OFDM_EQ_TOP_RC_STS_DIFF__W 11 --#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF --#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0 -- --#define OFDM_EQ_TOP_RC_STS_FIRST__B 11 --#define OFDM_EQ_TOP_RC_STS_FIRST__W 1 --#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800 --#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0 --#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0 --#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800 -- --#define OFDM_EQ_TOP_RC_STS_SELEC__B 12 --#define OFDM_EQ_TOP_RC_STS_SELEC__W 1 --#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000 --#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0 --#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0 --#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000 -- --#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13 --#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1 --#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000 --#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0 --#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0 --#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000 -- --#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14 --#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1 --#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000 --#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0 --#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0 --#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000 -- --#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15 --#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1 --#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000 --#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0 --#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0 --#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000 -- -- --#define OFDM_EQ_TOP_OT_CONST__A 0x3010046 --#define OFDM_EQ_TOP_OT_CONST__W 2 --#define OFDM_EQ_TOP_OT_CONST__M 0x3 --#define OFDM_EQ_TOP_OT_CONST__PRE 0x2 -- --#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047 --#define OFDM_EQ_TOP_OT_ALPHA__W 2 --#define OFDM_EQ_TOP_OT_ALPHA__M 0x3 --#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0 -- --#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048 --#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5 --#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F --#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E -- --#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049 --#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5 --#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F --#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F -- --#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A --#define OFDM_EQ_TOP_OT_CSI_STEP__W 4 --#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF --#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5 -- --#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B --#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8 --#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF --#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5 -- --#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C --#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8 --#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF --#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B -- --#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D --#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7 --#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F --#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0 -- --#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E --#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7 --#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F --#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050 --#define OFDM_EQ_TOP_TD_TPS_INIT__W 1 --#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1 --#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0 --#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1 -- -- --#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051 --#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16 --#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF --#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE --#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11 -- -- --#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052 --#define OFDM_EQ_TOP_TD_TPS_LEN__W 6 --#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F --#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17 --#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F -- -- --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053 --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2 --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3 --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0 --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1 --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2 --#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3 -- -- --#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 --#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 --#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 --#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 --#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 --#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 -- -- --#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055 --#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3 --#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7 --#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0 --#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1 --#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2 --#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3 -- -- --#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3 --#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4 -- -- --#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 --#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 -- -- --#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058 --#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2 --#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3 --#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0 --#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1 --#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2 --#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3 -- -- --#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059 --#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2 --#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3 --#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0 --#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0 --#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1 -- -- --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8 --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8 --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF --#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C --#define OFDM_EQ_TOP_TD_TPS_RSV__W 6 --#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F --#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D --#define OFDM_EQ_TOP_TD_TPS_BCH__W 14 --#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF --#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E --#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16 --#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF --#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F --#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16 --#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF --#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 --#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4 --#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF --#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0 -- --#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 --#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16 --#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF --#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200 -- --#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 --#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10 --#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF --#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F -- -- -- -- -- --#define OFDM_FE_COMM_EXEC__A 0x2000000 --#define OFDM_FE_COMM_EXEC__W 3 --#define OFDM_FE_COMM_EXEC__M 0x7 --#define OFDM_FE_COMM_EXEC__PRE 0x0 --#define OFDM_FE_COMM_EXEC_STOP 0x0 --#define OFDM_FE_COMM_EXEC_ACTIVE 0x1 --#define OFDM_FE_COMM_EXEC_HOLD 0x2 --#define OFDM_FE_COMM_EXEC_STEP 0x3 -- --#define OFDM_FE_COMM_STATE__A 0x2000001 --#define OFDM_FE_COMM_STATE__W 16 --#define OFDM_FE_COMM_STATE__M 0xFFFF --#define OFDM_FE_COMM_STATE__PRE 0x0 --#define OFDM_FE_COMM_MB__A 0x2000002 --#define OFDM_FE_COMM_MB__W 16 --#define OFDM_FE_COMM_MB__M 0xFFFF --#define OFDM_FE_COMM_MB__PRE 0x0 --#define OFDM_FE_COMM_INT_REQ__A 0x2000004 --#define OFDM_FE_COMM_INT_REQ__W 16 --#define OFDM_FE_COMM_INT_REQ__M 0xFFFF --#define OFDM_FE_COMM_INT_REQ__PRE 0x0 --#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0 --#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1 --#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1 --#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0 -- --#define OFDM_FE_COMM_INT_STA__A 0x2000005 --#define OFDM_FE_COMM_INT_STA__W 16 --#define OFDM_FE_COMM_INT_STA__M 0xFFFF --#define OFDM_FE_COMM_INT_STA__PRE 0x0 --#define OFDM_FE_COMM_INT_MSK__A 0x2000006 --#define OFDM_FE_COMM_INT_MSK__W 16 --#define OFDM_FE_COMM_INT_MSK__M 0xFFFF --#define OFDM_FE_COMM_INT_MSK__PRE 0x0 --#define OFDM_FE_COMM_INT_STM__A 0x2000007 --#define OFDM_FE_COMM_INT_STM__W 16 --#define OFDM_FE_COMM_INT_STM__M 0xFFFF --#define OFDM_FE_COMM_INT_STM__PRE 0x0 --#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0 --#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16 --#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF --#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0 -- -- -- --#define OFDM_FE_CU_COMM_EXEC__A 0x2010000 --#define OFDM_FE_CU_COMM_EXEC__W 3 --#define OFDM_FE_CU_COMM_EXEC__M 0x7 --#define OFDM_FE_CU_COMM_EXEC__PRE 0x0 --#define OFDM_FE_CU_COMM_EXEC_STOP 0x0 --#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1 --#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2 --#define OFDM_FE_CU_COMM_EXEC_STEP 0x3 -- --#define OFDM_FE_CU_COMM_STATE__A 0x2010001 --#define OFDM_FE_CU_COMM_STATE__W 4 --#define OFDM_FE_CU_COMM_STATE__M 0xF --#define OFDM_FE_CU_COMM_STATE__PRE 0x0 --#define OFDM_FE_CU_COMM_MB__A 0x2010002 --#define OFDM_FE_CU_COMM_MB__W 2 --#define OFDM_FE_CU_COMM_MB__M 0x3 --#define OFDM_FE_CU_COMM_MB__PRE 0x0 --#define OFDM_FE_CU_COMM_MB_CTL__B 0 --#define OFDM_FE_CU_COMM_MB_CTL__W 1 --#define OFDM_FE_CU_COMM_MB_CTL__M 0x1 --#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0 --#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0 --#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1 --#define OFDM_FE_CU_COMM_MB_OBS__B 1 --#define OFDM_FE_CU_COMM_MB_OBS__W 1 --#define OFDM_FE_CU_COMM_MB_OBS__M 0x2 --#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0 --#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0 --#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2 -- --#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004 --#define OFDM_FE_CU_COMM_INT_REQ__W 1 --#define OFDM_FE_CU_COMM_INT_REQ__M 0x1 --#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005 --#define OFDM_FE_CU_COMM_INT_STA__W 4 --#define OFDM_FE_CU_COMM_INT_STA__M 0xF --#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0 --#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1 --#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1 --#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1 --#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1 --#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2 --#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2 --#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1 --#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4 --#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3 --#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1 --#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8 --#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0 -- --#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006 --#define OFDM_FE_CU_COMM_INT_MSK__W 4 --#define OFDM_FE_CU_COMM_INT_MSK__M 0xF --#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0 --#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1 --#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1 --#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1 --#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1 --#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2 --#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2 --#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1 --#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4 --#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3 --#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1 --#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8 --#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0 -- --#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007 --#define OFDM_FE_CU_COMM_INT_STM__W 4 --#define OFDM_FE_CU_COMM_INT_STM__M 0xF --#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0 --#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1 --#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1 --#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1 --#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1 --#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2 --#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2 --#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1 --#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4 --#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0 --#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3 --#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1 --#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8 --#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0 -- --#define OFDM_FE_CU_MODE__A 0x2010010 --#define OFDM_FE_CU_MODE__W 8 --#define OFDM_FE_CU_MODE__M 0xFF --#define OFDM_FE_CU_MODE__PRE 0x20 -- --#define OFDM_FE_CU_MODE_FFT__B 0 --#define OFDM_FE_CU_MODE_FFT__W 1 --#define OFDM_FE_CU_MODE_FFT__M 0x1 --#define OFDM_FE_CU_MODE_FFT__PRE 0x0 --#define OFDM_FE_CU_MODE_FFT_M8K 0x0 --#define OFDM_FE_CU_MODE_FFT_M2K 0x1 -- --#define OFDM_FE_CU_MODE_COR__B 1 --#define OFDM_FE_CU_MODE_COR__W 1 --#define OFDM_FE_CU_MODE_COR__M 0x2 --#define OFDM_FE_CU_MODE_COR__PRE 0x0 --#define OFDM_FE_CU_MODE_COR_OFF 0x0 --#define OFDM_FE_CU_MODE_COR_ON 0x2 -- --#define OFDM_FE_CU_MODE_IFD__B 2 --#define OFDM_FE_CU_MODE_IFD__W 1 --#define OFDM_FE_CU_MODE_IFD__M 0x4 --#define OFDM_FE_CU_MODE_IFD__PRE 0x0 --#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0 --#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4 -- --#define OFDM_FE_CU_MODE_SEL__B 3 --#define OFDM_FE_CU_MODE_SEL__W 1 --#define OFDM_FE_CU_MODE_SEL__M 0x8 --#define OFDM_FE_CU_MODE_SEL__PRE 0x0 --#define OFDM_FE_CU_MODE_SEL_COR 0x0 --#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8 -- --#define OFDM_FE_CU_MODE_FES__B 4 --#define OFDM_FE_CU_MODE_FES__W 1 --#define OFDM_FE_CU_MODE_FES__M 0x10 --#define OFDM_FE_CU_MODE_FES__PRE 0x0 --#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0 --#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10 --#define OFDM_FE_CU_MODE_AVG__B 5 --#define OFDM_FE_CU_MODE_AVG__W 1 --#define OFDM_FE_CU_MODE_AVG__M 0x20 --#define OFDM_FE_CU_MODE_AVG__PRE 0x20 --#define OFDM_FE_CU_MODE_AVG_OFF 0x0 --#define OFDM_FE_CU_MODE_AVG_ON 0x20 --#define OFDM_FE_CU_MODE_SHF_ENA__B 6 --#define OFDM_FE_CU_MODE_SHF_ENA__W 1 --#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40 --#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0 --#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0 --#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40 --#define OFDM_FE_CU_MODE_SHF_DIR__B 7 --#define OFDM_FE_CU_MODE_SHF_DIR__W 1 --#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80 --#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0 --#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0 --#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80 -- -- --#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011 --#define OFDM_FE_CU_FRM_CNT_RST__W 15 --#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF --#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF -- --#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012 --#define OFDM_FE_CU_FRM_CNT_STR__W 15 --#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF --#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E -- --#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013 --#define OFDM_FE_CU_FRM_SMP_CNT__W 15 --#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF --#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0 -- --#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014 --#define OFDM_FE_CU_FRM_SMB_CNT__W 16 --#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF --#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0 -- --#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015 --#define OFDM_FE_CU_CMP_MAX_DAT__W 12 --#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF --#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0 -- --#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016 --#define OFDM_FE_CU_CMP_MAX_ADR__W 10 --#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF --#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0 -- --#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017 --#define OFDM_FE_CU_CMP_MAX_RE__W 12 --#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF --#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0 -- --#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018 --#define OFDM_FE_CU_CMP_MAX_IM__W 12 --#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF --#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0 -- --#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F --#define OFDM_FE_CU_BUF_NFC_DEL__W 14 --#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF --#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0 -- --#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020 --#define OFDM_FE_CU_CTR_NFC_ICR__W 5 --#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F --#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1 -- --#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021 --#define OFDM_FE_CU_CTR_NFC_OCR__W 15 --#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF --#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8 -- --#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022 --#define OFDM_FE_CU_CTR_NFC_CNT__W 15 --#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF --#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0 -- --#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023 --#define OFDM_FE_CU_CTR_NFC_STS__W 3 --#define OFDM_FE_CU_CTR_NFC_STS__M 0x7 --#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0 --#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0 --#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1 --#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2 --#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4 -- -- --#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024 --#define OFDM_FE_CU_DIV_NFC_REA__W 14 --#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF --#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0 -- --#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025 --#define OFDM_FE_CU_DIV_NFC_IMA__W 14 --#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF --#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0 -- --#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026 --#define OFDM_FE_CU_FRM_CNT_UPD__W 15 --#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF --#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF -- --#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027 --#define OFDM_FE_CU_DIV_NFC_CLP__W 2 --#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3 --#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0 --#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0 --#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1 --#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2 --#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3 -- -- --#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028 --#define OFDM_FE_CU_CMP_MAX_32__W 12 --#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF --#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0 -- --#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029 --#define OFDM_FE_CU_CMP_MAX_16__W 12 --#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF --#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0 -- --#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A --#define OFDM_FE_CU_CMP_MAX_8__W 12 --#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF --#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0 -- --#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B --#define OFDM_FE_CU_CMP_MAX_4__W 12 --#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF --#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C --#define OFDM_FE_CU_CMP_SUM_32_RE__W 14 --#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D --#define OFDM_FE_CU_CMP_SUM_32_IM__W 14 --#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E --#define OFDM_FE_CU_CMP_SUM_16_RE__W 14 --#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F --#define OFDM_FE_CU_CMP_SUM_16_IM__W 14 --#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030 --#define OFDM_FE_CU_CMP_SUM_8_RE__W 14 --#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031 --#define OFDM_FE_CU_CMP_SUM_8_IM__W 14 --#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032 --#define OFDM_FE_CU_CMP_SUM_4_RE__W 14 --#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0 -- --#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033 --#define OFDM_FE_CU_CMP_SUM_4_IM__W 14 --#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF --#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0 -- -- -- --#define OFDM_FE_CU_BUF_RAM__A 0x2020000 -- -- -- --#define OFDM_FE_CU_CMP_RAM__A 0x2030000 -- -- -- -- -- --#define OFDM_FT_COMM_EXEC__A 0x2400000 --#define OFDM_FT_COMM_EXEC__W 3 --#define OFDM_FT_COMM_EXEC__M 0x7 --#define OFDM_FT_COMM_EXEC__PRE 0x0 --#define OFDM_FT_COMM_EXEC_STOP 0x0 --#define OFDM_FT_COMM_EXEC_ACTIVE 0x1 --#define OFDM_FT_COMM_EXEC_HOLD 0x2 --#define OFDM_FT_COMM_EXEC_STEP 0x3 --#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4 --#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6 -- --#define OFDM_FT_COMM_STATE__A 0x2400001 --#define OFDM_FT_COMM_STATE__W 16 --#define OFDM_FT_COMM_STATE__M 0xFFFF --#define OFDM_FT_COMM_STATE__PRE 0x0 --#define OFDM_FT_COMM_MB__A 0x2400002 --#define OFDM_FT_COMM_MB__W 16 --#define OFDM_FT_COMM_MB__M 0xFFFF --#define OFDM_FT_COMM_MB__PRE 0x0 -- -- -- --#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000 --#define OFDM_FT_TOP_COMM_EXEC__W 3 --#define OFDM_FT_TOP_COMM_EXEC__M 0x7 --#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0 --#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0 --#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1 --#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2 --#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3 -- --#define OFDM_FT_TOP_COMM_MB__A 0x2410002 --#define OFDM_FT_TOP_COMM_MB__W 2 --#define OFDM_FT_TOP_COMM_MB__M 0x3 --#define OFDM_FT_TOP_COMM_MB__PRE 0x0 --#define OFDM_FT_TOP_COMM_MB_CTL__B 0 --#define OFDM_FT_TOP_COMM_MB_CTL__W 1 --#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1 --#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0 --#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0 --#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1 --#define OFDM_FT_TOP_COMM_MB_OBS__B 1 --#define OFDM_FT_TOP_COMM_MB_OBS__W 1 --#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2 --#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0 --#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0 --#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2 -- -- --#define OFDM_FT_TOP_MODE_2K__A 0x2410010 --#define OFDM_FT_TOP_MODE_2K__W 1 --#define OFDM_FT_TOP_MODE_2K__M 0x1 --#define OFDM_FT_TOP_MODE_2K__PRE 0x0 --#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0 --#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1 -- -- --#define OFDM_FT_TOP_NORM_OFF__A 0x2410016 --#define OFDM_FT_TOP_NORM_OFF__W 4 --#define OFDM_FT_TOP_NORM_OFF__M 0xF --#define OFDM_FT_TOP_NORM_OFF__PRE 0x2 -- -- -- --#define OFDM_FT_0TO2_0_RAM__A 0x2420000 -- -- -- --#define OFDM_FT_0TO2_1_RAM__A 0x2430000 -- -- -- --#define OFDM_FT_0TO2_2_RAM__A 0x2440000 -- -- -- --#define OFDM_FT_3TO7_0_RAM__A 0x2450000 -- -- -- --#define OFDM_FT_3TO7_1_RAM__A 0x2460000 -- -- -- -- -- --#define OFDM_LC_COMM_EXEC__A 0x3800000 --#define OFDM_LC_COMM_EXEC__W 3 --#define OFDM_LC_COMM_EXEC__M 0x7 --#define OFDM_LC_COMM_EXEC__PRE 0x0 --#define OFDM_LC_COMM_EXEC_STOP 0x0 --#define OFDM_LC_COMM_EXEC_ACTIVE 0x1 --#define OFDM_LC_COMM_EXEC_HOLD 0x2 --#define OFDM_LC_COMM_EXEC_STEP 0x3 --#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4 --#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6 -- --#define OFDM_LC_COMM_STATE__A 0x3800001 --#define OFDM_LC_COMM_STATE__W 16 --#define OFDM_LC_COMM_STATE__M 0xFFFF --#define OFDM_LC_COMM_STATE__PRE 0x0 --#define OFDM_LC_COMM_MB__A 0x3800002 --#define OFDM_LC_COMM_MB__W 16 --#define OFDM_LC_COMM_MB__M 0xFFFF --#define OFDM_LC_COMM_MB__PRE 0x0 --#define OFDM_LC_COMM_INT_REQ__A 0x3800004 --#define OFDM_LC_COMM_INT_REQ__W 16 --#define OFDM_LC_COMM_INT_REQ__M 0xFFFF --#define OFDM_LC_COMM_INT_REQ__PRE 0x0 --#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6 --#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1 --#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40 --#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0 -- --#define OFDM_LC_COMM_INT_STA__A 0x3800005 --#define OFDM_LC_COMM_INT_STA__W 16 --#define OFDM_LC_COMM_INT_STA__M 0xFFFF --#define OFDM_LC_COMM_INT_STA__PRE 0x0 --#define OFDM_LC_COMM_INT_MSK__A 0x3800006 --#define OFDM_LC_COMM_INT_MSK__W 16 --#define OFDM_LC_COMM_INT_MSK__M 0xFFFF --#define OFDM_LC_COMM_INT_MSK__PRE 0x0 --#define OFDM_LC_COMM_INT_STM__A 0x3800007 --#define OFDM_LC_COMM_INT_STM__W 16 --#define OFDM_LC_COMM_INT_STM__M 0xFFFF --#define OFDM_LC_COMM_INT_STM__PRE 0x0 --#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0 --#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16 --#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF --#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0 -- -- -- --#define OFDM_LC_CT_COMM_EXEC__A 0x3810000 --#define OFDM_LC_CT_COMM_EXEC__W 3 --#define OFDM_LC_CT_COMM_EXEC__M 0x7 --#define OFDM_LC_CT_COMM_EXEC__PRE 0x0 --#define OFDM_LC_CT_COMM_EXEC_STOP 0x0 --#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1 --#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2 --#define OFDM_LC_CT_COMM_EXEC_STEP 0x3 -- -- --#define OFDM_LC_CT_COMM_STATE__A 0x3810001 --#define OFDM_LC_CT_COMM_STATE__W 10 --#define OFDM_LC_CT_COMM_STATE__M 0x3FF --#define OFDM_LC_CT_COMM_STATE__PRE 0x0 --#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004 --#define OFDM_LC_CT_COMM_INT_REQ__W 1 --#define OFDM_LC_CT_COMM_INT_REQ__M 0x1 --#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0 --#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005 --#define OFDM_LC_CT_COMM_INT_STA__W 1 --#define OFDM_LC_CT_COMM_INT_STA__M 0x1 --#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0 --#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0 --#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1 --#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1 --#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0 -- --#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006 --#define OFDM_LC_CT_COMM_INT_MSK__W 1 --#define OFDM_LC_CT_COMM_INT_MSK__M 0x1 --#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0 --#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0 --#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1 --#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1 --#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 -- --#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007 --#define OFDM_LC_CT_COMM_INT_STM__W 1 --#define OFDM_LC_CT_COMM_INT_STM__M 0x1 --#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0 --#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0 --#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1 --#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1 --#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0 -- -- --#define OFDM_LC_CT_CTL_STK_0__A 0x3810010 --#define OFDM_LC_CT_CTL_STK_0__W 10 --#define OFDM_LC_CT_CTL_STK_0__M 0x3FF --#define OFDM_LC_CT_CTL_STK_0__PRE 0x0 -- --#define OFDM_LC_CT_CTL_STK_1__A 0x3810011 --#define OFDM_LC_CT_CTL_STK_1__W 10 --#define OFDM_LC_CT_CTL_STK_1__M 0x3FF --#define OFDM_LC_CT_CTL_STK_1__PRE 0x0 -- --#define OFDM_LC_CT_CTL_STK_2__A 0x3810012 --#define OFDM_LC_CT_CTL_STK_2__W 10 --#define OFDM_LC_CT_CTL_STK_2__M 0x3FF --#define OFDM_LC_CT_CTL_STK_2__PRE 0x0 -- --#define OFDM_LC_CT_CTL_STK_3__A 0x3810013 --#define OFDM_LC_CT_CTL_STK_3__W 10 --#define OFDM_LC_CT_CTL_STK_3__M 0x3FF --#define OFDM_LC_CT_CTL_STK_3__PRE 0x0 -- --#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F --#define OFDM_LC_CT_CTL_BPT_IDX__W 1 --#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1 --#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0 -- --#define OFDM_LC_CT_CTL_BPT__A 0x3810020 --#define OFDM_LC_CT_CTL_BPT__W 10 --#define OFDM_LC_CT_CTL_BPT__M 0x3FF --#define OFDM_LC_CT_CTL_BPT__PRE 0x0 -- -- -- --#define OFDM_LC_RA_RAM__A 0x3820000 -- -- -- -- --#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000 --#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12 --#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF --#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0 -- --#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001 --#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12 --#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF --#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0 -- --#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002 --#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12 --#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF --#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0 -- --#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004 --#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12 --#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF --#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0 -- --#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006 --#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12 --#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF --#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0 -- --#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007 --#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12 --#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF --#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0 -- -- -- -- -- -- -- --#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006 --#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16 --#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF --#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 --#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007 --#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16 --#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF --#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 --#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008 --#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16 --#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 --#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009 --#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16 --#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 --#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A --#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16 --#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF --#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0 --#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B --#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16 --#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF --#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0 --#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C --#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16 --#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF --#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0 --#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D --#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16 --#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF --#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0 --#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E --#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16 --#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF --#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0 --#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F --#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16 --#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF --#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010 --#define OFDM_LC_RA_RAM_MODE_2K__W 16 --#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF --#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011 --#define OFDM_LC_RA_RAM_MODE_GUARD__W 16 --#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF --#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0 --#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1 --#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2 --#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3 -- --#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012 --#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16 --#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF --#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 --#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 --#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 --#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 --#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 --#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 --#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 --#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000 --#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000 --#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0 -- --#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014 --#define OFDM_LC_RA_RAM_RC_STS__W 16 --#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF --#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0 --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018 --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019 --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A --#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16 --#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 --#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B --#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16 --#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 --#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C --#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16 --#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF --#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 --#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D --#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16 --#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF --#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 --#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F --#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 --#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020 --#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 --#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021 --#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 --#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022 --#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16 --#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF --#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0 --#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023 --#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16 --#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF --#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0 --#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024 --#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16 --#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025 --#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16 --#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF --#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0 --#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026 --#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16 --#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF --#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0 --#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027 --#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16 --#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF --#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E --#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16 --#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF --#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060 --#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7 --#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061 --#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066 --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067 --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068 --#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 --#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069 --#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070 --#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 --#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071 --#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076 --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077 --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078 --#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 --#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079 --#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0 --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16 --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF --#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0 -- -- -- -- -- --#define OFDM_SC_COMM_EXEC__A 0x3C00000 --#define OFDM_SC_COMM_EXEC__W 3 --#define OFDM_SC_COMM_EXEC__M 0x7 --#define OFDM_SC_COMM_EXEC__PRE 0x0 --#define OFDM_SC_COMM_EXEC_STOP 0x0 --#define OFDM_SC_COMM_EXEC_ACTIVE 0x1 --#define OFDM_SC_COMM_EXEC_HOLD 0x2 --#define OFDM_SC_COMM_EXEC_STEP 0x3 --#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4 --#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6 -- --#define OFDM_SC_COMM_STATE__A 0x3C00001 --#define OFDM_SC_COMM_STATE__W 16 --#define OFDM_SC_COMM_STATE__M 0xFFFF --#define OFDM_SC_COMM_STATE__PRE 0x0 --#define OFDM_SC_COMM_MB__A 0x3C00002 --#define OFDM_SC_COMM_MB__W 16 --#define OFDM_SC_COMM_MB__M 0xFFFF --#define OFDM_SC_COMM_MB__PRE 0x0 --#define OFDM_SC_COMM_INT_REQ__A 0x3C00004 --#define OFDM_SC_COMM_INT_REQ__W 16 --#define OFDM_SC_COMM_INT_REQ__M 0xFFFF --#define OFDM_SC_COMM_INT_REQ__PRE 0x0 --#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7 --#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1 --#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80 --#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0 -- --#define OFDM_SC_COMM_INT_STA__A 0x3C00005 --#define OFDM_SC_COMM_INT_STA__W 16 --#define OFDM_SC_COMM_INT_STA__M 0xFFFF --#define OFDM_SC_COMM_INT_STA__PRE 0x0 --#define OFDM_SC_COMM_INT_MSK__A 0x3C00006 --#define OFDM_SC_COMM_INT_MSK__W 16 --#define OFDM_SC_COMM_INT_MSK__M 0xFFFF --#define OFDM_SC_COMM_INT_MSK__PRE 0x0 --#define OFDM_SC_COMM_INT_STM__A 0x3C00007 --#define OFDM_SC_COMM_INT_STM__W 16 --#define OFDM_SC_COMM_INT_STM__M 0xFFFF --#define OFDM_SC_COMM_INT_STM__PRE 0x0 --#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0 --#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16 --#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF --#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0 -- -- -- --#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000 --#define OFDM_SC_CT_COMM_EXEC__W 3 --#define OFDM_SC_CT_COMM_EXEC__M 0x7 --#define OFDM_SC_CT_COMM_EXEC__PRE 0x0 --#define OFDM_SC_CT_COMM_EXEC_STOP 0x0 --#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1 --#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2 --#define OFDM_SC_CT_COMM_EXEC_STEP 0x3 -- -- --#define OFDM_SC_CT_COMM_STATE__A 0x3C10001 --#define OFDM_SC_CT_COMM_STATE__W 10 --#define OFDM_SC_CT_COMM_STATE__M 0x3FF --#define OFDM_SC_CT_COMM_STATE__PRE 0x0 --#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004 --#define OFDM_SC_CT_COMM_INT_REQ__W 1 --#define OFDM_SC_CT_COMM_INT_REQ__M 0x1 --#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0 --#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005 --#define OFDM_SC_CT_COMM_INT_STA__W 1 --#define OFDM_SC_CT_COMM_INT_STA__M 0x1 --#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0 --#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0 --#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1 --#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1 --#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0 -- --#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006 --#define OFDM_SC_CT_COMM_INT_MSK__W 1 --#define OFDM_SC_CT_COMM_INT_MSK__M 0x1 --#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0 --#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0 --#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1 --#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1 --#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 -- --#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007 --#define OFDM_SC_CT_COMM_INT_STM__W 1 --#define OFDM_SC_CT_COMM_INT_STM__M 0x1 --#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0 --#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0 --#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1 --#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1 --#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0 -- -- --#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010 --#define OFDM_SC_CT_CTL_STK_0__W 10 --#define OFDM_SC_CT_CTL_STK_0__M 0x3FF --#define OFDM_SC_CT_CTL_STK_0__PRE 0x0 -- --#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011 --#define OFDM_SC_CT_CTL_STK_1__W 10 --#define OFDM_SC_CT_CTL_STK_1__M 0x3FF --#define OFDM_SC_CT_CTL_STK_1__PRE 0x0 -- --#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012 --#define OFDM_SC_CT_CTL_STK_2__W 10 --#define OFDM_SC_CT_CTL_STK_2__M 0x3FF --#define OFDM_SC_CT_CTL_STK_2__PRE 0x0 -- --#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013 --#define OFDM_SC_CT_CTL_STK_3__W 10 --#define OFDM_SC_CT_CTL_STK_3__M 0x3FF --#define OFDM_SC_CT_CTL_STK_3__PRE 0x0 -- --#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F --#define OFDM_SC_CT_CTL_BPT_IDX__W 1 --#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1 --#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0 -- --#define OFDM_SC_CT_CTL_BPT__A 0x3C10020 --#define OFDM_SC_CT_CTL_BPT__W 13 --#define OFDM_SC_CT_CTL_BPT__M 0x1FFF --#define OFDM_SC_CT_CTL_BPT__PRE 0x0 -- -- -- --#define OFDM_SC_RA_RAM__A 0x3C20000 -- -- -- -- --#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000 --#define OFDM_SC_IF_RAM_TRP_RST_0__W 12 --#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF --#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0 -- --#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001 --#define OFDM_SC_IF_RAM_TRP_RST_1__W 12 --#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF --#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0 -- --#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002 --#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12 --#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF --#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0 -- --#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004 --#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12 --#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF --#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0 -- --#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004 --#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12 --#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF --#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0 -- --#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005 --#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12 --#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF --#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0 -- --#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE --#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12 --#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF --#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0 -- --#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF --#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12 --#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF --#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0 -- -- -- -- -- -- -- --#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 --#define OFDM_SC_RA_RAM_PARAM0__W 16 --#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF --#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 --#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 --#define OFDM_SC_RA_RAM_PARAM1__W 16 --#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF --#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 --#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 --#define OFDM_SC_RA_RAM_CMD_ADDR__W 16 --#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF --#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0 --#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 --#define OFDM_SC_RA_RAM_CMD__W 16 --#define OFDM_SC_RA_RAM_CMD__M 0xFFFF --#define OFDM_SC_RA_RAM_CMD__PRE 0x0 --#define OFDM_SC_RA_RAM_CMD_NULL 0x0 --#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 --#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 --#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 --#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 --#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 --#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 --#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 --#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 --#define OFDM_SC_RA_RAM_CMD_MAX 0x9 --#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4 -- --#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044 --#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16 --#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF --#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF --#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045 --#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16 --#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF --#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046 --#define OFDM_SC_RA_RAM_SW_EVENT__W 14 --#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF --#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2 --#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 --#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 --#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3 --#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 --#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4 --#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 --#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 --#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7 --#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 --#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 --#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0 --#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12 --#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1 --#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 --#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0 -- --#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047 --#define OFDM_SC_RA_RAM_LOCKTRACK__W 16 --#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF --#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0 --#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0 --#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 --#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1 --#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 --#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3 --#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4 --#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5 --#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6 --#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7 --#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8 --#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9 -- --#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 --#define OFDM_SC_RA_RAM_OP_PARAM__W 13 --#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF --#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 --#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 --#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 --#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 --#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC --#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4 --#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2 --#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30 --#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 --#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 --#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 --#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 --#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12 --#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1 --#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 --#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 --#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 -- --#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049 --#define OFDM_SC_RA_RAM_OP_AUTO__W 6 --#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F --#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F --#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0 --#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1 --#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 --#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1 --#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1 --#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1 --#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 --#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2 --#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2 --#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1 --#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 --#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4 --#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3 --#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1 --#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 --#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8 --#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4 --#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1 --#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 --#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10 --#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5 --#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1 --#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 --#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0 -- --#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A --#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16 --#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0 --#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0 --#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 --#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 --#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 -- --#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B --#define OFDM_SC_RA_RAM_LOCK__W 4 --#define OFDM_SC_RA_RAM_LOCK__M 0xF --#define OFDM_SC_RA_RAM_LOCK__PRE 0x0 --#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0 --#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1 --#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 --#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0 --#define OFDM_SC_RA_RAM_LOCK_FEC__B 1 --#define OFDM_SC_RA_RAM_LOCK_FEC__W 1 --#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 --#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0 --#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2 --#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1 --#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 --#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0 --#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3 --#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1 --#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 --#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0 -- --#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C --#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5 --#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F --#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C --#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10 --#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10 -- --#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D --#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16 --#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF --#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80 --#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E --#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 --#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF --#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 --#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F --#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 --#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 --#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 --#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 --#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF --#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 --#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 --#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 --#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 --#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 -- --#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 --#define OFDM_SC_RA_RAM_CONFIG__W 16 --#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF --#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14 --#define OFDM_SC_RA_RAM_CONFIG_ID__B 0 --#define OFDM_SC_RA_RAM_CONFIG_ID__W 1 --#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1 --#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0 --#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1 --#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 --#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 --#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 --#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 --#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 --#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 --#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4 --#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3 --#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1 --#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 --#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4 --#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1 --#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 --#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10 --#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5 --#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1 --#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20 --#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6 --#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1 --#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 --#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 --#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 --#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 --#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 --#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 --#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 --#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 --#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 --#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 --#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 --#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 --#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 --#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11 --#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1 --#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 --#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0 --#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 --#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 --#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 --#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0 -- --#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054 --#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 --#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF --#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 --#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055 --#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16 --#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 --#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056 --#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16 --#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 --#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057 --#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 --#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 --#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058 --#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16 --#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 --#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059 --#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16 --#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 --#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A --#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16 --#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1 --#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B --#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 --#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 --#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C --#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16 --#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1 --#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D --#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16 --#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF --#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB --#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E --#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16 --#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF --#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 --#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F --#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16 --#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF --#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE --#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E --#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16 --#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1 --#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F --#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16 --#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320 --#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070 --#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 --#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071 --#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 --#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072 --#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40 --#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073 --#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 --#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074 --#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 --#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075 --#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780 --#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076 --#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230 --#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077 --#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16 --#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF --#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 --#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C --#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 --#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 --#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D --#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 --#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF --#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C --#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E --#define OFDM_SC_RA_RAM_STATUS__W 16 --#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF --#define OFDM_SC_RA_RAM_STATUS__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F --#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16 --#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 --#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080 --#define OFDM_SC_RA_RAM_TIMER__W 16 --#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF --#define OFDM_SC_RA_RAM_TIMER__PRE 0x0 --#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081 --#define OFDM_SC_RA_RAM_FI_OFFSET__W 16 --#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF --#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382 --#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082 --#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16 --#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18 --#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D --#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16 --#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF --#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640 --#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E --#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16 --#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF --#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0 --#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F --#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16 --#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF --#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF --#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC --#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2 --#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16 --#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF --#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8 --#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7 --#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16 --#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF --#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230 --#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8 --#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16 --#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF --#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320 --#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9 --#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16 --#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF --#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400 -- --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16 --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3 --#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC --#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16 --#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6 --#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD --#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16 --#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28 --#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE --#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16 --#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6 --#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF --#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16 --#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF --#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14 --#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0 --#define OFDM_SC_RA_RAM_IR_FREQ__W 16 --#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 --#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 --#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100 --#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7 --#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 --#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 --#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8 --#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 --#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 --#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9 --#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 --#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 --#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA --#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 --#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB --#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB --#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 --#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 --#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC --#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 --#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF --#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD --#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 --#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE --#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16 --#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 --#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400 -- --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF --#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 --#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 --#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 --#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF --#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF --#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 --#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 --#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 --#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF --#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 --#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7 --#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16 --#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF --#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2 --#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8 --#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 --#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF --#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 --#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9 --#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 --#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF --#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C --#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA --#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 --#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF --#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 --#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB --#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16 --#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF --#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC --#define OFDM_SC_RA_RAM_BAND__W 16 --#define OFDM_SC_RA_RAM_BAND__M 0xFFFF --#define OFDM_SC_RA_RAM_BAND__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0 --#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4 --#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF --#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 --#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 --#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0 -- --#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED --#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 --#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF --#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16 --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19 --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16 --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF --#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B --#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0 --#define OFDM_SC_RA_RAM_REG_0__W 16 --#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF --#define OFDM_SC_RA_RAM_REG_0__PRE 0x0 --#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1 --#define OFDM_SC_RA_RAM_REG_1__W 16 --#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF --#define OFDM_SC_RA_RAM_REG_1__PRE 0x0 --#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2 --#define OFDM_SC_RA_RAM_BREAK__W 16 --#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF --#define OFDM_SC_RA_RAM_BREAK__PRE 0x0 --#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3 --#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16 --#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF --#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0 --#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4 --#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16 --#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF --#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F --#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5 --#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16 --#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF --#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F --#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6 --#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16 --#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF --#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1 --#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7 --#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 --#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF --#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF --#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F -- --#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9 --#define OFDM_SC_RA_RAM_LC_CP__W 16 --#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF --#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1 --#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA --#define OFDM_SC_RA_RAM_LC_DIFF__W 16 --#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF --#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7 --#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB --#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16 --#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58 --#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC --#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16 --#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0 -- --#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD --#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16 --#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF --#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38 --#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE --#define OFDM_SC_RA_RAM_RELOCK__W 16 --#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF --#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0 --#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF --#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16 --#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF --#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148 --#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 --#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149 --#define OFDM_SC_RA_RAM_NF_PREPOST__W 16 --#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A --#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16 --#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B --#define OFDM_SC_RA_RAM_NF_START__W 16 --#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_START__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C --#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16 --#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D --#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16 --#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F --#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16 --#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16 --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF --#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF --#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 --#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE --#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16 --#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF --#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0 --#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF --#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16 --#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF --#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0 -- -- -- -- -- --#define QAM_COMM_EXEC__A 0x1400000 --#define QAM_COMM_EXEC__W 2 --#define QAM_COMM_EXEC__M 0x3 --#define QAM_COMM_EXEC__PRE 0x0 --#define QAM_COMM_EXEC_STOP 0x0 --#define QAM_COMM_EXEC_ACTIVE 0x1 --#define QAM_COMM_EXEC_HOLD 0x2 -- --#define QAM_COMM_MB__A 0x1400002 --#define QAM_COMM_MB__W 16 --#define QAM_COMM_MB__M 0xFFFF --#define QAM_COMM_MB__PRE 0x0 --#define QAM_COMM_INT_REQ__A 0x1400003 --#define QAM_COMM_INT_REQ__W 16 --#define QAM_COMM_INT_REQ__M 0xFFFF --#define QAM_COMM_INT_REQ__PRE 0x0 -- --#define QAM_COMM_INT_REQ_SL_REQ__B 0 --#define QAM_COMM_INT_REQ_SL_REQ__W 1 --#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 --#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 -- --#define QAM_COMM_INT_REQ_LC_REQ__B 1 --#define QAM_COMM_INT_REQ_LC_REQ__W 1 --#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 --#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 -- --#define QAM_COMM_INT_REQ_VD_REQ__B 2 --#define QAM_COMM_INT_REQ_VD_REQ__W 1 --#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 --#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 -- --#define QAM_COMM_INT_REQ_SY_REQ__B 3 --#define QAM_COMM_INT_REQ_SY_REQ__W 1 --#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 --#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 -- --#define QAM_COMM_INT_STA__A 0x1400005 --#define QAM_COMM_INT_STA__W 16 --#define QAM_COMM_INT_STA__M 0xFFFF --#define QAM_COMM_INT_STA__PRE 0x0 --#define QAM_COMM_INT_MSK__A 0x1400006 --#define QAM_COMM_INT_MSK__W 16 --#define QAM_COMM_INT_MSK__M 0xFFFF --#define QAM_COMM_INT_MSK__PRE 0x0 --#define QAM_COMM_INT_STM__A 0x1400007 --#define QAM_COMM_INT_STM__W 16 --#define QAM_COMM_INT_STM__M 0xFFFF --#define QAM_COMM_INT_STM__PRE 0x0 -- -- -- --#define QAM_TOP_COMM_EXEC__A 0x1410000 --#define QAM_TOP_COMM_EXEC__W 2 --#define QAM_TOP_COMM_EXEC__M 0x3 --#define QAM_TOP_COMM_EXEC__PRE 0x0 --#define QAM_TOP_COMM_EXEC_STOP 0x0 --#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 --#define QAM_TOP_COMM_EXEC_HOLD 0x2 -- -- --#define QAM_TOP_ANNEX__A 0x1410010 --#define QAM_TOP_ANNEX__W 2 --#define QAM_TOP_ANNEX__M 0x3 --#define QAM_TOP_ANNEX__PRE 0x0 --#define QAM_TOP_ANNEX_A 0x0 --#define QAM_TOP_ANNEX_B 0x1 --#define QAM_TOP_ANNEX_C 0x2 --#define QAM_TOP_ANNEX_D 0x3 -- -- --#define QAM_TOP_CONSTELLATION__A 0x1410011 --#define QAM_TOP_CONSTELLATION__W 3 --#define QAM_TOP_CONSTELLATION__M 0x7 --#define QAM_TOP_CONSTELLATION__PRE 0x5 --#define QAM_TOP_CONSTELLATION_NONE 0x0 --#define QAM_TOP_CONSTELLATION_QPSK 0x1 --#define QAM_TOP_CONSTELLATION_QAM8 0x2 --#define QAM_TOP_CONSTELLATION_QAM16 0x3 --#define QAM_TOP_CONSTELLATION_QAM32 0x4 --#define QAM_TOP_CONSTELLATION_QAM64 0x5 --#define QAM_TOP_CONSTELLATION_QAM128 0x6 --#define QAM_TOP_CONSTELLATION_QAM256 0x7 -- -- -- --#define QAM_FQ_COMM_EXEC__A 0x1420000 --#define QAM_FQ_COMM_EXEC__W 2 --#define QAM_FQ_COMM_EXEC__M 0x3 --#define QAM_FQ_COMM_EXEC__PRE 0x0 --#define QAM_FQ_COMM_EXEC_STOP 0x0 --#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 --#define QAM_FQ_COMM_EXEC_HOLD 0x2 -- --#define QAM_FQ_MODE__A 0x1420010 --#define QAM_FQ_MODE__W 3 --#define QAM_FQ_MODE__M 0x7 --#define QAM_FQ_MODE__PRE 0x0 -- --#define QAM_FQ_MODE_TAPRESET__B 0 --#define QAM_FQ_MODE_TAPRESET__W 1 --#define QAM_FQ_MODE_TAPRESET__M 0x1 --#define QAM_FQ_MODE_TAPRESET__PRE 0x0 --#define QAM_FQ_MODE_TAPRESET_RST 0x1 -- --#define QAM_FQ_MODE_TAPLMS__B 1 --#define QAM_FQ_MODE_TAPLMS__W 1 --#define QAM_FQ_MODE_TAPLMS__M 0x2 --#define QAM_FQ_MODE_TAPLMS__PRE 0x0 --#define QAM_FQ_MODE_TAPLMS_UPD 0x2 -- --#define QAM_FQ_MODE_TAPDRAIN__B 2 --#define QAM_FQ_MODE_TAPDRAIN__W 1 --#define QAM_FQ_MODE_TAPDRAIN__M 0x4 --#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 --#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 -- -- --#define QAM_FQ_MU_FACTOR__A 0x1420011 --#define QAM_FQ_MU_FACTOR__W 3 --#define QAM_FQ_MU_FACTOR__M 0x7 --#define QAM_FQ_MU_FACTOR__PRE 0x0 -- --#define QAM_FQ_LA_FACTOR__A 0x1420012 --#define QAM_FQ_LA_FACTOR__W 4 --#define QAM_FQ_LA_FACTOR__M 0xF --#define QAM_FQ_LA_FACTOR__PRE 0xC --#define QAM_FQ_CENTTAP_IDX__A 0x1420016 --#define QAM_FQ_CENTTAP_IDX__W 5 --#define QAM_FQ_CENTTAP_IDX__M 0x1F --#define QAM_FQ_CENTTAP_IDX__PRE 0x13 -- --#define QAM_FQ_CENTTAP_IDX_IDX__B 0 --#define QAM_FQ_CENTTAP_IDX_IDX__W 5 --#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F --#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 -- --#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 --#define QAM_FQ_CENTTAP_VALUE__W 12 --#define QAM_FQ_CENTTAP_VALUE__M 0xFFF --#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 -- --#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 --#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 --#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF --#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 -- --#define QAM_FQ_TAP_RE_EL0__A 0x1420020 --#define QAM_FQ_TAP_RE_EL0__W 12 --#define QAM_FQ_TAP_RE_EL0__M 0xFFF --#define QAM_FQ_TAP_RE_EL0__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL0_TAP__B 0 --#define QAM_FQ_TAP_RE_EL0_TAP__W 12 --#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL0__A 0x1420021 --#define QAM_FQ_TAP_IM_EL0__W 12 --#define QAM_FQ_TAP_IM_EL0__M 0xFFF --#define QAM_FQ_TAP_IM_EL0__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL0_TAP__B 0 --#define QAM_FQ_TAP_IM_EL0_TAP__W 12 --#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL1__A 0x1420022 --#define QAM_FQ_TAP_RE_EL1__W 12 --#define QAM_FQ_TAP_RE_EL1__M 0xFFF --#define QAM_FQ_TAP_RE_EL1__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL1_TAP__B 0 --#define QAM_FQ_TAP_RE_EL1_TAP__W 12 --#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL1__A 0x1420023 --#define QAM_FQ_TAP_IM_EL1__W 12 --#define QAM_FQ_TAP_IM_EL1__M 0xFFF --#define QAM_FQ_TAP_IM_EL1__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL1_TAP__B 0 --#define QAM_FQ_TAP_IM_EL1_TAP__W 12 --#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL2__A 0x1420024 --#define QAM_FQ_TAP_RE_EL2__W 12 --#define QAM_FQ_TAP_RE_EL2__M 0xFFF --#define QAM_FQ_TAP_RE_EL2__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL2_TAP__B 0 --#define QAM_FQ_TAP_RE_EL2_TAP__W 12 --#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL2__A 0x1420025 --#define QAM_FQ_TAP_IM_EL2__W 12 --#define QAM_FQ_TAP_IM_EL2__M 0xFFF --#define QAM_FQ_TAP_IM_EL2__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL2_TAP__B 0 --#define QAM_FQ_TAP_IM_EL2_TAP__W 12 --#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL3__A 0x1420026 --#define QAM_FQ_TAP_RE_EL3__W 12 --#define QAM_FQ_TAP_RE_EL3__M 0xFFF --#define QAM_FQ_TAP_RE_EL3__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL3_TAP__B 0 --#define QAM_FQ_TAP_RE_EL3_TAP__W 12 --#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL3__A 0x1420027 --#define QAM_FQ_TAP_IM_EL3__W 12 --#define QAM_FQ_TAP_IM_EL3__M 0xFFF --#define QAM_FQ_TAP_IM_EL3__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL3_TAP__B 0 --#define QAM_FQ_TAP_IM_EL3_TAP__W 12 --#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL4__A 0x1420028 --#define QAM_FQ_TAP_RE_EL4__W 12 --#define QAM_FQ_TAP_RE_EL4__M 0xFFF --#define QAM_FQ_TAP_RE_EL4__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL4_TAP__B 0 --#define QAM_FQ_TAP_RE_EL4_TAP__W 12 --#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL4__A 0x1420029 --#define QAM_FQ_TAP_IM_EL4__W 12 --#define QAM_FQ_TAP_IM_EL4__M 0xFFF --#define QAM_FQ_TAP_IM_EL4__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL4_TAP__B 0 --#define QAM_FQ_TAP_IM_EL4_TAP__W 12 --#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL5__A 0x142002A --#define QAM_FQ_TAP_RE_EL5__W 12 --#define QAM_FQ_TAP_RE_EL5__M 0xFFF --#define QAM_FQ_TAP_RE_EL5__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL5_TAP__B 0 --#define QAM_FQ_TAP_RE_EL5_TAP__W 12 --#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL5__A 0x142002B --#define QAM_FQ_TAP_IM_EL5__W 12 --#define QAM_FQ_TAP_IM_EL5__M 0xFFF --#define QAM_FQ_TAP_IM_EL5__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL5_TAP__B 0 --#define QAM_FQ_TAP_IM_EL5_TAP__W 12 --#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL6__A 0x142002C --#define QAM_FQ_TAP_RE_EL6__W 12 --#define QAM_FQ_TAP_RE_EL6__M 0xFFF --#define QAM_FQ_TAP_RE_EL6__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL6_TAP__B 0 --#define QAM_FQ_TAP_RE_EL6_TAP__W 12 --#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL6__A 0x142002D --#define QAM_FQ_TAP_IM_EL6__W 12 --#define QAM_FQ_TAP_IM_EL6__M 0xFFF --#define QAM_FQ_TAP_IM_EL6__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL6_TAP__B 0 --#define QAM_FQ_TAP_IM_EL6_TAP__W 12 --#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL7__A 0x142002E --#define QAM_FQ_TAP_RE_EL7__W 12 --#define QAM_FQ_TAP_RE_EL7__M 0xFFF --#define QAM_FQ_TAP_RE_EL7__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL7_TAP__B 0 --#define QAM_FQ_TAP_RE_EL7_TAP__W 12 --#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL7__A 0x142002F --#define QAM_FQ_TAP_IM_EL7__W 12 --#define QAM_FQ_TAP_IM_EL7__M 0xFFF --#define QAM_FQ_TAP_IM_EL7__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL7_TAP__B 0 --#define QAM_FQ_TAP_IM_EL7_TAP__W 12 --#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL8__A 0x1420030 --#define QAM_FQ_TAP_RE_EL8__W 12 --#define QAM_FQ_TAP_RE_EL8__M 0xFFF --#define QAM_FQ_TAP_RE_EL8__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL8_TAP__B 0 --#define QAM_FQ_TAP_RE_EL8_TAP__W 12 --#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL8__A 0x1420031 --#define QAM_FQ_TAP_IM_EL8__W 12 --#define QAM_FQ_TAP_IM_EL8__M 0xFFF --#define QAM_FQ_TAP_IM_EL8__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL8_TAP__B 0 --#define QAM_FQ_TAP_IM_EL8_TAP__W 12 --#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL9__A 0x1420032 --#define QAM_FQ_TAP_RE_EL9__W 12 --#define QAM_FQ_TAP_RE_EL9__M 0xFFF --#define QAM_FQ_TAP_RE_EL9__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL9_TAP__B 0 --#define QAM_FQ_TAP_RE_EL9_TAP__W 12 --#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL9__A 0x1420033 --#define QAM_FQ_TAP_IM_EL9__W 12 --#define QAM_FQ_TAP_IM_EL9__M 0xFFF --#define QAM_FQ_TAP_IM_EL9__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL9_TAP__B 0 --#define QAM_FQ_TAP_IM_EL9_TAP__W 12 --#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL10__A 0x1420034 --#define QAM_FQ_TAP_RE_EL10__W 12 --#define QAM_FQ_TAP_RE_EL10__M 0xFFF --#define QAM_FQ_TAP_RE_EL10__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL10_TAP__B 0 --#define QAM_FQ_TAP_RE_EL10_TAP__W 12 --#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL10__A 0x1420035 --#define QAM_FQ_TAP_IM_EL10__W 12 --#define QAM_FQ_TAP_IM_EL10__M 0xFFF --#define QAM_FQ_TAP_IM_EL10__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL10_TAP__B 0 --#define QAM_FQ_TAP_IM_EL10_TAP__W 12 --#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL11__A 0x1420036 --#define QAM_FQ_TAP_RE_EL11__W 12 --#define QAM_FQ_TAP_RE_EL11__M 0xFFF --#define QAM_FQ_TAP_RE_EL11__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL11_TAP__B 0 --#define QAM_FQ_TAP_RE_EL11_TAP__W 12 --#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL11__A 0x1420037 --#define QAM_FQ_TAP_IM_EL11__W 12 --#define QAM_FQ_TAP_IM_EL11__M 0xFFF --#define QAM_FQ_TAP_IM_EL11__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL11_TAP__B 0 --#define QAM_FQ_TAP_IM_EL11_TAP__W 12 --#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL12__A 0x1420038 --#define QAM_FQ_TAP_RE_EL12__W 12 --#define QAM_FQ_TAP_RE_EL12__M 0xFFF --#define QAM_FQ_TAP_RE_EL12__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL12_TAP__B 0 --#define QAM_FQ_TAP_RE_EL12_TAP__W 12 --#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL12__A 0x1420039 --#define QAM_FQ_TAP_IM_EL12__W 12 --#define QAM_FQ_TAP_IM_EL12__M 0xFFF --#define QAM_FQ_TAP_IM_EL12__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL12_TAP__B 0 --#define QAM_FQ_TAP_IM_EL12_TAP__W 12 --#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL13__A 0x142003A --#define QAM_FQ_TAP_RE_EL13__W 12 --#define QAM_FQ_TAP_RE_EL13__M 0xFFF --#define QAM_FQ_TAP_RE_EL13__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL13_TAP__B 0 --#define QAM_FQ_TAP_RE_EL13_TAP__W 12 --#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL13__A 0x142003B --#define QAM_FQ_TAP_IM_EL13__W 12 --#define QAM_FQ_TAP_IM_EL13__M 0xFFF --#define QAM_FQ_TAP_IM_EL13__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL13_TAP__B 0 --#define QAM_FQ_TAP_IM_EL13_TAP__W 12 --#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL14__A 0x142003C --#define QAM_FQ_TAP_RE_EL14__W 12 --#define QAM_FQ_TAP_RE_EL14__M 0xFFF --#define QAM_FQ_TAP_RE_EL14__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL14_TAP__B 0 --#define QAM_FQ_TAP_RE_EL14_TAP__W 12 --#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL14__A 0x142003D --#define QAM_FQ_TAP_IM_EL14__W 12 --#define QAM_FQ_TAP_IM_EL14__M 0xFFF --#define QAM_FQ_TAP_IM_EL14__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL14_TAP__B 0 --#define QAM_FQ_TAP_IM_EL14_TAP__W 12 --#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL15__A 0x142003E --#define QAM_FQ_TAP_RE_EL15__W 12 --#define QAM_FQ_TAP_RE_EL15__M 0xFFF --#define QAM_FQ_TAP_RE_EL15__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL15_TAP__B 0 --#define QAM_FQ_TAP_RE_EL15_TAP__W 12 --#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL15__A 0x142003F --#define QAM_FQ_TAP_IM_EL15__W 12 --#define QAM_FQ_TAP_IM_EL15__M 0xFFF --#define QAM_FQ_TAP_IM_EL15__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL15_TAP__B 0 --#define QAM_FQ_TAP_IM_EL15_TAP__W 12 --#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL16__A 0x1420040 --#define QAM_FQ_TAP_RE_EL16__W 12 --#define QAM_FQ_TAP_RE_EL16__M 0xFFF --#define QAM_FQ_TAP_RE_EL16__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL16_TAP__B 0 --#define QAM_FQ_TAP_RE_EL16_TAP__W 12 --#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL16__A 0x1420041 --#define QAM_FQ_TAP_IM_EL16__W 12 --#define QAM_FQ_TAP_IM_EL16__M 0xFFF --#define QAM_FQ_TAP_IM_EL16__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL16_TAP__B 0 --#define QAM_FQ_TAP_IM_EL16_TAP__W 12 --#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL17__A 0x1420042 --#define QAM_FQ_TAP_RE_EL17__W 12 --#define QAM_FQ_TAP_RE_EL17__M 0xFFF --#define QAM_FQ_TAP_RE_EL17__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL17_TAP__B 0 --#define QAM_FQ_TAP_RE_EL17_TAP__W 12 --#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL17__A 0x1420043 --#define QAM_FQ_TAP_IM_EL17__W 12 --#define QAM_FQ_TAP_IM_EL17__M 0xFFF --#define QAM_FQ_TAP_IM_EL17__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL17_TAP__B 0 --#define QAM_FQ_TAP_IM_EL17_TAP__W 12 --#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL18__A 0x1420044 --#define QAM_FQ_TAP_RE_EL18__W 12 --#define QAM_FQ_TAP_RE_EL18__M 0xFFF --#define QAM_FQ_TAP_RE_EL18__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL18_TAP__B 0 --#define QAM_FQ_TAP_RE_EL18_TAP__W 12 --#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL18__A 0x1420045 --#define QAM_FQ_TAP_IM_EL18__W 12 --#define QAM_FQ_TAP_IM_EL18__M 0xFFF --#define QAM_FQ_TAP_IM_EL18__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL18_TAP__B 0 --#define QAM_FQ_TAP_IM_EL18_TAP__W 12 --#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL19__A 0x1420046 --#define QAM_FQ_TAP_RE_EL19__W 12 --#define QAM_FQ_TAP_RE_EL19__M 0xFFF --#define QAM_FQ_TAP_RE_EL19__PRE 0x600 -- --#define QAM_FQ_TAP_RE_EL19_TAP__B 0 --#define QAM_FQ_TAP_RE_EL19_TAP__W 12 --#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 -- --#define QAM_FQ_TAP_IM_EL19__A 0x1420047 --#define QAM_FQ_TAP_IM_EL19__W 12 --#define QAM_FQ_TAP_IM_EL19__M 0xFFF --#define QAM_FQ_TAP_IM_EL19__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL19_TAP__B 0 --#define QAM_FQ_TAP_IM_EL19_TAP__W 12 --#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL20__A 0x1420048 --#define QAM_FQ_TAP_RE_EL20__W 12 --#define QAM_FQ_TAP_RE_EL20__M 0xFFF --#define QAM_FQ_TAP_RE_EL20__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL20_TAP__B 0 --#define QAM_FQ_TAP_RE_EL20_TAP__W 12 --#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL20__A 0x1420049 --#define QAM_FQ_TAP_IM_EL20__W 12 --#define QAM_FQ_TAP_IM_EL20__M 0xFFF --#define QAM_FQ_TAP_IM_EL20__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL20_TAP__B 0 --#define QAM_FQ_TAP_IM_EL20_TAP__W 12 --#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL21__A 0x142004A --#define QAM_FQ_TAP_RE_EL21__W 12 --#define QAM_FQ_TAP_RE_EL21__M 0xFFF --#define QAM_FQ_TAP_RE_EL21__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL21_TAP__B 0 --#define QAM_FQ_TAP_RE_EL21_TAP__W 12 --#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL21__A 0x142004B --#define QAM_FQ_TAP_IM_EL21__W 12 --#define QAM_FQ_TAP_IM_EL21__M 0xFFF --#define QAM_FQ_TAP_IM_EL21__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL21_TAP__B 0 --#define QAM_FQ_TAP_IM_EL21_TAP__W 12 --#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL22__A 0x142004C --#define QAM_FQ_TAP_RE_EL22__W 12 --#define QAM_FQ_TAP_RE_EL22__M 0xFFF --#define QAM_FQ_TAP_RE_EL22__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL22_TAP__B 0 --#define QAM_FQ_TAP_RE_EL22_TAP__W 12 --#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL22__A 0x142004D --#define QAM_FQ_TAP_IM_EL22__W 12 --#define QAM_FQ_TAP_IM_EL22__M 0xFFF --#define QAM_FQ_TAP_IM_EL22__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL22_TAP__B 0 --#define QAM_FQ_TAP_IM_EL22_TAP__W 12 --#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL23__A 0x142004E --#define QAM_FQ_TAP_RE_EL23__W 12 --#define QAM_FQ_TAP_RE_EL23__M 0xFFF --#define QAM_FQ_TAP_RE_EL23__PRE 0x2 -- --#define QAM_FQ_TAP_RE_EL23_TAP__B 0 --#define QAM_FQ_TAP_RE_EL23_TAP__W 12 --#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF --#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL23__A 0x142004F --#define QAM_FQ_TAP_IM_EL23__W 12 --#define QAM_FQ_TAP_IM_EL23__M 0xFFF --#define QAM_FQ_TAP_IM_EL23__PRE 0x2 -- --#define QAM_FQ_TAP_IM_EL23_TAP__B 0 --#define QAM_FQ_TAP_IM_EL23_TAP__W 12 --#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF --#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 -- -- -- --#define QAM_SL_COMM_EXEC__A 0x1430000 --#define QAM_SL_COMM_EXEC__W 2 --#define QAM_SL_COMM_EXEC__M 0x3 --#define QAM_SL_COMM_EXEC__PRE 0x0 --#define QAM_SL_COMM_EXEC_STOP 0x0 --#define QAM_SL_COMM_EXEC_ACTIVE 0x1 --#define QAM_SL_COMM_EXEC_HOLD 0x2 -- --#define QAM_SL_COMM_MB__A 0x1430002 --#define QAM_SL_COMM_MB__W 4 --#define QAM_SL_COMM_MB__M 0xF --#define QAM_SL_COMM_MB__PRE 0x0 --#define QAM_SL_COMM_MB_CTL__B 0 --#define QAM_SL_COMM_MB_CTL__W 1 --#define QAM_SL_COMM_MB_CTL__M 0x1 --#define QAM_SL_COMM_MB_CTL__PRE 0x0 --#define QAM_SL_COMM_MB_CTL_OFF 0x0 --#define QAM_SL_COMM_MB_CTL_ON 0x1 --#define QAM_SL_COMM_MB_OBS__B 1 --#define QAM_SL_COMM_MB_OBS__W 1 --#define QAM_SL_COMM_MB_OBS__M 0x2 --#define QAM_SL_COMM_MB_OBS__PRE 0x0 --#define QAM_SL_COMM_MB_OBS_OFF 0x0 --#define QAM_SL_COMM_MB_OBS_ON 0x2 --#define QAM_SL_COMM_MB_MUX_OBS__B 2 --#define QAM_SL_COMM_MB_MUX_OBS__W 2 --#define QAM_SL_COMM_MB_MUX_OBS__M 0xC --#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 --#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 --#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 --#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 --#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC -- --#define QAM_SL_COMM_INT_REQ__A 0x1430003 --#define QAM_SL_COMM_INT_REQ__W 1 --#define QAM_SL_COMM_INT_REQ__M 0x1 --#define QAM_SL_COMM_INT_REQ__PRE 0x0 --#define QAM_SL_COMM_INT_STA__A 0x1430005 --#define QAM_SL_COMM_INT_STA__W 2 --#define QAM_SL_COMM_INT_STA__M 0x3 --#define QAM_SL_COMM_INT_STA__PRE 0x0 -- --#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 --#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 --#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 --#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 -- --#define QAM_SL_COMM_INT_STA_MER_INT__B 1 --#define QAM_SL_COMM_INT_STA_MER_INT__W 1 --#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 --#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 -- --#define QAM_SL_COMM_INT_MSK__A 0x1430006 --#define QAM_SL_COMM_INT_MSK__W 2 --#define QAM_SL_COMM_INT_MSK__M 0x3 --#define QAM_SL_COMM_INT_MSK__PRE 0x0 --#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 --#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 --#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 --#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 --#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 --#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 --#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 --#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 -- --#define QAM_SL_COMM_INT_STM__A 0x1430007 --#define QAM_SL_COMM_INT_STM__W 2 --#define QAM_SL_COMM_INT_STM__M 0x3 --#define QAM_SL_COMM_INT_STM__PRE 0x0 --#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 --#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 --#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 --#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 --#define QAM_SL_COMM_INT_STM_MER_STM__B 1 --#define QAM_SL_COMM_INT_STM_MER_STM__W 1 --#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 --#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 -- --#define QAM_SL_MODE__A 0x1430010 --#define QAM_SL_MODE__W 11 --#define QAM_SL_MODE__M 0x7FF --#define QAM_SL_MODE__PRE 0xA -- --#define QAM_SL_MODE_SLICER4LC__B 0 --#define QAM_SL_MODE_SLICER4LC__W 2 --#define QAM_SL_MODE_SLICER4LC__M 0x3 --#define QAM_SL_MODE_SLICER4LC__PRE 0x2 --#define QAM_SL_MODE_SLICER4LC_RECT 0x0 --#define QAM_SL_MODE_SLICER4LC_ONET 0x1 --#define QAM_SL_MODE_SLICER4LC_RAD 0x2 -- --#define QAM_SL_MODE_SLICER4DQ__B 2 --#define QAM_SL_MODE_SLICER4DQ__W 2 --#define QAM_SL_MODE_SLICER4DQ__M 0xC --#define QAM_SL_MODE_SLICER4DQ__PRE 0x8 --#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 --#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 --#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 -- --#define QAM_SL_MODE_SLICER4VD__B 4 --#define QAM_SL_MODE_SLICER4VD__W 2 --#define QAM_SL_MODE_SLICER4VD__M 0x30 --#define QAM_SL_MODE_SLICER4VD__PRE 0x0 --#define QAM_SL_MODE_SLICER4VD_RECT 0x0 --#define QAM_SL_MODE_SLICER4VD_ONET 0x10 --#define QAM_SL_MODE_SLICER4VD_RAD 0x20 -- --#define QAM_SL_MODE_ROT_DIS__B 6 --#define QAM_SL_MODE_ROT_DIS__W 1 --#define QAM_SL_MODE_ROT_DIS__M 0x40 --#define QAM_SL_MODE_ROT_DIS__PRE 0x0 --#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0 --#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40 -- --#define QAM_SL_MODE_DQROT_DIS__B 7 --#define QAM_SL_MODE_DQROT_DIS__W 1 --#define QAM_SL_MODE_DQROT_DIS__M 0x80 --#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 --#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0 --#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80 -- --#define QAM_SL_MODE_DFE_DIS__B 8 --#define QAM_SL_MODE_DFE_DIS__W 1 --#define QAM_SL_MODE_DFE_DIS__M 0x100 --#define QAM_SL_MODE_DFE_DIS__PRE 0x0 --#define QAM_SL_MODE_DFE_DIS_DQ 0x0 --#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100 -- --#define QAM_SL_MODE_RADIUS_MIX__B 9 --#define QAM_SL_MODE_RADIUS_MIX__W 1 --#define QAM_SL_MODE_RADIUS_MIX__M 0x200 --#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 --#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0 --#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200 -- --#define QAM_SL_MODE_TILT_COMP__B 10 --#define QAM_SL_MODE_TILT_COMP__W 1 --#define QAM_SL_MODE_TILT_COMP__M 0x400 --#define QAM_SL_MODE_TILT_COMP__PRE 0x0 --#define QAM_SL_MODE_TILT_COMP_OFF 0x0 --#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400 -- -- --#define QAM_SL_K_FACTOR__A 0x1430011 --#define QAM_SL_K_FACTOR__W 4 --#define QAM_SL_K_FACTOR__M 0xF --#define QAM_SL_K_FACTOR__PRE 0xC --#define QAM_SL_MEDIAN__A 0x1430012 --#define QAM_SL_MEDIAN__W 14 --#define QAM_SL_MEDIAN__M 0x3FFF --#define QAM_SL_MEDIAN__PRE 0x2C86 -- --#define QAM_SL_MEDIAN_LENGTH__B 0 --#define QAM_SL_MEDIAN_LENGTH__W 2 --#define QAM_SL_MEDIAN_LENGTH__M 0x3 --#define QAM_SL_MEDIAN_LENGTH__PRE 0x2 --#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0 --#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1 --#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2 --#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3 -- --#define QAM_SL_MEDIAN_CORRECT__B 2 --#define QAM_SL_MEDIAN_CORRECT__W 4 --#define QAM_SL_MEDIAN_CORRECT__M 0x3C --#define QAM_SL_MEDIAN_CORRECT__PRE 0x4 -- --#define QAM_SL_MEDIAN_TOLERANCE__B 6 --#define QAM_SL_MEDIAN_TOLERANCE__W 7 --#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 --#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80 -- --#define QAM_SL_MEDIAN_FAST__B 13 --#define QAM_SL_MEDIAN_FAST__W 1 --#define QAM_SL_MEDIAN_FAST__M 0x2000 --#define QAM_SL_MEDIAN_FAST__PRE 0x2000 --#define QAM_SL_MEDIAN_FAST_AVER 0x0 --#define QAM_SL_MEDIAN_FAST_LAST 0x2000 -- -- --#define QAM_SL_ALPHA__A 0x1430013 --#define QAM_SL_ALPHA__W 3 --#define QAM_SL_ALPHA__M 0x7 --#define QAM_SL_ALPHA__PRE 0x0 -- --#define QAM_SL_PHASELIMIT__A 0x1430014 --#define QAM_SL_PHASELIMIT__W 9 --#define QAM_SL_PHASELIMIT__M 0x1FF --#define QAM_SL_PHASELIMIT__PRE 0x0 --#define QAM_SL_MTA_LENGTH__A 0x1430015 --#define QAM_SL_MTA_LENGTH__W 2 --#define QAM_SL_MTA_LENGTH__M 0x3 --#define QAM_SL_MTA_LENGTH__PRE 0x1 -- --#define QAM_SL_MTA_LENGTH_LENGTH__B 0 --#define QAM_SL_MTA_LENGTH_LENGTH__W 2 --#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 --#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 -- --#define QAM_SL_MEDIAN_ERROR__A 0x1430016 --#define QAM_SL_MEDIAN_ERROR__W 10 --#define QAM_SL_MEDIAN_ERROR__M 0x3FF --#define QAM_SL_MEDIAN_ERROR__PRE 0x0 -- --#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 --#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 --#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF --#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 -- -- --#define QAM_SL_ERR_POWER__A 0x1430017 --#define QAM_SL_ERR_POWER__W 16 --#define QAM_SL_ERR_POWER__M 0xFFFF --#define QAM_SL_ERR_POWER__PRE 0x0 --#define QAM_SL_QUAL_QAM_4_0__A 0x1430018 --#define QAM_SL_QUAL_QAM_4_0__W 3 --#define QAM_SL_QUAL_QAM_4_0__M 0x7 --#define QAM_SL_QUAL_QAM_4_0__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_4_0_Q0__B 0 --#define QAM_SL_QUAL_QAM_4_0_Q0__W 3 --#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_8_0__A 0x1430019 --#define QAM_SL_QUAL_QAM_8_0__W 6 --#define QAM_SL_QUAL_QAM_8_0__M 0x3F --#define QAM_SL_QUAL_QAM_8_0__PRE 0xD -- --#define QAM_SL_QUAL_QAM_8_0_Q0__B 0 --#define QAM_SL_QUAL_QAM_8_0_Q0__W 3 --#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_8_0_Q1__B 3 --#define QAM_SL_QUAL_QAM_8_0_Q1__W 3 --#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8 -- --#define QAM_SL_QUAL_QAM_16_0__A 0x143001A --#define QAM_SL_QUAL_QAM_16_0__W 3 --#define QAM_SL_QUAL_QAM_16_0__M 0x7 --#define QAM_SL_QUAL_QAM_16_0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_16_0_Q0__B 0 --#define QAM_SL_QUAL_QAM_16_0_Q0__W 3 --#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_16_1__A 0x143001B --#define QAM_SL_QUAL_QAM_16_1__W 6 --#define QAM_SL_QUAL_QAM_16_1__M 0x3F --#define QAM_SL_QUAL_QAM_16_1__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_16_1_Q0__B 0 --#define QAM_SL_QUAL_QAM_16_1_Q0__W 3 --#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_16_1_Q1__B 3 --#define QAM_SL_QUAL_QAM_16_1_Q1__W 3 --#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_32_0__A 0x143001C --#define QAM_SL_QUAL_QAM_32_0__W 3 --#define QAM_SL_QUAL_QAM_32_0__M 0x7 --#define QAM_SL_QUAL_QAM_32_0__PRE 0x4 -- --#define QAM_SL_QUAL_QAM_32_0_Q0__B 0 --#define QAM_SL_QUAL_QAM_32_0_Q0__W 3 --#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4 -- --#define QAM_SL_QUAL_QAM_32_1__A 0x143001D --#define QAM_SL_QUAL_QAM_32_1__W 6 --#define QAM_SL_QUAL_QAM_32_1__M 0x3F --#define QAM_SL_QUAL_QAM_32_1__PRE 0x3 -- --#define QAM_SL_QUAL_QAM_32_1_Q0__B 0 --#define QAM_SL_QUAL_QAM_32_1_Q0__W 3 --#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3 -- --#define QAM_SL_QUAL_QAM_32_1_Q1__B 3 --#define QAM_SL_QUAL_QAM_32_1_Q1__W 3 --#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_32_2__A 0x143001E --#define QAM_SL_QUAL_QAM_32_2__W 9 --#define QAM_SL_QUAL_QAM_32_2__M 0x1FF --#define QAM_SL_QUAL_QAM_32_2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_32_2_Q0__B 0 --#define QAM_SL_QUAL_QAM_32_2_Q0__W 3 --#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_32_2_Q1__B 3 --#define QAM_SL_QUAL_QAM_32_2_Q1__W 3 --#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_32_2_Q2__B 6 --#define QAM_SL_QUAL_QAM_32_2_Q2__W 3 --#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_64_0__A 0x143001F --#define QAM_SL_QUAL_QAM_64_0__W 3 --#define QAM_SL_QUAL_QAM_64_0__M 0x7 --#define QAM_SL_QUAL_QAM_64_0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_64_0_Q0__B 0 --#define QAM_SL_QUAL_QAM_64_0_Q0__W 3 --#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_64_1__A 0x1430020 --#define QAM_SL_QUAL_QAM_64_1__W 6 --#define QAM_SL_QUAL_QAM_64_1__M 0x3F --#define QAM_SL_QUAL_QAM_64_1__PRE 0x2 -- --#define QAM_SL_QUAL_QAM_64_1_Q0__B 0 --#define QAM_SL_QUAL_QAM_64_1_Q0__W 3 --#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2 -- --#define QAM_SL_QUAL_QAM_64_1_Q1__B 3 --#define QAM_SL_QUAL_QAM_64_1_Q1__W 3 --#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_64_2__A 0x1430021 --#define QAM_SL_QUAL_QAM_64_2__W 9 --#define QAM_SL_QUAL_QAM_64_2__M 0x1FF --#define QAM_SL_QUAL_QAM_64_2__PRE 0x9 -- --#define QAM_SL_QUAL_QAM_64_2_Q0__B 0 --#define QAM_SL_QUAL_QAM_64_2_Q0__W 3 --#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_64_2_Q1__B 3 --#define QAM_SL_QUAL_QAM_64_2_Q1__W 3 --#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8 -- --#define QAM_SL_QUAL_QAM_64_2_Q2__B 6 --#define QAM_SL_QUAL_QAM_64_2_Q2__W 3 --#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_64_3__A 0x1430022 --#define QAM_SL_QUAL_QAM_64_3__W 12 --#define QAM_SL_QUAL_QAM_64_3__M 0xFFF --#define QAM_SL_QUAL_QAM_64_3__PRE 0xD -- --#define QAM_SL_QUAL_QAM_64_3_Q0__B 0 --#define QAM_SL_QUAL_QAM_64_3_Q0__W 3 --#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_64_3_Q1__B 3 --#define QAM_SL_QUAL_QAM_64_3_Q1__W 3 --#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8 -- --#define QAM_SL_QUAL_QAM_64_3_Q2__B 6 --#define QAM_SL_QUAL_QAM_64_3_Q2__W 3 --#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_64_3_Q3__B 9 --#define QAM_SL_QUAL_QAM_64_3_Q3__W 3 --#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_0__A 0x1430023 --#define QAM_SL_QUAL_QAM_128_0__W 3 --#define QAM_SL_QUAL_QAM_128_0__M 0x7 --#define QAM_SL_QUAL_QAM_128_0__PRE 0x4 -- --#define QAM_SL_QUAL_QAM_128_0_Q0__B 0 --#define QAM_SL_QUAL_QAM_128_0_Q0__W 3 --#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4 -- --#define QAM_SL_QUAL_QAM_128_1__A 0x1430024 --#define QAM_SL_QUAL_QAM_128_1__W 6 --#define QAM_SL_QUAL_QAM_128_1__M 0x3F --#define QAM_SL_QUAL_QAM_128_1__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_128_1_Q0__B 0 --#define QAM_SL_QUAL_QAM_128_1_Q0__W 3 --#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_128_1_Q1__B 3 --#define QAM_SL_QUAL_QAM_128_1_Q1__W 3 --#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_2__A 0x1430025 --#define QAM_SL_QUAL_QAM_128_2__W 9 --#define QAM_SL_QUAL_QAM_128_2__M 0x1FF --#define QAM_SL_QUAL_QAM_128_2__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_128_2_Q0__B 0 --#define QAM_SL_QUAL_QAM_128_2_Q0__W 3 --#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_128_2_Q1__B 3 --#define QAM_SL_QUAL_QAM_128_2_Q1__W 3 --#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_2_Q2__B 6 --#define QAM_SL_QUAL_QAM_128_2_Q2__W 3 --#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_3__A 0x1430026 --#define QAM_SL_QUAL_QAM_128_3__W 12 --#define QAM_SL_QUAL_QAM_128_3__M 0xFFF --#define QAM_SL_QUAL_QAM_128_3__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_128_3_Q0__B 0 --#define QAM_SL_QUAL_QAM_128_3_Q0__W 3 --#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_128_3_Q1__B 3 --#define QAM_SL_QUAL_QAM_128_3_Q1__W 3 --#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_3_Q2__B 6 --#define QAM_SL_QUAL_QAM_128_3_Q2__W 3 --#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_3_Q3__B 9 --#define QAM_SL_QUAL_QAM_128_3_Q3__W 3 --#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_4__A 0x1430027 --#define QAM_SL_QUAL_QAM_128_4__W 15 --#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF --#define QAM_SL_QUAL_QAM_128_4__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_4_Q0__B 0 --#define QAM_SL_QUAL_QAM_128_4_Q0__W 3 --#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_4_Q1__B 3 --#define QAM_SL_QUAL_QAM_128_4_Q1__W 3 --#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_4_Q2__B 6 --#define QAM_SL_QUAL_QAM_128_4_Q2__W 3 --#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_4_Q3__B 9 --#define QAM_SL_QUAL_QAM_128_4_Q3__W 3 --#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_4_Q4__B 12 --#define QAM_SL_QUAL_QAM_128_4_Q4__W 3 --#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000 --#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_5__A 0x1430028 --#define QAM_SL_QUAL_QAM_128_5__W 15 --#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF --#define QAM_SL_QUAL_QAM_128_5__PRE 0x90 -- --#define QAM_SL_QUAL_QAM_128_5_Q0__B 0 --#define QAM_SL_QUAL_QAM_128_5_Q0__W 3 --#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_5_Q1__B 3 --#define QAM_SL_QUAL_QAM_128_5_Q1__W 3 --#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10 -- --#define QAM_SL_QUAL_QAM_128_5_Q2__B 6 --#define QAM_SL_QUAL_QAM_128_5_Q2__W 3 --#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80 -- --#define QAM_SL_QUAL_QAM_128_5_Q3__B 9 --#define QAM_SL_QUAL_QAM_128_5_Q3__W 3 --#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_5_Q4__B 12 --#define QAM_SL_QUAL_QAM_128_5_Q4__W 3 --#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000 --#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029 --#define QAM_SL_QUAL_QAM_128_5H__W 3 --#define QAM_SL_QUAL_QAM_128_5H__M 0x7 --#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0 --#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3 --#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7 --#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_0__A 0x143002A --#define QAM_SL_QUAL_QAM_256_0__W 3 --#define QAM_SL_QUAL_QAM_256_0__M 0x7 --#define QAM_SL_QUAL_QAM_256_0__PRE 0x3 -- --#define QAM_SL_QUAL_QAM_256_0_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_0_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3 -- --#define QAM_SL_QUAL_QAM_256_1__A 0x143002B --#define QAM_SL_QUAL_QAM_256_1__W 6 --#define QAM_SL_QUAL_QAM_256_1__M 0x3F --#define QAM_SL_QUAL_QAM_256_1__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_256_1_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_1_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_256_1_Q1__B 3 --#define QAM_SL_QUAL_QAM_256_1_Q1__W 3 --#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_2__A 0x143002C --#define QAM_SL_QUAL_QAM_256_2__W 9 --#define QAM_SL_QUAL_QAM_256_2__M 0x1FF --#define QAM_SL_QUAL_QAM_256_2__PRE 0x9 -- --#define QAM_SL_QUAL_QAM_256_2_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_2_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_256_2_Q1__B 3 --#define QAM_SL_QUAL_QAM_256_2_Q1__W 3 --#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8 -- --#define QAM_SL_QUAL_QAM_256_2_Q2__B 6 --#define QAM_SL_QUAL_QAM_256_2_Q2__W 3 --#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_3__A 0x143002D --#define QAM_SL_QUAL_QAM_256_3__W 12 --#define QAM_SL_QUAL_QAM_256_3__M 0xFFF --#define QAM_SL_QUAL_QAM_256_3__PRE 0x13 -- --#define QAM_SL_QUAL_QAM_256_3_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_3_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3 -- --#define QAM_SL_QUAL_QAM_256_3_Q1__B 3 --#define QAM_SL_QUAL_QAM_256_3_Q1__W 3 --#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10 -- --#define QAM_SL_QUAL_QAM_256_3_Q2__B 6 --#define QAM_SL_QUAL_QAM_256_3_Q2__W 3 --#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_3_Q3__B 9 --#define QAM_SL_QUAL_QAM_256_3_Q3__W 3 --#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_4__A 0x143002E --#define QAM_SL_QUAL_QAM_256_4__W 15 --#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF --#define QAM_SL_QUAL_QAM_256_4__PRE 0x49 -- --#define QAM_SL_QUAL_QAM_256_4_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_4_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_256_4_Q1__B 3 --#define QAM_SL_QUAL_QAM_256_4_Q1__W 3 --#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8 -- --#define QAM_SL_QUAL_QAM_256_4_Q2__B 6 --#define QAM_SL_QUAL_QAM_256_4_Q2__W 3 --#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40 -- --#define QAM_SL_QUAL_QAM_256_4_Q3__B 9 --#define QAM_SL_QUAL_QAM_256_4_Q3__W 3 --#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_4_Q4__B 12 --#define QAM_SL_QUAL_QAM_256_4_Q4__W 3 --#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000 --#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_5__A 0x143002F --#define QAM_SL_QUAL_QAM_256_5__W 15 --#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF --#define QAM_SL_QUAL_QAM_256_5__PRE 0x59 -- --#define QAM_SL_QUAL_QAM_256_5_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_5_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1 -- --#define QAM_SL_QUAL_QAM_256_5_Q1__B 3 --#define QAM_SL_QUAL_QAM_256_5_Q1__W 3 --#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18 -- --#define QAM_SL_QUAL_QAM_256_5_Q2__B 6 --#define QAM_SL_QUAL_QAM_256_5_Q2__W 3 --#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40 -- --#define QAM_SL_QUAL_QAM_256_5_Q3__B 9 --#define QAM_SL_QUAL_QAM_256_5_Q3__W 3 --#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_5_Q4__B 12 --#define QAM_SL_QUAL_QAM_256_5_Q4__W 3 --#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000 --#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030 --#define QAM_SL_QUAL_QAM_256_5H__W 3 --#define QAM_SL_QUAL_QAM_256_5H__M 0x7 --#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0 --#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3 --#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7 --#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_6__A 0x1430031 --#define QAM_SL_QUAL_QAM_256_6__W 15 --#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF --#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A -- --#define QAM_SL_QUAL_QAM_256_6_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_6_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2 -- --#define QAM_SL_QUAL_QAM_256_6_Q1__B 3 --#define QAM_SL_QUAL_QAM_256_6_Q1__W 3 --#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18 -- --#define QAM_SL_QUAL_QAM_256_6_Q2__B 6 --#define QAM_SL_QUAL_QAM_256_6_Q2__W 3 --#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_6_Q3__B 9 --#define QAM_SL_QUAL_QAM_256_6_Q3__W 3 --#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200 -- --#define QAM_SL_QUAL_QAM_256_6_Q4__B 12 --#define QAM_SL_QUAL_QAM_256_6_Q4__W 3 --#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000 --#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032 --#define QAM_SL_QUAL_QAM_256_6H__W 6 --#define QAM_SL_QUAL_QAM_256_6H__M 0x3F --#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0 --#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3 --#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7 --#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3 --#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3 --#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38 --#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_7__A 0x1430033 --#define QAM_SL_QUAL_QAM_256_7__W 15 --#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF --#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D -- --#define QAM_SL_QUAL_QAM_256_7_Q0__B 0 --#define QAM_SL_QUAL_QAM_256_7_Q0__W 3 --#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7 --#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5 -- --#define QAM_SL_QUAL_QAM_256_7_Q1__B 3 --#define QAM_SL_QUAL_QAM_256_7_Q1__W 3 --#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38 --#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18 -- --#define QAM_SL_QUAL_QAM_256_7_Q2__B 6 --#define QAM_SL_QUAL_QAM_256_7_Q2__W 3 --#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0 --#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80 -- --#define QAM_SL_QUAL_QAM_256_7_Q3__B 9 --#define QAM_SL_QUAL_QAM_256_7_Q3__W 3 --#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00 --#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200 -- --#define QAM_SL_QUAL_QAM_256_7_Q4__B 12 --#define QAM_SL_QUAL_QAM_256_7_Q4__W 3 --#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000 --#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034 --#define QAM_SL_QUAL_QAM_256_7H__W 9 --#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF --#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0 --#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3 --#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7 --#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3 --#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3 --#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38 --#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0 -- --#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6 --#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3 --#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0 --#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0 -- -- -- --#define QAM_DQ_COMM_EXEC__A 0x1440000 --#define QAM_DQ_COMM_EXEC__W 2 --#define QAM_DQ_COMM_EXEC__M 0x3 --#define QAM_DQ_COMM_EXEC__PRE 0x0 --#define QAM_DQ_COMM_EXEC_STOP 0x0 --#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 --#define QAM_DQ_COMM_EXEC_HOLD 0x2 -- --#define QAM_DQ_MODE__A 0x1440010 --#define QAM_DQ_MODE__W 5 --#define QAM_DQ_MODE__M 0x1F --#define QAM_DQ_MODE__PRE 0x0 -- --#define QAM_DQ_MODE_TAPRESET__B 0 --#define QAM_DQ_MODE_TAPRESET__W 1 --#define QAM_DQ_MODE_TAPRESET__M 0x1 --#define QAM_DQ_MODE_TAPRESET__PRE 0x0 --#define QAM_DQ_MODE_TAPRESET_RST 0x1 -- --#define QAM_DQ_MODE_TAPLMS__B 1 --#define QAM_DQ_MODE_TAPLMS__W 1 --#define QAM_DQ_MODE_TAPLMS__M 0x2 --#define QAM_DQ_MODE_TAPLMS__PRE 0x0 --#define QAM_DQ_MODE_TAPLMS_UPD 0x2 -- --#define QAM_DQ_MODE_TAPDRAIN__B 2 --#define QAM_DQ_MODE_TAPDRAIN__W 1 --#define QAM_DQ_MODE_TAPDRAIN__M 0x4 --#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 --#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 -- --#define QAM_DQ_MODE_FB__B 3 --#define QAM_DQ_MODE_FB__W 2 --#define QAM_DQ_MODE_FB__M 0x18 --#define QAM_DQ_MODE_FB__PRE 0x0 --#define QAM_DQ_MODE_FB_CMA 0x0 --#define QAM_DQ_MODE_FB_RADIUS 0x8 --#define QAM_DQ_MODE_FB_DFB 0x10 --#define QAM_DQ_MODE_FB_TRELLIS 0x18 -- -- --#define QAM_DQ_MU_FACTOR__A 0x1440011 --#define QAM_DQ_MU_FACTOR__W 3 --#define QAM_DQ_MU_FACTOR__M 0x7 --#define QAM_DQ_MU_FACTOR__PRE 0x0 -- --#define QAM_DQ_LA_FACTOR__A 0x1440012 --#define QAM_DQ_LA_FACTOR__W 4 --#define QAM_DQ_LA_FACTOR__M 0xF --#define QAM_DQ_LA_FACTOR__PRE 0xC -- --#define QAM_DQ_CMA_RATIO__A 0x1440013 --#define QAM_DQ_CMA_RATIO__W 14 --#define QAM_DQ_CMA_RATIO__M 0x3FFF --#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 --#define QAM_DQ_CMA_RATIO_QPSK 0x2000 --#define QAM_DQ_CMA_RATIO_QAM16 0x34CD --#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 --#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D --#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 -- --#define QAM_DQ_QUAL_RADSEL__A 0x1440014 --#define QAM_DQ_QUAL_RADSEL__W 3 --#define QAM_DQ_QUAL_RADSEL__M 0x7 --#define QAM_DQ_QUAL_RADSEL__PRE 0x0 -- --#define QAM_DQ_QUAL_RADSEL_BIT__B 0 --#define QAM_DQ_QUAL_RADSEL_BIT__W 3 --#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 --#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 --#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 --#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 -- --#define QAM_DQ_QUAL_ENA__A 0x1440015 --#define QAM_DQ_QUAL_ENA__W 1 --#define QAM_DQ_QUAL_ENA__M 0x1 --#define QAM_DQ_QUAL_ENA__PRE 0x0 -- --#define QAM_DQ_QUAL_ENA_ENA__B 0 --#define QAM_DQ_QUAL_ENA_ENA__W 1 --#define QAM_DQ_QUAL_ENA_ENA__M 0x1 --#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 --#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 -- --#define QAM_DQ_QUAL_FUN0__A 0x1440018 --#define QAM_DQ_QUAL_FUN0__W 6 --#define QAM_DQ_QUAL_FUN0__M 0x3F --#define QAM_DQ_QUAL_FUN0__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN0_BIT__B 0 --#define QAM_DQ_QUAL_FUN0_BIT__W 6 --#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F --#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN1__A 0x1440019 --#define QAM_DQ_QUAL_FUN1__W 6 --#define QAM_DQ_QUAL_FUN1__M 0x3F --#define QAM_DQ_QUAL_FUN1__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN1_BIT__B 0 --#define QAM_DQ_QUAL_FUN1_BIT__W 6 --#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F --#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN2__A 0x144001A --#define QAM_DQ_QUAL_FUN2__W 6 --#define QAM_DQ_QUAL_FUN2__M 0x3F --#define QAM_DQ_QUAL_FUN2__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN2_BIT__B 0 --#define QAM_DQ_QUAL_FUN2_BIT__W 6 --#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F --#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN3__A 0x144001B --#define QAM_DQ_QUAL_FUN3__W 6 --#define QAM_DQ_QUAL_FUN3__M 0x3F --#define QAM_DQ_QUAL_FUN3__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN3_BIT__B 0 --#define QAM_DQ_QUAL_FUN3_BIT__W 6 --#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F --#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 -- --#define QAM_DQ_QUAL_FUN4__A 0x144001C --#define QAM_DQ_QUAL_FUN4__W 6 --#define QAM_DQ_QUAL_FUN4__M 0x3F --#define QAM_DQ_QUAL_FUN4__PRE 0x6 -- --#define QAM_DQ_QUAL_FUN4_BIT__B 0 --#define QAM_DQ_QUAL_FUN4_BIT__W 6 --#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F --#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 -- --#define QAM_DQ_QUAL_FUN5__A 0x144001D --#define QAM_DQ_QUAL_FUN5__W 6 --#define QAM_DQ_QUAL_FUN5__M 0x3F --#define QAM_DQ_QUAL_FUN5__PRE 0x6 -- --#define QAM_DQ_QUAL_FUN5_BIT__B 0 --#define QAM_DQ_QUAL_FUN5_BIT__W 6 --#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F --#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 -- --#define QAM_DQ_RAW_LIM__A 0x144001E --#define QAM_DQ_RAW_LIM__W 5 --#define QAM_DQ_RAW_LIM__M 0x1F --#define QAM_DQ_RAW_LIM__PRE 0x1F -- --#define QAM_DQ_RAW_LIM_BIT__B 0 --#define QAM_DQ_RAW_LIM_BIT__W 5 --#define QAM_DQ_RAW_LIM_BIT__M 0x1F --#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F -- --#define QAM_DQ_TAP_RE_EL0__A 0x1440020 --#define QAM_DQ_TAP_RE_EL0__W 12 --#define QAM_DQ_TAP_RE_EL0__M 0xFFF --#define QAM_DQ_TAP_RE_EL0__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL0_TAP__B 0 --#define QAM_DQ_TAP_RE_EL0_TAP__W 12 --#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL0__A 0x1440021 --#define QAM_DQ_TAP_IM_EL0__W 12 --#define QAM_DQ_TAP_IM_EL0__M 0xFFF --#define QAM_DQ_TAP_IM_EL0__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL0_TAP__B 0 --#define QAM_DQ_TAP_IM_EL0_TAP__W 12 --#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL1__A 0x1440022 --#define QAM_DQ_TAP_RE_EL1__W 12 --#define QAM_DQ_TAP_RE_EL1__M 0xFFF --#define QAM_DQ_TAP_RE_EL1__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL1_TAP__B 0 --#define QAM_DQ_TAP_RE_EL1_TAP__W 12 --#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL1__A 0x1440023 --#define QAM_DQ_TAP_IM_EL1__W 12 --#define QAM_DQ_TAP_IM_EL1__M 0xFFF --#define QAM_DQ_TAP_IM_EL1__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL1_TAP__B 0 --#define QAM_DQ_TAP_IM_EL1_TAP__W 12 --#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL2__A 0x1440024 --#define QAM_DQ_TAP_RE_EL2__W 12 --#define QAM_DQ_TAP_RE_EL2__M 0xFFF --#define QAM_DQ_TAP_RE_EL2__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL2_TAP__B 0 --#define QAM_DQ_TAP_RE_EL2_TAP__W 12 --#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL2__A 0x1440025 --#define QAM_DQ_TAP_IM_EL2__W 12 --#define QAM_DQ_TAP_IM_EL2__M 0xFFF --#define QAM_DQ_TAP_IM_EL2__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL2_TAP__B 0 --#define QAM_DQ_TAP_IM_EL2_TAP__W 12 --#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL3__A 0x1440026 --#define QAM_DQ_TAP_RE_EL3__W 12 --#define QAM_DQ_TAP_RE_EL3__M 0xFFF --#define QAM_DQ_TAP_RE_EL3__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL3_TAP__B 0 --#define QAM_DQ_TAP_RE_EL3_TAP__W 12 --#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL3__A 0x1440027 --#define QAM_DQ_TAP_IM_EL3__W 12 --#define QAM_DQ_TAP_IM_EL3__M 0xFFF --#define QAM_DQ_TAP_IM_EL3__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL3_TAP__B 0 --#define QAM_DQ_TAP_IM_EL3_TAP__W 12 --#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL4__A 0x1440028 --#define QAM_DQ_TAP_RE_EL4__W 12 --#define QAM_DQ_TAP_RE_EL4__M 0xFFF --#define QAM_DQ_TAP_RE_EL4__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL4_TAP__B 0 --#define QAM_DQ_TAP_RE_EL4_TAP__W 12 --#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL4__A 0x1440029 --#define QAM_DQ_TAP_IM_EL4__W 12 --#define QAM_DQ_TAP_IM_EL4__M 0xFFF --#define QAM_DQ_TAP_IM_EL4__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL4_TAP__B 0 --#define QAM_DQ_TAP_IM_EL4_TAP__W 12 --#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL5__A 0x144002A --#define QAM_DQ_TAP_RE_EL5__W 12 --#define QAM_DQ_TAP_RE_EL5__M 0xFFF --#define QAM_DQ_TAP_RE_EL5__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL5_TAP__B 0 --#define QAM_DQ_TAP_RE_EL5_TAP__W 12 --#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL5__A 0x144002B --#define QAM_DQ_TAP_IM_EL5__W 12 --#define QAM_DQ_TAP_IM_EL5__M 0xFFF --#define QAM_DQ_TAP_IM_EL5__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL5_TAP__B 0 --#define QAM_DQ_TAP_IM_EL5_TAP__W 12 --#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL6__A 0x144002C --#define QAM_DQ_TAP_RE_EL6__W 12 --#define QAM_DQ_TAP_RE_EL6__M 0xFFF --#define QAM_DQ_TAP_RE_EL6__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL6_TAP__B 0 --#define QAM_DQ_TAP_RE_EL6_TAP__W 12 --#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL6__A 0x144002D --#define QAM_DQ_TAP_IM_EL6__W 12 --#define QAM_DQ_TAP_IM_EL6__M 0xFFF --#define QAM_DQ_TAP_IM_EL6__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL6_TAP__B 0 --#define QAM_DQ_TAP_IM_EL6_TAP__W 12 --#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL7__A 0x144002E --#define QAM_DQ_TAP_RE_EL7__W 12 --#define QAM_DQ_TAP_RE_EL7__M 0xFFF --#define QAM_DQ_TAP_RE_EL7__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL7_TAP__B 0 --#define QAM_DQ_TAP_RE_EL7_TAP__W 12 --#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL7__A 0x144002F --#define QAM_DQ_TAP_IM_EL7__W 12 --#define QAM_DQ_TAP_IM_EL7__M 0xFFF --#define QAM_DQ_TAP_IM_EL7__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL7_TAP__B 0 --#define QAM_DQ_TAP_IM_EL7_TAP__W 12 --#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL8__A 0x1440030 --#define QAM_DQ_TAP_RE_EL8__W 12 --#define QAM_DQ_TAP_RE_EL8__M 0xFFF --#define QAM_DQ_TAP_RE_EL8__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL8_TAP__B 0 --#define QAM_DQ_TAP_RE_EL8_TAP__W 12 --#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL8__A 0x1440031 --#define QAM_DQ_TAP_IM_EL8__W 12 --#define QAM_DQ_TAP_IM_EL8__M 0xFFF --#define QAM_DQ_TAP_IM_EL8__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL8_TAP__B 0 --#define QAM_DQ_TAP_IM_EL8_TAP__W 12 --#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL9__A 0x1440032 --#define QAM_DQ_TAP_RE_EL9__W 12 --#define QAM_DQ_TAP_RE_EL9__M 0xFFF --#define QAM_DQ_TAP_RE_EL9__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL9_TAP__B 0 --#define QAM_DQ_TAP_RE_EL9_TAP__W 12 --#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL9__A 0x1440033 --#define QAM_DQ_TAP_IM_EL9__W 12 --#define QAM_DQ_TAP_IM_EL9__M 0xFFF --#define QAM_DQ_TAP_IM_EL9__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL9_TAP__B 0 --#define QAM_DQ_TAP_IM_EL9_TAP__W 12 --#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL10__A 0x1440034 --#define QAM_DQ_TAP_RE_EL10__W 12 --#define QAM_DQ_TAP_RE_EL10__M 0xFFF --#define QAM_DQ_TAP_RE_EL10__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL10_TAP__B 0 --#define QAM_DQ_TAP_RE_EL10_TAP__W 12 --#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL10__A 0x1440035 --#define QAM_DQ_TAP_IM_EL10__W 12 --#define QAM_DQ_TAP_IM_EL10__M 0xFFF --#define QAM_DQ_TAP_IM_EL10__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL10_TAP__B 0 --#define QAM_DQ_TAP_IM_EL10_TAP__W 12 --#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL11__A 0x1440036 --#define QAM_DQ_TAP_RE_EL11__W 12 --#define QAM_DQ_TAP_RE_EL11__M 0xFFF --#define QAM_DQ_TAP_RE_EL11__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL11_TAP__B 0 --#define QAM_DQ_TAP_RE_EL11_TAP__W 12 --#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL11__A 0x1440037 --#define QAM_DQ_TAP_IM_EL11__W 12 --#define QAM_DQ_TAP_IM_EL11__M 0xFFF --#define QAM_DQ_TAP_IM_EL11__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL11_TAP__B 0 --#define QAM_DQ_TAP_IM_EL11_TAP__W 12 --#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL12__A 0x1440038 --#define QAM_DQ_TAP_RE_EL12__W 12 --#define QAM_DQ_TAP_RE_EL12__M 0xFFF --#define QAM_DQ_TAP_RE_EL12__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL12_TAP__B 0 --#define QAM_DQ_TAP_RE_EL12_TAP__W 12 --#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL12__A 0x1440039 --#define QAM_DQ_TAP_IM_EL12__W 12 --#define QAM_DQ_TAP_IM_EL12__M 0xFFF --#define QAM_DQ_TAP_IM_EL12__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL12_TAP__B 0 --#define QAM_DQ_TAP_IM_EL12_TAP__W 12 --#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL13__A 0x144003A --#define QAM_DQ_TAP_RE_EL13__W 12 --#define QAM_DQ_TAP_RE_EL13__M 0xFFF --#define QAM_DQ_TAP_RE_EL13__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL13_TAP__B 0 --#define QAM_DQ_TAP_RE_EL13_TAP__W 12 --#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL13__A 0x144003B --#define QAM_DQ_TAP_IM_EL13__W 12 --#define QAM_DQ_TAP_IM_EL13__M 0xFFF --#define QAM_DQ_TAP_IM_EL13__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL13_TAP__B 0 --#define QAM_DQ_TAP_IM_EL13_TAP__W 12 --#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL14__A 0x144003C --#define QAM_DQ_TAP_RE_EL14__W 12 --#define QAM_DQ_TAP_RE_EL14__M 0xFFF --#define QAM_DQ_TAP_RE_EL14__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL14_TAP__B 0 --#define QAM_DQ_TAP_RE_EL14_TAP__W 12 --#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL14__A 0x144003D --#define QAM_DQ_TAP_IM_EL14__W 12 --#define QAM_DQ_TAP_IM_EL14__M 0xFFF --#define QAM_DQ_TAP_IM_EL14__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL14_TAP__B 0 --#define QAM_DQ_TAP_IM_EL14_TAP__W 12 --#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL15__A 0x144003E --#define QAM_DQ_TAP_RE_EL15__W 12 --#define QAM_DQ_TAP_RE_EL15__M 0xFFF --#define QAM_DQ_TAP_RE_EL15__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL15_TAP__B 0 --#define QAM_DQ_TAP_RE_EL15_TAP__W 12 --#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL15__A 0x144003F --#define QAM_DQ_TAP_IM_EL15__W 12 --#define QAM_DQ_TAP_IM_EL15__M 0xFFF --#define QAM_DQ_TAP_IM_EL15__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL15_TAP__B 0 --#define QAM_DQ_TAP_IM_EL15_TAP__W 12 --#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL16__A 0x1440040 --#define QAM_DQ_TAP_RE_EL16__W 12 --#define QAM_DQ_TAP_RE_EL16__M 0xFFF --#define QAM_DQ_TAP_RE_EL16__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL16_TAP__B 0 --#define QAM_DQ_TAP_RE_EL16_TAP__W 12 --#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL16__A 0x1440041 --#define QAM_DQ_TAP_IM_EL16__W 12 --#define QAM_DQ_TAP_IM_EL16__M 0xFFF --#define QAM_DQ_TAP_IM_EL16__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL16_TAP__B 0 --#define QAM_DQ_TAP_IM_EL16_TAP__W 12 --#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL17__A 0x1440042 --#define QAM_DQ_TAP_RE_EL17__W 12 --#define QAM_DQ_TAP_RE_EL17__M 0xFFF --#define QAM_DQ_TAP_RE_EL17__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL17_TAP__B 0 --#define QAM_DQ_TAP_RE_EL17_TAP__W 12 --#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL17__A 0x1440043 --#define QAM_DQ_TAP_IM_EL17__W 12 --#define QAM_DQ_TAP_IM_EL17__M 0xFFF --#define QAM_DQ_TAP_IM_EL17__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL17_TAP__B 0 --#define QAM_DQ_TAP_IM_EL17_TAP__W 12 --#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL18__A 0x1440044 --#define QAM_DQ_TAP_RE_EL18__W 12 --#define QAM_DQ_TAP_RE_EL18__M 0xFFF --#define QAM_DQ_TAP_RE_EL18__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL18_TAP__B 0 --#define QAM_DQ_TAP_RE_EL18_TAP__W 12 --#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL18__A 0x1440045 --#define QAM_DQ_TAP_IM_EL18__W 12 --#define QAM_DQ_TAP_IM_EL18__M 0xFFF --#define QAM_DQ_TAP_IM_EL18__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL18_TAP__B 0 --#define QAM_DQ_TAP_IM_EL18_TAP__W 12 --#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL19__A 0x1440046 --#define QAM_DQ_TAP_RE_EL19__W 12 --#define QAM_DQ_TAP_RE_EL19__M 0xFFF --#define QAM_DQ_TAP_RE_EL19__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL19_TAP__B 0 --#define QAM_DQ_TAP_RE_EL19_TAP__W 12 --#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL19__A 0x1440047 --#define QAM_DQ_TAP_IM_EL19__W 12 --#define QAM_DQ_TAP_IM_EL19__M 0xFFF --#define QAM_DQ_TAP_IM_EL19__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL19_TAP__B 0 --#define QAM_DQ_TAP_IM_EL19_TAP__W 12 --#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL20__A 0x1440048 --#define QAM_DQ_TAP_RE_EL20__W 12 --#define QAM_DQ_TAP_RE_EL20__M 0xFFF --#define QAM_DQ_TAP_RE_EL20__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL20_TAP__B 0 --#define QAM_DQ_TAP_RE_EL20_TAP__W 12 --#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL20__A 0x1440049 --#define QAM_DQ_TAP_IM_EL20__W 12 --#define QAM_DQ_TAP_IM_EL20__M 0xFFF --#define QAM_DQ_TAP_IM_EL20__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL20_TAP__B 0 --#define QAM_DQ_TAP_IM_EL20_TAP__W 12 --#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL21__A 0x144004A --#define QAM_DQ_TAP_RE_EL21__W 12 --#define QAM_DQ_TAP_RE_EL21__M 0xFFF --#define QAM_DQ_TAP_RE_EL21__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL21_TAP__B 0 --#define QAM_DQ_TAP_RE_EL21_TAP__W 12 --#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL21__A 0x144004B --#define QAM_DQ_TAP_IM_EL21__W 12 --#define QAM_DQ_TAP_IM_EL21__M 0xFFF --#define QAM_DQ_TAP_IM_EL21__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL21_TAP__B 0 --#define QAM_DQ_TAP_IM_EL21_TAP__W 12 --#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL22__A 0x144004C --#define QAM_DQ_TAP_RE_EL22__W 12 --#define QAM_DQ_TAP_RE_EL22__M 0xFFF --#define QAM_DQ_TAP_RE_EL22__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL22_TAP__B 0 --#define QAM_DQ_TAP_RE_EL22_TAP__W 12 --#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL22__A 0x144004D --#define QAM_DQ_TAP_IM_EL22__W 12 --#define QAM_DQ_TAP_IM_EL22__M 0xFFF --#define QAM_DQ_TAP_IM_EL22__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL22_TAP__B 0 --#define QAM_DQ_TAP_IM_EL22_TAP__W 12 --#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL23__A 0x144004E --#define QAM_DQ_TAP_RE_EL23__W 12 --#define QAM_DQ_TAP_RE_EL23__M 0xFFF --#define QAM_DQ_TAP_RE_EL23__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL23_TAP__B 0 --#define QAM_DQ_TAP_RE_EL23_TAP__W 12 --#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL23__A 0x144004F --#define QAM_DQ_TAP_IM_EL23__W 12 --#define QAM_DQ_TAP_IM_EL23__M 0xFFF --#define QAM_DQ_TAP_IM_EL23__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL23_TAP__B 0 --#define QAM_DQ_TAP_IM_EL23_TAP__W 12 --#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL24__A 0x1440050 --#define QAM_DQ_TAP_RE_EL24__W 12 --#define QAM_DQ_TAP_RE_EL24__M 0xFFF --#define QAM_DQ_TAP_RE_EL24__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL24_TAP__B 0 --#define QAM_DQ_TAP_RE_EL24_TAP__W 12 --#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL24__A 0x1440051 --#define QAM_DQ_TAP_IM_EL24__W 12 --#define QAM_DQ_TAP_IM_EL24__M 0xFFF --#define QAM_DQ_TAP_IM_EL24__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL24_TAP__B 0 --#define QAM_DQ_TAP_IM_EL24_TAP__W 12 --#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL25__A 0x1440052 --#define QAM_DQ_TAP_RE_EL25__W 12 --#define QAM_DQ_TAP_RE_EL25__M 0xFFF --#define QAM_DQ_TAP_RE_EL25__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL25_TAP__B 0 --#define QAM_DQ_TAP_RE_EL25_TAP__W 12 --#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL25__A 0x1440053 --#define QAM_DQ_TAP_IM_EL25__W 12 --#define QAM_DQ_TAP_IM_EL25__M 0xFFF --#define QAM_DQ_TAP_IM_EL25__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL25_TAP__B 0 --#define QAM_DQ_TAP_IM_EL25_TAP__W 12 --#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL26__A 0x1440054 --#define QAM_DQ_TAP_RE_EL26__W 12 --#define QAM_DQ_TAP_RE_EL26__M 0xFFF --#define QAM_DQ_TAP_RE_EL26__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL26_TAP__B 0 --#define QAM_DQ_TAP_RE_EL26_TAP__W 12 --#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL26__A 0x1440055 --#define QAM_DQ_TAP_IM_EL26__W 12 --#define QAM_DQ_TAP_IM_EL26__M 0xFFF --#define QAM_DQ_TAP_IM_EL26__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL26_TAP__B 0 --#define QAM_DQ_TAP_IM_EL26_TAP__W 12 --#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL27__A 0x1440056 --#define QAM_DQ_TAP_RE_EL27__W 12 --#define QAM_DQ_TAP_RE_EL27__M 0xFFF --#define QAM_DQ_TAP_RE_EL27__PRE 0x2 -- --#define QAM_DQ_TAP_RE_EL27_TAP__B 0 --#define QAM_DQ_TAP_RE_EL27_TAP__W 12 --#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF --#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL27__A 0x1440057 --#define QAM_DQ_TAP_IM_EL27__W 12 --#define QAM_DQ_TAP_IM_EL27__M 0xFFF --#define QAM_DQ_TAP_IM_EL27__PRE 0x2 -- --#define QAM_DQ_TAP_IM_EL27_TAP__B 0 --#define QAM_DQ_TAP_IM_EL27_TAP__W 12 --#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF --#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 -- -- -- --#define QAM_LC_COMM_EXEC__A 0x1450000 --#define QAM_LC_COMM_EXEC__W 2 --#define QAM_LC_COMM_EXEC__M 0x3 --#define QAM_LC_COMM_EXEC__PRE 0x0 --#define QAM_LC_COMM_EXEC_STOP 0x0 --#define QAM_LC_COMM_EXEC_ACTIVE 0x1 --#define QAM_LC_COMM_EXEC_HOLD 0x2 -- --#define QAM_LC_COMM_MB__A 0x1450002 --#define QAM_LC_COMM_MB__W 2 --#define QAM_LC_COMM_MB__M 0x3 --#define QAM_LC_COMM_MB__PRE 0x0 --#define QAM_LC_COMM_MB_CTL__B 0 --#define QAM_LC_COMM_MB_CTL__W 1 --#define QAM_LC_COMM_MB_CTL__M 0x1 --#define QAM_LC_COMM_MB_CTL__PRE 0x0 --#define QAM_LC_COMM_MB_CTL_OFF 0x0 --#define QAM_LC_COMM_MB_CTL_ON 0x1 --#define QAM_LC_COMM_MB_OBS__B 1 --#define QAM_LC_COMM_MB_OBS__W 1 --#define QAM_LC_COMM_MB_OBS__M 0x2 --#define QAM_LC_COMM_MB_OBS__PRE 0x0 --#define QAM_LC_COMM_MB_OBS_OFF 0x0 --#define QAM_LC_COMM_MB_OBS_ON 0x2 -- --#define QAM_LC_COMM_INT_REQ__A 0x1450003 --#define QAM_LC_COMM_INT_REQ__W 1 --#define QAM_LC_COMM_INT_REQ__M 0x1 --#define QAM_LC_COMM_INT_REQ__PRE 0x0 --#define QAM_LC_COMM_INT_STA__A 0x1450005 --#define QAM_LC_COMM_INT_STA__W 3 --#define QAM_LC_COMM_INT_STA__M 0x7 --#define QAM_LC_COMM_INT_STA__PRE 0x0 -- --#define QAM_LC_COMM_INT_STA_READY__B 0 --#define QAM_LC_COMM_INT_STA_READY__W 1 --#define QAM_LC_COMM_INT_STA_READY__M 0x1 --#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 -- --#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 --#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 --#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 --#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 -- --#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 --#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 --#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 --#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 -- --#define QAM_LC_COMM_INT_MSK__A 0x1450006 --#define QAM_LC_COMM_INT_MSK__W 3 --#define QAM_LC_COMM_INT_MSK__M 0x7 --#define QAM_LC_COMM_INT_MSK__PRE 0x0 --#define QAM_LC_COMM_INT_MSK_READY__B 0 --#define QAM_LC_COMM_INT_MSK_READY__W 1 --#define QAM_LC_COMM_INT_MSK_READY__M 0x1 --#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 --#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 --#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 --#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 --#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 --#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 --#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 --#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 --#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 -- --#define QAM_LC_COMM_INT_STM__A 0x1450007 --#define QAM_LC_COMM_INT_STM__W 3 --#define QAM_LC_COMM_INT_STM__M 0x7 --#define QAM_LC_COMM_INT_STM__PRE 0x0 --#define QAM_LC_COMM_INT_STM_READY__B 0 --#define QAM_LC_COMM_INT_STM_READY__W 1 --#define QAM_LC_COMM_INT_STM_READY__M 0x1 --#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 --#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 --#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 --#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 --#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 --#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 --#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 --#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 --#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 -- --#define QAM_LC_MODE__A 0x1450010 --#define QAM_LC_MODE__W 4 --#define QAM_LC_MODE__M 0xF --#define QAM_LC_MODE__PRE 0xE -- --#define QAM_LC_MODE_ENABLE_A__B 0 --#define QAM_LC_MODE_ENABLE_A__W 1 --#define QAM_LC_MODE_ENABLE_A__M 0x1 --#define QAM_LC_MODE_ENABLE_A__PRE 0x0 -- --#define QAM_LC_MODE_ENABLE_F__B 1 --#define QAM_LC_MODE_ENABLE_F__W 1 --#define QAM_LC_MODE_ENABLE_F__M 0x2 --#define QAM_LC_MODE_ENABLE_F__PRE 0x2 -- --#define QAM_LC_MODE_ENABLE_R__B 2 --#define QAM_LC_MODE_ENABLE_R__W 1 --#define QAM_LC_MODE_ENABLE_R__M 0x4 --#define QAM_LC_MODE_ENABLE_R__PRE 0x4 -- --#define QAM_LC_MODE_ENABLE_PQUAL__B 3 --#define QAM_LC_MODE_ENABLE_PQUAL__W 1 --#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8 --#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8 -- --#define QAM_LC_CA__A 0x1450011 --#define QAM_LC_CA__W 6 --#define QAM_LC_CA__M 0x3F --#define QAM_LC_CA__PRE 0x28 -- --#define QAM_LC_CA_COEF__B 0 --#define QAM_LC_CA_COEF__W 6 --#define QAM_LC_CA_COEF__M 0x3F --#define QAM_LC_CA_COEF__PRE 0x28 -- --#define QAM_LC_CF__A 0x1450012 --#define QAM_LC_CF__W 8 --#define QAM_LC_CF__M 0xFF --#define QAM_LC_CF__PRE 0x30 -- --#define QAM_LC_CF_COEF__B 0 --#define QAM_LC_CF_COEF__W 8 --#define QAM_LC_CF_COEF__M 0xFF --#define QAM_LC_CF_COEF__PRE 0x30 -- --#define QAM_LC_CF1__A 0x1450013 --#define QAM_LC_CF1__W 8 --#define QAM_LC_CF1__M 0xFF --#define QAM_LC_CF1__PRE 0x14 -- --#define QAM_LC_CF1_COEF__B 0 --#define QAM_LC_CF1_COEF__W 8 --#define QAM_LC_CF1_COEF__M 0xFF --#define QAM_LC_CF1_COEF__PRE 0x14 -- --#define QAM_LC_CP__A 0x1450014 --#define QAM_LC_CP__W 8 --#define QAM_LC_CP__M 0xFF --#define QAM_LC_CP__PRE 0x64 -- --#define QAM_LC_CP_COEF__B 0 --#define QAM_LC_CP_COEF__W 8 --#define QAM_LC_CP_COEF__M 0xFF --#define QAM_LC_CP_COEF__PRE 0x64 -- --#define QAM_LC_CI__A 0x1450015 --#define QAM_LC_CI__W 8 --#define QAM_LC_CI__M 0xFF --#define QAM_LC_CI__PRE 0x32 -- --#define QAM_LC_CI_COEF__B 0 --#define QAM_LC_CI_COEF__W 8 --#define QAM_LC_CI_COEF__M 0xFF --#define QAM_LC_CI_COEF__PRE 0x32 -- --#define QAM_LC_EP__A 0x1450016 --#define QAM_LC_EP__W 6 --#define QAM_LC_EP__M 0x3F --#define QAM_LC_EP__PRE 0x0 -- --#define QAM_LC_EP_COEF__B 0 --#define QAM_LC_EP_COEF__W 6 --#define QAM_LC_EP_COEF__M 0x3F --#define QAM_LC_EP_COEF__PRE 0x0 -- --#define QAM_LC_EI__A 0x1450017 --#define QAM_LC_EI__W 6 --#define QAM_LC_EI__M 0x3F --#define QAM_LC_EI__PRE 0x0 -- --#define QAM_LC_EI_COEF__B 0 --#define QAM_LC_EI_COEF__W 6 --#define QAM_LC_EI_COEF__M 0x3F --#define QAM_LC_EI_COEF__PRE 0x0 -- --#define QAM_LC_QUAL_TAB0__A 0x1450018 --#define QAM_LC_QUAL_TAB0__W 5 --#define QAM_LC_QUAL_TAB0__M 0x1F --#define QAM_LC_QUAL_TAB0__PRE 0x0 -- --#define QAM_LC_QUAL_TAB0_VALUE__B 0 --#define QAM_LC_QUAL_TAB0_VALUE__W 5 --#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 -- --#define QAM_LC_QUAL_TAB1__A 0x1450019 --#define QAM_LC_QUAL_TAB1__W 5 --#define QAM_LC_QUAL_TAB1__M 0x1F --#define QAM_LC_QUAL_TAB1__PRE 0x1 -- --#define QAM_LC_QUAL_TAB1_VALUE__B 0 --#define QAM_LC_QUAL_TAB1_VALUE__W 5 --#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 -- --#define QAM_LC_QUAL_TAB2__A 0x145001A --#define QAM_LC_QUAL_TAB2__W 5 --#define QAM_LC_QUAL_TAB2__M 0x1F --#define QAM_LC_QUAL_TAB2__PRE 0x2 -- --#define QAM_LC_QUAL_TAB2_VALUE__B 0 --#define QAM_LC_QUAL_TAB2_VALUE__W 5 --#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 -- --#define QAM_LC_QUAL_TAB3__A 0x145001B --#define QAM_LC_QUAL_TAB3__W 5 --#define QAM_LC_QUAL_TAB3__M 0x1F --#define QAM_LC_QUAL_TAB3__PRE 0x3 -- --#define QAM_LC_QUAL_TAB3_VALUE__B 0 --#define QAM_LC_QUAL_TAB3_VALUE__W 5 --#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 -- --#define QAM_LC_QUAL_TAB4__A 0x145001C --#define QAM_LC_QUAL_TAB4__W 5 --#define QAM_LC_QUAL_TAB4__M 0x1F --#define QAM_LC_QUAL_TAB4__PRE 0x4 -- --#define QAM_LC_QUAL_TAB4_VALUE__B 0 --#define QAM_LC_QUAL_TAB4_VALUE__W 5 --#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 -- --#define QAM_LC_QUAL_TAB5__A 0x145001D --#define QAM_LC_QUAL_TAB5__W 5 --#define QAM_LC_QUAL_TAB5__M 0x1F --#define QAM_LC_QUAL_TAB5__PRE 0x5 -- --#define QAM_LC_QUAL_TAB5_VALUE__B 0 --#define QAM_LC_QUAL_TAB5_VALUE__W 5 --#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 -- --#define QAM_LC_QUAL_TAB6__A 0x145001E --#define QAM_LC_QUAL_TAB6__W 5 --#define QAM_LC_QUAL_TAB6__M 0x1F --#define QAM_LC_QUAL_TAB6__PRE 0x6 -- --#define QAM_LC_QUAL_TAB6_VALUE__B 0 --#define QAM_LC_QUAL_TAB6_VALUE__W 5 --#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 -- --#define QAM_LC_QUAL_TAB8__A 0x145001F --#define QAM_LC_QUAL_TAB8__W 5 --#define QAM_LC_QUAL_TAB8__M 0x1F --#define QAM_LC_QUAL_TAB8__PRE 0x8 -- --#define QAM_LC_QUAL_TAB8_VALUE__B 0 --#define QAM_LC_QUAL_TAB8_VALUE__W 5 --#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 -- --#define QAM_LC_QUAL_TAB9__A 0x1450020 --#define QAM_LC_QUAL_TAB9__W 5 --#define QAM_LC_QUAL_TAB9__M 0x1F --#define QAM_LC_QUAL_TAB9__PRE 0x9 -- --#define QAM_LC_QUAL_TAB9_VALUE__B 0 --#define QAM_LC_QUAL_TAB9_VALUE__W 5 --#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 -- --#define QAM_LC_QUAL_TAB10__A 0x1450021 --#define QAM_LC_QUAL_TAB10__W 5 --#define QAM_LC_QUAL_TAB10__M 0x1F --#define QAM_LC_QUAL_TAB10__PRE 0xA -- --#define QAM_LC_QUAL_TAB10_VALUE__B 0 --#define QAM_LC_QUAL_TAB10_VALUE__W 5 --#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA -- --#define QAM_LC_QUAL_TAB12__A 0x1450022 --#define QAM_LC_QUAL_TAB12__W 5 --#define QAM_LC_QUAL_TAB12__M 0x1F --#define QAM_LC_QUAL_TAB12__PRE 0xC -- --#define QAM_LC_QUAL_TAB12_VALUE__B 0 --#define QAM_LC_QUAL_TAB12_VALUE__W 5 --#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC -- --#define QAM_LC_QUAL_TAB15__A 0x1450023 --#define QAM_LC_QUAL_TAB15__W 5 --#define QAM_LC_QUAL_TAB15__M 0x1F --#define QAM_LC_QUAL_TAB15__PRE 0xF -- --#define QAM_LC_QUAL_TAB15_VALUE__B 0 --#define QAM_LC_QUAL_TAB15_VALUE__W 5 --#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF -- --#define QAM_LC_QUAL_TAB16__A 0x1450024 --#define QAM_LC_QUAL_TAB16__W 5 --#define QAM_LC_QUAL_TAB16__M 0x1F --#define QAM_LC_QUAL_TAB16__PRE 0x10 -- --#define QAM_LC_QUAL_TAB16_VALUE__B 0 --#define QAM_LC_QUAL_TAB16_VALUE__W 5 --#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 -- --#define QAM_LC_QUAL_TAB20__A 0x1450025 --#define QAM_LC_QUAL_TAB20__W 5 --#define QAM_LC_QUAL_TAB20__M 0x1F --#define QAM_LC_QUAL_TAB20__PRE 0x14 -- --#define QAM_LC_QUAL_TAB20_VALUE__B 0 --#define QAM_LC_QUAL_TAB20_VALUE__W 5 --#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 -- --#define QAM_LC_QUAL_TAB25__A 0x1450026 --#define QAM_LC_QUAL_TAB25__W 5 --#define QAM_LC_QUAL_TAB25__M 0x1F --#define QAM_LC_QUAL_TAB25__PRE 0x19 -- --#define QAM_LC_QUAL_TAB25_VALUE__B 0 --#define QAM_LC_QUAL_TAB25_VALUE__W 5 --#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F --#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 -- --#define QAM_LC_EQ_TIMING__A 0x1450027 --#define QAM_LC_EQ_TIMING__W 10 --#define QAM_LC_EQ_TIMING__M 0x3FF --#define QAM_LC_EQ_TIMING__PRE 0x0 -- --#define QAM_LC_EQ_TIMING_OFFS__B 0 --#define QAM_LC_EQ_TIMING_OFFS__W 10 --#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF --#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 -- --#define QAM_LC_LPF_FACTORP__A 0x1450028 --#define QAM_LC_LPF_FACTORP__W 3 --#define QAM_LC_LPF_FACTORP__M 0x7 --#define QAM_LC_LPF_FACTORP__PRE 0x3 -- --#define QAM_LC_LPF_FACTORP_FACTOR__B 0 --#define QAM_LC_LPF_FACTORP_FACTOR__W 3 --#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 --#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 -- --#define QAM_LC_LPF_FACTORI__A 0x1450029 --#define QAM_LC_LPF_FACTORI__W 3 --#define QAM_LC_LPF_FACTORI__M 0x7 --#define QAM_LC_LPF_FACTORI__PRE 0x3 -- --#define QAM_LC_LPF_FACTORI_FACTOR__B 0 --#define QAM_LC_LPF_FACTORI_FACTOR__W 3 --#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 --#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 -- --#define QAM_LC_RATE_LIMIT__A 0x145002A --#define QAM_LC_RATE_LIMIT__W 2 --#define QAM_LC_RATE_LIMIT__M 0x3 --#define QAM_LC_RATE_LIMIT__PRE 0x3 -- --#define QAM_LC_RATE_LIMIT_LIMIT__B 0 --#define QAM_LC_RATE_LIMIT_LIMIT__W 2 --#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 --#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 -- --#define QAM_LC_SYMBOL_FREQ__A 0x145002B --#define QAM_LC_SYMBOL_FREQ__W 10 --#define QAM_LC_SYMBOL_FREQ__M 0x3FF --#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF -- --#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 --#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 --#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF --#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF -- --#define QAM_LC_MTA_LENGTH__A 0x145002C --#define QAM_LC_MTA_LENGTH__W 2 --#define QAM_LC_MTA_LENGTH__M 0x3 --#define QAM_LC_MTA_LENGTH__PRE 0x2 -- --#define QAM_LC_MTA_LENGTH_LENGTH__B 0 --#define QAM_LC_MTA_LENGTH_LENGTH__W 2 --#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 --#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 -- --#define QAM_LC_AMP_ACCU__A 0x145002D --#define QAM_LC_AMP_ACCU__W 14 --#define QAM_LC_AMP_ACCU__M 0x3FFF --#define QAM_LC_AMP_ACCU__PRE 0x600 -- --#define QAM_LC_AMP_ACCU_ACCU__B 0 --#define QAM_LC_AMP_ACCU_ACCU__W 14 --#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF --#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 -- --#define QAM_LC_FREQ_ACCU__A 0x145002E --#define QAM_LC_FREQ_ACCU__W 10 --#define QAM_LC_FREQ_ACCU__M 0x3FF --#define QAM_LC_FREQ_ACCU__PRE 0x0 -- --#define QAM_LC_FREQ_ACCU_ACCU__B 0 --#define QAM_LC_FREQ_ACCU_ACCU__W 10 --#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF --#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 -- --#define QAM_LC_RATE_ACCU__A 0x145002F --#define QAM_LC_RATE_ACCU__W 10 --#define QAM_LC_RATE_ACCU__M 0x3FF --#define QAM_LC_RATE_ACCU__PRE 0x0 -- --#define QAM_LC_RATE_ACCU_ACCU__B 0 --#define QAM_LC_RATE_ACCU_ACCU__W 10 --#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF --#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 -- --#define QAM_LC_AMPLITUDE__A 0x1450030 --#define QAM_LC_AMPLITUDE__W 10 --#define QAM_LC_AMPLITUDE__M 0x3FF --#define QAM_LC_AMPLITUDE__PRE 0x0 -- --#define QAM_LC_AMPLITUDE_SIZE__B 0 --#define QAM_LC_AMPLITUDE_SIZE__W 10 --#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF --#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 -- --#define QAM_LC_RAD_ERROR__A 0x1450031 --#define QAM_LC_RAD_ERROR__W 10 --#define QAM_LC_RAD_ERROR__M 0x3FF --#define QAM_LC_RAD_ERROR__PRE 0x0 -- --#define QAM_LC_RAD_ERROR_SIZE__B 0 --#define QAM_LC_RAD_ERROR_SIZE__W 10 --#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF --#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 -- --#define QAM_LC_FREQ_OFFS__A 0x1450032 --#define QAM_LC_FREQ_OFFS__W 10 --#define QAM_LC_FREQ_OFFS__M 0x3FF --#define QAM_LC_FREQ_OFFS__PRE 0x0 -- --#define QAM_LC_FREQ_OFFS_OFFS__B 0 --#define QAM_LC_FREQ_OFFS_OFFS__W 10 --#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF --#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 -- --#define QAM_LC_PHASE_ERROR__A 0x1450033 --#define QAM_LC_PHASE_ERROR__W 10 --#define QAM_LC_PHASE_ERROR__M 0x3FF --#define QAM_LC_PHASE_ERROR__PRE 0x0 -- --#define QAM_LC_PHASE_ERROR_SIZE__B 0 --#define QAM_LC_PHASE_ERROR_SIZE__W 10 --#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF --#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 -- -- -- --#define QAM_SY_COMM_EXEC__A 0x1470000 --#define QAM_SY_COMM_EXEC__W 2 --#define QAM_SY_COMM_EXEC__M 0x3 --#define QAM_SY_COMM_EXEC__PRE 0x0 --#define QAM_SY_COMM_EXEC_STOP 0x0 --#define QAM_SY_COMM_EXEC_ACTIVE 0x1 --#define QAM_SY_COMM_EXEC_HOLD 0x2 -- --#define QAM_SY_COMM_MB__A 0x1470002 --#define QAM_SY_COMM_MB__W 4 --#define QAM_SY_COMM_MB__M 0xF --#define QAM_SY_COMM_MB__PRE 0x0 --#define QAM_SY_COMM_MB_CTL__B 0 --#define QAM_SY_COMM_MB_CTL__W 1 --#define QAM_SY_COMM_MB_CTL__M 0x1 --#define QAM_SY_COMM_MB_CTL__PRE 0x0 --#define QAM_SY_COMM_MB_CTL_OFF 0x0 --#define QAM_SY_COMM_MB_CTL_ON 0x1 --#define QAM_SY_COMM_MB_OBS__B 1 --#define QAM_SY_COMM_MB_OBS__W 1 --#define QAM_SY_COMM_MB_OBS__M 0x2 --#define QAM_SY_COMM_MB_OBS__PRE 0x0 --#define QAM_SY_COMM_MB_OBS_OFF 0x0 --#define QAM_SY_COMM_MB_OBS_ON 0x2 --#define QAM_SY_COMM_MB_MUX_CTL__B 2 --#define QAM_SY_COMM_MB_MUX_CTL__W 1 --#define QAM_SY_COMM_MB_MUX_CTL__M 0x4 --#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0 --#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0 --#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4 --#define QAM_SY_COMM_MB_MUX_OBS__B 3 --#define QAM_SY_COMM_MB_MUX_OBS__W 1 --#define QAM_SY_COMM_MB_MUX_OBS__M 0x8 --#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0 --#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0 --#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8 -- --#define QAM_SY_COMM_INT_REQ__A 0x1470003 --#define QAM_SY_COMM_INT_REQ__W 1 --#define QAM_SY_COMM_INT_REQ__M 0x1 --#define QAM_SY_COMM_INT_REQ__PRE 0x0 --#define QAM_SY_COMM_INT_STA__A 0x1470005 --#define QAM_SY_COMM_INT_STA__W 4 --#define QAM_SY_COMM_INT_STA__M 0xF --#define QAM_SY_COMM_INT_STA__PRE 0x0 -- --#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 --#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 --#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 --#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 -- --#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 --#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 --#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 --#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 -- --#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 --#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 --#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 --#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 -- --#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 --#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 --#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 --#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 -- --#define QAM_SY_COMM_INT_MSK__A 0x1470006 --#define QAM_SY_COMM_INT_MSK__W 4 --#define QAM_SY_COMM_INT_MSK__M 0xF --#define QAM_SY_COMM_INT_MSK__PRE 0x0 --#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 --#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 --#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 --#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 --#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 --#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 --#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 --#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 --#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 --#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 --#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 --#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 --#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 --#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 --#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 --#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 -- --#define QAM_SY_COMM_INT_STM__A 0x1470007 --#define QAM_SY_COMM_INT_STM__W 4 --#define QAM_SY_COMM_INT_STM__M 0xF --#define QAM_SY_COMM_INT_STM__PRE 0x0 --#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 --#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 --#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 --#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 --#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 --#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 --#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 --#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 --#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 --#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 --#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 --#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 --#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 --#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 --#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 --#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 -- --#define QAM_SY_STATUS__A 0x1470010 --#define QAM_SY_STATUS__W 2 --#define QAM_SY_STATUS__M 0x3 --#define QAM_SY_STATUS__PRE 0x0 -- --#define QAM_SY_STATUS_SYNC_STATE__B 0 --#define QAM_SY_STATUS_SYNC_STATE__W 2 --#define QAM_SY_STATUS_SYNC_STATE__M 0x3 --#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 -- -- --#define QAM_SY_TIMEOUT__A 0x1470011 --#define QAM_SY_TIMEOUT__W 16 --#define QAM_SY_TIMEOUT__M 0xFFFF --#define QAM_SY_TIMEOUT__PRE 0x3A98 -- --#define QAM_SY_SYNC_LWM__A 0x1470012 --#define QAM_SY_SYNC_LWM__W 4 --#define QAM_SY_SYNC_LWM__M 0xF --#define QAM_SY_SYNC_LWM__PRE 0x2 -- --#define QAM_SY_SYNC_AWM__A 0x1470013 --#define QAM_SY_SYNC_AWM__W 4 --#define QAM_SY_SYNC_AWM__M 0xF --#define QAM_SY_SYNC_AWM__PRE 0x3 -- --#define QAM_SY_SYNC_HWM__A 0x1470014 --#define QAM_SY_SYNC_HWM__W 4 --#define QAM_SY_SYNC_HWM__M 0xF --#define QAM_SY_SYNC_HWM__PRE 0x5 -- --#define QAM_SY_UNLOCK__A 0x1470015 --#define QAM_SY_UNLOCK__W 1 --#define QAM_SY_UNLOCK__M 0x1 --#define QAM_SY_UNLOCK__PRE 0x0 --#define QAM_SY_CONTROL_WORD__A 0x1470016 --#define QAM_SY_CONTROL_WORD__W 4 --#define QAM_SY_CONTROL_WORD__M 0xF --#define QAM_SY_CONTROL_WORD__PRE 0x0 -- --#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 --#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 --#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF --#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 -- -- --#define QAM_SY_SP_INV__A 0x1470017 --#define QAM_SY_SP_INV__W 1 --#define QAM_SY_SP_INV__M 0x1 --#define QAM_SY_SP_INV__PRE 0x0 --#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 --#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1 -- -- -- --#define QAM_VD_ISS_RAM__A 0x1480000 -- -- -- --#define QAM_VD_QSS_RAM__A 0x1490000 -- -- -- --#define QAM_VD_SYM_RAM__A 0x14A0000 -- -- -- -- -- --#define SCU_COMM_EXEC__A 0x800000 --#define SCU_COMM_EXEC__W 2 --#define SCU_COMM_EXEC__M 0x3 --#define SCU_COMM_EXEC__PRE 0x0 --#define SCU_COMM_EXEC_STOP 0x0 --#define SCU_COMM_EXEC_ACTIVE 0x1 --#define SCU_COMM_EXEC_HOLD 0x2 -- --#define SCU_COMM_STATE__A 0x800001 --#define SCU_COMM_STATE__W 16 --#define SCU_COMM_STATE__M 0xFFFF --#define SCU_COMM_STATE__PRE 0x0 -- --#define SCU_COMM_STATE_COMM_STATE__B 0 --#define SCU_COMM_STATE_COMM_STATE__W 16 --#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF --#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 -- -- -- --#define SCU_TOP_COMM_EXEC__A 0x810000 --#define SCU_TOP_COMM_EXEC__W 2 --#define SCU_TOP_COMM_EXEC__M 0x3 --#define SCU_TOP_COMM_EXEC__PRE 0x0 --#define SCU_TOP_COMM_EXEC_STOP 0x0 --#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 --#define SCU_TOP_COMM_EXEC_HOLD 0x2 -- -- --#define SCU_TOP_COMM_STATE__A 0x810001 --#define SCU_TOP_COMM_STATE__W 16 --#define SCU_TOP_COMM_STATE__M 0xFFFF --#define SCU_TOP_COMM_STATE__PRE 0x0 --#define SCU_TOP_MWAIT_CTR__A 0x810010 --#define SCU_TOP_MWAIT_CTR__W 2 --#define SCU_TOP_MWAIT_CTR__M 0x3 --#define SCU_TOP_MWAIT_CTR__PRE 0x0 -- --#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 --#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 --#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 --#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 --#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 --#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 -- --#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 --#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 --#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 --#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 --#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 --#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 -- -- -- --#define SCU_LOW_RAM__A 0x820000 -- --#define SCU_LOW_RAM_LOW__B 0 --#define SCU_LOW_RAM_LOW__W 16 --#define SCU_LOW_RAM_LOW__M 0xFFFF --#define SCU_LOW_RAM_LOW__PRE 0x0 -- -- -- --#define SCU_HIGH_RAM__A 0x830000 -- --#define SCU_HIGH_RAM_HIGH__B 0 --#define SCU_HIGH_RAM_HIGH__W 16 --#define SCU_HIGH_RAM_HIGH__M 0xFFFF --#define SCU_HIGH_RAM_HIGH__PRE 0x0 -- -- -- -- -- -- --#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF --#define SCU_RAM_DRIVER_DEBUG__W 16 --#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF --#define SCU_RAM_DRIVER_DEBUG__PRE 0x0 -- --#define SCU_RAM_SP__A 0x831EC0 --#define SCU_RAM_SP__W 16 --#define SCU_RAM_SP__M 0xFFFF --#define SCU_RAM_SP__PRE 0x0 -- --#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1 --#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16 --#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF --#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0 -- --#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2 --#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16 --#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF --#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0 -- --#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3 --#define SCU_RAM_QAM_NO_ACQ_CNT__W 16 --#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF --#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 --#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16 --#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF --#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0 -- --#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5 --#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 --#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF --#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000 -- --#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6 --#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 --#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF --#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 --#define SCU_RAM_GPIO__A 0x831EC7 --#define SCU_RAM_GPIO__W 2 --#define SCU_RAM_GPIO__M 0x3 --#define SCU_RAM_GPIO__PRE 0x0 -- --#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 --#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 --#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 --#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 --#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 --#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 -- --#define SCU_RAM_GPIO_VSYNC_IND__B 1 --#define SCU_RAM_GPIO_VSYNC_IND__W 1 --#define SCU_RAM_GPIO_VSYNC_IND__M 0x2 --#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0 --#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0 --#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2 -- --#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 --#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 --#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF --#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 -- --#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 --#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 --#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 --#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 --#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 --#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 -- --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 -- --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 --#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 -- -- --#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 --#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 --#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF --#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000 -- --#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA --#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 --#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF --#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 -- --#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB --#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 --#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF --#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 -- --#define SCU_RAM_INHIBIT_1__A 0x831ECC --#define SCU_RAM_INHIBIT_1__W 16 --#define SCU_RAM_INHIBIT_1__M 0xFFFF --#define SCU_RAM_INHIBIT_1__PRE 0x0 -- --#define SCU_RAM_HTOL_BUF_0__A 0x831ECD --#define SCU_RAM_HTOL_BUF_0__W 16 --#define SCU_RAM_HTOL_BUF_0__M 0xFFFF --#define SCU_RAM_HTOL_BUF_0__PRE 0x0 -- --#define SCU_RAM_HTOL_BUF_1__A 0x831ECE --#define SCU_RAM_HTOL_BUF_1__W 16 --#define SCU_RAM_HTOL_BUF_1__M 0xFFFF --#define SCU_RAM_HTOL_BUF_1__PRE 0x0 -- --#define SCU_RAM_INHIBIT_2__A 0x831ECF --#define SCU_RAM_INHIBIT_2__W 16 --#define SCU_RAM_INHIBIT_2__M 0xFFFF --#define SCU_RAM_INHIBIT_2__PRE 0x0 -- --#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 --#define SCU_RAM_TR_SHORT_BUF_0__W 16 --#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF --#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 -- --#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 --#define SCU_RAM_TR_SHORT_BUF_1__W 16 --#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF --#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 --#define SCU_RAM_TR_LONG_BUF_0__W 16 --#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 --#define SCU_RAM_TR_LONG_BUF_1__W 16 --#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 --#define SCU_RAM_TR_LONG_BUF_2__W 16 --#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 --#define SCU_RAM_TR_LONG_BUF_3__W 16 --#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 --#define SCU_RAM_TR_LONG_BUF_4__W 16 --#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 --#define SCU_RAM_TR_LONG_BUF_5__W 16 --#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 --#define SCU_RAM_TR_LONG_BUF_6__W 16 --#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 --#define SCU_RAM_TR_LONG_BUF_7__W 16 --#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA --#define SCU_RAM_TR_LONG_BUF_8__W 16 --#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB --#define SCU_RAM_TR_LONG_BUF_9__W 16 --#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC --#define SCU_RAM_TR_LONG_BUF_10__W 16 --#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD --#define SCU_RAM_TR_LONG_BUF_11__W 16 --#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE --#define SCU_RAM_TR_LONG_BUF_12__W 16 --#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF --#define SCU_RAM_TR_LONG_BUF_13__W 16 --#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 --#define SCU_RAM_TR_LONG_BUF_14__W 16 --#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 --#define SCU_RAM_TR_LONG_BUF_15__W 16 --#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 --#define SCU_RAM_TR_LONG_BUF_16__W 16 --#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 --#define SCU_RAM_TR_LONG_BUF_17__W 16 --#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 --#define SCU_RAM_TR_LONG_BUF_18__W 16 --#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 --#define SCU_RAM_TR_LONG_BUF_19__W 16 --#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 --#define SCU_RAM_TR_LONG_BUF_20__W 16 --#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 --#define SCU_RAM_TR_LONG_BUF_21__W 16 --#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 --#define SCU_RAM_TR_LONG_BUF_22__W 16 --#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 --#define SCU_RAM_TR_LONG_BUF_23__W 16 --#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA --#define SCU_RAM_TR_LONG_BUF_24__W 16 --#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB --#define SCU_RAM_TR_LONG_BUF_25__W 16 --#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC --#define SCU_RAM_TR_LONG_BUF_26__W 16 --#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED --#define SCU_RAM_TR_LONG_BUF_27__W 16 --#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE --#define SCU_RAM_TR_LONG_BUF_28__W 16 --#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF --#define SCU_RAM_TR_LONG_BUF_29__W 16 --#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 --#define SCU_RAM_TR_LONG_BUF_30__W 16 --#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 -- --#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 --#define SCU_RAM_TR_LONG_BUF_31__W 16 --#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF --#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 --#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 --#define SCU_RAM_ATV_AMS_MAX__W 11 --#define SCU_RAM_ATV_AMS_MAX__M 0x7FF --#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 -- --#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 --#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 --#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF --#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 -- --#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 --#define SCU_RAM_ATV_AMS_MIN__W 11 --#define SCU_RAM_ATV_AMS_MIN__M 0x7FF --#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF -- --#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 --#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 --#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF --#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF -- --#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 --#define SCU_RAM_ATV_FIELD_CNT__W 9 --#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF --#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 --#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 --#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF --#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 --#define SCU_RAM_ATV_AAGC_FAST__W 1 --#define SCU_RAM_ATV_AAGC_FAST__M 0x1 --#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 -- --#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 --#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 --#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 --#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 --#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 --#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 -- --#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 --#define SCU_RAM_ATV_AAGC_LP2__W 16 --#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF --#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 -- --#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 --#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 --#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF --#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 -- --#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 --#define SCU_RAM_ATV_BP_LVL__W 11 --#define SCU_RAM_ATV_BP_LVL__M 0x7FF --#define SCU_RAM_ATV_BP_LVL__PRE 0x0 -- --#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 --#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 --#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF --#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 -- --#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 --#define SCU_RAM_ATV_BP_RELY__W 8 --#define SCU_RAM_ATV_BP_RELY__M 0xFF --#define SCU_RAM_ATV_BP_RELY__PRE 0x0 -- --#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 --#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 --#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF --#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 -- --#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 --#define SCU_RAM_ATV_BP_MTA__W 14 --#define SCU_RAM_ATV_BP_MTA__M 0x3FFF --#define SCU_RAM_ATV_BP_MTA__PRE 0x0 -- --#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 --#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 --#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF --#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 -- --#define SCU_RAM_ATV_BP_REF__A 0x831EFA --#define SCU_RAM_ATV_BP_REF__W 11 --#define SCU_RAM_ATV_BP_REF__M 0x7FF --#define SCU_RAM_ATV_BP_REF__PRE 0x0 -- --#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 --#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 --#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF --#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 -- --#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB --#define SCU_RAM_ATV_BP_REF_MIN__W 11 --#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF --#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64 -- --#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 --#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 --#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF --#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64 -- --#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC --#define SCU_RAM_ATV_BP_REF_MAX__W 11 --#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF --#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104 -- --#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 --#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 --#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF --#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104 -- --#define SCU_RAM_ATV_BP_CNT__A 0x831EFD --#define SCU_RAM_ATV_BP_CNT__W 8 --#define SCU_RAM_ATV_BP_CNT__M 0xFF --#define SCU_RAM_ATV_BP_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 --#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 --#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF --#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE --#define SCU_RAM_ATV_BP_XD_CNT__W 12 --#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF --#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 --#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 --#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF --#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF --#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 --#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF --#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445 -- --#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 --#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 --#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF --#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445 -- --#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 --#define SCU_RAM_ATV_BPC_KI_MIN__W 12 --#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF --#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223 -- --#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 --#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 --#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF --#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223 -- -- --#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01 --#define SCU_RAM_OFDM_AGC_POW_TGT__W 15 --#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF --#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848 -- --#define SCU_RAM_OFDM_RSV_01__A 0x831F02 --#define SCU_RAM_OFDM_RSV_01__W 16 --#define SCU_RAM_OFDM_RSV_01__M 0xFFFF --#define SCU_RAM_OFDM_RSV_01__PRE 0x0 -- --#define SCU_RAM_OFDM_RSV_02__A 0x831F03 --#define SCU_RAM_OFDM_RSV_02__W 16 --#define SCU_RAM_OFDM_RSV_02__M 0xFFFF --#define SCU_RAM_OFDM_RSV_02__PRE 0x0 --#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04 --#define SCU_RAM_FEC_PRE_RS_BER__W 16 --#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF --#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0 -- --#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0 --#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16 --#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF --#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0 -- --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16 --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0 -- --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0 --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16 --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF --#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0 -- --#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06 --#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16 --#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF --#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0 --#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16 --#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF --#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0 -- --#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07 --#define SCU_RAM_ATV_VSYNC_PERIOD__W 16 --#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF --#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0 -- --#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0 --#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16 --#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF --#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0 -- --#define SCU_RAM_FREE_7944__A 0x831F08 --#define SCU_RAM_FREE_7944__W 16 --#define SCU_RAM_FREE_7944__M 0xFFFF --#define SCU_RAM_FREE_7944__PRE 0x0 -- --#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7945__A 0x831F09 --#define SCU_RAM_FREE_7945__W 16 --#define SCU_RAM_FREE_7945__M 0xFFFF --#define SCU_RAM_FREE_7945__PRE 0x0 -- --#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7946__A 0x831F0A --#define SCU_RAM_FREE_7946__W 16 --#define SCU_RAM_FREE_7946__M 0xFFFF --#define SCU_RAM_FREE_7946__PRE 0x0 -- --#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7947__A 0x831F0B --#define SCU_RAM_FREE_7947__W 16 --#define SCU_RAM_FREE_7947__M 0xFFFF --#define SCU_RAM_FREE_7947__PRE 0x0 -- --#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7948__A 0x831F0C --#define SCU_RAM_FREE_7948__W 16 --#define SCU_RAM_FREE_7948__M 0xFFFF --#define SCU_RAM_FREE_7948__PRE 0x0 -- --#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7949__A 0x831F0D --#define SCU_RAM_FREE_7949__W 16 --#define SCU_RAM_FREE_7949__M 0xFFFF --#define SCU_RAM_FREE_7949__PRE 0x0 -- --#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7950__A 0x831F0E --#define SCU_RAM_FREE_7950__W 16 --#define SCU_RAM_FREE_7950__M 0xFFFF --#define SCU_RAM_FREE_7950__PRE 0x0 -- --#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7951__A 0x831F0F --#define SCU_RAM_FREE_7951__W 16 --#define SCU_RAM_FREE_7951__M 0xFFFF --#define SCU_RAM_FREE_7951__PRE 0x0 -- --#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7952__A 0x831F10 --#define SCU_RAM_FREE_7952__W 16 --#define SCU_RAM_FREE_7952__M 0xFFFF --#define SCU_RAM_FREE_7952__PRE 0x0 -- --#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7953__A 0x831F11 --#define SCU_RAM_FREE_7953__W 16 --#define SCU_RAM_FREE_7953__M 0xFFFF --#define SCU_RAM_FREE_7953__PRE 0x0 -- --#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7954__A 0x831F12 --#define SCU_RAM_FREE_7954__W 16 --#define SCU_RAM_FREE_7954__M 0xFFFF --#define SCU_RAM_FREE_7954__PRE 0x0 -- --#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7955__A 0x831F13 --#define SCU_RAM_FREE_7955__W 16 --#define SCU_RAM_FREE_7955__M 0xFFFF --#define SCU_RAM_FREE_7955__PRE 0x0 -- --#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0 -- -- --#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14 --#define SCU_RAM_ADC_COMP_CONTROL__W 3 --#define SCU_RAM_ADC_COMP_CONTROL__M 0x7 --#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0 --#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0 --#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1 --#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2 --#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3 -- -- --#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 --#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 --#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF --#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32 -- --#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16 --#define SCU_RAM_AGC_KI_CYCCNT__W 16 --#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF --#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 -- --#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 --#define SCU_RAM_AGC_KI_CYCLEN__W 16 --#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF --#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4 -- --#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 --#define SCU_RAM_AGC_SNS_CYCLEN__W 16 --#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF --#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4 -- --#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 --#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 --#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF --#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF -- --#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A --#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 --#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF --#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01 -- --#define SCU_RAM_AGC_RF_MAX__A 0x831F1B --#define SCU_RAM_AGC_RF_MAX__W 15 --#define SCU_RAM_AGC_RF_MAX__M 0x7FFF --#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF --#define SCU_RAM_FREE_7964__A 0x831F1C --#define SCU_RAM_FREE_7964__W 16 --#define SCU_RAM_FREE_7964__M 0xFFFF --#define SCU_RAM_FREE_7964__PRE 0x0 -- --#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7965__A 0x831F1D --#define SCU_RAM_FREE_7965__W 16 --#define SCU_RAM_FREE_7965__M 0xFFFF --#define SCU_RAM_FREE_7965__PRE 0x0 -- --#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7966__A 0x831F1E --#define SCU_RAM_FREE_7966__W 16 --#define SCU_RAM_FREE_7966__M 0xFFFF --#define SCU_RAM_FREE_7966__PRE 0x0 -- --#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7967__A 0x831F1F --#define SCU_RAM_FREE_7967__W 16 --#define SCU_RAM_FREE_7967__M 0xFFFF --#define SCU_RAM_FREE_7967__PRE 0x0 -- --#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20 --#define SCU_RAM_QAM_PARAM_MIRRORING__W 8 --#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF --#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0 --#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1 --#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1 --#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0 --#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0 --#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1 -- --#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1 --#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1 --#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2 --#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0 --#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0 --#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2 -- --#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2 --#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1 --#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4 --#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0 --#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0 --#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4 -- --#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21 --#define SCU_RAM_QAM_PARAM_OPTIONS__W 8 --#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF --#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0 --#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1 --#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1 --#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0 --#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0 --#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1 -- --#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1 --#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1 --#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2 --#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0 --#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0 --#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2 -- --#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4 --#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1 --#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10 --#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0 --#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0 --#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10 -- --#define SCU_RAM_FREE_7970__A 0x831F22 --#define SCU_RAM_FREE_7970__W 16 --#define SCU_RAM_FREE_7970__M 0xFFFF --#define SCU_RAM_FREE_7970__PRE 0x0 -- --#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_FREE_7971__A 0x831F23 --#define SCU_RAM_FREE_7971__W 16 --#define SCU_RAM_FREE_7971__M 0xFFFF --#define SCU_RAM_FREE_7971__PRE 0x0 -- --#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0 --#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16 --#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF --#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0 -- --#define SCU_RAM_AGC_CONFIG__A 0x831F24 --#define SCU_RAM_AGC_CONFIG__W 16 --#define SCU_RAM_AGC_CONFIG__M 0xFFFF --#define SCU_RAM_AGC_CONFIG__PRE 0x0 -- --#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0 --#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1 --#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 --#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0 -- --#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1 --#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1 --#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 --#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0 -- --#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2 --#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1 --#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4 --#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0 -- --#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8 --#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1 --#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 --#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0 -- --#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9 --#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1 --#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 --#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0 -- --#define SCU_RAM_AGC_KI__A 0x831F25 --#define SCU_RAM_AGC_KI__W 15 --#define SCU_RAM_AGC_KI__M 0x7FFF --#define SCU_RAM_AGC_KI__PRE 0x22A -- --#define SCU_RAM_AGC_KI_DGAIN__B 0 --#define SCU_RAM_AGC_KI_DGAIN__W 4 --#define SCU_RAM_AGC_KI_DGAIN__M 0xF --#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA -- --#define SCU_RAM_AGC_KI_RF__B 4 --#define SCU_RAM_AGC_KI_RF__W 4 --#define SCU_RAM_AGC_KI_RF__M 0xF0 --#define SCU_RAM_AGC_KI_RF__PRE 0x20 -- --#define SCU_RAM_AGC_KI_IF__B 8 --#define SCU_RAM_AGC_KI_IF__W 4 --#define SCU_RAM_AGC_KI_IF__M 0xF00 --#define SCU_RAM_AGC_KI_IF__PRE 0x200 -- --#define SCU_RAM_AGC_KI_RED__A 0x831F26 --#define SCU_RAM_AGC_KI_RED__W 6 --#define SCU_RAM_AGC_KI_RED__M 0x3F --#define SCU_RAM_AGC_KI_RED__PRE 0x0 -- --#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 --#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 --#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 --#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 -- --#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 --#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 --#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC --#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 -- --#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 --#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 --#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 --#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 -- -- --#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 --#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 --#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF --#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 -- --#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 --#define SCU_RAM_AGC_KI_MINGAIN__W 16 --#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF --#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000 -- --#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 --#define SCU_RAM_AGC_KI_MAXGAIN__W 16 --#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF --#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 -- --#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A --#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 --#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF --#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 --#define SCU_RAM_AGC_KI_MIN__A 0x831F2B --#define SCU_RAM_AGC_KI_MIN__W 12 --#define SCU_RAM_AGC_KI_MIN__M 0xFFF --#define SCU_RAM_AGC_KI_MIN__PRE 0x111 -- --#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 --#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 --#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF --#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1 -- --#define SCU_RAM_AGC_KI_MIN_RF__B 4 --#define SCU_RAM_AGC_KI_MIN_RF__W 4 --#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 --#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10 -- --#define SCU_RAM_AGC_KI_MIN_IF__B 8 --#define SCU_RAM_AGC_KI_MIN_IF__W 4 --#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 --#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100 -- --#define SCU_RAM_AGC_KI_MAX__A 0x831F2C --#define SCU_RAM_AGC_KI_MAX__W 12 --#define SCU_RAM_AGC_KI_MAX__M 0xFFF --#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF -- --#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 --#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 --#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF --#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF -- --#define SCU_RAM_AGC_KI_MAX_RF__B 4 --#define SCU_RAM_AGC_KI_MAX_RF__W 4 --#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 --#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0 -- --#define SCU_RAM_AGC_KI_MAX_IF__B 8 --#define SCU_RAM_AGC_KI_MAX_IF__W 4 --#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 --#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00 -- -- --#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D --#define SCU_RAM_AGC_CLP_SUM__W 16 --#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF --#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 -- --#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E --#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 --#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF --#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8 -- --#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F --#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 --#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF --#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400 -- --#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 --#define SCU_RAM_AGC_CLP_CYCLEN__W 16 --#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF --#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4 -- --#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 --#define SCU_RAM_AGC_CLP_CYCCNT__W 16 --#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF --#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 -- --#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 --#define SCU_RAM_AGC_CLP_DIR_TO__W 8 --#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF --#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC -- --#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 --#define SCU_RAM_AGC_CLP_DIR_WD__W 8 --#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF --#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 -- --#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 --#define SCU_RAM_AGC_CLP_DIR_STP__W 16 --#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF --#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1 -- --#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 --#define SCU_RAM_AGC_SNS_SUM__W 16 --#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF --#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 -- --#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 --#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 --#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF --#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8 -- --#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 --#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 --#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF --#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400 -- --#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 --#define SCU_RAM_AGC_SNS_CYCCNT__W 16 --#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF --#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 -- --#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 --#define SCU_RAM_AGC_SNS_DIR_TO__W 8 --#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF --#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC -- --#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A --#define SCU_RAM_AGC_SNS_DIR_WD__W 8 --#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF --#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 -- --#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B --#define SCU_RAM_AGC_SNS_DIR_STP__W 16 --#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF --#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1 -- --#define SCU_RAM_AGC_INGAIN__A 0x831F3C --#define SCU_RAM_AGC_INGAIN__W 16 --#define SCU_RAM_AGC_INGAIN__M 0xFFFF --#define SCU_RAM_AGC_INGAIN__PRE 0x708 -- --#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D --#define SCU_RAM_AGC_INGAIN_TGT__W 15 --#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF --#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708 -- --#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E --#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 --#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF --#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708 -- --#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F --#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 --#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF --#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF -- --#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 --#define SCU_RAM_AGC_IF_IACCU_HI__W 16 --#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF --#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 -- --#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 --#define SCU_RAM_AGC_IF_IACCU_LO__W 8 --#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF --#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 -- --#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 --#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 --#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF --#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008 -- --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 -- --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF --#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C -- --#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 --#define SCU_RAM_AGC_RF_IACCU_HI__W 16 --#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF --#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 -- --#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 --#define SCU_RAM_AGC_RF_IACCU_LO__W 8 --#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF --#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 -- --#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 --#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 --#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF --#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 --#define SCU_RAM_ATV_STANDARD__A 0x831F48 --#define SCU_RAM_ATV_STANDARD__W 12 --#define SCU_RAM_ATV_STANDARD__M 0xFFF --#define SCU_RAM_ATV_STANDARD__PRE 0x2 -- --#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 --#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 --#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF --#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2 --#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 --#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 --#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 --#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 --#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 --#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 --#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA --#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 -- --#define SCU_RAM_ATV_DETECT__A 0x831F49 --#define SCU_RAM_ATV_DETECT__W 1 --#define SCU_RAM_ATV_DETECT__M 0x1 --#define SCU_RAM_ATV_DETECT__PRE 0x0 -- --#define SCU_RAM_ATV_DETECT_DETECT__B 0 --#define SCU_RAM_ATV_DETECT_DETECT__W 1 --#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 --#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 --#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 --#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 -- --#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A --#define SCU_RAM_ATV_DETECT_TH__W 8 --#define SCU_RAM_ATV_DETECT_TH__M 0xFF --#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F -- --#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 --#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 --#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF --#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F -- --#define SCU_RAM_ATV_LOCK__A 0x831F4B --#define SCU_RAM_ATV_LOCK__W 2 --#define SCU_RAM_ATV_LOCK__M 0x3 --#define SCU_RAM_ATV_LOCK__PRE 0x0 -- --#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 --#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 --#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 --#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 --#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 --#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 -- --#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 --#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 --#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 --#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 --#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 --#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 -- --#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C --#define SCU_RAM_ATV_CR_LOCK__W 11 --#define SCU_RAM_ATV_CR_LOCK__M 0x7FF --#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 -- --#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 --#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 --#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF --#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 -- --#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D --#define SCU_RAM_ATV_AGC_MODE__W 8 --#define SCU_RAM_ATV_AGC_MODE__M 0xFF --#define SCU_RAM_ATV_AGC_MODE__PRE 0x50 -- --#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 --#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 --#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 --#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 --#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 --#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 -- --#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 --#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 --#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 --#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 --#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 --#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 -- --#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 --#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 --#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 --#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10 --#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 --#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 --#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 -- --#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 --#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 --#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 --#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40 --#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 --#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 -- --#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 --#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 --#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 --#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 --#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 --#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 -- -- --#define SCU_RAM_ATV_RSV_01__A 0x831F4E --#define SCU_RAM_ATV_RSV_01__W 16 --#define SCU_RAM_ATV_RSV_01__M 0xFFFF --#define SCU_RAM_ATV_RSV_01__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_02__A 0x831F4F --#define SCU_RAM_ATV_RSV_02__W 16 --#define SCU_RAM_ATV_RSV_02__M 0xFFFF --#define SCU_RAM_ATV_RSV_02__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_03__A 0x831F50 --#define SCU_RAM_ATV_RSV_03__W 16 --#define SCU_RAM_ATV_RSV_03__M 0xFFFF --#define SCU_RAM_ATV_RSV_03__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_04__A 0x831F51 --#define SCU_RAM_ATV_RSV_04__W 16 --#define SCU_RAM_ATV_RSV_04__M 0xFFFF --#define SCU_RAM_ATV_RSV_04__PRE 0x0 --#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 --#define SCU_RAM_ATV_FAGC_TH_RED__W 8 --#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF --#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA -- --#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 --#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 --#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF --#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA -- --#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 --#define SCU_RAM_ATV_AMS_MAX_REF__W 11 --#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF --#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC -- --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 --#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A -- --#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 --#define SCU_RAM_ATV_ACT_AMX__W 11 --#define SCU_RAM_ATV_ACT_AMX__M 0x7FF --#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 -- --#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 --#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 --#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF --#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 -- --#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 --#define SCU_RAM_ATV_ACT_AMI__W 11 --#define SCU_RAM_ATV_ACT_AMI__M 0x7FF --#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 -- --#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 --#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 --#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF --#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 -- --#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56 --#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16 --#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF --#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0 -- --#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0 --#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16 --#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF --#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0 -- --#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57 --#define SCU_RAM_ATV_BPC_REF_CNT__W 16 --#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF --#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0 -- --#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0 --#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16 --#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF --#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0 -- -- --#define SCU_RAM_ATV_RSV_07__A 0x831F58 --#define SCU_RAM_ATV_RSV_07__W 16 --#define SCU_RAM_ATV_RSV_07__M 0xFFFF --#define SCU_RAM_ATV_RSV_07__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_08__A 0x831F59 --#define SCU_RAM_ATV_RSV_08__W 16 --#define SCU_RAM_ATV_RSV_08__M 0xFFFF --#define SCU_RAM_ATV_RSV_08__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_09__A 0x831F5A --#define SCU_RAM_ATV_RSV_09__W 16 --#define SCU_RAM_ATV_RSV_09__M 0xFFFF --#define SCU_RAM_ATV_RSV_09__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_10__A 0x831F5B --#define SCU_RAM_ATV_RSV_10__W 16 --#define SCU_RAM_ATV_RSV_10__M 0xFFFF --#define SCU_RAM_ATV_RSV_10__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_11__A 0x831F5C --#define SCU_RAM_ATV_RSV_11__W 16 --#define SCU_RAM_ATV_RSV_11__M 0xFFFF --#define SCU_RAM_ATV_RSV_11__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_12__A 0x831F5D --#define SCU_RAM_ATV_RSV_12__W 16 --#define SCU_RAM_ATV_RSV_12__M 0xFFFF --#define SCU_RAM_ATV_RSV_12__PRE 0x0 --#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E --#define SCU_RAM_ATV_VID_GAIN_HI__W 16 --#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF --#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000 -- --#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 --#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 --#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF --#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000 -- --#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F --#define SCU_RAM_ATV_VID_GAIN_LO__W 8 --#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF --#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 -- --#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 --#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 --#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF --#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 -- -- --#define SCU_RAM_ATV_RSV_13__A 0x831F60 --#define SCU_RAM_ATV_RSV_13__W 16 --#define SCU_RAM_ATV_RSV_13__M 0xFFFF --#define SCU_RAM_ATV_RSV_13__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_14__A 0x831F61 --#define SCU_RAM_ATV_RSV_14__W 16 --#define SCU_RAM_ATV_RSV_14__M 0xFFFF --#define SCU_RAM_ATV_RSV_14__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_15__A 0x831F62 --#define SCU_RAM_ATV_RSV_15__W 16 --#define SCU_RAM_ATV_RSV_15__M 0xFFFF --#define SCU_RAM_ATV_RSV_15__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_16__A 0x831F63 --#define SCU_RAM_ATV_RSV_16__W 16 --#define SCU_RAM_ATV_RSV_16__M 0xFFFF --#define SCU_RAM_ATV_RSV_16__PRE 0x0 --#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 --#define SCU_RAM_ATV_AAGC_CNT__W 8 --#define SCU_RAM_ATV_AAGC_CNT__M 0xFF --#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7 -- --#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 --#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 --#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF --#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7 -- --#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 --#define SCU_RAM_ATV_SIF_GAIN__W 11 --#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF --#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80 -- --#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 --#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 --#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF --#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80 -- -- --#define SCU_RAM_ATV_RSV_17__A 0x831F66 --#define SCU_RAM_ATV_RSV_17__W 16 --#define SCU_RAM_ATV_RSV_17__M 0xFFFF --#define SCU_RAM_ATV_RSV_17__PRE 0x0 -- --#define SCU_RAM_ATV_RSV_18__A 0x831F67 --#define SCU_RAM_ATV_RSV_18__W 16 --#define SCU_RAM_ATV_RSV_18__M 0xFFFF --#define SCU_RAM_ATV_RSV_18__PRE 0x0 -- --#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 --#define SCU_RAM_ATV_RATE_OFS__W 12 --#define SCU_RAM_ATV_RATE_OFS__M 0xFFF --#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 -- --#define SCU_RAM_ATV_LO_INCR__A 0x831F69 --#define SCU_RAM_ATV_LO_INCR__W 12 --#define SCU_RAM_ATV_LO_INCR__M 0xFFF --#define SCU_RAM_ATV_LO_INCR__PRE 0x0 -- --#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A --#define SCU_RAM_ATV_IIR_CRIT__W 12 --#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF --#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 -- --#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B --#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 --#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF --#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 -- --#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C --#define SCU_RAM_ATV_DEF_LO_INCR__W 12 --#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF --#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 -- --#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D --#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 --#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 --#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 --#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E --#define SCU_RAM_ATV_MOD_CONTROL__W 12 --#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF --#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 -- --#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0 --#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12 --#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF --#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0 -- --#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F --#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 --#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF --#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667 -- --#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0 --#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12 --#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF --#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667 -- --#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 --#define SCU_RAM_ATV_BPC_KI_MAX__W 12 --#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF --#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337 -- --#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0 --#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12 --#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF --#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337 -- --#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 --#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 --#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF --#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447 -- --#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0 --#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12 --#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF --#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447 -- --#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 --#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 --#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF --#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225 -- --#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 --#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 --#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF --#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225 -- --#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 --#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 --#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF --#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14 -- --#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 --#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 --#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF --#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14 --#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 --#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 -- --#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 --#define SCU_RAM_QAM_PARAM_ANNEX__W 2 --#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 --#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1 -- --#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 --#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 --#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 --#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1 --#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 --#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 --#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 --#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 -- --#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 --#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 --#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 --#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5 -- --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 --#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 -- --#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 --#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 --#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF --#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1 -- --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE --#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF -- --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF --#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 --#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 --#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF --#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13 -- --#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 --#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 --#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF --#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13 -- --#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A --#define SCU_RAM_QAM_WR_RSV_0__W 16 --#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 -- --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF --#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D --#define SCU_RAM_QAM_WR_RSV_5__W 16 --#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E --#define SCU_RAM_QAM_WR_RSV_6__W 16 --#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F --#define SCU_RAM_QAM_WR_RSV_7__W 16 --#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 --#define SCU_RAM_QAM_WR_RSV_8__W 16 --#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 --#define SCU_RAM_QAM_WR_RSV_9__W 16 --#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 --#define SCU_RAM_QAM_WR_RSV_10__W 16 --#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 --#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 --#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF --#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258 -- --#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 --#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 --#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258 --#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 -- --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B --#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 --#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF --#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 --#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 -- --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 --#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D --#define SCU_RAM_QAM_FSM_ATH__W 16 --#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF --#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 --#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 --#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E --#define SCU_RAM_QAM_FSM_RTH__W 16 --#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF --#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B -- --#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 --#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 --#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B --#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C --#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 --#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E --#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 --#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D -- --#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F --#define SCU_RAM_QAM_FSM_FTH__W 16 --#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF --#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C -- --#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 --#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 --#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C --#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 --#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E --#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E --#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 --#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 -- --#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 --#define SCU_RAM_QAM_FSM_PTH__W 16 --#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF --#define SCU_RAM_QAM_FSM_PTH__PRE 0x64 -- --#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 --#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 --#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64 --#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 --#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 --#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C --#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 --#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 -- --#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 --#define SCU_RAM_QAM_FSM_MTH__W 16 --#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF --#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E -- --#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 --#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 --#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E --#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A --#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 --#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 --#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C --#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 -- --#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 --#define SCU_RAM_QAM_FSM_CTH__W 16 --#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF --#define SCU_RAM_QAM_FSM_CTH__PRE 0x50 -- --#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 --#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 --#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50 --#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 --#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C --#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C --#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C --#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C -- --#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 --#define SCU_RAM_QAM_FSM_QTH__W 16 --#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF --#define SCU_RAM_QAM_FSM_QTH__PRE 0x96 -- --#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 --#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 --#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96 --#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 --#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA --#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 --#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C --#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 -- --#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 --#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 --#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF --#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28 -- --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28 --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 --#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 -- --#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 --#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 --#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF --#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF -- --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 --#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 -- --#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 --#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 --#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF --#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4 -- --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4 --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 --#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 -- --#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 --#define SCU_RAM_QAM_LC_CA_COARSE__W 16 --#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF --#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28 -- --#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 --#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 --#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28 -- --#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 --#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 --#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF --#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28 -- --#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 --#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 --#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28 -- --#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 --#define SCU_RAM_QAM_LC_CA_FINE__W 16 --#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF --#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF -- --#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 --#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 --#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF -- --#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A --#define SCU_RAM_QAM_LC_CP_COARSE__W 16 --#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF --#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64 -- --#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 --#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 --#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64 -- --#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B --#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 --#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF --#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E -- --#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 --#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 --#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E -- --#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C --#define SCU_RAM_QAM_LC_CP_FINE__W 16 --#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF --#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5 -- --#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 --#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 --#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5 -- --#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D --#define SCU_RAM_QAM_LC_CI_COARSE__W 16 --#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF --#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32 -- --#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 --#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 --#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32 -- --#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E --#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 --#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF --#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E -- --#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 --#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 --#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E -- --#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F --#define SCU_RAM_QAM_LC_CI_FINE__W 16 --#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF --#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5 -- --#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 --#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 --#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5 -- --#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 --#define SCU_RAM_QAM_LC_EP_COARSE__W 16 --#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF --#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18 -- --#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 --#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 --#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18 -- --#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 --#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 --#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF --#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18 -- --#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 --#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 --#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF --#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18 -- --#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 --#define SCU_RAM_QAM_LC_EP_FINE__W 16 --#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF --#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC -- --#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 --#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 --#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC -- --#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 --#define SCU_RAM_QAM_LC_EI_COARSE__W 16 --#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF --#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10 -- --#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 --#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 --#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10 -- --#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 --#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 --#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF --#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10 -- --#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 --#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 --#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF --#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10 -- --#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 --#define SCU_RAM_QAM_LC_EI_FINE__W 16 --#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF --#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC -- --#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 --#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 --#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC -- --#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 --#define SCU_RAM_QAM_LC_CF_COARSE__W 16 --#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF --#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 -- --#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 --#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 --#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 -- --#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 --#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 --#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF --#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 -- --#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 --#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 --#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 -- --#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 --#define SCU_RAM_QAM_LC_CF_FINE__W 16 --#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF --#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 -- --#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 --#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 --#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 -- --#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 --#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 --#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF --#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA -- --#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 --#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 --#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA -- --#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA --#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 --#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF --#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA -- --#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 --#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 --#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA -- --#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB --#define SCU_RAM_QAM_LC_CF1_FINE__W 16 --#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF --#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 -- --#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 --#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 --#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF --#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 -- --#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC --#define SCU_RAM_QAM_SL_SIG_POWER__W 16 --#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF --#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00 -- --#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 --#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 --#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF --#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00 -- --#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD --#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 -- --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 --#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE -- --#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE --#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A -- --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 --#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 -- --#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF --#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 -- --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA --#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF -- --#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 --#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 -- --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 --#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 -- --#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 --#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 -- --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 --#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D -- --#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 --#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 -- --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 --#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 -- --#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 --#define SCU_RAM_QAM_CTL_ENA__W 16 --#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF --#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF -- --#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 --#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 --#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 --#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1 -- --#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 --#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 --#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 --#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2 -- --#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 --#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 --#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 --#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4 -- --#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 --#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 --#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 --#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8 -- --#define SCU_RAM_QAM_CTL_ENA_LC__B 4 --#define SCU_RAM_QAM_CTL_ENA_LC__W 1 --#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 --#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10 -- --#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 --#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 --#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 --#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20 -- --#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 --#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 --#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 --#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40 -- --#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 --#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 --#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 --#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80 -- --#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 --#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 --#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 --#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100 -- --#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 --#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 --#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 --#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200 -- --#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 --#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 --#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 --#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400 -- --#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 --#define SCU_RAM_QAM_WR_RSV_1__W 16 --#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 --#define SCU_RAM_QAM_WR_RSV_2__W 16 --#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 --#define SCU_RAM_QAM_WR_RSV_3__W 16 --#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 -- --#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 --#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 --#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF --#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 -- --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 --#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 -- --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1 -- --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 --#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE -- --#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 --#define SCU_RAM_QAM_RD_RSV_4__W 16 --#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_LOCKED__A 0x831FBA --#define SCU_RAM_QAM_LOCKED__W 16 --#define SCU_RAM_QAM_LOCKED__M 0xFFFF --#define SCU_RAM_QAM_LOCKED__PRE 0x0 -- --#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 --#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 --#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF --#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 --#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 -- --#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 --#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 --#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 --#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 --#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 --#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 --#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 --#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB --#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 --#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF --#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 --#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 --#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 --#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 --#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 --#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 --#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 --#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 --#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 --#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 --#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC --#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 --#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF --#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 --#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 --#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 --#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 --#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 --#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 --#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 --#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 --#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 --#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 --#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 --#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 --#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 --#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 --#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 --#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 --#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD --#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 --#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF --#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 --#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 --#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF --#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE --#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 --#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF --#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 -- --#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 --#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 --#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF --#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF --#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 --#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF --#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 -- --#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 --#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 --#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF --#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 --#define SCU_RAM_QAM_TASKLETS_RUN__W 16 --#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF --#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 -- --#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 --#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 --#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF --#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 -- --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 -- --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF --#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 --#define SCU_RAM_QAM_RD_RSV_5__W 16 --#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 --#define SCU_RAM_QAM_RD_RSV_6__W 16 --#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 --#define SCU_RAM_QAM_RD_RSV_7__W 16 --#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 --#define SCU_RAM_QAM_RD_RSV_8__W 16 --#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 --#define SCU_RAM_QAM_RD_RSV_9__W 16 --#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 --#define SCU_RAM_QAM_RD_RSV_10__W 16 --#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 --#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 --#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF --#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 -- --#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 --#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 --#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF --#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA --#define SCU_RAM_QAM_FSM_STATE__W 4 --#define SCU_RAM_QAM_FSM_STATE__M 0xF --#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 --#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 --#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF --#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 --#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 --#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 --#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 --#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 --#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 --#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 --#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 --#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 -- --#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB --#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 --#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF --#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 --#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC --#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF --#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000 --#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0 -- --#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD --#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 --#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF --#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46 -- --#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 --#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 --#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46 -- --#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE --#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 --#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF --#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E -- --#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 --#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 --#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF --#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E -- --#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF --#define SCU_RAM_QAM_ERR_STATE__W 4 --#define SCU_RAM_QAM_ERR_STATE__M 0xF --#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 -- --#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 --#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 --#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF --#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 --#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 --#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 --#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 --#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 --#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 --#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 --#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 --#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 -- --#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 --#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 --#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF --#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 -- --#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 --#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 --#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 --#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 -- --#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 --#define SCU_RAM_QAM_EQ_LOCK__W 1 --#define SCU_RAM_QAM_EQ_LOCK__M 0x1 --#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 -- --#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 --#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 --#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 --#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 --#define SCU_RAM_QAM_EQ_STATE__W 16 --#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF --#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 -- --#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 --#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 --#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF --#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 --#define SCU_RAM_QAM_RD_RSV_0__W 16 --#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 --#define SCU_RAM_QAM_RD_RSV_1__W 16 --#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 --#define SCU_RAM_QAM_RD_RSV_2__W 16 --#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 --#define SCU_RAM_QAM_RD_RSV_3__W 16 --#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 -- --#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 --#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 --#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF --#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 -- -- --#define SCU_RAM_FREE_8151__A 0x831FD7 --#define SCU_RAM_FREE_8151__W 16 --#define SCU_RAM_FREE_8151__M 0xFFFF --#define SCU_RAM_FREE_8151__PRE 0x0 -- --#define SCU_RAM_FREE_8152__A 0x831FD8 --#define SCU_RAM_FREE_8152__W 16 --#define SCU_RAM_FREE_8152__M 0xFFFF --#define SCU_RAM_FREE_8152__PRE 0x0 -- --#define SCU_RAM_FREE_8153__A 0x831FD9 --#define SCU_RAM_FREE_8153__W 16 --#define SCU_RAM_FREE_8153__M 0xFFFF --#define SCU_RAM_FREE_8153__PRE 0x0 -- --#define SCU_RAM_FREE_8154__A 0x831FDA --#define SCU_RAM_FREE_8154__W 16 --#define SCU_RAM_FREE_8154__M 0xFFFF --#define SCU_RAM_FREE_8154__PRE 0x0 -- --#define SCU_RAM_FREE_8155__A 0x831FDB --#define SCU_RAM_FREE_8155__W 16 --#define SCU_RAM_FREE_8155__M 0xFFFF --#define SCU_RAM_FREE_8155__PRE 0x0 -- --#define SCU_RAM_FREE_8156__A 0x831FDC --#define SCU_RAM_FREE_8156__W 16 --#define SCU_RAM_FREE_8156__M 0xFFFF --#define SCU_RAM_FREE_8156__PRE 0x0 -- --#define SCU_RAM_FREE_8157__A 0x831FDD --#define SCU_RAM_FREE_8157__W 16 --#define SCU_RAM_FREE_8157__M 0xFFFF --#define SCU_RAM_FREE_8157__PRE 0x0 -- --#define SCU_RAM_FREE_8158__A 0x831FDE --#define SCU_RAM_FREE_8158__W 16 --#define SCU_RAM_FREE_8158__M 0xFFFF --#define SCU_RAM_FREE_8158__PRE 0x0 -- --#define SCU_RAM_FREE_8159__A 0x831FDF --#define SCU_RAM_FREE_8159__W 16 --#define SCU_RAM_FREE_8159__M 0xFFFF --#define SCU_RAM_FREE_8159__PRE 0x0 -- --#define SCU_RAM_FREE_8160__A 0x831FE0 --#define SCU_RAM_FREE_8160__W 16 --#define SCU_RAM_FREE_8160__M 0xFFFF --#define SCU_RAM_FREE_8160__PRE 0x0 -- --#define SCU_RAM_FREE_8161__A 0x831FE1 --#define SCU_RAM_FREE_8161__W 16 --#define SCU_RAM_FREE_8161__M 0xFFFF --#define SCU_RAM_FREE_8161__PRE 0x0 -- --#define SCU_RAM_FREE_8162__A 0x831FE2 --#define SCU_RAM_FREE_8162__W 16 --#define SCU_RAM_FREE_8162__M 0xFFFF --#define SCU_RAM_FREE_8162__PRE 0x0 -- --#define SCU_RAM_FREE_8163__A 0x831FE3 --#define SCU_RAM_FREE_8163__W 16 --#define SCU_RAM_FREE_8163__M 0xFFFF --#define SCU_RAM_FREE_8163__PRE 0x0 -- --#define SCU_RAM_FREE_8164__A 0x831FE4 --#define SCU_RAM_FREE_8164__W 16 --#define SCU_RAM_FREE_8164__M 0xFFFF --#define SCU_RAM_FREE_8164__PRE 0x0 -- --#define SCU_RAM_FREE_8165__A 0x831FE5 --#define SCU_RAM_FREE_8165__W 16 --#define SCU_RAM_FREE_8165__M 0xFFFF --#define SCU_RAM_FREE_8165__PRE 0x0 -- --#define SCU_RAM_FREE_8166__A 0x831FE6 --#define SCU_RAM_FREE_8166__W 16 --#define SCU_RAM_FREE_8166__M 0xFFFF --#define SCU_RAM_FREE_8166__PRE 0x0 -- --#define SCU_RAM_FREE_8167__A 0x831FE7 --#define SCU_RAM_FREE_8167__W 16 --#define SCU_RAM_FREE_8167__M 0xFFFF --#define SCU_RAM_FREE_8167__PRE 0x0 -- --#define SCU_RAM_FREE_8168__A 0x831FE8 --#define SCU_RAM_FREE_8168__W 16 --#define SCU_RAM_FREE_8168__M 0xFFFF --#define SCU_RAM_FREE_8168__PRE 0x0 -- --#define SCU_RAM_FREE_8169__A 0x831FE9 --#define SCU_RAM_FREE_8169__W 16 --#define SCU_RAM_FREE_8169__M 0xFFFF --#define SCU_RAM_FREE_8169__PRE 0x0 -- --#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA --#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 --#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF --#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E -- --#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB --#define SCU_RAM_DRIVER_VER_HI__W 16 --#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF --#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 -- --#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC --#define SCU_RAM_DRIVER_VER_LO__W 16 --#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF --#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 -- --#define SCU_RAM_PARAM_15__A 0x831FED --#define SCU_RAM_PARAM_15__W 16 --#define SCU_RAM_PARAM_15__M 0xFFFF --#define SCU_RAM_PARAM_15__PRE 0x0 -- --#define SCU_RAM_PARAM_14__A 0x831FEE --#define SCU_RAM_PARAM_14__W 16 --#define SCU_RAM_PARAM_14__M 0xFFFF --#define SCU_RAM_PARAM_14__PRE 0x0 -- --#define SCU_RAM_PARAM_13__A 0x831FEF --#define SCU_RAM_PARAM_13__W 16 --#define SCU_RAM_PARAM_13__M 0xFFFF --#define SCU_RAM_PARAM_13__PRE 0x0 -- --#define SCU_RAM_PARAM_12__A 0x831FF0 --#define SCU_RAM_PARAM_12__W 16 --#define SCU_RAM_PARAM_12__M 0xFFFF --#define SCU_RAM_PARAM_12__PRE 0x0 -- --#define SCU_RAM_PARAM_11__A 0x831FF1 --#define SCU_RAM_PARAM_11__W 16 --#define SCU_RAM_PARAM_11__M 0xFFFF --#define SCU_RAM_PARAM_11__PRE 0x0 -- --#define SCU_RAM_PARAM_10__A 0x831FF2 --#define SCU_RAM_PARAM_10__W 16 --#define SCU_RAM_PARAM_10__M 0xFFFF --#define SCU_RAM_PARAM_10__PRE 0x0 -- --#define SCU_RAM_PARAM_9__A 0x831FF3 --#define SCU_RAM_PARAM_9__W 16 --#define SCU_RAM_PARAM_9__M 0xFFFF --#define SCU_RAM_PARAM_9__PRE 0x0 -- --#define SCU_RAM_PARAM_8__A 0x831FF4 --#define SCU_RAM_PARAM_8__W 16 --#define SCU_RAM_PARAM_8__M 0xFFFF --#define SCU_RAM_PARAM_8__PRE 0x0 -- --#define SCU_RAM_PARAM_7__A 0x831FF5 --#define SCU_RAM_PARAM_7__W 16 --#define SCU_RAM_PARAM_7__M 0xFFFF --#define SCU_RAM_PARAM_7__PRE 0x0 -- --#define SCU_RAM_PARAM_6__A 0x831FF6 --#define SCU_RAM_PARAM_6__W 16 --#define SCU_RAM_PARAM_6__M 0xFFFF --#define SCU_RAM_PARAM_6__PRE 0x0 -- --#define SCU_RAM_PARAM_5__A 0x831FF7 --#define SCU_RAM_PARAM_5__W 16 --#define SCU_RAM_PARAM_5__M 0xFFFF --#define SCU_RAM_PARAM_5__PRE 0x0 -- --#define SCU_RAM_PARAM_4__A 0x831FF8 --#define SCU_RAM_PARAM_4__W 16 --#define SCU_RAM_PARAM_4__M 0xFFFF --#define SCU_RAM_PARAM_4__PRE 0x0 -- --#define SCU_RAM_PARAM_3__A 0x831FF9 --#define SCU_RAM_PARAM_3__W 16 --#define SCU_RAM_PARAM_3__M 0xFFFF --#define SCU_RAM_PARAM_3__PRE 0x0 -- --#define SCU_RAM_PARAM_2__A 0x831FFA --#define SCU_RAM_PARAM_2__W 16 --#define SCU_RAM_PARAM_2__M 0xFFFF --#define SCU_RAM_PARAM_2__PRE 0x0 -- --#define SCU_RAM_PARAM_1__A 0x831FFB --#define SCU_RAM_PARAM_1__W 16 --#define SCU_RAM_PARAM_1__M 0xFFFF --#define SCU_RAM_PARAM_1__PRE 0x0 --#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 --#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 --#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 --#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 -- -- --#define SCU_RAM_PARAM_0__A 0x831FFC --#define SCU_RAM_PARAM_0__W 16 --#define SCU_RAM_PARAM_0__M 0xFFFF --#define SCU_RAM_PARAM_0__PRE 0x0 --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA --#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 --#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 --#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 --#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 --#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 --#define SCU_RAM_PARAM_0_RESULT_OK 0x0 --#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF --#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE --#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD --#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC -- -- --#define SCU_RAM_COMMAND__A 0x831FFD --#define SCU_RAM_COMMAND__W 16 --#define SCU_RAM_COMMAND__M 0xFFFF --#define SCU_RAM_COMMAND__PRE 0x0 --#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 --#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 --#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 --#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 --#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 --#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 --#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 --#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 --#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 --#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 --#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 --#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 --#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 --#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 --#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 --#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 --#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 --#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 --#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 --#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 --#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85 --#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86 --#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87 --#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF --#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE --#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD --#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 --#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1 -- --#define SCU_RAM_COMMAND_STANDARD__B 8 --#define SCU_RAM_COMMAND_STANDARD__W 8 --#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 --#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 --#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 --#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 --#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 --#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 --#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 --#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 -- --#define SCU_RAM_VERSION_HI__A 0x831FFE --#define SCU_RAM_VERSION_HI__W 16 --#define SCU_RAM_VERSION_HI__M 0xFFFF --#define SCU_RAM_VERSION_HI__PRE 0x0 -- --#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 -- --#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 -- --#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 --#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 -- --#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 --#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 --#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF --#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 -- --#define SCU_RAM_VERSION_LO__A 0x831FFF --#define SCU_RAM_VERSION_LO__W 16 --#define SCU_RAM_VERSION_LO__M 0xFFFF --#define SCU_RAM_VERSION_LO__PRE 0x0 -- --#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 --#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 --#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 --#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 -- --#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 --#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 --#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 --#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 -- --#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 --#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 --#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 --#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 -- --#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 --#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 --#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF --#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 -- -- -- -- -- --#define SIO_COMM_EXEC__A 0x400000 --#define SIO_COMM_EXEC__W 2 --#define SIO_COMM_EXEC__M 0x3 --#define SIO_COMM_EXEC__PRE 0x0 --#define SIO_COMM_EXEC_STOP 0x0 --#define SIO_COMM_EXEC_ACTIVE 0x1 --#define SIO_COMM_EXEC_HOLD 0x2 -- --#define SIO_COMM_STATE__A 0x400001 --#define SIO_COMM_STATE__W 16 --#define SIO_COMM_STATE__M 0xFFFF --#define SIO_COMM_STATE__PRE 0x0 --#define SIO_COMM_MB__A 0x400002 --#define SIO_COMM_MB__W 16 --#define SIO_COMM_MB__M 0xFFFF --#define SIO_COMM_MB__PRE 0x0 --#define SIO_COMM_INT_REQ__A 0x400003 --#define SIO_COMM_INT_REQ__W 16 --#define SIO_COMM_INT_REQ__M 0xFFFF --#define SIO_COMM_INT_REQ__PRE 0x0 -- --#define SIO_COMM_INT_REQ_HI_REQ__B 0 --#define SIO_COMM_INT_REQ_HI_REQ__W 1 --#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 --#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 -- --#define SIO_COMM_INT_REQ_SA_REQ__B 1 --#define SIO_COMM_INT_REQ_SA_REQ__W 1 --#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 --#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 -- --#define SIO_COMM_INT_REQ_BL_REQ__B 2 --#define SIO_COMM_INT_REQ_BL_REQ__W 1 --#define SIO_COMM_INT_REQ_BL_REQ__M 0x4 --#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0 -- --#define SIO_COMM_INT_STA__A 0x400005 --#define SIO_COMM_INT_STA__W 16 --#define SIO_COMM_INT_STA__M 0xFFFF --#define SIO_COMM_INT_STA__PRE 0x0 --#define SIO_COMM_INT_MSK__A 0x400006 --#define SIO_COMM_INT_MSK__W 16 --#define SIO_COMM_INT_MSK__M 0xFFFF --#define SIO_COMM_INT_MSK__PRE 0x0 --#define SIO_COMM_INT_STM__A 0x400007 --#define SIO_COMM_INT_STM__W 16 --#define SIO_COMM_INT_STM__M 0xFFFF --#define SIO_COMM_INT_STM__PRE 0x0 -- -- -- --#define SIO_TOP_COMM_EXEC__A 0x410000 --#define SIO_TOP_COMM_EXEC__W 2 --#define SIO_TOP_COMM_EXEC__M 0x3 --#define SIO_TOP_COMM_EXEC__PRE 0x0 --#define SIO_TOP_COMM_EXEC_STOP 0x0 --#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 --#define SIO_TOP_COMM_EXEC_HOLD 0x2 -- -- --#define SIO_TOP_COMM_KEY__A 0x41000F --#define SIO_TOP_COMM_KEY__W 16 --#define SIO_TOP_COMM_KEY__M 0xFFFF --#define SIO_TOP_COMM_KEY__PRE 0x0 --#define SIO_TOP_COMM_KEY_KEY 0xFABA -- -- --#define SIO_TOP_JTAGID_LO__A 0x410012 --#define SIO_TOP_JTAGID_LO__W 16 --#define SIO_TOP_JTAGID_LO__M 0xFFFF --#define SIO_TOP_JTAGID_LO__PRE 0x0 -- --#define SIO_TOP_JTAGID_HI__A 0x410013 --#define SIO_TOP_JTAGID_HI__W 16 --#define SIO_TOP_JTAGID_HI__M 0xFFFF --#define SIO_TOP_JTAGID_HI__PRE 0x0 -- -- -- -- --#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 --#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 --#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 --#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 --#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 --#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F --#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 -- --#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 --#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 --#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 --#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 --#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 --#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 --#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF --#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 --#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 --#define SIO_HI_RA_RAM_S0_STATE__W 1 --#define SIO_HI_RA_RAM_S0_STATE__M 0x1 --#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 --#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 --#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 --#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 --#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 --#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF --#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 -- --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 -- --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 --#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 -- --#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 --#define SIO_HI_RA_RAM_S0_ADDR__W 16 --#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF --#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 --#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 --#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF --#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 --#define SIO_HI_RA_RAM_S0_CRC__W 16 --#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF --#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 --#define SIO_HI_RA_RAM_S0_BUFFER__W 16 --#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF --#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 --#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 --#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF --#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A --#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 --#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 --#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B --#define SIO_HI_RA_RAM_S0_TEMP0__W 16 --#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF --#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C --#define SIO_HI_RA_RAM_S0_TEMP1__W 16 --#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF --#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 -- --#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D --#define SIO_HI_RA_RAM_S0_OFFSET__W 16 --#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF --#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 --#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 --#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 --#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 --#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 --#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F --#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 -- --#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 --#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 --#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 --#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 --#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 --#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 --#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF --#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 --#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 --#define SIO_HI_RA_RAM_S1_STATE__W 1 --#define SIO_HI_RA_RAM_S1_STATE__M 0x1 --#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 --#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 --#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 --#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 --#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 --#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF --#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 -- --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 -- --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 --#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 -- --#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 --#define SIO_HI_RA_RAM_S1_ADDR__W 16 --#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF --#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 --#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 --#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF --#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 --#define SIO_HI_RA_RAM_S1_CRC__W 16 --#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF --#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 --#define SIO_HI_RA_RAM_S1_BUFFER__W 16 --#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF --#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 --#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 --#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF --#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A --#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 --#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 --#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B --#define SIO_HI_RA_RAM_S1_TEMP0__W 16 --#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF --#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C --#define SIO_HI_RA_RAM_S1_TEMP1__W 16 --#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF --#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 -- --#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D --#define SIO_HI_RA_RAM_S1_OFFSET__W 16 --#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF --#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 --#define SIO_HI_RA_RAM_SEMA__A 0x420030 --#define SIO_HI_RA_RAM_SEMA__W 1 --#define SIO_HI_RA_RAM_SEMA__M 0x1 --#define SIO_HI_RA_RAM_SEMA__PRE 0x0 --#define SIO_HI_RA_RAM_SEMA_FREE 0x0 --#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 -- --#define SIO_HI_RA_RAM_RES__A 0x420031 --#define SIO_HI_RA_RAM_RES__W 3 --#define SIO_HI_RA_RAM_RES__M 0x7 --#define SIO_HI_RA_RAM_RES__PRE 0x0 --#define SIO_HI_RA_RAM_RES_OK 0x0 --#define SIO_HI_RA_RAM_RES_ERROR 0x1 --#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 --#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 --#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 --#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 -- --#define SIO_HI_RA_RAM_CMD__A 0x420032 --#define SIO_HI_RA_RAM_CMD__W 4 --#define SIO_HI_RA_RAM_CMD__M 0xF --#define SIO_HI_RA_RAM_CMD__PRE 0x0 --#define SIO_HI_RA_RAM_CMD_NULL 0x0 --#define SIO_HI_RA_RAM_CMD_UIO 0x1 --#define SIO_HI_RA_RAM_CMD_RESET 0x2 --#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 --#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 --#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 --#define SIO_HI_RA_RAM_CMD_EXEC 0x6 --#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 --#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 -- --#define SIO_HI_RA_RAM_PAR_1__A 0x420033 --#define SIO_HI_RA_RAM_PAR_1__W 16 --#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 --#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 --#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -- --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 --#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 --#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 -- --#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 --#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 --#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF --#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 --#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_2__A 0x420034 --#define SIO_HI_RA_RAM_PAR_2__W 16 --#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 --#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 --#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 --#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 --#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F --#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 -- --#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 --#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 --#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 --#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 --#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 --#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 --#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 --#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 --#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -- --#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 --#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 --#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_3__A 0x420035 --#define SIO_HI_RA_RAM_PAR_3__W 16 --#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 --#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 --#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F -- --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 --#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 -- --#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 --#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 --#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 --#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 --#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 --#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 --#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 --#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 --#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 --#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -- --#define SIO_HI_RA_RAM_PAR_4__A 0x420036 --#define SIO_HI_RA_RAM_PAR_4__W 16 --#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 --#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 --#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 --#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 --#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF --#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 -- --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 --#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 --#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_5__A 0x420037 --#define SIO_HI_RA_RAM_PAR_5__W 16 --#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 --#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 --#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -- --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 -- --#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -- --#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 --#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 --#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 --#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 --#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 -- --#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 --#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 --#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 --#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 --#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_6__A 0x420038 --#define SIO_HI_RA_RAM_PAR_6__W 16 --#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF --#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 --#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 --#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF --#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 -- --#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 --#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 --#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF --#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF -- --#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 --#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 --#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 --#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 -- -- --#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E --#define SIO_HI_RA_RAM_AB_TEMP__W 16 --#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF --#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 -- --#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F --#define SIO_HI_RA_RAM_I2C_CTL__W 16 --#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF --#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 --#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 --#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 --#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 --#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 --#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 --#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 --#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 --#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 --#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 --#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 --#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 --#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 --#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 --#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 --#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A --#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 --#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B --#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C --#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 --#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D --#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 -- -- --#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E --#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 --#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF --#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 --#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F --#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 -- --#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 --#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 --#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF --#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 -- -- -- --#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 --#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 --#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF --#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 --#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 --#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 --#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF --#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 --#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 --#define SIO_HI_IF_RAM_TRP_STK_0__W 12 --#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF --#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 --#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 --#define SIO_HI_IF_RAM_TRP_STK_1__W 12 --#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF --#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 --#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 --#define SIO_HI_IF_RAM_FUN_BASE__W 12 --#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF --#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 -- -- -- --#define SIO_HI_IF_COMM_EXEC__A 0x440000 --#define SIO_HI_IF_COMM_EXEC__W 2 --#define SIO_HI_IF_COMM_EXEC__M 0x3 --#define SIO_HI_IF_COMM_EXEC__PRE 0x0 --#define SIO_HI_IF_COMM_EXEC_STOP 0x0 --#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 --#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 --#define SIO_HI_IF_COMM_EXEC_STEP 0x3 -- -- --#define SIO_HI_IF_COMM_STATE__A 0x440001 --#define SIO_HI_IF_COMM_STATE__W 10 --#define SIO_HI_IF_COMM_STATE__M 0x3FF --#define SIO_HI_IF_COMM_STATE__PRE 0x0 --#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 --#define SIO_HI_IF_COMM_INT_REQ__W 1 --#define SIO_HI_IF_COMM_INT_REQ__M 0x1 --#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 --#define SIO_HI_IF_COMM_INT_STA__A 0x440005 --#define SIO_HI_IF_COMM_INT_STA__W 1 --#define SIO_HI_IF_COMM_INT_STA__M 0x1 --#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 --#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 --#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 --#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 --#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 -- --#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 --#define SIO_HI_IF_COMM_INT_MSK__W 1 --#define SIO_HI_IF_COMM_INT_MSK__M 0x1 --#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 --#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 --#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 --#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 --#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 -- --#define SIO_HI_IF_COMM_INT_STM__A 0x440007 --#define SIO_HI_IF_COMM_INT_STM__W 1 --#define SIO_HI_IF_COMM_INT_STM__M 0x1 --#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 --#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 --#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 --#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 --#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 -- --#define SIO_HI_IF_STK_0__A 0x440010 --#define SIO_HI_IF_STK_0__W 10 --#define SIO_HI_IF_STK_0__M 0x3FF --#define SIO_HI_IF_STK_0__PRE 0x2 -- --#define SIO_HI_IF_STK_0_ADDR__B 0 --#define SIO_HI_IF_STK_0_ADDR__W 10 --#define SIO_HI_IF_STK_0_ADDR__M 0x3FF --#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 -- --#define SIO_HI_IF_STK_1__A 0x440011 --#define SIO_HI_IF_STK_1__W 10 --#define SIO_HI_IF_STK_1__M 0x3FF --#define SIO_HI_IF_STK_1__PRE 0x2 --#define SIO_HI_IF_STK_1_ADDR__B 0 --#define SIO_HI_IF_STK_1_ADDR__W 10 --#define SIO_HI_IF_STK_1_ADDR__M 0x3FF --#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 -- --#define SIO_HI_IF_STK_2__A 0x440012 --#define SIO_HI_IF_STK_2__W 10 --#define SIO_HI_IF_STK_2__M 0x3FF --#define SIO_HI_IF_STK_2__PRE 0x2 --#define SIO_HI_IF_STK_2_ADDR__B 0 --#define SIO_HI_IF_STK_2_ADDR__W 10 --#define SIO_HI_IF_STK_2_ADDR__M 0x3FF --#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 -- --#define SIO_HI_IF_STK_3__A 0x440013 --#define SIO_HI_IF_STK_3__W 10 --#define SIO_HI_IF_STK_3__M 0x3FF --#define SIO_HI_IF_STK_3__PRE 0x2 -- --#define SIO_HI_IF_STK_3_ADDR__B 0 --#define SIO_HI_IF_STK_3_ADDR__W 10 --#define SIO_HI_IF_STK_3_ADDR__M 0x3FF --#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 -- --#define SIO_HI_IF_BPT_IDX__A 0x44001F --#define SIO_HI_IF_BPT_IDX__W 1 --#define SIO_HI_IF_BPT_IDX__M 0x1 --#define SIO_HI_IF_BPT_IDX__PRE 0x0 -- --#define SIO_HI_IF_BPT_IDX_ADDR__B 0 --#define SIO_HI_IF_BPT_IDX_ADDR__W 1 --#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 --#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 -- --#define SIO_HI_IF_BPT__A 0x440020 --#define SIO_HI_IF_BPT__W 10 --#define SIO_HI_IF_BPT__M 0x3FF --#define SIO_HI_IF_BPT__PRE 0x2 -- --#define SIO_HI_IF_BPT_ADDR__B 0 --#define SIO_HI_IF_BPT_ADDR__W 10 --#define SIO_HI_IF_BPT_ADDR__M 0x3FF --#define SIO_HI_IF_BPT_ADDR__PRE 0x2 -- -- -- --#define SIO_CC_COMM_EXEC__A 0x450000 --#define SIO_CC_COMM_EXEC__W 2 --#define SIO_CC_COMM_EXEC__M 0x3 --#define SIO_CC_COMM_EXEC__PRE 0x0 --#define SIO_CC_COMM_EXEC_STOP 0x0 --#define SIO_CC_COMM_EXEC_ACTIVE 0x1 --#define SIO_CC_COMM_EXEC_HOLD 0x2 -- --#define SIO_CC_PLL_MODE__A 0x450010 --#define SIO_CC_PLL_MODE__W 6 --#define SIO_CC_PLL_MODE__M 0x3F --#define SIO_CC_PLL_MODE__PRE 0x0 -- --#define SIO_CC_PLL_MODE_FREF_SEL__B 0 --#define SIO_CC_PLL_MODE_FREF_SEL__W 2 --#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 --#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 --#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 --#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 --#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 --#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 -- --#define SIO_CC_PLL_MODE_LOCKSEL__B 2 --#define SIO_CC_PLL_MODE_LOCKSEL__W 2 --#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC --#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 -- --#define SIO_CC_PLL_MODE_BYPASS__B 4 --#define SIO_CC_PLL_MODE_BYPASS__W 2 --#define SIO_CC_PLL_MODE_BYPASS__M 0x30 --#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 --#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 --#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 --#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 -- -- --#define SIO_CC_PLL_TEST__A 0x450011 --#define SIO_CC_PLL_TEST__W 8 --#define SIO_CC_PLL_TEST__M 0xFF --#define SIO_CC_PLL_TEST__PRE 0x0 -- --#define SIO_CC_PLL_LOCK__A 0x450012 --#define SIO_CC_PLL_LOCK__W 1 --#define SIO_CC_PLL_LOCK__M 0x1 --#define SIO_CC_PLL_LOCK__PRE 0x0 --#define SIO_CC_CLK_TEST__A 0x450013 --#define SIO_CC_CLK_TEST__W 8 --#define SIO_CC_CLK_TEST__M 0xFF --#define SIO_CC_CLK_TEST__PRE 0x0 -- --#define SIO_CC_CLK_TEST_SEL1__B 0 --#define SIO_CC_CLK_TEST_SEL1__W 3 --#define SIO_CC_CLK_TEST_SEL1__M 0x7 --#define SIO_CC_CLK_TEST_SEL1__PRE 0x0 -- --#define SIO_CC_CLK_TEST_ENAB1__B 3 --#define SIO_CC_CLK_TEST_ENAB1__W 1 --#define SIO_CC_CLK_TEST_ENAB1__M 0x8 --#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0 -- --#define SIO_CC_CLK_TEST_SEL2__B 4 --#define SIO_CC_CLK_TEST_SEL2__W 3 --#define SIO_CC_CLK_TEST_SEL2__M 0x70 --#define SIO_CC_CLK_TEST_SEL2__PRE 0x0 -- --#define SIO_CC_CLK_TEST_ENAB2__B 7 --#define SIO_CC_CLK_TEST_ENAB2__W 1 --#define SIO_CC_CLK_TEST_ENAB2__M 0x80 --#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0 -- --#define SIO_CC_CLK_MODE__A 0x450014 --#define SIO_CC_CLK_MODE__W 7 --#define SIO_CC_CLK_MODE__M 0x7F --#define SIO_CC_CLK_MODE__PRE 0x0 -- --#define SIO_CC_CLK_MODE_DELAY__B 0 --#define SIO_CC_CLK_MODE_DELAY__W 4 --#define SIO_CC_CLK_MODE_DELAY__M 0xF --#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 -- --#define SIO_CC_CLK_MODE_INVERT__B 4 --#define SIO_CC_CLK_MODE_INVERT__W 1 --#define SIO_CC_CLK_MODE_INVERT__M 0x10 --#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 -- --#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5 --#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1 --#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20 --#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0 -- --#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6 --#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1 --#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40 --#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0 -- --#define SIO_CC_PWD_MODE__A 0x450015 --#define SIO_CC_PWD_MODE__W 4 --#define SIO_CC_PWD_MODE__M 0xF --#define SIO_CC_PWD_MODE__PRE 0x0 -- --#define SIO_CC_PWD_MODE_LEVEL__B 0 --#define SIO_CC_PWD_MODE_LEVEL__W 3 --#define SIO_CC_PWD_MODE_LEVEL__M 0x7 --#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 --#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 --#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 --#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 --#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 --#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 -- --#define SIO_CC_PWD_MODE_USE_LOCK__B 3 --#define SIO_CC_PWD_MODE_USE_LOCK__W 1 --#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8 --#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 -- --#define SIO_CC_SOFT_RST__A 0x450016 --#define SIO_CC_SOFT_RST__W 3 --#define SIO_CC_SOFT_RST__M 0x7 --#define SIO_CC_SOFT_RST__PRE 0x0 -- --#define SIO_CC_SOFT_RST_OFDM__B 0 --#define SIO_CC_SOFT_RST_OFDM__W 1 --#define SIO_CC_SOFT_RST_OFDM__M 0x1 --#define SIO_CC_SOFT_RST_OFDM__PRE 0x0 -- --#define SIO_CC_SOFT_RST_SYS__B 1 --#define SIO_CC_SOFT_RST_SYS__W 1 --#define SIO_CC_SOFT_RST_SYS__M 0x2 --#define SIO_CC_SOFT_RST_SYS__PRE 0x0 -- --#define SIO_CC_SOFT_RST_OSC__B 2 --#define SIO_CC_SOFT_RST_OSC__W 1 --#define SIO_CC_SOFT_RST_OSC__M 0x4 --#define SIO_CC_SOFT_RST_OSC__PRE 0x0 -- -- --#define SIO_CC_UPDATE__A 0x450017 --#define SIO_CC_UPDATE__W 16 --#define SIO_CC_UPDATE__M 0xFFFF --#define SIO_CC_UPDATE__PRE 0x0 --#define SIO_CC_UPDATE_KEY 0xFABA -- -- -- --#define SIO_SA_COMM_EXEC__A 0x460000 --#define SIO_SA_COMM_EXEC__W 2 --#define SIO_SA_COMM_EXEC__M 0x3 --#define SIO_SA_COMM_EXEC__PRE 0x0 --#define SIO_SA_COMM_EXEC_STOP 0x0 --#define SIO_SA_COMM_EXEC_ACTIVE 0x1 --#define SIO_SA_COMM_EXEC_HOLD 0x2 -- --#define SIO_SA_COMM_INT_REQ__A 0x460003 --#define SIO_SA_COMM_INT_REQ__W 1 --#define SIO_SA_COMM_INT_REQ__M 0x1 --#define SIO_SA_COMM_INT_REQ__PRE 0x0 --#define SIO_SA_COMM_INT_STA__A 0x460005 --#define SIO_SA_COMM_INT_STA__W 4 --#define SIO_SA_COMM_INT_STA__M 0xF --#define SIO_SA_COMM_INT_STA__PRE 0x0 -- --#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 --#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 --#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 --#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 -- --#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 --#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 --#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 --#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 -- --#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 --#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 --#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 --#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 -- --#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 --#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 --#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 --#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 -- --#define SIO_SA_COMM_INT_MSK__A 0x460006 --#define SIO_SA_COMM_INT_MSK__W 4 --#define SIO_SA_COMM_INT_MSK__M 0xF --#define SIO_SA_COMM_INT_MSK__PRE 0x0 -- --#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 --#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 --#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 --#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 -- --#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 --#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 --#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 --#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 -- --#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 --#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 --#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 --#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 -- --#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 --#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 --#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 --#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 -- --#define SIO_SA_COMM_INT_STM__A 0x460007 --#define SIO_SA_COMM_INT_STM__W 4 --#define SIO_SA_COMM_INT_STM__M 0xF --#define SIO_SA_COMM_INT_STM__PRE 0x0 -- --#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 --#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 --#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 --#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 -- --#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 --#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 --#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 --#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 -- --#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 --#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 --#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 --#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 -- --#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 --#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 --#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 --#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 -- --#define SIO_SA_PRESCALER__A 0x460010 --#define SIO_SA_PRESCALER__W 13 --#define SIO_SA_PRESCALER__M 0x1FFF --#define SIO_SA_PRESCALER__PRE 0x18B7 --#define SIO_SA_TX_DATA0__A 0x460011 --#define SIO_SA_TX_DATA0__W 16 --#define SIO_SA_TX_DATA0__M 0xFFFF --#define SIO_SA_TX_DATA0__PRE 0x0 --#define SIO_SA_TX_DATA1__A 0x460012 --#define SIO_SA_TX_DATA1__W 16 --#define SIO_SA_TX_DATA1__M 0xFFFF --#define SIO_SA_TX_DATA1__PRE 0x0 --#define SIO_SA_TX_DATA2__A 0x460013 --#define SIO_SA_TX_DATA2__W 16 --#define SIO_SA_TX_DATA2__M 0xFFFF --#define SIO_SA_TX_DATA2__PRE 0x0 --#define SIO_SA_TX_DATA3__A 0x460014 --#define SIO_SA_TX_DATA3__W 16 --#define SIO_SA_TX_DATA3__M 0xFFFF --#define SIO_SA_TX_DATA3__PRE 0x0 --#define SIO_SA_TX_LENGTH__A 0x460015 --#define SIO_SA_TX_LENGTH__W 6 --#define SIO_SA_TX_LENGTH__M 0x3F --#define SIO_SA_TX_LENGTH__PRE 0x0 --#define SIO_SA_TX_COMMAND__A 0x460016 --#define SIO_SA_TX_COMMAND__W 2 --#define SIO_SA_TX_COMMAND__M 0x3 --#define SIO_SA_TX_COMMAND__PRE 0x3 -- --#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 --#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 --#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 --#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 -- --#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 --#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 --#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 --#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 -- --#define SIO_SA_TX_STATUS__A 0x460017 --#define SIO_SA_TX_STATUS__W 2 --#define SIO_SA_TX_STATUS__M 0x3 --#define SIO_SA_TX_STATUS__PRE 0x0 -- --#define SIO_SA_TX_STATUS_BUSY__B 0 --#define SIO_SA_TX_STATUS_BUSY__W 1 --#define SIO_SA_TX_STATUS_BUSY__M 0x1 --#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 -- --#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 --#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 --#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 --#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 -- --#define SIO_SA_RX_DATA0__A 0x460018 --#define SIO_SA_RX_DATA0__W 16 --#define SIO_SA_RX_DATA0__M 0xFFFF --#define SIO_SA_RX_DATA0__PRE 0x0 --#define SIO_SA_RX_DATA1__A 0x460019 --#define SIO_SA_RX_DATA1__W 16 --#define SIO_SA_RX_DATA1__M 0xFFFF --#define SIO_SA_RX_DATA1__PRE 0x0 --#define SIO_SA_RX_LENGTH__A 0x46001A --#define SIO_SA_RX_LENGTH__W 6 --#define SIO_SA_RX_LENGTH__M 0x3F --#define SIO_SA_RX_LENGTH__PRE 0x0 --#define SIO_SA_RX_COMMAND__A 0x46001B --#define SIO_SA_RX_COMMAND__W 1 --#define SIO_SA_RX_COMMAND__M 0x1 --#define SIO_SA_RX_COMMAND__PRE 0x1 -- --#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 --#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 --#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 --#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 -- --#define SIO_SA_RX_STATUS__A 0x46001C --#define SIO_SA_RX_STATUS__W 2 --#define SIO_SA_RX_STATUS__M 0x3 --#define SIO_SA_RX_STATUS__PRE 0x0 -- --#define SIO_SA_RX_STATUS_BUSY__B 0 --#define SIO_SA_RX_STATUS_BUSY__W 1 --#define SIO_SA_RX_STATUS_BUSY__M 0x1 --#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 -- --#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 --#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 --#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 --#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 -- -- -- --#define SIO_OFDM_SH_COMM_EXEC__A 0x470000 --#define SIO_OFDM_SH_COMM_EXEC__W 2 --#define SIO_OFDM_SH_COMM_EXEC__M 0x3 --#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0 --#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0 --#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1 --#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2 -- --#define SIO_OFDM_SH_COMM_MB__A 0x470002 --#define SIO_OFDM_SH_COMM_MB__W 2 --#define SIO_OFDM_SH_COMM_MB__M 0x3 --#define SIO_OFDM_SH_COMM_MB__PRE 0x0 --#define SIO_OFDM_SH_COMM_MB_CTL__B 0 --#define SIO_OFDM_SH_COMM_MB_CTL__W 1 --#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1 --#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0 --#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0 --#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1 --#define SIO_OFDM_SH_COMM_MB_OBS__B 1 --#define SIO_OFDM_SH_COMM_MB_OBS__W 1 --#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2 --#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0 --#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0 --#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2 -- --#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 --#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1 --#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1 --#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0 --#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 --#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 -- --#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011 --#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2 --#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3 --#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0 -- --#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1 -- --#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0 --#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2 -- --#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 --#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1 --#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1 --#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0 --#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 --#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 -- --#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013 --#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3 --#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7 --#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6 --#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0 --#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3 --#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7 --#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6 -- -- -- --#define SIO_BL_COMM_EXEC__A 0x480000 --#define SIO_BL_COMM_EXEC__W 2 --#define SIO_BL_COMM_EXEC__M 0x3 --#define SIO_BL_COMM_EXEC__PRE 0x0 --#define SIO_BL_COMM_EXEC_STOP 0x0 --#define SIO_BL_COMM_EXEC_ACTIVE 0x1 --#define SIO_BL_COMM_EXEC_HOLD 0x2 -- --#define SIO_BL_COMM_INT_REQ__A 0x480003 --#define SIO_BL_COMM_INT_REQ__W 1 --#define SIO_BL_COMM_INT_REQ__M 0x1 --#define SIO_BL_COMM_INT_REQ__PRE 0x0 --#define SIO_BL_COMM_INT_STA__A 0x480005 --#define SIO_BL_COMM_INT_STA__W 1 --#define SIO_BL_COMM_INT_STA__M 0x1 --#define SIO_BL_COMM_INT_STA__PRE 0x0 -- --#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0 --#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1 --#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1 --#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0 -- --#define SIO_BL_COMM_INT_MSK__A 0x480006 --#define SIO_BL_COMM_INT_MSK__W 1 --#define SIO_BL_COMM_INT_MSK__M 0x1 --#define SIO_BL_COMM_INT_MSK__PRE 0x0 -- --#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0 --#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1 --#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1 --#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0 -- --#define SIO_BL_COMM_INT_STM__A 0x480007 --#define SIO_BL_COMM_INT_STM__W 1 --#define SIO_BL_COMM_INT_STM__M 0x1 --#define SIO_BL_COMM_INT_STM__PRE 0x0 -- --#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0 --#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1 --#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1 --#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0 -- --#define SIO_BL_STATUS__A 0x480010 --#define SIO_BL_STATUS__W 1 --#define SIO_BL_STATUS__M 0x1 --#define SIO_BL_STATUS__PRE 0x0 --#define SIO_BL_MODE__A 0x480011 --#define SIO_BL_MODE__W 1 --#define SIO_BL_MODE__M 0x1 --#define SIO_BL_MODE__PRE 0x1 --#define SIO_BL_MODE_DIRECT 0x0 --#define SIO_BL_MODE_CHAIN 0x1 -- --#define SIO_BL_ENABLE__A 0x480012 --#define SIO_BL_ENABLE__W 1 --#define SIO_BL_ENABLE__M 0x1 --#define SIO_BL_ENABLE__PRE 0x0 --#define SIO_BL_ENABLE_OFF 0x0 --#define SIO_BL_ENABLE_ON 0x1 -- --#define SIO_BL_TGT_HDR__A 0x480014 --#define SIO_BL_TGT_HDR__W 12 --#define SIO_BL_TGT_HDR__M 0xFFF --#define SIO_BL_TGT_HDR__PRE 0x0 --#define SIO_BL_TGT_HDR_BANK__B 0 --#define SIO_BL_TGT_HDR_BANK__W 6 --#define SIO_BL_TGT_HDR_BANK__M 0x3F --#define SIO_BL_TGT_HDR_BANK__PRE 0x0 --#define SIO_BL_TGT_HDR_BLOCK__B 6 --#define SIO_BL_TGT_HDR_BLOCK__W 6 --#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0 --#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0 -- --#define SIO_BL_TGT_ADDR__A 0x480015 --#define SIO_BL_TGT_ADDR__W 16 --#define SIO_BL_TGT_ADDR__M 0xFFFF --#define SIO_BL_TGT_ADDR__PRE 0x0 --#define SIO_BL_SRC_ADDR__A 0x480016 --#define SIO_BL_SRC_ADDR__W 16 --#define SIO_BL_SRC_ADDR__M 0xFFFF --#define SIO_BL_SRC_ADDR__PRE 0x0 --#define SIO_BL_SRC_LEN__A 0x480017 --#define SIO_BL_SRC_LEN__W 16 --#define SIO_BL_SRC_LEN__M 0xFFFF --#define SIO_BL_SRC_LEN__PRE 0x0 -- --#define SIO_BL_CHAIN_ADDR__A 0x480018 --#define SIO_BL_CHAIN_ADDR__W 16 --#define SIO_BL_CHAIN_ADDR__M 0xFFFF --#define SIO_BL_CHAIN_ADDR__PRE 0x0 -- --#define SIO_BL_CHAIN_LEN__A 0x480019 --#define SIO_BL_CHAIN_LEN__W 4 --#define SIO_BL_CHAIN_LEN__M 0xF --#define SIO_BL_CHAIN_LEN__PRE 0x2 -- -- -- --#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000 -- -- -- --#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000 -- -- -- --#define SIO_BL_ROM__A 0x4E0000 -- -- -- --#define SIO_PDR_COMM_EXEC__A 0x7F0000 --#define SIO_PDR_COMM_EXEC__W 2 --#define SIO_PDR_COMM_EXEC__M 0x3 --#define SIO_PDR_COMM_EXEC__PRE 0x0 --#define SIO_PDR_COMM_EXEC_STOP 0x0 --#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 --#define SIO_PDR_COMM_EXEC_HOLD 0x2 -- --#define SIO_PDR_MON_CFG__A 0x7F0010 --#define SIO_PDR_MON_CFG__W 4 --#define SIO_PDR_MON_CFG__M 0xF --#define SIO_PDR_MON_CFG__PRE 0x0 -- --#define SIO_PDR_MON_CFG_OSEL__B 0 --#define SIO_PDR_MON_CFG_OSEL__W 1 --#define SIO_PDR_MON_CFG_OSEL__M 0x1 --#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 -- --#define SIO_PDR_MON_CFG_IACT__B 1 --#define SIO_PDR_MON_CFG_IACT__W 1 --#define SIO_PDR_MON_CFG_IACT__M 0x2 --#define SIO_PDR_MON_CFG_IACT__PRE 0x0 -- --#define SIO_PDR_MON_CFG_ISEL__B 2 --#define SIO_PDR_MON_CFG_ISEL__W 1 --#define SIO_PDR_MON_CFG_ISEL__M 0x4 --#define SIO_PDR_MON_CFG_ISEL__PRE 0x0 -- --#define SIO_PDR_MON_CFG_INV_CLK__B 3 --#define SIO_PDR_MON_CFG_INV_CLK__W 1 --#define SIO_PDR_MON_CFG_INV_CLK__M 0x8 --#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0 -- --#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 --#define SIO_PDR_SMA_RX_SEL__W 4 --#define SIO_PDR_SMA_RX_SEL__M 0xF --#define SIO_PDR_SMA_RX_SEL__PRE 0x0 -- --#define SIO_PDR_SMA_RX_SEL_SEL__B 0 --#define SIO_PDR_SMA_RX_SEL_SEL__W 4 --#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF --#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 -- --#define SIO_PDR_SILENT__A 0x7F0013 --#define SIO_PDR_SILENT__W 13 --#define SIO_PDR_SILENT__M 0x1FFF --#define SIO_PDR_SILENT__PRE 0x0 -- --#define SIO_PDR_SILENT_I2S_WS__B 0 --#define SIO_PDR_SILENT_I2S_WS__W 1 --#define SIO_PDR_SILENT_I2S_WS__M 0x1 --#define SIO_PDR_SILENT_I2S_WS__PRE 0x0 -- --#define SIO_PDR_SILENT_I2S_DA__B 1 --#define SIO_PDR_SILENT_I2S_DA__W 1 --#define SIO_PDR_SILENT_I2S_DA__M 0x2 --#define SIO_PDR_SILENT_I2S_DA__PRE 0x0 -- --#define SIO_PDR_SILENT_I2S_CL__B 2 --#define SIO_PDR_SILENT_I2S_CL__W 1 --#define SIO_PDR_SILENT_I2S_CL__M 0x4 --#define SIO_PDR_SILENT_I2S_CL__PRE 0x0 -- --#define SIO_PDR_SILENT_I2C_SCL2__B 3 --#define SIO_PDR_SILENT_I2C_SCL2__W 1 --#define SIO_PDR_SILENT_I2C_SCL2__M 0x8 --#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0 -- --#define SIO_PDR_SILENT_I2C_SDA2__B 4 --#define SIO_PDR_SILENT_I2C_SDA2__W 1 --#define SIO_PDR_SILENT_I2C_SDA2__M 0x10 --#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0 -- --#define SIO_PDR_SILENT_SMA_TX__B 8 --#define SIO_PDR_SILENT_SMA_TX__W 1 --#define SIO_PDR_SILENT_SMA_TX__M 0x100 --#define SIO_PDR_SILENT_SMA_TX__PRE 0x0 -- --#define SIO_PDR_SILENT_SMA_RX__B 9 --#define SIO_PDR_SILENT_SMA_RX__W 1 --#define SIO_PDR_SILENT_SMA_RX__M 0x200 --#define SIO_PDR_SILENT_SMA_RX__PRE 0x0 -- --#define SIO_PDR_SILENT_GPIO__B 10 --#define SIO_PDR_SILENT_GPIO__W 1 --#define SIO_PDR_SILENT_GPIO__M 0x400 --#define SIO_PDR_SILENT_GPIO__PRE 0x0 -- --#define SIO_PDR_SILENT_VSYNC__B 11 --#define SIO_PDR_SILENT_VSYNC__W 1 --#define SIO_PDR_SILENT_VSYNC__M 0x800 --#define SIO_PDR_SILENT_VSYNC__PRE 0x0 -- --#define SIO_PDR_SILENT_IRQN__B 12 --#define SIO_PDR_SILENT_IRQN__W 1 --#define SIO_PDR_SILENT_IRQN__M 0x1000 --#define SIO_PDR_SILENT_IRQN__PRE 0x0 -- --#define SIO_PDR_UIO_IN_LO__A 0x7F0014 --#define SIO_PDR_UIO_IN_LO__W 16 --#define SIO_PDR_UIO_IN_LO__M 0xFFFF --#define SIO_PDR_UIO_IN_LO__PRE 0x0 --#define SIO_PDR_UIO_IN_LO_DATA__B 0 --#define SIO_PDR_UIO_IN_LO_DATA__W 16 --#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF --#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 -- --#define SIO_PDR_UIO_IN_HI__A 0x7F0015 --#define SIO_PDR_UIO_IN_HI__W 14 --#define SIO_PDR_UIO_IN_HI__M 0x3FFF --#define SIO_PDR_UIO_IN_HI__PRE 0x0 --#define SIO_PDR_UIO_IN_HI_DATA__B 0 --#define SIO_PDR_UIO_IN_HI_DATA__W 14 --#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF --#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 -- --#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 --#define SIO_PDR_UIO_OUT_LO__W 16 --#define SIO_PDR_UIO_OUT_LO__M 0xFFFF --#define SIO_PDR_UIO_OUT_LO__PRE 0x0 --#define SIO_PDR_UIO_OUT_LO_DATA__B 0 --#define SIO_PDR_UIO_OUT_LO_DATA__W 16 --#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF --#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 -- --#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 --#define SIO_PDR_UIO_OUT_HI__W 14 --#define SIO_PDR_UIO_OUT_HI__M 0x3FFF --#define SIO_PDR_UIO_OUT_HI__PRE 0x0 --#define SIO_PDR_UIO_OUT_HI_DATA__B 0 --#define SIO_PDR_UIO_OUT_HI_DATA__W 14 --#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF --#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 -- --#define SIO_PDR_PWM1_MODE__A 0x7F0018 --#define SIO_PDR_PWM1_MODE__W 2 --#define SIO_PDR_PWM1_MODE__M 0x3 --#define SIO_PDR_PWM1_MODE__PRE 0x0 --#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 --#define SIO_PDR_PWM1_PRESCALE__W 6 --#define SIO_PDR_PWM1_PRESCALE__M 0x3F --#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 --#define SIO_PDR_PWM1_VALUE__A 0x7F001A --#define SIO_PDR_PWM1_VALUE__W 11 --#define SIO_PDR_PWM1_VALUE__M 0x7FF --#define SIO_PDR_PWM1_VALUE__PRE 0x0 -- --#define SIO_PDR_IRQN_SEL__A 0x7F001B --#define SIO_PDR_IRQN_SEL__W 4 --#define SIO_PDR_IRQN_SEL__M 0xF --#define SIO_PDR_IRQN_SEL__PRE 0x3 --#define SIO_PDR_PWM2_MODE__A 0x7F001C --#define SIO_PDR_PWM2_MODE__W 2 --#define SIO_PDR_PWM2_MODE__M 0x3 --#define SIO_PDR_PWM2_MODE__PRE 0x0 --#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D --#define SIO_PDR_PWM2_PRESCALE__W 6 --#define SIO_PDR_PWM2_PRESCALE__M 0x3F --#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 --#define SIO_PDR_PWM2_VALUE__A 0x7F001E --#define SIO_PDR_PWM2_VALUE__W 11 --#define SIO_PDR_PWM2_VALUE__M 0x7FF --#define SIO_PDR_PWM2_VALUE__PRE 0x0 --#define SIO_PDR_OHW_CFG__A 0x7F001F --#define SIO_PDR_OHW_CFG__W 7 --#define SIO_PDR_OHW_CFG__M 0x7F --#define SIO_PDR_OHW_CFG__PRE 0x0 -- --#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 --#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 --#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 --#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 -- --#define SIO_PDR_OHW_CFG_BYPASS__B 2 --#define SIO_PDR_OHW_CFG_BYPASS__W 1 --#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 --#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 -- --#define SIO_PDR_OHW_CFG_ASEL__B 3 --#define SIO_PDR_OHW_CFG_ASEL__W 3 --#define SIO_PDR_OHW_CFG_ASEL__M 0x38 --#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 -- --#define SIO_PDR_OHW_CFG_SPEED__B 6 --#define SIO_PDR_OHW_CFG_SPEED__W 1 --#define SIO_PDR_OHW_CFG_SPEED__M 0x40 --#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 -- --#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 --#define SIO_PDR_I2S_WS_CFG__W 9 --#define SIO_PDR_I2S_WS_CFG__M 0x1FF --#define SIO_PDR_I2S_WS_CFG__PRE 0x10 --#define SIO_PDR_I2S_WS_CFG_MODE__B 0 --#define SIO_PDR_I2S_WS_CFG_MODE__W 3 --#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 --#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 --#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 --#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 --#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 --#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 --#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 --#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 --#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 --#define SIO_PDR_I2S_WS_CFG_UIO__B 8 --#define SIO_PDR_I2S_WS_CFG_UIO__W 1 --#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 --#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_GPIO_CFG__A 0x7F0021 --#define SIO_PDR_GPIO_CFG__W 9 --#define SIO_PDR_GPIO_CFG__M 0x1FF --#define SIO_PDR_GPIO_CFG__PRE 0x10 --#define SIO_PDR_GPIO_CFG_MODE__B 0 --#define SIO_PDR_GPIO_CFG_MODE__W 3 --#define SIO_PDR_GPIO_CFG_MODE__M 0x7 --#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 --#define SIO_PDR_GPIO_CFG_DRIVE__B 3 --#define SIO_PDR_GPIO_CFG_DRIVE__W 3 --#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 --#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_GPIO_CFG_KEEP__B 6 --#define SIO_PDR_GPIO_CFG_KEEP__W 2 --#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 --#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 --#define SIO_PDR_GPIO_CFG_UIO__B 8 --#define SIO_PDR_GPIO_CFG_UIO__W 1 --#define SIO_PDR_GPIO_CFG_UIO__M 0x100 --#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MSTRT_CFG__A 0x7F0025 --#define SIO_PDR_MSTRT_CFG__W 9 --#define SIO_PDR_MSTRT_CFG__M 0x1FF --#define SIO_PDR_MSTRT_CFG__PRE 0x50 --#define SIO_PDR_MSTRT_CFG_MODE__B 0 --#define SIO_PDR_MSTRT_CFG_MODE__W 3 --#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 --#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 --#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 --#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 --#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 --#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MSTRT_CFG_KEEP__B 6 --#define SIO_PDR_MSTRT_CFG_KEEP__W 2 --#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 --#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MSTRT_CFG_UIO__B 8 --#define SIO_PDR_MSTRT_CFG_UIO__W 1 --#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 --#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MERR_CFG__A 0x7F0026 --#define SIO_PDR_MERR_CFG__W 9 --#define SIO_PDR_MERR_CFG__M 0x1FF --#define SIO_PDR_MERR_CFG__PRE 0x50 --#define SIO_PDR_MERR_CFG_MODE__B 0 --#define SIO_PDR_MERR_CFG_MODE__W 3 --#define SIO_PDR_MERR_CFG_MODE__M 0x7 --#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 --#define SIO_PDR_MERR_CFG_DRIVE__B 3 --#define SIO_PDR_MERR_CFG_DRIVE__W 3 --#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 --#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MERR_CFG_KEEP__B 6 --#define SIO_PDR_MERR_CFG_KEEP__W 2 --#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 --#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MERR_CFG_UIO__B 8 --#define SIO_PDR_MERR_CFG_UIO__W 1 --#define SIO_PDR_MERR_CFG_UIO__M 0x100 --#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MCLK_CFG__A 0x7F0028 --#define SIO_PDR_MCLK_CFG__W 9 --#define SIO_PDR_MCLK_CFG__M 0x1FF --#define SIO_PDR_MCLK_CFG__PRE 0x50 --#define SIO_PDR_MCLK_CFG_MODE__B 0 --#define SIO_PDR_MCLK_CFG_MODE__W 3 --#define SIO_PDR_MCLK_CFG_MODE__M 0x7 --#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 --#define SIO_PDR_MCLK_CFG_DRIVE__B 3 --#define SIO_PDR_MCLK_CFG_DRIVE__W 3 --#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 --#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MCLK_CFG_KEEP__B 6 --#define SIO_PDR_MCLK_CFG_KEEP__W 2 --#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 --#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MCLK_CFG_UIO__B 8 --#define SIO_PDR_MCLK_CFG_UIO__W 1 --#define SIO_PDR_MCLK_CFG_UIO__M 0x100 --#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MVAL_CFG__A 0x7F0029 --#define SIO_PDR_MVAL_CFG__W 9 --#define SIO_PDR_MVAL_CFG__M 0x1FF --#define SIO_PDR_MVAL_CFG__PRE 0x50 --#define SIO_PDR_MVAL_CFG_MODE__B 0 --#define SIO_PDR_MVAL_CFG_MODE__W 3 --#define SIO_PDR_MVAL_CFG_MODE__M 0x7 --#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 --#define SIO_PDR_MVAL_CFG_DRIVE__B 3 --#define SIO_PDR_MVAL_CFG_DRIVE__W 3 --#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 --#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MVAL_CFG_KEEP__B 6 --#define SIO_PDR_MVAL_CFG_KEEP__W 2 --#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 --#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MVAL_CFG_UIO__B 8 --#define SIO_PDR_MVAL_CFG_UIO__W 1 --#define SIO_PDR_MVAL_CFG_UIO__M 0x100 --#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD0_CFG__A 0x7F002A --#define SIO_PDR_MD0_CFG__W 9 --#define SIO_PDR_MD0_CFG__M 0x1FF --#define SIO_PDR_MD0_CFG__PRE 0x50 --#define SIO_PDR_MD0_CFG_MODE__B 0 --#define SIO_PDR_MD0_CFG_MODE__W 3 --#define SIO_PDR_MD0_CFG_MODE__M 0x7 --#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD0_CFG_DRIVE__B 3 --#define SIO_PDR_MD0_CFG_DRIVE__W 3 --#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD0_CFG_KEEP__B 6 --#define SIO_PDR_MD0_CFG_KEEP__W 2 --#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD0_CFG_UIO__B 8 --#define SIO_PDR_MD0_CFG_UIO__W 1 --#define SIO_PDR_MD0_CFG_UIO__M 0x100 --#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD1_CFG__A 0x7F002B --#define SIO_PDR_MD1_CFG__W 9 --#define SIO_PDR_MD1_CFG__M 0x1FF --#define SIO_PDR_MD1_CFG__PRE 0x50 --#define SIO_PDR_MD1_CFG_MODE__B 0 --#define SIO_PDR_MD1_CFG_MODE__W 3 --#define SIO_PDR_MD1_CFG_MODE__M 0x7 --#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD1_CFG_DRIVE__B 3 --#define SIO_PDR_MD1_CFG_DRIVE__W 3 --#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD1_CFG_KEEP__B 6 --#define SIO_PDR_MD1_CFG_KEEP__W 2 --#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD1_CFG_UIO__B 8 --#define SIO_PDR_MD1_CFG_UIO__W 1 --#define SIO_PDR_MD1_CFG_UIO__M 0x100 --#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD2_CFG__A 0x7F002C --#define SIO_PDR_MD2_CFG__W 9 --#define SIO_PDR_MD2_CFG__M 0x1FF --#define SIO_PDR_MD2_CFG__PRE 0x50 --#define SIO_PDR_MD2_CFG_MODE__B 0 --#define SIO_PDR_MD2_CFG_MODE__W 3 --#define SIO_PDR_MD2_CFG_MODE__M 0x7 --#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD2_CFG_DRIVE__B 3 --#define SIO_PDR_MD2_CFG_DRIVE__W 3 --#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD2_CFG_KEEP__B 6 --#define SIO_PDR_MD2_CFG_KEEP__W 2 --#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD2_CFG_UIO__B 8 --#define SIO_PDR_MD2_CFG_UIO__W 1 --#define SIO_PDR_MD2_CFG_UIO__M 0x100 --#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD3_CFG__A 0x7F002D --#define SIO_PDR_MD3_CFG__W 9 --#define SIO_PDR_MD3_CFG__M 0x1FF --#define SIO_PDR_MD3_CFG__PRE 0x50 --#define SIO_PDR_MD3_CFG_MODE__B 0 --#define SIO_PDR_MD3_CFG_MODE__W 3 --#define SIO_PDR_MD3_CFG_MODE__M 0x7 --#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD3_CFG_DRIVE__B 3 --#define SIO_PDR_MD3_CFG_DRIVE__W 3 --#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD3_CFG_KEEP__B 6 --#define SIO_PDR_MD3_CFG_KEEP__W 2 --#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD3_CFG_UIO__B 8 --#define SIO_PDR_MD3_CFG_UIO__W 1 --#define SIO_PDR_MD3_CFG_UIO__M 0x100 --#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD4_CFG__A 0x7F002F --#define SIO_PDR_MD4_CFG__W 9 --#define SIO_PDR_MD4_CFG__M 0x1FF --#define SIO_PDR_MD4_CFG__PRE 0x50 --#define SIO_PDR_MD4_CFG_MODE__B 0 --#define SIO_PDR_MD4_CFG_MODE__W 3 --#define SIO_PDR_MD4_CFG_MODE__M 0x7 --#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD4_CFG_DRIVE__B 3 --#define SIO_PDR_MD4_CFG_DRIVE__W 3 --#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD4_CFG_KEEP__B 6 --#define SIO_PDR_MD4_CFG_KEEP__W 2 --#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD4_CFG_UIO__B 8 --#define SIO_PDR_MD4_CFG_UIO__W 1 --#define SIO_PDR_MD4_CFG_UIO__M 0x100 --#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD5_CFG__A 0x7F0030 --#define SIO_PDR_MD5_CFG__W 9 --#define SIO_PDR_MD5_CFG__M 0x1FF --#define SIO_PDR_MD5_CFG__PRE 0x50 --#define SIO_PDR_MD5_CFG_MODE__B 0 --#define SIO_PDR_MD5_CFG_MODE__W 3 --#define SIO_PDR_MD5_CFG_MODE__M 0x7 --#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD5_CFG_DRIVE__B 3 --#define SIO_PDR_MD5_CFG_DRIVE__W 3 --#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD5_CFG_KEEP__B 6 --#define SIO_PDR_MD5_CFG_KEEP__W 2 --#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD5_CFG_UIO__B 8 --#define SIO_PDR_MD5_CFG_UIO__W 1 --#define SIO_PDR_MD5_CFG_UIO__M 0x100 --#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD6_CFG__A 0x7F0031 --#define SIO_PDR_MD6_CFG__W 9 --#define SIO_PDR_MD6_CFG__M 0x1FF --#define SIO_PDR_MD6_CFG__PRE 0x50 --#define SIO_PDR_MD6_CFG_MODE__B 0 --#define SIO_PDR_MD6_CFG_MODE__W 3 --#define SIO_PDR_MD6_CFG_MODE__M 0x7 --#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD6_CFG_DRIVE__B 3 --#define SIO_PDR_MD6_CFG_DRIVE__W 3 --#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD6_CFG_KEEP__B 6 --#define SIO_PDR_MD6_CFG_KEEP__W 2 --#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD6_CFG_UIO__B 8 --#define SIO_PDR_MD6_CFG_UIO__W 1 --#define SIO_PDR_MD6_CFG_UIO__M 0x100 --#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_MD7_CFG__A 0x7F0032 --#define SIO_PDR_MD7_CFG__W 9 --#define SIO_PDR_MD7_CFG__M 0x1FF --#define SIO_PDR_MD7_CFG__PRE 0x50 --#define SIO_PDR_MD7_CFG_MODE__B 0 --#define SIO_PDR_MD7_CFG_MODE__W 3 --#define SIO_PDR_MD7_CFG_MODE__M 0x7 --#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 --#define SIO_PDR_MD7_CFG_DRIVE__B 3 --#define SIO_PDR_MD7_CFG_DRIVE__W 3 --#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 --#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_MD7_CFG_KEEP__B 6 --#define SIO_PDR_MD7_CFG_KEEP__W 2 --#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 --#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 --#define SIO_PDR_MD7_CFG_UIO__B 8 --#define SIO_PDR_MD7_CFG_UIO__W 1 --#define SIO_PDR_MD7_CFG_UIO__M 0x100 --#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 --#define SIO_PDR_I2C_SCL1_CFG__W 9 --#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF --#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 --#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 --#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 --#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 --#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 --#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 --#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 --#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 --#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 --#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 --#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 --#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 --#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 --#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 --#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 --#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 --#define SIO_PDR_I2C_SDA1_CFG__W 9 --#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF --#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 --#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 --#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 --#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 --#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 --#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 --#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 --#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 --#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 --#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 --#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 --#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 --#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 --#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 --#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 --#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_VSYNC_CFG__A 0x7F0036 --#define SIO_PDR_VSYNC_CFG__W 9 --#define SIO_PDR_VSYNC_CFG__M 0x1FF --#define SIO_PDR_VSYNC_CFG__PRE 0x10 --#define SIO_PDR_VSYNC_CFG_MODE__B 0 --#define SIO_PDR_VSYNC_CFG_MODE__W 3 --#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 --#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 --#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 --#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 --#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 --#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_VSYNC_CFG_KEEP__B 6 --#define SIO_PDR_VSYNC_CFG_KEEP__W 2 --#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 --#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 --#define SIO_PDR_VSYNC_CFG_UIO__B 8 --#define SIO_PDR_VSYNC_CFG_UIO__W 1 --#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 --#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 --#define SIO_PDR_SMA_RX_CFG__W 9 --#define SIO_PDR_SMA_RX_CFG__M 0x1FF --#define SIO_PDR_SMA_RX_CFG__PRE 0x10 --#define SIO_PDR_SMA_RX_CFG_MODE__B 0 --#define SIO_PDR_SMA_RX_CFG_MODE__W 3 --#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 --#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 --#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 --#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 --#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 --#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 --#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 --#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 --#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 --#define SIO_PDR_SMA_RX_CFG_UIO__B 8 --#define SIO_PDR_SMA_RX_CFG_UIO__W 1 --#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 --#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 --#define SIO_PDR_SMA_TX_CFG__W 9 --#define SIO_PDR_SMA_TX_CFG__M 0x1FF --#define SIO_PDR_SMA_TX_CFG__PRE 0x90 --#define SIO_PDR_SMA_TX_CFG_MODE__B 0 --#define SIO_PDR_SMA_TX_CFG_MODE__W 3 --#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 --#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 --#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 --#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 --#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 --#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 --#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 --#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 --#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 --#define SIO_PDR_SMA_TX_CFG_UIO__B 8 --#define SIO_PDR_SMA_TX_CFG_UIO__W 1 --#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 --#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F --#define SIO_PDR_I2C_SDA2_CFG__W 9 --#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF --#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 --#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 --#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 --#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 --#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 --#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 --#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 --#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 --#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 --#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 --#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 --#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 --#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 --#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 --#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 --#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 --#define SIO_PDR_I2C_SCL2_CFG__W 9 --#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF --#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 --#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 --#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 --#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 --#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 --#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 --#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 --#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 --#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 --#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 --#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 --#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 --#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 --#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 --#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 --#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 --#define SIO_PDR_I2S_CL_CFG__W 9 --#define SIO_PDR_I2S_CL_CFG__M 0x1FF --#define SIO_PDR_I2S_CL_CFG__PRE 0x10 --#define SIO_PDR_I2S_CL_CFG_MODE__B 0 --#define SIO_PDR_I2S_CL_CFG_MODE__W 3 --#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 --#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 --#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 --#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 --#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 --#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 --#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 --#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 --#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 --#define SIO_PDR_I2S_CL_CFG_UIO__B 8 --#define SIO_PDR_I2S_CL_CFG_UIO__W 1 --#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 --#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 --#define SIO_PDR_I2S_DA_CFG__W 9 --#define SIO_PDR_I2S_DA_CFG__M 0x1FF --#define SIO_PDR_I2S_DA_CFG__PRE 0x10 --#define SIO_PDR_I2S_DA_CFG_MODE__B 0 --#define SIO_PDR_I2S_DA_CFG_MODE__W 3 --#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 --#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 --#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 --#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 --#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 --#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 --#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 --#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 --#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 --#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 --#define SIO_PDR_I2S_DA_CFG_UIO__B 8 --#define SIO_PDR_I2S_DA_CFG_UIO__W 1 --#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 --#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 -- --#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 --#define SIO_PDR_GPIO_GPIO_FNC__W 2 --#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 --#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 --#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 --#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 --#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 --#define SIO_PDR_MSTRT_GPIO_FNC__W 2 --#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 --#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 --#define SIO_PDR_MERR_GPIO_FNC__W 2 --#define SIO_PDR_MERR_GPIO_FNC__M 0x3 --#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 --#define SIO_PDR_MCLK_GPIO_FNC__W 2 --#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 --#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 --#define SIO_PDR_MVAL_GPIO_FNC__W 2 --#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 --#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 --#define SIO_PDR_MD0_GPIO_FNC__W 2 --#define SIO_PDR_MD0_GPIO_FNC__M 0x3 --#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 --#define SIO_PDR_MD1_GPIO_FNC__W 2 --#define SIO_PDR_MD1_GPIO_FNC__M 0x3 --#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 --#define SIO_PDR_MD2_GPIO_FNC__W 2 --#define SIO_PDR_MD2_GPIO_FNC__M 0x3 --#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 --#define SIO_PDR_MD3_GPIO_FNC__W 2 --#define SIO_PDR_MD3_GPIO_FNC__M 0x3 --#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A --#define SIO_PDR_MD4_GPIO_FNC__W 2 --#define SIO_PDR_MD4_GPIO_FNC__M 0x3 --#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B --#define SIO_PDR_MD5_GPIO_FNC__W 2 --#define SIO_PDR_MD5_GPIO_FNC__M 0x3 --#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C --#define SIO_PDR_MD6_GPIO_FNC__W 2 --#define SIO_PDR_MD6_GPIO_FNC__M 0x3 --#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D --#define SIO_PDR_MD7_GPIO_FNC__W 2 --#define SIO_PDR_MD7_GPIO_FNC__M 0x3 --#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 --#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 --#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 --#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E --#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 --#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 --#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 --#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 --#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 --#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 -- --#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F --#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 --#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 --#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 --#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 --#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 --#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 --#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 -- --#endif -- -- -+#define AUD_COMM_EXEC__A 0x1000000 -+#define AUD_COMM_EXEC_STOP 0x0 -+#define FEC_COMM_EXEC__A 0x1C00000 -+#define FEC_COMM_EXEC_STOP 0x0 -+#define FEC_COMM_EXEC_ACTIVE 0x1 -+#define FEC_DI_COMM_EXEC__A 0x1C20000 -+#define FEC_DI_COMM_EXEC_STOP 0x0 -+#define FEC_DI_INPUT_CTL__A 0x1C20016 -+#define FEC_RS_COMM_EXEC__A 0x1C30000 -+#define FEC_RS_COMM_EXEC_STOP 0x0 -+#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 -+#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 -+#define FEC_OC_MODE__A 0x1C40011 -+#define FEC_OC_MODE_PARITY__M 0x1 -+#define FEC_OC_DTO_MODE__A 0x1C40014 -+#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 -+#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 -+#define FEC_OC_DTO_PERIOD__A 0x1C40015 -+#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 -+#define FEC_OC_FCT_MODE__A 0x1C4001A -+#define FEC_OC_FCT_MODE__PRE 0x0 -+#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 -+#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 -+#define FEC_OC_TMD_MODE__A 0x1C4001E -+#define FEC_OC_TMD_COUNT__A 0x1C4001F -+#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 -+#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 -+#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 -+#define FEC_OC_AVR_PARM_A__A 0x1C40026 -+#define FEC_OC_AVR_PARM_B__A 0x1C40027 -+#define FEC_OC_RCN_GAIN__A 0x1C4002E -+#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 -+#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 -+#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 -+#define FEC_OC_SNC_MODE__A 0x1C40040 -+#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 -+#define FEC_OC_SNC_LWM__A 0x1C40041 -+#define FEC_OC_SNC_HWM__A 0x1C40042 -+#define FEC_OC_SNC_UNLOCK__A 0x1C40043 -+#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 -+#define FEC_OC_IPR_MODE__A 0x1C40048 -+#define FEC_OC_IPR_MODE_SERIAL__M 0x1 -+#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 -+#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 -+#define FEC_OC_IPR_INVERT__A 0x1C40049 -+#define FEC_OC_IPR_INVERT_MD0__M 0x1 -+#define FEC_OC_IPR_INVERT_MD1__M 0x2 -+#define FEC_OC_IPR_INVERT_MD2__M 0x4 -+#define FEC_OC_IPR_INVERT_MD3__M 0x8 -+#define FEC_OC_IPR_INVERT_MD4__M 0x10 -+#define FEC_OC_IPR_INVERT_MD5__M 0x20 -+#define FEC_OC_IPR_INVERT_MD6__M 0x40 -+#define FEC_OC_IPR_INVERT_MD7__M 0x80 -+#define FEC_OC_IPR_INVERT_MERR__M 0x100 -+#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 -+#define FEC_OC_IPR_INVERT_MVAL__M 0x400 -+#define FEC_OC_IPR_INVERT_MCLK__M 0x800 -+#define FEC_OC_OCR_INVERT__A 0x1C40052 -+#define IQM_COMM_EXEC__A 0x1800000 -+#define IQM_COMM_EXEC_B_STOP 0x0 -+#define IQM_COMM_EXEC_B_ACTIVE 0x1 -+#define IQM_FS_RATE_OFS_LO__A 0x1820010 -+#define IQM_FS_ADJ_SEL__A 0x1820014 -+#define IQM_FS_ADJ_SEL_B_OFF 0x0 -+#define IQM_FS_ADJ_SEL_B_QAM 0x1 -+#define IQM_FS_ADJ_SEL_B_VSB 0x2 -+#define IQM_FD_RATESEL__A 0x1830010 -+#define IQM_RC_RATE_OFS_LO__A 0x1840010 -+#define IQM_RC_RATE_OFS_LO__W 16 -+#define IQM_RC_RATE_OFS_LO__M 0xFFFF -+#define IQM_RC_RATE_OFS_HI__M 0xFF -+#define IQM_RC_ADJ_SEL__A 0x1840014 -+#define IQM_RC_ADJ_SEL_B_OFF 0x0 -+#define IQM_RC_ADJ_SEL_B_QAM 0x1 -+#define IQM_RC_ADJ_SEL_B_VSB 0x2 -+#define IQM_RC_STRETCH__A 0x1840016 -+#define IQM_CF_COMM_INT_MSK__A 0x1860006 -+#define IQM_CF_SYMMETRIC__A 0x1860010 -+#define IQM_CF_MIDTAP__A 0x1860011 -+#define IQM_CF_MIDTAP_RE__B 0 -+#define IQM_CF_MIDTAP_IM__B 1 -+#define IQM_CF_OUT_ENA__A 0x1860012 -+#define IQM_CF_OUT_ENA_QAM__B 1 -+#define IQM_CF_OUT_ENA_OFDM__M 0x4 -+#define IQM_CF_ADJ_SEL__A 0x1860013 -+#define IQM_CF_SCALE__A 0x1860014 -+#define IQM_CF_SCALE_SH__A 0x1860015 -+#define IQM_CF_SCALE_SH__PRE 0x0 -+#define IQM_CF_POW_MEAS_LEN__A 0x1860017 -+#define IQM_CF_DS_ENA__A 0x1860019 -+#define IQM_CF_TAP_RE0__A 0x1860020 -+#define IQM_CF_TAP_IM0__A 0x1860040 -+#define IQM_CF_CLP_VAL__A 0x1860060 -+#define IQM_CF_DATATH__A 0x1860061 -+#define IQM_CF_PKDTH__A 0x1860062 -+#define IQM_CF_WND_LEN__A 0x1860063 -+#define IQM_CF_DET_LCT__A 0x1860064 -+#define IQM_CF_BYPASSDET__A 0x1860067 -+#define IQM_AF_COMM_EXEC__A 0x1870000 -+#define IQM_AF_COMM_EXEC_ACTIVE 0x1 -+#define IQM_AF_CLKNEG__A 0x1870012 -+#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 -+#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 -+#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 -+#define IQM_AF_START_LOCK__A 0x187001B -+#define IQM_AF_PHASE0__A 0x187001C -+#define IQM_AF_PHASE1__A 0x187001D -+#define IQM_AF_PHASE2__A 0x187001E -+#define IQM_AF_CLP_LEN__A 0x1870023 -+#define IQM_AF_CLP_TH__A 0x1870024 -+#define IQM_AF_SNS_LEN__A 0x1870026 -+#define IQM_AF_AGC_IF__A 0x1870028 -+#define IQM_AF_AGC_RF__A 0x1870029 -+#define IQM_AF_PDREF__A 0x187002B -+#define IQM_AF_PDREF__M 0x1F -+#define IQM_AF_STDBY__A 0x187002C -+#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 -+#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 -+#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 -+#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 -+#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 -+#define IQM_AF_AMUX__A 0x187002D -+#define IQM_AF_AMUX_SIGNAL2ADC 0x1 -+#define IQM_AF_UPD_SEL__A 0x187002F -+#define IQM_AF_INC_LCT__A 0x1870034 -+#define IQM_AF_INC_BYPASS__A 0x1870036 -+#define OFDM_CP_COMM_EXEC__A 0x2800000 -+#define OFDM_CP_COMM_EXEC_STOP 0x0 -+#define OFDM_EC_SB_PRIOR__A 0x3410013 -+#define OFDM_EC_SB_PRIOR_HI 0x0 -+#define OFDM_EC_SB_PRIOR_LO 0x1 -+#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 -+#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 -+#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 -+#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 -+#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 -+#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 -+#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E -+#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F -+#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 -+#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 -+#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 -+#define OFDM_LC_COMM_EXEC__A 0x3800000 -+#define OFDM_LC_COMM_EXEC_STOP 0x0 -+#define OFDM_SC_COMM_EXEC__A 0x3C00000 -+#define OFDM_SC_COMM_EXEC_STOP 0x0 -+#define OFDM_SC_COMM_STATE__A 0x3C00001 -+#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 -+#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 -+#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 -+#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 -+#define OFDM_SC_RA_RAM_CMD_NULL 0x0 -+#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 -+#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -+#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 -+#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -+#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 -+#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 -+#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -+#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -+#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 -+#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 -+#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -+#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -+#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -+#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 -+#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 -+#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 -+#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC -+#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 -+#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -+#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -+#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 -+#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 -+#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 -+#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -+#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 -+#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 -+#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 -+#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 -+#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -+#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 -+#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 -+#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 -+#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -+#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 -+#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 -+#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 -+#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B -+#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 -+#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 -+#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 -+#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 -+#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D -+#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E -+#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F -+#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 -+#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF -+#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 -+#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 -+#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 -+#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 -+#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D -+#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 -+#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 -+#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 -+#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 -+#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 -+#define QAM_COMM_EXEC__A 0x1400000 -+#define QAM_COMM_EXEC_STOP 0x0 -+#define QAM_COMM_EXEC_ACTIVE 0x1 -+#define QAM_TOP_ANNEX_A 0x0 -+#define QAM_TOP_ANNEX_C 0x2 -+#define QAM_SL_ERR_POWER__A 0x1430017 -+#define QAM_DQ_QUAL_FUN0__A 0x1440018 -+#define QAM_DQ_QUAL_FUN1__A 0x1440019 -+#define QAM_DQ_QUAL_FUN2__A 0x144001A -+#define QAM_DQ_QUAL_FUN3__A 0x144001B -+#define QAM_DQ_QUAL_FUN4__A 0x144001C -+#define QAM_DQ_QUAL_FUN5__A 0x144001D -+#define QAM_LC_MODE__A 0x1450010 -+#define QAM_LC_QUAL_TAB0__A 0x1450018 -+#define QAM_LC_QUAL_TAB1__A 0x1450019 -+#define QAM_LC_QUAL_TAB2__A 0x145001A -+#define QAM_LC_QUAL_TAB3__A 0x145001B -+#define QAM_LC_QUAL_TAB4__A 0x145001C -+#define QAM_LC_QUAL_TAB5__A 0x145001D -+#define QAM_LC_QUAL_TAB6__A 0x145001E -+#define QAM_LC_QUAL_TAB8__A 0x145001F -+#define QAM_LC_QUAL_TAB9__A 0x1450020 -+#define QAM_LC_QUAL_TAB10__A 0x1450021 -+#define QAM_LC_QUAL_TAB12__A 0x1450022 -+#define QAM_LC_QUAL_TAB15__A 0x1450023 -+#define QAM_LC_QUAL_TAB16__A 0x1450024 -+#define QAM_LC_QUAL_TAB20__A 0x1450025 -+#define QAM_LC_QUAL_TAB25__A 0x1450026 -+#define QAM_LC_LPF_FACTORP__A 0x1450028 -+#define QAM_LC_LPF_FACTORI__A 0x1450029 -+#define QAM_LC_RATE_LIMIT__A 0x145002A -+#define QAM_LC_SYMBOL_FREQ__A 0x145002B -+#define QAM_SY_TIMEOUT__A 0x1470011 -+#define QAM_SY_TIMEOUT__PRE 0x3A98 -+#define QAM_SY_SYNC_LWM__A 0x1470012 -+#define QAM_SY_SYNC_AWM__A 0x1470013 -+#define QAM_SY_SYNC_HWM__A 0x1470014 -+#define QAM_SY_SP_INV__A 0x1470017 -+#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 -+#define SCU_COMM_EXEC__A 0x800000 -+#define SCU_COMM_EXEC_STOP 0x0 -+#define SCU_COMM_EXEC_ACTIVE 0x1 -+#define SCU_COMM_EXEC_HOLD 0x2 -+#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF -+#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 -+#define SCU_RAM_GPIO__A 0x831EC7 -+#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 -+#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 -+#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB -+#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 -+#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 -+#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 -+#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 -+#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 -+#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A -+#define SCU_RAM_AGC_RF_MAX__A 0x831F1B -+#define SCU_RAM_AGC_CONFIG__A 0x831F24 -+#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 -+#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 -+#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 -+#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 -+#define SCU_RAM_AGC_KI__A 0x831F25 -+#define SCU_RAM_AGC_KI_RF__B 4 -+#define SCU_RAM_AGC_KI_RF__M 0xF0 -+#define SCU_RAM_AGC_KI_IF__B 8 -+#define SCU_RAM_AGC_KI_IF__M 0xF00 -+#define SCU_RAM_AGC_KI_RED__A 0x831F26 -+#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 -+#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC -+#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 -+#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 -+#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 -+#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 -+#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 -+#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A -+#define SCU_RAM_AGC_KI_MIN__A 0x831F2B -+#define SCU_RAM_AGC_KI_MAX__A 0x831F2C -+#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D -+#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E -+#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F -+#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 -+#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 -+#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 -+#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 -+#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 -+#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 -+#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 -+#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 -+#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 -+#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 -+#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A -+#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B -+#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D -+#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E -+#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F -+#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 -+#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 -+#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 -+#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 -+#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 -+#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 -+#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 -+#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 -+#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 -+#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 -+#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 -+#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 -+#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 -+#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 -+#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A -+#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E -+#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F -+#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 -+#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 -+#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 -+#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 -+#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 -+#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 -+#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 -+#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 -+#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 -+#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A -+#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B -+#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C -+#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D -+#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E -+#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F -+#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 -+#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 -+#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 -+#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 -+#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 -+#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 -+#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 -+#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 -+#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 -+#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 -+#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA -+#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB -+#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC -+#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD -+#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE -+#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF -+#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 -+#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 -+#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 -+#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 -+#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 -+#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 -+#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA -+#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB -+#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC -+#define SCU_RAM_PARAM_15__A 0x831FED -+#define SCU_RAM_PARAM_0__A 0x831FFC -+#define SCU_RAM_COMMAND__A 0x831FFD -+#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 -+#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 -+#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 -+#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 -+#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 -+#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 -+#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 -+#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 -+#define SIO_TOP_COMM_KEY__A 0x41000F -+#define SIO_TOP_COMM_KEY_KEY 0xFABA -+#define SIO_TOP_JTAGID_LO__A 0x410012 -+#define SIO_HI_RA_RAM_RES__A 0x420031 -+#define SIO_HI_RA_RAM_CMD__A 0x420032 -+#define SIO_HI_RA_RAM_CMD_RESET 0x2 -+#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 -+#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 -+#define SIO_HI_RA_RAM_PAR_1__A 0x420033 -+#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 -+#define SIO_HI_RA_RAM_PAR_2__A 0x420034 -+#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F -+#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 -+#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 -+#define SIO_HI_RA_RAM_PAR_3__A 0x420035 -+#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F -+#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 -+#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 -+#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 -+#define SIO_HI_RA_RAM_PAR_4__A 0x420036 -+#define SIO_HI_RA_RAM_PAR_5__A 0x420037 -+#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 -+#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 -+#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 -+#define SIO_HI_RA_RAM_PAR_6__A 0x420038 -+#define SIO_CC_PLL_LOCK__A 0x450012 -+#define SIO_CC_PWD_MODE__A 0x450015 -+#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 -+#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 -+#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 -+#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 -+#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 -+#define SIO_CC_SOFT_RST__A 0x450016 -+#define SIO_CC_SOFT_RST_OFDM__M 0x1 -+#define SIO_CC_SOFT_RST_SYS__M 0x2 -+#define SIO_CC_SOFT_RST_OSC__M 0x4 -+#define SIO_CC_UPDATE__A 0x450017 -+#define SIO_CC_UPDATE_KEY 0xFABA -+#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 -+#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 -+#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 -+#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 -+#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 -+#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 -+#define SIO_BL_COMM_EXEC__A 0x480000 -+#define SIO_BL_COMM_EXEC_ACTIVE 0x1 -+#define SIO_BL_STATUS__A 0x480010 -+#define SIO_BL_MODE__A 0x480011 -+#define SIO_BL_MODE_DIRECT 0x0 -+#define SIO_BL_MODE_CHAIN 0x1 -+#define SIO_BL_ENABLE__A 0x480012 -+#define SIO_BL_ENABLE_ON 0x1 -+#define SIO_BL_TGT_HDR__A 0x480014 -+#define SIO_BL_TGT_ADDR__A 0x480015 -+#define SIO_BL_SRC_ADDR__A 0x480016 -+#define SIO_BL_SRC_LEN__A 0x480017 -+#define SIO_BL_CHAIN_ADDR__A 0x480018 -+#define SIO_BL_CHAIN_LEN__A 0x480019 -+#define SIO_PDR_MON_CFG__A 0x7F0010 -+#define SIO_PDR_UIO_IN_HI__A 0x7F0015 -+#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 -+#define SIO_PDR_OHW_CFG__A 0x7F001F -+#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 -+#define SIO_PDR_GPIO_CFG__A 0x7F0021 -+#define SIO_PDR_MSTRT_CFG__A 0x7F0025 -+#define SIO_PDR_MERR_CFG__A 0x7F0026 -+#define SIO_PDR_MCLK_CFG__A 0x7F0028 -+#define SIO_PDR_MCLK_CFG_DRIVE__B 3 -+#define SIO_PDR_MVAL_CFG__A 0x7F0029 -+#define SIO_PDR_MD0_CFG__A 0x7F002A -+#define SIO_PDR_MD0_CFG_DRIVE__B 3 -+#define SIO_PDR_MD1_CFG__A 0x7F002B -+#define SIO_PDR_MD2_CFG__A 0x7F002C -+#define SIO_PDR_MD3_CFG__A 0x7F002D -+#define SIO_PDR_MD4_CFG__A 0x7F002F -+#define SIO_PDR_MD5_CFG__A 0x7F0030 -+#define SIO_PDR_MD6_CFG__A 0x7F0031 -+#define SIO_PDR_MD7_CFG__A 0x7F0032 -+#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 -+#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 -diff --git a/frontends/tda18271c2dd.c b/frontends/tda18271c2dd.c -index 5c098c7..ad7c72e 100644 ---- a/frontends/tda18271c2dd.c -+++ b/frontends/tda18271c2dd.c -@@ -1,1301 +1,1246 @@ --/* -- * tda18271c2dd: Driver for the TDA18271C2 tuner -- * -- * Copyright (C) 2010 Digital Devices GmbH -- * -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License -- * version 2 only, as published by the Free Software Foundation. -- * -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- * 02110-1301, USA -- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#include "dvb_frontend.h" -- --struct SStandardParam { -- s32 m_IFFrequency; -- u32 m_BandWidth; -- u8 m_EP3_4_0; -- u8 m_EB22; --}; -- --struct SMap { -- u32 m_Frequency; -- u8 m_Param; --}; -- --struct SMapI { -- u32 m_Frequency; -- s32 m_Param; --}; -- --struct SMap2 { -- u32 m_Frequency; -- u8 m_Param1; -- u8 m_Param2; --}; -- --struct SRFBandMap { -- u32 m_RF_max; -- u32 m_RF1_Default; -- u32 m_RF2_Default; -- u32 m_RF3_Default; --}; -- --enum ERegister { -- ID = 0, -- TM, -- PL, -- EP1, EP2, EP3, EP4, EP5, -- CPD, CD1, CD2, CD3, -- MPD, MD1, MD2, MD3, -- EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10, -- EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20, -- EB21, EB22, EB23, -- NUM_REGS --}; -- --struct tda_state { -- struct i2c_adapter *i2c; -- u8 adr; -- -- u32 m_Frequency; -- u32 IF; -- -- u8 m_IFLevelAnalog; -- u8 m_IFLevelDigital; -- u8 m_IFLevelDVBC; -- u8 m_IFLevelDVBT; -- -- u8 m_EP4; -- u8 m_EP3_Standby; -- -- bool m_bMaster; -- -- s32 m_SettlingTime; -- -- u8 m_Regs[NUM_REGS]; -- -- /* Tracking filter settings for band 0..6 */ -- u32 m_RF1[7]; -- s32 m_RF_A1[7]; -- s32 m_RF_B1[7]; -- u32 m_RF2[7]; -- s32 m_RF_A2[7]; -- s32 m_RF_B2[7]; -- u32 m_RF3[7]; -- -- u8 m_TMValue_RFCal; /* Calibration temperatur */ -- -- bool m_bFMInput; /* true to use Pin 8 for FM Radio */ -- --}; -- --static int PowerScan(struct tda_state *state, -- u8 RFBand, u32 RF_in, -- u32 *pRF_Out, bool *pbcal); -- --static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) --{ -- struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, -- .buf = data, .len = len} }; -- return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; --} -- --static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) --{ -- struct i2c_msg msg = {.addr = adr, .flags = 0, -- .buf = data, .len = len}; -- -- if (i2c_transfer(adap, &msg, 1) != 1) { -- printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr); -- return -1; -- } -- return 0; --} -- --static int WriteRegs(struct tda_state *state, -- u8 SubAddr, u8 *Regs, u16 nRegs) --{ -- u8 data[nRegs+1]; -- -- data[0] = SubAddr; -- memcpy(data + 1, Regs, nRegs); -- return i2c_write(state->i2c, state->adr, data, nRegs+1); --} -- --static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) --{ -- u8 msg[2] = {SubAddr, Reg}; -- -- return i2c_write(state->i2c, state->adr, msg, 2); --} -- --static int Read(struct tda_state *state, u8 * Regs) --{ -- return i2c_readn(state->i2c, state->adr, Regs, 16); --} -- --static int ReadExtented(struct tda_state *state, u8 * Regs) --{ -- return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS); --} -- --static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo) --{ -- return WriteRegs(state, RegFrom, -- &state->m_Regs[RegFrom], RegTo-RegFrom+1); --} --static int UpdateReg(struct tda_state *state, u8 Reg) --{ -- return WriteReg(state, Reg, state->m_Regs[Reg]); --} -- --#include "tda18271c2dd_maps.h" -- --static void reset(struct tda_state *state) --{ -- u32 ulIFLevelAnalog = 0; -- u32 ulIFLevelDigital = 2; -- u32 ulIFLevelDVBC = 7; -- u32 ulIFLevelDVBT = 6; -- u32 ulXTOut = 0; -- u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */ -- u32 ulSlave = 0; -- u32 ulFMInput = 0; -- u32 ulSettlingTime = 100; -- -- state->m_Frequency = 0; -- state->m_SettlingTime = 100; -- state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2; -- state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2; -- state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2; -- state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2; -- -- state->m_EP4 = 0x20; -- if (ulXTOut != 0) -- state->m_EP4 |= 0x40; -- -- state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F; -- state->m_bMaster = (ulSlave == 0); -- -- state->m_SettlingTime = ulSettlingTime; -- -- state->m_bFMInput = (ulFMInput == 2); --} -- --static bool SearchMap1(struct SMap Map[], -- u32 Frequency, u8 *pParam) --{ -- int i = 0; -- -- while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency)) -- i += 1; -- if (Map[i].m_Frequency == 0) -- return false; -- *pParam = Map[i].m_Param; -- return true; --} -- --static bool SearchMap2(struct SMapI Map[], -- u32 Frequency, s32 *pParam) --{ -- int i = 0; -- -- while ((Map[i].m_Frequency != 0) && -- (Frequency > Map[i].m_Frequency)) -- i += 1; -- if (Map[i].m_Frequency == 0) -- return false; -- *pParam = Map[i].m_Param; -- return true; --} -- --static bool SearchMap3(struct SMap2 Map[], u32 Frequency, -- u8 *pParam1, u8 *pParam2) --{ -- int i = 0; -- -- while ((Map[i].m_Frequency != 0) && -- (Frequency > Map[i].m_Frequency)) -- i += 1; -- if (Map[i].m_Frequency == 0) -- return false; -- *pParam1 = Map[i].m_Param1; -- *pParam2 = Map[i].m_Param2; -- return true; --} -- --static bool SearchMap4(struct SRFBandMap Map[], -- u32 Frequency, u8 *pRFBand) --{ -- int i = 0; -- -- while (i < 7 && (Frequency > Map[i].m_RF_max)) -- i += 1; -- if (i == 7) -- return false; -- *pRFBand = i; -- return true; --} -- --static int ThermometerRead(struct tda_state *state, u8 *pTM_Value) --{ -- int status = 0; -- -- do { -- u8 Regs[16]; -- state->m_Regs[TM] |= 0x10; -- status = UpdateReg(state, TM); -- if (status < 0) -- break; -- status = Read(state, Regs); -- if (status < 0) -- break; -- if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) || -- ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) { -- state->m_Regs[TM] ^= 0x20; -- status = UpdateReg(state, TM); -- if (status < 0) -- break; -- msleep(10); -- status = Read(state, Regs); -- if (status < 0) -- break; -- } -- *pTM_Value = (Regs[TM] & 0x20) -- ? m_Thermometer_Map_2[Regs[TM] & 0x0F] -- : m_Thermometer_Map_1[Regs[TM] & 0x0F] ; -- state->m_Regs[TM] &= ~0x10; /* Thermometer off */ -- status = UpdateReg(state, TM); -- if (status < 0) -- break; -- state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */ -- status = UpdateReg(state, EP4); -- if (status < 0) -- break; -- } while (0); -- -- return status; --} -- --static int StandBy(struct tda_state *state) --{ -- int status = 0; -- do { -- state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */ -- status = UpdateReg(state, EB12); -- if (status < 0) -- break; -- state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */ -- status = UpdateReg(state, EB18); -- if (status < 0) -- break; -- state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */ -- state->m_Regs[EP3] = state->m_EP3_Standby; -- status = UpdateReg(state, EP3); -- if (status < 0) -- break; -- state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */ -- status = UpdateRegs(state, EB21, EB23); -- if (status < 0) -- break; -- } while (0); -- return status; --} -- --static int CalcMainPLL(struct tda_state *state, u32 freq) --{ -- -- u8 PostDiv; -- u8 Div; -- u64 OscFreq; -- u32 MainDiv; -- -- if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) -- return -EINVAL; -- -- OscFreq = (u64) freq * (u64) Div; -- OscFreq *= (u64) 16384; -- do_div(OscFreq, (u64)16000000); -- MainDiv = OscFreq; -- -- state->m_Regs[MPD] = PostDiv & 0x77; -- state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F); -- state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF); -- state->m_Regs[MD3] = (MainDiv & 0xFF); -- -- return UpdateRegs(state, MPD, MD3); --} -- --static int CalcCalPLL(struct tda_state *state, u32 freq) --{ -- u8 PostDiv; -- u8 Div; -- u64 OscFreq; -- u32 CalDiv; -- -- if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div)) -- return -EINVAL; -- -- OscFreq = (u64)freq * (u64)Div; -- /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */ -- OscFreq *= (u64)16384; -- do_div(OscFreq, (u64)16000000); -- CalDiv = OscFreq; -- -- state->m_Regs[CPD] = PostDiv; -- state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF); -- state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF); -- state->m_Regs[CD3] = (CalDiv & 0xFF); -- -- return UpdateRegs(state, CPD, CD3); --} -- --static int CalibrateRF(struct tda_state *state, -- u8 RFBand, u32 freq, s32 *pCprog) --{ -- int status = 0; -- u8 Regs[NUM_REGS]; -- do { -- u8 BP_Filter = 0; -- u8 GainTaper = 0; -- u8 RFC_K = 0; -- u8 RFC_M = 0; -- -- state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */ -- status = UpdateReg(state, EP4); -- if (status < 0) -- break; -- state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */ -- status = UpdateReg(state, EB18); -- if (status < 0) -- break; -- -- /* Switching off LT (as datasheet says) causes calibration on C1 to fail */ -- /* (Readout of Cprog is allways 255) */ -- if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */ -- state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */ -- -- if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) && -- SearchMap1(m_GainTaper_Map, freq, &GainTaper) && -- SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M))) -- return -EINVAL; -- -- state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter; -- state->m_Regs[EP2] = (RFBand << 5) | GainTaper; -- -- state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2); -- -- status = UpdateRegs(state, EP1, EP3); -- if (status < 0) -- break; -- status = UpdateReg(state, EB13); -- if (status < 0) -- break; -- -- state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */ -- status = UpdateReg(state, EB4); -- if (status < 0) -- break; -- -- state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */ -- status = UpdateReg(state, EB7); -- if (status < 0) -- break; -- -- state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */ -- status = UpdateReg(state, EB14); -- if (status < 0) -- break; -- -- state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */ -- status = UpdateReg(state, EB20); -- if (status < 0) -- break; -- -- state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */ -- status = UpdateRegs(state, EP4, EP5); -- if (status < 0) -- break; -- -- status = CalcCalPLL(state, freq); -- if (status < 0) -- break; -- status = CalcMainPLL(state, freq + 1000000); -- if (status < 0) -- break; -- -- msleep(5); -- status = UpdateReg(state, EP2); -- if (status < 0) -- break; -- status = UpdateReg(state, EP1); -- if (status < 0) -- break; -- status = UpdateReg(state, EP2); -- if (status < 0) -- break; -- status = UpdateReg(state, EP1); -- if (status < 0) -- break; -- -- state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */ -- status = UpdateReg(state, EB4); -- if (status < 0) -- break; -- -- state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */ -- status = UpdateReg(state, EB7); -- if (status < 0) -- break; -- msleep(10); -- -- state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */ -- status = UpdateReg(state, EB20); -- if (status < 0) -- break; -- msleep(60); -- -- state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */ -- state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */ -- state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */ -- status = UpdateReg(state, EB18); -- if (status < 0) -- break; -- status = UpdateRegs(state, EP3, EP4); -- if (status < 0) -- break; -- status = UpdateReg(state, EP1); -- if (status < 0) -- break; -- -- status = ReadExtented(state, Regs); -- if (status < 0) -- break; -- -- *pCprog = Regs[EB14]; -- -- } while (0); -- return status; --} -- --static int RFTrackingFiltersInit(struct tda_state *state, -- u8 RFBand) --{ -- int status = 0; -- -- u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default; -- u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default; -- u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default; -- bool bcal = false; -- -- s32 Cprog_cal1 = 0; -- s32 Cprog_table1 = 0; -- s32 Cprog_cal2 = 0; -- s32 Cprog_table2 = 0; -- s32 Cprog_cal3 = 0; -- s32 Cprog_table3 = 0; -- -- state->m_RF_A1[RFBand] = 0; -- state->m_RF_B1[RFBand] = 0; -- state->m_RF_A2[RFBand] = 0; -- state->m_RF_B2[RFBand] = 0; -- -- do { -- status = PowerScan(state, RFBand, RF1, &RF1, &bcal); -- if (status < 0) -- break; -- if (bcal) { -- status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1); -- if (status < 0) -- break; -- } -- SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1); -- if (!bcal) -- Cprog_cal1 = Cprog_table1; -- state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1; -- /* state->m_RF_A1[RF_Band] = ???? */ -- -- if (RF2 == 0) -- break; -- -- status = PowerScan(state, RFBand, RF2, &RF2, &bcal); -- if (status < 0) -- break; -- if (bcal) { -- status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2); -- if (status < 0) -- break; -- } -- SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2); -- if (!bcal) -- Cprog_cal2 = Cprog_table2; -- -- state->m_RF_A1[RFBand] = -- (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) / -- ((s32)(RF2) - (s32)(RF1)); -- -- if (RF3 == 0) -- break; -- -- status = PowerScan(state, RFBand, RF3, &RF3, &bcal); -- if (status < 0) -- break; -- if (bcal) { -- status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3); -- if (status < 0) -- break; -- } -- SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3); -- if (!bcal) -- Cprog_cal3 = Cprog_table3; -- state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2)); -- state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2; -- -- } while (0); -- -- state->m_RF1[RFBand] = RF1; -- state->m_RF2[RFBand] = RF2; -- state->m_RF3[RFBand] = RF3; -- --#if 0 -- printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__, -- RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2, -- state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3); --#endif -- -- return status; --} -- --static int PowerScan(struct tda_state *state, -- u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal) --{ -- int status = 0; -- do { -- u8 Gain_Taper = 0; -- s32 RFC_Cprog = 0; -- u8 CID_Target = 0; -- u8 CountLimit = 0; -- u32 freq_MainPLL; -- u8 Regs[NUM_REGS]; -- u8 CID_Gain; -- s32 Count = 0; -- int sign = 1; -- bool wait = false; -- -- if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) && -- SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) && -- SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) { -- -- printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__); -- return -EINVAL; -- } -- -- state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper; -- state->m_Regs[EB14] = (RFC_Cprog); -- status = UpdateReg(state, EP2); -- if (status < 0) -- break; -- status = UpdateReg(state, EB14); -- if (status < 0) -- break; -- -- freq_MainPLL = RF_in + 1000000; -- status = CalcMainPLL(state, freq_MainPLL); -- if (status < 0) -- break; -- msleep(5); -- state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */ -- status = UpdateReg(state, EP4); -- if (status < 0) -- break; -- status = UpdateReg(state, EP2); /* Launch power measurement */ -- if (status < 0) -- break; -- status = ReadExtented(state, Regs); -- if (status < 0) -- break; -- CID_Gain = Regs[EB10] & 0x3F; -- state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */ -- -- *pRF_Out = RF_in; -- -- while (CID_Gain < CID_Target) { -- freq_MainPLL = RF_in + sign * Count + 1000000; -- status = CalcMainPLL(state, freq_MainPLL); -- if (status < 0) -- break; -- msleep(wait ? 5 : 1); -- wait = false; -- status = UpdateReg(state, EP2); /* Launch power measurement */ -- if (status < 0) -- break; -- status = ReadExtented(state, Regs); -- if (status < 0) -- break; -- CID_Gain = Regs[EB10] & 0x3F; -- Count += 200000; -- -- if (Count < CountLimit * 100000) -- continue; -- if (sign < 0) -- break; -- -- sign = -sign; -- Count = 200000; -- wait = true; -- } -- status = status; -- if (status < 0) -- break; -- if (CID_Gain >= CID_Target) { -- *pbcal = true; -- *pRF_Out = freq_MainPLL - 1000000; -- } else -- *pbcal = false; -- } while (0); -- -- return status; --} -- --static int PowerScanInit(struct tda_state *state) --{ -- int status = 0; -- do { -- state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12; -- state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */ -- status = UpdateRegs(state, EP3, EP4); -- if (status < 0) -- break; -- state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */ -- status = UpdateReg(state, EB18); -- if (status < 0) -- break; -- state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */ -- state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ -- status = UpdateRegs(state, EB21, EB23); -- if (status < 0) -- break; -- } while (0); -- return status; --} -- --static int CalcRFFilterCurve(struct tda_state *state) --{ -- int status = 0; -- do { -- msleep(200); /* Temperature stabilisation */ -- status = PowerScanInit(state); -- if (status < 0) -- break; -- status = RFTrackingFiltersInit(state, 0); -- if (status < 0) -- break; -- status = RFTrackingFiltersInit(state, 1); -- if (status < 0) -- break; -- status = RFTrackingFiltersInit(state, 2); -- if (status < 0) -- break; -- status = RFTrackingFiltersInit(state, 3); -- if (status < 0) -- break; -- status = RFTrackingFiltersInit(state, 4); -- if (status < 0) -- break; -- status = RFTrackingFiltersInit(state, 5); -- if (status < 0) -- break; -- status = RFTrackingFiltersInit(state, 6); -- if (status < 0) -- break; -- status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */ -- if (status < 0) -- break; -- } while (0); -- -- return status; --} -- --static int FixedContentsI2CUpdate(struct tda_state *state) --{ -- static u8 InitRegs[] = { -- 0x08, 0x80, 0xC6, -- 0xDF, 0x16, 0x60, 0x80, -- 0x80, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, -- 0xFC, 0x01, 0x84, 0x41, -- 0x01, 0x84, 0x40, 0x07, -- 0x00, 0x00, 0x96, 0x3F, -- 0xC1, 0x00, 0x8F, 0x00, -- 0x00, 0x8C, 0x00, 0x20, -- 0xB3, 0x48, 0xB0, -- }; -- int status = 0; -- memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1); -- do { -- status = UpdateRegs(state, TM, EB23); -- if (status < 0) -- break; -- -- /* AGC1 gain setup */ -- state->m_Regs[EB17] = 0x00; -- status = UpdateReg(state, EB17); -- if (status < 0) -- break; -- state->m_Regs[EB17] = 0x03; -- status = UpdateReg(state, EB17); -- if (status < 0) -- break; -- state->m_Regs[EB17] = 0x43; -- status = UpdateReg(state, EB17); -- if (status < 0) -- break; -- state->m_Regs[EB17] = 0x4C; -- status = UpdateReg(state, EB17); -- if (status < 0) -- break; -- -- /* IRC Cal Low band */ -- state->m_Regs[EP3] = 0x1F; -- state->m_Regs[EP4] = 0x66; -- state->m_Regs[EP5] = 0x81; -- state->m_Regs[CPD] = 0xCC; -- state->m_Regs[CD1] = 0x6C; -- state->m_Regs[CD2] = 0x00; -- state->m_Regs[CD3] = 0x00; -- state->m_Regs[MPD] = 0xC5; -- state->m_Regs[MD1] = 0x77; -- state->m_Regs[MD2] = 0x08; -- state->m_Regs[MD3] = 0x00; -- status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */ -- if (status < 0) -- break; -- --#if 0 -- state->m_Regs[EB4] = 0x61; /* missing in sw */ -- status = UpdateReg(state, EB4); -- if (status < 0) -- break; -- msleep(1); -- state->m_Regs[EB4] = 0x41; -- status = UpdateReg(state, EB4); -- if (status < 0) -- break; --#endif -- -- msleep(5); -- status = UpdateReg(state, EP1); -- if (status < 0) -- break; -- msleep(5); -- -- state->m_Regs[EP5] = 0x85; -- state->m_Regs[CPD] = 0xCB; -- state->m_Regs[CD1] = 0x66; -- state->m_Regs[CD2] = 0x70; -- status = UpdateRegs(state, EP3, CD3); -- if (status < 0) -- break; -- msleep(5); -- status = UpdateReg(state, EP2); -- if (status < 0) -- break; -- msleep(30); -- -- /* IRC Cal mid band */ -- state->m_Regs[EP5] = 0x82; -- state->m_Regs[CPD] = 0xA8; -- state->m_Regs[CD2] = 0x00; -- state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */ -- state->m_Regs[MD1] = 0x73; -- state->m_Regs[MD2] = 0x1A; -- status = UpdateRegs(state, EP3, MD3); -- if (status < 0) -- break; -- -- msleep(5); -- status = UpdateReg(state, EP1); -- if (status < 0) -- break; -- msleep(5); -- -- state->m_Regs[EP5] = 0x86; -- state->m_Regs[CPD] = 0xA8; -- state->m_Regs[CD1] = 0x66; -- state->m_Regs[CD2] = 0xA0; -- status = UpdateRegs(state, EP3, CD3); -- if (status < 0) -- break; -- msleep(5); -- status = UpdateReg(state, EP2); -- if (status < 0) -- break; -- msleep(30); -- -- /* IRC Cal high band */ -- state->m_Regs[EP5] = 0x83; -- state->m_Regs[CPD] = 0x98; -- state->m_Regs[CD1] = 0x65; -- state->m_Regs[CD2] = 0x00; -- state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */ -- state->m_Regs[MD1] = 0x71; -- state->m_Regs[MD2] = 0xCD; -- status = UpdateRegs(state, EP3, MD3); -- if (status < 0) -- break; -- msleep(5); -- status = UpdateReg(state, EP1); -- if (status < 0) -- break; -- msleep(5); -- state->m_Regs[EP5] = 0x87; -- state->m_Regs[CD1] = 0x65; -- state->m_Regs[CD2] = 0x50; -- status = UpdateRegs(state, EP3, CD3); -- if (status < 0) -- break; -- msleep(5); -- status = UpdateReg(state, EP2); -- if (status < 0) -- break; -- msleep(30); -- -- /* Back to normal */ -- state->m_Regs[EP4] = 0x64; -- status = UpdateReg(state, EP4); -- if (status < 0) -- break; -- status = UpdateReg(state, EP1); -- if (status < 0) -- break; -- -- } while (0); -- return status; --} -- --static int InitCal(struct tda_state *state) --{ -- int status = 0; -- -- do { -- status = FixedContentsI2CUpdate(state); -- if (status < 0) -- break; -- status = CalcRFFilterCurve(state); -- if (status < 0) -- break; -- status = StandBy(state); -- if (status < 0) -- break; -- /* m_bInitDone = true; */ -- } while (0); -- return status; --}; -- --static int RFTrackingFiltersCorrection(struct tda_state *state, -- u32 Frequency) --{ -- int status = 0; -- s32 Cprog_table; -- u8 RFBand; -- u8 dCoverdT; -- -- if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) || -- !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) || -- !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT)) -- -- return -EINVAL; -- -- do { -- u8 TMValue_Current; -- u32 RF1 = state->m_RF1[RFBand]; -- u32 RF2 = state->m_RF1[RFBand]; -- u32 RF3 = state->m_RF1[RFBand]; -- s32 RF_A1 = state->m_RF_A1[RFBand]; -- s32 RF_B1 = state->m_RF_B1[RFBand]; -- s32 RF_A2 = state->m_RF_A2[RFBand]; -- s32 RF_B2 = state->m_RF_B2[RFBand]; -- s32 Capprox = 0; -- int TComp; -- -- state->m_Regs[EP3] &= ~0xE0; /* Power up */ -- status = UpdateReg(state, EP3); -- if (status < 0) -- break; -- -- status = ThermometerRead(state, &TMValue_Current); -- if (status < 0) -- break; -- -- if (RF3 == 0 || Frequency < RF2) -- Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table; -- else -- Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table; -- -- TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000; -- -- Capprox += TComp; -- -- if (Capprox < 0) -- Capprox = 0; -- else if (Capprox > 255) -- Capprox = 255; -- -- -- /* TODO Temperature compensation. There is defenitely a scale factor */ -- /* missing in the datasheet, so leave it out for now. */ -- state->m_Regs[EB14] = Capprox; -- -- status = UpdateReg(state, EB14); -- if (status < 0) -- break; -- -- } while (0); -- return status; --} -- --static int ChannelConfiguration(struct tda_state *state, -- u32 Frequency, int Standard) --{ -- -- s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency; -- int status = 0; -- -- u8 BP_Filter = 0; -- u8 RF_Band = 0; -- u8 GainTaper = 0; -- u8 IR_Meas = 0; -- -- state->IF = IntermediateFrequency; -- /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ -- /* get values from tables */ -- -- if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) && -- SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) && -- SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) && -- SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) { -- -- printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__); -- return -EINVAL; -- } -- -- do { -- state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0; -- state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */ -- -- /* m_EP4 default for XToutOn, CAL_Mode (0) */ -- state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog); -- /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */ -- if (Standard <= HF_AnalogMax) -- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog; -- else if (Standard <= HF_ATSC) -- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT; -- else if (Standard <= HF_DVBC) -- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC; -- else -- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; -- -- if ((Standard == HF_FM_Radio) && state->m_bFMInput) -- state->m_Regs[EP4] |= 80; -- -- state->m_Regs[MPD] &= ~0x80; -- if (Standard > HF_AnalogMax) -- state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */ -- -- state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22; -- -- /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */ -- if (Standard == HF_FM_Radio) -- state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ -- else -- state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */ -- -- status = UpdateRegs(state, EB22, EB23); -- if (status < 0) -- break; -- -- state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */ -- state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas; -- state->m_Regs[EP2] = (RF_Band << 5) | GainTaper; -- -- state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) | -- (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */ -- /* AGC1_always_master = 0 */ -- /* AGC_firstn = 0 */ -- status = UpdateReg(state, EB1); -- if (status < 0) -- break; -- -- if (state->m_bMaster) { -- status = CalcMainPLL(state, Frequency + IntermediateFrequency); -- if (status < 0) -- break; -- status = UpdateRegs(state, TM, EP5); -- if (status < 0) -- break; -- state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */ -- status = UpdateReg(state, EB4); -- if (status < 0) -- break; -- msleep(1); -- state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ -- status = UpdateReg(state, EB4); -- if (status < 0) -- break; -- } else { -- u8 PostDiv = 0; -- u8 Div; -- status = CalcCalPLL(state, Frequency + IntermediateFrequency); -- if (status < 0) -- break; -- -- SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div); -- state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77); -- status = UpdateReg(state, MPD); -- if (status < 0) -- break; -- status = UpdateRegs(state, TM, EP5); -- if (status < 0) -- break; -- -- state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */ -- status = UpdateReg(state, EB7); -- if (status < 0) -- break; -- msleep(1); -- state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */ -- status = UpdateReg(state, EB7); -- if (status < 0) -- break; -- } -- msleep(20); -- if (Standard != HF_FM_Radio) -- state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */ -- status = UpdateReg(state, EP3); -- if (status < 0) -- break; -- -- } while (0); -- return status; --} -- --static int sleep(struct dvb_frontend *fe) --{ -- struct tda_state *state = fe->tuner_priv; -- -- StandBy(state); -- return 0; --} -- --static int init(struct dvb_frontend *fe) --{ -- return 0; --} -- --static int release(struct dvb_frontend *fe) --{ -- kfree(fe->tuner_priv); -- fe->tuner_priv = NULL; -- return 0; --} -- --/* -- * As defined on EN 300 429 Annex A and on ITU-T J.83 annex A, the DVB-C -- * roll-off factor is 0.15. -- * According with the specs, the amount of the needed bandwith is given by: -- * Bw = Symbol_rate * (1 + 0.15) -- * As such, the maximum symbol rate supported by 6 MHz is -- * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds -- *NOTE: For ITU-T J.83 Annex C, the roll-off factor is 0.13. So: -- * max_symbol_rate = 6 MHz / 1.13 = 5309735 Baud -- * That means that an adjustment is needed for Japan, -- * but, as currently DRX-K is hardcoded to Annex A, let's stick -- * with 0.15 roll-off factor. -- */ --#define MAX_SYMBOL_RATE_6MHz 5217391 -- --#ifndef USE_API3 --static int set_params(struct dvb_frontend *fe) --#else --static int set_params(struct dvb_frontend *fe, -- struct dvb_frontend_parameters *params) --#endif --{ -- struct tda_state *state = fe->tuner_priv; -- int status = 0; -- int Standard; --#ifndef USE_API3 -- u32 bw = fe->dtv_property_cache.bandwidth_hz; -- u32 delsys = fe->dtv_property_cache.delivery_system; -- -- state->m_Frequency = fe->dtv_property_cache.frequency; -- -- switch (delsys) { -- case SYS_DVBT: -- case SYS_DVBT2: -- switch (bw) { -- case 6000000: -- Standard = HF_DVBT_6MHZ; -- break; -- case 7000000: -- Standard = HF_DVBT_7MHZ; -- break; -- case 8000000: -- Standard = HF_DVBT_8MHZ; -- break; -- default: -- return -EINVAL; -- } -- case SYS_DVBC_ANNEX_A: -- case SYS_DVBC_ANNEX_C: -- if (bw <= 6000000) -- Standard = HF_DVBC_6MHZ; -- else if (bw <= 7000000) -- Standard = HF_DVBC_7MHZ; -- else -- Standard = HF_DVBC_8MHZ; -- break; -- default: -- return -EINVAL; -- } -- do { -- status = RFTrackingFiltersCorrection(state, state->m_Frequency); -- if (status < 0) -- break; -- status = ChannelConfiguration(state, state->m_Frequency, -- Standard); -- if (status < 0) -- break; -- -- msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ -- } while (0); --#else -- state->m_Frequency = params->frequency; -- -- if (fe->ops.info.type == FE_OFDM) -- switch (params->u.ofdm.bandwidth) { -- case BANDWIDTH_6_MHZ: -- Standard = HF_DVBT_6MHZ; -- break; -- case BANDWIDTH_7_MHZ: -- Standard = HF_DVBT_7MHZ; -- break; -- default: -- case BANDWIDTH_8_MHZ: -- Standard = HF_DVBT_8MHZ; -- break; -- } -- else if (fe->ops.info.type == FE_QAM) { -- if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) -- Standard = HF_DVBC_6MHZ; -- else -- Standard = HF_DVBC_8MHZ; -- } else -- return -EINVAL; -- do { -- status = RFTrackingFiltersCorrection(state, params->frequency); -- if (status < 0) -- break; -- status = ChannelConfiguration(state, params->frequency, Standard); -- if (status < 0) -- break; -- -- msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ -- } while (0); --#endif -- return status; --} -- --#if 0 --static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc) --{ -- if (IFAgc < 500) { -- /* Scale this from 0 to 50000 */ -- *pSignalStrength = IFAgc * 100; -- } else { -- /* Scale range 500-1500 to 50000-80000 */ -- *pSignalStrength = 50000 + (IFAgc - 500) * 30; -- } -- -- return 0; --} --#endif -- --static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency) --{ -- struct tda_state *state = fe->tuner_priv; -- -- *frequency = state->IF; -- return 0; --} -- --static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) --{ -- /* struct tda_state *state = fe->tuner_priv; */ -- /* *bandwidth = priv->bandwidth; */ -- return 0; --} -- -- --static struct dvb_tuner_ops tuner_ops = { -- .info = { -- .name = "NXP TDA18271C2D", -- .frequency_min = 47125000, -- .frequency_max = 865000000, -- .frequency_step = 62500 -- }, -- .init = init, -- .sleep = sleep, -- .set_params = set_params, -- .release = release, -- .get_if_frequency = get_if_frequency, -- .get_bandwidth = get_bandwidth, --}; -- --struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, -- struct i2c_adapter *i2c, u8 adr) --{ -- struct tda_state *state; -- -- state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); -- if (!state) -- return NULL; -- -- fe->tuner_priv = state; -- state->adr = adr; -- state->i2c = i2c; -- memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); -- reset(state); -- InitCal(state); -- -- return fe; --} --EXPORT_SYMBOL_GPL(tda18271c2dd_attach); -- --MODULE_DESCRIPTION("TDA18271C2 driver"); --MODULE_AUTHOR("DD"); --MODULE_LICENSE("GPL"); -+/* -+ * tda18271c2dd: Driver for the TDA18271C2 tuner -+ * -+ * Copyright (C) 2010 Digital Devices GmbH -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dvb_frontend.h" -+ -+struct SStandardParam { -+ s32 m_IFFrequency; -+ u32 m_BandWidth; -+ u8 m_EP3_4_0; -+ u8 m_EB22; -+}; -+ -+struct SMap { -+ u32 m_Frequency; -+ u8 m_Param; -+}; -+ -+struct SMapI { -+ u32 m_Frequency; -+ s32 m_Param; -+}; -+ -+struct SMap2 { -+ u32 m_Frequency; -+ u8 m_Param1; -+ u8 m_Param2; -+}; -+ -+struct SRFBandMap { -+ u32 m_RF_max; -+ u32 m_RF1_Default; -+ u32 m_RF2_Default; -+ u32 m_RF3_Default; -+}; -+ -+enum ERegister { -+ ID = 0, -+ TM, -+ PL, -+ EP1, EP2, EP3, EP4, EP5, -+ CPD, CD1, CD2, CD3, -+ MPD, MD1, MD2, MD3, -+ EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10, -+ EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20, -+ EB21, EB22, EB23, -+ NUM_REGS -+}; -+ -+struct tda_state { -+ struct i2c_adapter *i2c; -+ u8 adr; -+ -+ u32 m_Frequency; -+ u32 IF; -+ -+ u8 m_IFLevelAnalog; -+ u8 m_IFLevelDigital; -+ u8 m_IFLevelDVBC; -+ u8 m_IFLevelDVBT; -+ -+ u8 m_EP4; -+ u8 m_EP3_Standby; -+ -+ bool m_bMaster; -+ -+ s32 m_SettlingTime; -+ -+ u8 m_Regs[NUM_REGS]; -+ -+ /* Tracking filter settings for band 0..6 */ -+ u32 m_RF1[7]; -+ s32 m_RF_A1[7]; -+ s32 m_RF_B1[7]; -+ u32 m_RF2[7]; -+ s32 m_RF_A2[7]; -+ s32 m_RF_B2[7]; -+ u32 m_RF3[7]; -+ -+ u8 m_TMValue_RFCal; /* Calibration temperatur */ -+ -+ bool m_bFMInput; /* true to use Pin 8 for FM Radio */ -+ -+}; -+ -+static int PowerScan(struct tda_state *state, -+ u8 RFBand, u32 RF_in, -+ u32 *pRF_Out, bool *pbcal); -+ -+static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, -+ .buf = data, .len = len} }; -+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -+} -+ -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msg = {.addr = adr, .flags = 0, -+ .buf = data, .len = len}; -+ -+ if (i2c_transfer(adap, &msg, 1) != 1) { -+ printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr); -+ return -1; -+ } -+ return 0; -+} -+ -+static int WriteRegs(struct tda_state *state, -+ u8 SubAddr, u8 *Regs, u16 nRegs) -+{ -+ u8 data[nRegs+1]; -+ -+ data[0] = SubAddr; -+ memcpy(data + 1, Regs, nRegs); -+ return i2c_write(state->i2c, state->adr, data, nRegs+1); -+} -+ -+static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) -+{ -+ u8 msg[2] = {SubAddr, Reg}; -+ -+ return i2c_write(state->i2c, state->adr, msg, 2); -+} -+ -+static int Read(struct tda_state *state, u8 * Regs) -+{ -+ return i2c_readn(state->i2c, state->adr, Regs, 16); -+} -+ -+static int ReadExtented(struct tda_state *state, u8 * Regs) -+{ -+ return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS); -+} -+ -+static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo) -+{ -+ return WriteRegs(state, RegFrom, -+ &state->m_Regs[RegFrom], RegTo-RegFrom+1); -+} -+static int UpdateReg(struct tda_state *state, u8 Reg) -+{ -+ return WriteReg(state, Reg, state->m_Regs[Reg]); -+} -+ -+#include "tda18271c2dd_maps.h" -+ -+static void reset(struct tda_state *state) -+{ -+ u32 ulIFLevelAnalog = 0; -+ u32 ulIFLevelDigital = 2; -+ u32 ulIFLevelDVBC = 7; -+ u32 ulIFLevelDVBT = 6; -+ u32 ulXTOut = 0; -+ u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */ -+ u32 ulSlave = 0; -+ u32 ulFMInput = 0; -+ u32 ulSettlingTime = 100; -+ -+ state->m_Frequency = 0; -+ state->m_SettlingTime = 100; -+ state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2; -+ state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2; -+ state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2; -+ state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2; -+ -+ state->m_EP4 = 0x20; -+ if (ulXTOut != 0) -+ state->m_EP4 |= 0x40; -+ -+ state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F; -+ state->m_bMaster = (ulSlave == 0); -+ -+ state->m_SettlingTime = ulSettlingTime; -+ -+ state->m_bFMInput = (ulFMInput == 2); -+} -+ -+static bool SearchMap1(struct SMap Map[], -+ u32 Frequency, u8 *pParam) -+{ -+ int i = 0; -+ -+ while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency)) -+ i += 1; -+ if (Map[i].m_Frequency == 0) -+ return false; -+ *pParam = Map[i].m_Param; -+ return true; -+} -+ -+static bool SearchMap2(struct SMapI Map[], -+ u32 Frequency, s32 *pParam) -+{ -+ int i = 0; -+ -+ while ((Map[i].m_Frequency != 0) && -+ (Frequency > Map[i].m_Frequency)) -+ i += 1; -+ if (Map[i].m_Frequency == 0) -+ return false; -+ *pParam = Map[i].m_Param; -+ return true; -+} -+ -+static bool SearchMap3(struct SMap2 Map[], u32 Frequency, -+ u8 *pParam1, u8 *pParam2) -+{ -+ int i = 0; -+ -+ while ((Map[i].m_Frequency != 0) && -+ (Frequency > Map[i].m_Frequency)) -+ i += 1; -+ if (Map[i].m_Frequency == 0) -+ return false; -+ *pParam1 = Map[i].m_Param1; -+ *pParam2 = Map[i].m_Param2; -+ return true; -+} -+ -+static bool SearchMap4(struct SRFBandMap Map[], -+ u32 Frequency, u8 *pRFBand) -+{ -+ int i = 0; -+ -+ while (i < 7 && (Frequency > Map[i].m_RF_max)) -+ i += 1; -+ if (i == 7) -+ return false; -+ *pRFBand = i; -+ return true; -+} -+ -+static int ThermometerRead(struct tda_state *state, u8 *pTM_Value) -+{ -+ int status = 0; -+ -+ do { -+ u8 Regs[16]; -+ state->m_Regs[TM] |= 0x10; -+ status = UpdateReg(state, TM); -+ if (status < 0) -+ break; -+ status = Read(state, Regs); -+ if (status < 0) -+ break; -+ if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) || -+ ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) { -+ state->m_Regs[TM] ^= 0x20; -+ status = UpdateReg(state, TM); -+ if (status < 0) -+ break; -+ msleep(10); -+ status = Read(state, Regs); -+ if (status < 0) -+ break; -+ } -+ *pTM_Value = (Regs[TM] & 0x20) -+ ? m_Thermometer_Map_2[Regs[TM] & 0x0F] -+ : m_Thermometer_Map_1[Regs[TM] & 0x0F] ; -+ state->m_Regs[TM] &= ~0x10; /* Thermometer off */ -+ status = UpdateReg(state, TM); -+ if (status < 0) -+ break; -+ state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */ -+ status = UpdateReg(state, EP4); -+ if (status < 0) -+ break; -+ } while (0); -+ -+ return status; -+} -+ -+static int StandBy(struct tda_state *state) -+{ -+ int status = 0; -+ do { -+ state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */ -+ status = UpdateReg(state, EB12); -+ if (status < 0) -+ break; -+ state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */ -+ status = UpdateReg(state, EB18); -+ if (status < 0) -+ break; -+ state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */ -+ state->m_Regs[EP3] = state->m_EP3_Standby; -+ status = UpdateReg(state, EP3); -+ if (status < 0) -+ break; -+ state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */ -+ status = UpdateRegs(state, EB21, EB23); -+ if (status < 0) -+ break; -+ } while (0); -+ return status; -+} -+ -+static int CalcMainPLL(struct tda_state *state, u32 freq) -+{ -+ -+ u8 PostDiv; -+ u8 Div; -+ u64 OscFreq; -+ u32 MainDiv; -+ -+ if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) -+ return -EINVAL; -+ -+ OscFreq = (u64) freq * (u64) Div; -+ OscFreq *= (u64) 16384; -+ do_div(OscFreq, (u64)16000000); -+ MainDiv = OscFreq; -+ -+ state->m_Regs[MPD] = PostDiv & 0x77; -+ state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F); -+ state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF); -+ state->m_Regs[MD3] = (MainDiv & 0xFF); -+ -+ return UpdateRegs(state, MPD, MD3); -+} -+ -+static int CalcCalPLL(struct tda_state *state, u32 freq) -+{ -+ u8 PostDiv; -+ u8 Div; -+ u64 OscFreq; -+ u32 CalDiv; -+ -+ if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div)) -+ return -EINVAL; -+ -+ OscFreq = (u64)freq * (u64)Div; -+ /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */ -+ OscFreq *= (u64)16384; -+ do_div(OscFreq, (u64)16000000); -+ CalDiv = OscFreq; -+ -+ state->m_Regs[CPD] = PostDiv; -+ state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF); -+ state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF); -+ state->m_Regs[CD3] = (CalDiv & 0xFF); -+ -+ return UpdateRegs(state, CPD, CD3); -+} -+ -+static int CalibrateRF(struct tda_state *state, -+ u8 RFBand, u32 freq, s32 *pCprog) -+{ -+ int status = 0; -+ u8 Regs[NUM_REGS]; -+ do { -+ u8 BP_Filter = 0; -+ u8 GainTaper = 0; -+ u8 RFC_K = 0; -+ u8 RFC_M = 0; -+ -+ state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */ -+ status = UpdateReg(state, EP4); -+ if (status < 0) -+ break; -+ state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */ -+ status = UpdateReg(state, EB18); -+ if (status < 0) -+ break; -+ -+ /* Switching off LT (as datasheet says) causes calibration on C1 to fail */ -+ /* (Readout of Cprog is allways 255) */ -+ if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */ -+ state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */ -+ -+ if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) && -+ SearchMap1(m_GainTaper_Map, freq, &GainTaper) && -+ SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M))) -+ return -EINVAL; -+ -+ state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter; -+ state->m_Regs[EP2] = (RFBand << 5) | GainTaper; -+ -+ state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2); -+ -+ status = UpdateRegs(state, EP1, EP3); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EB13); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */ -+ status = UpdateReg(state, EB4); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */ -+ status = UpdateReg(state, EB7); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */ -+ status = UpdateReg(state, EB14); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */ -+ status = UpdateReg(state, EB20); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */ -+ status = UpdateRegs(state, EP4, EP5); -+ if (status < 0) -+ break; -+ -+ status = CalcCalPLL(state, freq); -+ if (status < 0) -+ break; -+ status = CalcMainPLL(state, freq + 1000000); -+ if (status < 0) -+ break; -+ -+ msleep(5); -+ status = UpdateReg(state, EP2); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EP1); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EP2); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EP1); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */ -+ status = UpdateReg(state, EB4); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */ -+ status = UpdateReg(state, EB7); -+ if (status < 0) -+ break; -+ msleep(10); -+ -+ state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */ -+ status = UpdateReg(state, EB20); -+ if (status < 0) -+ break; -+ msleep(60); -+ -+ state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */ -+ state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */ -+ state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */ -+ status = UpdateReg(state, EB18); -+ if (status < 0) -+ break; -+ status = UpdateRegs(state, EP3, EP4); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EP1); -+ if (status < 0) -+ break; -+ -+ status = ReadExtented(state, Regs); -+ if (status < 0) -+ break; -+ -+ *pCprog = Regs[EB14]; -+ -+ } while (0); -+ return status; -+} -+ -+static int RFTrackingFiltersInit(struct tda_state *state, -+ u8 RFBand) -+{ -+ int status = 0; -+ -+ u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default; -+ u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default; -+ u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default; -+ bool bcal = false; -+ -+ s32 Cprog_cal1 = 0; -+ s32 Cprog_table1 = 0; -+ s32 Cprog_cal2 = 0; -+ s32 Cprog_table2 = 0; -+ s32 Cprog_cal3 = 0; -+ s32 Cprog_table3 = 0; -+ -+ state->m_RF_A1[RFBand] = 0; -+ state->m_RF_B1[RFBand] = 0; -+ state->m_RF_A2[RFBand] = 0; -+ state->m_RF_B2[RFBand] = 0; -+ -+ do { -+ status = PowerScan(state, RFBand, RF1, &RF1, &bcal); -+ if (status < 0) -+ break; -+ if (bcal) { -+ status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1); -+ if (status < 0) -+ break; -+ } -+ SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1); -+ if (!bcal) -+ Cprog_cal1 = Cprog_table1; -+ state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1; -+ /* state->m_RF_A1[RF_Band] = ???? */ -+ -+ if (RF2 == 0) -+ break; -+ -+ status = PowerScan(state, RFBand, RF2, &RF2, &bcal); -+ if (status < 0) -+ break; -+ if (bcal) { -+ status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2); -+ if (status < 0) -+ break; -+ } -+ SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2); -+ if (!bcal) -+ Cprog_cal2 = Cprog_table2; -+ -+ state->m_RF_A1[RFBand] = -+ (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) / -+ ((s32)(RF2) - (s32)(RF1)); -+ -+ if (RF3 == 0) -+ break; -+ -+ status = PowerScan(state, RFBand, RF3, &RF3, &bcal); -+ if (status < 0) -+ break; -+ if (bcal) { -+ status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3); -+ if (status < 0) -+ break; -+ } -+ SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3); -+ if (!bcal) -+ Cprog_cal3 = Cprog_table3; -+ state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2)); -+ state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2; -+ -+ } while (0); -+ -+ state->m_RF1[RFBand] = RF1; -+ state->m_RF2[RFBand] = RF2; -+ state->m_RF3[RFBand] = RF3; -+ -+#if 0 -+ printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__, -+ RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2, -+ state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3); -+#endif -+ -+ return status; -+} -+ -+static int PowerScan(struct tda_state *state, -+ u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal) -+{ -+ int status = 0; -+ do { -+ u8 Gain_Taper = 0; -+ s32 RFC_Cprog = 0; -+ u8 CID_Target = 0; -+ u8 CountLimit = 0; -+ u32 freq_MainPLL; -+ u8 Regs[NUM_REGS]; -+ u8 CID_Gain; -+ s32 Count = 0; -+ int sign = 1; -+ bool wait = false; -+ -+ if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) && -+ SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) && -+ SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) { -+ -+ printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__); -+ return -EINVAL; -+ } -+ -+ state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper; -+ state->m_Regs[EB14] = (RFC_Cprog); -+ status = UpdateReg(state, EP2); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EB14); -+ if (status < 0) -+ break; -+ -+ freq_MainPLL = RF_in + 1000000; -+ status = CalcMainPLL(state, freq_MainPLL); -+ if (status < 0) -+ break; -+ msleep(5); -+ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */ -+ status = UpdateReg(state, EP4); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EP2); /* Launch power measurement */ -+ if (status < 0) -+ break; -+ status = ReadExtented(state, Regs); -+ if (status < 0) -+ break; -+ CID_Gain = Regs[EB10] & 0x3F; -+ state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */ -+ -+ *pRF_Out = RF_in; -+ -+ while (CID_Gain < CID_Target) { -+ freq_MainPLL = RF_in + sign * Count + 1000000; -+ status = CalcMainPLL(state, freq_MainPLL); -+ if (status < 0) -+ break; -+ msleep(wait ? 5 : 1); -+ wait = false; -+ status = UpdateReg(state, EP2); /* Launch power measurement */ -+ if (status < 0) -+ break; -+ status = ReadExtented(state, Regs); -+ if (status < 0) -+ break; -+ CID_Gain = Regs[EB10] & 0x3F; -+ Count += 200000; -+ -+ if (Count < CountLimit * 100000) -+ continue; -+ if (sign < 0) -+ break; -+ -+ sign = -sign; -+ Count = 200000; -+ wait = true; -+ } -+ status = status; -+ if (status < 0) -+ break; -+ if (CID_Gain >= CID_Target) { -+ *pbcal = true; -+ *pRF_Out = freq_MainPLL - 1000000; -+ } else -+ *pbcal = false; -+ } while (0); -+ -+ return status; -+} -+ -+static int PowerScanInit(struct tda_state *state) -+{ -+ int status = 0; -+ do { -+ state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12; -+ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */ -+ status = UpdateRegs(state, EP3, EP4); -+ if (status < 0) -+ break; -+ state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */ -+ status = UpdateReg(state, EB18); -+ if (status < 0) -+ break; -+ state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */ -+ state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ -+ status = UpdateRegs(state, EB21, EB23); -+ if (status < 0) -+ break; -+ } while (0); -+ return status; -+} -+ -+static int CalcRFFilterCurve(struct tda_state *state) -+{ -+ int status = 0; -+ do { -+ msleep(200); /* Temperature stabilisation */ -+ status = PowerScanInit(state); -+ if (status < 0) -+ break; -+ status = RFTrackingFiltersInit(state, 0); -+ if (status < 0) -+ break; -+ status = RFTrackingFiltersInit(state, 1); -+ if (status < 0) -+ break; -+ status = RFTrackingFiltersInit(state, 2); -+ if (status < 0) -+ break; -+ status = RFTrackingFiltersInit(state, 3); -+ if (status < 0) -+ break; -+ status = RFTrackingFiltersInit(state, 4); -+ if (status < 0) -+ break; -+ status = RFTrackingFiltersInit(state, 5); -+ if (status < 0) -+ break; -+ status = RFTrackingFiltersInit(state, 6); -+ if (status < 0) -+ break; -+ status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */ -+ if (status < 0) -+ break; -+ } while (0); -+ -+ return status; -+} -+ -+static int FixedContentsI2CUpdate(struct tda_state *state) -+{ -+ static u8 InitRegs[] = { -+ 0x08, 0x80, 0xC6, -+ 0xDF, 0x16, 0x60, 0x80, -+ 0x80, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, -+ 0xFC, 0x01, 0x84, 0x41, -+ 0x01, 0x84, 0x40, 0x07, -+ 0x00, 0x00, 0x96, 0x3F, -+ 0xC1, 0x00, 0x8F, 0x00, -+ 0x00, 0x8C, 0x00, 0x20, -+ 0xB3, 0x48, 0xB0, -+ }; -+ int status = 0; -+ memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1); -+ do { -+ status = UpdateRegs(state, TM, EB23); -+ if (status < 0) -+ break; -+ -+ /* AGC1 gain setup */ -+ state->m_Regs[EB17] = 0x00; -+ status = UpdateReg(state, EB17); -+ if (status < 0) -+ break; -+ state->m_Regs[EB17] = 0x03; -+ status = UpdateReg(state, EB17); -+ if (status < 0) -+ break; -+ state->m_Regs[EB17] = 0x43; -+ status = UpdateReg(state, EB17); -+ if (status < 0) -+ break; -+ state->m_Regs[EB17] = 0x4C; -+ status = UpdateReg(state, EB17); -+ if (status < 0) -+ break; -+ -+ /* IRC Cal Low band */ -+ state->m_Regs[EP3] = 0x1F; -+ state->m_Regs[EP4] = 0x66; -+ state->m_Regs[EP5] = 0x81; -+ state->m_Regs[CPD] = 0xCC; -+ state->m_Regs[CD1] = 0x6C; -+ state->m_Regs[CD2] = 0x00; -+ state->m_Regs[CD3] = 0x00; -+ state->m_Regs[MPD] = 0xC5; -+ state->m_Regs[MD1] = 0x77; -+ state->m_Regs[MD2] = 0x08; -+ state->m_Regs[MD3] = 0x00; -+ status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */ -+ if (status < 0) -+ break; -+ -+#if 0 -+ state->m_Regs[EB4] = 0x61; /* missing in sw */ -+ status = UpdateReg(state, EB4); -+ if (status < 0) -+ break; -+ msleep(1); -+ state->m_Regs[EB4] = 0x41; -+ status = UpdateReg(state, EB4); -+ if (status < 0) -+ break; -+#endif -+ -+ msleep(5); -+ status = UpdateReg(state, EP1); -+ if (status < 0) -+ break; -+ msleep(5); -+ -+ state->m_Regs[EP5] = 0x85; -+ state->m_Regs[CPD] = 0xCB; -+ state->m_Regs[CD1] = 0x66; -+ state->m_Regs[CD2] = 0x70; -+ status = UpdateRegs(state, EP3, CD3); -+ if (status < 0) -+ break; -+ msleep(5); -+ status = UpdateReg(state, EP2); -+ if (status < 0) -+ break; -+ msleep(30); -+ -+ /* IRC Cal mid band */ -+ state->m_Regs[EP5] = 0x82; -+ state->m_Regs[CPD] = 0xA8; -+ state->m_Regs[CD2] = 0x00; -+ state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */ -+ state->m_Regs[MD1] = 0x73; -+ state->m_Regs[MD2] = 0x1A; -+ status = UpdateRegs(state, EP3, MD3); -+ if (status < 0) -+ break; -+ -+ msleep(5); -+ status = UpdateReg(state, EP1); -+ if (status < 0) -+ break; -+ msleep(5); -+ -+ state->m_Regs[EP5] = 0x86; -+ state->m_Regs[CPD] = 0xA8; -+ state->m_Regs[CD1] = 0x66; -+ state->m_Regs[CD2] = 0xA0; -+ status = UpdateRegs(state, EP3, CD3); -+ if (status < 0) -+ break; -+ msleep(5); -+ status = UpdateReg(state, EP2); -+ if (status < 0) -+ break; -+ msleep(30); -+ -+ /* IRC Cal high band */ -+ state->m_Regs[EP5] = 0x83; -+ state->m_Regs[CPD] = 0x98; -+ state->m_Regs[CD1] = 0x65; -+ state->m_Regs[CD2] = 0x00; -+ state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */ -+ state->m_Regs[MD1] = 0x71; -+ state->m_Regs[MD2] = 0xCD; -+ status = UpdateRegs(state, EP3, MD3); -+ if (status < 0) -+ break; -+ msleep(5); -+ status = UpdateReg(state, EP1); -+ if (status < 0) -+ break; -+ msleep(5); -+ state->m_Regs[EP5] = 0x87; -+ state->m_Regs[CD1] = 0x65; -+ state->m_Regs[CD2] = 0x50; -+ status = UpdateRegs(state, EP3, CD3); -+ if (status < 0) -+ break; -+ msleep(5); -+ status = UpdateReg(state, EP2); -+ if (status < 0) -+ break; -+ msleep(30); -+ -+ /* Back to normal */ -+ state->m_Regs[EP4] = 0x64; -+ status = UpdateReg(state, EP4); -+ if (status < 0) -+ break; -+ status = UpdateReg(state, EP1); -+ if (status < 0) -+ break; -+ -+ } while (0); -+ return status; -+} -+ -+static int InitCal(struct tda_state *state) -+{ -+ int status = 0; -+ -+ do { -+ status = FixedContentsI2CUpdate(state); -+ if (status < 0) -+ break; -+ status = CalcRFFilterCurve(state); -+ if (status < 0) -+ break; -+ status = StandBy(state); -+ if (status < 0) -+ break; -+ /* m_bInitDone = true; */ -+ } while (0); -+ return status; -+}; -+ -+static int RFTrackingFiltersCorrection(struct tda_state *state, -+ u32 Frequency) -+{ -+ int status = 0; -+ s32 Cprog_table; -+ u8 RFBand; -+ u8 dCoverdT; -+ -+ if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) || -+ !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) || -+ !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT)) -+ -+ return -EINVAL; -+ -+ do { -+ u8 TMValue_Current; -+ u32 RF1 = state->m_RF1[RFBand]; -+ u32 RF2 = state->m_RF1[RFBand]; -+ u32 RF3 = state->m_RF1[RFBand]; -+ s32 RF_A1 = state->m_RF_A1[RFBand]; -+ s32 RF_B1 = state->m_RF_B1[RFBand]; -+ s32 RF_A2 = state->m_RF_A2[RFBand]; -+ s32 RF_B2 = state->m_RF_B2[RFBand]; -+ s32 Capprox = 0; -+ int TComp; -+ -+ state->m_Regs[EP3] &= ~0xE0; /* Power up */ -+ status = UpdateReg(state, EP3); -+ if (status < 0) -+ break; -+ -+ status = ThermometerRead(state, &TMValue_Current); -+ if (status < 0) -+ break; -+ -+ if (RF3 == 0 || Frequency < RF2) -+ Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table; -+ else -+ Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table; -+ -+ TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000; -+ -+ Capprox += TComp; -+ -+ if (Capprox < 0) -+ Capprox = 0; -+ else if (Capprox > 255) -+ Capprox = 255; -+ -+ -+ /* TODO Temperature compensation. There is defenitely a scale factor */ -+ /* missing in the datasheet, so leave it out for now. */ -+ state->m_Regs[EB14] = Capprox; -+ -+ status = UpdateReg(state, EB14); -+ if (status < 0) -+ break; -+ -+ } while (0); -+ return status; -+} -+ -+static int ChannelConfiguration(struct tda_state *state, -+ u32 Frequency, int Standard) -+{ -+ -+ s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency; -+ int status = 0; -+ -+ u8 BP_Filter = 0; -+ u8 RF_Band = 0; -+ u8 GainTaper = 0; -+ u8 IR_Meas = 0; -+ -+ state->IF = IntermediateFrequency; -+ /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ -+ /* get values from tables */ -+ -+ if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) && -+ SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) && -+ SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) && -+ SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) { -+ -+ printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__); -+ return -EINVAL; -+ } -+ -+ do { -+ state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0; -+ state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */ -+ -+ /* m_EP4 default for XToutOn, CAL_Mode (0) */ -+ state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog); -+ /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */ -+ if (Standard <= HF_AnalogMax) -+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog; -+ else if (Standard <= HF_ATSC) -+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT; -+ else if (Standard <= HF_DVBC) -+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC; -+ else -+ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; -+ -+ if ((Standard == HF_FM_Radio) && state->m_bFMInput) -+ state->m_Regs[EP4] |= 80; -+ -+ state->m_Regs[MPD] &= ~0x80; -+ if (Standard > HF_AnalogMax) -+ state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */ -+ -+ state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22; -+ -+ /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */ -+ if (Standard == HF_FM_Radio) -+ state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ -+ else -+ state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */ -+ -+ status = UpdateRegs(state, EB22, EB23); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */ -+ state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas; -+ state->m_Regs[EP2] = (RF_Band << 5) | GainTaper; -+ -+ state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) | -+ (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */ -+ /* AGC1_always_master = 0 */ -+ /* AGC_firstn = 0 */ -+ status = UpdateReg(state, EB1); -+ if (status < 0) -+ break; -+ -+ if (state->m_bMaster) { -+ status = CalcMainPLL(state, Frequency + IntermediateFrequency); -+ if (status < 0) -+ break; -+ status = UpdateRegs(state, TM, EP5); -+ if (status < 0) -+ break; -+ state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */ -+ status = UpdateReg(state, EB4); -+ if (status < 0) -+ break; -+ msleep(1); -+ state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ -+ status = UpdateReg(state, EB4); -+ if (status < 0) -+ break; -+ } else { -+ u8 PostDiv = 0; -+ u8 Div; -+ status = CalcCalPLL(state, Frequency + IntermediateFrequency); -+ if (status < 0) -+ break; -+ -+ SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div); -+ state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77); -+ status = UpdateReg(state, MPD); -+ if (status < 0) -+ break; -+ status = UpdateRegs(state, TM, EP5); -+ if (status < 0) -+ break; -+ -+ state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */ -+ status = UpdateReg(state, EB7); -+ if (status < 0) -+ break; -+ msleep(1); -+ state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */ -+ status = UpdateReg(state, EB7); -+ if (status < 0) -+ break; -+ } -+ msleep(20); -+ if (Standard != HF_FM_Radio) -+ state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */ -+ status = UpdateReg(state, EP3); -+ if (status < 0) -+ break; -+ -+ } while (0); -+ return status; -+} -+ -+static int sleep(struct dvb_frontend *fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ StandBy(state); -+ return 0; -+} -+ -+static int init(struct dvb_frontend *fe) -+{ -+ return 0; -+} -+ -+static int release(struct dvb_frontend *fe) -+{ -+ kfree(fe->tuner_priv); -+ fe->tuner_priv = NULL; -+ return 0; -+} -+ -+ -+static int set_params(struct dvb_frontend *fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ int status = 0; -+ int Standard; -+ u32 bw = fe->dtv_property_cache.bandwidth_hz; -+ u32 delsys = fe->dtv_property_cache.delivery_system; -+ -+ state->m_Frequency = fe->dtv_property_cache.frequency; -+ -+ switch (delsys) { -+ case SYS_DVBT: -+ case SYS_DVBT2: -+ switch (bw) { -+ case 6000000: -+ Standard = HF_DVBT_6MHZ; -+ break; -+ case 7000000: -+ Standard = HF_DVBT_7MHZ; -+ break; -+ case 8000000: -+ Standard = HF_DVBT_8MHZ; -+ break; -+ default: -+ return -EINVAL; -+ } -+ case SYS_DVBC_ANNEX_A: -+ case SYS_DVBC_ANNEX_C: -+ if (bw <= 6000000) -+ Standard = HF_DVBC_6MHZ; -+ else if (bw <= 7000000) -+ Standard = HF_DVBC_7MHZ; -+ else -+ Standard = HF_DVBC_8MHZ; -+ break; -+ default: -+ return -EINVAL; -+ } -+ do { -+ status = RFTrackingFiltersCorrection(state, state->m_Frequency); -+ if (status < 0) -+ break; -+ status = ChannelConfiguration(state, state->m_Frequency, -+ Standard); -+ if (status < 0) -+ break; -+ -+ msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ -+ } while (0); -+ return status; -+} -+ -+#if 0 -+static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc) -+{ -+ if (IFAgc < 500) { -+ /* Scale this from 0 to 50000 */ -+ *pSignalStrength = IFAgc * 100; -+ } else { -+ /* Scale range 500-1500 to 50000-80000 */ -+ *pSignalStrength = 50000 + (IFAgc - 500) * 30; -+ } -+ -+ return 0; -+} -+#endif -+ -+static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ *frequency = state->IF; -+ return 0; -+} -+ -+static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -+{ -+ /* struct tda_state *state = fe->tuner_priv; */ -+ /* *bandwidth = priv->bandwidth; */ -+ return 0; -+} -+ -+ -+static struct dvb_tuner_ops tuner_ops = { -+ .info = { -+ .name = "NXP TDA18271C2D", -+ .frequency_min = 47125000, -+ .frequency_max = 865000000, -+ .frequency_step = 62500 -+ }, -+ .init = init, -+ .sleep = sleep, -+ .set_params = set_params, -+ .release = release, -+ .get_if_frequency = get_if_frequency, -+ .get_bandwidth = get_bandwidth, -+}; -+ -+struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, u8 adr) -+{ -+ struct tda_state *state; -+ -+ state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); -+ if (!state) -+ return NULL; -+ -+ fe->tuner_priv = state; -+ state->adr = adr; -+ state->i2c = i2c; -+ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); -+ reset(state); -+ InitCal(state); -+ -+ return fe; -+} -+EXPORT_SYMBOL_GPL(tda18271c2dd_attach); -+ -+MODULE_DESCRIPTION("TDA18271C2 driver"); -+MODULE_AUTHOR("DD"); -+MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk_lockstatus_fix.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk_lockstatus_fix.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk_lockstatus_fix.diff 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/drxk_lockstatus_fix.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,10 +0,0 @@ ---- a/frontends/drxk_hard.c 2012-01-21 18:02:59.000000000 +0100 -+++ b/frontends/drxk_hard.c 2012-01-21 18:05:06.000000000 +0100 -@@ -1958,6 +1958,7 @@ static int GetLockStatus(struct drxk_sta - status = GetDVBTLockStatus(state, pLockStatus); - break; - default: -+ status = 0; - break; - } - error: diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/srcversion.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/srcversion.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.5yavdr0/patches/srcversion.diff 2013-11-09 17:55:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.5yavdr0/patches/srcversion.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,32 +0,0 @@ -diff --git a/frontends/stv6110x.c b/frontends/stv6110x.c -index f36cab1..ed013d5 100644 ---- a/frontends/stv6110x.c -+++ b/frontends/stv6110x.c -@@ -36,6 +36,11 @@ static unsigned int verbose; - module_param(verbose, int, 0644); - MODULE_PARM_DESC(verbose, "Set Verbosity level"); - -+static int stv6110x_dummy_for_srcversion(void) -+{ -+ return 0; -+} -+ - static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data) - { - int ret; -diff --git a/frontends/lnbp21.c b/frontends/lnbp21.c -index 1343725..9098aee 100644 ---- a/frontends/lnbp21.c -+++ b/frontends/lnbp21.c -@@ -44,6 +44,11 @@ struct lnbp21 { - u8 i2c_addr; - }; - -+static int lnbp21_dummy_for_srcversion(void) -+{ -+ return 0; -+} -+ - static int lnbp21_set_voltage(struct dvb_frontend *fe, - fe_sec_voltage_t voltage) - { diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/CHANGELOG dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/CHANGELOG --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/CHANGELOG 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/CHANGELOG 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,112 @@ +0.9.8 2013.05.05 + +- + +0.9.7 2013.04.15 + +- Octopus Net complete + +- changes for 3.8 kernels + + +0.9.6 2012.09.26 + +- basic Octopus Net support + + +0.9.5 2012.08.05 + +- cleanup + +0.9.4 2012.07.11 + +- support for new modulator bitstream 1.1 + +0.9.3 2012.06.13 + +- add hwid, remap attributes + +0.9.2 2012.06.08 + +- fix cxd2099 address writing optmization + +- add setting of TS output gap size through sysfs + gap_size = (gap_value*2)+4 + bit rate = 72 Mbps * 188 / gap_size + +0.9.1 2012.05.01 + +- support for reworked DVB-C modulator + +- support for multiple channels + +- move some funktions from tasklets back into + interrupt in those cases where it is more efficient + + +0.9.0 2012.03.05 + +- initial support of DVB-C modulator card + +- rework of redirect mechanism to support modulator + + +0.8.5 2012.01.30 + +- init DMA_BUFFER_CONTROL before starting input/output + in case it was not stopped properly before reboot + (can only happen on cards on PCIe extensions without reset line) + + +0.8.4 2012.01.04 + +- support for reading bridge serial number + +- test code for proper start/stop of redirected streams + + +0.8.3 2011.12.18 + +- add support for EEProms on 0x50 + +- make flashprog safer to use for end users + +- lost of kernel coding style adjustments + + +0.8.2 2011.10.14 + +- added some documentation in docs/ + +0.8.1 2011.10.13 + +- signal strength and SNR for STV0367/TDA18212 combo + +- serial number support via sysfs + + +0.8 2011.07.30 + +- Support for DVB-C/T cards with stv0367 demod and TDA18212 tuner + +- loopback TS for testing + +- support of octopus cards with fan, led and temperature sensors + via attributes. + +- redirect of TS to CI and back + + +0.7 2011.06.14 + +- Add IDs for new cards in ddbridge driver + +- Change dvb adapter allocation for ddbridge driver + Configurable with module parameter adapter_alloc: + + 0 = one adapter per io (old behavior) + 1 = one per tab with io present (tab connected to something) + 2 = one per tab regardless of something connected or not + 3 = one adapter for all devices of one card + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/Kbuild 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/Kbuild 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,7 @@ +# +# Makefile for the kernel multimedia device drivers. +# + +obj-y := dvb-core/ \ + ddbridge/ \ + frontends/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/Makefile 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,19 @@ +KDIR ?= /lib/modules/$(shell uname -r)/build +PWD := $(shell pwd) + +MODDEFS := CONFIG_DVB_CORE=m CONFIG_DVB_DDBRIDGE=m CONFIG_DVB_DRXK=m CONFIG_DVB_TDA18271C2DD=m CONFIG_DVB_CXD2099=m CONFIG_DVB_LNBP21=m CONFIG_DVB_STV090x=m CONFIG_DVB_STV6110x=m CONFIG_DVB_STV0367=m CONFIG_DVB_TDA18212=m CONFIG_DVB_STV0367DD=m CONFIG_DVB_TDA18212DD=m CONFIG_DVB_OCTONET=m CONFIG_DVB_CXD2843=m + +all: + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) $(MODDEFS) modules + $(MAKE) -C apps + +dep: + DIR=`pwd`; (cd $(TOPDIR); make SUBDIRS=$$DIR dep) + +install: all + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules_install + +clean: + rm -rf */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules* + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/Makefile 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,16 @@ +all: cit flashprog modt ddtest setmod + +cit: cit.c + gcc -o cit cit.c -lpthread + +modt: modt.c + gcc -o modt modt.c -lpthread + +setmod: setmod.c + gcc -o setmod setmod.c -I../include/ + +flashprog: flashprog.c + gcc -o flashprog flashprog.c + +ddtest: ddtest.c + gcc -o ddtest ddtest.c \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/cit.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/cit.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/cit.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/cit.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,138 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uint8_t fill[188]={0x47, 0x1f, 0xff, 0x10, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff }; + +uint8_t ts[188]={0x47, 0x0a, 0xaa, 0x00, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff }; + +void proc_buf(uint8_t *buf, uint32_t *d) +{ + uint32_t c; + static uint32_t tc=0; + + + if (buf[1]==0x1f && buf[2]==0xff) { + //printf("fill\n"); + return; + } + if (buf[1]==0x9f && buf[2]==0xff) { + //printf("fill\n"); + return; + } + if (buf[1]==0x1a && buf[2]==0xbb) { + tc++; + if (!(tc&0xfff)) + printf("T %d\n", tc); + return; + } + printf("%02x %02x %02x %02x\n", buf[0], buf[1], buf [2], buf[3]); + if (buf[1]!=0x0a || buf[2]!=0xaa) + return; + c=(buf[4]<<24)|(buf[5]<<16)|(buf[6]<<8)|buf[7]; + if (c!=*d) { + printf("CONT ERROR: got %08x expected %08x\n", c, *d); + *d=c; + } else { + if (memcmp(ts+8, buf+8, 180)) + printf("error\n"); + if (!(c&0xffff)) + printf("R %d\n", c); + } + (*d)++; +} + +void *get_ts(void *a) +{ + uint8_t buf[188*1024]; + int len, off; + + int fdi=open("/dev/dvb/adapter0/ci0", O_RDONLY); + uint32_t d=0; + + while (1) { + len=read(fdi, buf, 188*1024); + if (len<0) + continue; + if (buf[0]!=0x47) { + read(fdi, buf, 1); + continue; + } + for (off=0; off>24); + cts[5]=(c>>16); + cts[6]=(c>>8); + cts[7]=c; + //write(fdo, fill, 188); + //printf("S %d\n", c); + c++; + //usleep(100000+0xffff&rand()); + //usleep(1000); + } + write(fdo, buf, 188*SNUM); + } +} + + +int main() +{ + pthread_t th; + + memset(ts+8, 180, 0x5a); + pthread_create(&th, NULL, get_ts, NULL); + usleep(10000); + send(); +} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/citin.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/citin.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/citin.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/citin.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,61 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void proc_ts(int i, uint8_t *buf) +{ + uint16_t pid=0x1fff&((buf[1]<<8)|buf[2]); + + if (buf[3]&0xc0) /* only descrambled packets */ + return; + /* only ORF */ + if (pid==160 || pid==161 || pid==1001||pid==13001 || pid==0) + write(1, buf, 188); +} + +#define TSBUFSIZE (100*188) + +void citest() +{ + uint8_t *buf; + uint8_t id; + int i, nts; + int len; + int ts=open("/dev/dvb/adapter4/sec0", O_RDONLY); + buf=(uint8_t *)malloc(TSBUFSIZE); + + + while(1) { + len=read(ts, buf, TSBUFSIZE); + if (len<0) { + continue; + } + if (buf[0]!=0x47) { + read(ts, buf, 1); + continue; + } + if (len%188) { /* should not happen */ + printf("blah\n"); + continue; + } + nts=len/188; + for (i=0; i +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TSBUFSIZE (100*188) + +void citest() +{ + uint8_t *buf; + uint8_t id; + int i, nts; + int len; + int ts0=open("/dev/dvb/adapter0/dvr0", O_RDONLY); + int ts1=open("/dev/dvb/adapter4/sec0", O_WRONLY); + int demux0=open("/dev/dvb/adapter0/demux0", O_RDWR); + + struct dmx_pes_filter_params pesFilterParams; + + pesFilterParams.input = DMX_IN_FRONTEND; + pesFilterParams.output = DMX_OUT_TS_TAP; + pesFilterParams.pes_type = DMX_PES_OTHER; + pesFilterParams.flags = DMX_IMMEDIATE_START; + + pesFilterParams.pid = 8192; + if (ioctl(demux0, DMX_SET_PES_FILTER, &pesFilterParams) < 0) { + printf("Could not set PES filter\n"); + return; + } + buf=(uint8_t *)malloc(TSBUFSIZE); + + while(1) { + len=read(ts0, buf, TSBUFSIZE); + if (len<=0) + break; + if (buf[0]!=0x47) + printf("oops\n"); + write(ts1, buf, len); + } +} + +int main() +{ + citest(); +} + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/ddtest.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/ddtest.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/ddtest.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/ddtest.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1137 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DDB_MAGIC 'd' + +struct ddb_id { + __u16 vendor; + __u16 device; + __u16 subvendor; + __u16 subdevice; + __u32 hw; + __u32 regmap; +}; + +struct ddb_flashio { + __u8 *write_buf; + __u32 write_len; + __u8 *read_buf; + __u32 read_len; +}; + +struct ddb_reg { + __u32 reg; + __u32 val; +}; + +struct ddb_mem { + __u32 off; + __u8 *buf; + __u32 len; +}; + +#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) +#define IOCTL_DDB_GPIO_IN _IOWR(DDB_MAGIC, 0x01, struct ddb_gpio) +#define IOCTL_DDB_GPIO_OUT _IOWR(DDB_MAGIC, 0x02, struct ddb_gpio) +#define IOCTL_DDB_ID _IOR(DDB_MAGIC, 0x03, struct ddb_id) +#define IOCTL_DDB_READ_REG _IOWR(DDB_MAGIC, 0x04, struct ddb_reg) +#define IOCTL_DDB_WRITE_REG _IOW(DDB_MAGIC, 0x05, struct ddb_reg) +#define IOCTL_DDB_READ_MEM _IOWR(DDB_MAGIC, 0x06, struct ddb_mem) +#define IOCTL_DDB_WRITE_MEM _IOR(DDB_MAGIC, 0x07, struct ddb_mem) + +typedef int (*COMMAND_FUNCTION)(int dev, int argc, char* argv[], uint32_t Flags); + +enum { + REPEAT_FLAG = 0x00000001, + SILENT_FLAG = 0x00000002, +}; + +enum { + UNKNOWN_FLASH = 0, + ATMEL_AT45DB642D = 1, + SSTI_SST25VF016B = 2, + SSTI_SST25VF032B = 3, +}; + +struct SCommand +{ + char* Name; + COMMAND_FUNCTION Function; + int Open; + char* Help; +}; + +// -------------------------------------------------------------------------------------------- + +void Dump(const uint8_t *b, uint32_t start, int l) +{ + int i, j; + + for (j = 0; j < l; j += 16, b += 16) { + printf("%04x: ", start + j); + for (i = 0; i < 16; i++) + if (i + j < l) + printf("%02x ", b[i]); + else + printf(" "); + printf(" |"); + for (i = 0; i < 16; i++) + if (i + j < l) + putchar((b[i] > 31 && b[i] < 127) ? b[i] : '.'); + printf("|\n"); + } +} + +int readreg(int dev, uint32_t RegAddress, uint32_t *pRegValue) +{ + struct ddb_reg reg = { .reg = RegAddress }; + int ret; + + ret = ioctl(dev, IOCTL_DDB_READ_REG, ®); + if (ret < 0) + return ret; + if (pRegValue) + *pRegValue = reg.val; + return 0; +} + +int writereg(int dev, uint32_t RegAddress, uint32_t RegValue) +{ + struct ddb_reg reg = { .reg = RegAddress, .val = RegValue}; + + return ioctl(dev, IOCTL_DDB_WRITE_REG, ®); +} + +int FlashIO(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen) +{ + struct ddb_flashio fio = { + .write_buf=wbuf, + .write_len=wlen, + .read_buf=rbuf, + .read_len=rlen, + }; + + return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio); +} + +int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len) +{ + int ret; + uint8_t cmd[4]; + uint32_t l; + + while (len) { + cmd[0] = 3; + cmd[1] = (addr >> 16) & 0xff; + cmd[2] = (addr >> 8) & 0xff; + cmd[3] = addr & 0xff; + + if (len > 1024) + l = 1024; + else + l = len; + ret = FlashIO(ddb, cmd, 4, buf, l); + if (ret < 0) + return ret; + addr += l; + buf += l; + len -= l; + } + return 0; +} + +int ReadFlash(int ddb, int argc, char *argv[], uint32_t Flags) +{ + uint32_t Start; + uint32_t Len; + uint8_t *Buffer; + + if (argc < 2 ) + return -1; + Start = strtoul(argv[0],NULL,16); + Len = strtoul(argv[1],NULL,16); + + Buffer = malloc(Len); + if (flashread(ddb, Buffer, Start, Len) < 0) { + printf("flashread error\n"); + free(Buffer); + return 0; + } + + Dump(Buffer,Start,Len); + + free(Buffer); + return 0; +} + + + +int FlashDetect(int dev) +{ + uint8_t Cmd = 0x9F; + uint8_t Id[3]; + + int r = FlashIO(dev, &Cmd, 1, Id, 3); + if (r < 0) + return r; + + if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x41) + r = SSTI_SST25VF016B; + else if (Id[0] == 0xBF && Id[1] == 0x25 && Id[2] == 0x4A) + r = SSTI_SST25VF032B; + else if ( Id[0] == 0x1F && Id[1] == 0x28) + r = ATMEL_AT45DB642D; + else r = UNKNOWN_FLASH; + + switch(r) { + case UNKNOWN_FLASH : + printf("Unknown Flash Flash ID = %02x %02x %02x\n",Id[0],Id[1],Id[2]); + break; + case ATMEL_AT45DB642D : + printf("Flash: Atmel AT45DB642D 64 MBit\n"); + break; + case SSTI_SST25VF016B : + printf("Flash: SSTI SST25VF016B 16 MBit\n"); + break; + case SSTI_SST25VF032B : + printf("Flash: SSTI SST25VF032B 32 MBit\n"); + break; + } + return r; +} + +int FlashChipEraseAtmel(int dev) +{ + int err = 0; + // Note Sector 0 is in 2 parts + int i = 0; + while(i < 0x800000) + { + uint8_t Cmd[4]; + + printf(" Erase %08x\n",i); + Cmd[0] = 0x7C; // Sector Erase + Cmd[1] = ( (( i ) >> 16) & 0xFF ); + Cmd[2] = ( (( i ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + err = FlashIO(dev,Cmd,4,NULL,0); + if( err < 0 ) + break; + while (1) { + Cmd[0] = 0xD7; // Read Status register + err = FlashIO(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x80) == 0x80 ) break; + } + if( i == 0 ) i = 0x2000; + else if( i == 0x2000 ) i = 0x40000; + else i += 0x40000; + } + return 0; +} + +int FlashChipEraseSSTI(int dev) +{ + int err = 0; + uint8_t Cmd[4]; + + do + { + Cmd[0] = 0x50; // EWSR + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x01; // WRSR + Cmd[1] = 0x00; // BPx = 0, Unlock all blocks + err = FlashIO(dev,Cmd,2,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x06; // WREN + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x60; // CHIP Erase + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + while(1) + { + Cmd[0] = 0x05; // RDRS + err = FlashIO(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x01) == 0 ) break; + } + if( err < 0 ) break; + + Cmd[0] = 0x50; // EWSR + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x01; // WRSR + Cmd[1] = 0x1C; // BPx = 0, Lock all blocks + err = FlashIO(dev,Cmd,2,NULL,0); + } + while(0); + + if( err >= 0 ) printf("Flash erase succeeded\n"); + else printf("Flash erase failed\n"); + return 0; +} + + +int FlashWriteAtmel(int dev,uint32_t FlashOffset,uint8_t * Buffer,int BufferSize) +{ + int err = 0, i; + int BlockErase = BufferSize >= 8192; + uint8_t Cmd[4]; + + if( BlockErase ) { + for(i = 0; i < BufferSize; i += 8192 ) { + if( (i & 0xFFFF) == 0 ) + { + printf(" Erase %08x\n",FlashOffset + i); + } + Cmd[0] = 0x50; // Block Erase + Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + err = FlashIO(dev,Cmd,4,NULL,0); + if( err < 0 ) break; + + while(1) { + Cmd[0] = 0xD7; // Read Status register + err = FlashIO(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x80) == 0x80 ) break; + } + } + } + + for(i = 0; i < BufferSize; i += 1024 ) + { + if( (i & 0xFFFF) == 0 ) + { + printf(" Programm %08x\n",FlashOffset + i); + } + uint8_t Cmd[4 + 1024]; + Cmd[0] = 0x84; // Buffer 1 + Cmd[1] = 0x00; + Cmd[2] = 0x00; + Cmd[3] = 0x00; + memcpy(&Cmd[4],&Buffer[i],1024); + + err = FlashIO(dev,Cmd,4 + 1024,NULL,0); + if( err < 0 ) break; + + Cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase) + Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + + err = FlashIO(dev,Cmd,4,NULL,0); + if( err < 0 ) break; + + while(1) + { + Cmd[0] = 0xD7; // Read Status register + err = FlashIO(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x80) == 0x80 ) break; + } + if( err < 0 ) break; + } + return err; +} + +// ************************************************************************************** +// BUG: Erasing and writing an incomplete image will result in an failure to boot golden image. +// FIX: Write the new image from high to low addresses + +int FlashWriteSSTI(int dev,uint32_t FlashOffset,uint8_t * Buffer,int BufferSize) +{ + int err = 0, i, j; + uint8_t Cmd[6]; + + if( (BufferSize % 4096) != 0 ) return -1; // Must be multiple of sector size + + do + { + Cmd[0] = 0x50; // EWSR + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x01; // WRSR + Cmd[1] = 0x00; // BPx = 0, Unlock all blocks + err = FlashIO(dev,Cmd,2,NULL,0); + if( err < 0 ) break; + + for (i = 0; i < BufferSize; i += 4096 ) + { + if( (i & 0xFFFF) == 0 ) + { + printf(" Erase %08x\n",FlashOffset + i); + } + + Cmd[0] = 0x06; // WREN + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x20; // Sector erase ( 4Kb) + Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + err = FlashIO(dev,Cmd,4,NULL,0); + if( err < 0 ) break; + + while(1) + { + Cmd[0] = 0x05; // RDRS + err = FlashIO(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x01) == 0 ) break; + } + if( err < 0 ) break; + + } + if( err < 0 ) break; + + + for (j = BufferSize - 4096; j >= 0; j -= 4096 ) + { + if( (j & 0xFFFF) == 0 ) + { + printf(" Programm %08x\n",FlashOffset + j); + } + + for (i = 0; i < 4096; i += 2 ) + { + + if( i == 0 ) + { + Cmd[0] = 0x06; // WREN + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0xAD; // AAI + Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + Cmd[4] = Buffer[j+i]; + Cmd[5] = Buffer[j+i+1]; + err = FlashIO(dev,Cmd,6,NULL,0); + } + else + { + Cmd[0] = 0xAD; // AAI + Cmd[1] = Buffer[j+i]; + Cmd[2] = Buffer[j+i+1]; + err = FlashIO(dev,Cmd,3,NULL,0); + } + if( err < 0 ) break; + + while(1) + { + Cmd[0] = 0x05; // RDRS + err = FlashIO(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x01) == 0 ) break; + } + if( err < 0 ) break; + } + if( err < 0 ) break; + + Cmd[0] = 0x04; // WDIS + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + } + if( err < 0 ) break; + + + Cmd[0] = 0x50; // EWSR + err = FlashIO(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x01; // WRSR + Cmd[1] = 0x1C; // BPx = 0, Lock all blocks + err = FlashIO(dev,Cmd,2,NULL,0); + + } + while(0); + return err; +} + + + + + +// -------------------------------------------------------------------------------------------- + +int ReadDeviceMemory(int dev,int argc, char* argv[],uint32_t Flags) +{ + uint32_t Start; + uint32_t Len; + uint8_t * Buffer; + + if( argc < 2 ) return -1; + + Start = strtoul(argv[0],NULL,16); + Len = strtoul(argv[1],NULL,16); + if( Start > 0xFFFF || Start + Len > 0x10000 || Len == 0 ) return -1; + Buffer = malloc(Len); + + { + struct ddb_mem mem = {.off=Start, .len=Len, .buf=Buffer }; + ioctl(dev, IOCTL_DDB_READ_MEM, &mem); + } + Dump(Buffer,Start,Len); + free(Buffer); + return 0; +} + +int WriteDeviceMemory(int dev,int argc, char* argv[],uint32_t Flags) +{ + uint8_t * Buffer; + uint32_t Start, Len, i; + + if( argc < 2 ) return -1; + Start = strtoul(argv[0],NULL,16); + Len = argc - 1; + if( Start > 0xFFFF || Start + Len > 0x10000 || Len == 0 ) return -1; + Buffer = malloc(Len + sizeof(uint32_t)); + if( Buffer == NULL ) + return -2; + + *((uint32_t *)Buffer) = Start; + for (i = 0; i < Len; i += 1 ) + Buffer[i+sizeof(uint32_t)] = (uint8_t) strtoul(argv[i+1],NULL,16); + + + { + struct ddb_mem mem = {.off=Start, .len=Len, .buf=Buffer+4 }; + ioctl(dev, IOCTL_DDB_WRITE_MEM, &mem); + } + free(Buffer); + return 0; +} + +int FillDeviceMemory(int dev,int argc, char* argv[],uint32_t Flags) +{ + uint32_t Start, Len; + uint8_t * Buffer; + uint8_t Value = 0; + + if( argc < 2 ) return -1; + Start = strtoul(argv[0],NULL,16); + Len = strtoul(argv[1],NULL,16); + + if (Start > 0xFFFF || Start + Len > 0x10000 || Len == 0 ) + return -1; + + Buffer = malloc(Len); + if (Buffer == NULL) + return -2; + + if(argc > 2) + Value = (uint8_t) strtoul(argv[2],NULL,16); + memset(Buffer, Value, Len); + { + struct ddb_mem mem = {.off=Start, .len=Len, .buf=Buffer }; + ioctl(dev, IOCTL_DDB_WRITE_MEM, &mem); + } + free(Buffer); + return 0; +} + +int GetSetRegister(int dev,int argc, char* argv[],uint32_t Flags) +{ + uint32_t i; + + if( argc < 1 ) return -1; + + uint32_t Reg[2]; + char* p; + Reg[0] = strtoul(argv[0],&p,16) & 0xFFFC; + uint32_t LastReg = Reg[0]; + + if( Reg[0] >= 0x10000 ) return -1; + + if( argc == 1 ) + { + if( *p == '-' ) + { + LastReg = strtoul(&p[1],NULL,16) & 0xFFFC; + } + else if( *p == '+' ) + { + LastReg = Reg[0] + (strtoul(&p[1],NULL,16) - 1) * 4; + } + } + + uint32_t NumRegs = (LastReg - Reg[0]) / 4 + 1; + + if( LastReg >= 0x10000 || LastReg < Reg[0] ) return -1; + + if( argc > 1 ) + { + Reg[1] = strtoul(argv[1],NULL,0); + if( writereg(dev,Reg[0],Reg[1]) != 0 ) + { + return -2; + } + } + else + { + for(i = 0; i < NumRegs; i += 1 ) + { + if (readreg(dev,Reg[0],&Reg[1]) < 0 ) + { + return -2; + } + printf(" Register %02X = %08X (%d)\n",Reg[0],Reg[1],Reg[1]); + Reg[0] += 4; + } + } + + return 0; +} + + +// ----------------------------------------------------------------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------- + +int FlashIOC(int dev,int argc, char* argv[],uint32_t Flags) +{ + uint8_t *Buffer; + uint32_t tmp = 0, i; + uint32_t WriteLen = (argc-1); + uint32_t BufferLength = WriteLen; + uint32_t ReadLen; + + if( argc < 2 ) return -1; + + ReadLen = strtoul(argv[argc-1],NULL,0); + if( ReadLen > BufferLength ) BufferLength = ReadLen ; + + Buffer = malloc(WriteLen); + + for(i = 0; i < (argc-1); i += 1 ) + { + tmp = strtoul(argv[i],NULL,16); + if( tmp > 255 ) + { + return -1; + } + Buffer[i] = (uint8_t) tmp; + } + + if( FlashIO(dev,Buffer,WriteLen,Buffer,ReadLen) < 0 ) + { + return 0; + } + + if( ReadLen > 0 ) + Dump(Buffer,0,ReadLen); + + return 0; + +} + +// ----------------------------------------------------------------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------- + +// Searach and return FPGA ID from Buffer, buffer size must be 64 kByte or larger +uint32_t GetFPGA_ID(uint8_t * Buffer) +{ + uint32_t ID = 0xFFFFFF; + int Len = 0x10000 - 16; + while( Len > 0 ) + { + if( Buffer[0] == 0xBD && Buffer[1] == 0xB3 ) + { + ID = ((Buffer[6]) << 24) | ((Buffer[7]) << 16) | ((Buffer[8]) << 8) | ((Buffer[9])); + break; + } + if( Buffer[0] == 0xBC && Buffer[1] == 0xB3 ) + { + // Proteced bitstream. + ID = ((Buffer[2]^Buffer[6]^Buffer[10]^Buffer[14]) << 24) + | ((Buffer[3]^Buffer[7]^Buffer[11]^Buffer[15]) << 16) + | ((Buffer[4]^Buffer[8]^Buffer[12]^Buffer[16]) << 8) + | ((Buffer[5]^Buffer[9]^Buffer[13]^Buffer[17])); + break; + } + + Len -= 1; + Buffer += 1; + } + + return ID; +} + + +int FlashProg(int dev,int argc, char* argv[],uint32_t Flags) +{ + uint8_t * Buffer = NULL; + int BufferSize = 0; + int BlockErase = 0; + uint32_t FlashOffset = 0x10000; + int SectorSize = 0; + int FlashSize = 0; + int ValidateFPGAType = 1; + int Flash; + uint32_t Id1, Id2; + + if( argc < 1 ) + return -1; + Flash = FlashDetect(dev); + switch(Flash) + { + case ATMEL_AT45DB642D: SectorSize = 1024; FlashSize = 0x800000; break; + case SSTI_SST25VF016B: SectorSize = 4096; FlashSize = 0x200000; break; + case SSTI_SST25VF032B: SectorSize = 4096; FlashSize = 0x400000; break; + } + if (SectorSize == 0) + return 0; + + if( strncasecmp("-SubVendorID",argv[0],strlen(argv[0])) == 0 ) + { + if( argc < 2 ) return -1; + + uint32_t SubVendorID = strtoul(argv[1],NULL,16); + + BufferSize = SectorSize; + FlashOffset = 0; + + Buffer = malloc(BufferSize); + if( Buffer == NULL ) + { + printf("out of memory\n"); + return 0; + } + memset(Buffer,0xFF,BufferSize); + + Buffer[0] = ( ( SubVendorID >> 24 ) & 0xFF ); + Buffer[1] = ( ( SubVendorID >> 16 ) & 0xFF ); + Buffer[2] = ( ( SubVendorID >> 8 ) & 0xFF ); + Buffer[3] = ( ( SubVendorID ) & 0xFF ); + + } + else if( strncasecmp("-Jump",argv[0],strlen(argv[0])) == 0 ) + { + uint32_t Jump; + if( argc < 2 ) return -1; + + Jump = strtoul(argv[1],NULL,16); + + BufferSize = SectorSize; + FlashOffset = FlashSize - SectorSize; + + Buffer = malloc(BufferSize); + if( Buffer == NULL ) + { + printf("out of memory\n"); + return 0; + } + memset(Buffer,0xFF,BufferSize); + + memset(&Buffer[BufferSize - 256 + 0x10],0x00,16); + + Buffer[BufferSize - 256 + 0x10] = 0xbd; + Buffer[BufferSize - 256 + 0x11] = 0xb3; + Buffer[BufferSize - 256 + 0x12] = 0xc4; + Buffer[BufferSize - 256 + 0x1a] = 0xfe; + Buffer[BufferSize - 256 + 0x1e] = 0x03; + Buffer[BufferSize - 256 + 0x1f] = ( ( Jump >> 16 ) & 0xFF ); + Buffer[BufferSize - 256 + 0x20] = ( ( Jump >> 8 ) & 0xFF ); + Buffer[BufferSize - 256 + 0x21] = ( ( Jump ) & 0xFF ); + + } + else + { + if( argc > 1 ) + { + FlashOffset = strtoul(argv[1],NULL,16); + ValidateFPGAType = 0; // Don't validate if offset is given + } + + int fh = open(argv[0],O_RDONLY); + if( fh < 0 ) + { + printf("File not found \n"); + return 0; + } + + int fsize = lseek(fh,0,SEEK_END); + + if( fsize > 4000000 || fsize < SectorSize ) + { + close(fh); + printf("Invalid File Size \n"); + return 0; + } + + if( Flash == ATMEL_AT45DB642D ) + { + BlockErase = fsize >= 8192; + if( BlockErase ) + BufferSize = (fsize + 8191) & ~8191; + else + BufferSize = (fsize + 1023) & ~1023; + } + else + { + BufferSize = (fsize + SectorSize - 1 ) & ~(SectorSize - 1); + } + printf(" Size %08x\n",BufferSize); + + Buffer = malloc(BufferSize); + if( Buffer == NULL ) + { + close(fh); + printf("out of memory\n"); + return 0; + } + + memset(Buffer,0xFF,BufferSize); + lseek(fh,0,SEEK_SET); + read(fh,Buffer,fsize); + close(fh); + + if( BufferSize >= 0x10000 ) + { + int i; + // Clear header + for(i = 0; i < 0x200; i += 1 ) + { + if( *(uint16_t *)(&Buffer[i]) == 0xFFFF ) + break; + Buffer[i] = 0xFF; + } + // Place our own header + + if( ValidateFPGAType ) + { + uint8_t * CmpBuffer = malloc(0x10000); + if( CmpBuffer == NULL ) + { + free(Buffer); + printf("out of memory\n"); + return 0; + } + if (flashread(dev, CmpBuffer, FlashOffset, 0x10000)<0) { + printf("Ioctl returns error\n"); + free(Buffer); + free(CmpBuffer); + return 0; + } + + Id1 = GetFPGA_ID(Buffer); + Id2 = GetFPGA_ID(CmpBuffer); + + if (Id2 != 0xFFFFFFFF ) + { + if( Id1 == 0xFFFFFFFF || Id1 != Id2 ) + { + printf(" FPGA ID mismatch\n"); + free(Buffer); + free(CmpBuffer); + return 0; + } + } + } + + } + } + + int err = -1; + + switch(Flash) + { + case ATMEL_AT45DB642D: err = FlashWriteAtmel(dev,FlashOffset,Buffer,BufferSize); break; + case SSTI_SST25VF016B: + case SSTI_SST25VF032B: err = FlashWriteSSTI(dev,FlashOffset,Buffer,BufferSize); break; + } + + if( err < 0 ) printf(" Programm Error\n"); + else printf(" Programm Done\n"); + + free(Buffer); + return 0; +} + +// ----------------------------------------------------------------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------- + +int FlashVerify(int dev,int argc, char* argv[],uint32_t Flags) +{ + if( argc < 1 ) return -1; + + uint8_t * Buffer = NULL; + uint8_t * Buffer2 = NULL; + int BufferSize = 0; + int BlockErase = 0; + uint32_t FlashOffset = 0x10000; + int fsize, fh; + int i; + int err = 0; + + if( argc > 1 ) + { + FlashOffset = strtoul(argv[1],NULL,16); + } + + fh = open(argv[0],O_RDONLY); + if( fh < 0 ) + { + printf("File not found \n"); + return 0; + } + + fsize = lseek(fh,0,SEEK_END); + + if( fsize > 4000000 || fsize < 1024 ) + { + close(fh); + printf("Invalid File Size \n"); + return 0; + } + BlockErase = fsize >= 8192; + + BufferSize = (fsize + 1023) & ~1023; + printf(" Size %08x\n",BufferSize); + + Buffer = malloc(BufferSize); + if( Buffer == NULL ) + { + close(fh); + printf("out of memory\n"); + return 0; + } + + Buffer2 = malloc(BufferSize); + if( Buffer2 == NULL ) + { + close(fh); + free(Buffer); + printf("out of memory\n"); + return 0; + } + memset(Buffer,0xFF,BufferSize); + memset(Buffer2,0xFF,BufferSize); + lseek(fh,0,SEEK_SET); + read(fh,Buffer,fsize); + close(fh); + + if( BufferSize >= 0x10000 ) + { + int i; + // Clear header + for(i = 0; i < 0x200; i += 1 ) + { + if( *(uint16_t *)(&Buffer[i]) == 0xFFFF ) break; + Buffer[i] = 0xFF; + } + // Place our own header + } + if (flashread(dev, Buffer2, FlashOffset, BufferSize)<0) { + printf("Ioctl returns error\n"); + free(Buffer); + free(Buffer2); + return 0; + } + for (i=0; i 2) { + val = strtoul(argv[2], NULL, 16); + writereg(dev, 0x2c, val); + writereg(dev, 0x20, 0x03); + do { + readreg(dev, 0x20, &val); + } while (val & 0x02); + } else { + writereg(dev, 0x20, 0x07); + do { + readreg(dev, 0x20, &val); + } while (val & 0x02); + readreg(dev, 0x2c, &val); + printf("%04x\n", val); + } + return 0; +} + +struct SCommand CommandTable[] = +{ + { "memread", ReadDeviceMemory, 1, "Read Device Memory : memread " }, + { "memfill", FillDeviceMemory, 1, "Fill Device Memory : memfill []" }, + { "memwrite", WriteDeviceMemory, 1, "Write Device Memory : memwrite .." }, + { "register", GetSetRegister, 1, "Get/Set Register : reg |<[0x]regnum> [[0x]value(32)]" }, + + { "flashread", ReadFlash, 1, "Read Flash : flashread " }, + { "flashio", FlashIO, 1, "Flash IO : flashio .. " }, + { "flashprog", FlashProg, 1, "Flash Programming : flashprog [
]" }, + { "flashprog", FlashProg, 1, "Flash Programming : flashprog -SubVendorID " }, + { "flashprog", FlashProg, 1, "Flash Programming : flashprog -Jump
" }, + { "flashverify", FlashVerify, 1, "Flash Verify : flashverify [
]" }, + { "flasherase", FlashErase, 1, "FlashErase : flasherase" }, + //{ "flashtest", FlashTest, 1, "FlashTest : flashtest" }, + + + { "mdio", mdio, 1, "mdio : mdio []" }, + { NULL,NULL,0 } +}; + +void Help() +{ + int i = 0; + while (CommandTable[i].Name != NULL) { + printf(" %s\n", CommandTable[i].Help); + i += 1; + } +} + + +int main(int argc, char **argv) +{ + int cmd = 0, status; + int i = 1; + int Device = 0; + uint32_t Flags = 0; + int CmdIndex = 0; + int dev; + char ddbname[80]; + + if( argc < 2 ) { + Help(); + return 1; + } + + + while( i < argc ) + { + if (*argv[i] != '-') + break; + if (strcmp(argv[i],"-r") == 0 || strcmp(argv[i],"--repeat") == 0 ) + Flags |= REPEAT_FLAG; + else if( strcmp(argv[i],"-s") == 0 || strcmp(argv[i],"--silent") == 0 ) + Flags |= SILENT_FLAG; + else if( strcmp(argv[i],"-d") == 0 || strcmp(argv[i],"--device") == 0 ) { + i += 1; + if( i < argc ) Device = strtoul(argv[i],NULL,0); + } else if( strcmp(argv[i],"-?") == 0 || strcmp(argv[i],"--help") == 0 ) { + Help(); + return 1; + } + i += 1; + } + + if (i >= argc || Device > 99) { + Help(); + return 1; + } + + sprintf(ddbname, "/dev/ddbridge/card%d", Device); + dev=open(ddbname, O_RDWR); + if (dev < 0) { + printf("Could not open device\n"); + return -1; + } + + CmdIndex = i; + + while( CommandTable[cmd].Name != NULL ) { + if (strncasecmp(CommandTable[cmd].Name,argv[CmdIndex],strlen(argv[CmdIndex])) == 0 ) + break; + cmd += 1; + } + + if (CommandTable[cmd].Name == NULL) { + Help(); + return 1; + } + + if( Flags != 0 ) printf(" Flags: %s %s\n",(Flags&REPEAT_FLAG)?"Repeat":"",(Flags&SILENT_FLAG)?"Silent":""); + status = (*CommandTable[cmd].Function)(dev,argc-CmdIndex-1,&argv[CmdIndex+1],Flags); + + if( status == -1 ) + { + printf(" %s\n",CommandTable[cmd].Help); + } + + + return 0; +} + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/flashprog.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/flashprog.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/flashprog.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/flashprog.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,574 @@ +/* +/* flashprog - Programmer for flash on Digital Devices Octopus + * + * Copyright (C) 2010-2011 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DDB_MAGIC 'd' + +struct ddb_id { + __u16 vendor; + __u16 device; + __u16 subvendor; + __u16 subdevice; + __u32 hw; + __u32 regmap; +}; + +struct ddb_flashio { + __u8 *write_buf; + __u32 write_len; + __u8 *read_buf; + __u32 read_len; +}; + +#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) +#define IOCTL_DDB_ID _IOR(DDB_MAGIC, 0x03, struct ddb_id) + + +int flashio(int ddb, uint8_t *wbuf, uint32_t wlen, uint8_t *rbuf, uint32_t rlen) +{ + struct ddb_flashio fio = { + .write_buf=wbuf, + .write_len=wlen, + .read_buf=rbuf, + .read_len=rlen, + }; + + return ioctl(ddb, IOCTL_DDB_FLASHIO, &fio); +} + +enum { + UNKNOWN_FLASH = 0, + ATMEL_AT45DB642D = 1, + SSTI_SST25VF016B = 2, + SSTI_SST25VF032B = 3, +}; + + +int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len) +{ + uint8_t cmd[4]= {0x03, (addr >> 16) & 0xff, + (addr >> 8) & 0xff, addr & 0xff}; + + return flashio(ddb, cmd, 4, buf, len); +} + +int flashdump(int ddb, uint32_t addr, uint32_t len) +{ + int i, j; + uint8_t buf[32]; + int bl = sizeof(buf); + + for (j=0; j= 8192; + int i; + + if (BlockErase) { + for(i = 0; i < BufferSize; i += 8192 ) { + uint8_t Cmd[4]; + if( (i & 0xFFFF) == 0 ) + printf(" Erase %08x\n",FlashOffset + i); + Cmd[0] = 0x50; // Block Erase + Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + err = flashio(dev,Cmd,4,NULL,0); + if( err < 0 ) break; + + while( 1 ) + { + Cmd[0] = 0xD7; // Read Status register + err = flashio(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x80) == 0x80 ) break; + } + } + } + + for(i = 0; i < BufferSize; i += 1024 ) + { + uint8_t Cmd[4 + 1024]; + if( (i & 0xFFFF) == 0 ) + { + printf(" Program %08x\n",FlashOffset + i); + } + Cmd[0] = 0x84; // Buffer 1 + Cmd[1] = 0x00; + Cmd[2] = 0x00; + Cmd[3] = 0x00; + memcpy(&Cmd[4],&Buffer[i],1024); + + err = flashio(dev,Cmd,4 + 1024,NULL,0); + if( err < 0 ) break; + + Cmd[0] = BlockErase ? 0x88 : 0x83; // Buffer to Main Memory (with Erase) + Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + + err = flashio(dev,Cmd,4,NULL,0); + if( err < 0 ) break; + + while( 1 ) + { + Cmd[0] = 0xD7; // Read Status register + err = flashio(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x80) == 0x80 ) break; + } + if( err < 0 ) break; + } + return err; +} + +int FlashWriteSSTI(int dev, uint32_t FlashOffset, uint8_t *Buffer, int BufferSize) +{ + int err = 0; + uint8_t Cmd[6]; + int i, j; + + // Must be multiple of sector size + if( (BufferSize % 4096) != 0 ) + return -1; + + do { + Cmd[0] = 0x50; // EWSR + err = flashio(dev,Cmd,1,NULL,0); + if( err < 0 ) + break; + + Cmd[0] = 0x01; // WRSR + Cmd[1] = 0x00; // BPx = 0, Unlock all blocks + err = flashio(dev,Cmd,2,NULL,0); + if( err < 0 ) + break; + + for(i = 0; i < BufferSize; i += 4096 ) { + if( (i & 0xFFFF) == 0 ) + printf(" Erase %08x\n",FlashOffset + i); + Cmd[0] = 0x06; // WREN + err = flashio(dev,Cmd,1,NULL,0); + if( err < 0 ) + break; + + Cmd[0] = 0x20; // Sector erase ( 4Kb) + Cmd[1] = ( (( FlashOffset + i ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + i ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + err = flashio(dev,Cmd,4,NULL,0); + if( err < 0 ) + break; + + while(1) { + Cmd[0] = 0x05; // RDRS + err = flashio(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x01) == 0 ) break; + } + if( err < 0 ) break; + } + if( err < 0 ) + break; + for(j = BufferSize - 4096; j >= 0; j -= 4096 ) { + if( (j & 0xFFFF) == 0 ) + printf(" Program %08x\n",FlashOffset + j); + + for(i = 0; i < 4096; i += 2 ) { + if( i == 0 ) { + Cmd[0] = 0x06; // WREN + err = flashio(dev,Cmd,1,NULL,0); + if( err < 0 ) + break; + + Cmd[0] = 0xAD; // AAI + Cmd[1] = ( (( FlashOffset + j ) >> 16) & 0xFF ); + Cmd[2] = ( (( FlashOffset + j ) >> 8) & 0xFF ); + Cmd[3] = 0x00; + Cmd[4] = Buffer[j+i]; + Cmd[5] = Buffer[j+i+1]; + err = flashio(dev,Cmd,6,NULL,0); + } else { + Cmd[0] = 0xAD; // AAI + Cmd[1] = Buffer[j+i]; + Cmd[2] = Buffer[j+i+1]; + err = flashio(dev,Cmd,3,NULL,0); + } + if( err < 0 ) + break; + + while(1) { + Cmd[0] = 0x05; // RDRS + err = flashio(dev,Cmd,1,&Cmd[0],1); + if( err < 0 ) break; + if( (Cmd[0] & 0x01) == 0 ) break; + } + if( err < 0 ) break; + } + if( err < 0 ) break; + + Cmd[0] = 0x04; // WDIS + err = flashio(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + } + if( err < 0 ) break; + + Cmd[0] = 0x50; // EWSR + err = flashio(dev,Cmd,1,NULL,0); + if( err < 0 ) break; + + Cmd[0] = 0x01; // WRSR + Cmd[1] = 0x1C; // BPx = 0, Lock all blocks + err = flashio(dev,Cmd,2,NULL,0); + } while(0); + return err; +} + +void get_id(int ddb, struct ddb_id *ddbid) { + uint8_t id[4]; + + if (ioctl(ddb, IOCTL_DDB_ID, ddbid)>=0) + return; + memset(ddbid, 0, sizeof(*ddbid)); + flashread(ddb, id, 0, 4); + printf("%02x %02x %02x %02x\n", + id[0], id[1], id[2], id[3]); + ddbid->subvendor=(id[0] << 8) | id[1]; + ddbid->subdevice=(id[2] << 8) | id[3]; +} + +int sure() +{ + char c; + + printf("\n\nWARNING! Flashing a new FPGA image might make your card unusable!\n"); + printf("\n\nWARNUNG! Das Flashen eines neuen FPGA-Images kann Ihre Karte unbrauchbar machen.\n"); + printf("\n\nAre you sure? y/n?"); + printf("\n\nSind Sie sicher? y/n?"); + fflush(0); + c = getchar(); + if (c!='y') { + printf("\nFlashing aborted.\n\n"); + return -1; + } + printf("\nStarting to flash\n\n"); + return 0; +} + + +int main(int argc, char **argv) +{ + char ddbname[80]; + int type = 0; + struct ddb_id ddbid; + uint8_t *buffer; + int BufferSize = 0; + int BlockErase = 0; + uint32_t FlashOffset = 0x10000; + int ddb; + int i, err; + int SectorSize=0; + int FlashSize=0; + int Flash; + + uint32_t svid=0, jump=0, dump=0; + int bin; + + int ddbnum = 0; + int force = 0; + + while (1) { + int option_index = 0; + int c; + static struct option long_options[] = { + {"svid", required_argument, NULL, 's'}, + {"help", no_argument , NULL, 'h'}, + {"force", no_argument , NULL, 'f'}, + {0, 0, 0, 0} + }; + c = getopt_long(argc, argv, + "d:n:s:o:l:dfhj", + long_options, &option_index); + if (c==-1) + break; + + switch (c) { + case 'd': + dump = strtoul(optarg, NULL, 16); + break; + case 's': + svid = strtoul(optarg, NULL, 16); + break; + case 'o': + FlashOffset = strtoul(optarg, NULL, 16); + break; + case 'n': + ddbnum = strtol(optarg, NULL, 0); + break; + case 'f': + force = 1; + break; + case 'j': + jump = 1; + break; + case 'h': + default: + break; + + } + } + if (optind> 24 ) & 0xFF); + buffer[1] = ((svid >> 16 ) & 0xFF); + buffer[2] = ((svid >> 8 ) & 0xFF); + buffer[3] = ((svid ) & 0xFF); + } else { + int fh, i; + int fsize; + char *fname; + + switch (type) { + default: + case 0: + fname="DVBBridgeV1B_DVBBridgeV1B.bit"; + printf("Octopus\n"); + break; + case 1: + fname="CIBridgeV1B_CIBridgeV1B.bit"; + printf("Octopus CI\n"); + break; + case 2: + fname="DVBModulatorV1B_DVBModulatorV1B.bit"; + printf("Modulator\n"); + break; + case 3: + fname="DVBBridgeV1A_DVBBridgeV1A.bit"; + printf("Octopus 35\n"); + break; + } + //fname="DVBNetPCIeV1A_DVBNetPCIeV1A.bit"; + //fname="DVBNetV1A_DVBNetV1A.bit"; + + fh = open(fname, O_RDONLY); + if (fh < 0 ) { + printf("File not found \n"); + return 0; + } + printf("Using bitstream %s\n", fname); + + fsize = lseek(fh,0,SEEK_END); + if( fsize > 4000000 || fsize < SectorSize ) + { + close(fh); + printf("Invalid File Size \n"); + return 0; + } + + if( Flash == ATMEL_AT45DB642D ) { + BlockErase = fsize >= 8192; + if( BlockErase ) + BufferSize = (fsize + 8191) & ~8191; + else + BufferSize = (fsize + 1023) & ~1023; + } else { + BufferSize = (fsize + SectorSize - 1 ) & ~(SectorSize - 1); + } + printf(" Size %08x, target %08x\n", BufferSize, FlashOffset); + + buffer = malloc(BufferSize); + + if( buffer == NULL ) { + close(fh); + printf("out of memory\n"); + return 0; + } + + memset(buffer, 0xFF, BufferSize); + lseek(fh, 0, SEEK_SET); + read(fh, buffer, fsize); + close(fh); + + if (BufferSize >= 0x10000) { + for(i = 0; i < 0x200; i += 1 ) { + if ( *(uint16_t *) (&buffer[i]) == 0xFFFF ) + break; + buffer[i] = 0xFF; + } + } + } + if (!force && sure()<0) + return 0; + switch(Flash) { + case ATMEL_AT45DB642D: + err = FlashWriteAtmel(ddb, FlashOffset, buffer, BufferSize); + break; + case SSTI_SST25VF016B: + case SSTI_SST25VF032B: + err = FlashWriteSSTI(ddb, FlashOffset, buffer, BufferSize); + break; + } + + if (err < 0) + printf("Programming Error\n"); + else + printf("Programming Done\n"); + + free(buffer); + return 0; +} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/modt.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/modt.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/modt.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/modt.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,36 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define SNUM 1000 +//671 +void send(void) +{ + uint8_t buf[188*SNUM], *cts; + int i; + uint32_t c=0; + int fdo; + + fdo=open("/dev/dvb/adapter0/mod0", O_WRONLY); + + + while (1) { + read(0, buf, sizeof(buf)); + write(fdo, buf, 188*SNUM); + } +} + + +int main() +{ + send(); +} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/setmod.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/setmod.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/apps/setmod.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/apps/setmod.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,31 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +int main() +{ + int fd; + struct dvb_mod_params mp; + struct dvb_mod_channel_params mc; + + fd = open("/dev/dvb/adapter1/mod0", O_RDONLY); + + mp.base_frequency = 730000000; + mp.attenuator = 0; + ioctl(fd, DVB_MOD_SET, &mp); + + mc.modulation = QAM_256; + ioctl(fd, DVB_MOD_CHANNEL_SET, &mc); + close(fd); +} + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Kbuild 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Kbuild 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,8 @@ +EXTRA_CFLAGS += -DCONFIG_DVB_LNBP21 -DCONFIG_DVB_STV090x -DCONFIG_DVB_STV6110x -g + +obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o +obj-$(CONFIG_DVB_OCTONET) += octonet.o + +EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -Idrivers/media/dvb-frontends +EXTRA_CFLAGS += -Idrivers/media/common/tuners +NOSTDINC_FLAGS += -I$(SUBDIRS)/frontends -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/Makefile 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,19 @@ +KDIR ?= /lib/modules/$(shell uname -r)/build +PWD := $(shell pwd) + +MODDEFS := CONFIG_DVB_DDBRIDGE=m + +all: + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) $(MODDEFS) modules + $(MAKE) -C apps + +dep: + DIR=`pwd`; (cd $(TOPDIR); make SUBDIRS=$$DIR dep) + +install: all + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules_install + +clean: + rm -rf */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules* + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-core.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-core.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-core.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-core.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,3337 @@ +DEFINE_MUTEX(redirect_lock); + +static int ci_bitrate = 72000; +module_param(ci_bitrate, int, 0444); +MODULE_PARM_DESC(ci_bitrate, " Bitrate for output to CI."); + +static int ts_loop = -1; +module_param(ts_loop, int, 0444); +MODULE_PARM_DESC(ts_loop, "TS in/out test loop on port ts_loop"); + +static int vlan = 0; +module_param(vlan, int, 0444); +MODULE_PARM_DESC(vlan, "VLAN and QoS IDs enabled"); + +static int tt = 0; +module_param(tt, int, 0444); +MODULE_PARM_DESC(tt, ""); + +#define DDB_MAX_ADAPTER 32 +static struct ddb *ddbs[DDB_MAX_ADAPTER]; + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +#include "ddbridge-mod.c" +#include "ddbridge-i2c.c" +#include "ddbridge-ns.c" + + +static void ddb_set_dma_table(struct ddb *dev, struct ddb_dma *dma) +{ + u32 i, base; + u64 mem; + + if (!dma) + return; + base = DMA_BASE_ADDRESS_TABLE + dma->nr * 0x100; + for (i = 0; i < dma->num; i++) { + mem = dma->pbuf[i]; + ddbwritel(dev, mem & 0xffffffff, base + i * 8); + ddbwritel(dev, mem >> 32, base + i * 8 + 4); + } + dma->bufreg = (dma->div << 16) | + ((dma->num & 0x1f) << 11) | + ((dma->size >> 7) & 0x7ff); +} + +static void ddb_set_dma_tables(struct ddb *dev) +{ + u32 i; + + for (i = 0; i < dev->info->port_num * 2; i++) + ddb_set_dma_table(dev, dev->input[i].dma); + for (i = 0; i < dev->info->port_num; i++) + ddb_set_dma_table(dev, dev->output[i].dma); +} + + +/******************************************************************************/ +/******************************************************************************/ +/******************************************************************************/ + +static void ddb_redirect_dma(struct ddb *dev, + struct ddb_dma *sdma, + struct ddb_dma *ddma) +{ + u32 i, base; + u64 mem; + + sdma->bufreg = ddma->bufreg; + base = DMA_BASE_ADDRESS_TABLE + sdma->nr * 0x100; + for (i = 0; i < ddma->num; i++) { + mem = ddma->pbuf[i]; + ddbwritel(dev, mem & 0xffffffff, base + i * 8); + ddbwritel(dev, mem >> 32, base + i * 8 + 4); + } +} + +static int ddb_unredirect(struct ddb_port *port) +{ + struct ddb_input *oredi, *iredi = 0; + struct ddb_output *iredo = 0; + + //printk("unredirect %d.%d\n", port->dev->nr, port->nr); + mutex_lock(&redirect_lock); + if (port->output->dma->running) { + mutex_unlock(&redirect_lock); + return -EBUSY; + } + oredi = port->output->redi; + if (!oredi) + goto done; + if (port->input[0]) { + iredi = port->input[0]->redi; + iredo = port->input[0]->redo; + + if (iredo) { + iredo->port->output->redi = oredi; + if (iredo->port->input[0]) { + iredo->port->input[0]->redi = iredi; + ddb_redirect_dma(oredi->port->dev, + oredi->dma, iredo->dma); + } + port->input[0]->redo = 0; + ddb_set_dma_table(port->dev, port->input[0]->dma); + } + oredi->redi = iredi; + port->input[0]->redi = 0; + } + oredi->redo = 0; + port->output->redi = 0; + + ddb_set_dma_table(oredi->port->dev, oredi->dma); +done: + mutex_unlock(&redirect_lock); + return 0; +} + +static int ddb_redirect(u32 i, u32 p) +{ + struct ddb *idev = ddbs[(i >> 4) & 0x1f]; + struct ddb_input *input, *input2; + struct ddb *pdev = ddbs[(p >> 4) & 0x1f]; + struct ddb_port *port; + + if (!idev->has_dma || !pdev->has_dma) + return -EINVAL; + if (!idev || !pdev) + return -EINVAL; + + port = &pdev->port[p & 0x0f]; + if (!port->output) + return -EINVAL; + if (ddb_unredirect(port)) + return -EBUSY; + + if (i == 8) + return 0; + + input = &idev->input[i & 7]; + if (!input) + return -EINVAL; + + mutex_lock(&redirect_lock); + if (port->output->dma->running || input->dma->running) { + mutex_unlock(&redirect_lock); + return -EBUSY; + } + if ((input2 = port->input[0])) { + if (input->redi) { + input2->redi = input->redi; + input->redi = 0; + } else + input2->redi = input; + } + input->redo = port->output; + port->output->redi = input; + + ddb_redirect_dma(input->port->dev, input->dma, port->output->dma); + mutex_unlock(&redirect_lock); + return 0; +} + +/******************************************************************************/ +/******************************************************************************/ +/******************************************************************************/ + +#ifdef DDB_ALT_DMA +static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir) +{ + int i; + + if (!dma) + return; + for (i = 0; i < dma->num; i++) { + if (dma->vbuf[i]) { + dma_unmap_single(&pdev->dev, dma->pbuf[i], + dma->size, + dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE); + kfree(dma->vbuf[i]); + dma->vbuf[i] = 0; + } + } +} + +static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir) +{ + int i; + + if (!dma) + return 0; + for (i = 0; i < dma->num; i++) { + dma->vbuf[i] = kmalloc(dma->size, __GFP_REPEAT); + if (!dma->vbuf[i]) + return -ENOMEM; + dma->pbuf[i] = dma_map_single(&pdev->dev, dma->vbuf[i], + dma->size, + dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE); + if (dma_mapping_error(&pdev->dev, dma->pbuf[i])) { + kfree(dma->vbuf[i]); + return -ENOMEM; + } + } + return 0; +} +#else + +static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir) +{ + int i; + + if (!dma) + return; + for (i = 0; i < dma->num; i++) { + if (dma->vbuf[i]) { + pci_free_consistent(pdev, dma->size, + dma->vbuf[i], dma->pbuf[i]); + dma->vbuf[i] = 0; + } + } +} + +static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir) +{ + int i; + + if (!dma) + return 0; + for (i = 0; i < dma->num; i++) { + dma->vbuf[i] = pci_alloc_consistent(pdev, dma->size, + &dma->pbuf[i]); + if (!dma->vbuf[i]) + return -ENOMEM; + } + return 0; +} +#endif + +static int ddb_buffers_alloc(struct ddb *dev) +{ + int i; + struct ddb_port *port; + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + switch (port->class) { + case DDB_PORT_TUNER: + if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0) + return -1; + if (dma_alloc(dev->pdev, port->input[1]->dma, 0) < 0) + return -1; + break; + case DDB_PORT_CI: + case DDB_PORT_LOOP: + if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0) + return -1; + case DDB_PORT_MOD: + if (dma_alloc(dev->pdev, port->output->dma, 1) < 0) + return -1; + break; + default: + break; + } + } + ddb_set_dma_tables(dev); + return 0; +} + +static void ddb_buffers_free(struct ddb *dev) +{ + int i; + struct ddb_port *port; + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + + if (port->input[0]) + dma_free(dev->pdev, port->input[0]->dma, 0); + if (port->input[1]) + dma_free(dev->pdev, port->input[1]->dma, 0); + if (port->output) + dma_free(dev->pdev, port->output->dma, 1); + } +} + +static void ddb_output_start(struct ddb_output *output) +{ + struct ddb *dev = output->port->dev; + u32 con2; + + con2 = ((output->port->obr << 13) + 71999) / 72000; + con2 = (con2 << 16) | output->port->gap; + + if (output->dma) { + spin_lock_irq(&output->dma->lock); + output->dma->cbuf = 0; + output->dma->coff = 0; + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); + } + if (output->port->class == DDB_PORT_MOD) + ddbridge_mod_output_start(output); + else { + ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); + ddbwritel(dev, 2, TS_OUTPUT_CONTROL(output->nr)); + ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); + ddbwritel(dev, 0x3c, TS_OUTPUT_CONTROL(output->nr)); + ddbwritel(dev, con2, TS_OUTPUT_CONTROL2(output->nr)); + } + if (output->dma) { + ddbwritel(dev, output->dma->bufreg, DMA_BUFFER_SIZE(output->dma->nr)); + ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); + ddbwritel(dev, 1, DMA_BASE_READ); + ddbwritel(dev, 3, DMA_BUFFER_CONTROL(output->dma->nr)); + } + if (output->port->class != DDB_PORT_MOD) { + if (output->port->input[0]->port->class == DDB_PORT_LOOP) + //ddbwritel(dev, 0x15, TS_OUTPUT_CONTROL(output->nr)); + //ddbwritel(dev, 0x45, TS_OUTPUT_CONTROL(output->nr)); + ddbwritel(dev, (1 << 13) | 0x15, TS_OUTPUT_CONTROL(output->nr)); + else + ddbwritel(dev, 0x1d, TS_OUTPUT_CONTROL(output->nr)); + } + if (output->dma) { + output->dma->running = 1; + spin_unlock_irq(&output->dma->lock); + } +} + +static void ddb_output_stop(struct ddb_output *output) +{ + struct ddb *dev = output->port->dev; + + if (output->dma) + spin_lock_irq(&output->dma->lock); + if (output->port->class == DDB_PORT_MOD) + ddbridge_mod_output_stop(output); + else + ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); + if (output->dma) { + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); + output->dma->running = 0; + spin_unlock_irq(&output->dma->lock); + } +} + +static void ddb_input_stop(struct ddb_input *input) +{ + struct ddb *dev = input->port->dev; + + if (input->dma) + spin_lock_irq(&input->dma->lock); + ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); + if (input->dma) { + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); + input->dma->running = 0; + spin_unlock_irq(&input->dma->lock); + } + //printk("input_stop %d.%d\n", dev->nr, input->nr); +} + +static void ddb_input_start(struct ddb_input *input) +{ + struct ddb *dev = input->port->dev; + + if (input->dma) { + spin_lock_irq(&input->dma->lock); + input->dma->cbuf = 0; + input->dma->coff = 0; + ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); + } + ddbwritel(dev, 0, TS_INPUT_CONTROL2(input->nr)); + ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); + ddbwritel(dev, 2, TS_INPUT_CONTROL(input->nr)); + ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); + + if (input->dma) { + ddbwritel(dev, input->dma->bufreg, DMA_BUFFER_SIZE(input->dma->nr)); + ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); + ddbwritel(dev, 1, DMA_BASE_WRITE); + ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma->nr)); + } + if (dev->info->type == DDB_OCTONET) + ddbwritel(dev, 0x01, TS_INPUT_CONTROL(input->nr)); + else + ddbwritel(dev, 0x09, TS_INPUT_CONTROL(input->nr)); + if (input->dma) { + input->dma->running = 1; + spin_unlock_irq(&input->dma->lock); + } + //printk("input_start %d.%d\n", dev->nr, input->nr); +} + + +static int ddb_dvb_input_start(struct ddb_input *input) +{ + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + + if (!dvb->users) + ddb_input_start(input); + + return ++dvb->users; +} + +static int ddb_dvb_input_stop(struct ddb_input *input) +{ + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + + if (--dvb->users) + return dvb->users; + + ddb_input_stop(input); + return 0; +} + +static void ddb_input_start_all(struct ddb_input *input) +{ + struct ddb_input *i = input; + struct ddb_output *o; + + mutex_lock(&redirect_lock); + while (i && (o = i->redo)) { + ddb_output_start(o); + if ((i = o->port->input[0])) + ddb_input_start(i); + } + ddb_input_start(input); + mutex_unlock(&redirect_lock); +} + +static void ddb_input_stop_all(struct ddb_input *input) +{ + struct ddb_input *i = input; + struct ddb_output *o; + + mutex_lock(&redirect_lock); + ddb_input_stop(input); + while (i && (o = i->redo)) { + ddb_output_stop(o); + if ((i = o->port->input[0])) + ddb_input_stop(i); + } + mutex_unlock(&redirect_lock); +} + +static u32 ddb_output_free(struct ddb_output *output) +{ + u32 idx, off, stat = output->dma->stat; + s32 diff; + + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + + if (output->dma->cbuf != idx) { + if ((((output->dma->cbuf + 1) % output->dma->num) == idx) && + (output->dma->size - output->dma->coff <= 188)) + return 0; + return 188; + } + diff = off - output->dma->coff; + if (diff <= 0 || diff > 188) + return 188; + return 0; +} + +static u32 ddb_dma_free(struct ddb_dma *dma) +{ + u32 idx, off, stat = dma->stat; + s32 p1, p2, diff; + + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + + p1 = idx * dma->size + off; + p2 = dma->cbuf * dma->size + dma->coff; + + diff = p1 - p2; + if (diff <= 0) + diff += dma->num * dma->size; + return diff; +} + +static ssize_t ddb_output_write(struct ddb_output *output, + const u8 *buf, size_t count) +{ + struct ddb *dev = output->port->dev; + u32 idx, off, stat = output->dma->stat; + u32 left = count, len; + + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + + while (left) { + len = output->dma->size - output->dma->coff; + if ((((output->dma->cbuf + 1) % output->dma->num) == idx) && + (off == 0)) { + if (len <= 188) + break; + len -= 188; + } + if (output->dma->cbuf == idx) { + if (off > output->dma->coff) { + len = off - output->dma->coff; + len -= (len % 188); + if (len <= 188) + break; + len -= 188; + } + } + if (len > left) + len = left; + if (copy_from_user(output->dma->vbuf[output->dma->cbuf] + + output->dma->coff, + buf, len)) + return -EIO; +#ifdef DDB_ALT_DMA + dma_sync_single_for_device(dev->dev, + output->dma->pbuf[output->dma->cbuf], + output->dma->size, DMA_TO_DEVICE); +#endif + left -= len; + buf += len; + output->dma->coff += len; + if (output->dma->coff == output->dma->size) { + output->dma->coff = 0; + output->dma->cbuf = ((output->dma->cbuf + 1) % + output->dma->num); + } + ddbwritel(dev, + (output->dma->cbuf << 11) | (output->dma->coff >> 7), + DMA_BUFFER_ACK(output->dma->nr)); + } + return count - left; +} + +static u32 ddb_input_free_bytes(struct ddb_input *input) +{ + struct ddb *dev = input->port->dev; + u32 idx, off, stat = input->dma->stat; + u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); + + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + + if (ctrl & 4) + return 0; + if (input->dma->cbuf != idx) + return 1; + return 0; +} + +static s32 ddb_output_used_bufs(struct ddb_output *output) +{ + u32 idx, off, stat, ctrl; + s32 diff; + + spin_lock_irq(&output->dma->lock); + stat = output->dma->stat; + ctrl = output->dma->ctrl; + spin_unlock_irq(&output->dma->lock); + + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + + if (ctrl & 4) + return 0; + diff = output->dma->cbuf - idx; + if (diff == 0 && off < output->dma->coff) + return 0; + if (diff <= 0) + diff += output->dma->num; + return diff; +} + +static s32 ddb_input_free_bufs(struct ddb_input *input) +{ + u32 idx, off, stat, ctrl; + s32 free; + + spin_lock_irq(&input->dma->lock); + ctrl = input->dma->ctrl; + stat = input->dma->stat; + spin_unlock_irq(&input->dma->lock); + if (ctrl & 4) + return 0; + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + free = input->dma->cbuf - idx; + if (free == 0 && off < input->dma->coff) + return 0; + if (free <= 0) + free += input->dma->num; + return free - 1; +} + +static u32 ddb_output_ok(struct ddb_output *output) +{ + struct ddb_input *input = output->port->input[0]; + s32 diff; + + diff = ddb_input_free_bufs(input) - ddb_output_used_bufs(output); + if (diff > 0) + return 1; + return 0; +} + +static u32 ddb_input_avail(struct ddb_input *input) +{ + struct ddb *dev = input->port->dev; + u32 idx, off, stat = input->dma->stat; + u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); + + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + + if (ctrl & 4) { + printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); + ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma->nr)); + return 0; + } + if (input->dma->cbuf != idx || off < input->dma->coff) + return 188; + return 0; +} + +static size_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count) +{ + struct ddb *dev = input->port->dev; + u32 left = count; + u32 idx, off, free, stat = input->dma->stat; + int ret; + + idx = (stat >> 11) & 0x1f; + off = (stat & 0x7ff) << 7; + + while (left) { + if (input->dma->cbuf == idx) + return count - left; + free = input->dma->size - input->dma->coff; + if (free > left) + free = left; +#ifdef DDB_ALT_DMA + dma_sync_single_for_cpu(dev->dev, + input->dma->pbuf[input->dma->cbuf], + input->dma->size, DMA_FROM_DEVICE); +#endif + ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] + + input->dma->coff, free); + if (ret) + return -EFAULT; + input->dma->coff += free; + if (input->dma->coff == input->dma->size) { + input->dma->coff = 0; + input->dma->cbuf = (input->dma->cbuf + 1) % + input->dma->num; + } + left -= free; + ddbwritel(dev, + (input->dma->cbuf << 11) | (input->dma->coff >> 7), + DMA_BUFFER_ACK(input->dma->nr)); + } + return count; +} + +/****************************************************************************/ +/****************************************************************************/ + +static ssize_t ts_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb *dev = output->port->dev; + size_t left = count; + int stat; + + if (!dev->has_dma) + return -EINVAL; + while (left) { + if (ddb_output_free(output) < 188) { + if (file->f_flags & O_NONBLOCK) + break; + if (wait_event_interruptible( + output->dma->wq, + ddb_output_free(output) >= 188) < 0) + break; + } + stat = ddb_output_write(output, buf, left); + if (stat < 0) + return stat; + buf += stat; + left -= stat; + } + return (left == count) ? -EAGAIN : (count - left); +} + +static ssize_t ts_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; + struct ddb *dev = output->port->dev; + int left, read; + + if (!dev->has_dma) + return -EINVAL; + count -= count % 188; + left = count; + while (left) { + if (ddb_input_avail(input) < 188) { + if (file->f_flags & O_NONBLOCK) + break; + if (wait_event_interruptible( + input->dma->wq, + ddb_input_avail(input) >= 188) < 0) + break; + } + read = ddb_input_read(input, buf, left); + left -= read; + buf += read; + } + return (left == count) ? -EAGAIN : (count - left); +} + +static unsigned int ts_poll(struct file *file, poll_table *wait) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; + + unsigned int mask = 0; + + poll_wait(file, &input->dma->wq, wait); + poll_wait(file, &output->dma->wq, wait); + if (ddb_input_avail(input) >= 188) + mask |= POLLIN | POLLRDNORM; + if (ddb_output_free(output) >= 188) + mask |= POLLOUT | POLLWRNORM; + return mask; +} + +static int ts_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + if (!input) + return -EINVAL; + ddb_input_stop(input); + } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + if (!output) + return -EINVAL; + ddb_output_stop(output); + } + return dvb_generic_release(inode, file); +} + +static int ts_open(struct inode *inode, struct file *file) +{ + int err; + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + if (!input) + return -EINVAL; + if (input->redo || input->redi) + return -EBUSY; + } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + if (!output) + return -EINVAL; + } + if ((err = dvb_generic_open(inode, file)) < 0) + return err; + if ((file->f_flags & O_ACCMODE) == O_RDONLY) + ddb_input_start(input); + else if ((file->f_flags & O_ACCMODE) == O_WRONLY) + ddb_output_start(output); + return err; +} + +static int mod_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; + + if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + if (!output) + return -EINVAL; + ddb_output_stop(output); + } + return dvb_generic_release(inode, file); +} + +static int mod_open(struct inode *inode, struct file *file) +{ + int err; + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + + if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + if (!output) + return -EINVAL; + } + if ((err = dvb_generic_open(inode, file)) < 0) + return err; + if ((file->f_flags & O_ACCMODE) == O_WRONLY) + ddb_output_start(output); + return err; +} +static const struct file_operations ci_fops = { + .owner = THIS_MODULE, + .read = ts_read, + .write = ts_write, + .open = ts_open, + .release = ts_release, + .poll = ts_poll, + .mmap = 0, +}; + +static struct dvb_device dvbdev_ci = { + .priv = 0, + .readers = 1, + .writers = 1, + .users = 2, + .fops = &ci_fops, +}; + + +/****************************************************************************/ +/****************************************************************************/ + +static long mod_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return dvb_usercopy(file, cmd, arg, ddbridge_mod_do_ioctl); +} + +static const struct file_operations mod_fops = { + .owner = THIS_MODULE, + .read = ts_read, + .write = ts_write, + .open = mod_open, + .release = mod_release, + .poll = ts_poll, + .mmap = 0, + .unlocked_ioctl = mod_ioctl, +}; + +static struct dvb_device dvbdev_mod = { + .priv = 0, + .readers = 1, + .writers = 1, + .users = 2, + .fops = &mod_fops, +}; + + +#if 0 +static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) +{ + int i; + + for (i = 0; i < dev->info->port_num * 2; i++) { + if (dev->input[i].fe == fe) + return &dev->input[i]; + } + return NULL; +} +#endif + +static int locked_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct ddb_input *input = fe->sec_priv; + struct ddb_port *port = input->port; + struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; + int status; + + if (enable) { + mutex_lock(&port->i2c_gate_lock); + status = dvb->gate_ctrl(fe, 1); + } else { + status = dvb->gate_ctrl(fe, 0); + mutex_unlock(&port->i2c_gate_lock); + } + return status; +} + +#ifdef CONFIG_DVB_DRXK +static int demod_attach_drxk(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + + fe = dvb->fe = dvb_attach(drxk_attach, + i2c, 0x29 + (input->nr&1), + &dvb->fe2); + if (!fe) { + printk(KERN_ERR "No DRXK found!\n"); + return -ENODEV; + } + fe->sec_priv = input; + dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; + fe->ops.i2c_gate_ctrl = locked_gate_ctrl; + return 0; +} +#endif + +#if 0 +struct stv0367_config stv0367_0 = { + .demod_address = 0x1f, + .xtal = 27000000, + .if_khz = 5000, + .if_iq_mode = FE_TER_NORMAL_IF_TUNER, + .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, + .clk_pol = STV0367_RISINGEDGE_CLOCK, +}; + +struct stv0367_config stv0367_1 = { + .demod_address = 0x1e, + .xtal = 27000000, + .if_khz = 5000, + .if_iq_mode = FE_TER_NORMAL_IF_TUNER, + .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, + .clk_pol = STV0367_RISINGEDGE_CLOCK, +}; + + +static int demod_attach_stv0367(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + + fe = dvb->fe = dvb_attach(stv0367ter_attach, + (input->nr & 1) ? &stv0367_1 : &stv0367_0, + i2c); + if (!dvb->fe) { + printk(KERN_ERR "No stv0367 found!\n"); + return -ENODEV; + } + fe->sec_priv = input; + dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; + fe->ops.i2c_gate_ctrl = locked_gate_ctrl; + return 0; +} +#endif + +struct cxd2843_cfg cxd2843_0 = { + .adr = 0x6c, +}; + +struct cxd2843_cfg cxd2843_1 = { + .adr = 0x6d, +}; + +static int demod_attach_cxd2843(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + + fe = dvb->fe = dvb_attach(cxd2843_attach, i2c, + (input->nr & 1) ? &cxd2843_1 : &cxd2843_0); + if (!dvb->fe) { + printk(KERN_ERR "No cxd2843 found!\n"); + return -ENODEV; + } + fe->sec_priv = input; + dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; + fe->ops.i2c_gate_ctrl = locked_gate_ctrl; + return 0; +} + +struct stv0367_cfg stv0367dd_0 = { + .adr = 0x1f, + .xtal = 27000000, +}; + +struct stv0367_cfg stv0367dd_1 = { + .adr = 0x1e, + .xtal = 27000000, +}; + +static int demod_attach_stv0367dd(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + + fe = dvb->fe = dvb_attach(stv0367_attach, i2c, + (input->nr & 1) ? &stv0367dd_1 : &stv0367dd_0, + &dvb->fe2); + if (!dvb->fe) { + printk(KERN_ERR "No stv0367 found!\n"); + return -ENODEV; + } + fe->sec_priv = input; + dvb->gate_ctrl = fe->ops.i2c_gate_ctrl; + fe->ops.i2c_gate_ctrl = locked_gate_ctrl; + return 0; +} + +static int tuner_attach_tda18271(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + + if (dvb->fe->ops.i2c_gate_ctrl) + dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 1); + fe = dvb_attach(tda18271c2dd_attach, dvb->fe, i2c, 0x60); + if (dvb->fe->ops.i2c_gate_ctrl) + dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0); + if (!fe) { + printk(KERN_ERR "No TDA18271 found!\n"); + return -ENODEV; + } + return 0; +} + +static int tuner_attach_tda18212dd(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + + fe = dvb_attach(tda18212dd_attach, dvb->fe, i2c, + (input->nr & 1) ? 0x63 : 0x60); + if (!fe) { + printk(KERN_ERR "No TDA18212 found!\n"); + return -ENODEV; + } + return 0; +} + +#ifdef CONFIG_DVB_TDA18212 +struct tda18212_config tda18212_0 = { + .i2c_address = 0x60, +}; + +struct tda18212_config tda18212_1 = { + .i2c_address = 0x63, +}; + +static int tuner_attach_tda18212(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; + struct tda18212_config *cfg; + + cfg = (input->nr & 1) ? &tda18212_1 : &tda18212_0; + fe = dvb_attach(tda18212_attach, dvb->fe, i2c, cfg); + if (!fe) { + printk(KERN_ERR "No TDA18212 found!\n"); + return -ENODEV; + } + return 0; +} +#endif + +/******************************************************************************/ +/******************************************************************************/ +/******************************************************************************/ + +static struct stv090x_config stv0900 = { + .device = STV0900, + .demod_mode = STV090x_DUAL, + .clk_mode = STV090x_CLK_EXT, + + .xtal = 27000000, + .address = 0x69, + + .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, + .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, + + .repeater_level = STV090x_RPTLEVEL_16, + + .adc1_range = STV090x_ADC_1Vpp, + .adc2_range = STV090x_ADC_1Vpp, + + .diseqc_envelope_mode = true, +}; + +static struct stv090x_config stv0900_aa = { + .device = STV0900, + .demod_mode = STV090x_DUAL, + .clk_mode = STV090x_CLK_EXT, + + .xtal = 27000000, + .address = 0x68, + + .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, + .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, + + .repeater_level = STV090x_RPTLEVEL_16, + + .adc1_range = STV090x_ADC_1Vpp, + .adc2_range = STV090x_ADC_1Vpp, + + .diseqc_envelope_mode = true, +}; + +static struct stv6110x_config stv6110a = { + .addr = 0x60, + .refclk = 27000000, + .clk_div = 1, +}; + +static struct stv6110x_config stv6110b = { + .addr = 0x63, + .refclk = 27000000, + .clk_div = 1, +}; + +static int demod_attach_stv0900(struct ddb_input *input, int type) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + + dvb->fe = dvb_attach(stv090x_attach, feconf, i2c, + (input->nr & 1) ? STV090x_DEMODULATOR_1 + : STV090x_DEMODULATOR_0); + if (!dvb->fe) { + printk(KERN_ERR "No STV0900 found!\n"); + return -ENODEV; + } + if (!dvb_attach(lnbh24_attach, dvb->fe, i2c, 0, + 0, (input->nr & 1) ? + (0x09 - type) : (0x0b - type))) { + printk(KERN_ERR "No LNBH24 found!\n"); + return -ENODEV; + } + return 0; +} + +static int tuner_attach_stv6110(struct ddb_input *input, int type) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; + struct stv6110x_config *tunerconf = (input->nr & 1) ? + &stv6110b : &stv6110a; + struct stv6110x_devctl *ctl; + + ctl = dvb_attach(stv6110x_attach, dvb->fe, tunerconf, i2c); + if (!ctl) { + printk(KERN_ERR "No STV6110X found!\n"); + return -ENODEV; + } + printk(KERN_INFO "attach tuner input %d adr %02x\n", + input->nr, tunerconf->addr); + + feconf->tuner_init = ctl->tuner_init; + feconf->tuner_sleep = ctl->tuner_sleep; + feconf->tuner_set_mode = ctl->tuner_set_mode; + feconf->tuner_set_frequency = ctl->tuner_set_frequency; + feconf->tuner_get_frequency = ctl->tuner_get_frequency; + feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; + feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; + feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; + feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; + feconf->tuner_set_refclk = ctl->tuner_set_refclk; + feconf->tuner_get_status = ctl->tuner_get_status; + + return 0; +} + +static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, + int (*start_feed)(struct dvb_demux_feed *), + int (*stop_feed)(struct dvb_demux_feed *), + void *priv) +{ + dvbdemux->priv = priv; + + dvbdemux->filternum = 256; + dvbdemux->feednum = 256; + dvbdemux->start_feed = start_feed; + dvbdemux->stop_feed = stop_feed; + dvbdemux->write_to_decoder = NULL; + dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | + DMX_SECTION_FILTERING | + DMX_MEMORY_BASED_FILTERING); + return dvb_dmx_init(dvbdemux); +} + +static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, + struct dvb_demux *dvbdemux, + struct dmx_frontend *hw_frontend, + struct dmx_frontend *mem_frontend, + struct dvb_adapter *dvb_adapter) +{ + int ret; + + dmxdev->filternum = 256; + dmxdev->demux = &dvbdemux->dmx; + dmxdev->capabilities = 0; + ret = dvb_dmxdev_init(dmxdev, dvb_adapter); + if (ret < 0) + return ret; + + hw_frontend->source = DMX_FRONTEND_0; + dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); + mem_frontend->source = DMX_MEMORY_FE; + dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); + return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); +} + +static int start_input(struct ddb_input *input) +{ + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + + if (!dvb->users) + ddb_input_start_all(input); + + return ++dvb->users; +} + +static int stop_input(struct ddb_input *input) +{ + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + + if (--dvb->users) + return dvb->users; + + ddb_input_stop_all(input); + return 0; +} + +static int start_feed(struct dvb_demux_feed *dvbdmxfeed) +{ + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct ddb_input *input = dvbdmx->priv; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + + if (!dvb->users) + ddb_input_start_all(input); + + return ++dvb->users; +} + +static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) +{ + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct ddb_input *input = dvbdmx->priv; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + + if (--dvb->users) + return dvb->users; + + ddb_input_stop_all(input); + return 0; +} + +static void dvb_input_detach(struct ddb_input *input) +{ + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_demux *dvbdemux = &dvb->demux; + + switch (dvb->attached) { + case 0x31: + if (dvb->fe2) + dvb_unregister_frontend(dvb->fe2); + if (dvb->fe) + dvb_unregister_frontend(dvb->fe); + case 0x30: + dvb_frontend_detach(dvb->fe); + dvb->fe = dvb->fe2 = NULL; +#ifdef DVB_NETSTREAM + case 0x21: + dvb_netstream_release(&dvb->dvbns); +#endif + case 0x20: + dvb_net_release(&dvb->dvbnet); + case 0x11: + dvbdemux->dmx.close(&dvbdemux->dmx); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, + &dvb->hw_frontend); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, + &dvb->mem_frontend); + dvb_dmxdev_release(&dvb->dmxdev); + case 0x10: + dvb_dmx_release(&dvb->demux); + case 0x01: + break; + } + dvb->attached = 0x00; +} + +static int dvb_register_adapters(struct ddb *dev) +{ + int i, ret = 0; + struct ddb_port *port; + struct dvb_adapter *adap; + + if (adapter_alloc == 3 || dev->info->type == DDB_MOD) { + port = &dev->port[0]; + adap = port->dvb[0].adap; + ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, + port->dev->dev, + adapter_nr); + if (ret < 0) + return ret; + port->dvb[0].adap_registered = 1; + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + port->dvb[0].adap = adap; + port->dvb[1].adap = adap; + } + return 0; + } + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + switch (port->class) { + case DDB_PORT_TUNER: + adap = port->dvb[0].adap; + ret = dvb_register_adapter(adap, "DDBridge", + THIS_MODULE, + port->dev->dev, + adapter_nr); + if (ret < 0) + return ret; + port->dvb[0].adap_registered = 1; + + if (adapter_alloc > 0) { + port->dvb[1].adap = port->dvb[0].adap; + break; + } + adap = port->dvb[1].adap; + ret = dvb_register_adapter(adap, "DDBridge", + THIS_MODULE, + port->dev->dev, + adapter_nr); + if (ret < 0) + return ret; + port->dvb[1].adap_registered = 1; + break; + + case DDB_PORT_CI: + case DDB_PORT_LOOP: + adap = port->dvb[0].adap; + ret = dvb_register_adapter(adap, "DDBridge", + THIS_MODULE, + port->dev->dev, + adapter_nr); + if (ret < 0) + return ret; + port->dvb[0].adap_registered = 1; + break; + default: + if (adapter_alloc < 2) + break; + adap = port->dvb[0].adap; + ret = dvb_register_adapter(adap, "DDBridge", + THIS_MODULE, + port->dev->dev, + adapter_nr); + if (ret < 0) + return ret; + port->dvb[0].adap_registered = 1; + break; + } + } + return ret; +} + +static void dvb_unregister_adapters(struct ddb *dev) +{ + int i; + struct ddb_port *port; + struct ddb_dvb *dvb; + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + + dvb = &port->dvb[0]; + if (dvb->adap_registered) + dvb_unregister_adapter(dvb->adap); + dvb->adap_registered = 0; + + dvb = &port->dvb[1]; + if (dvb->adap_registered) + dvb_unregister_adapter(dvb->adap); + dvb->adap_registered = 0; + } +} + +static int dvb_input_attach(struct ddb_input *input) +{ + int ret = 0; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct ddb_port *port = input->port; + struct dvb_adapter *adap = dvb->adap; + struct dvb_demux *dvbdemux = &dvb->demux; + + dvb->attached = 0x01; + + ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", + start_feed, + stop_feed, input); + if (ret < 0) + return ret; + dvb->attached = 0x10; + + ret = my_dvb_dmxdev_ts_card_init(&dvb->dmxdev, + &dvb->demux, + &dvb->hw_frontend, + &dvb->mem_frontend, adap); + if (ret < 0) + return ret; + dvb->attached = 0x11; + + ret = dvb_net_init(adap, &dvb->dvbnet, dvb->dmxdev.demux); + if (ret < 0) + return ret; + dvb->attached = 0x20; + +#ifdef DVB_NETSTREAM + ret = netstream_init(input); + if (ret < 0) + return ret; + dvb->attached = 0x21; +#endif + dvb->fe = dvb->fe2 = 0; + switch (port->type) { + case DDB_TUNER_DVBS_ST: + if (demod_attach_stv0900(input, 0) < 0) + return -ENODEV; + if (tuner_attach_stv6110(input, 0) < 0) + return -ENODEV; + break; + case DDB_TUNER_DVBS_ST_AA: + if (demod_attach_stv0900(input, 1) < 0) + return -ENODEV; + if (tuner_attach_stv6110(input, 1) < 0) + return -ENODEV; + break; +#ifdef CONFIG_DVB_DRXK + case DDB_TUNER_DVBCT_TR: + if (demod_attach_drxk(input) < 0) + return -ENODEV; + if (tuner_attach_tda18271(input) < 0) + return -ENODEV; + break; +#endif + case DDB_TUNER_DVBCT_ST: + if (demod_attach_stv0367dd(input) < 0) + return -ENODEV; + if (tuner_attach_tda18212dd(input) < 0) + return -ENODEV; + break; + case DDB_TUNER_DVBCT2_SONY: + case DDB_TUNER_DVBC2T2_SONY: + case DDB_TUNER_ISDBT_SONY: + if (demod_attach_cxd2843(input) < 0) + return -ENODEV; + if (tuner_attach_tda18212dd(input) < 0) + return -ENODEV; + break; + default: + return 0; + } + dvb->attached = 0x30; + if (dvb->fe) { + if (dvb_register_frontend(adap, dvb->fe) < 0) + return -ENODEV; + } + if (dvb->fe2) { + if (dvb_register_frontend(adap, dvb->fe2) < 0) + return -ENODEV; + dvb->fe2->tuner_priv = dvb->fe->tuner_priv; + memcpy(&dvb->fe2->ops.tuner_ops, + &dvb->fe->ops.tuner_ops, + sizeof(struct dvb_tuner_ops)); + } + dvb->attached = 0x31; + return 0; +} + + +static int port_has_encti(struct ddb_port *port) +{ + u8 val; + int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val); + + if (!ret) + printk("[0x20]=0x%02x\n", val); + + return ret ? 0 : 1; +} + +static int port_has_cxd_old(struct ddb_port *port) +{ + u8 val; + return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; +} + +static int port_has_cxd(struct ddb_port *port) +{ + u8 val; + u8 probe[4] = { 0xe0, 0x00, 0x00, 0x00 }, data[4]; + struct i2c_msg msgs[2] = {{ .addr = 0x40, .flags = 0, + .buf = probe, .len = 4 }, + { .addr = 0x40, .flags = I2C_M_RD, + .buf = data, .len = 4 }}; + val = i2c_transfer(&port->i2c->adap, msgs, 2); + if (val != 2) + return 0; + + if (data[0] == 0x02 && data[1] == 0x2b && data[3] == 0x43) + return 2; + return 1; +} + +static int port_has_mach(struct ddb_port *port, u8 *id) +{ + u8 val; + u8 probe[1] = { 0x00 }, data[4]; + struct i2c_msg msgs[2] = {{ .addr = 0x10, .flags = 0, + .buf = probe, .len = 1 }, + { .addr = 0x10, .flags = I2C_M_RD, + .buf = data, .len = 4 }}; + val = i2c_transfer(&port->i2c->adap, msgs, 2); + if (val != 2) + return 0; + + if (data[0] != 'D' || data[1] != 'F') + return 0; + + *id = data[2]; + return 1; +} + +static int port_has_stv0900(struct ddb_port *port) +{ + u8 val; + if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) + return 0; + return 1; +} + +static int port_has_stv0900_aa(struct ddb_port *port) +{ + u8 val; + if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) + return 0; + return 1; +} + +static int port_has_drxks(struct ddb_port *port) +{ + u8 val; + if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) + return 0; + if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) + return 0; + return 1; +} + +static int port_has_stv0367(struct ddb_port *port) +{ + u8 val; + + if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0) + return 0; + if (val != 0x60) + return 0; + if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0) + return 0; + if (val != 0x60) + return 0; + return 1; +} + +static int init_xo2_old(struct ddb_port *port) +{ + struct i2c_adapter *i2c =&port->i2c->adap; + u8 val; + int res; + + res = i2c_read_reg(i2c, 0x10, 0x04, &val); + if (res < 0) + return res; + + if (val != 0x02) { + printk(KERN_INFO "Port %d: invalid XO2\n", port->nr); + return -1; + } + + /* Disable XO2 I2C master */ + i2c_write_reg(i2c, 0x10, 0xc0, 0x00); + + i2c_read_reg(i2c, 0x10, 0x08, &val); + if (val != 0) { + i2c_write_reg(i2c, 0x10, 0x08, 0x00); + msleep(100); + } + /* Enable tuner power, disable pll, reset demods */ + i2c_write_reg(i2c, 0x10, 0x08, 0x04); + msleep(2); + /* Release demod resets */ + i2c_write_reg(i2c, 0x10, 0x08, 0x07); + msleep(2); + /* Start XO2 PLL */ + i2c_write_reg(i2c, 0x10, 0x08, 0x87); + + return 0; +} + +static int init_xo2(struct ddb_port *port) +{ + struct i2c_adapter *i2c =&port->i2c->adap; + u8 val, data[2]; + int res; + + res = i2c_read_regs(i2c, 0x10, 0x04, data, 2); + if (res < 0) + return res; + + if (data[0] != 0x01) { + printk(KERN_INFO "Port %d: invalid XO2\n", port->nr); + return -1; + } + + i2c_read_reg(i2c, 0x10, 0x08, &val); + if (val != 0) { + i2c_write_reg(i2c, 0x10, 0x08, 0x00); + msleep(100); + } + /* Enable tuner power, disable pll, reset demods */ + i2c_write_reg(i2c, 0x10, 0x08, 0x04); + msleep(2); + /* Release demod resets */ + i2c_write_reg(i2c, 0x10, 0x08, 0x07); + msleep(2); + + /* Start XO2 PLL */ + i2c_write_reg(i2c, 0x10, 0x08, 0x87); + + return 0; +} + +static void ddb_port_probe(struct ddb_port *port) +{ + struct ddb *dev = port->dev; + char *modname = "NO MODULE"; + int val; + u8 id; + + port->class = DDB_PORT_NONE; + + if (dev->info->type == DDB_MOD) { + modname = "MOD"; + port->class = DDB_PORT_MOD; + printk(KERN_INFO "Port %d: MOD\n", port->nr); + return; + } + + if (port->nr > 1 && dev->info->type == DDB_OCTOPUS_CI) { + modname = "CI internal"; + port->class = DDB_PORT_CI; + port->type = DDB_CI_INTERNAL; + } else if ((val = port_has_cxd(port)) > 0) { + if (val == 1) { + modname = "CI"; + port->class = DDB_PORT_CI; + port->type = DDB_CI_EXTERNAL_SONY; + ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); + } else { + printk(KERN_INFO "Port %d: Uninitialized DuoFlex\n", port->nr); + return; + } + } else if (port_has_mach(port, &id)) { + char *xo2names[] = { "DUAL DVB-S2", "DUAL DVB-C/T/T2", "DUAL DVB-ISDBT", + "DUAL DVB-C/C2/T/T2", "DUAL ATSC", "DUAL DVB-C/C2/T/T2" }; + + ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); + id >>= 2; + if (id > 5) { + modname = "unknown XO2 DuoFlex"; + } else { + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_XO2 + id; + modname = xo2names[id]; + init_xo2(port); + } + } else if (port_has_stv0900(port)) { + modname = "DUAL DVB-S2"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBS_ST; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_stv0900_aa(port)) { + modname = "DUAL DVB-S2"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBS_ST_AA; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_drxks(port)) { + modname = "DUAL DVB-C/T"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBCT_TR; + ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); + } else if (port_has_stv0367(port)) { + modname = "DUAL DVB-C/T"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBCT_ST; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_encti(port)) { + modname = "ENCTI"; + port->class = DDB_PORT_LOOP; + } else if (port->nr == ts_loop) { + modname = "TS LOOP"; + port->class = DDB_PORT_LOOP; + } + printk(KERN_INFO "Port %d (TAB %d): %s\n", port->nr, port->nr + 1, modname); +} + + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static int wait_ci_ready(struct ddb_ci *ci) +{ + u32 count = 10; + + ndelay(500); + do { + if (ddbreadl(ci->port->dev, + CI_CONTROL(ci->nr)) & CI_READY) + break; + usleep_range(1, 2); + if ((--count) == 0) + return -1; + } while (1); + return 0; +} + +static int read_attribute_mem(struct dvb_ca_en50221 *ca, + int slot, int address) +{ + struct ddb_ci *ci = ca->data; + u32 val, off = (address >> 1) & (CI_BUFFER_SIZE-1); + + if (address > CI_BUFFER_SIZE) + return -1; + ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address, + CI_DO_READ_ATTRIBUTES(ci->nr)); + wait_ci_ready(ci); + val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off); + return val; +} + +static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, + int address, u8 value) +{ + struct ddb_ci *ci = ca->data; + + ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address, + CI_DO_ATTRIBUTE_RW(ci->nr)); + wait_ci_ready(ci); + return 0; +} + +static int read_cam_control(struct dvb_ca_en50221 *ca, + int slot, u8 address) +{ + u32 count = 100; + struct ddb_ci *ci = ca->data; + u32 res; + + ddbwritel(ci->port->dev, CI_READ_CMD | address, + CI_DO_IO_RW(ci->nr)); + ndelay(500); + do { + res = ddbreadl(ci->port->dev, CI_READDATA(ci->nr)); + if (res & CI_READY) + break; + usleep_range(1, 2); + if ((--count) == 0) + return -1; + } while (1); + return (0xff & res); +} + +static int write_cam_control(struct dvb_ca_en50221 *ca, int slot, + u8 address, u8 value) +{ + struct ddb_ci *ci = ca->data; + + ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address, + CI_DO_IO_RW(ci->nr)); + wait_ci_ready(ci); + return 0; +} + +static int slot_reset(struct dvb_ca_en50221 *ca, int slot) +{ + struct ddb_ci *ci = ca->data; + + ddbwritel(ci->port->dev, CI_POWER_ON, + CI_CONTROL(ci->nr)); + msleep(100); + ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM, + CI_CONTROL(ci->nr)); + ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM, + CI_CONTROL(ci->nr)); + udelay(20); + ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON, + CI_CONTROL(ci->nr)); + return 0; +} + +static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) +{ + struct ddb_ci *ci = ca->data; + + ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr)); + msleep(300); + return 0; +} + +static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) +{ + struct ddb_ci *ci = ca->data; + u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); + + ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE, + CI_CONTROL(ci->nr)); + return 0; +} + +static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) +{ + struct ddb_ci *ci = ca->data; + u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); + int stat = 0; + + if (val & CI_CAM_DETECT) + stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; + if (val & CI_CAM_READY) + stat |= DVB_CA_EN50221_POLL_CAM_READY; + return stat; +} + +static struct dvb_ca_en50221 en_templ = { + .read_attribute_mem = read_attribute_mem, + .write_attribute_mem = write_attribute_mem, + .read_cam_control = read_cam_control, + .write_cam_control = write_cam_control, + .slot_reset = slot_reset, + .slot_shutdown = slot_shutdown, + .slot_ts_enable = slot_ts_enable, + .poll_slot_status = poll_slot_status, +}; + +static void ci_attach(struct ddb_port *port) +{ + struct ddb_ci *ci = 0; + + ci = kzalloc(sizeof(*ci), GFP_KERNEL); + if (!ci) + return; + memcpy(&ci->en, &en_templ, sizeof(en_templ)); + ci->en.data = ci; + port->en = &ci->en; + ci->port = port; + ci->nr = port->nr - 2; +} + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + + +struct cxd2099_cfg cxd_cfg = { + .bitrate = 72000, + .adr = 0x40, + .polarity = 1, + .clock_mode = 1, //2, +}; + +static int ddb_ci_attach(struct ddb_port *port) +{ + if (port->type == DDB_CI_EXTERNAL_SONY) { + cxd_cfg.bitrate = ci_bitrate; + port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); + if (!port->en) + return -ENODEV; + dvb_ca_en50221_init(port->dvb[0].adap, + port->en, 0, 1); + } + if (port->type == DDB_CI_INTERNAL) { + ci_attach(port); + if (!port->en) + return -ENODEV; + dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1); + } + return 0; +} + +static int ddb_port_attach(struct ddb_port *port) +{ + int ret = 0; + + switch (port->class) { + case DDB_PORT_TUNER: + ret = dvb_input_attach(port->input[0]); + if (ret < 0) + break; + ret = dvb_input_attach(port->input[1]); + if (ret < 0) + break; + port->input[0]->redi = port->input[0]; + port->input[1]->redi = port->input[1]; + break; + case DDB_PORT_CI: + ret = ddb_ci_attach(port); + if (ret < 0) + break; + case DDB_PORT_LOOP: + ret = dvb_register_device(port->dvb[0].adap, + &port->dvb[0].dev, + &dvbdev_ci, (void *) port->output, + DVB_DEVICE_CI); + break; + case DDB_PORT_MOD: + ret = dvb_register_device(port->dvb[0].adap, + &port->dvb[0].dev, + &dvbdev_mod, (void *) port->output, + DVB_DEVICE_MOD); + break; + default: + break; + } + if (ret < 0) + printk(KERN_ERR "port_attach on port %d failed\n", port->nr); + return ret; +} + +static int ddb_ports_attach(struct ddb *dev) +{ + int i, ret = 0; + struct ddb_port *port; + + if (dev->info->port_num) { + ret = dvb_register_adapters(dev); + if (ret < 0) + return ret; + } + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + ret = ddb_port_attach(port); + if (ret < 0) + break; + } + return ret; +} + +static void ddb_ports_detach(struct ddb *dev) +{ + int i; + struct ddb_port *port; + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + + switch (port->class) { + case DDB_PORT_TUNER: + dvb_input_detach(port->input[0]); + dvb_input_detach(port->input[1]); + break; + case DDB_PORT_CI: + case DDB_PORT_LOOP: + if (port->dvb[0].dev) + dvb_unregister_device(port->dvb[0].dev); + if (port->en) { + dvb_ca_en50221_release(port->en); + kfree(port->en); + port->en = 0; + } + break; + case DDB_PORT_MOD: + if (port->dvb[0].dev) + dvb_unregister_device(port->dvb[0].dev); + break; + } + } + dvb_unregister_adapters(dev); +} + + +/* Copy input DMA pointers to output DMA and ACK. */ + +static void input_write_output(struct ddb_input *input, + struct ddb_output *output) +{ + ddbwritel(output->port->dev, + input->dma->stat, DMA_BUFFER_ACK(output->dma->nr)); + output->dma->cbuf = (input->dma->stat >> 11) & 0x1f; + output->dma->coff = (input->dma->stat & 0x7ff) << 7; +} + +static void output_ack_input(struct ddb_output *output, + struct ddb_input *input) +{ + ddbwritel(input->port->dev, + output->dma->stat, DMA_BUFFER_ACK(input->dma->nr)); +} + +static void input_write_dvb(struct ddb_input *input, + struct ddb_input *input2) +{ + struct ddb_dvb *dvb = &input2->port->dvb[input2->nr & 1]; + struct ddb_dma *dma, *dma2; + struct ddb *dev = input->port->dev; + int noack = 0; + + dma = dma2 = input->dma; + /* if there also is an output connected, do not ACK. + input_write_output will ACK. */ + if (input->redo) { + dma2 = input->redo->dma; + noack = 1; + } + while (dma->cbuf != ((dma->stat >> 11) & 0x1f) + || (4 & dma->ctrl)) { + if (4 & dma->ctrl) { + //printk(KERN_ERR "Overflow dma %d\n", dma->nr); + if (noack) + noack = 0; + } +#ifdef DDB_ALT_DMA + dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf], + dma2->size, DMA_FROM_DEVICE); +#endif + dvb_dmx_swfilter_packets(&dvb->demux, + dma2->vbuf[dma->cbuf], + dma2->size / 188); + dma->cbuf = (dma->cbuf + 1) % dma2->num; + if (!noack) + ddbwritel(dev, (dma->cbuf << 11), + DMA_BUFFER_ACK(dma->nr)); + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + } +} + +#ifdef DDB_USE_WORK +static void input_work(struct work_struct *work) +{ + struct ddb_dma *dma = container_of(work, struct ddb_dma, work); + struct ddb_input *input = (struct ddb_input *) dma->io; +#else +static void input_tasklet(unsigned long data) +{ + struct ddb_input *input = (struct ddb_input *) data; + struct ddb_dma *dma = input->dma; +#endif + struct ddb *dev = input->port->dev; + + spin_lock(&dma->lock); + if (!dma->running) { + spin_unlock(&dma->lock); + return; + } + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + + //printk(KERN_ERR "IT %d.%d %08x\n", dev->nr, dma->nr, dma->ctrl); +#if 0 + if (4 & dma->ctrl) + printk(KERN_ERR "Overflow dma %d\n", dma->nr); +#endif + if (input->redi) + input_write_dvb(input, input->redi); + if (input->redo) + input_write_output(input, input->redo); + wake_up(&dma->wq); + spin_unlock(&dma->lock); +} + +static void input_handler(unsigned long data) +{ + struct ddb_input *input = (struct ddb_input *) data; + struct ddb_dma *dma = input->dma; + + + /* If there is no input connected, input_tasklet() will + just copy pointers and ACK. So, there is no need to go + through the tasklet scheduler. */ +#ifdef DDB_USE_WORK + if (input->redi) + queue_work(ddb_wq, &dma->work); + else + input_work(&dma->work); +#else + if (input->redi) + tasklet_schedule(&dma->tasklet); + else + input_tasklet(data); +#endif +} + +/* hmm, don't really need this anymore. + The output IRQ just copies some pointers, acks and wakes. */ + +static void output_work(struct work_struct *work) +{ +} + +static void output_tasklet(unsigned long data) +{ +} + +static void output_handler(unsigned long data) +{ + struct ddb_output *output = (struct ddb_output *) data; + struct ddb_dma *dma = output->dma; + struct ddb *dev = output->port->dev; + + spin_lock(&dma->lock); + if (!dma->running) { + spin_unlock(&dma->lock); + return; + } + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + if (output->redi) + output_ack_input(output, output->redi); + wake_up(&dma->wq); + spin_unlock(&dma->lock); +} + + +/****************************************************************************/ +/****************************************************************************/ + + +static void ddb_dma_init(struct ddb_dma *dma, int nr, void *io, int out) +{ +#ifndef DDB_USE_WORK + unsigned long priv = (unsigned long) io; +#endif + + dma->io = io; + dma->nr = nr; + spin_lock_init(&dma->lock); + init_waitqueue_head(&dma->wq); + if (out) { +#ifdef DDB_USE_WORK + INIT_WORK(&dma->work, output_work); +#else + tasklet_init(&dma->tasklet, output_tasklet, priv); +#endif + dma->num = OUTPUT_DMA_BUFS; + dma->size = OUTPUT_DMA_SIZE; + dma->div = OUTPUT_DMA_IRQ_DIV; + } else { +#ifdef DDB_USE_WORK + INIT_WORK(&dma->work, input_work); +#else + tasklet_init(&dma->tasklet, input_tasklet, priv); +#endif + dma->num = INPUT_DMA_BUFS; + dma->size = INPUT_DMA_SIZE; + dma->div = INPUT_DMA_IRQ_DIV; + } +} + +static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int dma_nr) +{ + struct ddb *dev = port->dev; + struct ddb_input *input = &dev->input[nr]; + + if (dev->has_dma) { + dev->handler[dma_nr + 8] = input_handler; + dev->handler_data[dma_nr + 8] = (unsigned long) input; + } + port->input[pnr] = input; + input->nr = nr; + input->port = port; + if (dev->has_dma) { + input->dma = &dev->dma[dma_nr]; + ddb_dma_init(input->dma, dma_nr, (void *) input, 0); + } + ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); + ddbwritel(dev, 2, TS_INPUT_CONTROL(nr)); + ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); + if (dev->has_dma) + ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); +} + +static void ddb_output_init(struct ddb_port *port, int nr, int dma_nr) +{ + struct ddb *dev = port->dev; + struct ddb_output *output = &dev->output[nr]; + + if (dev->has_dma) { + dev->handler[dma_nr + 8] = output_handler; + dev->handler_data[dma_nr + 8] = (unsigned long) output; + } + port->output = output; + output->nr = nr; + output->port = port; + if (dev->has_dma) { + output->dma = &dev->dma[dma_nr]; + ddb_dma_init(output->dma, dma_nr, (void *) output, 1); + } + if (output->port->class == DDB_PORT_MOD) { + //ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); + } else { + ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); + ddbwritel(dev, 2, TS_OUTPUT_CONTROL(nr)); + ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); + } + if (dev->has_dma) + ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); +} + +static void ddb_ports_init(struct ddb *dev) +{ + int i; + struct ddb_port *port; + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + port->dev = dev; + port->nr = i; + port->i2c = &dev->i2c[i]; + port->gap = 4; + port->obr = ci_bitrate; + mutex_init(&port->i2c_gate_lock); + ddb_port_probe(port); + port->dvb[0].adap = &dev->adap[2 * i]; + port->dvb[1].adap = &dev->adap[2 * i + 1]; + + if ((dev->info->type == DDB_OCTOPUS_CI) || + (dev->info->type == DDB_OCTONET) || + (dev->info->type == DDB_OCTOPUS)) { + if (i >= 2 && dev->info->type == DDB_OCTOPUS_CI) { + ddb_input_init(port, 2 + i, 0, 2 + i); + ddb_input_init(port, 4 + i, 1, 4 + i); + } else { + ddb_input_init(port, 2 * i, 0, 2 * i); + ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1); + } + ddb_output_init(port, i, i + 8); + } + if (dev->info->type == DDB_MOD) { + ddb_output_init(port, i, i); + dev->handler[i + 18] = ddbridge_mod_rate_handler; + dev->handler_data[i + 18] = + (unsigned long) &dev->output[i]; + } + } +} + +static void ddb_ports_release(struct ddb *dev) +{ + int i; + struct ddb_port *port; + + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; +#ifdef DDB_USE_WORK + if (port->input[0]) + cancel_work_sync(&port->input[0]->dma->work); + if (port->input[1]) + cancel_work_sync(&port->input[1]->dma->work); + if (port->output) + cancel_work_sync(&port->output->dma->work); +#else + if (port->input[0]) + tasklet_kill(&port->input[0]->dma->tasklet); + if (port->input[1]) + tasklet_kill(&port->input[1]->dma->tasklet); + if (port->output) + tasklet_kill(&port->output->dma->tasklet); +#endif + } +} + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +#define IRQ_HANDLE(_nr) if ((s & (1UL << _nr)) && dev->handler[_nr]) \ + dev->handler[_nr](dev->handler_data[_nr]); + +static void irq_handle_msg(struct ddb *dev, u32 s) +{ + dev->i2c_irq++; + IRQ_HANDLE(0); + IRQ_HANDLE(1); + IRQ_HANDLE(2); + IRQ_HANDLE(3); +} + +static void irq_handle_io(struct ddb *dev, u32 s) +{ + dev->ts_irq++; + IRQ_HANDLE(8); + IRQ_HANDLE(9); + IRQ_HANDLE(10); + IRQ_HANDLE(11); + IRQ_HANDLE(12); + IRQ_HANDLE(13); + IRQ_HANDLE(14); + IRQ_HANDLE(15); + IRQ_HANDLE(16); + IRQ_HANDLE(17); + IRQ_HANDLE(18); + IRQ_HANDLE(19); + if (dev->info->type != DDB_MOD) + return; + IRQ_HANDLE(20); + IRQ_HANDLE(21); + IRQ_HANDLE(22); + IRQ_HANDLE(23); + IRQ_HANDLE(24); + IRQ_HANDLE(25); + IRQ_HANDLE(26); + IRQ_HANDLE(27); +} + +static irqreturn_t irq_handler0(int irq, void *dev_id) +{ + struct ddb *dev = (struct ddb *) dev_id; + u32 s = ddbreadl(dev, INTERRUPT_STATUS); + + do { + if (s & 0x80000000) + return IRQ_NONE; + if (!(s & 0xfff00)) + return IRQ_NONE; + ddbwritel(dev, s, INTERRUPT_ACK); + irq_handle_io(dev, s); + } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); + + return IRQ_HANDLED; +} + +static irqreturn_t irq_handler1(int irq, void *dev_id) +{ + struct ddb *dev = (struct ddb *) dev_id; + u32 s = ddbreadl(dev, INTERRUPT_STATUS); + + do { + if (s & 0x80000000) + return IRQ_NONE; + if (!(s & 0x0000f)) + return IRQ_NONE; + ddbwritel(dev, s, INTERRUPT_ACK); + irq_handle_msg(dev, s); + } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); + + return IRQ_HANDLED; +} + +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + struct ddb *dev = (struct ddb *) dev_id; + u32 s = ddbreadl(dev, INTERRUPT_STATUS); + int ret = IRQ_HANDLED; + + if (!s) + return IRQ_NONE; + do { + if (s & 0x80000000) + return IRQ_NONE; + ddbwritel(dev, s, INTERRUPT_ACK); + + if (s & 0x0000000f) + irq_handle_msg(dev, s); + if (s & 0x0fffff00) { + irq_handle_io(dev, s); +#ifdef DDB_TEST_THREADED + ret = IRQ_WAKE_THREAD; +#endif + } + } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); + + return ret; +} + +static irqreturn_t irq_thread(int irq, void *dev_id) +{ + struct ddb *dev = (struct ddb *) dev_id; + + //printk("%s\n", __func__); + + return IRQ_HANDLED; +} + + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static ssize_t nsd_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ + return 0; +} + +static unsigned int nsd_poll(struct file *file, poll_table *wait) +{ + return 0; +} + +static int nsd_release(struct inode *inode, struct file *file) +{ + return dvb_generic_release(inode, file); +} + +static int nsd_open(struct inode *inode, struct file *file) +{ + return dvb_generic_open(inode, file); +} + +static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb *dev = dvbdev->priv; + + unsigned long arg = (unsigned long) parg; + int ret = 0; + + switch (cmd) { + case NSD_START_GET_TS: + { + struct dvb_nsd_ts *ts = parg; + u32 ctrl = ((ts->input & 7) << 8) | (ts->filter_mask << 2); + u32 to; + int i; + + if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) { + printk("ts capture busy\n"); + return -EBUSY; + } + ddb_dvb_input_start(&dev->input[ts->input & 7]); + + ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL); + ddbwritel(dev, ts->pid, TS_CAPTURE_PID); + ddbwritel(dev, (ts->section_id << 16) | (ts->table << 8) | ts->section, + TS_CAPTURE_TABLESECTION); + /* 1024 ms default timeout if timeout set to 0 */ + if (ts->timeout) + to = ts->timeout; + else + to = 1024; + /* 21 packets default if num set to 0 */ + if (ts->num) + to |= ((u32) ts->num << 16); + else + to |= (21 << 16); + ddbwritel(dev, to, TS_CAPTURE_TIMEOUT); + if (ts->mode) + ctrl |= 2; + ddbwritel(dev, ctrl | 1, TS_CAPTURE_CONTROL); + +#if 0 + for (i = 0; i < (ts->timeout / 100); i++) { + if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) + msleep(100); + else + break; + } + //printk("ts capture done %d\n", i); + if ((ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) || + (ddbreadl(dev, TS_CAPTURE_CONTROL) & (1 << 14))) { + //printk("ts capture timeout\n"); + ddb_dvb_input_stop(&dev->input[ts->input & 7]); + return -EAGAIN; + } + ddb_dvb_input_stop(&dev->input[ts->input & 7]); + ddbcpyfrom(dev, dev->tsbuf, TS_CAPTURE_MEMORY, TS_CAPTURE_LEN); + ts->len = ddbreadl(dev, TS_CAPTURE_RECEIVED) & 0xfff; + ret = copy_to_user(ts->ts, dev->tsbuf, ts->len); + if (ret < 0) + return ret; +#endif + break; + } + case NSD_POLL_GET_TS: + { + struct dvb_nsd_ts *ts = parg; + u32 ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL); + + if (ctrl & 1) { + return -EBUSY; + } + if (ctrl & (1 << 14)) { + //printk("ts capture timeout\n"); + return -EAGAIN; + } + ddbcpyfrom(dev, dev->tsbuf, TS_CAPTURE_MEMORY, TS_CAPTURE_LEN); + ts->len = ddbreadl(dev, TS_CAPTURE_RECEIVED) & 0xfff; + if (copy_to_user(ts->ts, dev->tsbuf, ts->len) < 0) + return -EIO; + break; + } + case NSD_CANCEL_GET_TS: + { + u32 ctrl = 0; + printk("cancel ts capture: 0x%x\n", ctrl); + ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL); + ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL); + //printk("control register is 0x%x\n", ctrl); + break; + } + case NSD_STOP_GET_TS: + { + struct dvb_nsd_ts *ts = parg; + if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) { + printk("cannot stop ts capture, while it was neither finished not canceled\n"); + return -EBUSY; + } + //printk("ts capture stopped\n"); + ddb_dvb_input_stop(&dev->input[ts->input & 7]); + break; + } + default: + ret = -EINVAL; + break; + } + return ret; +} + +static long nsd_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return dvb_usercopy(file, cmd, arg, nsd_do_ioctl); +} + +static const struct file_operations nsd_fops = { + .owner = THIS_MODULE, + .read = nsd_read, + .open = nsd_open, + .release = nsd_release, + .poll = nsd_poll, + .unlocked_ioctl = nsd_ioctl, +}; + +static struct dvb_device dvbdev_nsd = { + .priv = 0, + .readers = 1, + .writers = 1, + .users = 1, + .fops = &nsd_fops, +}; + +static int ddb_nsd_attach(struct ddb *dev) +{ + int ret; + + ret = dvb_register_device(&dev->adap[0], + &dev->nsd_dev, + &dvbdev_nsd, (void *) dev, + DVB_DEVICE_NSD); + return ret; +} + +static void ddb_nsd_detach(struct ddb *dev) +{ + if (dev->nsd_dev->users > 2) { + wait_event(dev->nsd_dev->wait_queue, + dev->nsd_dev->users == 2); + } + dvb_unregister_device(dev->nsd_dev); +} + + +/******************************************************************************/ +/******************************************************************************/ +/******************************************************************************/ + +static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) +{ + u32 data, shift; + + if (wlen > 4) + ddbwritel(dev, 1, SPI_CONTROL); + while (wlen > 4) { + /* FIXME: check for big-endian */ + data = swab32(*(u32 *)wbuf); + wbuf += 4; + wlen -= 4; + ddbwritel(dev, data, SPI_DATA); + while (ddbreadl(dev, SPI_CONTROL) & 0x0004) + ; + } + + if (rlen) + ddbwritel(dev, 0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); + else + ddbwritel(dev, 0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); + + data = 0; + shift = ((4 - wlen) * 8); + while (wlen) { + data <<= 8; + data |= *wbuf; + wlen--; + wbuf++; + } + if (shift) + data <<= shift; + ddbwritel(dev, data, SPI_DATA); + while (ddbreadl(dev, SPI_CONTROL) & 0x0004) + ; + + if (!rlen) { + ddbwritel(dev, 0, SPI_CONTROL); + return 0; + } + if (rlen > 4) + ddbwritel(dev, 1, SPI_CONTROL); + + while (rlen > 4) { + ddbwritel(dev, 0xffffffff, SPI_DATA); + while (ddbreadl(dev, SPI_CONTROL) & 0x0004) + ; + data = ddbreadl(dev, SPI_DATA); + *(u32 *) rbuf = swab32(data); + rbuf += 4; + rlen -= 4; + } + ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); + ddbwritel(dev, 0xffffffff, SPI_DATA); + while (ddbreadl(dev, SPI_CONTROL) & 0x0004) + ; + + data = ddbreadl(dev, SPI_DATA); + ddbwritel(dev, 0, SPI_CONTROL); + + if (rlen < 4) + data <<= ((4 - rlen) * 8); + + while (rlen > 0) { + *rbuf = ((data >> 24) & 0xff); + data <<= 8; + rbuf++; + rlen--; + } + return 0; +} + +int ddbridge_flashread(struct ddb *dev, u8 *buf, u32 addr, u32 len) +{ + u8 cmd[4] = {0x03, (addr >> 16) & 0xff, + (addr >> 8) & 0xff, addr & 0xff}; + + return flashio(dev, cmd, 4, buf, len); +} + +static int mdio_write(struct ddb *dev, u8 adr, u8 reg, u16 val) +{ + ddbwritel(dev, adr, MDIO_ADR); + ddbwritel(dev, reg, MDIO_REG); + ddbwritel(dev, val, MDIO_VAL); + ddbwritel(dev, 0x03, MDIO_CTRL); + while (ddbreadl(dev, MDIO_CTRL) & 0x02); + return 0; +} + +static u16 mdio_read(struct ddb *dev, u8 adr, u8 reg) +{ + ddbwritel(dev, adr, MDIO_ADR); + ddbwritel(dev, reg, MDIO_REG); + ddbwritel(dev, 0x07, MDIO_CTRL); + while (ddbreadl(dev, MDIO_CTRL) & 0x02); + return ddbreadl(dev, MDIO_VAL); +} + +#define DDB_MAGIC 'd' + +struct ddb_flashio { + __u8 *write_buf; + __u32 write_len; + __u8 *read_buf; + __u32 read_len; +}; + +struct ddb_gpio { + __u32 mask; + __u32 data; +}; + +struct ddb_id { + __u16 vendor; + __u16 device; + __u16 subvendor; + __u16 subdevice; + __u32 hw; + __u32 regmap; +}; + +struct ddb_reg { + __u32 reg; + __u32 val; +}; + +struct ddb_mem { + __u32 off; + __u8 *buf; + __u32 len; +}; + +struct ddb_mdio { + __u8 adr; + __u8 reg; + __u16 val; +}; + +#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) +#define IOCTL_DDB_GPIO_IN _IOWR(DDB_MAGIC, 0x01, struct ddb_gpio) +#define IOCTL_DDB_GPIO_OUT _IOWR(DDB_MAGIC, 0x02, struct ddb_gpio) +#define IOCTL_DDB_ID _IOR(DDB_MAGIC, 0x03, struct ddb_id) +#define IOCTL_DDB_READ_REG _IOWR(DDB_MAGIC, 0x04, struct ddb_reg) +#define IOCTL_DDB_WRITE_REG _IOW(DDB_MAGIC, 0x05, struct ddb_reg) +#define IOCTL_DDB_READ_MEM _IOWR(DDB_MAGIC, 0x06, struct ddb_mem) +#define IOCTL_DDB_WRITE_MEM _IOR(DDB_MAGIC, 0x07, struct ddb_mem) +#define IOCTL_DDB_READ_MDIO _IOWR(DDB_MAGIC, 0x08, struct ddb_mdio) +#define IOCTL_DDB_WRITE_MDIO _IOR(DDB_MAGIC, 0x09, struct ddb_mdio) + +#define DDB_NAME "ddbridge" + +static u32 ddb_num; +static int ddb_major; +static DEFINE_MUTEX(ddb_mutex); + +static int ddb_release(struct inode *inode, struct file *file) +{ + struct ddb *dev = file->private_data; + + dev->ddb_dev_users--; + return 0; +} + +static int ddb_open(struct inode *inode, struct file *file) +{ + struct ddb *dev = ddbs[iminor(inode)]; + + if (dev->ddb_dev_users) + return -EBUSY; + dev->ddb_dev_users++; + file->private_data = dev; + return 0; +} + +static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct ddb *dev = file->private_data; + void *parg = (void *)arg; + int res; + + switch (cmd) { + case IOCTL_DDB_FLASHIO: + { + struct ddb_flashio fio; + u8 *rbuf, *wbuf; + + if (copy_from_user(&fio, parg, sizeof(fio))) + return -EFAULT; + + if (fio.write_len > 1028 || fio.read_len > 1028) + return -EINVAL; + if (fio.write_len + fio.read_len > 1028) + return -EINVAL; + + wbuf = &dev->iobuf[0]; + rbuf = wbuf + fio.write_len; + + if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) + return -EFAULT; + res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len); + if (res) + return res; + if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) + return -EFAULT; + break; + } + case IOCTL_DDB_GPIO_OUT: + { + struct ddb_gpio gpio; + if (copy_from_user(&gpio, parg, sizeof(gpio))) + return -EFAULT; + ddbwritel(dev, gpio.mask, GPIO_DIRECTION); + ddbwritel(dev, gpio.data, GPIO_OUTPUT); + break; + } + case IOCTL_DDB_ID: + { + struct ddb_id ddbid; + + ddbid.vendor = dev->id->vendor; + ddbid.device = dev->id->device; + ddbid.subvendor = dev->id->subvendor; + ddbid.subdevice = dev->id->subdevice; + ddbid.hw = ddbreadl(dev, 0); + ddbid.regmap = ddbreadl(dev, 4); + if (copy_to_user(parg, &ddbid, sizeof(ddbid))) + return -EFAULT; + break; + } + case IOCTL_DDB_READ_REG: + { + struct ddb_reg reg; + + if (copy_from_user(®, parg, sizeof(reg))) + return -EFAULT; + if (reg.reg >= dev->regs_len) + return -EINVAL; + reg.val = ddbreadl(dev, reg.reg); + if (copy_to_user(parg, ®, sizeof(reg))) + return -EFAULT; + break; + } + case IOCTL_DDB_WRITE_REG: + { + struct ddb_reg reg; + + if (copy_from_user(®, parg, sizeof(reg))) + return -EFAULT; + if (reg.reg >= dev->regs_len) + return -EINVAL; + ddbwritel(dev, reg.val, reg.reg); + break; + } + case IOCTL_DDB_READ_MDIO: + { + struct ddb_mdio mdio; + + if (copy_from_user(&mdio, parg, sizeof(mdio))) + return -EFAULT; + mdio.val = mdio_read(dev, mdio.adr, mdio.reg); + if (copy_to_user(parg, &mdio, sizeof(mdio))) + return -EFAULT; + break; + } + case IOCTL_DDB_WRITE_MDIO: + { + struct ddb_mdio mdio; + + if (copy_from_user(&mdio, parg, sizeof(mdio))) + return -EFAULT; + mdio_write(dev, mdio.adr, mdio.reg, mdio.val); + break; + } + case IOCTL_DDB_READ_MEM: + { + struct ddb_mem mem; + u8 *buf = &dev->iobuf[0]; + + if (copy_from_user(&mem, parg, sizeof(mem))) + return -EFAULT; + if ((mem.len + mem.off > dev->regs_len) || + mem.len > 1024) + return -EINVAL; + ddbcpyfrom(dev, buf, mem.off, mem.len); + if (copy_to_user(mem.buf, buf, mem.len)) + return -EFAULT; + break; + } + case IOCTL_DDB_WRITE_MEM: + { + struct ddb_mem mem; + u8 *buf = &dev->iobuf[0]; + + if (copy_from_user(&mem, parg, sizeof(mem))) + return -EFAULT; + if ((mem.len + mem.off > dev->regs_len) || + mem.len > 1024) + return -EINVAL; + if (copy_from_user(buf, mem.buf, mem.len)) + return -EFAULT; + ddbcpyto(dev, mem.off, buf, mem.len); + break; + } + default: + return -ENOTTY; + } + return 0; +} + +static const struct file_operations ddb_fops = { + .unlocked_ioctl = ddb_ioctl, + .open = ddb_open, + .release = ddb_release, +}; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) +static char *ddb_devnode(struct device *device, mode_t *mode) +#else +static char *ddb_devnode(struct device *device, umode_t *mode) +#endif +{ + struct ddb *dev = dev_get_drvdata(device); + + return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); +} + +#define __ATTR_MRO(_name, _show) { \ + .attr = { .name = __stringify(_name), .mode = 0444 }, \ + .show = _show, \ +} + +#define __ATTR_MWO(_name, _store) { \ + .attr = { .name = __stringify(_name), .mode = 0222 }, \ + .store = _store, \ +} + +static ssize_t ports_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + + return sprintf(buf, "%d\n", dev->info->port_num); +} + +static ssize_t ts_irq_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + + return sprintf(buf, "%d\n", dev->ts_irq); +} + +static ssize_t i2c_irq_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + + return sprintf(buf, "%d\n", dev->i2c_irq); +} + +static char *class_name[] = { + "NONE", "CI", "TUNER", "LOOP" +}; + +static char *type_name[] = { + "NONE", "DVBS_ST", "DVBS_ST_AA", "DVBCT_TR", "DVBCT_ST", "INTERNAL", "CXD2099", +}; + +static ssize_t fan_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + u32 val; + + val = ddbreadl(dev, GPIO_OUTPUT) & 1; + return sprintf(buf, "%d\n", val); +} + +static ssize_t fan_store(struct device *device, struct device_attribute *d, + const char *buf, size_t count) +{ + struct ddb *dev = dev_get_drvdata(device); + unsigned val; + + if (sscanf(buf, "%u\n", &val) != 1) + return -EINVAL; + ddbwritel(dev, 1, GPIO_DIRECTION); + ddbwritel(dev, val & 1, GPIO_OUTPUT); + return count; +} + +static ssize_t temp_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + struct i2c_adapter *adap; + int temp, temp2; + u8 tmp[2]; + + if (dev->info->type == DDB_MOD) { + ddbwritel(dev, 1, TEMPMON_CONTROL); + msleep(5); + temp = ddbreadl(dev, TEMPMON_SENSOR1); + temp2 = ddbreadl(dev, TEMPMON_SENSOR2); + temp = (temp * 1000) >> 8; + temp2 = (temp2 * 1000) >> 8; + return sprintf(buf, "%d %d\n", temp, temp2); + } + if (!dev->info->temp_num) + return sprintf(buf, "no sensor\n"); + adap = &dev->i2c[dev->info->temp_bus].adap; + if (i2c_read_regs(adap, 0x48, 0, tmp, 2) < 0) + return sprintf(buf, "read_error\n"); + temp = (tmp[0] << 3) | (tmp[1] >> 5); + temp *= 125; + if (dev->info->temp_num == 2) { + if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0) + return sprintf(buf, "read_error\n"); + temp2 = (tmp[0] << 3) | (tmp[1] >> 5); + temp2 *= 125; + return sprintf(buf, "%d %d\n", temp, temp2); + } + return sprintf(buf, "%d\n", temp); +} + +static ssize_t qam_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + struct i2c_adapter *adap; + u8 tmp[4]; + s16 i, q; + + adap = &dev->i2c[1].adap; + if (i2c_read_regs16(adap, 0x1f, 0xf480, tmp, 4) < 0) + return sprintf(buf, "read_error\n"); + i = (s16) (((u16) tmp[1]) << 14) | (((u16) tmp[0]) << 6); + q = (s16) (((u16) tmp[3]) << 14) | (((u16) tmp[2]) << 6); + + return sprintf(buf, "%d %d\n", i, q); +} + +static ssize_t mod_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + + return sprintf(buf, "%s:%s\n", + class_name[dev->port[num].class], + type_name[dev->port[num].type]); +} + +static ssize_t led_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + + return sprintf(buf, "%d\n", dev->leds & (1 << num) ? 1 : 0); +} + + +static void ddb_set_led(struct ddb *dev, int num, int val) +{ + if (!dev->info->led_num) + return; + switch (dev->port[num].class) { + case DDB_PORT_TUNER: + switch (dev->port[num].type) { + case DDB_TUNER_DVBS_ST: + i2c_write_reg16(&dev->i2c[num].adap, + 0x69, 0xf14c, val ? 2 : 0); + break; + case DDB_TUNER_DVBCT_ST: + i2c_write_reg16(&dev->i2c[num].adap, + 0x1f, 0xf00e, 0); + i2c_write_reg16(&dev->i2c[num].adap, + 0x1f, 0xf00f, val ? 1 : 0); + break; + } + break; + default: + break; + } +} + +static ssize_t led_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + unsigned val; + + if (sscanf(buf, "%u\n", &val) != 1) + return -EINVAL; + if (val) + dev->leds |= (1 << num); + else + dev->leds &= ~(1 << num); + ddb_set_led(dev, num, val); + return count; +} + +static ssize_t snr_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + char snr[32]; + int num = attr->attr.name[3] - 0x30; + + /* serial number at 0x100-0x11f */ + if (i2c_read_regs16(&dev->i2c[num].adap, 0x50, 0x100, snr, 32) < 0) + if (i2c_read_regs16(&dev->i2c[num].adap, 0x57, 0x100, snr, 32) < 0) + return sprintf(buf, "NO SNR\n"); + snr[31]=0; /* in case it is not terminated on EEPROM */ + return sprintf(buf, "%s\n", snr); +} + + +static ssize_t snr_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + u8 snr[34] = { 0x01, 0x00 }; + + if (count > 31) + return -EINVAL; + memcpy(snr + 2, buf, count); + i2c_write(&dev->i2c[num].adap, 0x57, snr, 34); + i2c_write(&dev->i2c[num].adap, 0x50, snr, 34); + return count; +} + +static ssize_t bsnr_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + char snr[16]; + + ddbridge_flashread(dev, snr, 0x10, 15); + snr[15]=0; /* in case it is not terminated on EEPROM */ + return sprintf(buf, "%s\n", snr); +} + +static ssize_t redirect_show(struct device *device, struct device_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t redirect_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned int i, p; + int res; + + if (sscanf(buf, "%x %x\n", &i, &p) != 2) + return -EINVAL; + res = ddb_redirect(i, p); + if (res < 0) + return res; + printk(KERN_INFO "redirect: %02x, %02x\n", i, p); + return count; +} + +static ssize_t gap_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + + return sprintf(buf, "%d\n", dev->port[num].gap); + +} +static ssize_t gap_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + unsigned int val; + + if (sscanf(buf, "%u\n", &val) != 1) + return -EINVAL; + if (val > 20) + return -EINVAL; + dev->port[num].gap = val; + return count; +} + +static ssize_t version_show(struct device *device, struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + + return sprintf(buf, "%08x %08x\n", ddbreadl(dev, 0), ddbreadl(dev, 4)); +} + +static ssize_t hwid_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + + return sprintf(buf, "0x%08X\n", dev->hwid); +} + +static ssize_t regmap_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + + return sprintf(buf, "0x%08X\n", dev->regmapid); +} + +static struct device_attribute ddb_attrs[] = { + __ATTR_RO(version), + __ATTR_RO(ports), + __ATTR_RO(ts_irq), + __ATTR_RO(i2c_irq), + __ATTR(gap0, 0666, gap_show, gap_store), + __ATTR(gap1, 0666, gap_show, gap_store), + __ATTR(gap2, 0666, gap_show, gap_store), + __ATTR(gap3, 0666, gap_show, gap_store), + __ATTR_RO(hwid), + __ATTR_RO(regmap), +#if 0 + __ATTR_RO(qam), +#endif + __ATTR(redirect, 0666, redirect_show, redirect_store), + __ATTR_MRO(snr, bsnr_show), + __ATTR_NULL, +}; + +static struct device_attribute ddb_attrs_temp[] = { + __ATTR_RO(temp), +}; + +static struct device_attribute ddb_attrs_mod[] = { + __ATTR_MRO(mod0, mod_show), + __ATTR_MRO(mod1, mod_show), + __ATTR_MRO(mod2, mod_show), + __ATTR_MRO(mod3, mod_show), +}; + +static struct device_attribute ddb_attrs_fan[] = { + __ATTR(fan, 0666, fan_show, fan_store), +}; + +static struct device_attribute ddb_attrs_snr[] = { + __ATTR(snr0, 0666, snr_show, snr_store), + __ATTR(snr1, 0666, snr_show, snr_store), + __ATTR(snr2, 0666, snr_show, snr_store), + __ATTR(snr3, 0666, snr_show, snr_store), +}; + +static struct device_attribute ddb_attrs_led[] = { + __ATTR(led0, 0666, led_show, led_store), + __ATTR(led1, 0666, led_show, led_store), + __ATTR(led2, 0666, led_show, led_store), + __ATTR(led3, 0666, led_show, led_store), +}; + +static struct class ddb_class = { + .name = "ddbridge", + .owner = THIS_MODULE, + .dev_attrs = ddb_attrs, + .devnode = ddb_devnode, +}; + +static int ddb_class_create(void) +{ + ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); + if (ddb_major < 0) + return ddb_major; + if (class_register(&ddb_class) < 0) + return -1; + return 0; +} + +static void ddb_class_destroy(void) +{ + class_unregister(&ddb_class); + unregister_chrdev(ddb_major, DDB_NAME); +} + +static void ddb_device_attrs_del(struct ddb *dev) +{ + int i; + + for (i = 0; i < dev->info->temp_num; i++) + device_remove_file(dev->ddb_dev, &ddb_attrs_temp[0]); + for (i = 0; i < dev->info->port_num; i++) + device_remove_file(dev->ddb_dev, &ddb_attrs_mod[i]); + for (i = 0; i < dev->info->fan_num; i++) + device_remove_file(dev->ddb_dev, &ddb_attrs_fan[0]); + for (i = 0; i < dev->info->i2c_num; i++) { + if (dev->info->led_num) + device_remove_file(dev->ddb_dev, &ddb_attrs_led[i]); + device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]); + } +} + +static int ddb_device_attrs_add(struct ddb *dev) +{ + int i, res = 0; + + for (i = 0; i < dev->info->temp_num; i++) + if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_temp[0]))) + goto fail; + for (i = 0; i < dev->info->port_num; i++) + if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_mod[i]))) + goto fail; + for (i = 0; i < dev->info->fan_num; i++) + if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_fan[0]))) + goto fail; + for (i = 0; i < dev->info->i2c_num; i++) { + if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_snr[i]))) + goto fail; + if (dev->info->led_num) + if ((res = device_create_file(dev->ddb_dev, &ddb_attrs_led[i]))) + goto fail; + } +fail: + return res; +} + +static int ddb_device_create(struct ddb *dev) +{ + int res = 0; + + if (ddb_num == DDB_MAX_ADAPTER) + return -ENOMEM; + mutex_lock(&ddb_mutex); + dev->nr = ddb_num; + ddbs[dev->nr] = dev; + dev->ddb_dev = device_create(&ddb_class, dev->dev, + MKDEV(ddb_major, dev->nr), + dev, "ddbridge%d", dev->nr); + if (IS_ERR(dev->ddb_dev)) { + res = PTR_ERR(dev->ddb_dev); + printk(KERN_INFO "Could not create ddbridge%d\n", dev->nr); + goto fail; + } + res = ddb_device_attrs_add(dev); + if (res) { + ddb_device_attrs_del(dev); + device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); + ddbs[dev->nr] = 0; + dev->ddb_dev = ERR_PTR(-ENODEV); + } else + ddb_num++; +fail: + mutex_unlock(&ddb_mutex); + return res; +} + +static void ddb_device_destroy(struct ddb *dev) +{ + if (IS_ERR(dev->ddb_dev)) + return; + ddb_device_attrs_del(dev); + device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); +} + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,243 @@ +/* + * ddbridge-i2c.c: Digital Devices bridge i2c driver + * + * Copyright (C) 2010-2013 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; + + return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; +} + +static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) +{ + struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 } }; + return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +} + +static int i2c_read_regs(struct i2c_adapter *adapter, + u8 adr, u8 reg, u8 *val, u8 len) +{ + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = ®, .len = 1 }, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = len } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static int i2c_read_regs16(struct i2c_adapter *adapter, + u8 adr, u16 reg, u8 *val, u8 len) +{ + u8 reg16[2] = { reg >> 8, reg }; + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = reg16, .len = 2 }, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = len } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) +{ + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = ®, .len = 1}, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, + u16 reg, u8 *val) +{ + u8 msg[2] = {reg >> 8, reg & 0xff}; + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = msg, .len = 2}, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, + u16 reg, u8 val) +{ + u8 msg[3] = {reg >> 8, reg & 0xff, val}; + + return i2c_write(adap, adr, msg, 3); +} + +static int i2c_write_reg(struct i2c_adapter *adap, u8 adr, + u8 reg, u8 val) +{ + u8 msg[2] = {reg, val}; + + return i2c_write(adap, adr, msg, 2); +} + +static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) +{ + struct ddb *dev = i2c->dev; + int stat; + u32 val; + + //i2c->done = 0; + ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND); + //stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); + stat = wait_for_completion_timeout(&i2c->completion, HZ); + if (stat <= 0) { + printk(KERN_ERR "DDBridge I2C timeout, card %d, port %d\n", + dev->nr, i2c->nr); +#ifdef CONFIG_PCI_MSI + { /* MSI debugging*/ + u32 istat = ddbreadl(dev, INTERRUPT_STATUS); + printk(KERN_ERR "DDBridge IRS %08x\n", istat); + ddbwritel(dev, istat, INTERRUPT_ACK); + } +#endif + return -EIO; + } + val = ddbreadl(dev, i2c->regs + I2C_COMMAND); + if (val & 0x70000) + return -EIO; + return 0; +} + +static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, + struct i2c_msg msg[], int num) +{ + struct ddb_i2c *i2c = (struct ddb_i2c *) i2c_get_adapdata(adapter); + struct ddb *dev = i2c->dev; + u8 addr = 0; + + if (num) + addr = msg[0].addr; + if (num == 2 && msg[1].flags & I2C_M_RD && + !(msg[0].flags & I2C_M_RD)) { + memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, + msg[0].buf, msg[0].len); + ddbwritel(dev, msg[0].len|(msg[1].len << 16), + i2c->regs + I2C_TASKLENGTH); + if (!ddb_i2c_cmd(i2c, addr, 1)) { + memcpy_fromio(msg[1].buf, + dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, + msg[1].len); + return num; + } + } + if (num == 1 && !(msg[0].flags & I2C_M_RD)) { + ddbcpyto(dev, I2C_TASKMEM_BASE + i2c->wbuf, + msg[0].buf, msg[0].len); + ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH); + if (!ddb_i2c_cmd(i2c, addr, 2)) { + return num; + } + } + if (num == 1 && (msg[0].flags & I2C_M_RD)) { + ddbwritel(dev, msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); + if (!ddb_i2c_cmd(i2c, addr, 3)) { + ddbcpyfrom(dev, msg[0].buf, + I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); + return num; + } + } + return -EIO; +} + + +static u32 ddb_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_SMBUS_EMUL; +} + +struct i2c_algorithm ddb_i2c_algo = { + .master_xfer = ddb_i2c_master_xfer, + .functionality = ddb_i2c_functionality, +}; + +static void ddb_i2c_release(struct ddb *dev) +{ + int i; + struct ddb_i2c *i2c; + struct i2c_adapter *adap; + + for (i = 0; i < dev->info->i2c_num; i++) { + i2c = &dev->i2c[i]; + adap = &i2c->adap; + i2c_del_adapter(adap); + } +} + +static void i2c_handler(unsigned long priv) +{ + struct ddb_i2c *i2c = (struct ddb_i2c *) priv; + + //i2c->done = 1; + //wake_up(&i2c->wq); + complete(&i2c->completion); +} + +static int ddb_i2c_init(struct ddb *dev) +{ + int i, j, stat = 0; + struct ddb_i2c *i2c; + struct i2c_adapter *adap; + + for (i = 0; i < dev->info->i2c_num; i++) { + i2c = &dev->i2c[i]; + dev->handler[i] = i2c_handler; + dev->handler_data[i] = (unsigned long) i2c; + i2c->dev = dev; + i2c->nr = i; + i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); + i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); + i2c->regs = 0x80 + i * 0x20; + ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING); + ddbwritel(dev, (i2c->rbuf << 16) | i2c->wbuf, + i2c->regs + I2C_TASKADDRESS); + //init_waitqueue_head(&i2c->wq); + init_completion(&i2c->completion); + + adap = &i2c->adap; + i2c_set_adapdata(adap, i2c); +#ifdef I2C_ADAP_CLASS_TV_DIGITAL + adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; +#else +#ifdef I2C_CLASS_TV_ANALOG + adap->class = I2C_CLASS_TV_ANALOG; +#endif +#endif + strcpy(adap->name, "ddbridge"); + adap->algo = &ddb_i2c_algo; + adap->algo_data = (void *)i2c; + adap->dev.parent = dev->dev; + stat = i2c_add_adapter(adap); + if (stat) + break; + } + if (stat) + for (j = 0; j < i; j++) { + i2c = &dev->i2c[j]; + adap = &i2c->adap; + i2c_del_adapter(adap); + } + return stat; +} + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-i2c.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,101 @@ +/* + * ddbridge-i2c.h: Digital Devices bridge i2c driver + * + * Copyright (C) 2010-2013 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DDBRIDGE_I2C_H_ +#define _DDBRIDGE_I2C_H_ + +#include +#include + +static inline int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; + + return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; +} + +static inline int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) +{ + struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 } }; + return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +} + +static inline int i2c_read_regs(struct i2c_adapter *adapter, + u8 adr, u8 reg, u8 *val, u8 len) +{ + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = ®, .len = 1 }, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = len } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static inline int i2c_read_regs16(struct i2c_adapter *adapter, + u8 adr, u16 reg, u8 *val, u8 len) +{ + u8 reg16[2] = { reg >> 8, reg }; + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = reg16, .len = 2 }, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = len } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static inline int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) +{ + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = ®, .len = 1}, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static inline int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, + u16 reg, u8 *val) +{ + u8 msg[2] = {reg >> 8, reg & 0xff}; + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = msg, .len = 2}, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 } }; + return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; +} + +static inline int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, + u16 reg, u8 val) +{ + u8 msg[3] = {reg >> 8, reg & 0xff, val}; + + return i2c_write(adap, adr, msg, 3); +} + +static inline int i2c_write_reg(struct i2c_adapter *adap, u8 adr, + u8 reg, u8 val) +{ + u8 msg[2] = {reg, val}; + + return i2c_write(adap, adr, msg, 2); +} + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-mod.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-mod.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-mod.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-mod.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1060 @@ +#include "ddbridge.h" +#include "ddbridge-regs.h" + +#include + +inline s64 ConvertPCR(s64 a) +{ + s32 ext; + s64 b; + + b = div_s64_rem(a, 300 << 22, &ext); + + return (b << 31) | ext; + +} + +inline s64 NegConvertPCR(s64 a) +{ + s32 ext; + s64 b; + + b = -div_s64_rem(a, 300 << 22, &ext); + + if( ext != 0 ) { + ext = (300 << 22) - ext; + b -= 1; + } + return (b << 31) | ext; +} + +inline s64 RoundPCR(s64 a) +{ + s64 b = a + (HW_LSB_MASK>>1); + return b & ~(HW_LSB_MASK - 1); +} + +inline s64 RoundPCRUp(s64 a) +{ + s64 b = a + (HW_LSB_MASK - 1); + return b & ~(HW_LSB_MASK - 1); +} + +inline s64 RoundPCRDown(s64 a) +{ + return a & ~(HW_LSB_MASK - 1); +} + +static int mod_busy(struct ddb *dev, int chan) +{ + u32 creg; + + while (1) { + creg = ddbreadl(dev, CHANNEL_CONTROL(chan)); + if (creg == 0xffffffff) + return -EFAULT; + if ((creg & CHANNEL_CONTROL_BUSY) == 0) + break; + } + return 0; +} + +void ddbridge_mod_output_stop(struct ddb_output *output) +{ + struct ddb *dev = output->port->dev; + struct mod_state *mod= &dev->mod[output->nr]; + + mod->State = CM_IDLE; + mod->Control = 0; + ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); +#if 0 + udelay(10); + ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr)); + udelay(10); + ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); +#endif + mod_busy(dev, output->nr); + printk("mod_output_stop %d.%d\n", dev->nr, output->nr); +} + +static void mod_set_incs(struct ddb_output *output) +{ + s64 pcr; + struct ddb *dev = output->port->dev; + struct mod_state *mod= &dev->mod[output->nr]; + + pcr = ConvertPCR(mod->PCRIncrement); + ddbwritel(dev, pcr & 0xffffffff, + CHANNEL_PCR_ADJUST_OUTL(output->nr)); + ddbwritel(dev, (pcr >> 32) & 0xffffffff, + CHANNEL_PCR_ADJUST_OUTH(output->nr)); + mod_busy(dev, output->nr); + + pcr = NegConvertPCR(mod->PCRDecrement); + ddbwritel(dev, pcr & 0xffffffff, + CHANNEL_PCR_ADJUST_INL(output->nr)); + ddbwritel(dev, (pcr >> 32) & 0xffffffff, + CHANNEL_PCR_ADJUST_INH(output->nr)); + mod_busy(dev, output->nr); + +} + +static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 }; + +void ddbridge_mod_output_start(struct ddb_output *output) +{ + struct ddb *dev = output->port->dev; + struct mod_state *mod= &dev->mod[output->nr]; + + //PCRIncrement = RoundPCR(PCRIncrement); + //PCRDecrement = RoundPCR(PCRDecrement); + + mod->LastInPacketCount = 0; + mod->LastOutPacketCount = 0; + mod->InOverflowPacketCount = 0; + mod->OutOverflowPacketCount = 0; + mod->LastInPackets = 0; + mod->LastOutPackets = 0; + mod->LastPCRAdjust = 0; + mod->PCRRunningCorr = 0; + mod->MinInputPackets = 524288/2; // we interrupt every 0x80000=524288 packets + mod->PCRIncrement = 0;//PCRIncrement; + mod->PCRDecrement = 0;//PCRDecrement; + + mod->State = CM_STARTUP; + mod->StateCounter = CM_STARTUP_DELAY; + + ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); + udelay(10); + ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr)); + udelay(10); + ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); + + // QAM: 600 601 602 903 604 = 16 32 64 128 256 + //ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); + ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr)); + + ddbwritel(dev, mod->rate_inc, CHANNEL_RATE_INCR(output->nr)); + mod_busy(dev, output->nr); + + mod_set_incs(output); + + mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | + CHANNEL_CONTROL_ENABLE_DVB | + CHANNEL_CONTROL_ENABLE_SOURCE); + + ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr)); + printk("mod_output_start %d.%d\n", dev->nr, output->nr); +} + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static void mod_write_dac_register(struct ddb *dev, u8 Index, u8 Value) +{ + u32 RegValue = 0; + + ddbwritel(dev, Value, DAC_WRITE_DATA); + ddbwritel(dev, DAC_CONTROL_STARTIO | Index, DAC_CONTROL); + do { + RegValue = ddbreadl(dev, DAC_CONTROL); + } while ((RegValue & DAC_CONTROL_STARTIO) != 0 ); +} + +static void mod_write_dac_register2(struct ddb *dev, u8 Index, u16 Value) +{ + u32 RegValue = 0; + + ddbwritel(dev, Value, DAC_WRITE_DATA); + ddbwritel(dev, DAC_CONTROL_STARTIO | 0x20 | Index, DAC_CONTROL); + do { + RegValue = ddbreadl(dev, DAC_CONTROL); + } while ((RegValue & DAC_CONTROL_STARTIO) != 0 ); +} + +static int mod_read_dac_register(struct ddb *dev, u8 Index, u8 *pValue) +{ + u32 RegValue = 0; + + ddbwritel(dev, DAC_CONTROL_STARTIO | 0x80 | Index, DAC_CONTROL); + do { + RegValue = ddbreadl(dev, DAC_CONTROL); + } while( (RegValue & DAC_CONTROL_STARTIO) != 0 ); + + RegValue = ddbreadl(dev, DAC_READ_DATA); + *pValue = (u8) RegValue; + return 0; +} + +static void mod_set_up_converter_vco1(struct ddb *dev, u32 Value) +{ + u32 RegValue = 0; + + /* Extra delay before writing N divider */ + if ((Value & 0x03) == 0x02) + msleep(50); + do { + RegValue = ddbreadl(dev, VCO1_CONTROL); + } while( (RegValue & VCO1_CONTROL_WRITE) != 0 ); + + if ((RegValue & VCO1_CONTROL_CE) == 0) { + RegValue |= VCO1_CONTROL_CE; + ddbwritel(dev, RegValue, VCO1_CONTROL); + msleep(10); + } + + ddbwritel(dev, Value, VCO1_DATA); + ddbwritel(dev, RegValue | VCO1_CONTROL_WRITE, VCO1_CONTROL); +} + +static void mod_set_up_converter_vco2(struct ddb *dev, u32 Value) +{ + u32 RegValue = 0; + + /* Extra delay before writing N divider */ + if ((Value & 0x03) == 0x02) + msleep(50); + do { + RegValue = ddbreadl(dev, VCO2_CONTROL); + } while ((RegValue & VCO2_CONTROL_WRITE) != 0); + + if ((RegValue & VCO2_CONTROL_CE) == 0) { + RegValue |= VCO2_CONTROL_CE; + ddbwritel(dev, RegValue, VCO2_CONTROL); + msleep(10); + } + + ddbwritel(dev, Value, VCO2_DATA); + ddbwritel(dev, RegValue | VCO2_CONTROL_WRITE, VCO2_CONTROL); +} + +static void mod_set_down_converter_vco(struct ddb *dev, u32 Value) +{ + u32 RegValue = 0; + + do { + RegValue = ddbreadl(dev, VCO3_CONTROL); + } while( (RegValue & VCO3_CONTROL_WRITE) != 0 ); + + if ((RegValue & VCO3_CONTROL_CE) == 0) { + RegValue |= VCO3_CONTROL_CE; + ddbwritel(dev, RegValue, VCO3_CONTROL); + msleep(10); + } + ddbwritel(dev, Value, VCO3_DATA); + ddbwritel(dev, RegValue | VCO3_CONTROL_WRITE, VCO3_CONTROL); +} + +static int mod_set_attenuator(struct ddb *dev, u32 Value) +{ + if (Value > 31) + return -EINVAL; + ddbwritel(dev, Value, RF_ATTENUATOR); + return 0; +} + +static void mod_si598_readreg(struct ddb *dev, u8 index, u8 *val) +{ + ddbwritel(dev, index, CLOCKGEN_INDEX); + ddbwritel(dev, 1, CLOCKGEN_CONTROL); + msleep(5); + *val = ddbreadl(dev, CLOCKGEN_READDATA); +} + +static void mod_si598_writereg(struct ddb *dev, u8 index, u8 val) +{ + ddbwritel(dev, index, CLOCKGEN_INDEX); + ddbwritel(dev, val, CLOCKGEN_WRITEDATA); + ddbwritel(dev, 3, CLOCKGEN_CONTROL); + msleep(5); +} + +static int mod_set_si598(struct ddb *dev, u32 freq) +{ + u8 Data[6]; + u64 fDCO = 0; + u64 RFreq = 0; + u32 fOut = 10000000; + u64 m_fXtal = 0; + u32 N = 0; + u64 HSDiv = 0; + + u32 fxtal; + u64 MinDiv, MaxDiv, Div; + u64 RF; + + if (freq < 10000000 || freq > 525000000 ) + return -EINVAL; + mod_si598_writereg(dev, 137, 0x10); + + if (m_fXtal == 0) { + mod_si598_writereg(dev, 135, 0x01); + mod_si598_readreg(dev, 7, &Data[0]); + mod_si598_readreg(dev, 8, &Data[1]); + mod_si598_readreg(dev, 9, &Data[2]); + mod_si598_readreg(dev, 10, &Data[3]); + mod_si598_readreg(dev, 11, &Data[4]); + mod_si598_readreg(dev, 12, &Data[5]); + + printk(" Data = %02x %02x %02x %02x %02x %02x\n", + Data[0],Data[1],Data[2],Data[3],Data[4],Data[5]); + RFreq = (((u64)Data[1] & 0x3F) << 32) | ((u64)Data[2] << 24) | + ((u64)Data[3] << 16) | ((u64)Data[4] << 8) | ((u64)Data[5]); + if (RFreq == 0) + return -EINVAL; + HSDiv = ((Data[0] & 0xE0) >> 5) + 4; + if (HSDiv == 8 || HSDiv == 10 ) + return -EINVAL; + N = (((u32)(Data[0] & 0x1F) << 2) | ((u32)(Data[1] & 0xE0) >> 6)) + 1; + fDCO = fOut * (u64)(HSDiv * N); + m_fXtal = fDCO << 28; + printk("fxtal %016llx rfreq %016llx\n", m_fXtal, RFreq); + + m_fXtal += RFreq >> 1; + m_fXtal = div64_u64(m_fXtal, RFreq); + + printk(" fOut = %d fXtal = %d fDCO = %d HDIV = %2d, N = %3d \n", + (u32) fOut,(u32) m_fXtal,(u32) fDCO,HSDiv,N); + } + + fOut = freq; + MinDiv = 4850000000ULL; do_div(MinDiv, freq); MinDiv += 1; + MaxDiv = 5670000000ULL; do_div(MaxDiv, freq); + Div = 5260000000ULL; do_div(Div, freq); + + if( Div < MinDiv ) + Div = Div + 1; + printk(" fOut = %d MinDiv = %4d MaxDiv = %4d StartDiv = %d\n", fOut,MinDiv,MaxDiv,Div); + + if( Div <= 11 ) { + N = 1; + HSDiv = Div; + } else { + int retry = 100; + while (retry > 0) { + N = 0; + HSDiv = Div; + while( (HSDiv > 11) /*|| ((HSDiv * N) != Div)*/ ) { + N = N + 2; + HSDiv = Div; + do_div(HSDiv, N); + if (N > 128) + break; + } + printk(" %3d: %llu %u %u %u\n", retry, Div, HSDiv*N, HSDiv, N); + if (HSDiv * N < MinDiv) { + Div = Div + 2; + } else if (HSDiv * N > MaxDiv) { + Div = Div - 2; + } else + break; + retry = retry - 1; + } + if( retry == 0 ) { + printk(" FAIL \n"); + return -EINVAL; + } + } + + if (HSDiv == 8 || HSDiv == 10) { + HSDiv = HSDiv >> 1; + N = N * 2; + } + + if (HSDiv < 4) + return -EINVAL; + + + fDCO = (u64)fOut * (u64)N * (u64)HSDiv; + printk("fdco %16llx\n", fDCO); + RFreq = fDCO<<28; + printk("%16llx %16llx\n", fDCO, RFreq); + + fxtal = m_fXtal; + do_div(RFreq, fxtal); + printk("%16llx %d\n", RFreq, fxtal); + RF = RFreq; + + //printk("fOut = %d fXtal = %d fDCO = %d HDIV = %d, N = %d, RFreq = %d\n",fOut,m_fXtal,fDCO,HSDiv,N,RFreq); + //printk("%16llx\n", RF); + + Data[0] = (u8)( ((HSDiv - 4) << 5) | ((N - 1) >> 2) ); + Data[1] = (u8)( (((N - 1) & 0x03) << 6) | (( RF >> 32 ) & 0x3F ) ); + Data[2] = (u8)( (RF >> 24) & 0xFF ); + Data[3] = (u8)( (RF >> 16) & 0xFF ); + Data[4] = (u8)( (RF >> 8) & 0xFF ); + Data[5] = (u8)( (RF ) & 0xFF ); + + printk(" Data = %02x %02x %02x %02x %02x %02x\n", + Data[0], Data[1], Data[2], Data[3], Data[4], Data[5]); + mod_si598_writereg(dev, 7, Data[0]); + mod_si598_writereg(dev, 8, Data[1]); + mod_si598_writereg(dev, 9, Data[2]); + mod_si598_writereg(dev, 10, Data[3]); + mod_si598_writereg(dev, 11, Data[4]); + mod_si598_writereg(dev, 12, Data[5]); + + mod_si598_writereg(dev, 137, 0x00); + mod_si598_writereg(dev, 135, 0x40); + return 0; +} + + +static void mod_bypass_equalizer(struct ddb *dev, int bypass) +{ + u32 RegValue; + + RegValue = ddbreadl(dev, IQOUTPUT_CONTROL); + RegValue &= ~IQOUTPUT_CONTROL_BYPASS_EQUALIZER; + RegValue |= (bypass ? IQOUTPUT_CONTROL_BYPASS_EQUALIZER : 0x00); + ddbwritel(dev, RegValue, IQOUTPUT_CONTROL); +} + +static int mod_set_equalizer(struct ddb *dev, u32 Num, s16 *cTable) +{ + u32 i, adr = IQOUTPUT_EQUALIZER_0; + + if (Num > 11) + return -EINVAL; + + for (i = 0; i < 11 - Num; i += 1) { + ddbwritel(dev, 0, adr); + adr += 4; + } + for (i = 0; i < Num; i += 1) { + ddbwritel(dev, (u32) cTable[i], adr); + adr += 4; + } + return 0; +} + +static void mod_peak(struct ddb *dev, u32 Time, s16 *pIPeak, s16 *pQPeak) +{ + u32 val; + + val = ddbreadl(dev, IQOUTPUT_CONTROL); + val &= ~(IQOUTPUT_CONTROL_ENABLE_PEAK | IQOUTPUT_CONTROL_RESET_PEAK); + ddbwritel(dev, val, IQOUTPUT_CONTROL); + ddbwritel(dev, val | IQOUTPUT_CONTROL_RESET_PEAK, IQOUTPUT_CONTROL); + msleep(10); + ddbwritel(dev, val, IQOUTPUT_CONTROL); + ddbwritel(dev, val | IQOUTPUT_CONTROL_ENABLE_PEAK, IQOUTPUT_CONTROL); + msleep(Time); + ddbwritel(dev, val, IQOUTPUT_CONTROL); + val = ddbreadl(dev, IQOUTPUT_PEAK_DETECTOR); + + *pIPeak = val & 0xffff; + *pQPeak = (val >> 16) & 0xffff; +} + +static int mod_init_dac_input(struct ddb *dev) +{ + u8 Set = 0; + u8 Hld = 0; + u8 Sample = 0; + + u8 Seek = 0; + u8 ReadSeek = 0; + + u8 SetTable[32]; + u8 HldTable[32]; + u8 SeekTable[32]; + + u8 Sample1 = 0xFF; + u8 Sample2 = 0xFF; + + u8 SelectSample = 0xFF; + u8 DiffMin = 0xFF; + + for (Sample = 0; Sample < 32; Sample++ ) { + Set = 0; + Hld = 0; + + mod_write_dac_register(dev, 0x04, Set << 4 | Hld); + mod_write_dac_register(dev, 0x05, Sample); + mod_read_dac_register(dev, 0x06, &ReadSeek); + Seek = ReadSeek & 0x01; + SeekTable[Sample] = Seek; + + HldTable[Sample] = 15; + + for (Hld = 1; Hld < 16; Hld += 1) { + mod_write_dac_register(dev, 0x04, Set << 4 | Hld); + mod_read_dac_register(dev, 0x06, &ReadSeek); + + if ((ReadSeek & 0x01) != Seek) + { + HldTable[Sample] = Hld; + break; + } + } + + Hld = 0; + SetTable[Sample] = 15; + for (Set = 1; Set < 16; Set += 1) { + mod_write_dac_register(dev, 0x04, Set << 4 | Hld); + mod_read_dac_register(dev, 0x06, &ReadSeek); + + if( (ReadSeek & 0x01) != Seek ) { + SetTable[Sample] = Set; + break; + } + } + } + + Seek = 1; + for (Sample = 0; Sample < 32; Sample += 1 ) { + //printk(" %2d: %d %2d %2d\n", Sample,SeekTable[Sample],SetTable[Sample],HldTable[Sample]); + + if (Sample1 == 0xFF && SeekTable[Sample] == 1 && Seek == 0 ) + Sample1 = Sample; + if (Sample1 != 0xFF && Sample2 == 0xFF && SeekTable[Sample] == 0 && Seek == 1 ) + Sample2 = Sample; + Seek = SeekTable[Sample]; + } + + if (Sample1 == 0xFF || Sample2 == 0xFF ) { + printk(" No valid window found\n"); + return -EINVAL; + } + + printk(" Window = %d - %d\n", Sample1, Sample2); + + for (Sample = Sample1; Sample < Sample2; Sample += 1) { + if (SetTable[Sample] < HldTable[Sample]) { + if (HldTable[Sample] - SetTable[Sample] < DiffMin) { + DiffMin = HldTable[Sample] - SetTable[Sample]; + SelectSample = Sample; + } + } + } + + printk("Select Sample %d\n", SelectSample); + + if (SelectSample == 0xFF) { + printk("No valid sample found\n"); + return -EINVAL; + } + + if (HldTable[SelectSample] + SetTable[SelectSample] < 8 ) { + printk("Too high jitter\n"); + return -EINVAL; + } + + mod_write_dac_register(dev, 0x04, 0x00); + mod_write_dac_register(dev, 0x05, (SelectSample - 1) & 0x1F); + mod_read_dac_register(dev, 0x06, &Seek); + mod_write_dac_register(dev, 0x05, (SelectSample + 1) & 0x1F); + mod_read_dac_register(dev, 0x06,&ReadSeek); + Seek &= ReadSeek; + + mod_write_dac_register(dev, 0x05, SelectSample); + mod_read_dac_register(dev, 0x06, &ReadSeek); + Seek &= ReadSeek; + if( (Seek & 0x01) == 0 ) { + printk("Insufficient timing margin\n"); + return -EINVAL; + } + printk("Done\n"); + return 0; +} + +static void mod_set_up1(struct ddb *dev, u32 Frequency, u32 Ref, u32 Ext) +{ + u32 RDiv = Ext / Ref; + + Frequency = Frequency / Ref; + mod_set_up_converter_vco1(dev, 0x360001 | (RDiv << 2)); + mod_set_up_converter_vco1(dev, 0x0ff128); + mod_set_up_converter_vco1(dev, 0x02 | (Frequency << 8)); +} + +static void mod_set_up2(struct ddb *dev, u32 Frequency, u32 Ref, u32 Ext) +{ + u32 Rdiv = Ext / Ref; + u32 PreScale = 8; + + Frequency = Frequency / Ref; + mod_set_up_converter_vco2(dev, 0x360001 | (Rdiv << 2)); + mod_set_up_converter_vco2(dev, 0x0fc128 | (((PreScale - 8) / 8) << 22)); + mod_set_up_converter_vco2(dev, 0x02 | ((Frequency / PreScale) << 8) + | (Frequency & (PreScale - 1)) << 2); +} + +static int mod_set_down(struct ddb *dev, u32 Frequency, u32 Ref, u32 Ext) +{ + u32 BandSelect = Ref * 8; + u32 RefMul = 1; + u32 RefDiv2 = 1; + u32 RefDiv = Ext * RefMul / (Ref * RefDiv2); + + if (Frequency < 2200 || Frequency > 4000) + return -EINVAL; + + Frequency = Frequency / Ref; + + mod_set_down_converter_vco(dev, 0x0080003C | ((BandSelect & 0xFF) << 12)); + mod_set_down_converter_vco(dev, 0x00000003); + mod_set_down_converter_vco(dev, 0x18001E42 | ((RefMul-1) << 25) | + ((RefDiv2-1) << 24) | (RefDiv << 14) ); + mod_set_down_converter_vco(dev, 0x08008021); + mod_set_down_converter_vco(dev, Frequency << 15); + return 0; +} + +static int mod_set_dac_clock(struct ddb *dev, u32 Frequency) +{ + int hr, i; + + if (Frequency) { + ddbwritel(dev, DAC_CONTROL_RESET, DAC_CONTROL); + msleep(10); + if (mod_set_si598(dev, Frequency)) { + printk("mod_set_si598 failed\n"); + return -1; + } + msleep(50); + ddbwritel(dev, 0x000, DAC_CONTROL); + msleep(10); + mod_write_dac_register(dev, 0, 0x02); + } + + for (i = 0; i < 10; i++) { + hr = mod_init_dac_input(dev); + if (hr == 0) + break; + msleep(100); + } + printk("mod_set_dac_clock OK\n"); + return hr; +} + +static void mod_set_dac_current(struct ddb *dev, u32 Current1, u32 Current2) +{ + mod_write_dac_register2(dev, 0x0b, Current1 & 0x3ff); + mod_write_dac_register2(dev, 0x0f, Current2 & 0x3ff); +} + +static void mod_output_enable(struct ddb *dev, int enable) +{ + + u32 RegValue; + + RegValue = ddbreadl(dev, IQOUTPUT_CONTROL); + RegValue &= ~(IQOUTPUT_CONTROL_ENABLE | IQOUTPUT_CONTROL_RESET); + ddbwritel(dev, RegValue, IQOUTPUT_CONTROL); + + if (enable) { + ddbwritel(dev, RegValue | IQOUTPUT_CONTROL_RESET, IQOUTPUT_CONTROL); + msleep(10); + ddbwritel(dev, RegValue, IQOUTPUT_CONTROL); + ddbwritel(dev, RegValue | IQOUTPUT_CONTROL_ENABLE, IQOUTPUT_CONTROL); + } +} + +static int mod_set_iq(struct ddb *dev, u32 steps, u32 chan, u32 freq) +{ + u32 i, j, k, fac = 8; + u32 s1 = 22, s2 = 33; + u64 amp = (1ULL << 17) - 1ULL; + u64 s = 0, c = (amp << s1), ss; + u64 frq = 0xC90FDAA22168C234ULL; + u32 *iqtab; + u32 iqtabadr; + u32 volatile regval; + + iqtab = kmalloc((steps + 1) * 4, GFP_KERNEL); + if (!iqtab) + return -ENOMEM; + frq = div64_u64(frq, steps * fac) >> (61 - s2); + + /* create sine table */ + for (i = 0; i <= steps * fac / 4; i++) { + if (!(i & (fac - 1))) { + j = i / fac; + ss = s >> s1; + //ss = ((s >> (s1 - 1)) + 1) >> 1; + + iqtab[j] = iqtab[steps / 2 - j] = ss; + iqtab[steps / 2 + j] = iqtab[steps - j] = -ss; + } + c -= ((s * frq) >> s2); + s += ((c * frq) >> s2); + } + + iqtabadr = chan << 16; + ddbwritel(dev, chan & 0x0f, MODULATOR_IQTABLE_INDEX); + for (i = j = 0, k = steps / 4; i < steps; i++) { + ddbwritel(dev, (iqtabadr + i) | MODULATOR_IQTABLE_INDEX_SEL_I, + MODULATOR_IQTABLE_INDEX); + ddbwritel(dev, iqtab[j], MODULATOR_IQTABLE_DATA); + regval = ddbreadl(dev, MODULATOR_CONTROL); + ddbwritel(dev, (iqtabadr + i) | MODULATOR_IQTABLE_INDEX_SEL_Q, + MODULATOR_IQTABLE_INDEX); + ddbwritel(dev, iqtab[k], MODULATOR_IQTABLE_DATA); + regval = ddbreadl(dev, MODULATOR_CONTROL); + j += freq; + j %= steps; + k += freq; + k %= steps; + } + ddbwritel(dev, steps - 1, MODULATOR_IQTABLE_END); + kfree(iqtab); + return 0; +} + +u32 eqtab[] = { + 0x0000FFDB, 0x00000121, 0x0000FF0A, 0x000003D7, + 0x000001C4, 0x000005A5, 0x000009CC, 0x0000F50D, + 0x00001B23, 0x0000EEB7, 0x00006A28 +}; + +static int mod_set_modulation(struct ddb *dev, int chan, int mod) +{ + static u32 setting[5] = { 0x600, 0x601, 0x602, 0x903, 0x604 }; + + if (mod > 4) + return -EINVAL; + ddbwritel(dev, setting[mod] , CHANNEL_SETTINGS(chan)); + return 0; +} + +static void mod_set_rateinc(struct ddb *dev, u32 chan, u32 inc) +{ + dev->mod[chan].rate_inc = inc; + ddbwritel(dev, inc, CHANNEL_RATE_INCR(chan)); + mod_busy(dev, chan); +} + +static void mod_set_channelsumshift(struct ddb *dev, u32 shift) +{ + ddbwritel(dev, (shift & 3) << 2, MODULATOR_CONTROL); +} + +static void mod_pre_eq_gain(struct ddb *dev, u16 gain) +{ + ddbwritel(dev, gain, IQOUTPUT_PRESCALER); +} + +static void mod_post_eq_gain(struct ddb *dev, u16 igain, u16 qgain) +{ + ddbwritel(dev, ((u32)qgain << 16) | igain, IQOUTPUT_POSTSCALER); +} + +static int set_base_frequency(struct ddb *dev, u32 freq) +{ + u32 Ext = 40; + u32 UP1Frequency = 290; + u32 UP2Frequency = 1896; + u32 down, freq10; + + printk("set base to %u\n", freq); + dev->mod_base.frequency = freq; + freq /= 1000000; + freq10 = dev->mod_base.flat_start + 4; + down = freq + 9 * 8 + freq10 + UP1Frequency + UP2Frequency; + + if ((freq10 + 9 * 8) > (dev->mod_base.flat_end - 4)) { + printk("Frequency out of range %d\n", freq10); + return -EINVAL; + } + if (down % 8) { + printk(" Invalid Frequency %d\n", down); + return -EINVAL; + } + return mod_set_down(dev, down, 8, Ext); +} + +static int mod_init(struct ddb *dev, u32 Frequency) +{ + int stat = 0; + u8 *buffer; + struct DDMOD_FLASH *flash; + u32 Ext = 40; + u32 UP1Frequency = 290; + u32 UP2Frequency = 1896; + u32 DownFrequency; + u32 FrequencyCH10; + u32 iqfreq, iqsteps, i; + + buffer = kmalloc(4096, GFP_KERNEL); + if (!buffer) + return -ENOMEM; + flash = (struct DDMOD_FLASH *) buffer; + + ddbridge_flashread(dev, buffer, DDMOD_FLASH_START, 4096); + + if (flash->Magic != DDMOD_FLASH_MAGIC && flash->Magic != 1) { + stat = -EINVAL; + goto fail; + } + printk("srate = %d\n", flash->DataSet[0].Symbolrate * 1000); + + mod_output_enable(dev, 0); + stat = mod_set_dac_clock(dev, flash->DataSet[0].DACFrequency * 1000); + if (stat < 0) { + printk("setting DAC clock failed\n"); + goto fail; + } + mod_set_dac_current(dev, 512, 512); + + ddbwritel(dev, flash->DataSet[0].Control2, IQOUTPUT_CONTROL2); + + mod_set_up1(dev, UP1Frequency, 5, Ext); + mod_set_up2(dev, UP2Frequency, 8, Ext); + + dev->mod_base.flat_start = flash->DataSet[0].FlatStart; + dev->mod_base.flat_end = flash->DataSet[0].FlatEnd; + + Frequency /= 1000000; + FrequencyCH10 = flash->DataSet[0].FlatStart + 4; + DownFrequency = Frequency + 9 * 8 + FrequencyCH10 + UP1Frequency + UP2Frequency; + printk("CH10 = %d, Down = %d\n", FrequencyCH10, DownFrequency); + + + if ((FrequencyCH10 + 9 * 8) > (flash->DataSet[0].FlatEnd - 4)) { + printk("Frequency out of range %d\n", FrequencyCH10); + stat = -EINVAL; + goto fail; + } + + if (DownFrequency % 8 != 0 ) { + printk(" Invalid Frequency %d\n", DownFrequency); + stat = -EINVAL; + goto fail; + } + + mod_set_down(dev, DownFrequency, 8, Ext); + + for (i = 0; i < 10; i++) { + ddbwritel(dev, 0, CHANNEL_CONTROL(i)); + + iqfreq = flash->DataSet[0].FrequencyFactor * (FrequencyCH10 + (9 - i) * 8); + iqsteps = flash->DataSet[0].IQTableLength; + mod_set_iq(dev, iqsteps, i, iqfreq); + + dev->mod[i].modulation = QAM_256; + } + + mod_bypass_equalizer(dev, 1); + mod_set_equalizer(dev, 11, flash->DataSet[0].EQTap); + mod_bypass_equalizer(dev, 0); + mod_post_eq_gain(dev, flash->DataSet[0].PostScaleI, flash->DataSet[0].PostScaleQ); + mod_pre_eq_gain(dev, flash->DataSet[0].PreScale); + //mod_pre_eq_gain(dev, 0x0680); + printk("prescaler %04x\n", flash->DataSet[0].PreScale); + mod_set_channelsumshift(dev, 2); + mod_output_enable(dev, 1); + + //mod_set_attenuator(dev, 10); +fail: + kfree(buffer); + return stat; +} + + +void ddbridge_mod_rate_handler(unsigned long data) +{ + struct ddb_output *output = (struct ddb_output *) data; + struct ddb_dma *dma = output->dma; + struct ddb *dev = output->port->dev; + struct mod_state *mod= &dev->mod[output->nr]; + + u32 chan = output->nr; + u32 OutPacketCount; + u32 InPacketCount; + u64 OutPackets, InPackets; + s64 PCRAdjust; + u32 PCRAdjustExt, PCRAdjustExtFrac, InPacketDiff, OutPacketDiff; + s32 PCRCorr; + + s64 pcr; + s64 PCRIncrementDiff; + s64 PCRIncrement; + u64 mul; + + if (!mod->do_handle) + return; + printk("rate_handler\n"); + + spin_lock(&dma->lock); + ddbwritel(dev, mod->Control | CHANNEL_CONTROL_FREEZE_STATUS, + CHANNEL_CONTROL(output->nr)); + + OutPacketCount = ddbreadl(dev, CHANNEL_PKT_COUNT_OUT(chan)); + if (OutPacketCount < mod->LastOutPacketCount ) + mod->OutOverflowPacketCount += 1; + mod->LastOutPacketCount = OutPacketCount; + + InPacketCount = ddbreadl(dev, CHANNEL_PKT_COUNT_IN(chan)); + if (InPacketCount < mod->LastInPacketCount ) + mod->InOverflowPacketCount += 1; + mod->LastInPacketCount = InPacketCount; + + OutPackets = ((u64) (mod->OutOverflowPacketCount) << 20) | OutPacketCount; + InPackets = ((u64) (mod->InOverflowPacketCount) << 20) | InPacketCount; + + PCRAdjust = (s64) ((u64) ddbreadl(dev, CHANNEL_PCR_ADJUST_ACCUL(chan)) | + (((u64) ddbreadl(dev, CHANNEL_PCR_ADJUST_ACCUH(chan)) << 32))); + PCRAdjustExt = (u32)((PCRAdjust & 0x7FFFFFFF) >> 22); + PCRAdjustExtFrac = (u32)((PCRAdjust & 0x003FFFFF) >> 12); + PCRAdjust >>= 31; + InPacketDiff = (u32) (InPackets - mod->LastInPackets); + OutPacketDiff = (u32) (OutPackets - mod->LastOutPackets); + PCRCorr = 0; + + switch (mod->State) { + case CM_STARTUP: + if (mod->StateCounter) { + if (mod->StateCounter == 1) { + mul = (0x1000000 * (u64) (OutPacketDiff - InPacketDiff - InPacketDiff/1000)); + if (OutPacketDiff) + mod->rate_inc = div_u64(mul, OutPacketDiff); + else + mod->rate_inc = 0; + printk("RI %08x\n", mod->rate_inc); + ddbwritel(dev, mod->rate_inc, CHANNEL_RATE_INCR(output->nr)); + mod_busy(dev, output->nr); +//#define PACKET_CLOCKS (27000000ULL*1504) +//#define FACTOR (1024<<12) +//double Increment = FACTOR*PACKET_CLOCKS/double(m_OutputBitrate); +//double Decrement = FACTOR*PACKET_CLOCKS/double(m_InputBitrate); + mod->PCRIncrement = 3348148758ULL; + if (InPacketDiff) + mod->PCRDecrement = div_u64(3348148758ULL * (u64) OutPacketDiff, + InPacketDiff); + else + mod->PCRDecrement = 0; + mod_set_incs(output); + } + mod->StateCounter--; + break; + } + if (InPacketDiff >= mod->MinInputPackets) { + mod->State = CM_ADJUST; + mod->Control |= CHANNEL_CONTROL_ENABLE_PCRADJUST; + mod->InPacketsSum = 0; + mod->OutPacketsSum = 0; + mod->PCRAdjustSum = 0; + mod->StateCounter = CM_AVERAGE; + } + break; + + case CM_ADJUST: + if (InPacketDiff < mod->MinInputPackets) { + printk("PCR Adjust reset IN: %u Min: %u\n", + InPacketDiff, mod->MinInputPackets); + mod->InPacketsSum = 0; + mod->OutPacketsSum = 0; + mod->PCRAdjustSum = 0; + mod->StateCounter = CM_AVERAGE; + ddbwritel(dev, + (mod->Control | CHANNEL_CONTROL_FREEZE_STATUS) & + ~CHANNEL_CONTROL_ENABLE_PCRADJUST, + CHANNEL_CONTROL(chan)); + break; + } + + mod->PCRAdjustSum += (s32) PCRAdjust; + mod->InPacketsSum += InPacketDiff; + mod->OutPacketsSum += OutPacketDiff; + if (mod->StateCounter--) + break; + + if (mod->OutPacketsSum) + PCRIncrement = div_s64((s64)mod->InPacketsSum * + (s64)mod->PCRDecrement + + (s64)(mod->OutPacketsSum >> 1) , + mod->OutPacketsSum); + else + PCRIncrement = 0; + + if( mod->PCRAdjustSum > 0 ) + PCRIncrement = RoundPCRDown(PCRIncrement); + else + PCRIncrement = RoundPCRUp(PCRIncrement); + + PCRIncrementDiff = PCRIncrement - mod->PCRIncrement; + if( PCRIncrementDiff > HW_LSB_MASK ) + PCRIncrementDiff = HW_LSB_MASK; + if( PCRIncrementDiff < -HW_LSB_MASK ) + PCRIncrementDiff = -HW_LSB_MASK; + + mod->PCRIncrement += PCRIncrementDiff; + pcr = ConvertPCR(mod->PCRIncrement); + printk("outl %016llx\n", pcr); + ddbwritel(dev, pcr & 0xffffffff, + CHANNEL_PCR_ADJUST_OUTL(output->nr)); + ddbwritel(dev, (pcr >> 32) & 0xffffffff, + CHANNEL_PCR_ADJUST_OUTH(output->nr)); + mod_busy(dev, chan); + + PCRCorr = (s32) (PCRIncrementDiff >> HW_LSB_SHIFT); + mod->PCRRunningCorr += PCRCorr; + + mod->InPacketsSum = 0; + mod->OutPacketsSum = 0; + mod->PCRAdjustSum = 0; + mod->StateCounter = CM_AVERAGE; + break; + + default: + break; + } + ddbwritel(dev, mod->Control, CHANNEL_CONTROL(chan)); + + mod->LastInPackets = InPackets; + mod->LastOutPackets = OutPackets; + mod->LastPCRAdjust = (s32) PCRAdjust; + + printk("chan %d out %016llx in %016llx indiff %08x\n", chan, OutPackets, InPackets, InPacketDiff); + printk("cnt %d pcra %016llx pcraext %08x pcraextfrac %08x pcrcorr %08x pcri %016llx\n", + mod->StateCounter, PCRAdjust, PCRAdjustExt, PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement); + //Channel,OutPackets,InPackets,InPacketDiff,PCRAdjust,PCRAdjustExt,PCRAdjustExtFrac,PCRCorr, mod->PCRRunningCorr,mod->StateCounter )); + spin_unlock(&dma->lock); +} + +int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb *dev = output->port->dev; + + //unsigned long arg = (unsigned long) parg; + int ret = 0; + + switch (cmd) { + case DVB_MOD_SET: + { + struct dvb_mod_params *mp = parg; + + if (mp->base_frequency != dev->mod_base.frequency) + if (set_base_frequency(dev, mp->base_frequency)) + return -EINVAL; + mod_set_attenuator(dev, mp->attenuator); + break; + } + case DVB_MOD_CHANNEL_SET: + { + struct dvb_mod_channel_params *cp = parg; + + if (cp->modulation > QAM_256) + return -EINVAL; + dev->mod[output->nr].modulation = cp->modulation; + dev->mod[output->nr].rate_inc = cp->rate_increment; + ddbwritel(dev, dev->mod[output->nr].rate_inc, CHANNEL_RATE_INCR(output->nr)); + break; + } + default: + ret = -EINVAL; + break; + } + return ret; +} + +int ddbridge_mod_init(struct ddb *dev) +{ + return mod_init(dev, 722000000); +} + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-ns.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-ns.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-ns.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-ns.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,465 @@ +static int ddb_dvb_input_start(struct ddb_input *input); +static int ddb_dvb_input_stop(struct ddb_input *input); + +static u16 calc_pcs(struct dvb_ns_params *p) +{ + u32 sum = 0; + u16 pcs; + + sum += (p->sip[0] << 8) | p->sip[1]; + sum += (p->sip[2] << 8) | p->sip[3]; + sum += (p->dip[0] << 8) | p->dip[1]; + sum += (p->dip[2] << 8) | p->dip[3]; + sum += 0x11; /* UDP proto */ + sum = (sum >> 16) + (sum & 0xffff); + pcs = sum; + //printk("PCS = %04x\n", pcs); + return pcs; +} + +static u16 calc_pcs16(struct dvb_ns_params *p, int ipv) +{ + u32 sum = 0, i; + u16 pcs; + + for (i = 0; i < ipv ? 16 : 4; i += 2) { + sum += (p->sip[i] << 8) | p->sip[i + 1]; + sum += (p->dip[i] << 8) | p->dip[i + 1]; + } + sum += 0x11; /* UDP proto */ + sum = (sum >> 16) + (sum & 0xffff); + pcs = sum; + return pcs; +} + +/******************************************************************************/ +/******************************************************************************/ +/******************************************************************************/ + +static void ns_free(struct dvbnss *nss) +{ + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + + mutex_lock(&dev->mutex); + dns->input = 0; + mutex_unlock(&dev->mutex); +} + +static int ns_alloc(struct dvbnss *nss) +{ + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + int i, ret = -EBUSY; + + mutex_lock(&dev->mutex); + for (i = 0; i < dev->ns_num; i++) { + if (dev->ns[i].input) + continue; + dev->ns[i].input = input; + dev->ns[i].fe = input->nr; + nss->priv = &dev->ns[i]; + ret = 0; + //printk("%s i=%d fe=%d\n", __func__, i, input->nr); + break; + } + ddbwritel(dev, 0x03, RTP_MASTER_CONTROL); + mutex_unlock(&dev->mutex); + return ret; +} + +static int ns_set_pids(struct dvbnss *nss) +{ + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + + //printk("ns_set_pids %02x %02x\n", nss->pids[0], nss->pids[1]); + if (dev->devid == 0x0301dd01) { + u32 sys = 0; + int pid, j = 1; + + sys |= nss->pids[0] & 3; + sys |= (nss->pids[2] & 0x1f) << 4; + ddbwritel(dev, sys, PID_FILTER_SYSTEM_PIDS(dns->nr)); + for (pid = 20; j < 5 && pid < 8192; pid++) + if (nss->pids[pid >> 3] & (1 << (pid & 7))) { + ddbwritel(dev, 0x8000 | pid, PID_FILTER_PID(dns->nr, j)); + j++; + } + /* disable unused pids */ + for (; j < 5; j++) + ddbwritel(dev, 0, PID_FILTER_PID(dns->nr, j)); + } else + ddbcpyto(dev, STREAM_PIDS(dns->nr), nss->pids, 0x400); + return 0; +} + +static int ns_set_pid(struct dvbnss *nss, u16 pid) +{ + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + u16 byte = (pid & 0x1fff) >> 3; + u8 bit = 1 << (pid & 7); + u32 off = STREAM_PIDS(dns->nr); + +#if 1 + if (dev->devid == 0x0301dd01) { + if (pid & 0x2000) { + if (pid & 0x8000) + memset(nss->pids, 0xff, 0x400); + else + memset(nss->pids, 0x00, 0x400); + } else { + if (pid & 0x8000) + nss->pids[byte] |= bit; + else + nss->pids[byte] &= ~bit; + } + ns_set_pids(nss); + } else { + if (pid & 0x2000) { + if (pid & 0x8000) + ddbmemset(dev, off, 0xff, 0x400); + else + ddbmemset(dev, off, 0x00, 0x400); + } else { + u8 val = ddbreadb(dev, off + byte); + if (pid & 0x8000) + ddbwriteb(dev, val | bit, off + byte); + else + ddbwriteb(dev, val & ~bit, off + byte); + } + } +#else + ddbcpyto(dev, STREAM_PIDS(dns->nr), nss->pids, 0x400); +#endif + return 0; +} + +static int citoport(struct ddb *dev, u8 ci) +{ + int i, j; + struct ddb_input *input; + + for (i = j = 0; i < dev->info->port_num; i++) { + if (dev->port[i].class == DDB_PORT_CI) { + if (j == ci) + return i; + j++; + } + } + return -1; +} + +static int ns_set_ci(struct dvbnss *nss, u8 ci) +{ + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + int ciport; + + if (ci == 255) { + dns->fe = input->nr; + return 0; + } + ciport = citoport(dev, ci); + if (ciport < 0) + return -EINVAL; + printk("input %d to ci %d at port %d\n", input->nr, ci, ciport); + ddbwritel(dev, (input->nr << 16) | 0x1c, TS_OUTPUT_CONTROL(ciport)); + usleep_range(1, 5); + ddbwritel(dev, (input->nr << 16) | 0x1d, TS_OUTPUT_CONTROL(ciport)); + dns->fe = ciport * 2; + return 0; +} + +static u8 rtp_head[] = { + 0x80, 0x21, + 0x00, 0x00, /* seq number */ + 0x00, 0x00, 0x00, 0x00, /* time stamp*/ + 0x91, 0x82, 0x73, 0x64, /* SSRC */ +}; + +static u8 rtcp_head[] = { + /* SR off 42:8 len 28*/ + 0x80, 0xc8, /* SR type */ + 0x00, 0x06, /* len */ + 0x91, 0x82, 0x73, 0x64, /* SSRC */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* NTP */ + 0x73, 0x64, 0x00, 0x00, /* RTP TS */ + 0x00, 0x00, 0x00, 0x00, /* packet count */ + 0x00, 0x00, 0x00, 0x00, /* octet count */ + /* SDES off 70:36 len 20 */ + 0x81, 0xca, /* SDES */ + 0x00, 0x03, /* len */ + 0x91, 0x82, 0x73, 0x64, /* SSRC */ + 0x01, 0x05, /* CNAME item */ + 0x53, 0x41, 0x54, 0x49, 0x50, /* "SATIP" */ + 0x00, /* item type 0 */ + /* APP off 86:52 len 16+string length */ + 0x80, 0xcc, /* APP */ + 0x00, 0x04, /* len */ + 0x91, 0x82, 0x73, 0x64, /* SSRC */ + 0x53, 0x45, 0x53, 0x31, /* "SES1" */ + 0x00, 0x00, /* identifier */ + 0x00, 0x00, /* string length */ + /* string off 102:68 */ +}; + +static int ns_set_rtcp_msg(struct dvbnss *nss, u8 *msg, u32 len) +{ + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + u32 off = STREAM_PACKET_ADR(dns->nr); + u32 coff = 96; + u16 wlen; + + //printk("%s len=%d\n", __func__, len); + + if (!len) { + ddbwritel(dev, ddbreadl(dev, STREAM_CONTROL(dns->nr)) & ~0x10, + STREAM_CONTROL(dns->nr)); + return 0; + } + if (copy_from_user(dns->p + coff + dns->rtcp_len, msg, len)) + return -EFAULT; + dns->p[coff + dns->rtcp_len - 2] = (len >> 8); + dns->p[coff + dns->rtcp_len - 1] = (len & 0xff); + if (len & 3) { + u32 pad = 4 - (len & 3); + memset(dns->p + coff + dns->rtcp_len + len, 0, pad); + len += pad; + } + wlen = len / 4; + wlen += 3; + dns->p[coff + dns->rtcp_len - 14] = (wlen >> 8); + dns->p[coff + dns->rtcp_len - 13] = (wlen & 0xff); + ddbcpyto(dev, off, dns->p, sizeof(dns->p)); + ddbwritel(dev, (dns->rtcp_udplen + len) | ((STREAM_PACKET_OFF(dns->nr) + coff) << 16), + STREAM_RTCP_PACKET(dns->nr)); + ddbwritel(dev, ddbreadl(dev, STREAM_CONTROL(dns->nr)) | 0x10, + STREAM_CONTROL(dns->nr)); + return 0; +} + +static u32 set_nsbuf(struct dvb_ns_params *p, u8 *buf, u32 *udplen, int rtcp) +{ + u32 c = 0; + u16 pcs; + u16 sport, dport; + + sport = rtcp ? p->sport2 : p->sport; + dport = rtcp ? p->dport2 : p->dport; + + /* MAC header */ + memcpy(buf + c, p->dmac, 6); + memcpy(buf + c + 6, p->smac, 6); + c += 12; + if (vlan) { + buf[c + 0] = 0x81; + buf[c + 1] = 0x00; + buf[c + 2] = ((p->qos & 7) << 5) | ((p->vlan & 0xf00) >> 8) ; + buf[c + 3] = p->vlan & 0xff; + c += 4; + } + buf[c + 0] = 0x08; + buf[c + 1] = 0x00; + c += 2; + + /* IP header */ + if (p->flags & DVB_NS_IPV6) { + u8 ip6head[8] = { 0x65, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x11, 0x00, }; + memcpy(buf + c, ip6head, sizeof(ip6head)); + buf[c + 7] = p->ttl; + memcpy(buf + c + 8, p->sip, 16); + memcpy(buf + c + 24, p->dip, 16); + c += 40; + + /* UDP */ + buf[c + 0] = sport >> 8; + buf[c + 1] = sport & 0xff; + buf[c + 2] = dport >> 8; + buf[c + 3] = dport & 0xff; + buf[c + 4] = 0; /* length */ + buf[c + 5] = 0; + pcs = calc_pcs16(p, p->flags & DVB_NS_IPV6); + buf[c + 6] = pcs >> 8; + buf[c + 7] = pcs & 0xff; + c += 8; + *udplen = 8; + + } else { + u8 ip4head[12] = { 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x00, 0x40, 0x11, 0x00, 0x00 }; + + memcpy(buf + c, ip4head, sizeof(ip4head)); + buf[c + 8] = p->ttl; + memcpy(buf + c + 12, p->sip, 4); + memcpy(buf + c + 16, p->dip, 4); + c += 20; + + /* UDP */ + buf[c + 0] = sport >> 8; + buf[c + 1] = sport & 0xff; + buf[c + 2] = dport >> 8; + buf[c + 3] = dport & 0xff; + buf[c + 4] = 0; /* length */ + buf[c + 5] = 0; + pcs = calc_pcs(p); + buf[c + 6] = pcs >> 8; + buf[c + 7] = pcs & 0xff; + c += 8; + *udplen = 8; + } + + if (rtcp) { + memcpy(buf + c, rtcp_head, sizeof(rtcp_head)); + memcpy(buf + c + 4, p->ssrc, 4); + memcpy(buf + c + 32, p->ssrc, 4); + memcpy(buf + c + 48, p->ssrc, 4); + c += sizeof(rtcp_head); + *udplen += sizeof(rtcp_head); + } else if (p->flags & DVB_NS_RTP) { + memcpy(buf + c, rtp_head, sizeof(rtp_head)); + memcpy(buf + c + 8, p->ssrc, 4); + c += sizeof(rtp_head); + *udplen += sizeof(rtp_head); + } + return c; +} + +static int ns_set_ts_packets(struct dvbnss *nss, u8 *buf, u32 len) +{ + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + u32 off = STREAM_PACKET_ADR(dns->nr); + + if (nss->params.flags & DVB_NS_RTCP) + return -EINVAL; + + if (copy_from_user(dns->p + dns->ts_offset, buf, len)) + return -EFAULT; + ddbcpyto(dev, off, dns->p, sizeof(dns->p)); + return 0; +} + +static int ns_insert_ts_packets(struct dvbnss *nss, u8 count) +{ + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + u32 value = count; + + if (nss->params.flags & DVB_NS_RTCP) + return -EINVAL; + + if (count < 1 || count > 2) + return -EINVAL; + + ddbwritel(dev, value, STREAM_INSERT_PACKET(dns->nr)); + return 0; +} + +static int ns_set_net(struct dvbnss *nss) +{ + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + struct dvb_ns_params *p = &nss->params; + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + u32 off = STREAM_PACKET_ADR(dns->nr); + u32 coff = 96; + + dns->ts_offset = set_nsbuf(p, dns->p, &dns->udplen, 0); + if (nss->params.flags & DVB_NS_RTCP) + dns->rtcp_len = set_nsbuf(p, dns->p + coff, &dns->rtcp_udplen, 1); + ddbcpyto(dev, off, dns->p, sizeof(dns->p)); + ddbwritel(dev, dns->udplen | (STREAM_PACKET_OFF(dns->nr) << 16), + STREAM_RTP_PACKET(dns->nr)); + ddbwritel(dev, dns->rtcp_udplen | ((STREAM_PACKET_OFF(dns->nr) + coff) << 16), + STREAM_RTCP_PACKET(dns->nr)); + return 0; +} + +static int ns_start(struct dvbnss *nss) +{ + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + u32 reg = 0x8003; + + + if (nss->params.flags & DVB_NS_RTCP) + reg |= 0x10; + if (nss->params.flags & DVB_NS_RTP_TO) + reg |= 0x20; + if (nss->params.flags & DVB_NS_RTP) + reg |= 0x40; + if (nss->params.flags & DVB_NS_IPV6) + reg |= 0x80; + if (dns->fe != input->nr) + ddb_dvb_input_start(&dev->input[dns->fe]); + ddb_dvb_input_start(input); + ddbwritel(dev, reg | (dns->fe << 8), STREAM_CONTROL(dns->nr)); + return 0; +} + +static int ns_stop(struct dvbnss *nss) +{ + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + struct dvb_netstream *ns = nss->ns; + struct ddb_input *input = ns->priv; + struct ddb *dev = input->port->dev; + + ddbwritel(dev, 0x00, STREAM_CONTROL(dns->nr)); + ddb_dvb_input_stop(input); + if (dns->fe != input->nr) + ddb_dvb_input_stop(&dev->input[dns->fe]); + return 0; +} + +static int netstream_init(struct ddb_input *input) +{ + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_adapter *adap = dvb->adap; + struct dvb_netstream *ns = &dvb->dvbns; + struct ddb *dev = input->port->dev; + int i, res; + + ddbmemset(dev, STREAM_PIDS(input->nr), 0x00, 0x400); + if (dev->devid == 0x0301dd01) + dev->ns_num = 15; + else + dev->ns_num = 12; + for (i = 0; i < dev->ns_num; i++) + dev->ns[i].nr = i; + ns->priv = input; + ns->set_net = ns_set_net; + ns->set_rtcp_msg = ns_set_rtcp_msg; + ns->set_ts_packets = ns_set_ts_packets; + ns->insert_ts_packets = ns_insert_ts_packets; + ns->set_pid = ns_set_pid; + ns->set_pids = ns_set_pids; + ns->set_ci = ns_set_ci; + ns->start = ns_start; + ns->stop = ns_stop; + ns->alloc = ns_alloc; + ns->free = ns_free; + res = dvb_netstream_init(adap, ns); + return res; +} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-regs.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-regs.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-regs.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge-regs.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,399 @@ +/* + * ddbridge-regs.h: Digital Devices PCIe bridge driver + * + * Copyright (C) 2010-2013 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +/* Register Definitions */ + +#define CUR_REGISTERMAP_VERSION 0x10003 +#define CUR_REGISTERMAP_VERSION_CI 0x10000 +#define CUR_REGISTERMAP_VERSION_MOD 0x10000 + +#define HARDWARE_VERSION 0x00 +#define REGISTERMAP_VERSION 0x04 + +/* ------------------------------------------------------------------------- */ +/* SPI Controller */ + +#define SPI_CONTROL 0x10 +#define SPI_DATA 0x14 + +/* ------------------------------------------------------------------------- */ +/* GPIO */ + +#define GPIO_OUTPUT 0x20 +#define GPIO_INPUT 0x24 +#define GPIO_DIRECTION 0x28 + +/* ------------------------------------------------------------------------- */ +/* MDIO */ + +#define MDIO_CTRL 0x20 +#define MDIO_ADR 0x24 +#define MDIO_REG 0x28 +#define MDIO_VAL 0x2C + +/* ------------------------------------------------------------------------- */ + +/* Interrupt controller +// How many MSI's are available depends on HW (Min 2 max 8) +// How many are usable also depends on Host platform +*/ + +#define INTERRUPT_BASE (0x40) + +#define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) +#define MSI0_ENABLE (INTERRUPT_BASE + 0x00) +#define MSI1_ENABLE (INTERRUPT_BASE + 0x04) +#define MSI2_ENABLE (INTERRUPT_BASE + 0x08) +#define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) +#define MSI4_ENABLE (INTERRUPT_BASE + 0x10) +#define MSI5_ENABLE (INTERRUPT_BASE + 0x14) +#define MSI6_ENABLE (INTERRUPT_BASE + 0x18) +#define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) + +#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) +#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) + +#define INTMASK_CLOCKGEN (0x00000001) +#define INTMASK_TEMPMON (0x00000002) + +#define INTMASK_I2C1 (0x00000001) +#define INTMASK_I2C2 (0x00000002) +#define INTMASK_I2C3 (0x00000004) +#define INTMASK_I2C4 (0x00000008) + +#define INTMASK_CIRQ1 (0x00000010) +#define INTMASK_CIRQ2 (0x00000020) +#define INTMASK_CIRQ3 (0x00000040) +#define INTMASK_CIRQ4 (0x00000080) + +#define INTMASK_TSINPUT1 (0x00000100) +#define INTMASK_TSINPUT2 (0x00000200) +#define INTMASK_TSINPUT3 (0x00000400) +#define INTMASK_TSINPUT4 (0x00000800) +#define INTMASK_TSINPUT5 (0x00001000) +#define INTMASK_TSINPUT6 (0x00002000) +#define INTMASK_TSINPUT7 (0x00004000) +#define INTMASK_TSINPUT8 (0x00008000) + +#define INTMASK_TSOUTPUT1 (0x00010000) +#define INTMASK_TSOUTPUT2 (0x00020000) +#define INTMASK_TSOUTPUT3 (0x00040000) +#define INTMASK_TSOUTPUT4 (0x00080000) + + +// Clock Generator ( Sil598 @ 0xAA I2c ) +#define CLOCKGEN_BASE (0x80) +#define CLOCKGEN_CONTROL (CLOCKGEN_BASE + 0x00) +#define CLOCKGEN_INDEX (CLOCKGEN_BASE + 0x04) +#define CLOCKGEN_WRITEDATA (CLOCKGEN_BASE + 0x08) +#define CLOCKGEN_READDATA (CLOCKGEN_BASE + 0x0C) + +// DAC ( AD9781/AD9783 SPI ) +#define DAC_BASE (0x090) +#define DAC_CONTROL (DAC_BASE) +#define DAC_WRITE_DATA (DAC_BASE+4) +#define DAC_READ_DATA (DAC_BASE+8) + +#define DAC_CONTROL_INSTRUCTION_REG (0xFF) +#define DAC_CONTROL_STARTIO (0x100) +#define DAC_CONTROL_RESET (0x200) + +// Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) +#define TEMPMON_BASE (0xA0) +#define TEMPMON_CONTROL (TEMPMON_BASE + 0x00) +#define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08) // SHORT Temperature in °C x 256 +#define TEMPMON_SENSOR2 (TEMPMON_BASE + 0x0C) // SHORT Temperature in °C x 256 + +// +// -------------------------------------------------------------------------- + + +/* ------------------------------------------------------------------------- */ +/* I2C Master Controller */ + +#define I2C_BASE (0x80) /* Byte offset */ + +#define I2C_COMMAND (0x00) +#define I2C_TIMING (0x04) +#define I2C_TASKLENGTH (0x08) /* High read, low write */ +#define I2C_TASKADDRESS (0x0C) /* High read, low write */ +#define I2C_MONITOR (0x1C) + +#define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) + +#define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ +#define I2C_TASKMEM_SIZE (0x0800) + +#define I2C_SPEED_400 (0x04030404) +#define I2C_SPEED_200 (0x09080909) +#define I2C_SPEED_154 (0x0C0B0C0C) +#define I2C_SPEED_100 (0x13121313) +#define I2C_SPEED_77 (0x19181919) +#define I2C_SPEED_50 (0x27262727) + + +/* ------------------------------------------------------------------------- */ +/* DMA Controller */ + +#define DMA_BASE_WRITE (0x100) +#define DMA_BASE_READ (0x140) + +#define DMA_CONTROL (0x00) +#define DMA_ERROR (0x04) + +#define DMA_DIAG_CONTROL (0x1C) +#define DMA_DIAG_PACKETCOUNTER_LOW (0x20) +#define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) +#define DMA_DIAG_TIMECOUNTER_LOW (0x28) +#define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) +#define DMA_DIAG_RECHECKCOUNTER (0x30) +#define DMA_DIAG_WAITTIMEOUTINIT (0x34) +#define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) +#define DMA_DIAG_WAITCOUNTER (0x3C) + +/* ------------------------------------------------------------------------- */ +/* DMA Buffer */ + +#define TS_INPUT_BASE (0x200) +#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 0x10 + 0x00) +#define TS_INPUT_CONTROL2(i) (TS_INPUT_BASE + (i) * 0x10 + 0x04) + +#define TS_OUTPUT_BASE (0x280) +#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x00) +#define TS_OUTPUT_CONTROL2(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x04) + +#define DMA_BUFFER_BASE (0x300) + +#define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x00) +#define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x04) +#define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x08) +#define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 0x10 + 0x0c) + +#define DMA_BASE_ADDRESS_TABLE (0x2000) +#define DMA_BASE_ADDRESS_TABLE_ENTRIES (512) + +/* ------------------------------------------------------------------------- */ +/* CI Interface (only CI-Bridge) */ + +#define CI_BASE (0x400) +#define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00) + +#define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04) +#define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08) +#define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c) +#define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10) + +#define CI_RESET_CAM (0x00000001) +#define CI_POWER_ON (0x00000002) +#define CI_ENABLE (0x00000004) +#define CI_BLOCKIO_ENABLE (0x00000008) +#define CI_BYPASS_DISABLE (0x00000010) +#define CI_DISABLE_AUTO_OFF (0x00000020) + +#define CI_CAM_READY (0x00010000) +#define CI_CAM_DETECT (0x00020000) +#define CI_READY (0x80000000) +#define CI_BLOCKIO_ACTIVE (0x40000000) +#define CI_BLOCKIO_RCVDATA (0x20000000) +#define CI_BLOCKIO_SEND_PENDING (0x10000000) +#define CI_BLOCKIO_SEND_COMPLETE (0x08000000) + +#define CI_READ_CMD (0x40000000) +#define CI_WRITE_CMD (0x80000000) + +#define CI_BLOCKIO_SEND(i) (CI_BASE + (i) * 32 + 0x14) +#define CI_BLOCKIO_RECEIVE(i) (CI_BASE + (i) * 32 + 0x18) + +#define CI_BLOCKIO_SEND_COMMAND (0x80000000) +#define CI_BLOCKIO_SEND_COMPLETE_ACK (0x40000000) +#define CI_BLOCKIO_RCVDATA_ACK (0x40000000) + +#define CI_BUFFER_BASE (0x3000) +#define CI_BUFFER_SIZE (0x0800) +#define CI_BLOCKIO_BUFFER_SIZE (CI_BUFFER_SIZE/2) + +#define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE ) +#define CI_BLOCKIO_RECEIVE_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE ) +#define CI_BLOCKIO_SEND_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE + CI_BLOCKIO_BUFFER_SIZE ) + +#define VCO1_BASE (0xC0) +#define VCO1_CONTROL (VCO1_BASE + 0x00) +#define VCO1_DATA (VCO1_BASE + 0x04) // 24 Bit +#define VCO1_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done +#define VCO1_CONTROL_CE (0x00000002) // 0 = Put VCO into power down +#define VCO1_CONTROL_MUXOUT (0x00000004) // Muxout from VCO (usually = Lock) + +#define VCO2_BASE (0xC8) +#define VCO2_CONTROL (VCO2_BASE + 0x00) +#define VCO2_DATA (VCO2_BASE + 0x04) // 24 Bit +#define VCO2_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done +#define VCO2_CONTROL_CE (0x00000002) // 0 = Put VCO into power down +#define VCO2_CONTROL_MUXOUT (0x00000004) // Muxout from VCO (usually = Lock) + +#define VCO3_BASE (0xD0) +#define VCO3_CONTROL (VCO3_BASE + 0x00) +#define VCO3_DATA (VCO3_BASE + 0x04) // 32 Bit +#define VCO3_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done +#define VCO3_CONTROL_CE (0x00000002) // 0 = Put VCO into power down +#define VCO3_CONTROL_MUXOUT (0x00000004) // Muxout from VCO (usually = Lock) + +#define RF_ATTENUATOR (0xD8) +// 0x00 = 0 dB +// 0x01 = 1 dB +// ... +// 0x1F = 31 dB + +#define RF_POWER (0xE0) +#define RF_POWER_BASE (0xE0) +#define RF_POWER_CONTROL (RF_POWER_BASE + 0x00) +#define RF_POWER_DATA (RF_POWER_BASE + 0x04) + +#define RF_POWER_CONTROL_START (0x00000001) +#define RF_POWER_CONTROL_DONE (0x00000002) +#define RF_POWER_CONTROL_VALIDMASK (0x00000700) +#define RF_POWER_CONTROL_VALID (0x00000500) + + +// -------------------------------------------------------------------------- +// Output control + +#define IQOUTPUT_BASE (0x240) +#define IQOUTPUT_CONTROL (IQOUTPUT_BASE + 0x00) +#define IQOUTPUT_CONTROL2 (IQOUTPUT_BASE + 0x04) +#define IQOUTPUT_PEAK_DETECTOR (IQOUTPUT_BASE + 0x08) +#define IQOUTPUT_POSTSCALER (IQOUTPUT_BASE + 0x0C) +#define IQOUTPUT_PRESCALER (IQOUTPUT_BASE + 0x10) + +#define IQOUTPUT_EQUALIZER_0 (IQOUTPUT_BASE + 0x14) +#define IQOUTPUT_EQUALIZER_1 (IQOUTPUT_BASE + 0x18) +#define IQOUTPUT_EQUALIZER_2 (IQOUTPUT_BASE + 0x1C) +#define IQOUTPUT_EQUALIZER_3 (IQOUTPUT_BASE + 0x20) +#define IQOUTPUT_EQUALIZER_4 (IQOUTPUT_BASE + 0x24) +#define IQOUTPUT_EQUALIZER_5 (IQOUTPUT_BASE + 0x28) +#define IQOUTPUT_EQUALIZER_6 (IQOUTPUT_BASE + 0x2C) +#define IQOUTPUT_EQUALIZER_7 (IQOUTPUT_BASE + 0x30) +#define IQOUTPUT_EQUALIZER_8 (IQOUTPUT_BASE + 0x34) +#define IQOUTPUT_EQUALIZER_9 (IQOUTPUT_BASE + 0x38) +#define IQOUTPUT_EQUALIZER_10 (IQOUTPUT_BASE + 0x3C) + +#define IQOUTPUT_EQUALIZER(i) (IQOUTPUT_EQUALIZER_0 + (i) * 4 ) + +#define IQOUTPUT_CONTROL_RESET (0x00000001) +#define IQOUTPUT_CONTROL_ENABLE (0x00000002) +#define IQOUTPUT_CONTROL_RESET_PEAK (0x00000004) +#define IQOUTPUT_CONTROL_ENABLE_PEAK (0x00000008) +#define IQOUTPUT_CONTROL_BYPASS_EQUALIZER (0x00000010) + + +// -------------------------------------------------------------------------- +// + +#define MODULATOR_BASE (0x200) +#define MODULATOR_CONTROL (MODULATOR_BASE) +#define MODULATOR_IQTABLE_END (MODULATOR_BASE+4) +#define MODULATOR_IQTABLE_INDEX (MODULATOR_BASE+8) +#define MODULATOR_IQTABLE_DATA (MODULATOR_BASE+12) + +#define MODULATOR_IQTABLE_INDEX_CHANNEL_MASK ( 0x000F0000 ) +#define MODULATOR_IQTABLE_INDEX_IQ_MASK ( 0x00008000 ) +#define MODULATOR_IQTABLE_INDEX_ADDRESS_MASK ( 0x000007FF ) +#define MODULATOR_IQTABLE_INDEX_SEL_I ( 0x00000000 ) +#define MODULATOR_IQTABLE_INDEX_SEL_Q ( MODULATOR_IQTABLE_INDEX_IQ_MASK ) +#define MODULATOR_IQTABLE_SIZE (2048) + + +// -------------------------------------------------------------------------- +// Modulator Channels + +#define CHANNEL_BASE (0x400) +#define CHANNEL_CONTROL(i) (CHANNEL_BASE + (i) * 64 + 0x00) +#define CHANNEL_SETTINGS(i) (CHANNEL_BASE + (i) * 64 + 0x04) +#define CHANNEL_RATE_INCR(i) (CHANNEL_BASE + (i) * 64 + 0x0C) +#define CHANNEL_PCR_ADJUST_OUTL(i) (CHANNEL_BASE + (i) * 64 + 0x10) +#define CHANNEL_PCR_ADJUST_OUTH(i) (CHANNEL_BASE + (i) * 64 + 0x14) +#define CHANNEL_PCR_ADJUST_INL(i) (CHANNEL_BASE + (i) * 64 + 0x18) +#define CHANNEL_PCR_ADJUST_INH(i) (CHANNEL_BASE + (i) * 64 + 0x1C) +#define CHANNEL_PCR_ADJUST_ACCUL(i) (CHANNEL_BASE + (i) * 64 + 0x20) +#define CHANNEL_PCR_ADJUST_ACCUH(i) (CHANNEL_BASE + (i) * 64 + 0x24) +#define CHANNEL_PKT_COUNT_OUT(i) (CHANNEL_BASE + (i) * 64 + 0x28) +#define CHANNEL_PKT_COUNT_IN(i) (CHANNEL_BASE + (i) * 64 + 0x2C) + +#define CHANNEL_CONTROL_RESET (0x00000001) +#define CHANNEL_CONTROL_ENABLE_DVB (0x00000002) +#define CHANNEL_CONTROL_ENABLE_IQ (0x00000004) +#define CHANNEL_CONTROL_ENABLE_SOURCE (0x00000008) +#define CHANNEL_CONTROL_ENABLE_PCRADJUST (0x00000010) +#define CHANNEL_CONTROL_FREEZE_STATUS (0x00000100) + +#define CHANNEL_CONTROL_RESET_ERROR (0x00010000) +#define CHANNEL_CONTROL_BUSY (0x01000000) +#define CHANNEL_CONTROL_ERROR_SYNC (0x20000000) +#define CHANNEL_CONTROL_ERROR_UNDERRUN (0x40000000) +#define CHANNEL_CONTROL_ERROR_FATAL (0x80000000) + +#define CHANNEL_SETTINGS_QAM_MASK (0x00000007) +#define CHANNEL_SETTINGS_QAM16 (0x00000000) +#define CHANNEL_SETTINGS_QAM32 (0x00000001) +#define CHANNEL_SETTINGS_QAM64 (0x00000002) +#define CHANNEL_SETTINGS_QAM128 (0x00000003) +#define CHANNEL_SETTINGS_QAM256 (0x00000004) + + +/* OCTONET */ + +#define ETHER_BASE (0x100) +#define ETHER_CONTROL (ETHER_BASE + 0x00) +#define ETHER_LENGTH (ETHER_BASE + 0x04) + +#define RTP_MASTER_BASE (0x120) +#define RTP_MASTER_CONTROL (RTP_MASTER_BASE + 0x00) +#define RTP_RTCP_INTERRUPT (RTP_MASTER_BASE + 0x04) +#define RTP_MASTER_RTCP_SETTINGS (RTP_MASTER_BASE + 0x0c) + +#define STREAM_BASE (0x400) +#define STREAM_CONTROL(i) (STREAM_BASE + (i) * 0x20 + 0x00) +#define STREAM_RTP_PACKET(i) (STREAM_BASE + (i) * 0x20 + 0x04) +#define STREAM_RTCP_PACKET(i) (STREAM_BASE + (i) * 0x20 + 0x08) +#define STREAM_RTP_SETTINGS(i) (STREAM_BASE + (i) * 0x20 + 0x0c) +#define STREAM_INSERT_PACKET(i) (STREAM_BASE + (i) * 0x20 + 0x10) + +#define STREAM_PACKET_OFF(i) ((i) * 0x200) +#define STREAM_PACKET_ADR(i) (0x2000 + (STREAM_PACKET_OFF(i))) + +#define STREAM_PIDS(i) (0x4000 + (i) * 0x400) + +#define TS_CAPTURE_BASE (0x0140) +#define TS_CAPTURE_CONTROL (TS_CAPTURE_BASE + 0x00) +#define TS_CAPTURE_PID (TS_CAPTURE_BASE + 0x04) +#define TS_CAPTURE_RECEIVED (TS_CAPTURE_BASE + 0x08) +#define TS_CAPTURE_TIMEOUT (TS_CAPTURE_BASE + 0x0c) +#define TS_CAPTURE_TABLESECTION (TS_CAPTURE_BASE + 0x10) + +#define TS_CAPTURE_MEMORY (0x7000) + +#define PID_FILTER_BASE (0x800) +#define PID_FILTER_SYSTEM_PIDS(i) (PID_FILTER_BASE + (i) * 0x20) +#define PID_FILTER_PID(i, j) (PID_FILTER_BASE + (i) * 0x20 + (j) * 4) + + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,432 @@ +/* + * ddbridge.c: Digital Devices PCIe bridge driver + * + * Copyright (C) 2010-2013 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +//#define DDB_ALT_DMA +#define DDB_USE_WORK +//#define DDB_TEST_THREADED +#undef CONFIG_PCI_MSI + +#include "ddbridge.h" +#include "ddbridge-regs.h" + +#include "tda18271c2dd.h" +#include "stv6110x.h" +#include "stv090x.h" +#include "lnbh24.h" +#include "drxk.h" +#include "stv0367.h" +#include "stv0367dd.h" +#include "tda18212.h" +#include "tda18212dd.h" +#include "cxd2843.h" + +static struct workqueue_struct *ddb_wq; + +static int adapter_alloc; +module_param(adapter_alloc, int, 0444); +MODULE_PARM_DESC(adapter_alloc, "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); + +#include "ddbridge-core.c" + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static void ddb_unmap(struct ddb *dev) +{ + if (dev->regs) + iounmap(dev->regs); + vfree(dev); +} + + +static void __devexit ddb_remove(struct pci_dev *pdev) +{ + struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev); + + ddb_ports_detach(dev); + ddb_i2c_release(dev); + + ddbwritel(dev, 0, INTERRUPT_ENABLE); + ddbwritel(dev, 0, MSI1_ENABLE); + if (dev->msi == 2) + free_irq(dev->pdev->irq + 1, dev); + free_irq(dev->pdev->irq, dev); +#ifdef CONFIG_PCI_MSI + if (dev->msi) + pci_disable_msi(dev->pdev); +#endif + ddb_ports_release(dev); + ddb_buffers_free(dev); + ddb_device_destroy(dev); + + ddb_unmap(dev); + pci_set_drvdata(pdev, 0); + pci_disable_device(pdev); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) +#define __devinit +#define __devinitdata +#endif + +static int __devinit ddb_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct ddb *dev; + int stat = 0; + int irq_flag = IRQF_SHARED; + + if (pci_enable_device(pdev) < 0) + return -ENODEV; + + dev = vzalloc(sizeof(struct ddb)); + if (dev == NULL) + return -ENOMEM; + + dev->has_dma = 1; + dev->pdev = pdev; + dev->dev = &pdev->dev; + pci_set_drvdata(pdev, dev); + dev->id = id; + dev->info = (struct ddb_info *) id->driver_data; + printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); + + dev->regs_len = pci_resource_len(dev->pdev, 0); + dev->regs = ioremap(pci_resource_start(dev->pdev, 0), + pci_resource_len(dev->pdev, 0)); + if (!dev->regs) { + printk("DDBridge: not enough memory for register map\n"); + stat = -ENOMEM; + goto fail; + } + if (ddbreadl(dev, 0) == 0xffffffff) { + printk("DDBridge: cannot read registers\n"); + stat = -ENODEV; + goto fail; + } + + dev->hwid = ddbreadl(dev, 0); + dev->regmapid = ddbreadl(dev, 4); + + printk(KERN_INFO "HW %08x REGMAP %08x\n", + dev->hwid, dev->regmapid); + + ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); + ddbwritel(dev, 0x00000000, MSI1_ENABLE); + ddbwritel(dev, 0x00000000, MSI2_ENABLE); + ddbwritel(dev, 0x00000000, MSI3_ENABLE); + ddbwritel(dev, 0x00000000, MSI4_ENABLE); + ddbwritel(dev, 0x00000000, MSI5_ENABLE); + ddbwritel(dev, 0x00000000, MSI6_ENABLE); + ddbwritel(dev, 0x00000000, MSI7_ENABLE); + +#ifdef CONFIG_PCI_MSI + if (pci_msi_enabled()) { + stat = pci_enable_msi_block(dev->pdev, 2); + if (stat == 0) { + dev->msi = 1; + printk("DDBrige using 2 MSI interrupts\n"); + } + if (stat == 1) + stat = pci_enable_msi(dev->pdev); + if (stat < 0) { + printk(KERN_INFO ": MSI not available.\n"); + } else { + irq_flag = 0; + dev->msi++; + } + } +#endif + if (dev->msi == 2) { + stat = request_irq(dev->pdev->irq, irq_handler0, + irq_flag, "ddbridge", (void *) dev); + if (stat < 0) + goto fail0; + stat = request_irq(dev->pdev->irq + 1, irq_handler1, + irq_flag, "ddbridge", (void *) dev); + if (stat < 0) { + free_irq(dev->pdev->irq, dev); + goto fail0; + } + } else { +#ifdef DDB_TEST_THREADED + stat = request_threaded_irq(dev->pdev->irq, irq_handler, + irq_thread, + irq_flag, + "ddbridge", (void *) dev); +#else + stat = request_irq(dev->pdev->irq, irq_handler, + irq_flag, "ddbridge", (void *) dev); +#endif + if (stat < 0) + goto fail0; + } + ddbwritel(dev, 0, DMA_BASE_READ); + if (dev->info->type != DDB_MOD) + ddbwritel(dev, 0, DMA_BASE_WRITE); + + //ddbwritel(dev, 0xffffffff, INTERRUPT_ACK); + if (dev->msi == 2) { + ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE); + ddbwritel(dev, 0x0000000f, MSI1_ENABLE); + } else { + ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); + ddbwritel(dev, 0x00000000, MSI1_ENABLE); + } + if (ddb_i2c_init(dev) < 0) + goto fail1; + ddb_ports_init(dev); + if (ddb_buffers_alloc(dev) < 0) { + printk(KERN_INFO ": Could not allocate buffer memory\n"); + goto fail2; + } + if (ddb_ports_attach(dev) < 0) + goto fail3; + + /* ignore if this fails */ + ddb_device_create(dev); + + if (dev->info->fan_num) { + ddbwritel(dev, 1, GPIO_DIRECTION); + ddbwritel(dev, 1, GPIO_OUTPUT); + } + if (dev->info->type == DDB_MOD) + ddbridge_mod_init(dev); + + return 0; + +fail3: + ddb_ports_detach(dev); + printk(KERN_ERR "fail3\n"); + ddb_ports_release(dev); +fail2: + printk(KERN_ERR "fail2\n"); + ddb_buffers_free(dev); + ddb_i2c_release(dev); +fail1: + printk(KERN_ERR "fail1\n"); + ddbwritel(dev, 0, INTERRUPT_ENABLE); + ddbwritel(dev, 0, MSI1_ENABLE); + free_irq(dev->pdev->irq, dev); + if (dev->msi == 2) + free_irq(dev->pdev->irq + 1, dev); +fail0: + printk(KERN_ERR "fail0\n"); + if (dev->msi) + pci_disable_msi(dev->pdev); +fail: + printk(KERN_ERR "fail\n"); + ddb_unmap(dev); + pci_set_drvdata(pdev, 0); + pci_disable_device(pdev); + return -1; +} + +/******************************************************************************/ +/******************************************************************************/ +/******************************************************************************/ + +struct ddb_regset octopus_i2c = { + .base = 0x80, + .num = 0x04, + .size = 0x20, +}; + +static struct ddb_regmap octopus_map = { +// .i2c = octopus_i2c, +}; + +static struct ddb_info ddb_none = { + .type = DDB_NONE, + .name = "unknown Digital Devices PCIe card, install newer driver", +// .regmap = octopus_map, +}; + +static struct ddb_info ddb_octopus = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus DVB adapter", + .port_num = 4, + .i2c_num = 4, +}; + +static struct ddb_info ddb_octopusv3 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus V3 DVB adapter", + .port_num = 4, + .i2c_num = 4, +}; + +static struct ddb_info ddb_octopus_le = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus LE DVB adapter", + .port_num = 2, + .i2c_num = 2, +}; + +static struct ddb_info ddb_octopus_oem = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus OEM", + .port_num = 4, + .i2c_num = 4, + .led_num = 1, + .fan_num = 1, + .temp_num = 1, + .temp_bus = 0, +}; + +static struct ddb_info ddb_octopus_mini = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus Mini", + .port_num = 4, + .i2c_num = 4, +}; + +static struct ddb_info ddb_v6 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Cine S2 V6 DVB adapter", + .port_num = 3, + .i2c_num = 3, +}; + +static struct ddb_info ddb_v6_5 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Cine S2 V6.5 DVB adapter", + .port_num = 4, + .i2c_num = 4, +}; + +static struct ddb_info ddb_satixS2v3 = { + .type = DDB_OCTOPUS, + .name = "Mystique SaTiX-S2 V3 DVB adapter", + .port_num = 3, + .i2c_num = 3, +}; + +static struct ddb_info ddb_ci = { + .type = DDB_OCTOPUS_CI, + .name = "Digital Devices Octopus CI", + .port_num = 4, + .i2c_num = 2, +}; + +static struct ddb_info ddb_cis = { + .type = DDB_OCTOPUS_CI, + .name = "Digital Devices Octopus CI single", + .port_num = 3, + .i2c_num = 2, +}; + +static struct ddb_info ddb_dvbct = { + .type = DDB_OCTOPUS, + .name = "Digital Devices DVBCT V6.1 DVB adapter", + .port_num = 3, + .i2c_num = 3, +}; + +static struct ddb_info ddb_mod = { + .type = DDB_MOD, + .name = "Digital Devices DVB-C modulator", + .port_num = 10, + .temp_num = 1, +}; + +static struct ddb_info ddb_octonet = { + .type = DDB_OCTONET, + .name = "Digital Devices Octopus Net", + .port_num = 4, + .i2c_num = 4, +}; + +#define DDVID 0xdd01 /* Digital Devices Vendor ID */ + +#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ + .vendor = _vend, .device = _dev, \ + .subvendor = _subvend, .subdevice = _subdev, \ + .driver_data = (unsigned long)&_driverdata } + +static const struct pci_device_id ddb_id_tbl[] __devinitdata = { + DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), + DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), + DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3), + DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), + DDB_ID(DDVID, 0x0003, DDVID, 0x0003, ddb_octopus_oem), + DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), + DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), + DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), + DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), + DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), + DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci), + DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis), + DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod), + /* in case sub-ids got deleted in flash */ + DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + {0} +}; +MODULE_DEVICE_TABLE(pci, ddb_id_tbl); + +static struct pci_driver ddb_pci_driver = { + .name = "ddbridge", + .id_table = ddb_id_tbl, + .probe = ddb_probe, + .remove = ddb_remove, +}; + +static __init int module_init_ddbridge(void) +{ + int stat = -1; + + printk(KERN_INFO "Digital Devices PCIE bridge driver 0.9.9, " + "Copyright (C) 2010-13 Digital Devices GmbH\n"); + if (ddb_class_create() < 0) + return -1; + ddb_wq = create_workqueue("ddbridge"); + if (ddb_wq == NULL) + goto exit1; + stat = pci_register_driver(&ddb_pci_driver); + if (stat < 0) + goto exit2; + return stat; +exit2: + destroy_workqueue(ddb_wq); +exit1: + ddb_class_destroy(); + return stat; +} + +static __exit void module_exit_ddbridge(void) +{ + pci_unregister_driver(&ddb_pci_driver); + destroy_workqueue(ddb_wq); + ddb_class_destroy(); +} + +module_init(module_init_ddbridge); +module_exit(module_exit_ddbridge); + +MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); +MODULE_AUTHOR("Ralph Metzler, Metzler Brothers Systementwicklung"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("0.9.9"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/ddbridge.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,477 @@ +/* + * ddbridge.h: Digital Devices PCIe bridge driver + * + * Copyright (C) 2010-2013 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DDBRIDGE_H_ +#define _DDBRIDGE_H_ + +#include + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) +#define __devexit +#define __devinit +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "dvb_netstream.h" +#include "dmxdev.h" +#include "dvbdev.h" +#include "dvb_demux.h" +#include "dvb_frontend.h" +#include "dvb_ringbuffer.h" +#include "dvb_ca_en50221.h" +#include "dvb_net.h" +#include "cxd2099.h" + +#define DDB_MAX_I2C 4 +#define DDB_MAX_PORT 10 +#define DDB_MAX_INPUT 8 +#define DDB_MAX_OUTPUT 10 + +struct ddb_regset { + uint32_t base; + uint32_t num; + uint32_t size; +}; + +struct ddb_regmap { + struct ddb_regset i2c; + struct ddb_regset i2c_buf; + struct ddb_regset dma; + struct ddb_regset dma_buf; + struct ddb_regset input; + struct ddb_regset output; + struct ddb_regset channel; + struct ddb_regset ci; + struct ddb_regset pid_filter; +}; + +struct ddb_info { + int type; +#define DDB_NONE 0 +#define DDB_OCTOPUS 1 +#define DDB_OCTOPUS_CI 2 +#define DDB_MOD 3 +#define DDB_OCTONET 4 + char *name; + int port_num; + int i2c_num; + int led_num; + int fan_num; + int temp_num; + int temp_bus; + struct ddb_regmap regmap; +}; + + +/* DMA_SIZE MUST be smaller than 256k and + MUST be divisible by 188 and 128 !!! */ + +#define DMA_MAX_BUFS 32 /* hardware table limit */ + +#define INPUT_DMA_BUFS 8 +#define INPUT_DMA_SIZE (128*47*21) +#define INPUT_DMA_IRQ_DIV 1 + +#define OUTPUT_DMA_BUFS 8 +#define OUTPUT_DMA_SIZE (128*47*21) +#define OUTPUT_DMA_IRQ_DIV 1 + +struct ddb; +struct ddb_port; + +struct ddb_dma { + void *io; + u32 nr; + dma_addr_t pbuf[DMA_MAX_BUFS]; + u8 *vbuf[DMA_MAX_BUFS]; + u32 num; + u32 size; + u32 div; + u32 bufreg; + +#ifdef DDB_USE_WORK + struct work_struct work; +#else + struct tasklet_struct tasklet; +#endif + spinlock_t lock; + wait_queue_head_t wq; + int running; + u32 stat; + u32 ctrl; + u32 cbuf; + u32 coff; +}; + +struct ddb_dvb { + struct dvb_adapter *adap; + int adap_registered; + struct dvb_device *dev; + struct dvb_frontend *fe; + struct dvb_frontend *fe2; + struct dmxdev dmxdev; + struct dvb_demux demux; + struct dvb_net dvbnet; + struct dvb_netstream dvbns; + struct dmx_frontend hw_frontend; + struct dmx_frontend mem_frontend; + int users; + int (*gate_ctrl)(struct dvb_frontend *, int); + int attached; +}; + +struct ddb_ci { + struct dvb_ca_en50221 en; + struct ddb_port *port; + u32 nr; + struct mutex lock; +}; + +struct ddb_io { + struct ddb_port *port; + u32 nr; + struct ddb_dma *dma; +// struct ddb_io *redirect; + struct ddb_io *redo; + struct ddb_io *redi; +}; + +#if 0 +struct ddb_input { + struct ddb_port *port; + u32 nr; + struct ddb_dma *dma; + struct ddb_output *redo; + struct ddb_input *redi; +}; + +struct ddb_output { + struct ddb_port *port; + u32 nr; + struct ddb_dma *dma; + struct ddb_output *redo; + struct ddb_input *redi; +}; +#else +#define ddb_output ddb_io +#define ddb_input ddb_io +#endif + +struct ddb_i2c { + struct ddb *dev; + u32 nr; + struct i2c_adapter adap; + u32 regs; + u32 rbuf; + u32 wbuf; +// int done; +// wait_queue_head_t wq; + struct completion completion; +}; + +struct ddb_port { + struct ddb *dev; + u32 nr; + struct ddb_i2c *i2c; + struct mutex i2c_gate_lock; + u32 class; +#define DDB_PORT_NONE 0 +#define DDB_PORT_CI 1 +#define DDB_PORT_TUNER 2 +#define DDB_PORT_LOOP 3 +#define DDB_PORT_MOD 4 + u32 type; +#define DDB_TUNER_NONE 0 +#define DDB_TUNER_DVBS_ST 1 +#define DDB_TUNER_DVBS_ST_AA 2 +#define DDB_TUNER_DVBCT_TR 3 +#define DDB_TUNER_DVBCT_ST 4 +#define DDB_CI_INTERNAL 5 +#define DDB_CI_EXTERNAL_SONY 6 +#define DDB_TUNER_XO2 16 +#define DDB_TUNER_DVBS 16 +#define DDB_TUNER_DVBCT2_SONY 17 +#define DDB_TUNER_ISDBT_SONY 18 +#define DDB_TUNER_DVBC2T2_SONY 19 +#define DDB_TUNER_ATSC_ST 20 +#define DDB_TUNER_DVBC2T2_ST 21 + + u32 adr; + + struct ddb_input *input[2]; + struct ddb_output *output; + struct dvb_ca_en50221 *en; + struct ddb_dvb dvb[2]; + u32 gap; + u32 obr; +}; + + +struct mod_base { + u32 frequency; + + u32 flat_start; + u32 flat_end; +}; + +struct mod_state { + u32 modulation; + + u32 do_handle; + + u32 rate_inc; + u32 Control; + u32 State; + u32 StateCounter; + s32 LastPCRAdjust; + s32 PCRAdjustSum; + s32 InPacketsSum; + s32 OutPacketsSum; + s64 PCRIncrement; + s64 PCRDecrement; + s32 PCRRunningCorr; + u32 OutOverflowPacketCount; + u32 InOverflowPacketCount; + u32 LastOutPacketCount; + u32 LastInPacketCount; + u64 LastOutPackets; + u64 LastInPackets; + u32 MinInputPackets; +}; + +#define CM_STARTUP_DELAY 2 +#define CM_AVERAGE 20 +#define CM_GAIN 10 + +#define HW_LSB_SHIFT 12 +#define HW_LSB_MASK 0x1000 + +#define CM_IDLE 0 +#define CM_STARTUP 1 +#define CM_ADJUST 2 + +#define TS_CAPTURE_LEN (21*188) + +/* net streaming hardware block */ + +#define DDB_NS_MAX 15 + +struct ddb_ns { + struct ddb_input *input; + int nr; + int fe; + u32 rtcp_udplen; + u32 rtcp_len; + u32 ts_offset; + u32 udplen; + u8 p[512]; +}; + +struct ddb { + struct pci_dev *pdev; + struct platform_device *pfdev; + struct device *dev; + const struct pci_device_id *id; + struct ddb_info *info; + int msi; + struct workqueue_struct *wq; + u32 has_dma; + u32 has_ns; + + struct ddb_regmap regmap; + unsigned char *regs; + u32 regs_len; + struct ddb_port port[DDB_MAX_PORT]; + struct ddb_i2c i2c[DDB_MAX_I2C]; + struct ddb_input input[DDB_MAX_INPUT]; + struct ddb_output output[DDB_MAX_OUTPUT]; + struct dvb_adapter adap[DDB_MAX_INPUT]; + struct ddb_dma dma[DDB_MAX_INPUT + DDB_MAX_OUTPUT]; + + void (*handler[32])(unsigned long); + unsigned long handler_data[32]; + + struct device *ddb_dev; + u32 ddb_dev_users; + u32 nr; + u8 iobuf[1028]; + + u8 leds; + u32 ts_irq; + u32 i2c_irq; + + u32 hwid; + u32 regmapid; + u32 mac; + u32 devid; + + int ns_num; + struct ddb_ns ns[DDB_NS_MAX]; + struct mutex mutex; + + struct dvb_device *nsd_dev; + u8 tsbuf[TS_CAPTURE_LEN]; + + struct mod_base mod_base; + struct mod_state mod[10]; +}; + + +/******************************************************************************/ + +static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr) +{ + writeb(val, (char *) (dev->regs+(adr))); +} + +static inline void ddbwritel(struct ddb *dev, u32 val, u32 adr) +{ + writel(val, (char *) (dev->regs+(adr))); +} + +static inline void ddbwritew(struct ddb *dev, u16 val, u32 adr) +{ + writew(val, (char *) (dev->regs+(adr))); +} + +static inline u32 ddbreadl(struct ddb *dev, u32 adr) +{ + return readl((char *) (dev->regs+(adr))); +} + +static inline u32 ddbreadb(struct ddb *dev, u32 adr) +{ + return readb((char *) (dev->regs+(adr))); +} + +#define ddbcpyto(_dev, _adr, _src, _count) \ + memcpy_toio((char *) (_dev->regs + (_adr)), (_src), (_count)) + +#define ddbcpyfrom(_dev, _dst, _adr, _count) \ + memcpy_fromio((_dst), (char *) (_dev->regs + (_adr)), (_count)) + +#define ddbmemset(_dev, _adr, _val, _count) \ + memset_io((char *) (_dev->regs + (_adr)), (_val), (_count)) + + +/******************************************************************************/ +/******************************************************************************/ +/******************************************************************************/ + +#define dd_uint8 u8 +#define dd_uint16 u16 +#define dd_int16 s16 +#define dd_uint32 u32 +#define dd_int32 s32 +#define dd_uint64 u64 +#define dd_int64 s64 + +#define DDMOD_FLASH_START 0x1000 + +struct DDMOD_FLASH_DS { + dd_uint32 Symbolrate; /* kSymbols/s */ + dd_uint32 DACFrequency; /* kHz */ + dd_uint16 FrequencyResolution; /* kHz */ + dd_uint16 IQTableLength; + dd_uint16 FrequencyFactor; + dd_int16 PhaseCorr; /* TBD */ + dd_uint32 Control2; + dd_uint16 PostScaleI; + dd_uint16 PostScaleQ; + dd_uint16 PreScale; + dd_int16 EQTap[11]; + dd_uint16 FlatStart; + dd_uint16 FlatEnd; + dd_uint32 FlashOffsetPrecalculatedIQTables; /* 0 = none */ + dd_uint8 Reserved[28]; + +}; + +struct DDMOD_FLASH { + dd_uint32 Magic; + dd_uint16 Version; + dd_uint16 DataSets; + + dd_uint16 VCORefFrequency; /* MHz */ + dd_uint16 VCO1Frequency; /* MHz */ + dd_uint16 VCO2Frequency; /* MHz */ + + dd_uint16 DACAux1; /* TBD */ + dd_uint16 DACAux2; /* TBD */ + + dd_uint8 Reserved1[238]; + + struct DDMOD_FLASH_DS DataSet[1]; +}; + +#define DDMOD_FLASH_MAGIC 0x5F564d5F + + +int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg); +int ddbridge_mod_init(struct ddb *dev); +void ddbridge_mod_output_stop(struct ddb_output *output); +void ddbridge_mod_output_start(struct ddb_output *output); +void ddbridge_mod_rate_handler(unsigned long data); + + +int ddbridge_flashread(struct ddb *dev, u8 *buf, u32 addr, u32 len); + + +#endif + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/octonet.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/octonet.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/octonet.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddbridge/octonet.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,176 @@ +/* + * octonet.c: Digital Devices network tuner driver + * + * Copyright (C) 2012-13 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include "ddbridge.h" +#include "ddbridge-regs.h" + +#include "tda18271c2dd.h" +#include "stv6110x.h" +#include "stv090x.h" +#include "lnbh24.h" +#include "drxk.h" +#include "stv0367.h" +#include "stv0367dd.h" +#include "tda18212dd.h" +#include "cxd2843.h" + +#include + +static int adapter_alloc = 3; +module_param(adapter_alloc, int, 0444); +MODULE_PARM_DESC(adapter_alloc, "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); + +#define DVB_NETSTREAM + +#include "ddbridge-core.c" + +static struct ddb_info ddb_octonet = { + .type = DDB_OCTONET, + .name = "Digital Devices OctopusNet network DVB adapter", + .port_num = 4, + .i2c_num = 4, +}; + +static void octonet_unmap(struct ddb *dev) +{ + if (dev->regs) + iounmap(dev->regs); + vfree(dev); +} + +static int __exit octonet_remove(struct platform_device *pdev) +{ + struct ddb *dev; + + dev = platform_get_drvdata(pdev); + + ddb_nsd_detach(dev); + ddb_ports_detach(dev); + ddb_i2c_release(dev); + + ddbwritel(dev, 0, ETHER_CONTROL); + ddbwritel(dev, 0, INTERRUPT_ENABLE); + free_irq(platform_get_irq(dev->pfdev, 0), dev); + + ddb_device_destroy(dev); + octonet_unmap(dev); + platform_set_drvdata(pdev, 0); + return 0; +} + +static int __init octonet_probe(struct platform_device *pdev) +{ + struct ddb *dev; + struct resource *regs; + + dev = vzalloc(sizeof(struct ddb)); + if (!dev) + return -ENOMEM; + platform_set_drvdata(pdev, dev); + dev->dev = &pdev->dev; + dev->pfdev = pdev; + dev->info = &ddb_octonet; + mutex_init(&dev->mutex); + + regs = platform_get_resource(dev->pfdev, IORESOURCE_MEM, 0); + if (!regs) + return -ENXIO; + dev->regs_len = (regs->end - regs->start) + 1; + dev->regs = ioremap(regs->start, dev->regs_len); + if (!dev->regs) + return -ENOMEM; + + dev->hwid = ddbreadl(dev, 0); + dev->regmapid = ddbreadl(dev, 4); + dev->devid = ddbreadl(dev, 8); + dev->mac = ddbreadl(dev, 12); + + printk(KERN_INFO "HW %08x REGMAP %08x\n", dev->hwid, dev->regmapid); + printk(KERN_INFO "MAC %08x DEVID %08x\n", dev->mac, dev->devid); + + ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); + + if (request_irq(platform_get_irq(dev->pfdev, 0), irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "octonet-dvb", (void *) dev) < 0) + goto fail; + ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); + ddbwritel(dev, 0x1, ETHER_CONTROL); + ddbwritel(dev, 14 + (vlan ? 4 : 0), ETHER_LENGTH); + + + if (ddb_i2c_init(dev) < 0) + goto fail1; + ddb_ports_init(dev); + if (ddb_ports_attach(dev) < 0) + goto fail3; + + ddb_nsd_attach(dev); + + ddb_device_create(dev); + + return 0; + +fail3: + ddb_ports_detach(dev); + printk(KERN_ERR "fail3\n"); +fail1: +fail: + ddbwritel(dev, 0, ETHER_CONTROL); + ddbwritel(dev, 0, INTERRUPT_ENABLE); + octonet_unmap(dev); + platform_set_drvdata(pdev, 0); + return 0; +} + +static struct platform_driver octonet_driver = { + .remove = __exit_p(octonet_remove), + .probe = octonet_probe, + .driver = { + .name = "octonet-dvb", + .owner = THIS_MODULE, + }, +}; + +static __init int init_octonet(void) +{ + printk(KERN_INFO "Digital Devices OctoNet driver, " + "Copyright (C) 2012-2013 Digital Devices GmbH\n"); + if (ddb_class_create()) + return -1; + return platform_driver_probe(&octonet_driver, octonet_probe); +} + +static __exit void exit_octonet(void) +{ + platform_driver_unregister(&octonet_driver); + ddb_class_destroy(); +} + +module_init(init_octonet); +module_exit(exit_octonet); + +MODULE_DESCRIPTION("GPL"); +MODULE_AUTHOR("Metzler Brothers Systementwicklung"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("0.3"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddip/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddip/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddip/Kbuild 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddip/Kbuild 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,5 @@ +obj-$(CONFIG_DVB_DDBRIDGE) += ddip.o + +EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -Idrivers/media/dvb-frontends +EXTRA_CFLAGS += -Idrivers/media/common/tuners +NOSTDINC_FLAGS += -I$(SUBDIRS)/frontends -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddip/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddip/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddip/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddip/Makefile 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,18 @@ +KDIR ?= /lib/modules/$(shell uname -r)/build +PWD := $(shell pwd) + +MODDEFS := CONFIG_DVB_DDIP=m + +all: + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) $(MODDEFS) modules + +dep: + DIR=`pwd`; (cd $(TOPDIR); make SUBDIRS=$$DIR dep) + +install: all + $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules_install + +clean: + rm -rf */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules* + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddip/ddip.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddip/ddip.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/ddip/ddip.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/ddip/ddip.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,23 @@ +#include +#include +#include + + +static __init int init_ddip(void) +{ + + return 0; +} + +static __exit void exit_ddip(void) +{ +} + +module_init(init_ddip); +module_exit(exit_ddip); + +MODULE_DESCRIPTION("GPL"); +MODULE_AUTHOR("Metzler Brothers Systementwicklung"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("0.1"); + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dkms.conf dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dkms.conf --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dkms.conf 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dkms.conf 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,46 @@ +PACKAGE_NAME=dddvb +PACKAGE_VERSION=0.9.10.6yavdr0 +AUTOINSTALL=y +MAKE="make all" +CLEAN="make clean" +PATCH[0]=ddbridge.diff +PATCH[1]=drxk.diff +PATCH[2]=drxk_lockstatus_fix.diff +PATCH[3]=dbvals.diff +PATCH[4]=srcversion.diff +BUILT_MODULE_NAME[0]=dvb-core +BUILT_MODULE_LOCATION[0]=dvb-core/ +DEST_MODULE_LOCATION[0]=/updates/dkms +BUILT_MODULE_NAME[1]=octonet +BUILT_MODULE_LOCATION[1]=ddbridge/ +DEST_MODULE_LOCATION[1]=/updates/dkms +BUILT_MODULE_NAME[2]=ddbridge +BUILT_MODULE_LOCATION[2]=ddbridge/ +DEST_MODULE_LOCATION[2]=/updates/dkms +BUILT_MODULE_NAME[3]=drxk +BUILT_MODULE_LOCATION[3]=frontends/ +DEST_MODULE_LOCATION[3]=/updates/dkms +BUILT_MODULE_NAME[4]=tda18212dd +BUILT_MODULE_LOCATION[4]=frontends/ +DEST_MODULE_LOCATION[4]=/updates/dkms +BUILT_MODULE_NAME[5]=stv0367dd +BUILT_MODULE_LOCATION[5]=frontends/ +DEST_MODULE_LOCATION[5]=/updates/dkms +BUILT_MODULE_NAME[6]=lnbp21 +BUILT_MODULE_LOCATION[6]=frontends/ +DEST_MODULE_LOCATION[6]=/updates/dkms +BUILT_MODULE_NAME[7]=stv6110x +BUILT_MODULE_LOCATION[7]=frontends/ +DEST_MODULE_LOCATION[7]=/updates/dkms +BUILT_MODULE_NAME[8]=cxd2843 +BUILT_MODULE_LOCATION[8]=frontends/ +DEST_MODULE_LOCATION[8]=/updates/dkms +BUILT_MODULE_NAME[9]=stv090x +BUILT_MODULE_LOCATION[9]=frontends/ +DEST_MODULE_LOCATION[9]=/updates/dkms +BUILT_MODULE_NAME[10]=cxd2099 +BUILT_MODULE_LOCATION[10]=frontends/ +DEST_MODULE_LOCATION[10]=/updates/dkms +BUILT_MODULE_NAME[11]=tda18271c2dd +BUILT_MODULE_LOCATION[11]=frontends/ +DEST_MODULE_LOCATION[11]=/updates/dkms diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/adapter_alloc dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/adapter_alloc --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/adapter_alloc 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/adapter_alloc 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,7 @@ +The module parameter adapter_alloc lets you choose how adapter names are allocated. + +0 = one adapter per io if modules are present +1 = one adapter for each tab on which a module was detected +2 = one per tab even if no modules were detected +3 = one adapter for all devices of one card + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/ci dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/ci --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/ci 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/ci 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,29 @@ +The caX device associated with a CI device behaves just like any other +caX interface. You usually use it through a library like libdvben50221 +which is part of the dvb-apps package available at linuxtv.org. + +But contrary to other hardware where the CI module is physically placed +in the data path between the the demod and PCIe bridge, in the Digital +Devices cards the CI module is separate hardware. +So, you have to feed data to the CI module by writing to the secX +(in later kernel ci0) device and read it back from the same secX device. +The advantage is that the CI module can be used with any data coming from +any frontend or file. The disadvantage is that the user application has to +write/read the data to/from the module by itself. + +The sample application apps/cit.c shows how to pipe a stream through +the CI interface. In its ouput it will show discontinuities. Those should +only occur at the start of the program (due to old packets inside the CI +interface hardware and the CI module itself) and when a CI module is +inserted or removed. + +Since some users have problems using with standard software which cannot use +the CI interface in this way, there is now the redirect feature which allows +you to tell the driver to automatically pass the data coming from one +demod through a CI before offering it through the normal demux/dvr interface. +See docs/redirect for more info. + + + + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/modulator dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/modulator --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/modulator 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/modulator 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,29 @@ + +Modulator channels will automatically be enabled if you redirect data +from a demodulator to it. +E.g._: + +first demod on bridge 0 TAB1, modulator on bridge 1. + +echo "00 10" > /sys/class/ddbridge/ddbridge0/redirect + +Currently it is fixed to QAM256. Controls will be added later. +Rate control is experimental and PCR correction also not +implemented yet. So, depending on the reception device +there can be disturbances in playback. + +It is now also possible to chain redirects. +E.g., demod and modulator as above, CI on bridge 0 TAB 2: + +echo "00 01" > /sys/class/ddbridge/ddbridge0/redirect +echo "02 10" > /sys/class/ddbridge/ddbridge0/redirect + +The stream is also still available at the demux device +belonging to the demod devices. + +Now write and start an application (not provided) that +talks to the CI to decrypt the desired services. +For testing one can use a standard application that +supports decryption. Additionally to seeing the +decoded service on the PC it will then also be streamed +into cable by the modulator. \ No newline at end of file diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/octopusnet dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/octopusnet --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/octopusnet 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/octopusnet 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,69 @@ +OctopusNet +---------- + +Hardware: + +- SoC Atmel SAM9G45 400MHz ARM 926 + 64 MB DRAM + 256 MB NAND flash + +- FPGA Lattice ECP3 17 + data flash + +- 5 port switch Marvell 88E6175R + + +The FPGA is connected to the memory bus of the G45 and maps control registers into the memory space +of the G45. This is mainly to control the data flow on the FPGA. Only minimal data can be transferred +(e.g. single sections). Transport streams cannot be transferred to the G45 this way! +The FPGA can receive up to 8 TS from up to 4 Duo-Flex cards. You can also can alternatively connect +CI modules to port 2 and 3 (TAP 3 and 4). + +The FPGA is also connected to one of the ports of the gigabit switch. +There are up to 12 channels. Each channel can select one input TS, which is then passed through +a PID filter (8192 bit array) and sent to the switch as a UDP/RTP stream. + +The G45 is connected to another port of the switch (but only with 100 MBit) + + +Booting: + +The G45 does not boot from the NAND flash but from the dataflash connected to the FPGA. The G45 +does not support error correction for the boot sector and NAND with zero error boot pages +is no longer easily available. +Newer Atmel SoCs support 4-bit error correction in boot ROM but not the G45. + +So, the G45 boot looks like this: + +- Run a minimal boot rom mapped by the FPGA. +- Boot rom loads a modified bootstrap via SPI (provided via FPGA ports) from the dataflash. +- Bootstrap loads u-boot via SPI from dataflash. +- u-boot boots Linux ... + +If you remove jumper XX, boot rom is disabled and the G45 will boot from NAND flash like this: + +- Internal G45 boot rom bootstrap from NAND flash. +- Bootstrap boots u-boot from NAND flash +- u-boot boots Linux ... + +This is just a fall-back since page 0 can contain errors which cannot be corrected by the G45 boot ROM +and the bootstrap code which loads u-boot also does not contain error correction. + + + + + + + + + + + + + + + + + + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/redirect dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/redirect --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/docs/redirect 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/docs/redirect 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,24 @@ +Redirection of TS streams through CI modules is now supported +through /sys/class/ddbridge/ddbridge0/redirect. +It only works with cards based on the ddbridge PCIe bridge, not +with nGene based cards. + +It is set up in such a way that you can write "AB CD" to +a "redirect" attribute and data from input B of card A is then piped through +port D (meaning TAB (D+1) which uses output D and input 2*D for CI io) +of card C and then shows up in the demux device belonging to +input B (input (B&1) of TAB (B/2+1)) of card A. + +E.g.: + +echo "00 01" > /sys/class/ddbridge/ddbridge0/redirect + +will pipe input 0 of card 0 through CI at port 1 (TAB 2) of card 0. + +Redirection should only be done right after loading the driver +(or booting if the driver is built-in) and before using the +devices in any way. + +adapter_alloc=3 is rcommended when using redirect +The ci device will then show up in the same adapter directory and most +software will then assume it belongs to the frontend in the same directory. diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/Makefile 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,12 @@ +# +# Makefile for the kernel DVB device drivers. +# + +dvb-core-objs := dvbdev.o dmxdev.o dvb_demux.o dvb_filter.o \ + dvb_ca_en50221.o dvb_frontend.o \ + dvb_net.o dvb_ringbuffer.o dvb_math.o dvb_netstream.o + +obj-$(CONFIG_DVB_CORE) += dvb-core.o + +EXTRA_CFLAGS += -DCONFIG_DVB_DYNAMIC_MINORS -DCONFIG_DVB_NET +NOSTDINC_FLAGS += -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/demux.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/demux.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/demux.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/demux.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,241 @@ +/* + * demux.h + * + * Copyright (c) 2002 Convergence GmbH + * + * based on code: + * Copyright (c) 2000 Nokia Research Center + * Tampere, FINLAND + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef __DEMUX_H +#define __DEMUX_H + +#include +#include +#include +#include +#include + +/*--------------------------------------------------------------------------*/ +/* Common definitions */ +/*--------------------------------------------------------------------------*/ + +/* + * DMX_MAX_FILTER_SIZE: Maximum length (in bytes) of a section/PES filter. + */ + +#ifndef DMX_MAX_FILTER_SIZE +#define DMX_MAX_FILTER_SIZE 18 +#endif + +/* + * DMX_MAX_SECFEED_SIZE: Maximum length (in bytes) of a private section feed filter. + */ + +#ifndef DMX_MAX_SECTION_SIZE +#define DMX_MAX_SECTION_SIZE 4096 +#endif +#ifndef DMX_MAX_SECFEED_SIZE +#define DMX_MAX_SECFEED_SIZE (DMX_MAX_SECTION_SIZE + 188) +#endif + + +/* + * enum dmx_success: Success codes for the Demux Callback API. + */ + +enum dmx_success { + DMX_OK = 0, /* Received Ok */ + DMX_LENGTH_ERROR, /* Incorrect length */ + DMX_OVERRUN_ERROR, /* Receiver ring buffer overrun */ + DMX_CRC_ERROR, /* Incorrect CRC */ + DMX_FRAME_ERROR, /* Frame alignment error */ + DMX_FIFO_ERROR, /* Receiver FIFO overrun */ + DMX_MISSED_ERROR /* Receiver missed packet */ +} ; + +/*--------------------------------------------------------------------------*/ +/* TS packet reception */ +/*--------------------------------------------------------------------------*/ + +/* TS filter type for set() */ + +#define TS_PACKET 1 /* send TS packets (188 bytes) to callback (default) */ +#define TS_PAYLOAD_ONLY 2 /* in case TS_PACKET is set, only send the TS + payload (<=184 bytes per packet) to callback */ +#define TS_DECODER 4 /* send stream to built-in decoder (if present) */ +#define TS_DEMUX 8 /* in case TS_PACKET is set, send the TS to + the demux device, not to the dvr device */ + +struct dmx_ts_feed { + int is_filtering; /* Set to non-zero when filtering in progress */ + struct dmx_demux *parent; /* Back-pointer */ + void *priv; /* Pointer to private data of the API client */ + int (*set) (struct dmx_ts_feed *feed, + u16 pid, + int type, + enum dmx_ts_pes pes_type, + size_t circular_buffer_size, + struct timespec timeout); + int (*start_filtering) (struct dmx_ts_feed* feed); + int (*stop_filtering) (struct dmx_ts_feed* feed); +}; + +/*--------------------------------------------------------------------------*/ +/* Section reception */ +/*--------------------------------------------------------------------------*/ + +struct dmx_section_filter { + u8 filter_value [DMX_MAX_FILTER_SIZE]; + u8 filter_mask [DMX_MAX_FILTER_SIZE]; + u8 filter_mode [DMX_MAX_FILTER_SIZE]; + struct dmx_section_feed* parent; /* Back-pointer */ + void* priv; /* Pointer to private data of the API client */ +}; + +struct dmx_section_feed { + int is_filtering; /* Set to non-zero when filtering in progress */ + struct dmx_demux* parent; /* Back-pointer */ + void* priv; /* Pointer to private data of the API client */ + + int check_crc; + u32 crc_val; + + u8 *secbuf; + u8 secbuf_base[DMX_MAX_SECFEED_SIZE]; + u16 secbufp, seclen, tsfeedp; + + int (*set) (struct dmx_section_feed* feed, + u16 pid, + size_t circular_buffer_size, + int check_crc); + int (*allocate_filter) (struct dmx_section_feed* feed, + struct dmx_section_filter** filter); + int (*release_filter) (struct dmx_section_feed* feed, + struct dmx_section_filter* filter); + int (*start_filtering) (struct dmx_section_feed* feed); + int (*stop_filtering) (struct dmx_section_feed* feed); +}; + +/*--------------------------------------------------------------------------*/ +/* Callback functions */ +/*--------------------------------------------------------------------------*/ + +typedef int (*dmx_ts_cb) ( const u8 * buffer1, + size_t buffer1_length, + const u8 * buffer2, + size_t buffer2_length, + struct dmx_ts_feed* source, + enum dmx_success success); + +typedef int (*dmx_section_cb) ( const u8 * buffer1, + size_t buffer1_len, + const u8 * buffer2, + size_t buffer2_len, + struct dmx_section_filter * source, + enum dmx_success success); + +/*--------------------------------------------------------------------------*/ +/* DVB Front-End */ +/*--------------------------------------------------------------------------*/ + +enum dmx_frontend_source { + DMX_MEMORY_FE, + DMX_FRONTEND_0, + DMX_FRONTEND_1, + DMX_FRONTEND_2, + DMX_FRONTEND_3, + DMX_STREAM_0, /* external stream input, e.g. LVDS */ + DMX_STREAM_1, + DMX_STREAM_2, + DMX_STREAM_3 +}; + +struct dmx_frontend { + struct list_head connectivity_list; /* List of front-ends that can + be connected to a particular + demux */ + enum dmx_frontend_source source; +}; + +/*--------------------------------------------------------------------------*/ +/* MPEG-2 TS Demux */ +/*--------------------------------------------------------------------------*/ + +/* + * Flags OR'ed in the capabilities field of struct dmx_demux. + */ + +#define DMX_TS_FILTERING 1 +#define DMX_PES_FILTERING 2 +#define DMX_SECTION_FILTERING 4 +#define DMX_MEMORY_BASED_FILTERING 8 /* write() available */ +#define DMX_CRC_CHECKING 16 +#define DMX_TS_DESCRAMBLING 32 + +/* + * Demux resource type identifier. +*/ + +/* + * DMX_FE_ENTRY(): Casts elements in the list of registered + * front-ends from the generic type struct list_head + * to the type * struct dmx_frontend + *. +*/ + +#define DMX_FE_ENTRY(list) list_entry(list, struct dmx_frontend, connectivity_list) + +struct dmx_demux { + u32 capabilities; /* Bitfield of capability flags */ + struct dmx_frontend* frontend; /* Front-end connected to the demux */ + void* priv; /* Pointer to private data of the API client */ + int (*open) (struct dmx_demux* demux); + int (*close) (struct dmx_demux* demux); + int (*write) (struct dmx_demux* demux, const char __user *buf, size_t count); + int (*allocate_ts_feed) (struct dmx_demux* demux, + struct dmx_ts_feed** feed, + dmx_ts_cb callback); + int (*release_ts_feed) (struct dmx_demux* demux, + struct dmx_ts_feed* feed); + int (*allocate_section_feed) (struct dmx_demux* demux, + struct dmx_section_feed** feed, + dmx_section_cb callback); + int (*release_section_feed) (struct dmx_demux* demux, + struct dmx_section_feed* feed); + int (*add_frontend) (struct dmx_demux* demux, + struct dmx_frontend* frontend); + int (*remove_frontend) (struct dmx_demux* demux, + struct dmx_frontend* frontend); + struct list_head* (*get_frontends) (struct dmx_demux* demux); + int (*connect_frontend) (struct dmx_demux* demux, + struct dmx_frontend* frontend); + int (*disconnect_frontend) (struct dmx_demux* demux); + + int (*get_pes_pids) (struct dmx_demux* demux, u16 *pids); + + int (*get_caps) (struct dmx_demux* demux, struct dmx_caps *caps); + + int (*set_source) (struct dmx_demux* demux, const dmx_source_t *src); + + int (*get_stc) (struct dmx_demux* demux, unsigned int num, + u64 *stc, unsigned int *base); +}; + +#endif /* #ifndef __DEMUX_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1272 @@ +/* + * dmxdev.c - DVB demultiplexer device + * + * Copyright (C) 2000 Ralph Metzler & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dmxdev.h" + +static int debug; + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); + +#define dprintk if (debug) printk + +static int dvb_dmxdev_buffer_write(struct dvb_ringbuffer *buf, + const u8 *src, size_t len) +{ + ssize_t free; + + if (!len) + return 0; + if (!buf->data) + return 0; + + free = dvb_ringbuffer_free(buf); + if (len > free) { + dprintk("dmxdev: buffer overflow\n"); + return -EOVERFLOW; + } + + return dvb_ringbuffer_write(buf, src, len); +} + +static ssize_t dvb_dmxdev_buffer_read(struct dvb_ringbuffer *src, + int non_blocking, char __user *buf, + size_t count, loff_t *ppos) +{ + size_t todo; + ssize_t avail; + ssize_t ret = 0; + + if (!src->data) + return 0; + + if (src->error) { + ret = src->error; + dvb_ringbuffer_flush(src); + return ret; + } + + for (todo = count; todo > 0; todo -= ret) { + if (non_blocking && dvb_ringbuffer_empty(src)) { + ret = -EWOULDBLOCK; + break; + } + + ret = wait_event_interruptible(src->queue, + !dvb_ringbuffer_empty(src) || + (src->error != 0)); + if (ret < 0) + break; + + if (src->error) { + ret = src->error; + dvb_ringbuffer_flush(src); + break; + } + + avail = dvb_ringbuffer_avail(src); + if (avail > todo) + avail = todo; + + ret = dvb_ringbuffer_read_user(src, buf, avail); + if (ret < 0) + break; + + buf += ret; + } + + return (count - todo) ? (count - todo) : ret; +} + +static struct dmx_frontend *get_fe(struct dmx_demux *demux, int type) +{ + struct list_head *head, *pos; + + head = demux->get_frontends(demux); + if (!head) + return NULL; + list_for_each(pos, head) + if (DMX_FE_ENTRY(pos)->source == type) + return DMX_FE_ENTRY(pos); + + return NULL; +} + +static int dvb_dvr_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dmxdev *dmxdev = dvbdev->priv; + struct dmx_frontend *front; + + dprintk("function : %s\n", __func__); + + if (mutex_lock_interruptible(&dmxdev->mutex)) + return -ERESTARTSYS; + + if (dmxdev->exit) { + mutex_unlock(&dmxdev->mutex); + return -ENODEV; + } + + if ((file->f_flags & O_ACCMODE) == O_RDWR) { + if (!(dmxdev->capabilities & DMXDEV_CAP_DUPLEX)) { + mutex_unlock(&dmxdev->mutex); + return -EOPNOTSUPP; + } + } + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + void *mem; + if (!dvbdev->readers) { + mutex_unlock(&dmxdev->mutex); + return -EBUSY; + } + mem = vmalloc(DVR_BUFFER_SIZE); + if (!mem) { + mutex_unlock(&dmxdev->mutex); + return -ENOMEM; + } + dvb_ringbuffer_init(&dmxdev->dvr_buffer, mem, DVR_BUFFER_SIZE); + dvbdev->readers--; + } + + if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + dmxdev->dvr_orig_fe = dmxdev->demux->frontend; + + if (!dmxdev->demux->write) { + mutex_unlock(&dmxdev->mutex); + return -EOPNOTSUPP; + } + + front = get_fe(dmxdev->demux, DMX_MEMORY_FE); + + if (!front) { + mutex_unlock(&dmxdev->mutex); + return -EINVAL; + } + dmxdev->demux->disconnect_frontend(dmxdev->demux); + dmxdev->demux->connect_frontend(dmxdev->demux, front); + } + dvbdev->users++; + mutex_unlock(&dmxdev->mutex); + return 0; +} + +static int dvb_dvr_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dmxdev *dmxdev = dvbdev->priv; + + mutex_lock(&dmxdev->mutex); + + if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + dmxdev->demux->disconnect_frontend(dmxdev->demux); + dmxdev->demux->connect_frontend(dmxdev->demux, + dmxdev->dvr_orig_fe); + } + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + dvbdev->readers++; + if (dmxdev->dvr_buffer.data) { + void *mem = dmxdev->dvr_buffer.data; + mb(); + spin_lock_irq(&dmxdev->lock); + dmxdev->dvr_buffer.data = NULL; + spin_unlock_irq(&dmxdev->lock); + vfree(mem); + } + } + /* TODO */ + dvbdev->users--; + if (dvbdev->users == 1 && dmxdev->exit == 1) { + fops_put(file->f_op); + file->f_op = NULL; + mutex_unlock(&dmxdev->mutex); + wake_up(&dvbdev->wait_queue); + } else + mutex_unlock(&dmxdev->mutex); + + return 0; +} + +static ssize_t dvb_dvr_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct dmxdev *dmxdev = dvbdev->priv; + int ret; + + if (!dmxdev->demux->write) + return -EOPNOTSUPP; + if ((file->f_flags & O_ACCMODE) != O_WRONLY) + return -EINVAL; + if (mutex_lock_interruptible(&dmxdev->mutex)) + return -ERESTARTSYS; + + if (dmxdev->exit) { + mutex_unlock(&dmxdev->mutex); + return -ENODEV; + } + ret = dmxdev->demux->write(dmxdev->demux, buf, count); + mutex_unlock(&dmxdev->mutex); + return ret; +} + +static ssize_t dvb_dvr_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct dmxdev *dmxdev = dvbdev->priv; + + if (dmxdev->exit) + return -ENODEV; + + return dvb_dmxdev_buffer_read(&dmxdev->dvr_buffer, + file->f_flags & O_NONBLOCK, + buf, count, ppos); +} + +static int dvb_dvr_set_buffer_size(struct dmxdev *dmxdev, + unsigned long size) +{ + struct dvb_ringbuffer *buf = &dmxdev->dvr_buffer; + void *newmem; + void *oldmem; + + dprintk("function : %s\n", __func__); + + if (buf->size == size) + return 0; + if (!size) + return -EINVAL; + + newmem = vmalloc(size); + if (!newmem) + return -ENOMEM; + + oldmem = buf->data; + + spin_lock_irq(&dmxdev->lock); + buf->data = newmem; + buf->size = size; + + /* reset and not flush in case the buffer shrinks */ + dvb_ringbuffer_reset(buf); + spin_unlock_irq(&dmxdev->lock); + + vfree(oldmem); + + return 0; +} + +static inline void dvb_dmxdev_filter_state_set(struct dmxdev_filter + *dmxdevfilter, int state) +{ + spin_lock_irq(&dmxdevfilter->dev->lock); + dmxdevfilter->state = state; + spin_unlock_irq(&dmxdevfilter->dev->lock); +} + +static int dvb_dmxdev_set_buffer_size(struct dmxdev_filter *dmxdevfilter, + unsigned long size) +{ + struct dvb_ringbuffer *buf = &dmxdevfilter->buffer; + void *newmem; + void *oldmem; + + if (buf->size == size) + return 0; + if (!size) + return -EINVAL; + if (dmxdevfilter->state >= DMXDEV_STATE_GO) + return -EBUSY; + + newmem = vmalloc(size); + if (!newmem) + return -ENOMEM; + + oldmem = buf->data; + + spin_lock_irq(&dmxdevfilter->dev->lock); + buf->data = newmem; + buf->size = size; + + /* reset and not flush in case the buffer shrinks */ + dvb_ringbuffer_reset(buf); + spin_unlock_irq(&dmxdevfilter->dev->lock); + + vfree(oldmem); + + return 0; +} + +static void dvb_dmxdev_filter_timeout(unsigned long data) +{ + struct dmxdev_filter *dmxdevfilter = (struct dmxdev_filter *)data; + + dmxdevfilter->buffer.error = -ETIMEDOUT; + spin_lock_irq(&dmxdevfilter->dev->lock); + dmxdevfilter->state = DMXDEV_STATE_TIMEDOUT; + spin_unlock_irq(&dmxdevfilter->dev->lock); + wake_up(&dmxdevfilter->buffer.queue); +} + +static void dvb_dmxdev_filter_timer(struct dmxdev_filter *dmxdevfilter) +{ + struct dmx_sct_filter_params *para = &dmxdevfilter->params.sec; + + del_timer(&dmxdevfilter->timer); + if (para->timeout) { + dmxdevfilter->timer.function = dvb_dmxdev_filter_timeout; + dmxdevfilter->timer.data = (unsigned long)dmxdevfilter; + dmxdevfilter->timer.expires = + jiffies + 1 + (HZ / 2 + HZ * para->timeout) / 1000; + add_timer(&dmxdevfilter->timer); + } +} + +static int dvb_dmxdev_section_callback(const u8 *buffer1, size_t buffer1_len, + const u8 *buffer2, size_t buffer2_len, + struct dmx_section_filter *filter, + enum dmx_success success) +{ + struct dmxdev_filter *dmxdevfilter = filter->priv; + int ret; + + if (dmxdevfilter->buffer.error) { + wake_up(&dmxdevfilter->buffer.queue); + return 0; + } + spin_lock(&dmxdevfilter->dev->lock); + if (dmxdevfilter->state != DMXDEV_STATE_GO) { + spin_unlock(&dmxdevfilter->dev->lock); + return 0; + } + del_timer(&dmxdevfilter->timer); + dprintk("dmxdev: section callback %*ph\n", 6, buffer1); + ret = dvb_dmxdev_buffer_write(&dmxdevfilter->buffer, buffer1, + buffer1_len); + if (ret == buffer1_len) { + ret = dvb_dmxdev_buffer_write(&dmxdevfilter->buffer, buffer2, + buffer2_len); + } + if (ret < 0) + dmxdevfilter->buffer.error = ret; + if (dmxdevfilter->params.sec.flags & DMX_ONESHOT) + dmxdevfilter->state = DMXDEV_STATE_DONE; + spin_unlock(&dmxdevfilter->dev->lock); + wake_up(&dmxdevfilter->buffer.queue); + return 0; +} + +static int dvb_dmxdev_ts_callback(const u8 *buffer1, size_t buffer1_len, + const u8 *buffer2, size_t buffer2_len, + struct dmx_ts_feed *feed, + enum dmx_success success) +{ + struct dmxdev_filter *dmxdevfilter = feed->priv; + struct dvb_ringbuffer *buffer; + int ret; + + spin_lock(&dmxdevfilter->dev->lock); + if (dmxdevfilter->params.pes.output == DMX_OUT_DECODER) { + spin_unlock(&dmxdevfilter->dev->lock); + return 0; + } + + if (dmxdevfilter->params.pes.output == DMX_OUT_TAP + || dmxdevfilter->params.pes.output == DMX_OUT_TSDEMUX_TAP) + buffer = &dmxdevfilter->buffer; + else + buffer = &dmxdevfilter->dev->dvr_buffer; + if (buffer->error) { + spin_unlock(&dmxdevfilter->dev->lock); + wake_up(&buffer->queue); + return 0; + } + ret = dvb_dmxdev_buffer_write(buffer, buffer1, buffer1_len); + if (ret == buffer1_len) + ret = dvb_dmxdev_buffer_write(buffer, buffer2, buffer2_len); + if (ret < 0) + buffer->error = ret; + spin_unlock(&dmxdevfilter->dev->lock); + wake_up(&buffer->queue); + return 0; +} + +/* stop feed but only mark the specified filter as stopped (state set) */ +static int dvb_dmxdev_feed_stop(struct dmxdev_filter *dmxdevfilter) +{ + struct dmxdev_feed *feed; + + dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET); + + switch (dmxdevfilter->type) { + case DMXDEV_TYPE_SEC: + del_timer(&dmxdevfilter->timer); + dmxdevfilter->feed.sec->stop_filtering(dmxdevfilter->feed.sec); + break; + case DMXDEV_TYPE_PES: + list_for_each_entry(feed, &dmxdevfilter->feed.ts, next) + feed->ts->stop_filtering(feed->ts); + break; + default: + return -EINVAL; + } + return 0; +} + +/* start feed associated with the specified filter */ +static int dvb_dmxdev_feed_start(struct dmxdev_filter *filter) +{ + struct dmxdev_feed *feed; + int ret; + + dvb_dmxdev_filter_state_set(filter, DMXDEV_STATE_GO); + + switch (filter->type) { + case DMXDEV_TYPE_SEC: + return filter->feed.sec->start_filtering(filter->feed.sec); + case DMXDEV_TYPE_PES: + list_for_each_entry(feed, &filter->feed.ts, next) { + ret = feed->ts->start_filtering(feed->ts); + if (ret < 0) { + dvb_dmxdev_feed_stop(filter); + return ret; + } + } + break; + default: + return -EINVAL; + } + + return 0; +} + +/* restart section feed if it has filters left associated with it, + otherwise release the feed */ +static int dvb_dmxdev_feed_restart(struct dmxdev_filter *filter) +{ + int i; + struct dmxdev *dmxdev = filter->dev; + u16 pid = filter->params.sec.pid; + + for (i = 0; i < dmxdev->filternum; i++) + if (dmxdev->filter[i].state >= DMXDEV_STATE_GO && + dmxdev->filter[i].type == DMXDEV_TYPE_SEC && + dmxdev->filter[i].params.sec.pid == pid) { + dvb_dmxdev_feed_start(&dmxdev->filter[i]); + return 0; + } + + filter->dev->demux->release_section_feed(dmxdev->demux, + filter->feed.sec); + + return 0; +} + +static int dvb_dmxdev_filter_stop(struct dmxdev_filter *dmxdevfilter) +{ + struct dmxdev_feed *feed; + struct dmx_demux *demux; + + if (dmxdevfilter->state < DMXDEV_STATE_GO) + return 0; + + switch (dmxdevfilter->type) { + case DMXDEV_TYPE_SEC: + if (!dmxdevfilter->feed.sec) + break; + dvb_dmxdev_feed_stop(dmxdevfilter); + if (dmxdevfilter->filter.sec) + dmxdevfilter->feed.sec-> + release_filter(dmxdevfilter->feed.sec, + dmxdevfilter->filter.sec); + dvb_dmxdev_feed_restart(dmxdevfilter); + dmxdevfilter->feed.sec = NULL; + break; + case DMXDEV_TYPE_PES: + dvb_dmxdev_feed_stop(dmxdevfilter); + demux = dmxdevfilter->dev->demux; + list_for_each_entry(feed, &dmxdevfilter->feed.ts, next) { + demux->release_ts_feed(demux, feed->ts); + feed->ts = NULL; + } + break; + default: + if (dmxdevfilter->state == DMXDEV_STATE_ALLOCATED) + return 0; + return -EINVAL; + } + + dvb_ringbuffer_flush(&dmxdevfilter->buffer); + return 0; +} + +static void dvb_dmxdev_delete_pids(struct dmxdev_filter *dmxdevfilter) +{ + struct dmxdev_feed *feed, *tmp; + + /* delete all PIDs */ + list_for_each_entry_safe(feed, tmp, &dmxdevfilter->feed.ts, next) { + list_del(&feed->next); + kfree(feed); + } + + BUG_ON(!list_empty(&dmxdevfilter->feed.ts)); +} + +static inline int dvb_dmxdev_filter_reset(struct dmxdev_filter *dmxdevfilter) +{ + if (dmxdevfilter->state < DMXDEV_STATE_SET) + return 0; + + if (dmxdevfilter->type == DMXDEV_TYPE_PES) + dvb_dmxdev_delete_pids(dmxdevfilter); + + dmxdevfilter->type = DMXDEV_TYPE_NONE; + dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_ALLOCATED); + return 0; +} + +static int dvb_dmxdev_start_feed(struct dmxdev *dmxdev, + struct dmxdev_filter *filter, + struct dmxdev_feed *feed) +{ + struct timespec timeout = { 0 }; + struct dmx_pes_filter_params *para = &filter->params.pes; + dmx_output_t otype; + int ret; + int ts_type; + enum dmx_ts_pes ts_pes; + struct dmx_ts_feed *tsfeed; + + feed->ts = NULL; + otype = para->output; + + ts_pes = para->pes_type; + + if (ts_pes < DMX_PES_OTHER) + ts_type = TS_DECODER; + else + ts_type = 0; + + if (otype == DMX_OUT_TS_TAP) + ts_type |= TS_PACKET; + else if (otype == DMX_OUT_TSDEMUX_TAP) + ts_type |= TS_PACKET | TS_DEMUX; + else if (otype == DMX_OUT_TAP) + ts_type |= TS_PACKET | TS_DEMUX | TS_PAYLOAD_ONLY; + + ret = dmxdev->demux->allocate_ts_feed(dmxdev->demux, &feed->ts, + dvb_dmxdev_ts_callback); + if (ret < 0) + return ret; + + tsfeed = feed->ts; + tsfeed->priv = filter; + + ret = tsfeed->set(tsfeed, feed->pid, ts_type, ts_pes, 32768, timeout); + if (ret < 0) { + dmxdev->demux->release_ts_feed(dmxdev->demux, tsfeed); + return ret; + } + + ret = tsfeed->start_filtering(tsfeed); + if (ret < 0) { + dmxdev->demux->release_ts_feed(dmxdev->demux, tsfeed); + return ret; + } + + return 0; +} + +static int dvb_dmxdev_filter_start(struct dmxdev_filter *filter) +{ + struct dmxdev *dmxdev = filter->dev; + struct dmxdev_feed *feed; + void *mem; + int ret, i; + + if (filter->state < DMXDEV_STATE_SET) + return -EINVAL; + + if (filter->state >= DMXDEV_STATE_GO) + dvb_dmxdev_filter_stop(filter); + + if (!filter->buffer.data) { + mem = vmalloc(filter->buffer.size); + if (!mem) + return -ENOMEM; + spin_lock_irq(&filter->dev->lock); + filter->buffer.data = mem; + spin_unlock_irq(&filter->dev->lock); + } + + dvb_ringbuffer_flush(&filter->buffer); + + switch (filter->type) { + case DMXDEV_TYPE_SEC: + { + struct dmx_sct_filter_params *para = &filter->params.sec; + struct dmx_section_filter **secfilter = &filter->filter.sec; + struct dmx_section_feed **secfeed = &filter->feed.sec; + + *secfilter = NULL; + *secfeed = NULL; + + + /* find active filter/feed with same PID */ + for (i = 0; i < dmxdev->filternum; i++) { + if (dmxdev->filter[i].state >= DMXDEV_STATE_GO && + dmxdev->filter[i].type == DMXDEV_TYPE_SEC && + dmxdev->filter[i].params.sec.pid == para->pid) { + *secfeed = dmxdev->filter[i].feed.sec; + break; + } + } + + /* if no feed found, try to allocate new one */ + if (!*secfeed) { + ret = dmxdev->demux->allocate_section_feed(dmxdev->demux, + secfeed, + dvb_dmxdev_section_callback); + if (ret < 0) { + printk("DVB (%s): could not alloc feed\n", + __func__); + return ret; + } + + ret = (*secfeed)->set(*secfeed, para->pid, 32768, + (para->flags & DMX_CHECK_CRC) ? 1 : 0); + if (ret < 0) { + printk("DVB (%s): could not set feed\n", + __func__); + dvb_dmxdev_feed_restart(filter); + return ret; + } + } else { + dvb_dmxdev_feed_stop(filter); + } + + ret = (*secfeed)->allocate_filter(*secfeed, secfilter); + if (ret < 0) { + dvb_dmxdev_feed_restart(filter); + filter->feed.sec->start_filtering(*secfeed); + dprintk("could not get filter\n"); + return ret; + } + + (*secfilter)->priv = filter; + + memcpy(&((*secfilter)->filter_value[3]), + &(para->filter.filter[1]), DMX_FILTER_SIZE - 1); + memcpy(&(*secfilter)->filter_mask[3], + ¶->filter.mask[1], DMX_FILTER_SIZE - 1); + memcpy(&(*secfilter)->filter_mode[3], + ¶->filter.mode[1], DMX_FILTER_SIZE - 1); + + (*secfilter)->filter_value[0] = para->filter.filter[0]; + (*secfilter)->filter_mask[0] = para->filter.mask[0]; + (*secfilter)->filter_mode[0] = para->filter.mode[0]; + (*secfilter)->filter_mask[1] = 0; + (*secfilter)->filter_mask[2] = 0; + + filter->todo = 0; + + ret = filter->feed.sec->start_filtering(filter->feed.sec); + if (ret < 0) + return ret; + + dvb_dmxdev_filter_timer(filter); + break; + } + case DMXDEV_TYPE_PES: + list_for_each_entry(feed, &filter->feed.ts, next) { + ret = dvb_dmxdev_start_feed(dmxdev, filter, feed); + if (ret < 0) { + dvb_dmxdev_filter_stop(filter); + return ret; + } + } + break; + default: + return -EINVAL; + } + + dvb_dmxdev_filter_state_set(filter, DMXDEV_STATE_GO); + return 0; +} + +static int dvb_demux_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dmxdev *dmxdev = dvbdev->priv; + int i; + struct dmxdev_filter *dmxdevfilter; + + if (!dmxdev->filter) + return -EINVAL; + + if (mutex_lock_interruptible(&dmxdev->mutex)) + return -ERESTARTSYS; + + for (i = 0; i < dmxdev->filternum; i++) + if (dmxdev->filter[i].state == DMXDEV_STATE_FREE) + break; + + if (i == dmxdev->filternum) { + mutex_unlock(&dmxdev->mutex); + return -EMFILE; + } + + dmxdevfilter = &dmxdev->filter[i]; + mutex_init(&dmxdevfilter->mutex); + file->private_data = dmxdevfilter; + + dvb_ringbuffer_init(&dmxdevfilter->buffer, NULL, 8192); + dmxdevfilter->type = DMXDEV_TYPE_NONE; + dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_ALLOCATED); + init_timer(&dmxdevfilter->timer); + + dvbdev->users++; + + mutex_unlock(&dmxdev->mutex); + return 0; +} + +static int dvb_dmxdev_filter_free(struct dmxdev *dmxdev, + struct dmxdev_filter *dmxdevfilter) +{ + mutex_lock(&dmxdev->mutex); + mutex_lock(&dmxdevfilter->mutex); + + dvb_dmxdev_filter_stop(dmxdevfilter); + dvb_dmxdev_filter_reset(dmxdevfilter); + + if (dmxdevfilter->buffer.data) { + void *mem = dmxdevfilter->buffer.data; + + spin_lock_irq(&dmxdev->lock); + dmxdevfilter->buffer.data = NULL; + spin_unlock_irq(&dmxdev->lock); + vfree(mem); + } + + dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_FREE); + wake_up(&dmxdevfilter->buffer.queue); + mutex_unlock(&dmxdevfilter->mutex); + mutex_unlock(&dmxdev->mutex); + return 0; +} + +static inline void invert_mode(dmx_filter_t *filter) +{ + int i; + + for (i = 0; i < DMX_FILTER_SIZE; i++) + filter->mode[i] ^= 0xff; +} + +static int dvb_dmxdev_add_pid(struct dmxdev *dmxdev, + struct dmxdev_filter *filter, u16 pid) +{ + struct dmxdev_feed *feed; + + if ((filter->type != DMXDEV_TYPE_PES) || + (filter->state < DMXDEV_STATE_SET)) + return -EINVAL; + + /* only TS packet filters may have multiple PIDs */ + if ((filter->params.pes.output != DMX_OUT_TSDEMUX_TAP) && + (!list_empty(&filter->feed.ts))) + return -EINVAL; + + feed = kzalloc(sizeof(struct dmxdev_feed), GFP_KERNEL); + if (feed == NULL) + return -ENOMEM; + + feed->pid = pid; + list_add(&feed->next, &filter->feed.ts); + + if (filter->state >= DMXDEV_STATE_GO) + return dvb_dmxdev_start_feed(dmxdev, filter, feed); + + return 0; +} + +static int dvb_dmxdev_remove_pid(struct dmxdev *dmxdev, + struct dmxdev_filter *filter, u16 pid) +{ + struct dmxdev_feed *feed, *tmp; + + if ((filter->type != DMXDEV_TYPE_PES) || + (filter->state < DMXDEV_STATE_SET)) + return -EINVAL; + + list_for_each_entry_safe(feed, tmp, &filter->feed.ts, next) { + if ((feed->pid == pid) && (feed->ts != NULL)) { + feed->ts->stop_filtering(feed->ts); + filter->dev->demux->release_ts_feed(filter->dev->demux, + feed->ts); + list_del(&feed->next); + kfree(feed); + } + } + + return 0; +} + +static int dvb_dmxdev_filter_set(struct dmxdev *dmxdev, + struct dmxdev_filter *dmxdevfilter, + struct dmx_sct_filter_params *params) +{ + dprintk("function : %s, PID=0x%04x, flags=%02x, timeout=%d\n", + __func__, params->pid, params->flags, params->timeout); + + dvb_dmxdev_filter_stop(dmxdevfilter); + + dmxdevfilter->type = DMXDEV_TYPE_SEC; + memcpy(&dmxdevfilter->params.sec, + params, sizeof(struct dmx_sct_filter_params)); + invert_mode(&dmxdevfilter->params.sec.filter); + dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET); + + if (params->flags & DMX_IMMEDIATE_START) + return dvb_dmxdev_filter_start(dmxdevfilter); + + return 0; +} + +static int dvb_dmxdev_pes_filter_set(struct dmxdev *dmxdev, + struct dmxdev_filter *dmxdevfilter, + struct dmx_pes_filter_params *params) +{ + int ret; + + dvb_dmxdev_filter_stop(dmxdevfilter); + dvb_dmxdev_filter_reset(dmxdevfilter); + + if ((unsigned)params->pes_type > DMX_PES_OTHER) + return -EINVAL; + + dmxdevfilter->type = DMXDEV_TYPE_PES; + memcpy(&dmxdevfilter->params, params, + sizeof(struct dmx_pes_filter_params)); + INIT_LIST_HEAD(&dmxdevfilter->feed.ts); + + dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET); + + ret = dvb_dmxdev_add_pid(dmxdev, dmxdevfilter, + dmxdevfilter->params.pes.pid); + if (ret < 0) + return ret; + + if (params->flags & DMX_IMMEDIATE_START) + return dvb_dmxdev_filter_start(dmxdevfilter); + + return 0; +} + +static ssize_t dvb_dmxdev_read_sec(struct dmxdev_filter *dfil, + struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + int result, hcount; + int done = 0; + + if (dfil->todo <= 0) { + hcount = 3 + dfil->todo; + if (hcount > count) + hcount = count; + result = dvb_dmxdev_buffer_read(&dfil->buffer, + file->f_flags & O_NONBLOCK, + buf, hcount, ppos); + if (result < 0) { + dfil->todo = 0; + return result; + } + if (copy_from_user(dfil->secheader - dfil->todo, buf, result)) + return -EFAULT; + buf += result; + done = result; + count -= result; + dfil->todo -= result; + if (dfil->todo > -3) + return done; + dfil->todo = ((dfil->secheader[1] << 8) | dfil->secheader[2]) & 0xfff; + if (!count) + return done; + } + if (count > dfil->todo) + count = dfil->todo; + result = dvb_dmxdev_buffer_read(&dfil->buffer, + file->f_flags & O_NONBLOCK, + buf, count, ppos); + if (result < 0) + return result; + dfil->todo -= result; + return (result + done); +} + +static ssize_t +dvb_demux_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct dmxdev_filter *dmxdevfilter = file->private_data; + int ret; + + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) + return -ERESTARTSYS; + + if (dmxdevfilter->type == DMXDEV_TYPE_SEC) + ret = dvb_dmxdev_read_sec(dmxdevfilter, file, buf, count, ppos); + else + ret = dvb_dmxdev_buffer_read(&dmxdevfilter->buffer, + file->f_flags & O_NONBLOCK, + buf, count, ppos); + + mutex_unlock(&dmxdevfilter->mutex); + return ret; +} + +static int dvb_demux_do_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dmxdev_filter *dmxdevfilter = file->private_data; + struct dmxdev *dmxdev = dmxdevfilter->dev; + unsigned long arg = (unsigned long)parg; + int ret = 0; + + if (mutex_lock_interruptible(&dmxdev->mutex)) + return -ERESTARTSYS; + + switch (cmd) { + case DMX_START: + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { + mutex_unlock(&dmxdev->mutex); + return -ERESTARTSYS; + } + if (dmxdevfilter->state < DMXDEV_STATE_SET) + ret = -EINVAL; + else + ret = dvb_dmxdev_filter_start(dmxdevfilter); + mutex_unlock(&dmxdevfilter->mutex); + break; + + case DMX_STOP: + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { + mutex_unlock(&dmxdev->mutex); + return -ERESTARTSYS; + } + ret = dvb_dmxdev_filter_stop(dmxdevfilter); + mutex_unlock(&dmxdevfilter->mutex); + break; + + case DMX_SET_FILTER: + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { + mutex_unlock(&dmxdev->mutex); + return -ERESTARTSYS; + } + ret = dvb_dmxdev_filter_set(dmxdev, dmxdevfilter, parg); + mutex_unlock(&dmxdevfilter->mutex); + break; + + case DMX_SET_PES_FILTER: + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { + mutex_unlock(&dmxdev->mutex); + return -ERESTARTSYS; + } + ret = dvb_dmxdev_pes_filter_set(dmxdev, dmxdevfilter, parg); + mutex_unlock(&dmxdevfilter->mutex); + break; + + case DMX_SET_BUFFER_SIZE: + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { + mutex_unlock(&dmxdev->mutex); + return -ERESTARTSYS; + } + ret = dvb_dmxdev_set_buffer_size(dmxdevfilter, arg); + mutex_unlock(&dmxdevfilter->mutex); + break; + + case DMX_GET_PES_PIDS: + if (!dmxdev->demux->get_pes_pids) { + ret = -EINVAL; + break; + } + dmxdev->demux->get_pes_pids(dmxdev->demux, parg); + break; + + case DMX_GET_CAPS: + if (!dmxdev->demux->get_caps) { + ret = -EINVAL; + break; + } + ret = dmxdev->demux->get_caps(dmxdev->demux, parg); + break; + + case DMX_SET_SOURCE: + if (!dmxdev->demux->set_source) { + ret = -EINVAL; + break; + } + ret = dmxdev->demux->set_source(dmxdev->demux, parg); + break; + + case DMX_GET_STC: + if (!dmxdev->demux->get_stc) { + ret = -EINVAL; + break; + } + ret = dmxdev->demux->get_stc(dmxdev->demux, + ((struct dmx_stc *)parg)->num, + &((struct dmx_stc *)parg)->stc, + &((struct dmx_stc *)parg)->base); + break; + + case DMX_ADD_PID: + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { + ret = -ERESTARTSYS; + break; + } + ret = dvb_dmxdev_add_pid(dmxdev, dmxdevfilter, *(u16 *)parg); + mutex_unlock(&dmxdevfilter->mutex); + break; + + case DMX_REMOVE_PID: + if (mutex_lock_interruptible(&dmxdevfilter->mutex)) { + ret = -ERESTARTSYS; + break; + } + ret = dvb_dmxdev_remove_pid(dmxdev, dmxdevfilter, *(u16 *)parg); + mutex_unlock(&dmxdevfilter->mutex); + break; + + default: + ret = -EINVAL; + break; + } + mutex_unlock(&dmxdev->mutex); + return ret; +} + +static long dvb_demux_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return dvb_usercopy(file, cmd, arg, dvb_demux_do_ioctl); +} + +static unsigned int dvb_demux_poll(struct file *file, poll_table *wait) +{ + struct dmxdev_filter *dmxdevfilter = file->private_data; + unsigned int mask = 0; + + if (!dmxdevfilter) + return -EINVAL; + + poll_wait(file, &dmxdevfilter->buffer.queue, wait); + + if (dmxdevfilter->state != DMXDEV_STATE_GO && + dmxdevfilter->state != DMXDEV_STATE_DONE && + dmxdevfilter->state != DMXDEV_STATE_TIMEDOUT) + return 0; + + if (dmxdevfilter->buffer.error) + mask |= (POLLIN | POLLRDNORM | POLLPRI | POLLERR); + + if (!dvb_ringbuffer_empty(&dmxdevfilter->buffer)) + mask |= (POLLIN | POLLRDNORM | POLLPRI); + + return mask; +} + +static int dvb_demux_release(struct inode *inode, struct file *file) +{ + struct dmxdev_filter *dmxdevfilter = file->private_data; + struct dmxdev *dmxdev = dmxdevfilter->dev; + + int ret; + + ret = dvb_dmxdev_filter_free(dmxdev, dmxdevfilter); + + mutex_lock(&dmxdev->mutex); + dmxdev->dvbdev->users--; + if(dmxdev->dvbdev->users==1 && dmxdev->exit==1) { + fops_put(file->f_op); + file->f_op = NULL; + mutex_unlock(&dmxdev->mutex); + wake_up(&dmxdev->dvbdev->wait_queue); + } else + mutex_unlock(&dmxdev->mutex); + + return ret; +} + +static const struct file_operations dvb_demux_fops = { + .owner = THIS_MODULE, + .read = dvb_demux_read, + .unlocked_ioctl = dvb_demux_ioctl, + .open = dvb_demux_open, + .release = dvb_demux_release, + .poll = dvb_demux_poll, + .llseek = default_llseek, +}; + +static struct dvb_device dvbdev_demux = { + .priv = NULL, + .users = 1, + .writers = 1, + .fops = &dvb_demux_fops +}; + +static int dvb_dvr_do_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct dmxdev *dmxdev = dvbdev->priv; + unsigned long arg = (unsigned long)parg; + int ret; + + if (mutex_lock_interruptible(&dmxdev->mutex)) + return -ERESTARTSYS; + + switch (cmd) { + case DMX_SET_BUFFER_SIZE: + ret = dvb_dvr_set_buffer_size(dmxdev, arg); + break; + + default: + ret = -EINVAL; + break; + } + mutex_unlock(&dmxdev->mutex); + return ret; +} + +static long dvb_dvr_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return dvb_usercopy(file, cmd, arg, dvb_dvr_do_ioctl); +} + +static unsigned int dvb_dvr_poll(struct file *file, poll_table *wait) +{ + struct dvb_device *dvbdev = file->private_data; + struct dmxdev *dmxdev = dvbdev->priv; + unsigned int mask = 0; + + dprintk("function : %s\n", __func__); + + poll_wait(file, &dmxdev->dvr_buffer.queue, wait); + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + if (dmxdev->dvr_buffer.error) + mask |= (POLLIN | POLLRDNORM | POLLPRI | POLLERR); + + if (!dvb_ringbuffer_empty(&dmxdev->dvr_buffer)) + mask |= (POLLIN | POLLRDNORM | POLLPRI); + } else + mask |= (POLLOUT | POLLWRNORM | POLLPRI); + + return mask; +} + +static const struct file_operations dvb_dvr_fops = { + .owner = THIS_MODULE, + .read = dvb_dvr_read, + .write = dvb_dvr_write, + .unlocked_ioctl = dvb_dvr_ioctl, + .open = dvb_dvr_open, + .release = dvb_dvr_release, + .poll = dvb_dvr_poll, + .llseek = default_llseek, +}; + +static struct dvb_device dvbdev_dvr = { + .priv = NULL, + .readers = 1, + .users = 1, + .fops = &dvb_dvr_fops +}; + +int dvb_dmxdev_init(struct dmxdev *dmxdev, struct dvb_adapter *dvb_adapter) +{ + int i; + + if (dmxdev->demux->open(dmxdev->demux) < 0) + return -EUSERS; + + dmxdev->filter = vmalloc(dmxdev->filternum * sizeof(struct dmxdev_filter)); + if (!dmxdev->filter) + return -ENOMEM; + + mutex_init(&dmxdev->mutex); + spin_lock_init(&dmxdev->lock); + for (i = 0; i < dmxdev->filternum; i++) { + dmxdev->filter[i].dev = dmxdev; + dmxdev->filter[i].buffer.data = NULL; + dvb_dmxdev_filter_state_set(&dmxdev->filter[i], + DMXDEV_STATE_FREE); + } + + dvb_register_device(dvb_adapter, &dmxdev->dvbdev, &dvbdev_demux, dmxdev, + DVB_DEVICE_DEMUX); + dvb_register_device(dvb_adapter, &dmxdev->dvr_dvbdev, &dvbdev_dvr, + dmxdev, DVB_DEVICE_DVR); + + dvb_ringbuffer_init(&dmxdev->dvr_buffer, NULL, 8192); + + return 0; +} + +EXPORT_SYMBOL(dvb_dmxdev_init); + +void dvb_dmxdev_release(struct dmxdev *dmxdev) +{ + dmxdev->exit=1; + if (dmxdev->dvbdev->users > 1) { + wait_event(dmxdev->dvbdev->wait_queue, + dmxdev->dvbdev->users==1); + } + if (dmxdev->dvr_dvbdev->users > 1) { + wait_event(dmxdev->dvr_dvbdev->wait_queue, + dmxdev->dvr_dvbdev->users==1); + } + + dvb_unregister_device(dmxdev->dvbdev); + dvb_unregister_device(dmxdev->dvr_dvbdev); + + vfree(dmxdev->filter); + dmxdev->filter = NULL; + dmxdev->demux->close(dmxdev->demux); +} + +EXPORT_SYMBOL(dvb_dmxdev_release); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dmxdev.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,119 @@ +/* + * dmxdev.h + * + * Copyright (C) 2000 Ralph Metzler & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DMXDEV_H_ +#define _DMXDEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "dvbdev.h" +#include "demux.h" +#include "dvb_ringbuffer.h" + +enum dmxdev_type { + DMXDEV_TYPE_NONE, + DMXDEV_TYPE_SEC, + DMXDEV_TYPE_PES, +}; + +enum dmxdev_state { + DMXDEV_STATE_FREE, + DMXDEV_STATE_ALLOCATED, + DMXDEV_STATE_SET, + DMXDEV_STATE_GO, + DMXDEV_STATE_DONE, + DMXDEV_STATE_TIMEDOUT +}; + +struct dmxdev_feed { + u16 pid; + struct dmx_ts_feed *ts; + struct list_head next; +}; + +struct dmxdev_filter { + union { + struct dmx_section_filter *sec; + } filter; + + union { + /* list of TS and PES feeds (struct dmxdev_feed) */ + struct list_head ts; + struct dmx_section_feed *sec; + } feed; + + union { + struct dmx_sct_filter_params sec; + struct dmx_pes_filter_params pes; + } params; + + enum dmxdev_type type; + enum dmxdev_state state; + struct dmxdev *dev; + struct dvb_ringbuffer buffer; + + struct mutex mutex; + + /* only for sections */ + struct timer_list timer; + int todo; + u8 secheader[3]; +}; + + +struct dmxdev { + struct dvb_device *dvbdev; + struct dvb_device *dvr_dvbdev; + + struct dmxdev_filter *filter; + struct dmx_demux *demux; + + int filternum; + int capabilities; + + unsigned int exit:1; +#define DMXDEV_CAP_DUPLEX 1 + struct dmx_frontend *dvr_orig_fe; + + struct dvb_ringbuffer dvr_buffer; +#define DVR_BUFFER_SIZE (10*188*1024) + + struct mutex mutex; + spinlock_t lock; +}; + + +int dvb_dmxdev_init(struct dmxdev *dmxdev, struct dvb_adapter *); +void dvb_dmxdev_release(struct dmxdev *dmxdev); + +#endif /* _DMXDEV_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1803 @@ +/* + * dvb_ca.c: generic DVB functions for EN50221 CAM interfaces + * + * Copyright (C) 2004 Andrew de Quincey + * + * Parts of this file were based on sources as follows: + * + * Copyright (C) 2003 Ralph Metzler + * + * based on code: + * + * Copyright (C) 1999-2002 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_ca_en50221.h" +#include "dvb_ringbuffer.h" + +static int dvb_ca_en50221_debug; + +module_param_named(cam_debug, dvb_ca_en50221_debug, int, 0644); +MODULE_PARM_DESC(cam_debug, "enable verbose debug messages"); + +#define dprintk if (dvb_ca_en50221_debug) printk + +#define INIT_TIMEOUT_SECS 10 + +#define HOST_LINK_BUF_SIZE 0x200 + +#define RX_BUFFER_SIZE 65535 + +#define MAX_RX_PACKETS_PER_ITERATION 10 + +#define CTRLIF_DATA 0 +#define CTRLIF_COMMAND 1 +#define CTRLIF_STATUS 1 +#define CTRLIF_SIZE_LOW 2 +#define CTRLIF_SIZE_HIGH 3 + +#define CMDREG_HC 1 /* Host control */ +#define CMDREG_SW 2 /* Size write */ +#define CMDREG_SR 4 /* Size read */ +#define CMDREG_RS 8 /* Reset interface */ +#define CMDREG_FRIE 0x40 /* Enable FR interrupt */ +#define CMDREG_DAIE 0x80 /* Enable DA interrupt */ +#define IRQEN (CMDREG_DAIE) + +#define STATUSREG_RE 1 /* read error */ +#define STATUSREG_WE 2 /* write error */ +#define STATUSREG_FR 0x40 /* module free */ +#define STATUSREG_DA 0x80 /* data available */ +#define STATUSREG_TXERR (STATUSREG_RE|STATUSREG_WE) /* general transfer error */ + + +#define DVB_CA_SLOTSTATE_NONE 0 +#define DVB_CA_SLOTSTATE_UNINITIALISED 1 +#define DVB_CA_SLOTSTATE_RUNNING 2 +#define DVB_CA_SLOTSTATE_INVALID 3 +#define DVB_CA_SLOTSTATE_WAITREADY 4 +#define DVB_CA_SLOTSTATE_VALIDATE 5 +#define DVB_CA_SLOTSTATE_WAITFR 6 +#define DVB_CA_SLOTSTATE_LINKINIT 7 + + +/* Information on a CA slot */ +struct dvb_ca_slot { + + /* current state of the CAM */ + int slot_state; + + /* mutex used for serializing access to one CI slot */ + struct mutex slot_lock; + + /* Number of CAMCHANGES that have occurred since last processing */ + atomic_t camchange_count; + + /* Type of last CAMCHANGE */ + int camchange_type; + + /* base address of CAM config */ + u32 config_base; + + /* value to write into Config Control register */ + u8 config_option; + + /* if 1, the CAM supports DA IRQs */ + u8 da_irq_supported:1; + + /* size of the buffer to use when talking to the CAM */ + int link_buf_size; + + /* buffer for incoming packets */ + struct dvb_ringbuffer rx_buffer; + + /* timer used during various states of the slot */ + unsigned long timeout; +}; + +/* Private CA-interface information */ +struct dvb_ca_private { + + /* pointer back to the public data structure */ + struct dvb_ca_en50221 *pub; + + /* the DVB device */ + struct dvb_device *dvbdev; + + /* Flags describing the interface (DVB_CA_FLAG_*) */ + u32 flags; + + /* number of slots supported by this CA interface */ + unsigned int slot_count; + + /* information on each slot */ + struct dvb_ca_slot *slot_info; + + /* wait queues for read() and write() operations */ + wait_queue_head_t wait_queue; + + /* PID of the monitoring thread */ + struct task_struct *thread; + + /* Flag indicating if the CA device is open */ + unsigned int open:1; + + /* Flag indicating the thread should wake up now */ + unsigned int wakeup:1; + + /* Delay the main thread should use */ + unsigned long delay; + + /* Slot to start looking for data to read from in the next user-space read operation */ + int next_read_slot; + + /* mutex serializing ioctls */ + struct mutex ioctl_mutex; +}; + +static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca); +static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 * ebuf, int ecount); +static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * ebuf, int ecount); + + +/** + * Safely find needle in haystack. + * + * @param haystack Buffer to look in. + * @param hlen Number of bytes in haystack. + * @param needle Buffer to find. + * @param nlen Number of bytes in needle. + * @return Pointer into haystack needle was found at, or NULL if not found. + */ +static char *findstr(char * haystack, int hlen, char * needle, int nlen) +{ + int i; + + if (hlen < nlen) + return NULL; + + for (i = 0; i <= hlen - nlen; i++) { + if (!strncmp(haystack + i, needle, nlen)) + return haystack + i; + } + + return NULL; +} + + + +/* ******************************************************************************** */ +/* EN50221 physical interface functions */ + + +/** + * Check CAM status. + */ +static int dvb_ca_en50221_check_camstatus(struct dvb_ca_private *ca, int slot) +{ + int slot_status; + int cam_present_now; + int cam_changed; + + /* IRQ mode */ + if (ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE) { + return (atomic_read(&ca->slot_info[slot].camchange_count) != 0); + } + + /* poll mode */ + slot_status = ca->pub->poll_slot_status(ca->pub, slot, ca->open); + + cam_present_now = (slot_status & DVB_CA_EN50221_POLL_CAM_PRESENT) ? 1 : 0; + cam_changed = (slot_status & DVB_CA_EN50221_POLL_CAM_CHANGED) ? 1 : 0; + if (!cam_changed) { + int cam_present_old = (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_NONE); + cam_changed = (cam_present_now != cam_present_old); + } + + if (cam_changed) { + if (!cam_present_now) { + ca->slot_info[slot].camchange_type = DVB_CA_EN50221_CAMCHANGE_REMOVED; + } else { + ca->slot_info[slot].camchange_type = DVB_CA_EN50221_CAMCHANGE_INSERTED; + } + atomic_set(&ca->slot_info[slot].camchange_count, 1); + } else { + if ((ca->slot_info[slot].slot_state == DVB_CA_SLOTSTATE_WAITREADY) && + (slot_status & DVB_CA_EN50221_POLL_CAM_READY)) { + // move to validate state if reset is completed + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_VALIDATE; + } + } + + return cam_changed; +} + + +/** + * Wait for flags to become set on the STATUS register on a CAM interface, + * checking for errors and timeout. + * + * @param ca CA instance. + * @param slot Slot on interface. + * @param waitfor Flags to wait for. + * @param timeout_ms Timeout in milliseconds. + * + * @return 0 on success, nonzero on error. + */ +static int dvb_ca_en50221_wait_if_status(struct dvb_ca_private *ca, int slot, + u8 waitfor, int timeout_hz) +{ + unsigned long timeout; + unsigned long start; + + dprintk("%s\n", __func__); + + /* loop until timeout elapsed */ + start = jiffies; + timeout = jiffies + timeout_hz; + while (1) { + /* read the status and check for error */ + int res = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS); + if (res < 0) + return -EIO; + + /* if we got the flags, it was successful! */ + if (res & waitfor) { + dprintk("%s succeeded timeout:%lu\n", __func__, jiffies - start); + return 0; + } + + /* check for timeout */ + if (time_after(jiffies, timeout)) { + break; + } + + /* wait for a bit */ + msleep(1); + } + + dprintk("%s failed timeout:%lu\n", __func__, jiffies - start); + + /* if we get here, we've timed out */ + return -ETIMEDOUT; +} + + +/** + * Initialise the link layer connection to a CAM. + * + * @param ca CA instance. + * @param slot Slot id. + * + * @return 0 on success, nonzero on failure. + */ +static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot) +{ + int ret; + int buf_size; + u8 buf[2]; + + dprintk("%s\n", __func__); + + /* we'll be determining these during this function */ + ca->slot_info[slot].da_irq_supported = 0; + + /* set the host link buffer size temporarily. it will be overwritten with the + * real negotiated size later. */ + ca->slot_info[slot].link_buf_size = 2; + + /* read the buffer size from the CAM */ + if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN | CMDREG_SR)) != 0) + return ret; + if ((ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_DA, HZ / 10)) != 0) + return ret; + if ((ret = dvb_ca_en50221_read_data(ca, slot, buf, 2)) != 2) + return -EIO; + if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN)) != 0) + return ret; + + /* store it, and choose the minimum of our buffer and the CAM's buffer size */ + buf_size = (buf[0] << 8) | buf[1]; + if (buf_size > HOST_LINK_BUF_SIZE) + buf_size = HOST_LINK_BUF_SIZE; + ca->slot_info[slot].link_buf_size = buf_size; + buf[0] = buf_size >> 8; + buf[1] = buf_size & 0xff; + dprintk("Chosen link buffer size of %i\n", buf_size); + + /* write the buffer size to the CAM */ + if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN | CMDREG_SW)) != 0) + return ret; + if ((ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_FR, HZ / 10)) != 0) + return ret; + if ((ret = dvb_ca_en50221_write_data(ca, slot, buf, 2)) != 2) + return -EIO; + if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN)) != 0) + return ret; + + /* success */ + return 0; +} + +/** + * Read a tuple from attribute memory. + * + * @param ca CA instance. + * @param slot Slot id. + * @param address Address to read from. Updated. + * @param tupleType Tuple id byte. Updated. + * @param tupleLength Tuple length. Updated. + * @param tuple Dest buffer for tuple (must be 256 bytes). Updated. + * + * @return 0 on success, nonzero on error. + */ +static int dvb_ca_en50221_read_tuple(struct dvb_ca_private *ca, int slot, + int *address, int *tupleType, int *tupleLength, u8 * tuple) +{ + int i; + int _tupleType; + int _tupleLength; + int _address = *address; + + /* grab the next tuple length and type */ + if ((_tupleType = ca->pub->read_attribute_mem(ca->pub, slot, _address)) < 0) + return _tupleType; + if (_tupleType == 0xff) { + dprintk("END OF CHAIN TUPLE type:0x%x\n", _tupleType); + *address += 2; + *tupleType = _tupleType; + *tupleLength = 0; + return 0; + } + if ((_tupleLength = ca->pub->read_attribute_mem(ca->pub, slot, _address + 2)) < 0) + return _tupleLength; + _address += 4; + + dprintk("TUPLE type:0x%x length:%i\n", _tupleType, _tupleLength); + + /* read in the whole tuple */ + for (i = 0; i < _tupleLength; i++) { + tuple[i] = ca->pub->read_attribute_mem(ca->pub, slot, _address + (i * 2)); + dprintk(" 0x%02x: 0x%02x %c\n", + i, tuple[i] & 0xff, + ((tuple[i] > 31) && (tuple[i] < 127)) ? tuple[i] : '.'); + } + _address += (_tupleLength * 2); + + // success + *tupleType = _tupleType; + *tupleLength = _tupleLength; + *address = _address; + return 0; +} + + +/** + * Parse attribute memory of a CAM module, extracting Config register, and checking + * it is a DVB CAM module. + * + * @param ca CA instance. + * @param slot Slot id. + * + * @return 0 on success, <0 on failure. + */ +static int dvb_ca_en50221_parse_attributes(struct dvb_ca_private *ca, int slot) +{ + int address = 0; + int tupleLength; + int tupleType; + u8 tuple[257]; + char *dvb_str; + int rasz; + int status; + int got_cftableentry = 0; + int end_chain = 0; + int i; + u16 manfid = 0; + u16 devid = 0; + + + // CISTPL_DEVICE_0A + if ((status = + dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, &tupleLength, tuple)) < 0) + return status; + if (tupleType != 0x1D) + return -EINVAL; + + + + // CISTPL_DEVICE_0C + if ((status = + dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, &tupleLength, tuple)) < 0) + return status; + if (tupleType != 0x1C) + return -EINVAL; + + + + // CISTPL_VERS_1 + if ((status = + dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, &tupleLength, tuple)) < 0) + return status; + if (tupleType != 0x15) + return -EINVAL; + + + + // CISTPL_MANFID + if ((status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, + &tupleLength, tuple)) < 0) + return status; + if (tupleType != 0x20) + return -EINVAL; + if (tupleLength != 4) + return -EINVAL; + manfid = (tuple[1] << 8) | tuple[0]; + devid = (tuple[3] << 8) | tuple[2]; + + + + // CISTPL_CONFIG + if ((status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, + &tupleLength, tuple)) < 0) + return status; + if (tupleType != 0x1A) + return -EINVAL; + if (tupleLength < 3) + return -EINVAL; + + /* extract the configbase */ + rasz = tuple[0] & 3; + if (tupleLength < (3 + rasz + 14)) + return -EINVAL; + ca->slot_info[slot].config_base = 0; + for (i = 0; i < rasz + 1; i++) { + ca->slot_info[slot].config_base |= (tuple[2 + i] << (8 * i)); + } + + /* check it contains the correct DVB string */ + dvb_str = findstr((char *)tuple, tupleLength, "DVB_CI_V", 8); + if (dvb_str == NULL) + return -EINVAL; + if (tupleLength < ((dvb_str - (char *) tuple) + 12)) + return -EINVAL; + + /* is it a version we support? */ + if (strncmp(dvb_str + 8, "1.00", 4)) { + printk("dvb_ca adapter %d: Unsupported DVB CAM module version %c%c%c%c\n", + ca->dvbdev->adapter->num, dvb_str[8], dvb_str[9], dvb_str[10], dvb_str[11]); + return -EINVAL; + } + + /* process the CFTABLE_ENTRY tuples, and any after those */ + while ((!end_chain) && (address < 0x1000)) { + if ((status = dvb_ca_en50221_read_tuple(ca, slot, &address, &tupleType, + &tupleLength, tuple)) < 0) + return status; + switch (tupleType) { + case 0x1B: // CISTPL_CFTABLE_ENTRY + if (tupleLength < (2 + 11 + 17)) + break; + + /* if we've already parsed one, just use it */ + if (got_cftableentry) + break; + + /* get the config option */ + ca->slot_info[slot].config_option = tuple[0] & 0x3f; + + /* OK, check it contains the correct strings */ + if ((findstr((char *)tuple, tupleLength, "DVB_HOST", 8) == NULL) || + (findstr((char *)tuple, tupleLength, "DVB_CI_MODULE", 13) == NULL)) + break; + + got_cftableentry = 1; + break; + + case 0x14: // CISTPL_NO_LINK + break; + + case 0xFF: // CISTPL_END + end_chain = 1; + break; + + default: /* Unknown tuple type - just skip this tuple and move to the next one */ + dprintk("dvb_ca: Skipping unknown tuple type:0x%x length:0x%x\n", tupleType, + tupleLength); + break; + } + } + + if ((address > 0x1000) || (!got_cftableentry)) + return -EINVAL; + + dprintk("Valid DVB CAM detected MANID:%x DEVID:%x CONFIGBASE:0x%x CONFIGOPTION:0x%x\n", + manfid, devid, ca->slot_info[slot].config_base, ca->slot_info[slot].config_option); + + // success! + return 0; +} + + +/** + * Set CAM's configoption correctly. + * + * @param ca CA instance. + * @param slot Slot containing the CAM. + */ +static int dvb_ca_en50221_set_configoption(struct dvb_ca_private *ca, int slot) +{ + int configoption; + + dprintk("%s\n", __func__); + + /* set the config option */ + ca->pub->write_attribute_mem(ca->pub, slot, + ca->slot_info[slot].config_base, + ca->slot_info[slot].config_option); + + /* check it */ + configoption = ca->pub->read_attribute_mem(ca->pub, slot, ca->slot_info[slot].config_base); + dprintk("Set configoption 0x%x, read configoption 0x%x\n", + ca->slot_info[slot].config_option, configoption & 0x3f); + + /* fine! */ + return 0; + +} + + +/** + * This function talks to an EN50221 CAM control interface. It reads a buffer of + * data from the CAM. The data can either be stored in a supplied buffer, or + * automatically be added to the slot's rx_buffer. + * + * @param ca CA instance. + * @param slot Slot to read from. + * @param ebuf If non-NULL, the data will be written to this buffer. If NULL, + * the data will be added into the buffering system as a normal fragment. + * @param ecount Size of ebuf. Ignored if ebuf is NULL. + * + * @return Number of bytes read, or < 0 on error + */ +static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 * ebuf, int ecount) +{ + int bytes_read; + int status; + u8 buf[HOST_LINK_BUF_SIZE]; + int i; + + dprintk("%s\n", __func__); + + /* check if we have space for a link buf in the rx_buffer */ + if (ebuf == NULL) { + int buf_free; + + if (ca->slot_info[slot].rx_buffer.data == NULL) { + status = -EIO; + goto exit; + } + buf_free = dvb_ringbuffer_free(&ca->slot_info[slot].rx_buffer); + + if (buf_free < (ca->slot_info[slot].link_buf_size + DVB_RINGBUFFER_PKTHDRSIZE)) { + status = -EAGAIN; + goto exit; + } + } + + if (ca->pub->read_data && (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_LINKINIT)) { + if (ebuf == NULL) + status = ca->pub->read_data(ca->pub, slot, buf, sizeof(buf)); + else + status = ca->pub->read_data(ca->pub, slot, buf, ecount); + if (status < 0) + return status; + bytes_read = status; + if (status == 0) + goto exit; + } else { + + /* check if there is data available */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) + goto exit; + if (!(status & STATUSREG_DA)) { + /* no data */ + status = 0; + goto exit; + } + + /* read the amount of data */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH)) < 0) + goto exit; + bytes_read = status << 8; + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_LOW)) < 0) + goto exit; + bytes_read |= status; + + /* check it will fit */ + if (ebuf == NULL) { + if (bytes_read > ca->slot_info[slot].link_buf_size) { + printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the link buffer size (%i > %i)!\n", + ca->dvbdev->adapter->num, bytes_read, ca->slot_info[slot].link_buf_size); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; + status = -EIO; + goto exit; + } + if (bytes_read < 2) { + printk("dvb_ca adapter %d: CAM sent a buffer that was less than 2 bytes!\n", + ca->dvbdev->adapter->num); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; + status = -EIO; + goto exit; + } + } else { + if (bytes_read > ecount) { + printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the ecount size!\n", + ca->dvbdev->adapter->num); + status = -EIO; + goto exit; + } + } + + /* fill the buffer */ + for (i = 0; i < bytes_read; i++) { + /* read byte and check */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_DATA)) < 0) + goto exit; + + /* OK, store it in the buffer */ + buf[i] = status; + } + + /* check for read error (RE should now be 0) */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) + goto exit; + if (status & STATUSREG_RE) { + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; + status = -EIO; + goto exit; + } + } + /* OK, add it to the receive buffer, or copy into external buffer if supplied */ + if (ebuf == NULL) { + if (ca->slot_info[slot].rx_buffer.data == NULL) { + status = -EIO; + goto exit; + } + dvb_ringbuffer_pkt_write(&ca->slot_info[slot].rx_buffer, buf, bytes_read); + } else { + memcpy(ebuf, buf, bytes_read); + } + + dprintk("Received CA packet for slot %i connection id 0x%x last_frag:%i size:0x%x\n", slot, + buf[0], (buf[1] & 0x80) == 0, bytes_read); + + /* wake up readers when a last_fragment is received */ + if ((buf[1] & 0x80) == 0x00) { + wake_up_interruptible(&ca->wait_queue); + } + status = bytes_read; + +exit: + return status; +} + + +/** + * This function talks to an EN50221 CAM control interface. It writes a buffer of data + * to a CAM. + * + * @param ca CA instance. + * @param slot Slot to write to. + * @param ebuf The data in this buffer is treated as a complete link-level packet to + * be written. + * @param count Size of ebuf. + * + * @return Number of bytes written, or < 0 on error. + */ +static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * buf, int bytes_write) +{ + int status; + int i; + + dprintk("%s\n", __func__); + + + /* sanity check */ + if (bytes_write > ca->slot_info[slot].link_buf_size) + return -EINVAL; + + if (ca->pub->write_data && (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_LINKINIT)) + return ca->pub->write_data(ca->pub, slot, buf, bytes_write); + + /* it is possible we are dealing with a single buffer implementation, + thus if there is data available for read or if there is even a read + already in progress, we do nothing but awake the kernel thread to + process the data if necessary. */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) + goto exitnowrite; + if (status & (STATUSREG_DA | STATUSREG_RE)) { + if (status & STATUSREG_DA) + dvb_ca_en50221_thread_wakeup(ca); + + status = -EAGAIN; + goto exitnowrite; + } + + /* OK, set HC bit */ + if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, + IRQEN | CMDREG_HC)) != 0) + goto exit; + + /* check if interface is still free */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) + goto exit; + if (!(status & STATUSREG_FR)) { + /* it wasn't free => try again later */ + status = -EAGAIN; + goto exit; + } + + /* It may need some time for the CAM to settle down, or there might be a + race condition between the CAM, writing HC and our last check for DA. + This happens, if the CAM asserts DA, just after checking DA before we + are setting HC. In this case it might be a bug in the CAM to keep the + FR bit, the lower layer/HW communication requires a longer timeout or + the CAM needs more time internally. But this happens in reality! + We need to read the status from the HW again and do the same we did + for the previous check for DA */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) + goto exit; + if (status & (STATUSREG_DA | STATUSREG_RE)) { + if (status & STATUSREG_DA) + dvb_ca_en50221_thread_wakeup(ca); + + status = -EAGAIN; + goto exit; + } + + /* send the amount of data */ + if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH, bytes_write >> 8)) != 0) + goto exit; + if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_LOW, + bytes_write & 0xff)) != 0) + goto exit; + + /* send the buffer */ + for (i = 0; i < bytes_write; i++) { + if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_DATA, buf[i])) != 0) + goto exit; + } + + /* check for write error (WE should now be 0) */ + if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) + goto exit; + if (status & STATUSREG_WE) { + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; + status = -EIO; + goto exit; + } + status = bytes_write; + + dprintk("Wrote CA packet for slot %i, connection id 0x%x last_frag:%i size:0x%x\n", slot, + buf[0], (buf[1] & 0x80) == 0, bytes_write); + +exit: + ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN); + +exitnowrite: + return status; +} +EXPORT_SYMBOL(dvb_ca_en50221_camchange_irq); + + + +/* ******************************************************************************** */ +/* EN50221 higher level functions */ + + +/** + * A CAM has been removed => shut it down. + * + * @param ca CA instance. + * @param slot Slot to shut down. + */ +static int dvb_ca_en50221_slot_shutdown(struct dvb_ca_private *ca, int slot) +{ + dprintk("%s\n", __func__); + + ca->pub->slot_shutdown(ca->pub, slot); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE; + + /* need to wake up all processes to check if they're now + trying to write to a defunct CAM */ + wake_up_interruptible(&ca->wait_queue); + + dprintk("Slot %i shutdown\n", slot); + + /* success */ + return 0; +} +EXPORT_SYMBOL(dvb_ca_en50221_camready_irq); + + +/** + * A CAMCHANGE IRQ has occurred. + * + * @param ca CA instance. + * @param slot Slot concerned. + * @param change_type One of the DVB_CA_CAMCHANGE_* values. + */ +void dvb_ca_en50221_camchange_irq(struct dvb_ca_en50221 *pubca, int slot, int change_type) +{ + struct dvb_ca_private *ca = pubca->private; + + dprintk("CAMCHANGE IRQ slot:%i change_type:%i\n", slot, change_type); + + switch (change_type) { + case DVB_CA_EN50221_CAMCHANGE_REMOVED: + case DVB_CA_EN50221_CAMCHANGE_INSERTED: + break; + + default: + return; + } + + ca->slot_info[slot].camchange_type = change_type; + atomic_inc(&ca->slot_info[slot].camchange_count); + dvb_ca_en50221_thread_wakeup(ca); +} +EXPORT_SYMBOL(dvb_ca_en50221_frda_irq); + + +/** + * A CAMREADY IRQ has occurred. + * + * @param ca CA instance. + * @param slot Slot concerned. + */ +void dvb_ca_en50221_camready_irq(struct dvb_ca_en50221 *pubca, int slot) +{ + struct dvb_ca_private *ca = pubca->private; + + dprintk("CAMREADY IRQ slot:%i\n", slot); + + if (ca->slot_info[slot].slot_state == DVB_CA_SLOTSTATE_WAITREADY) { + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_VALIDATE; + dvb_ca_en50221_thread_wakeup(ca); + } +} + + +/** + * An FR or DA IRQ has occurred. + * + * @param ca CA instance. + * @param slot Slot concerned. + */ +void dvb_ca_en50221_frda_irq(struct dvb_ca_en50221 *pubca, int slot) +{ + struct dvb_ca_private *ca = pubca->private; + int flags; + + dprintk("FR/DA IRQ slot:%i\n", slot); + + switch (ca->slot_info[slot].slot_state) { + case DVB_CA_SLOTSTATE_LINKINIT: + flags = ca->pub->read_cam_control(pubca, slot, CTRLIF_STATUS); + if (flags & STATUSREG_DA) { + dprintk("CAM supports DA IRQ\n"); + ca->slot_info[slot].da_irq_supported = 1; + } + break; + + case DVB_CA_SLOTSTATE_RUNNING: + if (ca->open) + dvb_ca_en50221_thread_wakeup(ca); + break; + } +} + + + +/* ******************************************************************************** */ +/* EN50221 thread functions */ + +/** + * Wake up the DVB CA thread + * + * @param ca CA instance. + */ +static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca) +{ + + dprintk("%s\n", __func__); + + ca->wakeup = 1; + mb(); + wake_up_process(ca->thread); +} + +/** + * Update the delay used by the thread. + * + * @param ca CA instance. + */ +static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca) +{ + int delay; + int curdelay = 100000000; + int slot; + + /* Beware of too high polling frequency, because one polling + * call might take several hundred milliseconds until timeout! + */ + for (slot = 0; slot < ca->slot_count; slot++) { + switch (ca->slot_info[slot].slot_state) { + default: + case DVB_CA_SLOTSTATE_NONE: + delay = HZ * 60; /* 60s */ + if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) + delay = HZ * 5; /* 5s */ + break; + case DVB_CA_SLOTSTATE_INVALID: + delay = HZ * 60; /* 60s */ + if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) + delay = HZ / 10; /* 100ms */ + break; + + case DVB_CA_SLOTSTATE_UNINITIALISED: + case DVB_CA_SLOTSTATE_WAITREADY: + case DVB_CA_SLOTSTATE_VALIDATE: + case DVB_CA_SLOTSTATE_WAITFR: + case DVB_CA_SLOTSTATE_LINKINIT: + delay = HZ / 10; /* 100ms */ + break; + + case DVB_CA_SLOTSTATE_RUNNING: + delay = HZ * 60; /* 60s */ + if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) + delay = HZ / 10; /* 100ms */ + if (ca->open) { + if ((!ca->slot_info[slot].da_irq_supported) || + (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_DA))) + delay = HZ / 10; /* 100ms */ + } + break; + } + + if (delay < curdelay) + curdelay = delay; + } + + ca->delay = curdelay; +} + + + +/** + * Kernel thread which monitors CA slots for CAM changes, and performs data transfers. + */ +static int dvb_ca_en50221_thread(void *data) +{ + struct dvb_ca_private *ca = data; + int slot; + int flags; + int status; + int pktcount; + void *rxbuf; + + dprintk("%s\n", __func__); + + /* choose the correct initial delay */ + dvb_ca_en50221_thread_update_delay(ca); + + /* main loop */ + while (!kthread_should_stop()) { + /* sleep for a bit */ + if (!ca->wakeup) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(ca->delay); + if (kthread_should_stop()) + return 0; + } + ca->wakeup = 0; + + /* go through all the slots processing them */ + for (slot = 0; slot < ca->slot_count; slot++) { + + mutex_lock(&ca->slot_info[slot].slot_lock); + + // check the cam status + deal with CAMCHANGEs + while (dvb_ca_en50221_check_camstatus(ca, slot)) { + /* clear down an old CI slot if necessary */ + if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_NONE) + dvb_ca_en50221_slot_shutdown(ca, slot); + + /* if a CAM is NOW present, initialise it */ + if (ca->slot_info[slot].camchange_type == DVB_CA_EN50221_CAMCHANGE_INSERTED) { + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_UNINITIALISED; + } + + /* we've handled one CAMCHANGE */ + dvb_ca_en50221_thread_update_delay(ca); + atomic_dec(&ca->slot_info[slot].camchange_count); + } + + // CAM state machine + switch (ca->slot_info[slot].slot_state) { + case DVB_CA_SLOTSTATE_NONE: + case DVB_CA_SLOTSTATE_INVALID: + // no action needed + break; + + case DVB_CA_SLOTSTATE_UNINITIALISED: + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_WAITREADY; + ca->pub->slot_reset(ca->pub, slot); + ca->slot_info[slot].timeout = jiffies + (INIT_TIMEOUT_SECS * HZ); + break; + + case DVB_CA_SLOTSTATE_WAITREADY: + if (time_after(jiffies, ca->slot_info[slot].timeout)) { + printk("dvb_ca adaptor %d: PC card did not respond :(\n", + ca->dvbdev->adapter->num); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + // no other action needed; will automatically change state when ready + break; + + case DVB_CA_SLOTSTATE_VALIDATE: + if (dvb_ca_en50221_parse_attributes(ca, slot) != 0) { + /* we need this extra check for annoying interfaces like the budget-av */ + if ((!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) && + (ca->pub->poll_slot_status)) { + status = ca->pub->poll_slot_status(ca->pub, slot, 0); + if (!(status & DVB_CA_EN50221_POLL_CAM_PRESENT)) { + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + } + + printk("dvb_ca adapter %d: Invalid PC card inserted :(\n", + ca->dvbdev->adapter->num); + //ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + if (dvb_ca_en50221_set_configoption(ca, slot) != 0) { + printk("dvb_ca adapter %d: Unable to initialise CAM :(\n", + ca->dvbdev->adapter->num); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + if (ca->pub->write_cam_control(ca->pub, slot, + CTRLIF_COMMAND, CMDREG_RS) != 0) { + printk("dvb_ca adapter %d: Unable to reset CAM IF\n", + ca->dvbdev->adapter->num); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + dprintk("DVB CAM validated successfully\n"); + + ca->slot_info[slot].timeout = jiffies + (INIT_TIMEOUT_SECS * HZ); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_WAITFR; + ca->wakeup = 1; + break; + + case DVB_CA_SLOTSTATE_WAITFR: + if (time_after(jiffies, ca->slot_info[slot].timeout)) { + printk("dvb_ca adapter %d: DVB CAM did not respond :(\n", + ca->dvbdev->adapter->num); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + + flags = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS); + if (flags & STATUSREG_FR) { + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; + ca->wakeup = 1; + } + break; + + case DVB_CA_SLOTSTATE_LINKINIT: + if (dvb_ca_en50221_link_init(ca, slot) != 0) { + /* we need this extra check for annoying interfaces like the budget-av */ + if ((!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) && + (ca->pub->poll_slot_status)) { + status = ca->pub->poll_slot_status(ca->pub, slot, 0); + if (!(status & DVB_CA_EN50221_POLL_CAM_PRESENT)) { + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_NONE; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + } + + printk("dvb_ca adapter %d: DVB CAM link initialisation failed :(\n", ca->dvbdev->adapter->num); +#if 1 + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; + dvb_ca_en50221_thread_update_delay(ca); +#else + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_UNINITIALISED; + dvb_ca_en50221_thread_update_delay(ca); +#endif + break; + } + + if (ca->slot_info[slot].rx_buffer.data == NULL) { + rxbuf = vmalloc(RX_BUFFER_SIZE); + if (rxbuf == NULL) { + printk("dvb_ca adapter %d: Unable to allocate CAM rx buffer :(\n", ca->dvbdev->adapter->num); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; + dvb_ca_en50221_thread_update_delay(ca); + break; + } + dvb_ringbuffer_init(&ca->slot_info[slot].rx_buffer, rxbuf, RX_BUFFER_SIZE); + } + + ca->pub->slot_ts_enable(ca->pub, slot); + ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_RUNNING; + dvb_ca_en50221_thread_update_delay(ca); + printk("dvb_ca adapter %d: DVB CAM detected and initialised successfully\n", ca->dvbdev->adapter->num); + break; + + case DVB_CA_SLOTSTATE_RUNNING: + if (!ca->open) + break; + + // poll slots for data + pktcount = 0; + while ((status = dvb_ca_en50221_read_data(ca, slot, NULL, 0)) > 0) { + if (!ca->open) + break; + + /* if a CAMCHANGE occurred at some point, do not do any more processing of this slot */ + if (dvb_ca_en50221_check_camstatus(ca, slot)) { + // we dont want to sleep on the next iteration so we can handle the cam change + ca->wakeup = 1; + break; + } + + /* check if we've hit our limit this time */ + if (++pktcount >= MAX_RX_PACKETS_PER_ITERATION) { + // dont sleep; there is likely to be more data to read + ca->wakeup = 1; + break; + } + } + break; + } + + mutex_unlock(&ca->slot_info[slot].slot_lock); + } + } + + return 0; +} + + + +/* ******************************************************************************** */ +/* EN50221 IO interface functions */ + +/** + * Real ioctl implementation. + * NOTE: CA_SEND_MSG/CA_GET_MSG ioctls have userspace buffers passed to them. + * + * @param inode Inode concerned. + * @param file File concerned. + * @param cmd IOCTL command. + * @param arg Associated argument. + * + * @return 0 on success, <0 on error. + */ +static int dvb_ca_en50221_io_do_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_ca_private *ca = dvbdev->priv; + int err = 0; + int slot; + + dprintk("%s\n", __func__); + + if (mutex_lock_interruptible(&ca->ioctl_mutex)) + return -ERESTARTSYS; + + switch (cmd) { + case CA_RESET: + for (slot = 0; slot < ca->slot_count; slot++) { + mutex_lock(&ca->slot_info[slot].slot_lock); + if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_NONE) { + dvb_ca_en50221_slot_shutdown(ca, slot); + if (ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE) + dvb_ca_en50221_camchange_irq(ca->pub, + slot, + DVB_CA_EN50221_CAMCHANGE_INSERTED); + } + mutex_unlock(&ca->slot_info[slot].slot_lock); + } + ca->next_read_slot = 0; + dvb_ca_en50221_thread_wakeup(ca); + break; + + case CA_GET_CAP: { + struct ca_caps *caps = parg; + + caps->slot_num = ca->slot_count; + caps->slot_type = CA_CI_LINK; + caps->descr_num = 0; + caps->descr_type = 0; + break; + } + + case CA_GET_SLOT_INFO: { + struct ca_slot_info *info = parg; + + if ((info->num > ca->slot_count) || (info->num < 0)) { + err = -EINVAL; + goto out_unlock; + } + + info->type = CA_CI_LINK; + info->flags = 0; + if ((ca->slot_info[info->num].slot_state != DVB_CA_SLOTSTATE_NONE) + && (ca->slot_info[info->num].slot_state != DVB_CA_SLOTSTATE_INVALID)) { + info->flags = CA_CI_MODULE_PRESENT; + } + if (ca->slot_info[info->num].slot_state == DVB_CA_SLOTSTATE_RUNNING) { + info->flags |= CA_CI_MODULE_READY; + } + break; + } + + default: + err = -EINVAL; + break; + } + +out_unlock: + mutex_unlock(&ca->ioctl_mutex); + return err; +} + + +/** + * Wrapper for ioctl implementation. + * + * @param inode Inode concerned. + * @param file File concerned. + * @param cmd IOCTL command. + * @param arg Associated argument. + * + * @return 0 on success, <0 on error. + */ +static long dvb_ca_en50221_io_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return dvb_usercopy(file, cmd, arg, dvb_ca_en50221_io_do_ioctl); +} + + +/** + * Implementation of write() syscall. + * + * @param file File structure. + * @param buf Source buffer. + * @param count Size of source buffer. + * @param ppos Position in file (ignored). + * + * @return Number of bytes read, or <0 on error. + */ +static ssize_t dvb_ca_en50221_io_write(struct file *file, + const char __user * buf, size_t count, loff_t * ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_ca_private *ca = dvbdev->priv; + u8 slot, connection_id; + int status; + u8 fragbuf[HOST_LINK_BUF_SIZE]; + int fragpos = 0; + int fraglen; + unsigned long timeout; + int written; + + dprintk("%s\n", __func__); + + /* Incoming packet has a 2 byte header. hdr[0] = slot_id, hdr[1] = connection_id */ + if (count < 2) + return -EINVAL; + + /* extract slot & connection id */ + if (copy_from_user(&slot, buf, 1)) + return -EFAULT; + if (copy_from_user(&connection_id, buf + 1, 1)) + return -EFAULT; + buf += 2; + count -= 2; + + /* check if the slot is actually running */ + if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_RUNNING) + return -EINVAL; + + /* fragment the packets & store in the buffer */ + while (fragpos < count) { + fraglen = ca->slot_info[slot].link_buf_size - 2; + if (fraglen < 0) + break; + if (fraglen > HOST_LINK_BUF_SIZE - 2) + fraglen = HOST_LINK_BUF_SIZE - 2; + if ((count - fragpos) < fraglen) + fraglen = count - fragpos; + + fragbuf[0] = connection_id; + fragbuf[1] = ((fragpos + fraglen) < count) ? 0x80 : 0x00; + status = copy_from_user(fragbuf + 2, buf + fragpos, fraglen); + if (status) { + status = -EFAULT; + goto exit; + } + + timeout = jiffies + HZ / 2; + written = 0; + while (!time_after(jiffies, timeout)) { + /* check the CAM hasn't been removed/reset in the meantime */ + if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_RUNNING) { + status = -EIO; + goto exit; + } + + mutex_lock(&ca->slot_info[slot].slot_lock); + status = dvb_ca_en50221_write_data(ca, slot, fragbuf, fraglen + 2); + mutex_unlock(&ca->slot_info[slot].slot_lock); + if (status == (fraglen + 2)) { + written = 1; + break; + } + if (status != -EAGAIN) + goto exit; + + msleep(1); + } + if (!written) { + status = -EIO; + goto exit; + } + + fragpos += fraglen; + } + status = count + 2; + +exit: + return status; +} + + +/** + * Condition for waking up in dvb_ca_en50221_io_read_condition + */ +static int dvb_ca_en50221_io_read_condition(struct dvb_ca_private *ca, + int *result, int *_slot) +{ + int slot; + int slot_count = 0; + int idx; + size_t fraglen; + int connection_id = -1; + int found = 0; + u8 hdr[2]; + + slot = ca->next_read_slot; + while ((slot_count < ca->slot_count) && (!found)) { + if (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_RUNNING) + goto nextslot; + + if (ca->slot_info[slot].rx_buffer.data == NULL) { + return 0; + } + + idx = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, -1, &fraglen); + while (idx != -1) { + dvb_ringbuffer_pkt_read(&ca->slot_info[slot].rx_buffer, idx, 0, hdr, 2); + if (connection_id == -1) + connection_id = hdr[0]; + if ((hdr[0] == connection_id) && ((hdr[1] & 0x80) == 0)) { + *_slot = slot; + found = 1; + break; + } + + idx = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, idx, &fraglen); + } + +nextslot: + slot = (slot + 1) % ca->slot_count; + slot_count++; + } + + ca->next_read_slot = slot; + return found; +} + + +/** + * Implementation of read() syscall. + * + * @param file File structure. + * @param buf Destination buffer. + * @param count Size of destination buffer. + * @param ppos Position in file (ignored). + * + * @return Number of bytes read, or <0 on error. + */ +static ssize_t dvb_ca_en50221_io_read(struct file *file, char __user * buf, + size_t count, loff_t * ppos) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_ca_private *ca = dvbdev->priv; + int status; + int result = 0; + u8 hdr[2]; + int slot; + int connection_id = -1; + size_t idx, idx2; + int last_fragment = 0; + size_t fraglen; + int pktlen; + int dispose = 0; + + dprintk("%s\n", __func__); + + /* Outgoing packet has a 2 byte header. hdr[0] = slot_id, hdr[1] = connection_id */ + if (count < 2) + return -EINVAL; + + /* wait for some data */ + if ((status = dvb_ca_en50221_io_read_condition(ca, &result, &slot)) == 0) { + + /* if we're in nonblocking mode, exit immediately */ + if (file->f_flags & O_NONBLOCK) + return -EWOULDBLOCK; + + /* wait for some data */ + status = wait_event_interruptible(ca->wait_queue, + dvb_ca_en50221_io_read_condition + (ca, &result, &slot)); + } + if ((status < 0) || (result < 0)) { + if (result) + return result; + return status; + } + + idx = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, -1, &fraglen); + pktlen = 2; + do { + if (idx == -1) { + printk("dvb_ca adapter %d: BUG: read packet ended before last_fragment encountered\n", ca->dvbdev->adapter->num); + status = -EIO; + goto exit; + } + + dvb_ringbuffer_pkt_read(&ca->slot_info[slot].rx_buffer, idx, 0, hdr, 2); + if (connection_id == -1) + connection_id = hdr[0]; + if (hdr[0] == connection_id) { + if (pktlen < count) { + if ((pktlen + fraglen - 2) > count) { + fraglen = count - pktlen; + } else { + fraglen -= 2; + } + + if ((status = dvb_ringbuffer_pkt_read_user(&ca->slot_info[slot].rx_buffer, idx, 2, + buf + pktlen, fraglen)) < 0) { + goto exit; + } + pktlen += fraglen; + } + + if ((hdr[1] & 0x80) == 0) + last_fragment = 1; + dispose = 1; + } + + idx2 = dvb_ringbuffer_pkt_next(&ca->slot_info[slot].rx_buffer, idx, &fraglen); + if (dispose) + dvb_ringbuffer_pkt_dispose(&ca->slot_info[slot].rx_buffer, idx); + idx = idx2; + dispose = 0; + } while (!last_fragment); + + hdr[0] = slot; + hdr[1] = connection_id; + status = copy_to_user(buf, hdr, 2); + if (status) { + status = -EFAULT; + goto exit; + } + status = pktlen; + +exit: + return status; +} + + +/** + * Implementation of file open syscall. + * + * @param inode Inode concerned. + * @param file File concerned. + * + * @return 0 on success, <0 on failure. + */ +static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_ca_private *ca = dvbdev->priv; + int err; + int i; + + dprintk("%s\n", __func__); + + if (!try_module_get(ca->pub->owner)) + return -EIO; + + err = dvb_generic_open(inode, file); + if (err < 0) { + module_put(ca->pub->owner); + return err; + } + + for (i = 0; i < ca->slot_count; i++) { + + if (ca->slot_info[i].slot_state == DVB_CA_SLOTSTATE_RUNNING) { + if (ca->slot_info[i].rx_buffer.data != NULL) { + /* it is safe to call this here without locks because + * ca->open == 0. Data is not read in this case */ + dvb_ringbuffer_flush(&ca->slot_info[i].rx_buffer); + } + } + } + + ca->open = 1; + dvb_ca_en50221_thread_update_delay(ca); + dvb_ca_en50221_thread_wakeup(ca); + + return 0; +} + + +/** + * Implementation of file close syscall. + * + * @param inode Inode concerned. + * @param file File concerned. + * + * @return 0 on success, <0 on failure. + */ +static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_ca_private *ca = dvbdev->priv; + int err; + + dprintk("%s\n", __func__); + + /* mark the CA device as closed */ + ca->open = 0; + dvb_ca_en50221_thread_update_delay(ca); + + err = dvb_generic_release(inode, file); + + module_put(ca->pub->owner); + + return err; +} + + +/** + * Implementation of poll() syscall. + * + * @param file File concerned. + * @param wait poll wait table. + * + * @return Standard poll mask. + */ +static unsigned int dvb_ca_en50221_io_poll(struct file *file, poll_table * wait) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_ca_private *ca = dvbdev->priv; + unsigned int mask = 0; + int slot; + int result = 0; + + dprintk("%s\n", __func__); + + if (dvb_ca_en50221_io_read_condition(ca, &result, &slot) == 1) { + mask |= POLLIN; + } + + /* if there is something, return now */ + if (mask) + return mask; + + /* wait for something to happen */ + poll_wait(file, &ca->wait_queue, wait); + + if (dvb_ca_en50221_io_read_condition(ca, &result, &slot) == 1) { + mask |= POLLIN; + } + + return mask; +} +EXPORT_SYMBOL(dvb_ca_en50221_init); + + +static const struct file_operations dvb_ca_fops = { + .owner = THIS_MODULE, + .read = dvb_ca_en50221_io_read, + .write = dvb_ca_en50221_io_write, + .unlocked_ioctl = dvb_ca_en50221_io_ioctl, + .open = dvb_ca_en50221_io_open, + .release = dvb_ca_en50221_io_release, + .poll = dvb_ca_en50221_io_poll, + .llseek = noop_llseek, +}; + +static struct dvb_device dvbdev_ca = { + .priv = NULL, + .users = 1, + .readers = 1, + .writers = 1, + .fops = &dvb_ca_fops, +}; + + +/* ******************************************************************************** */ +/* Initialisation/shutdown functions */ + + +/** + * Initialise a new DVB CA EN50221 interface device. + * + * @param dvb_adapter DVB adapter to attach the new CA device to. + * @param ca The dvb_ca instance. + * @param flags Flags describing the CA device (DVB_CA_FLAG_*). + * @param slot_count Number of slots supported. + * + * @return 0 on success, nonzero on failure + */ +int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter, + struct dvb_ca_en50221 *pubca, int flags, int slot_count) +{ + int ret; + struct dvb_ca_private *ca = NULL; + int i; + + dprintk("%s\n", __func__); + + if (slot_count < 1) + return -EINVAL; + + /* initialise the system data */ + if ((ca = kzalloc(sizeof(struct dvb_ca_private), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto error; + } + ca->pub = pubca; + ca->flags = flags; + ca->slot_count = slot_count; + if ((ca->slot_info = kcalloc(slot_count, sizeof(struct dvb_ca_slot), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto error; + } + init_waitqueue_head(&ca->wait_queue); + ca->open = 0; + ca->wakeup = 0; + ca->next_read_slot = 0; + pubca->private = ca; + + /* register the DVB device */ + ret = dvb_register_device(dvb_adapter, &ca->dvbdev, &dvbdev_ca, ca, DVB_DEVICE_CA); + if (ret) + goto error; + + /* now initialise each slot */ + for (i = 0; i < slot_count; i++) { + memset(&ca->slot_info[i], 0, sizeof(struct dvb_ca_slot)); + ca->slot_info[i].slot_state = DVB_CA_SLOTSTATE_NONE; + atomic_set(&ca->slot_info[i].camchange_count, 0); + ca->slot_info[i].camchange_type = DVB_CA_EN50221_CAMCHANGE_REMOVED; + mutex_init(&ca->slot_info[i].slot_lock); + } + + mutex_init(&ca->ioctl_mutex); + + if (signal_pending(current)) { + ret = -EINTR; + goto error; + } + mb(); + + /* create a kthread for monitoring this CA device */ + ca->thread = kthread_run(dvb_ca_en50221_thread, ca, "kdvb-ca-%i:%i", + ca->dvbdev->adapter->num, ca->dvbdev->id); + if (IS_ERR(ca->thread)) { + ret = PTR_ERR(ca->thread); + printk("dvb_ca_init: failed to start kernel_thread (%d)\n", + ret); + goto error; + } + return 0; + +error: + if (ca != NULL) { + if (ca->dvbdev != NULL) + dvb_unregister_device(ca->dvbdev); + kfree(ca->slot_info); + kfree(ca); + } + pubca->private = NULL; + return ret; +} +EXPORT_SYMBOL(dvb_ca_en50221_release); + + + +/** + * Release a DVB CA EN50221 interface device. + * + * @param ca_dev The dvb_device_t instance for the CA device. + * @param ca The associated dvb_ca instance. + */ +void dvb_ca_en50221_release(struct dvb_ca_en50221 *pubca) +{ + struct dvb_ca_private *ca = pubca->private; + int i; + + dprintk("%s\n", __func__); + + /* shutdown the thread if there was one */ + kthread_stop(ca->thread); + + for (i = 0; i < ca->slot_count; i++) { + dvb_ca_en50221_slot_shutdown(ca, i); + vfree(ca->slot_info[i].rx_buffer.data); + } + kfree(ca->slot_info); + dvb_unregister_device(ca->dvbdev); + kfree(ca); + pubca->private = NULL; +} diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ca_en50221.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,140 @@ +/* + * dvb_ca.h: generic DVB functions for EN50221 CA interfaces + * + * Copyright (C) 2004 Andrew de Quincey + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DVB_CA_EN50221_H_ +#define _DVB_CA_EN50221_H_ + +#include +#include + +#include "dvbdev.h" + +#define DVB_CA_EN50221_POLL_CAM_PRESENT 1 +#define DVB_CA_EN50221_POLL_CAM_CHANGED 2 +#define DVB_CA_EN50221_POLL_CAM_READY 4 + +#define DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE 1 +#define DVB_CA_EN50221_FLAG_IRQ_FR 2 +#define DVB_CA_EN50221_FLAG_IRQ_DA 4 + +#define DVB_CA_EN50221_CAMCHANGE_REMOVED 0 +#define DVB_CA_EN50221_CAMCHANGE_INSERTED 1 + + + +/* Structure describing a CA interface */ +struct dvb_ca_en50221 { + + /* the module owning this structure */ + struct module* owner; + + /* NOTE: the read_*, write_* and poll_slot_status functions will be + * called for different slots concurrently and need to use locks where + * and if appropriate. There will be no concurrent access to one slot. + */ + + /* functions for accessing attribute memory on the CAM */ + int (*read_attribute_mem)(struct dvb_ca_en50221* ca, int slot, int address); + int (*write_attribute_mem)(struct dvb_ca_en50221* ca, int slot, int address, u8 value); + + /* functions for accessing the control interface on the CAM */ + int (*read_cam_control)(struct dvb_ca_en50221* ca, int slot, u8 address); + int (*write_cam_control)(struct dvb_ca_en50221* ca, int slot, u8 address, u8 value); + + /* functions for readin/writing data */ + int (*read_data)(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount); + int (*write_data)(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount); + + /* Functions for controlling slots */ + int (*slot_reset)(struct dvb_ca_en50221* ca, int slot); + int (*slot_shutdown)(struct dvb_ca_en50221* ca, int slot); + int (*slot_ts_enable)(struct dvb_ca_en50221* ca, int slot); + + /* + * Poll slot status. + * Only necessary if DVB_CA_FLAG_EN50221_IRQ_CAMCHANGE is not set + */ + int (*poll_slot_status)(struct dvb_ca_en50221* ca, int slot, int open); + + /* private data, used by caller */ + void* data; + + /* Opaque data used by the dvb_ca core. Do not modify! */ + void* private; +}; + + + + +/* ******************************************************************************** */ +/* Functions for reporting IRQ events */ + +/** + * A CAMCHANGE IRQ has occurred. + * + * @param ca CA instance. + * @param slot Slot concerned. + * @param change_type One of the DVB_CA_CAMCHANGE_* values + */ +void dvb_ca_en50221_camchange_irq(struct dvb_ca_en50221* pubca, int slot, int change_type); + +/** + * A CAMREADY IRQ has occurred. + * + * @param ca CA instance. + * @param slot Slot concerned. + */ +void dvb_ca_en50221_camready_irq(struct dvb_ca_en50221* pubca, int slot); + +/** + * An FR or a DA IRQ has occurred. + * + * @param ca CA instance. + * @param slot Slot concerned. + */ +void dvb_ca_en50221_frda_irq(struct dvb_ca_en50221* ca, int slot); + + + +/* ******************************************************************************** */ +/* Initialisation/shutdown functions */ + +/** + * Initialise a new DVB CA device. + * + * @param dvb_adapter DVB adapter to attach the new CA device to. + * @param ca The dvb_ca instance. + * @param flags Flags describing the CA device (DVB_CA_EN50221_FLAG_*). + * @param slot_count Number of slots supported. + * + * @return 0 on success, nonzero on failure + */ +extern int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter, struct dvb_ca_en50221* ca, int flags, int slot_count); + +/** + * Release a DVB CA device. + * + * @param ca The associated dvb_ca instance. + */ +extern void dvb_ca_en50221_release(struct dvb_ca_en50221* ca); + + + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1320 @@ +/* + * dvb_demux.c - DVB kernel demux API + * + * Copyright (C) 2000-2001 Ralph Metzler + * & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_demux.h" + +#define NOBUFS +/* +** #define DVB_DEMUX_SECTION_LOSS_LOG to monitor payload loss in the syslog +*/ +// #define DVB_DEMUX_SECTION_LOSS_LOG + +static int dvb_demux_tscheck; +module_param(dvb_demux_tscheck, int, 0644); +MODULE_PARM_DESC(dvb_demux_tscheck, + "enable transport stream continuity and TEI check"); + +static int dvb_demux_speedcheck; +module_param(dvb_demux_speedcheck, int, 0644); +MODULE_PARM_DESC(dvb_demux_speedcheck, + "enable transport stream speed check"); + +static int dvb_demux_feed_err_pkts = 1; +module_param(dvb_demux_feed_err_pkts, int, 0644); +MODULE_PARM_DESC(dvb_demux_feed_err_pkts, + "when set to 0, drop packets with the TEI bit set (1 by default)"); + +#define dprintk_tscheck(x...) do { \ + if (dvb_demux_tscheck && printk_ratelimit()) \ + printk(x); \ + } while (0) + +/****************************************************************************** + * static inlined helper functions + ******************************************************************************/ + +static inline u16 section_length(const u8 *buf) +{ + return 3 + ((buf[1] & 0x0f) << 8) + buf[2]; +} + +static inline u16 ts_pid(const u8 *buf) +{ + return ((buf[1] & 0x1f) << 8) + buf[2]; +} + +static inline u8 payload(const u8 *tsp) +{ + if (!(tsp[3] & 0x10)) // no payload? + return 0; + + if (tsp[3] & 0x20) { // adaptation field? + if (tsp[4] > 183) // corrupted data? + return 0; + else + return 184 - 1 - tsp[4]; + } + + return 184; +} + +static u32 dvb_dmx_crc32(struct dvb_demux_feed *f, const u8 *src, size_t len) +{ + return (f->feed.sec.crc_val = crc32_be(f->feed.sec.crc_val, src, len)); +} + +static void dvb_dmx_memcopy(struct dvb_demux_feed *f, u8 *d, const u8 *s, + size_t len) +{ + memcpy(d, s, len); +} + +/****************************************************************************** + * Software filter functions + ******************************************************************************/ + +static inline int dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed, + const u8 *buf) +{ + int count = payload(buf); + int p; + //int ccok; + //u8 cc; + + if (count == 0) + return -1; + + p = 188 - count; + + /* + cc = buf[3] & 0x0f; + ccok = ((feed->cc + 1) & 0x0f) == cc; + feed->cc = cc; + if (!ccok) + printk("missed packet!\n"); + */ + + if (buf[1] & 0x40) // PUSI ? + feed->peslen = 0xfffa; + + feed->peslen += count; + + return feed->cb.ts(&buf[p], count, NULL, 0, &feed->feed.ts, DMX_OK); +} + +static int dvb_dmx_swfilter_sectionfilter(struct dvb_demux_feed *feed, + struct dvb_demux_filter *f) +{ + u8 neq = 0; + int i; + + for (i = 0; i < DVB_DEMUX_MASK_MAX; i++) { + u8 xor = f->filter.filter_value[i] ^ feed->feed.sec.secbuf[i]; + + if (f->maskandmode[i] & xor) + return 0; + + neq |= f->maskandnotmode[i] & xor; + } + + if (f->doneq && !neq) + return 0; + + return feed->cb.sec(feed->feed.sec.secbuf, feed->feed.sec.seclen, + NULL, 0, &f->filter, DMX_OK); +} + +static inline int dvb_dmx_swfilter_section_feed(struct dvb_demux_feed *feed) +{ + struct dvb_demux *demux = feed->demux; + struct dvb_demux_filter *f = feed->filter; + struct dmx_section_feed *sec = &feed->feed.sec; + int section_syntax_indicator; + + if (!sec->is_filtering) + return 0; + + if (!f) + return 0; + + if (sec->check_crc) { + section_syntax_indicator = ((sec->secbuf[1] & 0x80) != 0); + if (section_syntax_indicator && + demux->check_crc32(feed, sec->secbuf, sec->seclen)) + return -1; + } + + do { + if (dvb_dmx_swfilter_sectionfilter(feed, f) < 0) + return -1; + } while ((f = f->next) && sec->is_filtering); + + sec->seclen = 0; + + return 0; +} + +static void dvb_dmx_swfilter_section_new(struct dvb_demux_feed *feed) +{ + struct dmx_section_feed *sec = &feed->feed.sec; + +#ifdef DVB_DEMUX_SECTION_LOSS_LOG + if (sec->secbufp < sec->tsfeedp) { + int i, n = sec->tsfeedp - sec->secbufp; + + /* + * Section padding is done with 0xff bytes entirely. + * Due to speed reasons, we won't check all of them + * but just first and last. + */ + if (sec->secbuf[0] != 0xff || sec->secbuf[n - 1] != 0xff) { + printk("dvb_demux.c section ts padding loss: %d/%d\n", + n, sec->tsfeedp); + printk("dvb_demux.c pad data:"); + for (i = 0; i < n; i++) + printk(" %02x", sec->secbuf[i]); + printk("\n"); + } + } +#endif + + sec->tsfeedp = sec->secbufp = sec->seclen = 0; + sec->secbuf = sec->secbuf_base; +} + +/* + * Losless Section Demux 1.4.1 by Emard + * Valsecchi Patrick: + * - middle of section A (no PUSI) + * - end of section A and start of section B + * (with PUSI pointing to the start of the second section) + * + * In this case, without feed->pusi_seen you'll receive a garbage section + * consisting of the end of section A. Basically because tsfeedp + * is incemented and the use=0 condition is not raised + * when the second packet arrives. + * + * Fix: + * when demux is started, let feed->pusi_seen = 0 to + * prevent initial feeding of garbage from the end of + * previous section. When you for the first time see PUSI=1 + * then set feed->pusi_seen = 1 + */ +static int dvb_dmx_swfilter_section_copy_dump(struct dvb_demux_feed *feed, + const u8 *buf, u8 len) +{ + struct dvb_demux *demux = feed->demux; + struct dmx_section_feed *sec = &feed->feed.sec; + u16 limit, seclen, n; + + if (sec->tsfeedp >= DMX_MAX_SECFEED_SIZE) + return 0; + + if (sec->tsfeedp + len > DMX_MAX_SECFEED_SIZE) { +#ifdef DVB_DEMUX_SECTION_LOSS_LOG + printk("dvb_demux.c section buffer full loss: %d/%d\n", + sec->tsfeedp + len - DMX_MAX_SECFEED_SIZE, + DMX_MAX_SECFEED_SIZE); +#endif + len = DMX_MAX_SECFEED_SIZE - sec->tsfeedp; + } + + if (len <= 0) + return 0; + + demux->memcopy(feed, sec->secbuf_base + sec->tsfeedp, buf, len); + sec->tsfeedp += len; + + /* + * Dump all the sections we can find in the data (Emard) + */ + limit = sec->tsfeedp; + if (limit > DMX_MAX_SECFEED_SIZE) + return -1; /* internal error should never happen */ + + /* to be sure always set secbuf */ + sec->secbuf = sec->secbuf_base + sec->secbufp; + + for (n = 0; sec->secbufp + 2 < limit; n++) { + seclen = section_length(sec->secbuf); + if (seclen <= 0 || seclen > DMX_MAX_SECTION_SIZE + || seclen + sec->secbufp > limit) + return 0; + sec->seclen = seclen; + sec->crc_val = ~0; + /* dump [secbuf .. secbuf+seclen) */ + if (feed->pusi_seen) + dvb_dmx_swfilter_section_feed(feed); +#ifdef DVB_DEMUX_SECTION_LOSS_LOG + else + printk("dvb_demux.c pusi not seen, discarding section data\n"); +#endif + sec->secbufp += seclen; /* secbufp and secbuf moving together is */ + sec->secbuf += seclen; /* redundant but saves pointer arithmetic */ + } + + return 0; +} + +static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed, + const u8 *buf) +{ + u8 p, count; + int ccok, dc_i = 0; + u8 cc; + + count = payload(buf); + + if (count == 0) /* count == 0 if no payload or out of range */ + return -1; + + p = 188 - count; /* payload start */ + + cc = buf[3] & 0x0f; + ccok = ((feed->cc + 1) & 0x0f) == cc; + feed->cc = cc; + + if (buf[3] & 0x20) { + /* adaption field present, check for discontinuity_indicator */ + if ((buf[4] > 0) && (buf[5] & 0x80)) + dc_i = 1; + } + + if (!ccok || dc_i) { +#ifdef DVB_DEMUX_SECTION_LOSS_LOG + printk("dvb_demux.c discontinuity detected %d bytes lost\n", + count); + /* + * those bytes under sume circumstances will again be reported + * in the following dvb_dmx_swfilter_section_new + */ +#endif + /* + * Discontinuity detected. Reset pusi_seen = 0 to + * stop feeding of suspicious data until next PUSI=1 arrives + */ + feed->pusi_seen = 0; + dvb_dmx_swfilter_section_new(feed); + } + + if (buf[1] & 0x40) { + /* PUSI=1 (is set), section boundary is here */ + if (count > 1 && buf[p] < count) { + const u8 *before = &buf[p + 1]; + u8 before_len = buf[p]; + const u8 *after = &before[before_len]; + u8 after_len = count - 1 - before_len; + + dvb_dmx_swfilter_section_copy_dump(feed, before, + before_len); + /* before start of new section, set pusi_seen = 1 */ + feed->pusi_seen = 1; + dvb_dmx_swfilter_section_new(feed); + dvb_dmx_swfilter_section_copy_dump(feed, after, + after_len); + } +#ifdef DVB_DEMUX_SECTION_LOSS_LOG + else if (count > 0) + printk("dvb_demux.c PUSI=1 but %d bytes lost\n", count); +#endif + } else { + /* PUSI=0 (is not set), no section boundary */ + dvb_dmx_swfilter_section_copy_dump(feed, &buf[p], count); + } + + return 0; +} + +static inline void dvb_dmx_swfilter_packet_type(struct dvb_demux_feed *feed, + const u8 *buf) +{ + switch (feed->type) { + case DMX_TYPE_TS: + if (!feed->feed.ts.is_filtering) + break; + if (feed->ts_type & TS_PACKET) { + if (feed->ts_type & TS_PAYLOAD_ONLY) + dvb_dmx_swfilter_payload(feed, buf); + else + feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts, + DMX_OK); + } + if (feed->ts_type & TS_DECODER) + if (feed->demux->write_to_decoder) + feed->demux->write_to_decoder(feed, buf, 188); + break; + + case DMX_TYPE_SEC: + if (!feed->feed.sec.is_filtering) + break; + if (dvb_dmx_swfilter_section_packet(feed, buf) < 0) + feed->feed.sec.seclen = feed->feed.sec.secbufp = 0; + break; + + default: + break; + } +} + +#define DVR_FEED(f) \ + (((f)->type == DMX_TYPE_TS) && \ + ((f)->feed.ts.is_filtering) && \ + (((f)->ts_type & (TS_PACKET | TS_DEMUX)) == TS_PACKET)) + +static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf) +{ + struct dvb_demux_feed *feed; + u16 pid = ts_pid(buf); + int dvr_done = 0; + + if (dvb_demux_speedcheck) { + struct timespec cur_time, delta_time; + u64 speed_bytes, speed_timedelta; + + demux->speed_pkts_cnt++; + + /* show speed every SPEED_PKTS_INTERVAL packets */ + if (!(demux->speed_pkts_cnt % SPEED_PKTS_INTERVAL)) { + cur_time = current_kernel_time(); + + if (demux->speed_last_time.tv_sec != 0 && + demux->speed_last_time.tv_nsec != 0) { + delta_time = timespec_sub(cur_time, + demux->speed_last_time); + speed_bytes = (u64)demux->speed_pkts_cnt + * 188 * 8; + /* convert to 1024 basis */ + speed_bytes = 1000 * div64_u64(speed_bytes, + 1024); + speed_timedelta = + (u64)timespec_to_ns(&delta_time); + speed_timedelta = div64_u64(speed_timedelta, + 1000000); /* nsec -> usec */ + printk(KERN_INFO "TS speed %llu Kbits/sec \n", + div64_u64(speed_bytes, + speed_timedelta)); + } + + demux->speed_last_time = cur_time; + demux->speed_pkts_cnt = 0; + } + } + + if (buf[1] & 0x80) { + dprintk_tscheck("TEI detected. " + "PID=0x%x data1=0x%x\n", + pid, buf[1]); + /* data in this packet cant be trusted - drop it unless + * module option dvb_demux_feed_err_pkts is set */ + if (!dvb_demux_feed_err_pkts) + return; + } else /* if TEI bit is set, pid may be wrong- skip pkt counter */ + if (demux->cnt_storage && dvb_demux_tscheck) { + /* check pkt counter */ + if (pid < MAX_PID) { + if (buf[3] & 0x10) + demux->cnt_storage[pid] = + (demux->cnt_storage[pid] + 1) & 0xf; + + if ((buf[3] & 0xf) != demux->cnt_storage[pid]) { + dprintk_tscheck("TS packet counter mismatch. PID=0x%x expected 0x%x got 0x%x\n", + pid, demux->cnt_storage[pid], + buf[3] & 0xf); + demux->cnt_storage[pid] = buf[3] & 0xf; + } + } + /* end check */ + } + + list_for_each_entry(feed, &demux->feed_list, list_head) { + if ((feed->pid != pid) && (feed->pid != 0x2000)) + continue; + + /* copy each packet only once to the dvr device, even + * if a PID is in multiple filters (e.g. video + PCR) */ + if ((DVR_FEED(feed)) && (dvr_done++)) + continue; + + if (feed->pid == pid) + dvb_dmx_swfilter_packet_type(feed, buf); + else if (feed->pid == 0x2000) + feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts, DMX_OK); + } +} + +void dvb_dmx_swfilter_packets(struct dvb_demux *demux, const u8 *buf, + size_t count) +{ + spin_lock(&demux->lock); + + while (count--) { + if (buf[0] == 0x47) + dvb_dmx_swfilter_packet(demux, buf); + buf += 188; + } + + spin_unlock(&demux->lock); +} + +EXPORT_SYMBOL(dvb_dmx_swfilter_packets); + +static inline int find_next_packet(const u8 *buf, int pos, size_t count, + const int pktsize) +{ + int start = pos, lost; + + while (pos < count) { + if (buf[pos] == 0x47 || + (pktsize == 204 && buf[pos] == 0xB8)) + break; + pos++; + } + + lost = pos - start; + if (lost) { + /* This garbage is part of a valid packet? */ + int backtrack = pos - pktsize; + if (backtrack >= 0 && (buf[backtrack] == 0x47 || + (pktsize == 204 && buf[backtrack] == 0xB8))) + return backtrack; + } + + return pos; +} + +/* Filter all pktsize= 188 or 204 sized packets and skip garbage. */ +static inline void _dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, + size_t count, const int pktsize) +{ + int p = 0, i, j; + const u8 *q; + + spin_lock(&demux->lock); + + if (demux->tsbufp) { /* tsbuf[0] is now 0x47. */ + i = demux->tsbufp; + j = pktsize - i; + if (count < j) { + memcpy(&demux->tsbuf[i], buf, count); + demux->tsbufp += count; + goto bailout; + } + memcpy(&demux->tsbuf[i], buf, j); + if (demux->tsbuf[0] == 0x47) /* double check */ + dvb_dmx_swfilter_packet(demux, demux->tsbuf); + demux->tsbufp = 0; + p += j; + } + + while (1) { + p = find_next_packet(buf, p, count, pktsize); + if (p >= count) + break; + if (count - p < pktsize) + break; + + q = &buf[p]; + + if (pktsize == 204 && (*q == 0xB8)) { + memcpy(demux->tsbuf, q, 188); + demux->tsbuf[0] = 0x47; + q = demux->tsbuf; + } + dvb_dmx_swfilter_packet(demux, q); + p += pktsize; + } + + i = count - p; + if (i) { + memcpy(demux->tsbuf, &buf[p], i); + demux->tsbufp = i; + if (pktsize == 204 && demux->tsbuf[0] == 0xB8) + demux->tsbuf[0] = 0x47; + } + +bailout: + spin_unlock(&demux->lock); +} + +void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count) +{ + _dvb_dmx_swfilter(demux, buf, count, 188); +} +EXPORT_SYMBOL(dvb_dmx_swfilter); + +void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, size_t count) +{ + _dvb_dmx_swfilter(demux, buf, count, 204); +} +EXPORT_SYMBOL(dvb_dmx_swfilter_204); + +void dvb_dmx_swfilter_raw(struct dvb_demux *demux, const u8 *buf, size_t count) +{ + spin_lock(&demux->lock); + + demux->feed->cb.ts(buf, count, NULL, 0, &demux->feed->feed.ts, DMX_OK); + + spin_unlock(&demux->lock); +} +EXPORT_SYMBOL(dvb_dmx_swfilter_raw); + +static struct dvb_demux_filter *dvb_dmx_filter_alloc(struct dvb_demux *demux) +{ + int i; + + for (i = 0; i < demux->filternum; i++) + if (demux->filter[i].state == DMX_STATE_FREE) + break; + + if (i == demux->filternum) + return NULL; + + demux->filter[i].state = DMX_STATE_ALLOCATED; + + return &demux->filter[i]; +} + +static struct dvb_demux_feed *dvb_dmx_feed_alloc(struct dvb_demux *demux) +{ + int i; + + for (i = 0; i < demux->feednum; i++) + if (demux->feed[i].state == DMX_STATE_FREE) + break; + + if (i == demux->feednum) + return NULL; + + demux->feed[i].state = DMX_STATE_ALLOCATED; + + return &demux->feed[i]; +} + +static int dvb_demux_feed_find(struct dvb_demux_feed *feed) +{ + struct dvb_demux_feed *entry; + + list_for_each_entry(entry, &feed->demux->feed_list, list_head) + if (entry == feed) + return 1; + + return 0; +} + +static void dvb_demux_feed_add(struct dvb_demux_feed *feed) +{ + spin_lock_irq(&feed->demux->lock); + if (dvb_demux_feed_find(feed)) { + printk(KERN_ERR "%s: feed already in list (type=%x state=%x pid=%x)\n", + __func__, feed->type, feed->state, feed->pid); + goto out; + } + + list_add(&feed->list_head, &feed->demux->feed_list); +out: + spin_unlock_irq(&feed->demux->lock); +} + +static void dvb_demux_feed_del(struct dvb_demux_feed *feed) +{ + spin_lock_irq(&feed->demux->lock); + if (!(dvb_demux_feed_find(feed))) { + printk(KERN_ERR "%s: feed not in list (type=%x state=%x pid=%x)\n", + __func__, feed->type, feed->state, feed->pid); + goto out; + } + + list_del(&feed->list_head); +out: + spin_unlock_irq(&feed->demux->lock); +} + +static int dmx_ts_feed_set(struct dmx_ts_feed *ts_feed, u16 pid, int ts_type, + enum dmx_ts_pes pes_type, + size_t circular_buffer_size, struct timespec timeout) +{ + struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; + struct dvb_demux *demux = feed->demux; + + if (pid > DMX_MAX_PID) + return -EINVAL; + + if (mutex_lock_interruptible(&demux->mutex)) + return -ERESTARTSYS; + + if (ts_type & TS_DECODER) { + if (pes_type >= DMX_PES_OTHER) { + mutex_unlock(&demux->mutex); + return -EINVAL; + } + + if (demux->pesfilter[pes_type] && + demux->pesfilter[pes_type] != feed) { + mutex_unlock(&demux->mutex); + return -EINVAL; + } + + demux->pesfilter[pes_type] = feed; + demux->pids[pes_type] = pid; + } + + dvb_demux_feed_add(feed); + + feed->pid = pid; + feed->buffer_size = circular_buffer_size; + feed->timeout = timeout; + feed->ts_type = ts_type; + feed->pes_type = pes_type; + + if (feed->buffer_size) { +#ifdef NOBUFS + feed->buffer = NULL; +#else + feed->buffer = vmalloc(feed->buffer_size); + if (!feed->buffer) { + mutex_unlock(&demux->mutex); + return -ENOMEM; + } +#endif + } + + feed->state = DMX_STATE_READY; + mutex_unlock(&demux->mutex); + + return 0; +} + +static int dmx_ts_feed_start_filtering(struct dmx_ts_feed *ts_feed) +{ + struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; + struct dvb_demux *demux = feed->demux; + int ret; + + if (mutex_lock_interruptible(&demux->mutex)) + return -ERESTARTSYS; + + if (feed->state != DMX_STATE_READY || feed->type != DMX_TYPE_TS) { + mutex_unlock(&demux->mutex); + return -EINVAL; + } + + if (!demux->start_feed) { + mutex_unlock(&demux->mutex); + return -ENODEV; + } + + if ((ret = demux->start_feed(feed)) < 0) { + mutex_unlock(&demux->mutex); + return ret; + } + + spin_lock_irq(&demux->lock); + ts_feed->is_filtering = 1; + feed->state = DMX_STATE_GO; + spin_unlock_irq(&demux->lock); + mutex_unlock(&demux->mutex); + + return 0; +} + +static int dmx_ts_feed_stop_filtering(struct dmx_ts_feed *ts_feed) +{ + struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; + struct dvb_demux *demux = feed->demux; + int ret; + + mutex_lock(&demux->mutex); + + if (feed->state < DMX_STATE_GO) { + mutex_unlock(&demux->mutex); + return -EINVAL; + } + + if (!demux->stop_feed) { + mutex_unlock(&demux->mutex); + return -ENODEV; + } + + ret = demux->stop_feed(feed); + + spin_lock_irq(&demux->lock); + ts_feed->is_filtering = 0; + feed->state = DMX_STATE_ALLOCATED; + spin_unlock_irq(&demux->lock); + mutex_unlock(&demux->mutex); + + return ret; +} + +static int dvbdmx_allocate_ts_feed(struct dmx_demux *dmx, + struct dmx_ts_feed **ts_feed, + dmx_ts_cb callback) +{ + struct dvb_demux *demux = (struct dvb_demux *)dmx; + struct dvb_demux_feed *feed; + + if (mutex_lock_interruptible(&demux->mutex)) + return -ERESTARTSYS; + + if (!(feed = dvb_dmx_feed_alloc(demux))) { + mutex_unlock(&demux->mutex); + return -EBUSY; + } + + feed->type = DMX_TYPE_TS; + feed->cb.ts = callback; + feed->demux = demux; + feed->pid = 0xffff; + feed->peslen = 0xfffa; + feed->buffer = NULL; + + (*ts_feed) = &feed->feed.ts; + (*ts_feed)->parent = dmx; + (*ts_feed)->priv = NULL; + (*ts_feed)->is_filtering = 0; + (*ts_feed)->start_filtering = dmx_ts_feed_start_filtering; + (*ts_feed)->stop_filtering = dmx_ts_feed_stop_filtering; + (*ts_feed)->set = dmx_ts_feed_set; + + if (!(feed->filter = dvb_dmx_filter_alloc(demux))) { + feed->state = DMX_STATE_FREE; + mutex_unlock(&demux->mutex); + return -EBUSY; + } + + feed->filter->type = DMX_TYPE_TS; + feed->filter->feed = feed; + feed->filter->state = DMX_STATE_READY; + + mutex_unlock(&demux->mutex); + + return 0; +} + +static int dvbdmx_release_ts_feed(struct dmx_demux *dmx, + struct dmx_ts_feed *ts_feed) +{ + struct dvb_demux *demux = (struct dvb_demux *)dmx; + struct dvb_demux_feed *feed = (struct dvb_demux_feed *)ts_feed; + + mutex_lock(&demux->mutex); + + if (feed->state == DMX_STATE_FREE) { + mutex_unlock(&demux->mutex); + return -EINVAL; + } +#ifndef NOBUFS + vfree(feed->buffer); + feed->buffer = NULL; +#endif + + feed->state = DMX_STATE_FREE; + feed->filter->state = DMX_STATE_FREE; + + dvb_demux_feed_del(feed); + + feed->pid = 0xffff; + + if (feed->ts_type & TS_DECODER && feed->pes_type < DMX_PES_OTHER) + demux->pesfilter[feed->pes_type] = NULL; + + mutex_unlock(&demux->mutex); + return 0; +} + +/****************************************************************************** + * dmx_section_feed API calls + ******************************************************************************/ + +static int dmx_section_feed_allocate_filter(struct dmx_section_feed *feed, + struct dmx_section_filter **filter) +{ + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; + struct dvb_demux *dvbdemux = dvbdmxfeed->demux; + struct dvb_demux_filter *dvbdmxfilter; + + if (mutex_lock_interruptible(&dvbdemux->mutex)) + return -ERESTARTSYS; + + dvbdmxfilter = dvb_dmx_filter_alloc(dvbdemux); + if (!dvbdmxfilter) { + mutex_unlock(&dvbdemux->mutex); + return -EBUSY; + } + + spin_lock_irq(&dvbdemux->lock); + *filter = &dvbdmxfilter->filter; + (*filter)->parent = feed; + (*filter)->priv = NULL; + dvbdmxfilter->feed = dvbdmxfeed; + dvbdmxfilter->type = DMX_TYPE_SEC; + dvbdmxfilter->state = DMX_STATE_READY; + dvbdmxfilter->next = dvbdmxfeed->filter; + dvbdmxfeed->filter = dvbdmxfilter; + spin_unlock_irq(&dvbdemux->lock); + + mutex_unlock(&dvbdemux->mutex); + return 0; +} + +static int dmx_section_feed_set(struct dmx_section_feed *feed, + u16 pid, size_t circular_buffer_size, + int check_crc) +{ + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + + if (pid > 0x1fff) + return -EINVAL; + + if (mutex_lock_interruptible(&dvbdmx->mutex)) + return -ERESTARTSYS; + + dvb_demux_feed_add(dvbdmxfeed); + + dvbdmxfeed->pid = pid; + dvbdmxfeed->buffer_size = circular_buffer_size; + dvbdmxfeed->feed.sec.check_crc = check_crc; + +#ifdef NOBUFS + dvbdmxfeed->buffer = NULL; +#else + dvbdmxfeed->buffer = vmalloc(dvbdmxfeed->buffer_size); + if (!dvbdmxfeed->buffer) { + mutex_unlock(&dvbdmx->mutex); + return -ENOMEM; + } +#endif + + dvbdmxfeed->state = DMX_STATE_READY; + mutex_unlock(&dvbdmx->mutex); + return 0; +} + +static void prepare_secfilters(struct dvb_demux_feed *dvbdmxfeed) +{ + int i; + struct dvb_demux_filter *f; + struct dmx_section_filter *sf; + u8 mask, mode, doneq; + + if (!(f = dvbdmxfeed->filter)) + return; + do { + sf = &f->filter; + doneq = 0; + for (i = 0; i < DVB_DEMUX_MASK_MAX; i++) { + mode = sf->filter_mode[i]; + mask = sf->filter_mask[i]; + f->maskandmode[i] = mask & mode; + doneq |= f->maskandnotmode[i] = mask & ~mode; + } + f->doneq = doneq ? 1 : 0; + } while ((f = f->next)); +} + +static int dmx_section_feed_start_filtering(struct dmx_section_feed *feed) +{ + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + int ret; + + if (mutex_lock_interruptible(&dvbdmx->mutex)) + return -ERESTARTSYS; + + if (feed->is_filtering) { + mutex_unlock(&dvbdmx->mutex); + return -EBUSY; + } + + if (!dvbdmxfeed->filter) { + mutex_unlock(&dvbdmx->mutex); + return -EINVAL; + } + + dvbdmxfeed->feed.sec.tsfeedp = 0; + dvbdmxfeed->feed.sec.secbuf = dvbdmxfeed->feed.sec.secbuf_base; + dvbdmxfeed->feed.sec.secbufp = 0; + dvbdmxfeed->feed.sec.seclen = 0; + + if (!dvbdmx->start_feed) { + mutex_unlock(&dvbdmx->mutex); + return -ENODEV; + } + + prepare_secfilters(dvbdmxfeed); + + if ((ret = dvbdmx->start_feed(dvbdmxfeed)) < 0) { + mutex_unlock(&dvbdmx->mutex); + return ret; + } + + spin_lock_irq(&dvbdmx->lock); + feed->is_filtering = 1; + dvbdmxfeed->state = DMX_STATE_GO; + spin_unlock_irq(&dvbdmx->lock); + + mutex_unlock(&dvbdmx->mutex); + return 0; +} + +static int dmx_section_feed_stop_filtering(struct dmx_section_feed *feed) +{ + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + int ret; + + mutex_lock(&dvbdmx->mutex); + + if (!dvbdmx->stop_feed) { + mutex_unlock(&dvbdmx->mutex); + return -ENODEV; + } + + ret = dvbdmx->stop_feed(dvbdmxfeed); + + spin_lock_irq(&dvbdmx->lock); + dvbdmxfeed->state = DMX_STATE_READY; + feed->is_filtering = 0; + spin_unlock_irq(&dvbdmx->lock); + + mutex_unlock(&dvbdmx->mutex); + return ret; +} + +static int dmx_section_feed_release_filter(struct dmx_section_feed *feed, + struct dmx_section_filter *filter) +{ + struct dvb_demux_filter *dvbdmxfilter = (struct dvb_demux_filter *)filter, *f; + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + + mutex_lock(&dvbdmx->mutex); + + if (dvbdmxfilter->feed != dvbdmxfeed) { + mutex_unlock(&dvbdmx->mutex); + return -EINVAL; + } + + if (feed->is_filtering) + feed->stop_filtering(feed); + + spin_lock_irq(&dvbdmx->lock); + f = dvbdmxfeed->filter; + + if (f == dvbdmxfilter) { + dvbdmxfeed->filter = dvbdmxfilter->next; + } else { + while (f->next != dvbdmxfilter) + f = f->next; + f->next = f->next->next; + } + + dvbdmxfilter->state = DMX_STATE_FREE; + spin_unlock_irq(&dvbdmx->lock); + mutex_unlock(&dvbdmx->mutex); + return 0; +} + +static int dvbdmx_allocate_section_feed(struct dmx_demux *demux, + struct dmx_section_feed **feed, + dmx_section_cb callback) +{ + struct dvb_demux *dvbdmx = (struct dvb_demux *)demux; + struct dvb_demux_feed *dvbdmxfeed; + + if (mutex_lock_interruptible(&dvbdmx->mutex)) + return -ERESTARTSYS; + + if (!(dvbdmxfeed = dvb_dmx_feed_alloc(dvbdmx))) { + mutex_unlock(&dvbdmx->mutex); + return -EBUSY; + } + + dvbdmxfeed->type = DMX_TYPE_SEC; + dvbdmxfeed->cb.sec = callback; + dvbdmxfeed->demux = dvbdmx; + dvbdmxfeed->pid = 0xffff; + dvbdmxfeed->feed.sec.secbuf = dvbdmxfeed->feed.sec.secbuf_base; + dvbdmxfeed->feed.sec.secbufp = dvbdmxfeed->feed.sec.seclen = 0; + dvbdmxfeed->feed.sec.tsfeedp = 0; + dvbdmxfeed->filter = NULL; + dvbdmxfeed->buffer = NULL; + + (*feed) = &dvbdmxfeed->feed.sec; + (*feed)->is_filtering = 0; + (*feed)->parent = demux; + (*feed)->priv = NULL; + + (*feed)->set = dmx_section_feed_set; + (*feed)->allocate_filter = dmx_section_feed_allocate_filter; + (*feed)->start_filtering = dmx_section_feed_start_filtering; + (*feed)->stop_filtering = dmx_section_feed_stop_filtering; + (*feed)->release_filter = dmx_section_feed_release_filter; + + mutex_unlock(&dvbdmx->mutex); + return 0; +} + +static int dvbdmx_release_section_feed(struct dmx_demux *demux, + struct dmx_section_feed *feed) +{ + struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *)feed; + struct dvb_demux *dvbdmx = (struct dvb_demux *)demux; + + mutex_lock(&dvbdmx->mutex); + + if (dvbdmxfeed->state == DMX_STATE_FREE) { + mutex_unlock(&dvbdmx->mutex); + return -EINVAL; + } +#ifndef NOBUFS + vfree(dvbdmxfeed->buffer); + dvbdmxfeed->buffer = NULL; +#endif + dvbdmxfeed->state = DMX_STATE_FREE; + + dvb_demux_feed_del(dvbdmxfeed); + + dvbdmxfeed->pid = 0xffff; + + mutex_unlock(&dvbdmx->mutex); + return 0; +} + +/****************************************************************************** + * dvb_demux kernel data API calls + ******************************************************************************/ + +static int dvbdmx_open(struct dmx_demux *demux) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + + if (dvbdemux->users >= MAX_DVB_DEMUX_USERS) + return -EUSERS; + + dvbdemux->users++; + return 0; +} + +static int dvbdmx_close(struct dmx_demux *demux) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + + if (dvbdemux->users == 0) + return -ENODEV; + + dvbdemux->users--; + //FIXME: release any unneeded resources if users==0 + return 0; +} + +static int dvbdmx_write(struct dmx_demux *demux, const char __user *buf, size_t count) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + void *p; + + if ((!demux->frontend) || (demux->frontend->source != DMX_MEMORY_FE)) + return -EINVAL; + + p = memdup_user(buf, count); + if (IS_ERR(p)) + return PTR_ERR(p); + if (mutex_lock_interruptible(&dvbdemux->mutex)) { + kfree(p); + return -ERESTARTSYS; + } + dvb_dmx_swfilter(dvbdemux, p, count); + kfree(p); + mutex_unlock(&dvbdemux->mutex); + + if (signal_pending(current)) + return -EINTR; + return count; +} + +static int dvbdmx_add_frontend(struct dmx_demux *demux, + struct dmx_frontend *frontend) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + struct list_head *head = &dvbdemux->frontend_list; + + list_add(&(frontend->connectivity_list), head); + + return 0; +} + +static int dvbdmx_remove_frontend(struct dmx_demux *demux, + struct dmx_frontend *frontend) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + struct list_head *pos, *n, *head = &dvbdemux->frontend_list; + + list_for_each_safe(pos, n, head) { + if (DMX_FE_ENTRY(pos) == frontend) { + list_del(pos); + return 0; + } + } + + return -ENODEV; +} + +static struct list_head *dvbdmx_get_frontends(struct dmx_demux *demux) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + + if (list_empty(&dvbdemux->frontend_list)) + return NULL; + + return &dvbdemux->frontend_list; +} + +static int dvbdmx_connect_frontend(struct dmx_demux *demux, + struct dmx_frontend *frontend) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + + if (demux->frontend) + return -EINVAL; + + mutex_lock(&dvbdemux->mutex); + + demux->frontend = frontend; + mutex_unlock(&dvbdemux->mutex); + return 0; +} + +static int dvbdmx_disconnect_frontend(struct dmx_demux *demux) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + + mutex_lock(&dvbdemux->mutex); + + demux->frontend = NULL; + mutex_unlock(&dvbdemux->mutex); + return 0; +} + +static int dvbdmx_get_pes_pids(struct dmx_demux *demux, u16 * pids) +{ + struct dvb_demux *dvbdemux = (struct dvb_demux *)demux; + + memcpy(pids, dvbdemux->pids, 5 * sizeof(u16)); + return 0; +} + +int dvb_dmx_init(struct dvb_demux *dvbdemux) +{ + int i; + struct dmx_demux *dmx = &dvbdemux->dmx; + + dvbdemux->cnt_storage = NULL; + dvbdemux->users = 0; + dvbdemux->filter = vmalloc(dvbdemux->filternum * sizeof(struct dvb_demux_filter)); + + if (!dvbdemux->filter) + return -ENOMEM; + + dvbdemux->feed = vmalloc(dvbdemux->feednum * sizeof(struct dvb_demux_feed)); + if (!dvbdemux->feed) { + vfree(dvbdemux->filter); + dvbdemux->filter = NULL; + return -ENOMEM; + } + for (i = 0; i < dvbdemux->filternum; i++) { + dvbdemux->filter[i].state = DMX_STATE_FREE; + dvbdemux->filter[i].index = i; + } + for (i = 0; i < dvbdemux->feednum; i++) { + dvbdemux->feed[i].state = DMX_STATE_FREE; + dvbdemux->feed[i].index = i; + } + + dvbdemux->cnt_storage = vmalloc(MAX_PID + 1); + if (!dvbdemux->cnt_storage) + printk(KERN_WARNING "Couldn't allocate memory for TS/TEI check. Disabling it\n"); + + INIT_LIST_HEAD(&dvbdemux->frontend_list); + + for (i = 0; i < DMX_PES_OTHER; i++) { + dvbdemux->pesfilter[i] = NULL; + dvbdemux->pids[i] = 0xffff; + } + + INIT_LIST_HEAD(&dvbdemux->feed_list); + + dvbdemux->playing = 0; + dvbdemux->recording = 0; + dvbdemux->tsbufp = 0; + + if (!dvbdemux->check_crc32) + dvbdemux->check_crc32 = dvb_dmx_crc32; + + if (!dvbdemux->memcopy) + dvbdemux->memcopy = dvb_dmx_memcopy; + + dmx->frontend = NULL; + dmx->priv = dvbdemux; + dmx->open = dvbdmx_open; + dmx->close = dvbdmx_close; + dmx->write = dvbdmx_write; + dmx->allocate_ts_feed = dvbdmx_allocate_ts_feed; + dmx->release_ts_feed = dvbdmx_release_ts_feed; + dmx->allocate_section_feed = dvbdmx_allocate_section_feed; + dmx->release_section_feed = dvbdmx_release_section_feed; + + dmx->add_frontend = dvbdmx_add_frontend; + dmx->remove_frontend = dvbdmx_remove_frontend; + dmx->get_frontends = dvbdmx_get_frontends; + dmx->connect_frontend = dvbdmx_connect_frontend; + dmx->disconnect_frontend = dvbdmx_disconnect_frontend; + dmx->get_pes_pids = dvbdmx_get_pes_pids; + + mutex_init(&dvbdemux->mutex); + spin_lock_init(&dvbdemux->lock); + + return 0; +} + +EXPORT_SYMBOL(dvb_dmx_init); + +void dvb_dmx_release(struct dvb_demux *dvbdemux) +{ + vfree(dvbdemux->cnt_storage); + vfree(dvbdemux->filter); + vfree(dvbdemux->feed); +} + +EXPORT_SYMBOL(dvb_dmx_release); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_demux.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,151 @@ +/* + * dvb_demux.h: DVB kernel demux API + * + * Copyright (C) 2000-2001 Marcus Metzler & Ralph Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVB_DEMUX_H_ +#define _DVB_DEMUX_H_ + +#include +#include +#include +#include + +#include "demux.h" + +#define DMX_TYPE_TS 0 +#define DMX_TYPE_SEC 1 +#define DMX_TYPE_PES 2 + +#define DMX_STATE_FREE 0 +#define DMX_STATE_ALLOCATED 1 +#define DMX_STATE_SET 2 +#define DMX_STATE_READY 3 +#define DMX_STATE_GO 4 + +#define DVB_DEMUX_MASK_MAX 18 + +#define MAX_PID 0x1fff + +#define SPEED_PKTS_INTERVAL 50000 + +struct dvb_demux_filter { + struct dmx_section_filter filter; + u8 maskandmode[DMX_MAX_FILTER_SIZE]; + u8 maskandnotmode[DMX_MAX_FILTER_SIZE]; + int doneq; + + struct dvb_demux_filter *next; + struct dvb_demux_feed *feed; + int index; + int state; + int type; + + u16 hw_handle; + struct timer_list timer; +}; + +#define DMX_FEED_ENTRY(pos) list_entry(pos, struct dvb_demux_feed, list_head) + +struct dvb_demux_feed { + union { + struct dmx_ts_feed ts; + struct dmx_section_feed sec; + } feed; + + union { + dmx_ts_cb ts; + dmx_section_cb sec; + } cb; + + struct dvb_demux *demux; + void *priv; + int type; + int state; + u16 pid; + u8 *buffer; + int buffer_size; + + struct timespec timeout; + struct dvb_demux_filter *filter; + + int ts_type; + enum dmx_ts_pes pes_type; + + int cc; + int pusi_seen; /* prevents feeding of garbage from previous section */ + + u16 peslen; + + struct list_head list_head; + unsigned int index; /* a unique index for each feed (can be used as hardware pid filter index) */ +}; + +struct dvb_demux { + struct dmx_demux dmx; + void *priv; + int filternum; + int feednum; + int (*start_feed)(struct dvb_demux_feed *feed); + int (*stop_feed)(struct dvb_demux_feed *feed); + int (*write_to_decoder)(struct dvb_demux_feed *feed, + const u8 *buf, size_t len); + u32 (*check_crc32)(struct dvb_demux_feed *feed, + const u8 *buf, size_t len); + void (*memcopy)(struct dvb_demux_feed *feed, u8 *dst, + const u8 *src, size_t len); + + int users; +#define MAX_DVB_DEMUX_USERS 10 + struct dvb_demux_filter *filter; + struct dvb_demux_feed *feed; + + struct list_head frontend_list; + + struct dvb_demux_feed *pesfilter[DMX_PES_OTHER]; + u16 pids[DMX_PES_OTHER]; + int playing; + int recording; + +#define DMX_MAX_PID 0x2000 + struct list_head feed_list; + u8 tsbuf[204]; + int tsbufp; + + struct mutex mutex; + spinlock_t lock; + + uint8_t *cnt_storage; /* for TS continuity check */ + + struct timespec speed_last_time; /* for TS speed check */ + uint32_t speed_pkts_cnt; /* for TS speed check */ +}; + +int dvb_dmx_init(struct dvb_demux *dvbdemux); +void dvb_dmx_release(struct dvb_demux *dvbdemux); +void dvb_dmx_swfilter_packets(struct dvb_demux *dvbdmx, const u8 *buf, + size_t count); +void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count); +void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, + size_t count); +void dvb_dmx_swfilter_raw(struct dvb_demux *demux, const u8 *buf, + size_t count); + +#endif /* _DVB_DEMUX_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,603 @@ +#include +#include +#include +#include "dvb_filter.h" + +#if 0 +static unsigned int bitrates[3][16] = +{{0,32,64,96,128,160,192,224,256,288,320,352,384,416,448,0}, + {0,32,48,56,64,80,96,112,128,160,192,224,256,320,384,0}, + {0,32,40,48,56,64,80,96,112,128,160,192,224,256,320,0}}; +#endif + +static u32 freq[4] = {480, 441, 320, 0}; + +static unsigned int ac3_bitrates[32] = + {32,40,48,56,64,80,96,112,128,160,192,224,256,320,384,448,512,576,640, + 0,0,0,0,0,0,0,0,0,0,0,0,0}; + +static u32 ac3_frames[3][32] = + {{64,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024, + 1152,1280,0,0,0,0,0,0,0,0,0,0,0,0,0}, + {69,87,104,121,139,174,208,243,278,348,417,487,557,696,835,975,1114, + 1253,1393,0,0,0,0,0,0,0,0,0,0,0,0,0}, + {96,120,144,168,192,240,288,336,384,480,576,672,768,960,1152,1344, + 1536,1728,1920,0,0,0,0,0,0,0,0,0,0,0,0,0}}; + + + +#if 0 +static void setup_ts2pes(ipack *pa, ipack *pv, u16 *pida, u16 *pidv, + void (*pes_write)(u8 *buf, int count, void *data), + void *priv) +{ + dvb_filter_ipack_init(pa, IPACKS, pes_write); + dvb_filter_ipack_init(pv, IPACKS, pes_write); + pa->pid = pida; + pv->pid = pidv; + pa->data = priv; + pv->data = priv; +} +#endif + +#if 0 +static void ts_to_pes(ipack *p, u8 *buf) // don't need count (=188) +{ + u8 off = 0; + + if (!buf || !p ){ + printk("NULL POINTER IDIOT\n"); + return; + } + if (buf[1]&PAY_START) { + if (p->plength == MMAX_PLENGTH-6 && p->found>6){ + p->plength = p->found-6; + p->found = 0; + send_ipack(p); + dvb_filter_ipack_reset(p); + } + } + if (buf[3] & ADAPT_FIELD) { // adaptation field? + off = buf[4] + 1; + if (off+4 > 187) return; + } + dvb_filter_instant_repack(buf+4+off, TS_SIZE-4-off, p); +} +#endif + +#if 0 +/* needs 5 byte input, returns picture coding type*/ +static int read_picture_header(u8 *headr, struct mpg_picture *pic, int field, int pr) +{ + u8 pct; + + if (pr) printk( "Pic header: "); + pic->temporal_reference[field] = (( headr[0] << 2 ) | + (headr[1] & 0x03) )& 0x03ff; + if (pr) printk( " temp ref: 0x%04x", pic->temporal_reference[field]); + + pct = ( headr[1] >> 2 ) & 0x07; + pic->picture_coding_type[field] = pct; + if (pr) { + switch(pct){ + case I_FRAME: + printk( " I-FRAME"); + break; + case B_FRAME: + printk( " B-FRAME"); + break; + case P_FRAME: + printk( " P-FRAME"); + break; + } + } + + + pic->vinfo.vbv_delay = (( headr[1] >> 5 ) | ( headr[2] << 3) | + ( (headr[3] & 0x1F) << 11) ) & 0xffff; + + if (pr) printk( " vbv delay: 0x%04x", pic->vinfo.vbv_delay); + + pic->picture_header_parameter = ( headr[3] & 0xe0 ) | + ((headr[4] & 0x80) >> 3); + + if ( pct == B_FRAME ){ + pic->picture_header_parameter |= ( headr[4] >> 3 ) & 0x0f; + } + if (pr) printk( " pic head param: 0x%x", + pic->picture_header_parameter); + + return pct; +} +#endif + +#if 0 +/* needs 4 byte input */ +static int read_gop_header(u8 *headr, struct mpg_picture *pic, int pr) +{ + if (pr) printk("GOP header: "); + + pic->time_code = (( headr[0] << 17 ) | ( headr[1] << 9) | + ( headr[2] << 1 ) | (headr[3] &0x01)) & 0x1ffffff; + + if (pr) printk(" time: %d:%d.%d ", (headr[0]>>2)& 0x1F, + ((headr[0]<<4)& 0x30)| ((headr[1]>>4)& 0x0F), + ((headr[1]<<3)& 0x38)| ((headr[2]>>5)& 0x0F)); + + if ( ( headr[3] & 0x40 ) != 0 ){ + pic->closed_gop = 1; + } else { + pic->closed_gop = 0; + } + if (pr) printk("closed: %d", pic->closed_gop); + + if ( ( headr[3] & 0x20 ) != 0 ){ + pic->broken_link = 1; + } else { + pic->broken_link = 0; + } + if (pr) printk(" broken: %d\n", pic->broken_link); + + return 0; +} +#endif + +#if 0 +/* needs 8 byte input */ +static int read_sequence_header(u8 *headr, struct dvb_video_info *vi, int pr) +{ + int sw; + int form = -1; + + if (pr) printk("Reading sequence header\n"); + + vi->horizontal_size = ((headr[1] &0xF0) >> 4) | (headr[0] << 4); + vi->vertical_size = ((headr[1] &0x0F) << 8) | (headr[2]); + + sw = (int)((headr[3]&0xF0) >> 4) ; + + switch( sw ){ + case 1: + if (pr) + printk("Videostream: ASPECT: 1:1"); + vi->aspect_ratio = 100; + break; + case 2: + if (pr) + printk("Videostream: ASPECT: 4:3"); + vi->aspect_ratio = 133; + break; + case 3: + if (pr) + printk("Videostream: ASPECT: 16:9"); + vi->aspect_ratio = 177; + break; + case 4: + if (pr) + printk("Videostream: ASPECT: 2.21:1"); + vi->aspect_ratio = 221; + break; + + case 5 ... 15: + if (pr) + printk("Videostream: ASPECT: reserved"); + vi->aspect_ratio = 0; + break; + + default: + vi->aspect_ratio = 0; + return -1; + } + + if (pr) + printk(" Size = %dx%d",vi->horizontal_size,vi->vertical_size); + + sw = (int)(headr[3]&0x0F); + + switch ( sw ) { + case 1: + if (pr) + printk(" FRate: 23.976 fps"); + vi->framerate = 23976; + form = -1; + break; + case 2: + if (pr) + printk(" FRate: 24 fps"); + vi->framerate = 24000; + form = -1; + break; + case 3: + if (pr) + printk(" FRate: 25 fps"); + vi->framerate = 25000; + form = VIDEO_MODE_PAL; + break; + case 4: + if (pr) + printk(" FRate: 29.97 fps"); + vi->framerate = 29970; + form = VIDEO_MODE_NTSC; + break; + case 5: + if (pr) + printk(" FRate: 30 fps"); + vi->framerate = 30000; + form = VIDEO_MODE_NTSC; + break; + case 6: + if (pr) + printk(" FRate: 50 fps"); + vi->framerate = 50000; + form = VIDEO_MODE_PAL; + break; + case 7: + if (pr) + printk(" FRate: 60 fps"); + vi->framerate = 60000; + form = VIDEO_MODE_NTSC; + break; + } + + vi->bit_rate = (headr[4] << 10) | (headr[5] << 2) | (headr[6] & 0x03); + + vi->vbv_buffer_size + = (( headr[6] & 0xF8) >> 3 ) | (( headr[7] & 0x1F )<< 5); + + if (pr){ + printk(" BRate: %d Mbit/s",4*(vi->bit_rate)/10000); + printk(" vbvbuffer %d",16*1024*(vi->vbv_buffer_size)); + printk("\n"); + } + + vi->video_format = form; + + return 0; +} +#endif + + +#if 0 +static int get_vinfo(u8 *mbuf, int count, struct dvb_video_info *vi, int pr) +{ + u8 *headr; + int found = 0; + int c = 0; + + while (found < 4 && c+4 < count){ + u8 *b; + + b = mbuf+c; + if ( b[0] == 0x00 && b[1] == 0x00 && b[2] == 0x01 + && b[3] == 0xb3) found = 4; + else { + c++; + } + } + + if (! found) return -1; + c += 4; + if (c+12 >= count) return -1; + headr = mbuf+c; + if (read_sequence_header(headr, vi, pr) < 0) return -1; + vi->off = c-4; + return 0; +} +#endif + + +#if 0 +static int get_ainfo(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr) +{ + u8 *headr; + int found = 0; + int c = 0; + int fr = 0; + + while (found < 2 && c < count){ + u8 b[2]; + memcpy( b, mbuf+c, 2); + + if ( b[0] == 0xff && (b[1] & 0xf8) == 0xf8) + found = 2; + else { + c++; + } + } + + if (!found) return -1; + + if (c+3 >= count) return -1; + headr = mbuf+c; + + ai->layer = (headr[1] & 0x06) >> 1; + + if (pr) + printk("Audiostream: Layer: %d", 4-ai->layer); + + + ai->bit_rate = bitrates[(3-ai->layer)][(headr[2] >> 4 )]*1000; + + if (pr){ + if (ai->bit_rate == 0) + printk(" Bit rate: free"); + else if (ai->bit_rate == 0xf) + printk(" BRate: reserved"); + else + printk(" BRate: %d kb/s", ai->bit_rate/1000); + } + + fr = (headr[2] & 0x0c ) >> 2; + ai->frequency = freq[fr]*100; + if (pr){ + if (ai->frequency == 3) + printk(" Freq: reserved\n"); + else + printk(" Freq: %d kHz\n",ai->frequency); + + } + ai->off = c; + return 0; +} +#endif + + +int dvb_filter_get_ac3info(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr) +{ + u8 *headr; + int found = 0; + int c = 0; + u8 frame = 0; + int fr = 0; + + while ( !found && c < count){ + u8 *b = mbuf+c; + + if ( b[0] == 0x0b && b[1] == 0x77 ) + found = 1; + else { + c++; + } + } + + if (!found) return -1; + if (pr) + printk("Audiostream: AC3"); + + ai->off = c; + if (c+5 >= count) return -1; + + ai->layer = 0; // 0 for AC3 + headr = mbuf+c+2; + + frame = (headr[2]&0x3f); + ai->bit_rate = ac3_bitrates[frame >> 1]*1000; + + if (pr) + printk(" BRate: %d kb/s", (int) ai->bit_rate/1000); + + ai->frequency = (headr[2] & 0xc0 ) >> 6; + fr = (headr[2] & 0xc0 ) >> 6; + ai->frequency = freq[fr]*100; + if (pr) printk (" Freq: %d Hz\n", (int) ai->frequency); + + + ai->framesize = ac3_frames[fr][frame >> 1]; + if ((frame & 1) && (fr == 1)) ai->framesize++; + ai->framesize = ai->framesize << 1; + if (pr) printk (" Framesize %d\n",(int) ai->framesize); + + + return 0; +} +EXPORT_SYMBOL(dvb_filter_get_ac3info); + + +#if 0 +static u8 *skip_pes_header(u8 **bufp) +{ + u8 *inbuf = *bufp; + u8 *buf = inbuf; + u8 *pts = NULL; + int skip = 0; + + static const int mpeg1_skip_table[16] = { + 1, 0xffff, 5, 10, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff + }; + + + if ((inbuf[6] & 0xc0) == 0x80){ /* mpeg2 */ + if (buf[7] & PTS_ONLY) + pts = buf+9; + else pts = NULL; + buf = inbuf + 9 + inbuf[8]; + } else { /* mpeg1 */ + for (buf = inbuf + 6; *buf == 0xff; buf++) + if (buf == inbuf + 6 + 16) { + break; + } + if ((*buf & 0xc0) == 0x40) + buf += 2; + skip = mpeg1_skip_table [*buf >> 4]; + if (skip == 5 || skip == 10) pts = buf; + else pts = NULL; + + buf += mpeg1_skip_table [*buf >> 4]; + } + + *bufp = buf; + return pts; +} +#endif + +#if 0 +static void initialize_quant_matrix( u32 *matrix ) +{ + int i; + + matrix[0] = 0x08101013; + matrix[1] = 0x10131616; + matrix[2] = 0x16161616; + matrix[3] = 0x1a181a1b; + matrix[4] = 0x1b1b1a1a; + matrix[5] = 0x1a1a1b1b; + matrix[6] = 0x1b1d1d1d; + matrix[7] = 0x2222221d; + matrix[8] = 0x1d1d1b1b; + matrix[9] = 0x1d1d2020; + matrix[10] = 0x22222526; + matrix[11] = 0x25232322; + matrix[12] = 0x23262628; + matrix[13] = 0x28283030; + matrix[14] = 0x2e2e3838; + matrix[15] = 0x3a454553; + + for ( i = 16 ; i < 32 ; i++ ) + matrix[i] = 0x10101010; +} +#endif + +#if 0 +static void initialize_mpg_picture(struct mpg_picture *pic) +{ + int i; + + /* set MPEG1 */ + pic->mpeg1_flag = 1; + pic->profile_and_level = 0x4A ; /* MP@LL */ + pic->progressive_sequence = 1; + pic->low_delay = 0; + + pic->sequence_display_extension_flag = 0; + for ( i = 0 ; i < 4 ; i++ ){ + pic->frame_centre_horizontal_offset[i] = 0; + pic->frame_centre_vertical_offset[i] = 0; + } + pic->last_frame_centre_horizontal_offset = 0; + pic->last_frame_centre_vertical_offset = 0; + + pic->picture_display_extension_flag[0] = 0; + pic->picture_display_extension_flag[1] = 0; + pic->sequence_header_flag = 0; + pic->gop_flag = 0; + pic->sequence_end_flag = 0; +} +#endif + +#if 0 +static void mpg_set_picture_parameter( int32_t field_type, struct mpg_picture *pic ) +{ + int16_t last_h_offset; + int16_t last_v_offset; + + int16_t *p_h_offset; + int16_t *p_v_offset; + + if ( pic->mpeg1_flag ){ + pic->picture_structure[field_type] = VIDEO_FRAME_PICTURE; + pic->top_field_first = 0; + pic->repeat_first_field = 0; + pic->progressive_frame = 1; + pic->picture_coding_parameter = 0x000010; + } + + /* Reset flag */ + pic->picture_display_extension_flag[field_type] = 0; + + last_h_offset = pic->last_frame_centre_horizontal_offset; + last_v_offset = pic->last_frame_centre_vertical_offset; + if ( field_type == FIRST_FIELD ){ + p_h_offset = pic->frame_centre_horizontal_offset; + p_v_offset = pic->frame_centre_vertical_offset; + *p_h_offset = last_h_offset; + *(p_h_offset + 1) = last_h_offset; + *(p_h_offset + 2) = last_h_offset; + *p_v_offset = last_v_offset; + *(p_v_offset + 1) = last_v_offset; + *(p_v_offset + 2) = last_v_offset; + } else { + pic->frame_centre_horizontal_offset[3] = last_h_offset; + pic->frame_centre_vertical_offset[3] = last_v_offset; + } +} +#endif + +#if 0 +static void init_mpg_picture( struct mpg_picture *pic, int chan, int32_t field_type) +{ + pic->picture_header = 0; + pic->sequence_header_data + = ( INIT_HORIZONTAL_SIZE << 20 ) + | ( INIT_VERTICAL_SIZE << 8 ) + | ( INIT_ASPECT_RATIO << 4 ) + | ( INIT_FRAME_RATE ); + pic->mpeg1_flag = 0; + pic->vinfo.horizontal_size + = INIT_DISP_HORIZONTAL_SIZE; + pic->vinfo.vertical_size + = INIT_DISP_VERTICAL_SIZE; + pic->picture_display_extension_flag[field_type] + = 0; + pic->pts_flag[field_type] = 0; + + pic->sequence_gop_header = 0; + pic->picture_header = 0; + pic->sequence_header_flag = 0; + pic->gop_flag = 0; + pic->sequence_end_flag = 0; + pic->sequence_display_extension_flag = 0; + pic->last_frame_centre_horizontal_offset = 0; + pic->last_frame_centre_vertical_offset = 0; + pic->channel = chan; +} +#endif + +void dvb_filter_pes2ts_init(struct dvb_filter_pes2ts *p2ts, unsigned short pid, + dvb_filter_pes2ts_cb_t *cb, void *priv) +{ + unsigned char *buf=p2ts->buf; + + buf[0]=0x47; + buf[1]=(pid>>8); + buf[2]=pid&0xff; + p2ts->cc=0; + p2ts->cb=cb; + p2ts->priv=priv; +} +EXPORT_SYMBOL(dvb_filter_pes2ts_init); + +int dvb_filter_pes2ts(struct dvb_filter_pes2ts *p2ts, unsigned char *pes, + int len, int payload_start) +{ + unsigned char *buf=p2ts->buf; + int ret=0, rest; + + //len=6+((pes[4]<<8)|pes[5]); + + if (payload_start) + buf[1]|=0x40; + else + buf[1]&=~0x40; + while (len>=184) { + buf[3]=0x10|((p2ts->cc++)&0x0f); + memcpy(buf+4, pes, 184); + if ((ret=p2ts->cb(p2ts->priv, buf))) + return ret; + len-=184; pes+=184; + buf[1]&=~0x40; + } + if (!len) + return 0; + buf[3]=0x30|((p2ts->cc++)&0x0f); + rest=183-len; + if (rest) { + buf[5]=0x00; + if (rest-1) + memset(buf+6, 0xff, rest-1); + } + buf[4]=rest; + memcpy(buf+5+rest, pes, len); + return p2ts->cb(p2ts->priv, buf); +} +EXPORT_SYMBOL(dvb_filter_pes2ts); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_filter.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,246 @@ +/* + * dvb_filter.h + * + * Copyright (C) 2003 Convergence GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DVB_FILTER_H_ +#define _DVB_FILTER_H_ + +#include + +#include "demux.h" + +typedef int (dvb_filter_pes2ts_cb_t) (void *, unsigned char *); + +struct dvb_filter_pes2ts { + unsigned char buf[188]; + unsigned char cc; + dvb_filter_pes2ts_cb_t *cb; + void *priv; +}; + +void dvb_filter_pes2ts_init(struct dvb_filter_pes2ts *p2ts, unsigned short pid, + dvb_filter_pes2ts_cb_t *cb, void *priv); + +int dvb_filter_pes2ts(struct dvb_filter_pes2ts *p2ts, unsigned char *pes, + int len, int payload_start); + + +#define PROG_STREAM_MAP 0xBC +#define PRIVATE_STREAM1 0xBD +#define PADDING_STREAM 0xBE +#define PRIVATE_STREAM2 0xBF +#define AUDIO_STREAM_S 0xC0 +#define AUDIO_STREAM_E 0xDF +#define VIDEO_STREAM_S 0xE0 +#define VIDEO_STREAM_E 0xEF +#define ECM_STREAM 0xF0 +#define EMM_STREAM 0xF1 +#define DSM_CC_STREAM 0xF2 +#define ISO13522_STREAM 0xF3 +#define PROG_STREAM_DIR 0xFF + +#define DVB_PICTURE_START 0x00 +#define DVB_USER_START 0xb2 +#define DVB_SEQUENCE_HEADER 0xb3 +#define DVB_SEQUENCE_ERROR 0xb4 +#define DVB_EXTENSION_START 0xb5 +#define DVB_SEQUENCE_END 0xb7 +#define DVB_GOP_START 0xb8 +#define DVB_EXCEPT_SLICE 0xb0 + +#define SEQUENCE_EXTENSION 0x01 +#define SEQUENCE_DISPLAY_EXTENSION 0x02 +#define PICTURE_CODING_EXTENSION 0x08 +#define QUANT_MATRIX_EXTENSION 0x03 +#define PICTURE_DISPLAY_EXTENSION 0x07 + +#define I_FRAME 0x01 +#define B_FRAME 0x02 +#define P_FRAME 0x03 + +/* Initialize sequence_data */ +#define INIT_HORIZONTAL_SIZE 720 +#define INIT_VERTICAL_SIZE 576 +#define INIT_ASPECT_RATIO 0x02 +#define INIT_FRAME_RATE 0x03 +#define INIT_DISP_HORIZONTAL_SIZE 540 +#define INIT_DISP_VERTICAL_SIZE 576 + + +//flags2 +#define PTS_DTS_FLAGS 0xC0 +#define ESCR_FLAG 0x20 +#define ES_RATE_FLAG 0x10 +#define DSM_TRICK_FLAG 0x08 +#define ADD_CPY_FLAG 0x04 +#define PES_CRC_FLAG 0x02 +#define PES_EXT_FLAG 0x01 + +//pts_dts flags +#define PTS_ONLY 0x80 +#define PTS_DTS 0xC0 + +#define TS_SIZE 188 +#define TRANS_ERROR 0x80 +#define PAY_START 0x40 +#define TRANS_PRIO 0x20 +#define PID_MASK_HI 0x1F +//flags +#define TRANS_SCRMBL1 0x80 +#define TRANS_SCRMBL2 0x40 +#define ADAPT_FIELD 0x20 +#define PAYLOAD 0x10 +#define COUNT_MASK 0x0F + +// adaptation flags +#define DISCON_IND 0x80 +#define RAND_ACC_IND 0x40 +#define ES_PRI_IND 0x20 +#define PCR_FLAG 0x10 +#define OPCR_FLAG 0x08 +#define SPLICE_FLAG 0x04 +#define TRANS_PRIV 0x02 +#define ADAP_EXT_FLAG 0x01 + +// adaptation extension flags +#define LTW_FLAG 0x80 +#define PIECE_RATE 0x40 +#define SEAM_SPLICE 0x20 + + +#define MAX_PLENGTH 0xFFFF +#define MMAX_PLENGTH (256*MAX_PLENGTH) + +#ifndef IPACKS +#define IPACKS 2048 +#endif + +struct ipack { + int size; + int found; + u8 *buf; + u8 cid; + u32 plength; + u8 plen[2]; + u8 flag1; + u8 flag2; + u8 hlength; + u8 pts[5]; + u16 *pid; + int mpeg; + u8 check; + int which; + int done; + void *data; + void (*func)(u8 *buf, int size, void *priv); + int count; + int repack_subids; +}; + +struct dvb_video_info { + u32 horizontal_size; + u32 vertical_size; + u32 aspect_ratio; + u32 framerate; + u32 video_format; + u32 bit_rate; + u32 comp_bit_rate; + u32 vbv_buffer_size; + s16 vbv_delay; + u32 CSPF; + u32 off; +}; + +#define OFF_SIZE 4 +#define FIRST_FIELD 0 +#define SECOND_FIELD 1 +#define VIDEO_FRAME_PICTURE 0x03 + +struct mpg_picture { + int channel; + struct dvb_video_info vinfo; + u32 *sequence_gop_header; + u32 *picture_header; + s32 time_code; + int low_delay; + int closed_gop; + int broken_link; + int sequence_header_flag; + int gop_flag; + int sequence_end_flag; + + u8 profile_and_level; + s32 picture_coding_parameter; + u32 matrix[32]; + s8 matrix_change_flag; + + u8 picture_header_parameter; + /* bit 0 - 2: bwd f code + bit 3 : fpb vector + bit 4 - 6: fwd f code + bit 7 : fpf vector */ + + int mpeg1_flag; + int progressive_sequence; + int sequence_display_extension_flag; + u32 sequence_header_data; + s16 last_frame_centre_horizontal_offset; + s16 last_frame_centre_vertical_offset; + + u32 pts[2]; /* [0] 1st field, [1] 2nd field */ + int top_field_first; + int repeat_first_field; + int progressive_frame; + int bank; + int forward_bank; + int backward_bank; + int compress; + s16 frame_centre_horizontal_offset[OFF_SIZE]; + /* [0-2] 1st field, [3] 2nd field */ + s16 frame_centre_vertical_offset[OFF_SIZE]; + /* [0-2] 1st field, [3] 2nd field */ + s16 temporal_reference[2]; + /* [0] 1st field, [1] 2nd field */ + + s8 picture_coding_type[2]; + /* [0] 1st field, [1] 2nd field */ + s8 picture_structure[2]; + /* [0] 1st field, [1] 2nd field */ + s8 picture_display_extension_flag[2]; + /* [0] 1st field, [1] 2nd field */ + /* picture_display_extenion() 0:no 1:exit*/ + s8 pts_flag[2]; + /* [0] 1st field, [1] 2nd field */ +}; + +struct dvb_audio_info { + int layer; + u32 bit_rate; + u32 frequency; + u32 mode; + u32 mode_extension ; + u32 emphasis; + u32 framesize; + u32 off; +}; + +int dvb_filter_get_ac3info(u8 *mbuf, int count, struct dvb_audio_info *ai, int pr); + + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,2696 @@ +/* + * dvb_frontend.c: DVB frontend tuning interface/thread + * + * + * Copyright (C) 1999-2001 Ralph Metzler + * Marcus Metzler + * Holger Waechtler + * for convergence integrated media GmbH + * + * Copyright (C) 2004 Andrew de Quincey (tuning thread cleanup) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +/* Enables DVBv3 compatibility bits at the headers */ +#define __DVB_CORE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "dvbdev.h" +#include + +static int dvb_frontend_debug; +static int dvb_shutdown_timeout; +static int dvb_force_auto_inversion; +static int dvb_override_tune_delay; +static int dvb_powerdown_on_sleep = 1; +static int dvb_mfe_wait_time = 5; + +module_param_named(frontend_debug, dvb_frontend_debug, int, 0644); +MODULE_PARM_DESC(frontend_debug, "Turn on/off frontend core debugging (default:off)."); +module_param(dvb_shutdown_timeout, int, 0644); +MODULE_PARM_DESC(dvb_shutdown_timeout, "wait seconds after close() before suspending hardware"); +module_param(dvb_force_auto_inversion, int, 0644); +MODULE_PARM_DESC(dvb_force_auto_inversion, "0: normal (default), 1: INVERSION_AUTO forced always"); +module_param(dvb_override_tune_delay, int, 0644); +MODULE_PARM_DESC(dvb_override_tune_delay, "0: normal (default), >0 => delay in milliseconds to wait for lock after a tune attempt"); +module_param(dvb_powerdown_on_sleep, int, 0644); +MODULE_PARM_DESC(dvb_powerdown_on_sleep, "0: do not power down, 1: turn LNB voltage off on sleep (default)"); +module_param(dvb_mfe_wait_time, int, 0644); +MODULE_PARM_DESC(dvb_mfe_wait_time, "Wait up to seconds on open() for multi-frontend to become available (default:5 seconds)"); + +#define FESTATE_IDLE 1 +#define FESTATE_RETUNE 2 +#define FESTATE_TUNING_FAST 4 +#define FESTATE_TUNING_SLOW 8 +#define FESTATE_TUNED 16 +#define FESTATE_ZIGZAG_FAST 32 +#define FESTATE_ZIGZAG_SLOW 64 +#define FESTATE_DISEQC 128 +#define FESTATE_ERROR 256 +#define FESTATE_WAITFORLOCK (FESTATE_TUNING_FAST | FESTATE_TUNING_SLOW | FESTATE_ZIGZAG_FAST | FESTATE_ZIGZAG_SLOW | FESTATE_DISEQC) +#define FESTATE_SEARCHING_FAST (FESTATE_TUNING_FAST | FESTATE_ZIGZAG_FAST) +#define FESTATE_SEARCHING_SLOW (FESTATE_TUNING_SLOW | FESTATE_ZIGZAG_SLOW) +#define FESTATE_LOSTLOCK (FESTATE_ZIGZAG_FAST | FESTATE_ZIGZAG_SLOW) + +#define FE_ALGO_HW 1 +/* + * FESTATE_IDLE. No tuning parameters have been supplied and the loop is idling. + * FESTATE_RETUNE. Parameters have been supplied, but we have not yet performed the first tune. + * FESTATE_TUNING_FAST. Tuning parameters have been supplied and fast zigzag scan is in progress. + * FESTATE_TUNING_SLOW. Tuning parameters have been supplied. Fast zigzag failed, so we're trying again, but slower. + * FESTATE_TUNED. The frontend has successfully locked on. + * FESTATE_ZIGZAG_FAST. The lock has been lost, and a fast zigzag has been initiated to try and regain it. + * FESTATE_ZIGZAG_SLOW. The lock has been lost. Fast zigzag has been failed, so we're trying again, but slower. + * FESTATE_DISEQC. A DISEQC command has just been issued. + * FESTATE_WAITFORLOCK. When we're waiting for a lock. + * FESTATE_SEARCHING_FAST. When we're searching for a signal using a fast zigzag scan. + * FESTATE_SEARCHING_SLOW. When we're searching for a signal using a slow zigzag scan. + * FESTATE_LOSTLOCK. When the lock has been lost, and we're searching it again. + */ + +#define DVB_FE_NO_EXIT 0 +#define DVB_FE_NORMAL_EXIT 1 +#define DVB_FE_DEVICE_REMOVED 2 + +static DEFINE_MUTEX(frontend_mutex); + +struct dvb_frontend_private { + + /* thread/frontend values */ + struct dvb_device *dvbdev; + struct dvb_frontend_parameters parameters_out; + struct dvb_fe_events events; + struct semaphore sem; + struct list_head list_head; + wait_queue_head_t wait_queue; + struct task_struct *thread; + unsigned long release_jiffies; + unsigned int exit; + unsigned int wakeup; + fe_status_t status; + unsigned long tune_mode_flags; + unsigned int delay; + unsigned int reinitialise; + int tone; + int voltage; + + /* swzigzag values */ + unsigned int state; + unsigned int bending; + int lnb_drift; + unsigned int inversion; + unsigned int auto_step; + unsigned int auto_sub_step; + unsigned int started_auto_step; + unsigned int min_delay; + unsigned int max_drift; + unsigned int step_size; + int quality; + unsigned int check_wrapped; + enum dvbfe_search algo_status; +}; + +static void dvb_frontend_wakeup(struct dvb_frontend *fe); +static int dtv_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p_out); +static int dtv_property_legacy_params_sync(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p); + +static bool has_get_frontend(struct dvb_frontend *fe) +{ + return fe->ops.get_frontend != NULL; +} + +/* + * Due to DVBv3 API calls, a delivery system should be mapped into one of + * the 4 DVBv3 delivery systems (FE_QPSK, FE_QAM, FE_OFDM or FE_ATSC), + * otherwise, a DVBv3 call will fail. + */ +enum dvbv3_emulation_type { + DVBV3_UNKNOWN, + DVBV3_QPSK, + DVBV3_QAM, + DVBV3_OFDM, + DVBV3_ATSC, +}; + +static enum dvbv3_emulation_type dvbv3_type(u32 delivery_system) +{ + switch (delivery_system) { + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + return DVBV3_QAM; + case SYS_DVBS: + case SYS_DVBS2: + case SYS_TURBO: + case SYS_ISDBS: + case SYS_DSS: + return DVBV3_QPSK; + case SYS_DVBT: + case SYS_DVBT2: + case SYS_ISDBT: + case SYS_DTMB: + return DVBV3_OFDM; + case SYS_ATSC: + case SYS_ATSCMH: + case SYS_DVBC_ANNEX_B: + return DVBV3_ATSC; + case SYS_UNDEFINED: + case SYS_ISDBC: + case SYS_DVBH: + case SYS_DAB: + default: + /* + * Doesn't know how to emulate those types and/or + * there's no frontend driver from this type yet + * with some emulation code, so, we're not sure yet how + * to handle them, or they're not compatible with a DVBv3 call. + */ + return DVBV3_UNKNOWN; + } +} + +static void dvb_frontend_add_event(struct dvb_frontend *fe, fe_status_t status) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dvb_fe_events *events = &fepriv->events; + struct dvb_frontend_event *e; + int wp; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + if ((status & FE_HAS_LOCK) && has_get_frontend(fe)) + dtv_get_frontend(fe, &fepriv->parameters_out); + + mutex_lock(&events->mtx); + + wp = (events->eventw + 1) % MAX_EVENT; + if (wp == events->eventr) { + events->overflow = 1; + events->eventr = (events->eventr + 1) % MAX_EVENT; + } + + e = &events->events[events->eventw]; + e->status = status; + e->parameters = fepriv->parameters_out; + + events->eventw = wp; + + mutex_unlock(&events->mtx); + + wake_up_interruptible (&events->wait_queue); +} + +static int dvb_frontend_get_event(struct dvb_frontend *fe, + struct dvb_frontend_event *event, int flags) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dvb_fe_events *events = &fepriv->events; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + if (events->overflow) { + events->overflow = 0; + return -EOVERFLOW; + } + + if (events->eventw == events->eventr) { + int ret; + + if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + + up(&fepriv->sem); + + ret = wait_event_interruptible (events->wait_queue, + events->eventw != events->eventr); + + if (down_interruptible (&fepriv->sem)) + return -ERESTARTSYS; + + if (ret < 0) + return ret; + } + + mutex_lock(&events->mtx); + *event = events->events[events->eventr]; + events->eventr = (events->eventr + 1) % MAX_EVENT; + mutex_unlock(&events->mtx); + + return 0; +} + +static void dvb_frontend_clear_events(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dvb_fe_events *events = &fepriv->events; + + mutex_lock(&events->mtx); + events->eventr = events->eventw; + mutex_unlock(&events->mtx); +} + +static void dvb_frontend_init(struct dvb_frontend *fe) +{ + dev_dbg(fe->dvb->device, + "%s: initialising adapter %i frontend %i (%s)...\n", + __func__, fe->dvb->num, fe->id, fe->ops.info.name); + + if (fe->ops.init) + fe->ops.init(fe); + if (fe->ops.tuner_ops.init) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + fe->ops.tuner_ops.init(fe); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } +} + +void dvb_frontend_reinitialise(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + + fepriv->reinitialise = 1; + dvb_frontend_wakeup(fe); +} +EXPORT_SYMBOL(dvb_frontend_reinitialise); + +static void dvb_frontend_swzigzag_update_delay(struct dvb_frontend_private *fepriv, int locked) +{ + int q2; + struct dvb_frontend *fe = fepriv->dvbdev->priv; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + if (locked) + (fepriv->quality) = (fepriv->quality * 220 + 36*256) / 256; + else + (fepriv->quality) = (fepriv->quality * 220 + 0) / 256; + + q2 = fepriv->quality - 128; + q2 *= q2; + + fepriv->delay = fepriv->min_delay + q2 * HZ / (128*128); +} + +/** + * Performs automatic twiddling of frontend parameters. + * + * @param fe The frontend concerned. + * @param check_wrapped Checks if an iteration has completed. DO NOT SET ON THE FIRST ATTEMPT + * @returns Number of complete iterations that have been performed. + */ +static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wrapped) +{ + int autoinversion; + int ready = 0; + int fe_set_err = 0; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache, tmp; + int original_inversion = c->inversion; + u32 original_frequency = c->frequency; + + /* are we using autoinversion? */ + autoinversion = ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) && + (c->inversion == INVERSION_AUTO)); + + /* setup parameters correctly */ + while(!ready) { + /* calculate the lnb_drift */ + fepriv->lnb_drift = fepriv->auto_step * fepriv->step_size; + + /* wrap the auto_step if we've exceeded the maximum drift */ + if (fepriv->lnb_drift > fepriv->max_drift) { + fepriv->auto_step = 0; + fepriv->auto_sub_step = 0; + fepriv->lnb_drift = 0; + } + + /* perform inversion and +/- zigzag */ + switch(fepriv->auto_sub_step) { + case 0: + /* try with the current inversion and current drift setting */ + ready = 1; + break; + + case 1: + if (!autoinversion) break; + + fepriv->inversion = (fepriv->inversion == INVERSION_OFF) ? INVERSION_ON : INVERSION_OFF; + ready = 1; + break; + + case 2: + if (fepriv->lnb_drift == 0) break; + + fepriv->lnb_drift = -fepriv->lnb_drift; + ready = 1; + break; + + case 3: + if (fepriv->lnb_drift == 0) break; + if (!autoinversion) break; + + fepriv->inversion = (fepriv->inversion == INVERSION_OFF) ? INVERSION_ON : INVERSION_OFF; + fepriv->lnb_drift = -fepriv->lnb_drift; + ready = 1; + break; + + default: + fepriv->auto_step++; + fepriv->auto_sub_step = -1; /* it'll be incremented to 0 in a moment */ + break; + } + + if (!ready) fepriv->auto_sub_step++; + } + + /* if this attempt would hit where we started, indicate a complete + * iteration has occurred */ + if ((fepriv->auto_step == fepriv->started_auto_step) && + (fepriv->auto_sub_step == 0) && check_wrapped) { + return 1; + } + + dev_dbg(fe->dvb->device, "%s: drift:%i inversion:%i auto_step:%i " \ + "auto_sub_step:%i started_auto_step:%i\n", + __func__, fepriv->lnb_drift, fepriv->inversion, + fepriv->auto_step, fepriv->auto_sub_step, + fepriv->started_auto_step); + + /* set the frontend itself */ + c->frequency += fepriv->lnb_drift; + if (autoinversion) + c->inversion = fepriv->inversion; + tmp = *c; + if (fe->ops.set_frontend) + fe_set_err = fe->ops.set_frontend(fe); + *c = tmp; + if (fe_set_err < 0) { + fepriv->state = FESTATE_ERROR; + return fe_set_err; + } + + c->frequency = original_frequency; + c->inversion = original_inversion; + + fepriv->auto_sub_step++; + return 0; +} + +static void dvb_frontend_swzigzag(struct dvb_frontend *fe) +{ + fe_status_t s = 0; + int retval = 0; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache, tmp; + + /* if we've got no parameters, just keep idling */ + if (fepriv->state & FESTATE_IDLE) { + fepriv->delay = 3*HZ; + fepriv->quality = 0; + return; + } + + /* in SCAN mode, we just set the frontend when asked and leave it alone */ + if (fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT) { + if (fepriv->state & FESTATE_RETUNE) { + tmp = *c; + if (fe->ops.set_frontend) + retval = fe->ops.set_frontend(fe); + *c = tmp; + if (retval < 0) + fepriv->state = FESTATE_ERROR; + else + fepriv->state = FESTATE_TUNED; + } + fepriv->delay = 3*HZ; + fepriv->quality = 0; + return; + } + + /* get the frontend status */ + if (fepriv->state & FESTATE_RETUNE) { + s = 0; + } else { + if (fe->ops.read_status) + fe->ops.read_status(fe, &s); + if (s != fepriv->status) { + dvb_frontend_add_event(fe, s); + fepriv->status = s; + } + } + + /* if we're not tuned, and we have a lock, move to the TUNED state */ + if ((fepriv->state & FESTATE_WAITFORLOCK) && (s & FE_HAS_LOCK)) { + dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); + fepriv->state = FESTATE_TUNED; + + /* if we're tuned, then we have determined the correct inversion */ + if ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) && + (c->inversion == INVERSION_AUTO)) { + c->inversion = fepriv->inversion; + } + return; + } + + /* if we are tuned already, check we're still locked */ + if (fepriv->state & FESTATE_TUNED) { + dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); + + /* we're tuned, and the lock is still good... */ + if (s & FE_HAS_LOCK) { + return; + } else { /* if we _WERE_ tuned, but now don't have a lock */ + fepriv->state = FESTATE_ZIGZAG_FAST; + fepriv->started_auto_step = fepriv->auto_step; + fepriv->check_wrapped = 0; + } + } + + /* don't actually do anything if we're in the LOSTLOCK state, + * the frontend is set to FE_CAN_RECOVER, and the max_drift is 0 */ + if ((fepriv->state & FESTATE_LOSTLOCK) && + (fe->ops.info.caps & FE_CAN_RECOVER) && (fepriv->max_drift == 0)) { + dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); + return; + } + + /* don't do anything if we're in the DISEQC state, since this + * might be someone with a motorized dish controlled by DISEQC. + * If its actually a re-tune, there will be a SET_FRONTEND soon enough. */ + if (fepriv->state & FESTATE_DISEQC) { + dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); + return; + } + + /* if we're in the RETUNE state, set everything up for a brand + * new scan, keeping the current inversion setting, as the next + * tune is _very_ likely to require the same */ + if (fepriv->state & FESTATE_RETUNE) { + fepriv->lnb_drift = 0; + fepriv->auto_step = 0; + fepriv->auto_sub_step = 0; + fepriv->started_auto_step = 0; + fepriv->check_wrapped = 0; + } + + /* fast zigzag. */ + if ((fepriv->state & FESTATE_SEARCHING_FAST) || (fepriv->state & FESTATE_RETUNE)) { + fepriv->delay = fepriv->min_delay; + + /* perform a tune */ + retval = dvb_frontend_swzigzag_autotune(fe, + fepriv->check_wrapped); + if (retval < 0) { + return; + } else if (retval) { + /* OK, if we've run out of trials at the fast speed. + * Drop back to slow for the _next_ attempt */ + fepriv->state = FESTATE_SEARCHING_SLOW; + fepriv->started_auto_step = fepriv->auto_step; + return; + } + fepriv->check_wrapped = 1; + + /* if we've just retuned, enter the ZIGZAG_FAST state. + * This ensures we cannot return from an + * FE_SET_FRONTEND ioctl before the first frontend tune + * occurs */ + if (fepriv->state & FESTATE_RETUNE) { + fepriv->state = FESTATE_TUNING_FAST; + } + } + + /* slow zigzag */ + if (fepriv->state & FESTATE_SEARCHING_SLOW) { + dvb_frontend_swzigzag_update_delay(fepriv, s & FE_HAS_LOCK); + + /* Note: don't bother checking for wrapping; we stay in this + * state until we get a lock */ + dvb_frontend_swzigzag_autotune(fe, 0); + } +} + +static int dvb_frontend_is_exiting(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + + if (fepriv->exit != DVB_FE_NO_EXIT) + return 1; + + if (fepriv->dvbdev->writers == 1) + if (time_after_eq(jiffies, fepriv->release_jiffies + + dvb_shutdown_timeout * HZ)) + return 1; + + return 0; +} + +static int dvb_frontend_should_wakeup(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + + if (fepriv->wakeup) { + fepriv->wakeup = 0; + return 1; + } + return dvb_frontend_is_exiting(fe); +} + +static void dvb_frontend_wakeup(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + + fepriv->wakeup = 1; + wake_up_interruptible(&fepriv->wait_queue); +} + +static int dvb_frontend_thread(void *data) +{ + struct dvb_frontend *fe = data; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + fe_status_t s; + enum dvbfe_algo algo; + + bool re_tune = false; + bool semheld = false; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + fepriv->check_wrapped = 0; + fepriv->quality = 0; + fepriv->delay = 3*HZ; + fepriv->status = 0; + fepriv->wakeup = 0; + fepriv->reinitialise = 0; + + dvb_frontend_init(fe); + + set_freezable(); + while (1) { + up(&fepriv->sem); /* is locked when we enter the thread... */ +restart: + wait_event_interruptible_timeout(fepriv->wait_queue, + dvb_frontend_should_wakeup(fe) || kthread_should_stop() + || freezing(current), + fepriv->delay); + + if (kthread_should_stop() || dvb_frontend_is_exiting(fe)) { + /* got signal or quitting */ + if (!down_interruptible(&fepriv->sem)) + semheld = true; + fepriv->exit = DVB_FE_NORMAL_EXIT; + break; + } + + if (try_to_freeze()) + goto restart; + + if (down_interruptible(&fepriv->sem)) + break; + + if (fepriv->reinitialise) { + dvb_frontend_init(fe); + if (fe->ops.set_tone && fepriv->tone != -1) + fe->ops.set_tone(fe, fepriv->tone); + if (fe->ops.set_voltage && fepriv->voltage != -1) + fe->ops.set_voltage(fe, fepriv->voltage); + fepriv->reinitialise = 0; + } + + /* do an iteration of the tuning loop */ + if (fe->ops.get_frontend_algo) { + algo = fe->ops.get_frontend_algo(fe); + switch (algo) { + case DVBFE_ALGO_HW: + dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_HW\n", __func__); + + if (fepriv->state & FESTATE_RETUNE) { + dev_dbg(fe->dvb->device, "%s: Retune requested, FESTATE_RETUNE\n", __func__); + re_tune = true; + fepriv->state = FESTATE_TUNED; + } else { + re_tune = false; + } + + if (fe->ops.tune) + fe->ops.tune(fe, re_tune, fepriv->tune_mode_flags, &fepriv->delay, &s); + + if (s != fepriv->status && !(fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT)) { + dev_dbg(fe->dvb->device, "%s: state changed, adding current state\n", __func__); + dvb_frontend_add_event(fe, s); + fepriv->status = s; + } + break; + case DVBFE_ALGO_SW: + dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_SW\n", __func__); + dvb_frontend_swzigzag(fe); + break; + case DVBFE_ALGO_CUSTOM: + dev_dbg(fe->dvb->device, "%s: Frontend ALGO = DVBFE_ALGO_CUSTOM, state=%d\n", __func__, fepriv->state); + if (fepriv->state & FESTATE_RETUNE) { + dev_dbg(fe->dvb->device, "%s: Retune requested, FESTAT_RETUNE\n", __func__); + fepriv->state = FESTATE_TUNED; + } + /* Case where we are going to search for a carrier + * User asked us to retune again for some reason, possibly + * requesting a search with a new set of parameters + */ + if (fepriv->algo_status & DVBFE_ALGO_SEARCH_AGAIN) { + if (fe->ops.search) { + fepriv->algo_status = fe->ops.search(fe); + /* We did do a search as was requested, the flags are + * now unset as well and has the flags wrt to search. + */ + } else { + fepriv->algo_status &= ~DVBFE_ALGO_SEARCH_AGAIN; + } + } + /* Track the carrier if the search was successful */ + if (fepriv->algo_status != DVBFE_ALGO_SEARCH_SUCCESS) { + fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; + fepriv->delay = HZ / 2; + } + dtv_property_legacy_params_sync(fe, &fepriv->parameters_out); + fe->ops.read_status(fe, &s); + if (s != fepriv->status) { + dvb_frontend_add_event(fe, s); /* update event list */ + fepriv->status = s; + if (!(s & FE_HAS_LOCK)) { + fepriv->delay = HZ / 10; + fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; + } else { + fepriv->delay = 60 * HZ; + } + } + break; + default: + dev_dbg(fe->dvb->device, "%s: UNDEFINED ALGO !\n", __func__); + break; + } + } else { + dvb_frontend_swzigzag(fe); + } + } + + if (dvb_powerdown_on_sleep) { + if (fe->ops.set_voltage) + fe->ops.set_voltage(fe, SEC_VOLTAGE_OFF); + if (fe->ops.tuner_ops.sleep) { + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + fe->ops.tuner_ops.sleep(fe); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + if (fe->ops.sleep) + fe->ops.sleep(fe); + } + + fepriv->thread = NULL; + if (kthread_should_stop()) + fepriv->exit = DVB_FE_DEVICE_REMOVED; + else + fepriv->exit = DVB_FE_NO_EXIT; + mb(); + + if (semheld) + up(&fepriv->sem); + dvb_frontend_wakeup(fe); + return 0; +} + +static void dvb_frontend_stop(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + fepriv->exit = DVB_FE_NORMAL_EXIT; + mb(); + + if (!fepriv->thread) + return; + + kthread_stop(fepriv->thread); + + sema_init(&fepriv->sem, 1); + fepriv->state = FESTATE_IDLE; + + /* paranoia check in case a signal arrived */ + if (fepriv->thread) + dev_warn(fe->dvb->device, + "dvb_frontend_stop: warning: thread %p won't exit\n", + fepriv->thread); +} + +s32 timeval_usec_diff(struct timeval lasttime, struct timeval curtime) +{ + return ((curtime.tv_usec < lasttime.tv_usec) ? + 1000000 - lasttime.tv_usec + curtime.tv_usec : + curtime.tv_usec - lasttime.tv_usec); +} +EXPORT_SYMBOL(timeval_usec_diff); + +static inline void timeval_usec_add(struct timeval *curtime, u32 add_usec) +{ + curtime->tv_usec += add_usec; + if (curtime->tv_usec >= 1000000) { + curtime->tv_usec -= 1000000; + curtime->tv_sec++; + } +} + +/* + * Sleep until gettimeofday() > waketime + add_usec + * This needs to be as precise as possible, but as the delay is + * usually between 2ms and 32ms, it is done using a scheduled msleep + * followed by usleep (normally a busy-wait loop) for the remainder + */ +void dvb_frontend_sleep_until(struct timeval *waketime, u32 add_usec) +{ + struct timeval lasttime; + s32 delta, newdelta; + + timeval_usec_add(waketime, add_usec); + + do_gettimeofday(&lasttime); + delta = timeval_usec_diff(lasttime, *waketime); + if (delta > 2500) { + msleep((delta - 1500) / 1000); + do_gettimeofday(&lasttime); + newdelta = timeval_usec_diff(lasttime, *waketime); + delta = (newdelta > delta) ? 0 : newdelta; + } + if (delta > 0) + udelay(delta); +} +EXPORT_SYMBOL(dvb_frontend_sleep_until); + +static int dvb_frontend_start(struct dvb_frontend *fe) +{ + int ret; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct task_struct *fe_thread; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + if (fepriv->thread) { + if (fepriv->exit == DVB_FE_NO_EXIT) + return 0; + else + dvb_frontend_stop (fe); + } + + if (signal_pending(current)) + return -EINTR; + if (down_interruptible (&fepriv->sem)) + return -EINTR; + + fepriv->state = FESTATE_IDLE; + fepriv->exit = DVB_FE_NO_EXIT; + fepriv->thread = NULL; + mb(); + + fe_thread = kthread_run(dvb_frontend_thread, fe, + "kdvb-ad-%i-fe-%i", fe->dvb->num,fe->id); + if (IS_ERR(fe_thread)) { + ret = PTR_ERR(fe_thread); + dev_warn(fe->dvb->device, + "dvb_frontend_start: failed to start kthread (%d)\n", + ret); + up(&fepriv->sem); + return ret; + } + fepriv->thread = fe_thread; + return 0; +} + +static void dvb_frontend_get_frequency_limits(struct dvb_frontend *fe, + u32 *freq_min, u32 *freq_max) +{ + *freq_min = max(fe->ops.info.frequency_min, fe->ops.tuner_ops.info.frequency_min); + + if (fe->ops.info.frequency_max == 0) + *freq_max = fe->ops.tuner_ops.info.frequency_max; + else if (fe->ops.tuner_ops.info.frequency_max == 0) + *freq_max = fe->ops.info.frequency_max; + else + *freq_max = min(fe->ops.info.frequency_max, fe->ops.tuner_ops.info.frequency_max); + + if (*freq_min == 0 || *freq_max == 0) + dev_warn(fe->dvb->device, "DVB: adapter %i frontend %u frequency limits undefined - fix the driver\n", + fe->dvb->num, fe->id); +} + +static int dvb_frontend_check_parameters(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + u32 freq_min; + u32 freq_max; + + /* range check: frequency */ + dvb_frontend_get_frequency_limits(fe, &freq_min, &freq_max); + if ((freq_min && c->frequency < freq_min) || + (freq_max && c->frequency > freq_max)) { + dev_warn(fe->dvb->device, "DVB: adapter %i frontend %i frequency %u out of range (%u..%u)\n", + fe->dvb->num, fe->id, c->frequency, + freq_min, freq_max); + return -EINVAL; + } + + /* range check: symbol rate */ + switch (c->delivery_system) { + case SYS_DVBS: + case SYS_DVBS2: + case SYS_TURBO: + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + if ((fe->ops.info.symbol_rate_min && + c->symbol_rate < fe->ops.info.symbol_rate_min) || + (fe->ops.info.symbol_rate_max && + c->symbol_rate > fe->ops.info.symbol_rate_max)) { + dev_warn(fe->dvb->device, "DVB: adapter %i frontend %i symbol rate %u out of range (%u..%u)\n", + fe->dvb->num, fe->id, c->symbol_rate, + fe->ops.info.symbol_rate_min, + fe->ops.info.symbol_rate_max); + return -EINVAL; + } + default: + break; + } + + return 0; +} + +static int dvb_frontend_clear_cache(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int i; + u32 delsys; + + delsys = c->delivery_system; + memset(c, 0, offsetof(struct dtv_frontend_properties, strength)); + c->delivery_system = delsys; + + c->state = DTV_CLEAR; + + dev_dbg(fe->dvb->device, "%s: Clearing cache for delivery system %d\n", + __func__, c->delivery_system); + + c->transmission_mode = TRANSMISSION_MODE_AUTO; + c->bandwidth_hz = 0; /* AUTO */ + c->guard_interval = GUARD_INTERVAL_AUTO; + c->hierarchy = HIERARCHY_AUTO; + c->symbol_rate = 0; + c->code_rate_HP = FEC_AUTO; + c->code_rate_LP = FEC_AUTO; + c->fec_inner = FEC_AUTO; + c->rolloff = ROLLOFF_AUTO; + c->voltage = SEC_VOLTAGE_OFF; + c->sectone = SEC_TONE_OFF; + c->pilot = PILOT_AUTO; + + c->isdbt_partial_reception = 0; + c->isdbt_sb_mode = 0; + c->isdbt_sb_subchannel = 0; + c->isdbt_sb_segment_idx = 0; + c->isdbt_sb_segment_count = 0; + c->isdbt_layer_enabled = 0; + for (i = 0; i < 3; i++) { + c->layer[i].fec = FEC_AUTO; + c->layer[i].modulation = QAM_AUTO; + c->layer[i].interleaving = 0; + c->layer[i].segment_count = 0; + } + + c->stream_id = NO_STREAM_ID_FILTER; + + switch (c->delivery_system) { + case SYS_DVBS: + case SYS_DVBS2: + case SYS_TURBO: + c->modulation = QPSK; /* implied for DVB-S in legacy API */ + c->rolloff = ROLLOFF_35;/* implied for DVB-S */ + break; + case SYS_ATSC: + c->modulation = VSB_8; + break; + default: + c->modulation = QAM_AUTO; + break; + } + + c->lna = LNA_AUTO; + + return 0; +} + +#define _DTV_CMD(n, s, b) \ +[n] = { \ + .name = #n, \ + .cmd = n, \ + .set = s,\ + .buffer = b \ +} + +static struct dtv_cmds_h dtv_cmds[DTV_MAX_COMMAND + 1] = { + _DTV_CMD(DTV_TUNE, 1, 0), + _DTV_CMD(DTV_CLEAR, 1, 0), + + /* Set */ + _DTV_CMD(DTV_FREQUENCY, 1, 0), + _DTV_CMD(DTV_BANDWIDTH_HZ, 1, 0), + _DTV_CMD(DTV_MODULATION, 1, 0), + _DTV_CMD(DTV_INVERSION, 1, 0), + _DTV_CMD(DTV_DISEQC_MASTER, 1, 1), + _DTV_CMD(DTV_SYMBOL_RATE, 1, 0), + _DTV_CMD(DTV_INNER_FEC, 1, 0), + _DTV_CMD(DTV_VOLTAGE, 1, 0), + _DTV_CMD(DTV_TONE, 1, 0), + _DTV_CMD(DTV_PILOT, 1, 0), + _DTV_CMD(DTV_ROLLOFF, 1, 0), + _DTV_CMD(DTV_DELIVERY_SYSTEM, 1, 0), + _DTV_CMD(DTV_HIERARCHY, 1, 0), + _DTV_CMD(DTV_CODE_RATE_HP, 1, 0), + _DTV_CMD(DTV_CODE_RATE_LP, 1, 0), + _DTV_CMD(DTV_GUARD_INTERVAL, 1, 0), + _DTV_CMD(DTV_TRANSMISSION_MODE, 1, 0), + _DTV_CMD(DTV_INTERLEAVING, 1, 0), + + _DTV_CMD(DTV_ISDBT_PARTIAL_RECEPTION, 1, 0), + _DTV_CMD(DTV_ISDBT_SOUND_BROADCASTING, 1, 0), + _DTV_CMD(DTV_ISDBT_SB_SUBCHANNEL_ID, 1, 0), + _DTV_CMD(DTV_ISDBT_SB_SEGMENT_IDX, 1, 0), + _DTV_CMD(DTV_ISDBT_SB_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYER_ENABLED, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_FEC, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_MODULATION, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERA_TIME_INTERLEAVING, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_FEC, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_MODULATION, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERB_TIME_INTERLEAVING, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_FEC, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_MODULATION, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_SEGMENT_COUNT, 1, 0), + _DTV_CMD(DTV_ISDBT_LAYERC_TIME_INTERLEAVING, 1, 0), + + _DTV_CMD(DTV_STREAM_ID, 1, 0), + _DTV_CMD(DTV_DVBT2_PLP_ID_LEGACY, 1, 0), + _DTV_CMD(DTV_LNA, 1, 0), + + /* Get */ + _DTV_CMD(DTV_DISEQC_SLAVE_REPLY, 0, 1), + _DTV_CMD(DTV_API_VERSION, 0, 0), + + _DTV_CMD(DTV_ENUM_DELSYS, 0, 0), + + _DTV_CMD(DTV_ATSCMH_PARADE_ID, 1, 0), + _DTV_CMD(DTV_ATSCMH_RS_FRAME_ENSEMBLE, 1, 0), + + _DTV_CMD(DTV_ATSCMH_FIC_VER, 0, 0), + _DTV_CMD(DTV_ATSCMH_NOG, 0, 0), + _DTV_CMD(DTV_ATSCMH_TNOG, 0, 0), + _DTV_CMD(DTV_ATSCMH_SGN, 0, 0), + _DTV_CMD(DTV_ATSCMH_PRC, 0, 0), + _DTV_CMD(DTV_ATSCMH_RS_FRAME_MODE, 0, 0), + _DTV_CMD(DTV_ATSCMH_RS_CODE_MODE_PRI, 0, 0), + _DTV_CMD(DTV_ATSCMH_RS_CODE_MODE_SEC, 0, 0), + _DTV_CMD(DTV_ATSCMH_SCCC_BLOCK_MODE, 0, 0), + _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_A, 0, 0), + _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_B, 0, 0), + _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_C, 0, 0), + _DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_D, 0, 0), + + /* Statistics API */ + _DTV_CMD(DTV_STAT_SIGNAL_STRENGTH, 0, 0), + _DTV_CMD(DTV_STAT_CNR, 0, 0), + _DTV_CMD(DTV_STAT_PRE_ERROR_BIT_COUNT, 0, 0), + _DTV_CMD(DTV_STAT_PRE_TOTAL_BIT_COUNT, 0, 0), + _DTV_CMD(DTV_STAT_POST_ERROR_BIT_COUNT, 0, 0), + _DTV_CMD(DTV_STAT_POST_TOTAL_BIT_COUNT, 0, 0), + _DTV_CMD(DTV_STAT_ERROR_BLOCK_COUNT, 0, 0), + _DTV_CMD(DTV_STAT_TOTAL_BLOCK_COUNT, 0, 0), +}; + +static void dtv_property_dump(struct dvb_frontend *fe, struct dtv_property *tvp) +{ + int i; + + if (tvp->cmd <= 0 || tvp->cmd > DTV_MAX_COMMAND) { + dev_warn(fe->dvb->device, "%s: tvp.cmd = 0x%08x undefined\n", + __func__, tvp->cmd); + return; + } + + dev_dbg(fe->dvb->device, "%s: tvp.cmd = 0x%08x (%s)\n", __func__, + tvp->cmd, dtv_cmds[tvp->cmd].name); + + if (dtv_cmds[tvp->cmd].buffer) { + dev_dbg(fe->dvb->device, "%s: tvp.u.buffer.len = 0x%02x\n", + __func__, tvp->u.buffer.len); + + for(i = 0; i < tvp->u.buffer.len; i++) + dev_dbg(fe->dvb->device, + "%s: tvp.u.buffer.data[0x%02x] = 0x%02x\n", + __func__, i, tvp->u.buffer.data[i]); + } else { + dev_dbg(fe->dvb->device, "%s: tvp.u.data = 0x%08x\n", __func__, + tvp->u.data); + } +} + +/* Synchronise the legacy tuning parameters into the cache, so that demodulator + * drivers can use a single set_frontend tuning function, regardless of whether + * it's being used for the legacy or new API, reducing code and complexity. + */ +static int dtv_property_cache_sync(struct dvb_frontend *fe, + struct dtv_frontend_properties *c, + const struct dvb_frontend_parameters *p) +{ + c->frequency = p->frequency; + c->inversion = p->inversion; + + switch (dvbv3_type(c->delivery_system)) { + case DVBV3_QPSK: + dev_dbg(fe->dvb->device, "%s: Preparing QPSK req\n", __func__); + c->symbol_rate = p->u.qpsk.symbol_rate; + c->fec_inner = p->u.qpsk.fec_inner; + break; + case DVBV3_QAM: + dev_dbg(fe->dvb->device, "%s: Preparing QAM req\n", __func__); + c->symbol_rate = p->u.qam.symbol_rate; + c->fec_inner = p->u.qam.fec_inner; + c->modulation = p->u.qam.modulation; + break; + case DVBV3_OFDM: + dev_dbg(fe->dvb->device, "%s: Preparing OFDM req\n", __func__); + + switch (p->u.ofdm.bandwidth) { + case BANDWIDTH_10_MHZ: + c->bandwidth_hz = 10000000; + break; + case BANDWIDTH_8_MHZ: + c->bandwidth_hz = 8000000; + break; + case BANDWIDTH_7_MHZ: + c->bandwidth_hz = 7000000; + break; + case BANDWIDTH_6_MHZ: + c->bandwidth_hz = 6000000; + break; + case BANDWIDTH_5_MHZ: + c->bandwidth_hz = 5000000; + break; + case BANDWIDTH_1_712_MHZ: + c->bandwidth_hz = 1712000; + break; + case BANDWIDTH_AUTO: + c->bandwidth_hz = 0; + } + + c->code_rate_HP = p->u.ofdm.code_rate_HP; + c->code_rate_LP = p->u.ofdm.code_rate_LP; + c->modulation = p->u.ofdm.constellation; + c->transmission_mode = p->u.ofdm.transmission_mode; + c->guard_interval = p->u.ofdm.guard_interval; + c->hierarchy = p->u.ofdm.hierarchy_information; + break; + case DVBV3_ATSC: + dev_dbg(fe->dvb->device, "%s: Preparing ATSC req\n", __func__); + c->modulation = p->u.vsb.modulation; + if (c->delivery_system == SYS_ATSCMH) + break; + if ((c->modulation == VSB_8) || (c->modulation == VSB_16)) + c->delivery_system = SYS_ATSC; + else + c->delivery_system = SYS_DVBC_ANNEX_B; + break; + case DVBV3_UNKNOWN: + dev_err(fe->dvb->device, + "%s: doesn't know how to handle a DVBv3 call to delivery system %i\n", + __func__, c->delivery_system); + return -EINVAL; + } + + return 0; +} + +/* Ensure the cached values are set correctly in the frontend + * legacy tuning structures, for the advanced tuning API. + */ +static int dtv_property_legacy_params_sync(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + const struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + p->frequency = c->frequency; + p->inversion = c->inversion; + + switch (dvbv3_type(c->delivery_system)) { + case DVBV3_UNKNOWN: + dev_err(fe->dvb->device, + "%s: doesn't know how to handle a DVBv3 call to delivery system %i\n", + __func__, c->delivery_system); + return -EINVAL; + case DVBV3_QPSK: + dev_dbg(fe->dvb->device, "%s: Preparing QPSK req\n", __func__); + p->u.qpsk.symbol_rate = c->symbol_rate; + p->u.qpsk.fec_inner = c->fec_inner; + break; + case DVBV3_QAM: + dev_dbg(fe->dvb->device, "%s: Preparing QAM req\n", __func__); + p->u.qam.symbol_rate = c->symbol_rate; + p->u.qam.fec_inner = c->fec_inner; + p->u.qam.modulation = c->modulation; + break; + case DVBV3_OFDM: + dev_dbg(fe->dvb->device, "%s: Preparing OFDM req\n", __func__); + switch (c->bandwidth_hz) { + case 10000000: + p->u.ofdm.bandwidth = BANDWIDTH_10_MHZ; + break; + case 8000000: + p->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; + break; + case 7000000: + p->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; + break; + case 6000000: + p->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; + break; + case 5000000: + p->u.ofdm.bandwidth = BANDWIDTH_5_MHZ; + break; + case 1712000: + p->u.ofdm.bandwidth = BANDWIDTH_1_712_MHZ; + break; + case 0: + default: + p->u.ofdm.bandwidth = BANDWIDTH_AUTO; + } + p->u.ofdm.code_rate_HP = c->code_rate_HP; + p->u.ofdm.code_rate_LP = c->code_rate_LP; + p->u.ofdm.constellation = c->modulation; + p->u.ofdm.transmission_mode = c->transmission_mode; + p->u.ofdm.guard_interval = c->guard_interval; + p->u.ofdm.hierarchy_information = c->hierarchy; + break; + case DVBV3_ATSC: + dev_dbg(fe->dvb->device, "%s: Preparing VSB req\n", __func__); + p->u.vsb.modulation = c->modulation; + break; + } + return 0; +} + +/** + * dtv_get_frontend - calls a callback for retrieving DTV parameters + * @fe: struct dvb_frontend pointer + * @c: struct dtv_frontend_properties pointer (DVBv5 cache) + * @p_out struct dvb_frontend_parameters pointer (DVBv3 FE struct) + * + * This routine calls either the DVBv3 or DVBv5 get_frontend call. + * If c is not null, it will update the DVBv5 cache struct pointed by it. + * If p_out is not null, it will update the DVBv3 params pointed by it. + */ +static int dtv_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p_out) +{ + int r; + + if (fe->ops.get_frontend) { + r = fe->ops.get_frontend(fe); + if (unlikely(r < 0)) + return r; + if (p_out) + dtv_property_legacy_params_sync(fe, p_out); + return 0; + } + + /* As everything is in cache, get_frontend fops are always supported */ + return 0; +} + +static int dvb_frontend_ioctl_legacy(struct file *file, + unsigned int cmd, void *parg); +static int dvb_frontend_ioctl_properties(struct file *file, + unsigned int cmd, void *parg); + +static int dtv_property_process_get(struct dvb_frontend *fe, + const struct dtv_frontend_properties *c, + struct dtv_property *tvp, + struct file *file) +{ + int r, ncaps; + + switch(tvp->cmd) { + case DTV_ENUM_DELSYS: + ncaps = 0; + while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + tvp->u.buffer.data[ncaps] = fe->ops.delsys[ncaps]; + ncaps++; + } + tvp->u.buffer.len = ncaps; + break; + case DTV_FREQUENCY: + tvp->u.data = c->frequency; + break; + case DTV_MODULATION: + tvp->u.data = c->modulation; + break; + case DTV_BANDWIDTH_HZ: + tvp->u.data = c->bandwidth_hz; + break; + case DTV_INVERSION: + tvp->u.data = c->inversion; + break; + case DTV_SYMBOL_RATE: + tvp->u.data = c->symbol_rate; + break; + case DTV_INNER_FEC: + tvp->u.data = c->fec_inner; + break; + case DTV_PILOT: + tvp->u.data = c->pilot; + break; + case DTV_ROLLOFF: + tvp->u.data = c->rolloff; + break; + case DTV_DELIVERY_SYSTEM: + tvp->u.data = c->delivery_system; + break; + case DTV_VOLTAGE: + tvp->u.data = c->voltage; + break; + case DTV_TONE: + tvp->u.data = c->sectone; + break; + case DTV_API_VERSION: + tvp->u.data = (DVB_API_VERSION << 8) | DVB_API_VERSION_MINOR; + break; + case DTV_CODE_RATE_HP: + tvp->u.data = c->code_rate_HP; + break; + case DTV_CODE_RATE_LP: + tvp->u.data = c->code_rate_LP; + break; + case DTV_GUARD_INTERVAL: + tvp->u.data = c->guard_interval; + break; + case DTV_TRANSMISSION_MODE: + tvp->u.data = c->transmission_mode; + break; + case DTV_HIERARCHY: + tvp->u.data = c->hierarchy; + break; + case DTV_INTERLEAVING: + tvp->u.data = c->interleaving; + break; + + /* ISDB-T Support here */ + case DTV_ISDBT_PARTIAL_RECEPTION: + tvp->u.data = c->isdbt_partial_reception; + break; + case DTV_ISDBT_SOUND_BROADCASTING: + tvp->u.data = c->isdbt_sb_mode; + break; + case DTV_ISDBT_SB_SUBCHANNEL_ID: + tvp->u.data = c->isdbt_sb_subchannel; + break; + case DTV_ISDBT_SB_SEGMENT_IDX: + tvp->u.data = c->isdbt_sb_segment_idx; + break; + case DTV_ISDBT_SB_SEGMENT_COUNT: + tvp->u.data = c->isdbt_sb_segment_count; + break; + case DTV_ISDBT_LAYER_ENABLED: + tvp->u.data = c->isdbt_layer_enabled; + break; + case DTV_ISDBT_LAYERA_FEC: + tvp->u.data = c->layer[0].fec; + break; + case DTV_ISDBT_LAYERA_MODULATION: + tvp->u.data = c->layer[0].modulation; + break; + case DTV_ISDBT_LAYERA_SEGMENT_COUNT: + tvp->u.data = c->layer[0].segment_count; + break; + case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: + tvp->u.data = c->layer[0].interleaving; + break; + case DTV_ISDBT_LAYERB_FEC: + tvp->u.data = c->layer[1].fec; + break; + case DTV_ISDBT_LAYERB_MODULATION: + tvp->u.data = c->layer[1].modulation; + break; + case DTV_ISDBT_LAYERB_SEGMENT_COUNT: + tvp->u.data = c->layer[1].segment_count; + break; + case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: + tvp->u.data = c->layer[1].interleaving; + break; + case DTV_ISDBT_LAYERC_FEC: + tvp->u.data = c->layer[2].fec; + break; + case DTV_ISDBT_LAYERC_MODULATION: + tvp->u.data = c->layer[2].modulation; + break; + case DTV_ISDBT_LAYERC_SEGMENT_COUNT: + tvp->u.data = c->layer[2].segment_count; + break; + case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: + tvp->u.data = c->layer[2].interleaving; + break; + + /* Multistream support */ + case DTV_STREAM_ID: + case DTV_DVBT2_PLP_ID_LEGACY: + tvp->u.data = c->stream_id; + break; + + /* ATSC-MH */ + case DTV_ATSCMH_FIC_VER: + tvp->u.data = fe->dtv_property_cache.atscmh_fic_ver; + break; + case DTV_ATSCMH_PARADE_ID: + tvp->u.data = fe->dtv_property_cache.atscmh_parade_id; + break; + case DTV_ATSCMH_NOG: + tvp->u.data = fe->dtv_property_cache.atscmh_nog; + break; + case DTV_ATSCMH_TNOG: + tvp->u.data = fe->dtv_property_cache.atscmh_tnog; + break; + case DTV_ATSCMH_SGN: + tvp->u.data = fe->dtv_property_cache.atscmh_sgn; + break; + case DTV_ATSCMH_PRC: + tvp->u.data = fe->dtv_property_cache.atscmh_prc; + break; + case DTV_ATSCMH_RS_FRAME_MODE: + tvp->u.data = fe->dtv_property_cache.atscmh_rs_frame_mode; + break; + case DTV_ATSCMH_RS_FRAME_ENSEMBLE: + tvp->u.data = fe->dtv_property_cache.atscmh_rs_frame_ensemble; + break; + case DTV_ATSCMH_RS_CODE_MODE_PRI: + tvp->u.data = fe->dtv_property_cache.atscmh_rs_code_mode_pri; + break; + case DTV_ATSCMH_RS_CODE_MODE_SEC: + tvp->u.data = fe->dtv_property_cache.atscmh_rs_code_mode_sec; + break; + case DTV_ATSCMH_SCCC_BLOCK_MODE: + tvp->u.data = fe->dtv_property_cache.atscmh_sccc_block_mode; + break; + case DTV_ATSCMH_SCCC_CODE_MODE_A: + tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_a; + break; + case DTV_ATSCMH_SCCC_CODE_MODE_B: + tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_b; + break; + case DTV_ATSCMH_SCCC_CODE_MODE_C: + tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_c; + break; + case DTV_ATSCMH_SCCC_CODE_MODE_D: + tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_d; + break; + + case DTV_LNA: + tvp->u.data = c->lna; + break; + + /* Fill quality measures */ + case DTV_STAT_SIGNAL_STRENGTH: + tvp->u.st = c->strength; + break; + case DTV_STAT_CNR: + tvp->u.st = c->cnr; + break; + case DTV_STAT_PRE_ERROR_BIT_COUNT: + tvp->u.st = c->pre_bit_error; + break; + case DTV_STAT_PRE_TOTAL_BIT_COUNT: + tvp->u.st = c->pre_bit_count; + break; + case DTV_STAT_POST_ERROR_BIT_COUNT: + tvp->u.st = c->post_bit_error; + break; + case DTV_STAT_POST_TOTAL_BIT_COUNT: + tvp->u.st = c->post_bit_count; + break; + case DTV_STAT_ERROR_BLOCK_COUNT: + tvp->u.st = c->block_error; + break; + case DTV_STAT_TOTAL_BLOCK_COUNT: + tvp->u.st = c->block_count; + break; + default: + dev_dbg(fe->dvb->device, + "%s: FE property %d doesn't exist\n", + __func__, tvp->cmd); + return -EINVAL; + } + + /* Allow the frontend to override outgoing properties */ + if (fe->ops.get_property) { + r = fe->ops.get_property(fe, tvp); + if (r < 0) + return r; + } + + dtv_property_dump(fe, tvp); + + return 0; +} + +static int dtv_set_frontend(struct dvb_frontend *fe); + +static bool is_dvbv3_delsys(u32 delsys) +{ + bool status; + + status = (delsys == SYS_DVBT) || (delsys == SYS_DVBC_ANNEX_A) || + (delsys == SYS_DVBS) || (delsys == SYS_ATSC); + + return status; +} + +/** + * emulate_delivery_system - emulate a DVBv5 delivery system with a DVBv3 type + * @fe: struct frontend; + * @delsys: DVBv5 type that will be used for emulation + * + * Provides emulation for delivery systems that are compatible with the old + * DVBv3 call. Among its usages, it provices support for ISDB-T, and allows + * using a DVB-S2 only frontend just like it were a DVB-S, if the frontent + * parameters are compatible with DVB-S spec. + */ +static int emulate_delivery_system(struct dvb_frontend *fe, u32 delsys) +{ + int i; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + c->delivery_system = delsys; + + /* + * If the call is for ISDB-T, put it into full-seg, auto mode, TV + */ + if (c->delivery_system == SYS_ISDBT) { + dev_dbg(fe->dvb->device, + "%s: Using defaults for SYS_ISDBT\n", + __func__); + + if (!c->bandwidth_hz) + c->bandwidth_hz = 6000000; + + c->isdbt_partial_reception = 0; + c->isdbt_sb_mode = 0; + c->isdbt_sb_subchannel = 0; + c->isdbt_sb_segment_idx = 0; + c->isdbt_sb_segment_count = 0; + c->isdbt_layer_enabled = 7; + for (i = 0; i < 3; i++) { + c->layer[i].fec = FEC_AUTO; + c->layer[i].modulation = QAM_AUTO; + c->layer[i].interleaving = 0; + c->layer[i].segment_count = 0; + } + } + dev_dbg(fe->dvb->device, "%s: change delivery system on cache to %d\n", + __func__, c->delivery_system); + + return 0; +} + +/** + * dvbv5_set_delivery_system - Sets the delivery system for a DVBv5 API call + * @fe: frontend struct + * @desired_system: delivery system requested by the user + * + * A DVBv5 call know what's the desired system it wants. So, set it. + * + * There are, however, a few known issues with early DVBv5 applications that + * are also handled by this logic: + * + * 1) Some early apps use SYS_UNDEFINED as the desired delivery system. + * This is an API violation, but, as we don't want to break userspace, + * convert it to the first supported delivery system. + * 2) Some apps might be using a DVBv5 call in a wrong way, passing, for + * example, SYS_DVBT instead of SYS_ISDBT. This is because early usage of + * ISDB-T provided backward compat with DVB-T. + */ +static int dvbv5_set_delivery_system(struct dvb_frontend *fe, + u32 desired_system) +{ + int ncaps; + u32 delsys = SYS_UNDEFINED; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + enum dvbv3_emulation_type type; + + /* + * It was reported that some old DVBv5 applications were + * filling delivery_system with SYS_UNDEFINED. If this happens, + * assume that the application wants to use the first supported + * delivery system. + */ + if (desired_system == SYS_UNDEFINED) + desired_system = fe->ops.delsys[0]; + + /* + * This is a DVBv5 call. So, it likely knows the supported + * delivery systems. So, check if the desired delivery system is + * supported + */ + ncaps = 0; + while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + if (fe->ops.delsys[ncaps] == desired_system) { + c->delivery_system = desired_system; + dev_dbg(fe->dvb->device, + "%s: Changing delivery system to %d\n", + __func__, desired_system); + return 0; + } + ncaps++; + } + + /* + * The requested delivery system isn't supported. Maybe userspace + * is requesting a DVBv3 compatible delivery system. + * + * The emulation only works if the desired system is one of the + * delivery systems supported by DVBv3 API + */ + if (!is_dvbv3_delsys(desired_system)) { + dev_dbg(fe->dvb->device, + "%s: Delivery system %d not supported.\n", + __func__, desired_system); + return -EINVAL; + } + + type = dvbv3_type(desired_system); + + /* + * Get the last non-DVBv3 delivery system that has the same type + * of the desired system + */ + ncaps = 0; + while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + if (dvbv3_type(fe->ops.delsys[ncaps]) == type) + delsys = fe->ops.delsys[ncaps]; + ncaps++; + } + + /* There's nothing compatible with the desired delivery system */ + if (delsys == SYS_UNDEFINED) { + dev_dbg(fe->dvb->device, + "%s: Delivery system %d not supported on emulation mode.\n", + __func__, desired_system); + return -EINVAL; + } + + dev_dbg(fe->dvb->device, + "%s: Using delivery system %d emulated as if it were %d\n", + __func__, delsys, desired_system); + + return emulate_delivery_system(fe, desired_system); +} + +/** + * dvbv3_set_delivery_system - Sets the delivery system for a DVBv3 API call + * @fe: frontend struct + * + * A DVBv3 call doesn't know what's the desired system it wants. It also + * doesn't allow to switch between different types. Due to that, userspace + * should use DVBv5 instead. + * However, in order to avoid breaking userspace API, limited backward + * compatibility support is provided. + * + * There are some delivery systems that are incompatible with DVBv3 calls. + * + * This routine should work fine for frontends that support just one delivery + * system. + * + * For frontends that support multiple frontends: + * 1) It defaults to use the first supported delivery system. There's an + * userspace application that allows changing it at runtime; + * + * 2) If the current delivery system is not compatible with DVBv3, it gets + * the first one that it is compatible. + * + * NOTE: in order for this to work with applications like Kaffeine that + * uses a DVBv5 call for DVB-S2 and a DVBv3 call to go back to + * DVB-S, drivers that support both DVB-S and DVB-S2 should have the + * SYS_DVBS entry before the SYS_DVBS2, otherwise it won't switch back + * to DVB-S. + */ +static int dvbv3_set_delivery_system(struct dvb_frontend *fe) +{ + int ncaps; + u32 delsys = SYS_UNDEFINED; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + /* If not set yet, defaults to the first supported delivery system */ + if (c->delivery_system == SYS_UNDEFINED) + c->delivery_system = fe->ops.delsys[0]; + + /* + * Trivial case: just use the current one, if it already a DVBv3 + * delivery system + */ + if (is_dvbv3_delsys(c->delivery_system)) { + dev_dbg(fe->dvb->device, + "%s: Using delivery system to %d\n", + __func__, c->delivery_system); + return 0; + } + + /* + * Seek for the first delivery system that it is compatible with a + * DVBv3 standard + */ + ncaps = 0; + while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { + if (dvbv3_type(fe->ops.delsys[ncaps]) != DVBV3_UNKNOWN) { + delsys = fe->ops.delsys[ncaps]; + break; + } + ncaps++; + } + if (delsys == SYS_UNDEFINED) { + dev_dbg(fe->dvb->device, + "%s: Couldn't find a delivery system that works with FE_SET_FRONTEND\n", + __func__); + return -EINVAL; + } + return emulate_delivery_system(fe, delsys); +} + +static int dtv_property_process_set(struct dvb_frontend *fe, + struct dtv_property *tvp, + struct file *file) +{ + int r = 0; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + /* Allow the frontend to validate incoming properties */ + if (fe->ops.set_property) { + r = fe->ops.set_property(fe, tvp); + if (r < 0) + return r; + } + + switch(tvp->cmd) { + case DTV_CLEAR: + /* + * Reset a cache of data specific to the frontend here. This does + * not effect hardware. + */ + dvb_frontend_clear_cache(fe); + break; + case DTV_TUNE: + /* interpret the cache of data, build either a traditional frontend + * tunerequest so we can pass validation in the FE_SET_FRONTEND + * ioctl. + */ + c->state = tvp->cmd; + dev_dbg(fe->dvb->device, "%s: Finalised property cache\n", + __func__); + + r = dtv_set_frontend(fe); + break; + case DTV_FREQUENCY: + c->frequency = tvp->u.data; + break; + case DTV_MODULATION: + c->modulation = tvp->u.data; + break; + case DTV_BANDWIDTH_HZ: + c->bandwidth_hz = tvp->u.data; + break; + case DTV_INVERSION: + c->inversion = tvp->u.data; + break; + case DTV_SYMBOL_RATE: + c->symbol_rate = tvp->u.data; + break; + case DTV_INNER_FEC: + c->fec_inner = tvp->u.data; + break; + case DTV_PILOT: + c->pilot = tvp->u.data; + break; + case DTV_ROLLOFF: + c->rolloff = tvp->u.data; + break; + case DTV_DELIVERY_SYSTEM: + r = dvbv5_set_delivery_system(fe, tvp->u.data); + break; + case DTV_VOLTAGE: + c->voltage = tvp->u.data; + r = dvb_frontend_ioctl_legacy(file, FE_SET_VOLTAGE, + (void *)c->voltage); + break; + case DTV_TONE: + c->sectone = tvp->u.data; + r = dvb_frontend_ioctl_legacy(file, FE_SET_TONE, + (void *)c->sectone); + break; + case DTV_CODE_RATE_HP: + c->code_rate_HP = tvp->u.data; + break; + case DTV_CODE_RATE_LP: + c->code_rate_LP = tvp->u.data; + break; + case DTV_GUARD_INTERVAL: + c->guard_interval = tvp->u.data; + break; + case DTV_TRANSMISSION_MODE: + c->transmission_mode = tvp->u.data; + break; + case DTV_HIERARCHY: + c->hierarchy = tvp->u.data; + break; + case DTV_INTERLEAVING: + c->interleaving = tvp->u.data; + break; + + /* ISDB-T Support here */ + case DTV_ISDBT_PARTIAL_RECEPTION: + c->isdbt_partial_reception = tvp->u.data; + break; + case DTV_ISDBT_SOUND_BROADCASTING: + c->isdbt_sb_mode = tvp->u.data; + break; + case DTV_ISDBT_SB_SUBCHANNEL_ID: + c->isdbt_sb_subchannel = tvp->u.data; + break; + case DTV_ISDBT_SB_SEGMENT_IDX: + c->isdbt_sb_segment_idx = tvp->u.data; + break; + case DTV_ISDBT_SB_SEGMENT_COUNT: + c->isdbt_sb_segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYER_ENABLED: + c->isdbt_layer_enabled = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_FEC: + c->layer[0].fec = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_MODULATION: + c->layer[0].modulation = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_SEGMENT_COUNT: + c->layer[0].segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: + c->layer[0].interleaving = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_FEC: + c->layer[1].fec = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_MODULATION: + c->layer[1].modulation = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_SEGMENT_COUNT: + c->layer[1].segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: + c->layer[1].interleaving = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_FEC: + c->layer[2].fec = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_MODULATION: + c->layer[2].modulation = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_SEGMENT_COUNT: + c->layer[2].segment_count = tvp->u.data; + break; + case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: + c->layer[2].interleaving = tvp->u.data; + break; + + /* Multistream support */ + case DTV_STREAM_ID: + case DTV_DVBT2_PLP_ID_LEGACY: + c->stream_id = tvp->u.data; + break; + + /* ATSC-MH */ + case DTV_ATSCMH_PARADE_ID: + fe->dtv_property_cache.atscmh_parade_id = tvp->u.data; + break; + case DTV_ATSCMH_RS_FRAME_ENSEMBLE: + fe->dtv_property_cache.atscmh_rs_frame_ensemble = tvp->u.data; + break; + + case DTV_LNA: + c->lna = tvp->u.data; + if (fe->ops.set_lna) + r = fe->ops.set_lna(fe); + break; + + default: + return -EINVAL; + } + + return r; +} + +static int dvb_frontend_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_frontend *fe = dvbdev->priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + int err = -EOPNOTSUPP; + + dev_dbg(fe->dvb->device, "%s: (%d)\n", __func__, _IOC_NR(cmd)); + if (down_interruptible(&fepriv->sem)) + return -ERESTARTSYS; + + if (fepriv->exit != DVB_FE_NO_EXIT) { + up(&fepriv->sem); + return -ENODEV; + } + + if ((file->f_flags & O_ACCMODE) == O_RDONLY && + (_IOC_DIR(cmd) != _IOC_READ || cmd == FE_GET_EVENT || + cmd == FE_DISEQC_RECV_SLAVE_REPLY)) { + up(&fepriv->sem); + return -EPERM; + } + + if ((cmd == FE_SET_PROPERTY) || (cmd == FE_GET_PROPERTY)) + err = dvb_frontend_ioctl_properties(file, cmd, parg); + else { + c->state = DTV_UNDEFINED; + err = dvb_frontend_ioctl_legacy(file, cmd, parg); + } + + up(&fepriv->sem); + return err; +} + +static int dvb_frontend_ioctl_properties(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_frontend *fe = dvbdev->priv; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int err = 0; + + struct dtv_properties *tvps = NULL; + struct dtv_property *tvp = NULL; + int i; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + if(cmd == FE_SET_PROPERTY) { + tvps = (struct dtv_properties __user *)parg; + + dev_dbg(fe->dvb->device, "%s: properties.num = %d\n", __func__, tvps->num); + dev_dbg(fe->dvb->device, "%s: properties.props = %p\n", __func__, tvps->props); + + /* Put an arbitrary limit on the number of messages that can + * be sent at once */ + if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS)) + return -EINVAL; + + tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL); + if (!tvp) { + err = -ENOMEM; + goto out; + } + + if (copy_from_user(tvp, tvps->props, tvps->num * sizeof(struct dtv_property))) { + err = -EFAULT; + goto out; + } + + for (i = 0; i < tvps->num; i++) { + err = dtv_property_process_set(fe, tvp + i, file); + if (err < 0) + goto out; + (tvp + i)->result = err; + } + + if (c->state == DTV_TUNE) + dev_dbg(fe->dvb->device, "%s: Property cache is full, tuning\n", __func__); + + } else + if(cmd == FE_GET_PROPERTY) { + tvps = (struct dtv_properties __user *)parg; + + dev_dbg(fe->dvb->device, "%s: properties.num = %d\n", __func__, tvps->num); + dev_dbg(fe->dvb->device, "%s: properties.props = %p\n", __func__, tvps->props); + + /* Put an arbitrary limit on the number of messages that can + * be sent at once */ + if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS)) + return -EINVAL; + + tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL); + if (!tvp) { + err = -ENOMEM; + goto out; + } + + if (copy_from_user(tvp, tvps->props, tvps->num * sizeof(struct dtv_property))) { + err = -EFAULT; + goto out; + } + + /* + * Fills the cache out struct with the cache contents, plus + * the data retrieved from get_frontend, if the frontend + * is not idle. Otherwise, returns the cached content + */ + if (fepriv->state != FESTATE_IDLE) { + err = dtv_get_frontend(fe, NULL); + if (err < 0) + goto out; + } + for (i = 0; i < tvps->num; i++) { + err = dtv_property_process_get(fe, c, tvp + i, file); + if (err < 0) + goto out; + (tvp + i)->result = err; + } + + if (copy_to_user(tvps->props, tvp, tvps->num * sizeof(struct dtv_property))) { + err = -EFAULT; + goto out; + } + + } else + err = -EOPNOTSUPP; + +out: + kfree(tvp); + return err; +} + +static int dtv_set_frontend(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct dvb_frontend_tune_settings fetunesettings; + u32 rolloff = 0; + + if (dvb_frontend_check_parameters(fe) < 0) + return -EINVAL; + + /* + * Initialize output parameters to match the values given by + * the user. FE_SET_FRONTEND triggers an initial frontend event + * with status = 0, which copies output parameters to userspace. + */ + dtv_property_legacy_params_sync(fe, &fepriv->parameters_out); + + /* + * Be sure that the bandwidth will be filled for all + * non-satellite systems, as tuners need to know what + * low pass/Nyquist half filter should be applied, in + * order to avoid inter-channel noise. + * + * ISDB-T and DVB-T/T2 already sets bandwidth. + * ATSC and DVB-C don't set, so, the core should fill it. + * + * On DVB-C Annex A and C, the bandwidth is a function of + * the roll-off and symbol rate. Annex B defines different + * roll-off factors depending on the modulation. Fortunately, + * Annex B is only used with 6MHz, so there's no need to + * calculate it. + * + * While not officially supported, a side effect of handling it at + * the cache level is that a program could retrieve the bandwidth + * via DTV_BANDWIDTH_HZ, which may be useful for test programs. + */ + switch (c->delivery_system) { + case SYS_ATSC: + case SYS_DVBC_ANNEX_B: + c->bandwidth_hz = 6000000; + break; + case SYS_DVBC_ANNEX_A: + rolloff = 115; + break; + case SYS_DVBC_ANNEX_C: + rolloff = 113; + break; + default: + break; + } + if (rolloff) + c->bandwidth_hz = (c->symbol_rate * rolloff) / 100; + + /* force auto frequency inversion if requested */ + if (dvb_force_auto_inversion) + c->inversion = INVERSION_AUTO; + + /* + * without hierarchical coding code_rate_LP is irrelevant, + * so we tolerate the otherwise invalid FEC_NONE setting + */ + if (c->hierarchy == HIERARCHY_NONE && c->code_rate_LP == FEC_NONE) + c->code_rate_LP = FEC_AUTO; + + /* get frontend-specific tuning settings */ + memset(&fetunesettings, 0, sizeof(struct dvb_frontend_tune_settings)); + if (fe->ops.get_tune_settings && (fe->ops.get_tune_settings(fe, &fetunesettings) == 0)) { + fepriv->min_delay = (fetunesettings.min_delay_ms * HZ) / 1000; + fepriv->max_drift = fetunesettings.max_drift; + fepriv->step_size = fetunesettings.step_size; + } else { + /* default values */ + switch (c->delivery_system) { + case SYS_DVBS: + case SYS_DVBS2: + case SYS_ISDBS: + case SYS_TURBO: + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + fepriv->min_delay = HZ / 20; + fepriv->step_size = c->symbol_rate / 16000; + fepriv->max_drift = c->symbol_rate / 2000; + break; + case SYS_DVBT: + case SYS_DVBT2: + case SYS_ISDBT: + case SYS_DTMB: + fepriv->min_delay = HZ / 20; + fepriv->step_size = fe->ops.info.frequency_stepsize * 2; + fepriv->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1; + break; + default: + /* + * FIXME: This sounds wrong! if freqency_stepsize is + * defined by the frontend, why not use it??? + */ + fepriv->min_delay = HZ / 20; + fepriv->step_size = 0; /* no zigzag */ + fepriv->max_drift = 0; + break; + } + } + if (dvb_override_tune_delay > 0) + fepriv->min_delay = (dvb_override_tune_delay * HZ) / 1000; + + fepriv->state = FESTATE_RETUNE; + + /* Request the search algorithm to search */ + fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; + + dvb_frontend_clear_events(fe); + dvb_frontend_add_event(fe, 0); + dvb_frontend_wakeup(fe); + fepriv->status = 0; + + return 0; +} + + +static int dvb_frontend_ioctl_legacy(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_frontend *fe = dvbdev->priv; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int err = -EOPNOTSUPP; + + switch (cmd) { + case FE_GET_INFO: { + struct dvb_frontend_info* info = parg; + + memcpy(info, &fe->ops.info, sizeof(struct dvb_frontend_info)); + dvb_frontend_get_frequency_limits(fe, &info->frequency_min, &info->frequency_max); + + /* + * Associate the 4 delivery systems supported by DVBv3 + * API with their DVBv5 counterpart. For the other standards, + * use the closest type, assuming that it would hopefully + * work with a DVBv3 application. + * It should be noticed that, on multi-frontend devices with + * different types (terrestrial and cable, for example), + * a pure DVBv3 application won't be able to use all delivery + * systems. Yet, changing the DVBv5 cache to the other delivery + * system should be enough for making it work. + */ + switch (dvbv3_type(c->delivery_system)) { + case DVBV3_QPSK: + info->type = FE_QPSK; + break; + case DVBV3_ATSC: + info->type = FE_ATSC; + break; + case DVBV3_QAM: + info->type = FE_QAM; + break; + case DVBV3_OFDM: + info->type = FE_OFDM; + break; + default: + dev_err(fe->dvb->device, + "%s: doesn't know how to handle a DVBv3 call to delivery system %i\n", + __func__, c->delivery_system); + fe->ops.info.type = FE_OFDM; + } + dev_dbg(fe->dvb->device, "%s: current delivery system on cache: %d, V3 type: %d\n", + __func__, c->delivery_system, fe->ops.info.type); + + /* Force the CAN_INVERSION_AUTO bit on. If the frontend doesn't + * do it, it is done for it. */ + info->caps |= FE_CAN_INVERSION_AUTO; + err = 0; + break; + } + + case FE_READ_STATUS: { + fe_status_t* status = parg; + + /* if retune was requested but hasn't occurred yet, prevent + * that user get signal state from previous tuning */ + if (fepriv->state == FESTATE_RETUNE || + fepriv->state == FESTATE_ERROR) { + err=0; + *status = 0; + break; + } + + if (fe->ops.read_status) + err = fe->ops.read_status(fe, status); + break; + } + + case FE_READ_BER: + if (fe->ops.read_ber) { + if (fepriv->thread) + err = fe->ops.read_ber(fe, (__u32 *) parg); + else + err = -EAGAIN; + } + break; + + case FE_READ_SIGNAL_STRENGTH: + if (fe->ops.read_signal_strength) { + if (fepriv->thread) + err = fe->ops.read_signal_strength(fe, (__u16 *) parg); + else + err = -EAGAIN; + } + break; + + case FE_READ_SNR: + if (fe->ops.read_snr) { + if (fepriv->thread) + err = fe->ops.read_snr(fe, (__u16 *) parg); + else + err = -EAGAIN; + } + break; + + case FE_READ_UNCORRECTED_BLOCKS: + if (fe->ops.read_ucblocks) { + if (fepriv->thread) + err = fe->ops.read_ucblocks(fe, (__u32 *) parg); + else + err = -EAGAIN; + } + break; + + case FE_DISEQC_RESET_OVERLOAD: + if (fe->ops.diseqc_reset_overload) { + err = fe->ops.diseqc_reset_overload(fe); + fepriv->state = FESTATE_DISEQC; + fepriv->status = 0; + } + break; + + case FE_DISEQC_SEND_MASTER_CMD: + if (fe->ops.diseqc_send_master_cmd) { + err = fe->ops.diseqc_send_master_cmd(fe, (struct dvb_diseqc_master_cmd*) parg); + fepriv->state = FESTATE_DISEQC; + fepriv->status = 0; + } + break; + + case FE_DISEQC_SEND_BURST: + if (fe->ops.diseqc_send_burst) { + err = fe->ops.diseqc_send_burst(fe, (fe_sec_mini_cmd_t) parg); + fepriv->state = FESTATE_DISEQC; + fepriv->status = 0; + } + break; + + case FE_SET_TONE: + if (fe->ops.set_tone) { + err = fe->ops.set_tone(fe, (fe_sec_tone_mode_t) parg); + fepriv->tone = (fe_sec_tone_mode_t) parg; + fepriv->state = FESTATE_DISEQC; + fepriv->status = 0; + } + break; + + case FE_SET_VOLTAGE: + if (fe->ops.set_voltage) { + err = fe->ops.set_voltage(fe, (fe_sec_voltage_t) parg); + fepriv->voltage = (fe_sec_voltage_t) parg; + fepriv->state = FESTATE_DISEQC; + fepriv->status = 0; + } + break; + + case FE_DISHNETWORK_SEND_LEGACY_CMD: + if (fe->ops.dishnetwork_send_legacy_command) { + err = fe->ops.dishnetwork_send_legacy_command(fe, (unsigned long) parg); + fepriv->state = FESTATE_DISEQC; + fepriv->status = 0; + } else if (fe->ops.set_voltage) { + /* + * NOTE: This is a fallback condition. Some frontends + * (stv0299 for instance) take longer than 8msec to + * respond to a set_voltage command. Those switches + * need custom routines to switch properly. For all + * other frontends, the following should work ok. + * Dish network legacy switches (as used by Dish500) + * are controlled by sending 9-bit command words + * spaced 8msec apart. + * the actual command word is switch/port dependent + * so it is up to the userspace application to send + * the right command. + * The command must always start with a '0' after + * initialization, so parg is 8 bits and does not + * include the initialization or start bit + */ + unsigned long swcmd = ((unsigned long) parg) << 1; + struct timeval nexttime; + struct timeval tv[10]; + int i; + u8 last = 1; + if (dvb_frontend_debug) + printk("%s switch command: 0x%04lx\n", __func__, swcmd); + do_gettimeofday(&nexttime); + if (dvb_frontend_debug) + tv[0] = nexttime; + /* before sending a command, initialize by sending + * a 32ms 18V to the switch + */ + fe->ops.set_voltage(fe, SEC_VOLTAGE_18); + dvb_frontend_sleep_until(&nexttime, 32000); + + for (i = 0; i < 9; i++) { + if (dvb_frontend_debug) + do_gettimeofday(&tv[i + 1]); + if ((swcmd & 0x01) != last) { + /* set voltage to (last ? 13V : 18V) */ + fe->ops.set_voltage(fe, (last) ? SEC_VOLTAGE_13 : SEC_VOLTAGE_18); + last = (last) ? 0 : 1; + } + swcmd = swcmd >> 1; + if (i != 8) + dvb_frontend_sleep_until(&nexttime, 8000); + } + if (dvb_frontend_debug) { + printk("%s(%d): switch delay (should be 32k followed by all 8k\n", + __func__, fe->dvb->num); + for (i = 1; i < 10; i++) + printk("%d: %d\n", i, timeval_usec_diff(tv[i-1] , tv[i])); + } + err = 0; + fepriv->state = FESTATE_DISEQC; + fepriv->status = 0; + } + break; + + case FE_DISEQC_RECV_SLAVE_REPLY: + if (fe->ops.diseqc_recv_slave_reply) + err = fe->ops.diseqc_recv_slave_reply(fe, (struct dvb_diseqc_slave_reply*) parg); + break; + + case FE_ENABLE_HIGH_LNB_VOLTAGE: + if (fe->ops.enable_high_lnb_voltage) + err = fe->ops.enable_high_lnb_voltage(fe, (long) parg); + break; + + case FE_SET_FRONTEND: + err = dvbv3_set_delivery_system(fe); + if (err) + break; + + err = dtv_property_cache_sync(fe, c, parg); + if (err) + break; + err = dtv_set_frontend(fe); + break; + case FE_GET_EVENT: + err = dvb_frontend_get_event (fe, parg, file->f_flags); + break; + + case FE_GET_FRONTEND: + err = dtv_get_frontend(fe, parg); + break; + + case FE_SET_FRONTEND_TUNE_MODE: + fepriv->tune_mode_flags = (unsigned long) parg; + err = 0; + break; + } + + return err; +} + + +static unsigned int dvb_frontend_poll(struct file *file, struct poll_table_struct *wait) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_frontend *fe = dvbdev->priv; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + + //dev_dbg_ratelimited(fe->dvb->device, "%s:\n", __func__); + + poll_wait (file, &fepriv->events.wait_queue, wait); + + if (fepriv->events.eventw != fepriv->events.eventr) + return (POLLIN | POLLRDNORM | POLLPRI); + + return 0; +} + +static int dvb_frontend_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_frontend *fe = dvbdev->priv; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dvb_adapter *adapter = fe->dvb; + int ret; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + if (fepriv->exit == DVB_FE_DEVICE_REMOVED) + return -ENODEV; + + if (adapter->mfe_shared) { + mutex_lock (&adapter->mfe_lock); + + if (adapter->mfe_dvbdev == NULL) + adapter->mfe_dvbdev = dvbdev; + + else if (adapter->mfe_dvbdev != dvbdev) { + struct dvb_device + *mfedev = adapter->mfe_dvbdev; + struct dvb_frontend + *mfe = mfedev->priv; + struct dvb_frontend_private + *mfepriv = mfe->frontend_priv; + int mferetry = (dvb_mfe_wait_time << 1); + + mutex_unlock (&adapter->mfe_lock); + while (mferetry-- && (mfedev->users != -1 || + mfepriv->thread != NULL)) { + if(msleep_interruptible(500)) { + if(signal_pending(current)) + return -EINTR; + } + } + + mutex_lock (&adapter->mfe_lock); + if(adapter->mfe_dvbdev != dvbdev) { + mfedev = adapter->mfe_dvbdev; + mfe = mfedev->priv; + mfepriv = mfe->frontend_priv; + if (mfedev->users != -1 || + mfepriv->thread != NULL) { + mutex_unlock (&adapter->mfe_lock); + return -EBUSY; + } + adapter->mfe_dvbdev = dvbdev; + } + } + } + + if (dvbdev->users == -1 && fe->ops.ts_bus_ctrl) { + if ((ret = fe->ops.ts_bus_ctrl(fe, 1)) < 0) + goto err0; + + /* If we took control of the bus, we need to force + reinitialization. This is because many ts_bus_ctrl() + functions strobe the RESET pin on the demod, and if the + frontend thread already exists then the dvb_init() routine + won't get called (which is what usually does initial + register configuration). */ + fepriv->reinitialise = 1; + } + + if ((ret = dvb_generic_open (inode, file)) < 0) + goto err1; + + if ((file->f_flags & O_ACCMODE) != O_RDONLY) { + /* normal tune mode when opened R/W */ + fepriv->tune_mode_flags &= ~FE_TUNE_MODE_ONESHOT; + fepriv->tone = -1; + fepriv->voltage = -1; + + ret = dvb_frontend_start (fe); + if (ret) + goto err2; + + /* empty event queue */ + fepriv->events.eventr = fepriv->events.eventw = 0; + } + + if (adapter->mfe_shared) + mutex_unlock (&adapter->mfe_lock); + return ret; + +err2: + dvb_generic_release(inode, file); +err1: + if (dvbdev->users == -1 && fe->ops.ts_bus_ctrl) + fe->ops.ts_bus_ctrl(fe, 0); +err0: + if (adapter->mfe_shared) + mutex_unlock (&adapter->mfe_lock); + return ret; +} + +static int dvb_frontend_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_frontend *fe = dvbdev->priv; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + int ret; + + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + if ((file->f_flags & O_ACCMODE) != O_RDONLY) { + fepriv->release_jiffies = jiffies; + mb(); + } + + ret = dvb_generic_release (inode, file); + + if (dvbdev->users == -1) { + wake_up(&fepriv->wait_queue); + if (fepriv->exit != DVB_FE_NO_EXIT) + wake_up(&dvbdev->wait_queue); + if (fe->ops.ts_bus_ctrl) + fe->ops.ts_bus_ctrl(fe, 0); + } + + return ret; +} + +static const struct file_operations dvb_frontend_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = dvb_generic_ioctl, + .poll = dvb_frontend_poll, + .open = dvb_frontend_open, + .release = dvb_frontend_release, + .llseek = noop_llseek, +}; + +int dvb_frontend_suspend(struct dvb_frontend *fe) +{ + int ret = 0; + + dev_dbg(fe->dvb->device, "%s: adap=%d fe=%d\n", __func__, fe->dvb->num, + fe->id); + + if (fe->ops.tuner_ops.sleep) + ret = fe->ops.tuner_ops.sleep(fe); + + if (fe->ops.sleep) + ret = fe->ops.sleep(fe); + + return ret; +} +EXPORT_SYMBOL(dvb_frontend_suspend); + +int dvb_frontend_resume(struct dvb_frontend *fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + int ret = 0; + + dev_dbg(fe->dvb->device, "%s: adap=%d fe=%d\n", __func__, fe->dvb->num, + fe->id); + + if (fe->ops.init) + ret = fe->ops.init(fe); + + if (fe->ops.tuner_ops.init) + ret = fe->ops.tuner_ops.init(fe); + + fepriv->state = FESTATE_RETUNE; + dvb_frontend_wakeup(fe); + + return ret; +} +EXPORT_SYMBOL(dvb_frontend_resume); + +int dvb_register_frontend(struct dvb_adapter* dvb, + struct dvb_frontend* fe) +{ + struct dvb_frontend_private *fepriv; + static const struct dvb_device dvbdev_template = { + .users = ~0, + .writers = 1, + .readers = (~0)-1, + .fops = &dvb_frontend_fops, + .kernel_ioctl = dvb_frontend_ioctl + }; + + dev_dbg(dvb->device, "%s:\n", __func__); + + if (mutex_lock_interruptible(&frontend_mutex)) + return -ERESTARTSYS; + + fe->frontend_priv = kzalloc(sizeof(struct dvb_frontend_private), GFP_KERNEL); + if (fe->frontend_priv == NULL) { + mutex_unlock(&frontend_mutex); + return -ENOMEM; + } + fepriv = fe->frontend_priv; + + sema_init(&fepriv->sem, 1); + init_waitqueue_head (&fepriv->wait_queue); + init_waitqueue_head (&fepriv->events.wait_queue); + mutex_init(&fepriv->events.mtx); + fe->dvb = dvb; + fepriv->inversion = INVERSION_OFF; + + dvb_register_device (fe->dvb, &fepriv->dvbdev, &dvbdev_template, + fe, DVB_DEVICE_FRONTEND); + + dev_info(fe->dvb->device, + "DVB: registering adapter %i frontend %i (%s)...\n", + fe->dvb->num, fepriv->dvbdev->id, fe->ops.info.name); + + /* + * Initialize the cache to the proper values according with the + * first supported delivery system (ops->delsys[0]) + */ + + fe->dtv_property_cache.delivery_system = fe->ops.delsys[0]; + dvb_frontend_clear_cache(fe); + + mutex_unlock(&frontend_mutex); + return 0; +} +EXPORT_SYMBOL(dvb_register_frontend); + +int dvb_unregister_frontend(struct dvb_frontend* fe) +{ + struct dvb_frontend_private *fepriv = fe->frontend_priv; + dev_dbg(fe->dvb->device, "%s:\n", __func__); + + mutex_lock(&frontend_mutex); + dvb_frontend_stop (fe); + mutex_unlock(&frontend_mutex); + + if (fepriv->dvbdev->users < -1) + wait_event(fepriv->dvbdev->wait_queue, + fepriv->dvbdev->users==-1); + + mutex_lock(&frontend_mutex); + dvb_unregister_device (fepriv->dvbdev); + + /* fe is invalid now */ + kfree(fepriv); + mutex_unlock(&frontend_mutex); + return 0; +} +EXPORT_SYMBOL(dvb_unregister_frontend); + +#ifdef CONFIG_MEDIA_ATTACH +void dvb_frontend_detach(struct dvb_frontend* fe) +{ + void *ptr; + + if (fe->ops.release_sec) { + fe->ops.release_sec(fe); + symbol_put_addr(fe->ops.release_sec); + } + if (fe->ops.tuner_ops.release) { + fe->ops.tuner_ops.release(fe); + symbol_put_addr(fe->ops.tuner_ops.release); + } + if (fe->ops.analog_ops.release) { + fe->ops.analog_ops.release(fe); + symbol_put_addr(fe->ops.analog_ops.release); + } + ptr = (void*)fe->ops.release; + if (ptr) { + fe->ops.release(fe); + symbol_put_addr(ptr); + } +} +#else +void dvb_frontend_detach(struct dvb_frontend* fe) +{ + if (fe->ops.release_sec) + fe->ops.release_sec(fe); + if (fe->ops.tuner_ops.release) + fe->ops.tuner_ops.release(fe); + if (fe->ops.analog_ops.release) + fe->ops.analog_ops.release(fe); + if (fe->ops.release) + fe->ops.release(fe); +} +#endif +EXPORT_SYMBOL(dvb_frontend_detach); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_frontend.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,437 @@ +/* + * dvb_frontend.h + * + * Copyright (C) 2001 convergence integrated media GmbH + * Copyright (C) 2004 convergence GmbH + * + * Written by Ralph Metzler + * Overhauled by Holger Waechtler + * Kernel I2C stuff by Michael Hunold + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVB_FRONTEND_H_ +#define _DVB_FRONTEND_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "dvbdev.h" + +/* + * Maximum number of Delivery systems per frontend. It + * should be smaller or equal to 32 + */ +#define MAX_DELSYS 8 + +struct dvb_frontend_tune_settings { + int min_delay_ms; + int step_size; + int max_drift; +}; + +struct dvb_frontend; + +struct dvb_tuner_info { + char name[128]; + + u32 frequency_min; + u32 frequency_max; + u32 frequency_step; + + u32 bandwidth_min; + u32 bandwidth_max; + u32 bandwidth_step; +}; + +struct analog_parameters { + unsigned int frequency; + unsigned int mode; + unsigned int audmode; + u64 std; +}; + +enum dvbfe_modcod { + DVBFE_MODCOD_DUMMY_PLFRAME = 0, + DVBFE_MODCOD_QPSK_1_4, + DVBFE_MODCOD_QPSK_1_3, + DVBFE_MODCOD_QPSK_2_5, + DVBFE_MODCOD_QPSK_1_2, + DVBFE_MODCOD_QPSK_3_5, + DVBFE_MODCOD_QPSK_2_3, + DVBFE_MODCOD_QPSK_3_4, + DVBFE_MODCOD_QPSK_4_5, + DVBFE_MODCOD_QPSK_5_6, + DVBFE_MODCOD_QPSK_8_9, + DVBFE_MODCOD_QPSK_9_10, + DVBFE_MODCOD_8PSK_3_5, + DVBFE_MODCOD_8PSK_2_3, + DVBFE_MODCOD_8PSK_3_4, + DVBFE_MODCOD_8PSK_5_6, + DVBFE_MODCOD_8PSK_8_9, + DVBFE_MODCOD_8PSK_9_10, + DVBFE_MODCOD_16APSK_2_3, + DVBFE_MODCOD_16APSK_3_4, + DVBFE_MODCOD_16APSK_4_5, + DVBFE_MODCOD_16APSK_5_6, + DVBFE_MODCOD_16APSK_8_9, + DVBFE_MODCOD_16APSK_9_10, + DVBFE_MODCOD_32APSK_3_4, + DVBFE_MODCOD_32APSK_4_5, + DVBFE_MODCOD_32APSK_5_6, + DVBFE_MODCOD_32APSK_8_9, + DVBFE_MODCOD_32APSK_9_10, + DVBFE_MODCOD_RESERVED_1, + DVBFE_MODCOD_BPSK_1_3, + DVBFE_MODCOD_BPSK_1_4, + DVBFE_MODCOD_RESERVED_2 +}; + +enum tuner_param { + DVBFE_TUNER_FREQUENCY = (1 << 0), + DVBFE_TUNER_TUNERSTEP = (1 << 1), + DVBFE_TUNER_IFFREQ = (1 << 2), + DVBFE_TUNER_BANDWIDTH = (1 << 3), + DVBFE_TUNER_REFCLOCK = (1 << 4), + DVBFE_TUNER_IQSENSE = (1 << 5), + DVBFE_TUNER_DUMMY = (1 << 31) +}; + +/* + * ALGO_HW: (Hardware Algorithm) + * ---------------------------------------------------------------- + * Devices that support this algorithm do everything in hardware + * and no software support is needed to handle them. + * Requesting these devices to LOCK is the only thing required, + * device is supposed to do everything in the hardware. + * + * ALGO_SW: (Software Algorithm) + * ---------------------------------------------------------------- + * These are dumb devices, that require software to do everything + * + * ALGO_CUSTOM: (Customizable Agorithm) + * ---------------------------------------------------------------- + * Devices having this algorithm can be customized to have specific + * algorithms in the frontend driver, rather than simply doing a + * software zig-zag. In this case the zigzag maybe hardware assisted + * or it maybe completely done in hardware. In all cases, usage of + * this algorithm, in conjunction with the search and track + * callbacks, utilizes the driver specific algorithm. + * + * ALGO_RECOVERY: (Recovery Algorithm) + * ---------------------------------------------------------------- + * These devices have AUTO recovery capabilities from LOCK failure + */ +enum dvbfe_algo { + DVBFE_ALGO_HW = (1 << 0), + DVBFE_ALGO_SW = (1 << 1), + DVBFE_ALGO_CUSTOM = (1 << 2), + DVBFE_ALGO_RECOVERY = (1 << 31) +}; + +struct tuner_state { + u32 frequency; + u32 tunerstep; + u32 ifreq; + u32 bandwidth; + u32 iqsense; + u32 refclock; +}; + +/* + * search callback possible return status + * + * DVBFE_ALGO_SEARCH_SUCCESS + * The frontend search algorithm completed and returned successfully + * + * DVBFE_ALGO_SEARCH_ASLEEP + * The frontend search algorithm is sleeping + * + * DVBFE_ALGO_SEARCH_FAILED + * The frontend search for a signal failed + * + * DVBFE_ALGO_SEARCH_INVALID + * The frontend search algorith was probably supplied with invalid + * parameters and the search is an invalid one + * + * DVBFE_ALGO_SEARCH_ERROR + * The frontend search algorithm failed due to some error + * + * DVBFE_ALGO_SEARCH_AGAIN + * The frontend search algorithm was requested to search again + */ +enum dvbfe_search { + DVBFE_ALGO_SEARCH_SUCCESS = (1 << 0), + DVBFE_ALGO_SEARCH_ASLEEP = (1 << 1), + DVBFE_ALGO_SEARCH_FAILED = (1 << 2), + DVBFE_ALGO_SEARCH_INVALID = (1 << 3), + DVBFE_ALGO_SEARCH_AGAIN = (1 << 4), + DVBFE_ALGO_SEARCH_ERROR = (1 << 31), +}; + + +struct dvb_tuner_ops { + + struct dvb_tuner_info info; + + int (*release)(struct dvb_frontend *fe); + int (*init)(struct dvb_frontend *fe); + int (*sleep)(struct dvb_frontend *fe); + + /** This is for simple PLLs - set all parameters in one go. */ + int (*set_params)(struct dvb_frontend *fe); + int (*set_analog_params)(struct dvb_frontend *fe, struct analog_parameters *p); + + /** This is support for demods like the mt352 - fills out the supplied buffer with what to write. */ + int (*calc_regs)(struct dvb_frontend *fe, u8 *buf, int buf_len); + + /** This is to allow setting tuner-specific configs */ + int (*set_config)(struct dvb_frontend *fe, void *priv_cfg); + + int (*get_frequency)(struct dvb_frontend *fe, u32 *frequency); + int (*get_bandwidth)(struct dvb_frontend *fe, u32 *bandwidth); + int (*get_if_frequency)(struct dvb_frontend *fe, u32 *frequency); + +#define TUNER_STATUS_LOCKED 1 +#define TUNER_STATUS_STEREO 2 + int (*get_status)(struct dvb_frontend *fe, u32 *status); + int (*get_rf_strength)(struct dvb_frontend *fe, u16 *strength); + int (*get_afc)(struct dvb_frontend *fe, s32 *afc); + + /** These are provided separately from set_params in order to facilitate silicon + * tuners which require sophisticated tuning loops, controlling each parameter separately. */ + int (*set_frequency)(struct dvb_frontend *fe, u32 frequency); + int (*set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth); + + /* + * These are provided separately from set_params in order to facilitate silicon + * tuners which require sophisticated tuning loops, controlling each parameter separately. + */ + int (*set_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); + int (*get_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); +}; + +struct analog_demod_info { + char *name; +}; + +struct analog_demod_ops { + + struct analog_demod_info info; + + void (*set_params)(struct dvb_frontend *fe, + struct analog_parameters *params); + int (*has_signal)(struct dvb_frontend *fe, u16 *signal); + int (*get_afc)(struct dvb_frontend *fe, s32 *afc); + void (*tuner_status)(struct dvb_frontend *fe); + void (*standby)(struct dvb_frontend *fe); + void (*release)(struct dvb_frontend *fe); + int (*i2c_gate_ctrl)(struct dvb_frontend *fe, int enable); + + /** This is to allow setting tuner-specific configuration */ + int (*set_config)(struct dvb_frontend *fe, void *priv_cfg); +}; + +struct dtv_frontend_properties; + +struct dvb_frontend_ops { + + struct dvb_frontend_info info; + + u8 delsys[MAX_DELSYS]; + + void (*release)(struct dvb_frontend* fe); + void (*release_sec)(struct dvb_frontend* fe); + + int (*init)(struct dvb_frontend* fe); + int (*sleep)(struct dvb_frontend* fe); + + int (*write)(struct dvb_frontend* fe, const u8 buf[], int len); + + /* if this is set, it overrides the default swzigzag */ + int (*tune)(struct dvb_frontend* fe, + bool re_tune, + unsigned int mode_flags, + unsigned int *delay, + fe_status_t *status); + /* get frontend tuning algorithm from the module */ + enum dvbfe_algo (*get_frontend_algo)(struct dvb_frontend *fe); + + /* these two are only used for the swzigzag code */ + int (*set_frontend)(struct dvb_frontend *fe); + int (*get_tune_settings)(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* settings); + + int (*get_frontend)(struct dvb_frontend *fe); + + int (*read_status)(struct dvb_frontend* fe, fe_status_t* status); + int (*read_ber)(struct dvb_frontend* fe, u32* ber); + int (*read_signal_strength)(struct dvb_frontend* fe, u16* strength); + int (*read_snr)(struct dvb_frontend* fe, u16* snr); + int (*read_ucblocks)(struct dvb_frontend* fe, u32* ucblocks); + + int (*diseqc_reset_overload)(struct dvb_frontend* fe); + int (*diseqc_send_master_cmd)(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd); + int (*diseqc_recv_slave_reply)(struct dvb_frontend* fe, struct dvb_diseqc_slave_reply* reply); + int (*diseqc_send_burst)(struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd); + int (*set_tone)(struct dvb_frontend* fe, fe_sec_tone_mode_t tone); + int (*set_voltage)(struct dvb_frontend* fe, fe_sec_voltage_t voltage); + int (*enable_high_lnb_voltage)(struct dvb_frontend* fe, long arg); + int (*dishnetwork_send_legacy_command)(struct dvb_frontend* fe, unsigned long cmd); + int (*i2c_gate_ctrl)(struct dvb_frontend* fe, int enable); + int (*ts_bus_ctrl)(struct dvb_frontend* fe, int acquire); + int (*set_lna)(struct dvb_frontend *); + + /* These callbacks are for devices that implement their own + * tuning algorithms, rather than a simple swzigzag + */ + enum dvbfe_search (*search)(struct dvb_frontend *fe); + + struct dvb_tuner_ops tuner_ops; + struct analog_demod_ops analog_ops; + + int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); + int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); +}; + +#ifdef __DVB_CORE__ +#define MAX_EVENT 8 + +struct dvb_fe_events { + struct dvb_frontend_event events[MAX_EVENT]; + int eventw; + int eventr; + int overflow; + wait_queue_head_t wait_queue; + struct mutex mtx; +}; +#endif + +struct dtv_frontend_properties { + + /* Cache State */ + u32 state; + + u32 frequency; + fe_modulation_t modulation; + + fe_sec_voltage_t voltage; + fe_sec_tone_mode_t sectone; + fe_spectral_inversion_t inversion; + fe_code_rate_t fec_inner; + fe_transmit_mode_t transmission_mode; + u32 bandwidth_hz; /* 0 = AUTO */ + fe_guard_interval_t guard_interval; + fe_hierarchy_t hierarchy; + u32 symbol_rate; + fe_code_rate_t code_rate_HP; + fe_code_rate_t code_rate_LP; + + fe_pilot_t pilot; + fe_rolloff_t rolloff; + + fe_delivery_system_t delivery_system; + + enum fe_interleaving interleaving; + + /* ISDB-T specifics */ + u8 isdbt_partial_reception; + u8 isdbt_sb_mode; + u8 isdbt_sb_subchannel; + u32 isdbt_sb_segment_idx; + u32 isdbt_sb_segment_count; + u8 isdbt_layer_enabled; + struct { + u8 segment_count; + fe_code_rate_t fec; + fe_modulation_t modulation; + u8 interleaving; + } layer[3]; + + /* Multistream specifics */ + u32 stream_id; + + /* ATSC-MH specifics */ + u8 atscmh_fic_ver; + u8 atscmh_parade_id; + u8 atscmh_nog; + u8 atscmh_tnog; + u8 atscmh_sgn; + u8 atscmh_prc; + + u8 atscmh_rs_frame_mode; + u8 atscmh_rs_frame_ensemble; + u8 atscmh_rs_code_mode_pri; + u8 atscmh_rs_code_mode_sec; + u8 atscmh_sccc_block_mode; + u8 atscmh_sccc_code_mode_a; + u8 atscmh_sccc_code_mode_b; + u8 atscmh_sccc_code_mode_c; + u8 atscmh_sccc_code_mode_d; + + u32 lna; + + /* statistics data */ + struct dtv_fe_stats strength; + struct dtv_fe_stats cnr; + struct dtv_fe_stats pre_bit_error; + struct dtv_fe_stats pre_bit_count; + struct dtv_fe_stats post_bit_error; + struct dtv_fe_stats post_bit_count; + struct dtv_fe_stats block_error; + struct dtv_fe_stats block_count; +}; + +struct dvb_frontend { + struct dvb_frontend_ops ops; + struct dvb_adapter *dvb; + void *demodulator_priv; + void *tuner_priv; + void *frontend_priv; + void *sec_priv; + void *analog_demod_priv; + struct dtv_frontend_properties dtv_property_cache; +#define DVB_FRONTEND_COMPONENT_TUNER 0 +#define DVB_FRONTEND_COMPONENT_DEMOD 1 + int (*callback)(void *adapter_priv, int component, int cmd, int arg); + int id; +}; + +extern int dvb_register_frontend(struct dvb_adapter *dvb, + struct dvb_frontend *fe); + +extern int dvb_unregister_frontend(struct dvb_frontend *fe); + +extern void dvb_frontend_detach(struct dvb_frontend *fe); + +extern void dvb_frontend_reinitialise(struct dvb_frontend *fe); +extern int dvb_frontend_suspend(struct dvb_frontend *fe); +extern int dvb_frontend_resume(struct dvb_frontend *fe); + +extern void dvb_frontend_sleep_until(struct timeval *waketime, u32 add_usec); +extern s32 timeval_usec_diff(struct timeval lasttime, struct timeval curtime); + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,145 @@ +/* + * dvb-math provides some complex fixed-point math + * operations shared between the dvb related stuff + * + * Copyright (C) 2006 Christoph Pfister (christophpfister@gmail.com) + * + * This library is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "dvb_math.h" + +static const unsigned short logtable[256] = { + 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7, + 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508, + 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6, + 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37, + 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f, + 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41, + 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1, + 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142, + 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68, + 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355, + 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c, + 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490, + 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3, + 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507, + 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe, + 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca, + 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c, + 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7, + 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c, + 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c, + 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a, + 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065, + 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730, + 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc, + 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469, + 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9, + 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c, + 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765, + 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83, + 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387, + 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973, + 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47 +}; + +unsigned int intlog2(u32 value) +{ + /** + * returns: log2(value) * 2^24 + * wrong result if value = 0 (log2(0) is undefined) + */ + unsigned int msb; + unsigned int logentry; + unsigned int significand; + unsigned int interpolation; + + if (unlikely(value == 0)) { + WARN_ON(1); + return 0; + } + + /* first detect the msb (count begins at 0) */ + msb = fls(value) - 1; + + /** + * now we use a logtable after the following method: + * + * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24 + * where x = msb and therefore 1 <= y < 2 + * first y is determined by shifting the value left + * so that msb is bit 31 + * 0x00231f56 -> 0x8C7D5800 + * the result is y * 2^31 -> "significand" + * then the highest 9 bits are used for a table lookup + * the highest bit is discarded because it's always set + * the highest nine bits in our example are 100011000 + * so we would use the entry 0x18 + */ + significand = value << (31 - msb); + logentry = (significand >> 23) & 0xff; + + /** + * last step we do is interpolation because of the + * limitations of the log table the error is that part of + * the significand which isn't used for lookup then we + * compute the ratio between the error and the next table entry + * and interpolate it between the log table entry used and the + * next one the biggest error possible is 0x7fffff + * (in our example it's 0x7D5800) + * needed value for next table entry is 0x800000 + * so the interpolation is + * (error / 0x800000) * (logtable_next - logtable_current) + * in the implementation the division is moved to the end for + * better accuracy there is also an overflow correction if + * logtable_next is 256 + */ + interpolation = ((significand & 0x7fffff) * + ((logtable[(logentry + 1) & 0xff] - + logtable[logentry]) & 0xffff)) >> 15; + + /* now we return the result */ + return ((msb << 24) + (logtable[logentry] << 8) + interpolation); +} +EXPORT_SYMBOL(intlog2); + +unsigned int intlog10(u32 value) +{ + /** + * returns: log10(value) * 2^24 + * wrong result if value = 0 (log10(0) is undefined) + */ + u64 log; + + if (unlikely(value == 0)) { + WARN_ON(1); + return 0; + } + + log = intlog2(value); + + /** + * we use the following method: + * log10(x) = log2(x) * log10(2) + */ + + return (log * 646456993) >> 31; +} +EXPORT_SYMBOL(intlog10); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_math.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,58 @@ +/* + * dvb-math provides some complex fixed-point math + * operations shared between the dvb related stuff + * + * Copyright (C) 2006 Christoph Pfister (christophpfister@gmail.com) + * + * This library is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __DVB_MATH_H +#define __DVB_MATH_H + +#include + +/** + * computes log2 of a value; the result is shifted left by 24 bits + * + * to use rational values you can use the following method: + * intlog2(value) = intlog2(value * 2^x) - x * 2^24 + * + * example: intlog2(8) will give 3 << 24 = 3 * 2^24 + * example: intlog2(9) will give 3 << 24 + ... = 3.16... * 2^24 + * example: intlog2(1.5) = intlog2(3) - 2^24 = 0.584... * 2^24 + * + * @param value The value (must be != 0) + * @return log2(value) * 2^24 + */ +extern unsigned int intlog2(u32 value); + +/** + * computes log10 of a value; the result is shifted left by 24 bits + * + * to use rational values you can use the following method: + * intlog10(value) = intlog10(value * 10^x) - x * 2^24 + * + * example: intlog10(1000) will give 3 << 24 = 3 * 2^24 + * due to the implementation intlog10(1000) might be not exactly 3 * 2^24 + * + * look at intlog2 for similar examples + * + * @param value The value (must be != 0) + * @return log10(value) * 2^24 + */ +extern unsigned int intlog10(u32 value); + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1542 @@ +/* + * dvb_net.c + * + * Copyright (C) 2001 Convergence integrated media GmbH + * Ralph Metzler + * Copyright (C) 2002 Ralph Metzler + * + * ULE Decapsulation code: + * Copyright (C) 2003, 2004 gcs - Global Communication & Services GmbH. + * and Department of Scientific Computing + * Paris Lodron University of Salzburg. + * Hilmar Linder + * and Wolfram Stering + * + * ULE Decaps according to RFC 4326. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +/* + * ULE ChangeLog: + * Feb 2004: hl/ws v1: Implementing draft-fair-ipdvb-ule-01.txt + * + * Dec 2004: hl/ws v2: Implementing draft-ietf-ipdvb-ule-03.txt: + * ULE Extension header handling. + * Bugreports by Moritz Vieth and Hanno Tersteegen, + * Fraunhofer Institute for Open Communication Systems + * Competence Center for Advanced Satellite Communications. + * Bugfixes and robustness improvements. + * Filtering on dest MAC addresses, if present (D-Bit = 0) + * ULE_DEBUG compile-time option. + * Apr 2006: cp v3: Bugfixes and compliency with RFC 4326 (ULE) by + * Christian Praehauser , + * Paris Lodron University of Salzburg. + */ + +/* + * FIXME / TODO (dvb_net.c): + * + * Unloading does not work for 2.6.9 kernels: a refcount doesn't go to zero. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_demux.h" +#include "dvb_net.h" + +#ifndef ETH_P_802_3_MIN +#define ETH_P_802_3_MIN 1536 +#endif + +static int dvb_net_debug; +module_param(dvb_net_debug, int, 0444); +MODULE_PARM_DESC(dvb_net_debug, "enable debug messages"); + +#define dprintk(x...) do { if (dvb_net_debug) printk(x); } while (0) + + +static inline __u32 iov_crc32( __u32 c, struct kvec *iov, unsigned int cnt ) +{ + unsigned int j; + for (j = 0; j < cnt; j++) + c = crc32_be( c, iov[j].iov_base, iov[j].iov_len ); + return c; +} + + +#define DVB_NET_MULTICAST_MAX 10 + +#undef ULE_DEBUG + +#ifdef ULE_DEBUG + +#define MAC_ADDR_PRINTFMT "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x" +#define MAX_ADDR_PRINTFMT_ARGS(macap) (macap)[0],(macap)[1],(macap)[2],(macap)[3],(macap)[4],(macap)[5] + +#define isprint(c) ((c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || (c >= '0' && c <= '9')) + +static void hexdump( const unsigned char *buf, unsigned short len ) +{ + char str[80], octet[10]; + int ofs, i, l; + + for (ofs = 0; ofs < len; ofs += 16) { + sprintf( str, "%03d: ", ofs ); + + for (i = 0; i < 16; i++) { + if ((i + ofs) < len) + sprintf( octet, "%02x ", buf[ofs + i] ); + else + strcpy( octet, " " ); + + strcat( str, octet ); + } + strcat( str, " " ); + l = strlen( str ); + + for (i = 0; (i < 16) && ((i + ofs) < len); i++) + str[l++] = isprint( buf[ofs + i] ) ? buf[ofs + i] : '.'; + + str[l] = '\0'; + printk( KERN_WARNING "%s\n", str ); + } +} + +#endif + +struct dvb_net_priv { + int in_use; + u16 pid; + struct net_device *net; + struct dvb_net *host; + struct dmx_demux *demux; + struct dmx_section_feed *secfeed; + struct dmx_section_filter *secfilter; + struct dmx_ts_feed *tsfeed; + int multi_num; + struct dmx_section_filter *multi_secfilter[DVB_NET_MULTICAST_MAX]; + unsigned char multi_macs[DVB_NET_MULTICAST_MAX][6]; + int rx_mode; +#define RX_MODE_UNI 0 +#define RX_MODE_MULTI 1 +#define RX_MODE_ALL_MULTI 2 +#define RX_MODE_PROMISC 3 + struct work_struct set_multicast_list_wq; + struct work_struct restart_net_feed_wq; + unsigned char feedtype; /* Either FEED_TYPE_ or FEED_TYPE_ULE */ + int need_pusi; /* Set to 1, if synchronization on PUSI required. */ + unsigned char tscc; /* TS continuity counter after sync on PUSI. */ + struct sk_buff *ule_skb; /* ULE SNDU decodes into this buffer. */ + unsigned char *ule_next_hdr; /* Pointer into skb to next ULE extension header. */ + unsigned short ule_sndu_len; /* ULE SNDU length in bytes, w/o D-Bit. */ + unsigned short ule_sndu_type; /* ULE SNDU type field, complete. */ + unsigned char ule_sndu_type_1; /* ULE SNDU type field, if split across 2 TS cells. */ + unsigned char ule_dbit; /* Whether the DestMAC address present + * or not (bit is set). */ + unsigned char ule_bridged; /* Whether the ULE_BRIDGED extension header was found. */ + int ule_sndu_remain; /* Nr. of bytes still required for current ULE SNDU. */ + unsigned long ts_count; /* Current ts cell counter. */ + struct mutex mutex; +}; + + +/** + * Determine the packet's protocol ID. The rule here is that we + * assume 802.3 if the type field is short enough to be a length. + * This is normal practice and works for any 'now in use' protocol. + * + * stolen from eth.c out of the linux kernel, hacked for dvb-device + * by Michael Holzt + */ +static __be16 dvb_net_eth_type_trans(struct sk_buff *skb, + struct net_device *dev) +{ + struct ethhdr *eth; + unsigned char *rawp; + + skb_reset_mac_header(skb); + skb_pull(skb,dev->hard_header_len); + eth = eth_hdr(skb); + + if (*eth->h_dest & 1) { + if(memcmp(eth->h_dest,dev->broadcast, ETH_ALEN)==0) + skb->pkt_type=PACKET_BROADCAST; + else + skb->pkt_type=PACKET_MULTICAST; + } + + if (ntohs(eth->h_proto) >= ETH_P_802_3_MIN) + return eth->h_proto; + + rawp = skb->data; + + /** + * This is a magic hack to spot IPX packets. Older Novell breaks + * the protocol design and runs IPX over 802.3 without an 802.2 LLC + * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This + * won't work for fault tolerant netware but does for the rest. + */ + if (*(unsigned short *)rawp == 0xFFFF) + return htons(ETH_P_802_3); + + /** + * Real 802.2 LLC + */ + return htons(ETH_P_802_2); +} + +#define TS_SZ 188 +#define TS_SYNC 0x47 +#define TS_TEI 0x80 +#define TS_SC 0xC0 +#define TS_PUSI 0x40 +#define TS_AF_A 0x20 +#define TS_AF_D 0x10 + +/* ULE Extension Header handlers. */ + +#define ULE_TEST 0 +#define ULE_BRIDGED 1 + +#define ULE_OPTEXTHDR_PADDING 0 + +static int ule_test_sndu( struct dvb_net_priv *p ) +{ + return -1; +} + +static int ule_bridged_sndu( struct dvb_net_priv *p ) +{ + struct ethhdr *hdr = (struct ethhdr*) p->ule_next_hdr; + if(ntohs(hdr->h_proto) < ETH_P_802_3_MIN) { + int framelen = p->ule_sndu_len - ((p->ule_next_hdr+sizeof(struct ethhdr)) - p->ule_skb->data); + /* A frame Type < ETH_P_802_3_MIN for a bridged frame, introduces a LLC Length field. */ + if(framelen != ntohs(hdr->h_proto)) { + return -1; + } + } + /* Note: + * From RFC4326: + * "A bridged SNDU is a Mandatory Extension Header of Type 1. + * It must be the final (or only) extension header specified in the header chain of a SNDU." + * The 'ule_bridged' flag will cause the extension header processing loop to terminate. + */ + p->ule_bridged = 1; + return 0; +} + +static int ule_exthdr_padding(struct dvb_net_priv *p) +{ + return 0; +} + +/** Handle ULE extension headers. + * Function is called after a successful CRC32 verification of an ULE SNDU to complete its decoding. + * Returns: >= 0: nr. of bytes consumed by next extension header + * -1: Mandatory extension header that is not recognized or TEST SNDU; discard. + */ +static int handle_one_ule_extension( struct dvb_net_priv *p ) +{ + /* Table of mandatory extension header handlers. The header type is the index. */ + static int (*ule_mandatory_ext_handlers[255])( struct dvb_net_priv *p ) = + { [0] = ule_test_sndu, [1] = ule_bridged_sndu, [2] = NULL, }; + + /* Table of optional extension header handlers. The header type is the index. */ + static int (*ule_optional_ext_handlers[255])( struct dvb_net_priv *p ) = + { [0] = ule_exthdr_padding, [1] = NULL, }; + + int ext_len = 0; + unsigned char hlen = (p->ule_sndu_type & 0x0700) >> 8; + unsigned char htype = p->ule_sndu_type & 0x00FF; + + /* Discriminate mandatory and optional extension headers. */ + if (hlen == 0) { + /* Mandatory extension header */ + if (ule_mandatory_ext_handlers[htype]) { + ext_len = ule_mandatory_ext_handlers[htype]( p ); + if(ext_len >= 0) { + p->ule_next_hdr += ext_len; + if (!p->ule_bridged) { + p->ule_sndu_type = ntohs(*(__be16 *)p->ule_next_hdr); + p->ule_next_hdr += 2; + } else { + p->ule_sndu_type = ntohs(*(__be16 *)(p->ule_next_hdr + ((p->ule_dbit ? 2 : 3) * ETH_ALEN))); + /* This assures the extension handling loop will terminate. */ + } + } + // else: extension handler failed or SNDU should be discarded + } else + ext_len = -1; /* SNDU has to be discarded. */ + } else { + /* Optional extension header. Calculate the length. */ + ext_len = hlen << 1; + /* Process the optional extension header according to its type. */ + if (ule_optional_ext_handlers[htype]) + (void)ule_optional_ext_handlers[htype]( p ); + p->ule_next_hdr += ext_len; + p->ule_sndu_type = ntohs( *(__be16 *)(p->ule_next_hdr-2) ); + /* + * note: the length of the next header type is included in the + * length of THIS optional extension header + */ + } + + return ext_len; +} + +static int handle_ule_extensions( struct dvb_net_priv *p ) +{ + int total_ext_len = 0, l; + + p->ule_next_hdr = p->ule_skb->data; + do { + l = handle_one_ule_extension( p ); + if (l < 0) + return l; /* Stop extension header processing and discard SNDU. */ + total_ext_len += l; +#ifdef ULE_DEBUG + dprintk("handle_ule_extensions: ule_next_hdr=%p, ule_sndu_type=%i, " + "l=%i, total_ext_len=%i\n", p->ule_next_hdr, + (int) p->ule_sndu_type, l, total_ext_len); +#endif + + } while (p->ule_sndu_type < ETH_P_802_3_MIN); + + return total_ext_len; +} + + +/** Prepare for a new ULE SNDU: reset the decoder state. */ +static inline void reset_ule( struct dvb_net_priv *p ) +{ + p->ule_skb = NULL; + p->ule_next_hdr = NULL; + p->ule_sndu_len = 0; + p->ule_sndu_type = 0; + p->ule_sndu_type_1 = 0; + p->ule_sndu_remain = 0; + p->ule_dbit = 0xFF; + p->ule_bridged = 0; +} + +/** + * Decode ULE SNDUs according to draft-ietf-ipdvb-ule-03.txt from a sequence of + * TS cells of a single PID. + */ +static void dvb_net_ule( struct net_device *dev, const u8 *buf, size_t buf_len ) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + unsigned long skipped = 0L; + const u8 *ts, *ts_end, *from_where = NULL; + u8 ts_remain = 0, how_much = 0, new_ts = 1; + struct ethhdr *ethh = NULL; + bool error = false; + +#ifdef ULE_DEBUG + /* The code inside ULE_DEBUG keeps a history of the last 100 TS cells processed. */ + static unsigned char ule_hist[100*TS_SZ]; + static unsigned char *ule_where = ule_hist, ule_dump; +#endif + + /* For all TS cells in current buffer. + * Appearently, we are called for every single TS cell. + */ + for (ts = buf, ts_end = buf + buf_len; ts < ts_end; /* no default incr. */ ) { + + if (new_ts) { + /* We are about to process a new TS cell. */ + +#ifdef ULE_DEBUG + if (ule_where >= &ule_hist[100*TS_SZ]) ule_where = ule_hist; + memcpy( ule_where, ts, TS_SZ ); + if (ule_dump) { + hexdump( ule_where, TS_SZ ); + ule_dump = 0; + } + ule_where += TS_SZ; +#endif + + /* Check TS error conditions: sync_byte, transport_error_indicator, scrambling_control . */ + if ((ts[0] != TS_SYNC) || (ts[1] & TS_TEI) || ((ts[3] & TS_SC) != 0)) { + printk(KERN_WARNING "%lu: Invalid TS cell: SYNC %#x, TEI %u, SC %#x.\n", + priv->ts_count, ts[0], ts[1] & TS_TEI >> 7, ts[3] & 0xC0 >> 6); + + /* Drop partly decoded SNDU, reset state, resync on PUSI. */ + if (priv->ule_skb) { + dev_kfree_skb( priv->ule_skb ); + /* Prepare for next SNDU. */ + dev->stats.rx_errors++; + dev->stats.rx_frame_errors++; + } + reset_ule(priv); + priv->need_pusi = 1; + + /* Continue with next TS cell. */ + ts += TS_SZ; + priv->ts_count++; + continue; + } + + ts_remain = 184; + from_where = ts + 4; + } + /* Synchronize on PUSI, if required. */ + if (priv->need_pusi) { + if (ts[1] & TS_PUSI) { + /* Find beginning of first ULE SNDU in current TS cell. */ + /* Synchronize continuity counter. */ + priv->tscc = ts[3] & 0x0F; + /* There is a pointer field here. */ + if (ts[4] > ts_remain) { + printk(KERN_ERR "%lu: Invalid ULE packet " + "(pointer field %d)\n", priv->ts_count, ts[4]); + ts += TS_SZ; + priv->ts_count++; + continue; + } + /* Skip to destination of pointer field. */ + from_where = &ts[5] + ts[4]; + ts_remain -= 1 + ts[4]; + skipped = 0; + } else { + skipped++; + ts += TS_SZ; + priv->ts_count++; + continue; + } + } + + if (new_ts) { + /* Check continuity counter. */ + if ((ts[3] & 0x0F) == priv->tscc) + priv->tscc = (priv->tscc + 1) & 0x0F; + else { + /* TS discontinuity handling: */ + printk(KERN_WARNING "%lu: TS discontinuity: got %#x, " + "expected %#x.\n", priv->ts_count, ts[3] & 0x0F, priv->tscc); + /* Drop partly decoded SNDU, reset state, resync on PUSI. */ + if (priv->ule_skb) { + dev_kfree_skb( priv->ule_skb ); + /* Prepare for next SNDU. */ + // reset_ule(priv); moved to below. + dev->stats.rx_errors++; + dev->stats.rx_frame_errors++; + } + reset_ule(priv); + /* skip to next PUSI. */ + priv->need_pusi = 1; + continue; + } + /* If we still have an incomplete payload, but PUSI is + * set; some TS cells are missing. + * This is only possible here, if we missed exactly 16 TS + * cells (continuity counter wrap). */ + if (ts[1] & TS_PUSI) { + if (! priv->need_pusi) { + if (!(*from_where < (ts_remain-1)) || *from_where != priv->ule_sndu_remain) { + /* Pointer field is invalid. Drop this TS cell and any started ULE SNDU. */ + printk(KERN_WARNING "%lu: Invalid pointer " + "field: %u.\n", priv->ts_count, *from_where); + + /* Drop partly decoded SNDU, reset state, resync on PUSI. */ + if (priv->ule_skb) { + error = true; + dev_kfree_skb(priv->ule_skb); + } + + if (error || priv->ule_sndu_remain) { + dev->stats.rx_errors++; + dev->stats.rx_frame_errors++; + error = false; + } + + reset_ule(priv); + priv->need_pusi = 1; + continue; + } + /* Skip pointer field (we're processing a + * packed payload). */ + from_where += 1; + ts_remain -= 1; + } else + priv->need_pusi = 0; + + if (priv->ule_sndu_remain > 183) { + /* Current SNDU lacks more data than there could be available in the + * current TS cell. */ + dev->stats.rx_errors++; + dev->stats.rx_length_errors++; + printk(KERN_WARNING "%lu: Expected %d more SNDU bytes, but " + "got PUSI (pf %d, ts_remain %d). Flushing incomplete payload.\n", + priv->ts_count, priv->ule_sndu_remain, ts[4], ts_remain); + dev_kfree_skb(priv->ule_skb); + /* Prepare for next SNDU. */ + reset_ule(priv); + /* Resync: go to where pointer field points to: start of next ULE SNDU. */ + from_where += ts[4]; + ts_remain -= ts[4]; + } + } + } + + /* Check if new payload needs to be started. */ + if (priv->ule_skb == NULL) { + /* Start a new payload with skb. + * Find ULE header. It is only guaranteed that the + * length field (2 bytes) is contained in the current + * TS. + * Check ts_remain has to be >= 2 here. */ + if (ts_remain < 2) { + printk(KERN_WARNING "Invalid payload packing: only %d " + "bytes left in TS. Resyncing.\n", ts_remain); + priv->ule_sndu_len = 0; + priv->need_pusi = 1; + ts += TS_SZ; + continue; + } + + if (! priv->ule_sndu_len) { + /* Got at least two bytes, thus extrace the SNDU length. */ + priv->ule_sndu_len = from_where[0] << 8 | from_where[1]; + if (priv->ule_sndu_len & 0x8000) { + /* D-Bit is set: no dest mac present. */ + priv->ule_sndu_len &= 0x7FFF; + priv->ule_dbit = 1; + } else + priv->ule_dbit = 0; + + if (priv->ule_sndu_len < 5) { + printk(KERN_WARNING "%lu: Invalid ULE SNDU length %u. " + "Resyncing.\n", priv->ts_count, priv->ule_sndu_len); + dev->stats.rx_errors++; + dev->stats.rx_length_errors++; + priv->ule_sndu_len = 0; + priv->need_pusi = 1; + new_ts = 1; + ts += TS_SZ; + priv->ts_count++; + continue; + } + ts_remain -= 2; /* consume the 2 bytes SNDU length. */ + from_where += 2; + } + + priv->ule_sndu_remain = priv->ule_sndu_len + 2; + /* + * State of current TS: + * ts_remain (remaining bytes in the current TS cell) + * 0 ule_type is not available now, we need the next TS cell + * 1 the first byte of the ule_type is present + * >=2 full ULE header present, maybe some payload data as well. + */ + switch (ts_remain) { + case 1: + priv->ule_sndu_remain--; + priv->ule_sndu_type = from_where[0] << 8; + priv->ule_sndu_type_1 = 1; /* first byte of ule_type is set. */ + ts_remain -= 1; from_where += 1; + /* Continue w/ next TS. */ + case 0: + new_ts = 1; + ts += TS_SZ; + priv->ts_count++; + continue; + + default: /* complete ULE header is present in current TS. */ + /* Extract ULE type field. */ + if (priv->ule_sndu_type_1) { + priv->ule_sndu_type_1 = 0; + priv->ule_sndu_type |= from_where[0]; + from_where += 1; /* points to payload start. */ + ts_remain -= 1; + } else { + /* Complete type is present in new TS. */ + priv->ule_sndu_type = from_where[0] << 8 | from_where[1]; + from_where += 2; /* points to payload start. */ + ts_remain -= 2; + } + break; + } + + /* Allocate the skb (decoder target buffer) with the correct size, as follows: + * prepare for the largest case: bridged SNDU with MAC address (dbit = 0). */ + priv->ule_skb = dev_alloc_skb( priv->ule_sndu_len + ETH_HLEN + ETH_ALEN ); + if (priv->ule_skb == NULL) { + printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", + dev->name); + dev->stats.rx_dropped++; + return; + } + + /* This includes the CRC32 _and_ dest mac, if !dbit. */ + priv->ule_sndu_remain = priv->ule_sndu_len; + priv->ule_skb->dev = dev; + /* Leave space for Ethernet or bridged SNDU header (eth hdr plus one MAC addr). */ + skb_reserve( priv->ule_skb, ETH_HLEN + ETH_ALEN ); + } + + /* Copy data into our current skb. */ + how_much = min(priv->ule_sndu_remain, (int)ts_remain); + memcpy(skb_put(priv->ule_skb, how_much), from_where, how_much); + priv->ule_sndu_remain -= how_much; + ts_remain -= how_much; + from_where += how_much; + + /* Check for complete payload. */ + if (priv->ule_sndu_remain <= 0) { + /* Check CRC32, we've got it in our skb already. */ + __be16 ulen = htons(priv->ule_sndu_len); + __be16 utype = htons(priv->ule_sndu_type); + const u8 *tail; + struct kvec iov[3] = { + { &ulen, sizeof ulen }, + { &utype, sizeof utype }, + { priv->ule_skb->data, priv->ule_skb->len - 4 } + }; + u32 ule_crc = ~0L, expected_crc; + if (priv->ule_dbit) { + /* Set D-bit for CRC32 verification, + * if it was set originally. */ + ulen |= htons(0x8000); + } + + ule_crc = iov_crc32(ule_crc, iov, 3); + tail = skb_tail_pointer(priv->ule_skb); + expected_crc = *(tail - 4) << 24 | + *(tail - 3) << 16 | + *(tail - 2) << 8 | + *(tail - 1); + if (ule_crc != expected_crc) { + printk(KERN_WARNING "%lu: CRC32 check FAILED: %08x / %08x, SNDU len %d type %#x, ts_remain %d, next 2: %x.\n", + priv->ts_count, ule_crc, expected_crc, priv->ule_sndu_len, priv->ule_sndu_type, ts_remain, ts_remain > 2 ? *(unsigned short *)from_where : 0); + +#ifdef ULE_DEBUG + hexdump( iov[0].iov_base, iov[0].iov_len ); + hexdump( iov[1].iov_base, iov[1].iov_len ); + hexdump( iov[2].iov_base, iov[2].iov_len ); + + if (ule_where == ule_hist) { + hexdump( &ule_hist[98*TS_SZ], TS_SZ ); + hexdump( &ule_hist[99*TS_SZ], TS_SZ ); + } else if (ule_where == &ule_hist[TS_SZ]) { + hexdump( &ule_hist[99*TS_SZ], TS_SZ ); + hexdump( ule_hist, TS_SZ ); + } else { + hexdump( ule_where - TS_SZ - TS_SZ, TS_SZ ); + hexdump( ule_where - TS_SZ, TS_SZ ); + } + ule_dump = 1; +#endif + + dev->stats.rx_errors++; + dev->stats.rx_crc_errors++; + dev_kfree_skb(priv->ule_skb); + } else { + /* CRC32 verified OK. */ + u8 dest_addr[ETH_ALEN]; + static const u8 bc_addr[ETH_ALEN] = + { [ 0 ... ETH_ALEN-1] = 0xff }; + + /* CRC32 was OK. Remove it from skb. */ + priv->ule_skb->tail -= 4; + priv->ule_skb->len -= 4; + + if (!priv->ule_dbit) { + /* + * The destination MAC address is the + * next data in the skb. It comes + * before any extension headers. + * + * Check if the payload of this SNDU + * should be passed up the stack. + */ + register int drop = 0; + if (priv->rx_mode != RX_MODE_PROMISC) { + if (priv->ule_skb->data[0] & 0x01) { + /* multicast or broadcast */ + if (memcmp(priv->ule_skb->data, bc_addr, ETH_ALEN)) { + /* multicast */ + if (priv->rx_mode == RX_MODE_MULTI) { + int i; + for(i = 0; i < priv->multi_num && memcmp(priv->ule_skb->data, priv->multi_macs[i], ETH_ALEN); i++) + ; + if (i == priv->multi_num) + drop = 1; + } else if (priv->rx_mode != RX_MODE_ALL_MULTI) + drop = 1; /* no broadcast; */ + /* else: all multicast mode: accept all multicast packets */ + } + /* else: broadcast */ + } + else if (memcmp(priv->ule_skb->data, dev->dev_addr, ETH_ALEN)) + drop = 1; + /* else: destination address matches the MAC address of our receiver device */ + } + /* else: promiscuous mode; pass everything up the stack */ + + if (drop) { +#ifdef ULE_DEBUG + dprintk("Dropping SNDU: MAC destination address does not match: dest addr: "MAC_ADDR_PRINTFMT", dev addr: "MAC_ADDR_PRINTFMT"\n", + MAX_ADDR_PRINTFMT_ARGS(priv->ule_skb->data), MAX_ADDR_PRINTFMT_ARGS(dev->dev_addr)); +#endif + dev_kfree_skb(priv->ule_skb); + goto sndu_done; + } + else + { + skb_copy_from_linear_data(priv->ule_skb, + dest_addr, + ETH_ALEN); + skb_pull(priv->ule_skb, ETH_ALEN); + } + } + + /* Handle ULE Extension Headers. */ + if (priv->ule_sndu_type < ETH_P_802_3_MIN) { + /* There is an extension header. Handle it accordingly. */ + int l = handle_ule_extensions(priv); + if (l < 0) { + /* Mandatory extension header unknown or TEST SNDU. Drop it. */ + // printk( KERN_WARNING "Dropping SNDU, extension headers.\n" ); + dev_kfree_skb(priv->ule_skb); + goto sndu_done; + } + skb_pull(priv->ule_skb, l); + } + + /* + * Construct/assure correct ethernet header. + * Note: in bridged mode (priv->ule_bridged != + * 0) we already have the (original) ethernet + * header at the start of the payload (after + * optional dest. address and any extension + * headers). + */ + + if (!priv->ule_bridged) { + skb_push(priv->ule_skb, ETH_HLEN); + ethh = (struct ethhdr *)priv->ule_skb->data; + if (!priv->ule_dbit) { + /* dest_addr buffer is only valid if priv->ule_dbit == 0 */ + memcpy(ethh->h_dest, dest_addr, ETH_ALEN); + memset(ethh->h_source, 0, ETH_ALEN); + } + else /* zeroize source and dest */ + memset( ethh, 0, ETH_ALEN*2 ); + + ethh->h_proto = htons(priv->ule_sndu_type); + } + /* else: skb is in correct state; nothing to do. */ + priv->ule_bridged = 0; + + /* Stuff into kernel's protocol stack. */ + priv->ule_skb->protocol = dvb_net_eth_type_trans(priv->ule_skb, dev); + /* If D-bit is set (i.e. destination MAC address not present), + * receive the packet anyhow. */ + /* if (priv->ule_dbit && skb->pkt_type == PACKET_OTHERHOST) + priv->ule_skb->pkt_type = PACKET_HOST; */ + dev->stats.rx_packets++; + dev->stats.rx_bytes += priv->ule_skb->len; + netif_rx(priv->ule_skb); + } + sndu_done: + /* Prepare for next SNDU. */ + reset_ule(priv); + } + + /* More data in current TS (look at the bytes following the CRC32)? */ + if (ts_remain >= 2 && *((unsigned short *)from_where) != 0xFFFF) { + /* Next ULE SNDU starts right there. */ + new_ts = 0; + priv->ule_skb = NULL; + priv->ule_sndu_type_1 = 0; + priv->ule_sndu_len = 0; + // printk(KERN_WARNING "More data in current TS: [%#x %#x %#x %#x]\n", + // *(from_where + 0), *(from_where + 1), + // *(from_where + 2), *(from_where + 3)); + // printk(KERN_WARNING "ts @ %p, stopped @ %p:\n", ts, from_where + 0); + // hexdump(ts, 188); + } else { + new_ts = 1; + ts += TS_SZ; + priv->ts_count++; + if (priv->ule_skb == NULL) { + priv->need_pusi = 1; + priv->ule_sndu_type_1 = 0; + priv->ule_sndu_len = 0; + } + } + } /* for all available TS cells */ +} + +static int dvb_net_ts_callback(const u8 *buffer1, size_t buffer1_len, + const u8 *buffer2, size_t buffer2_len, + struct dmx_ts_feed *feed, enum dmx_success success) +{ + struct net_device *dev = feed->priv; + + if (buffer2) + printk(KERN_WARNING "buffer2 not NULL: %p.\n", buffer2); + if (buffer1_len > 32768) + printk(KERN_WARNING "length > 32k: %zu.\n", buffer1_len); + /* printk("TS callback: %u bytes, %u TS cells @ %p.\n", + buffer1_len, buffer1_len / TS_SZ, buffer1); */ + dvb_net_ule(dev, buffer1, buffer1_len); + return 0; +} + + +static void dvb_net_sec(struct net_device *dev, + const u8 *pkt, int pkt_len) +{ + u8 *eth; + struct sk_buff *skb; + struct net_device_stats *stats = &dev->stats; + int snap = 0; + + /* note: pkt_len includes a 32bit checksum */ + if (pkt_len < 16) { + printk("%s: IP/MPE packet length = %d too small.\n", + dev->name, pkt_len); + stats->rx_errors++; + stats->rx_length_errors++; + return; + } +/* it seems some ISPs manage to screw up here, so we have to + * relax the error checks... */ +#if 0 + if ((pkt[5] & 0xfd) != 0xc1) { + /* drop scrambled or broken packets */ +#else + if ((pkt[5] & 0x3c) != 0x00) { + /* drop scrambled */ +#endif + stats->rx_errors++; + stats->rx_crc_errors++; + return; + } + if (pkt[5] & 0x02) { + /* handle LLC/SNAP, see rfc-1042 */ + if (pkt_len < 24 || memcmp(&pkt[12], "\xaa\xaa\x03\0\0\0", 6)) { + stats->rx_dropped++; + return; + } + snap = 8; + } + if (pkt[7]) { + /* FIXME: assemble datagram from multiple sections */ + stats->rx_errors++; + stats->rx_frame_errors++; + return; + } + + /* we have 14 byte ethernet header (ip header follows); + * 12 byte MPE header; 4 byte checksum; + 2 byte alignment, 8 byte LLC/SNAP + */ + if (!(skb = dev_alloc_skb(pkt_len - 4 - 12 + 14 + 2 - snap))) { + //printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); + stats->rx_dropped++; + return; + } + skb_reserve(skb, 2); /* longword align L3 header */ + skb->dev = dev; + + /* copy L3 payload */ + eth = (u8 *) skb_put(skb, pkt_len - 12 - 4 + 14 - snap); + memcpy(eth + 14, pkt + 12 + snap, pkt_len - 12 - 4 - snap); + + /* create ethernet header: */ + eth[0]=pkt[0x0b]; + eth[1]=pkt[0x0a]; + eth[2]=pkt[0x09]; + eth[3]=pkt[0x08]; + eth[4]=pkt[0x04]; + eth[5]=pkt[0x03]; + + eth[6]=eth[7]=eth[8]=eth[9]=eth[10]=eth[11]=0; + + if (snap) { + eth[12] = pkt[18]; + eth[13] = pkt[19]; + } else { + /* protocol numbers are from rfc-1700 or + * http://www.iana.org/assignments/ethernet-numbers + */ + if (pkt[12] >> 4 == 6) { /* version field from IP header */ + eth[12] = 0x86; /* IPv6 */ + eth[13] = 0xdd; + } else { + eth[12] = 0x08; /* IPv4 */ + eth[13] = 0x00; + } + } + + skb->protocol = dvb_net_eth_type_trans(skb, dev); + + stats->rx_packets++; + stats->rx_bytes+=skb->len; + netif_rx(skb); +} + +static int dvb_net_sec_callback(const u8 *buffer1, size_t buffer1_len, + const u8 *buffer2, size_t buffer2_len, + struct dmx_section_filter *filter, + enum dmx_success success) +{ + struct net_device *dev = filter->priv; + + /** + * we rely on the DVB API definition where exactly one complete + * section is delivered in buffer1 + */ + dvb_net_sec (dev, buffer1, buffer1_len); + return 0; +} + +static int dvb_net_tx(struct sk_buff *skb, struct net_device *dev) +{ + dev_kfree_skb(skb); + return NETDEV_TX_OK; +} + +static u8 mask_normal[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +static u8 mask_allmulti[6]={0xff, 0xff, 0xff, 0x00, 0x00, 0x00}; +static u8 mac_allmulti[6]={0x01, 0x00, 0x5e, 0x00, 0x00, 0x00}; +static u8 mask_promisc[6]={0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +static int dvb_net_filter_sec_set(struct net_device *dev, + struct dmx_section_filter **secfilter, + u8 *mac, u8 *mac_mask) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + int ret; + + *secfilter=NULL; + ret = priv->secfeed->allocate_filter(priv->secfeed, secfilter); + if (ret<0) { + printk("%s: could not get filter\n", dev->name); + return ret; + } + + (*secfilter)->priv=(void *) dev; + + memset((*secfilter)->filter_value, 0x00, DMX_MAX_FILTER_SIZE); + memset((*secfilter)->filter_mask, 0x00, DMX_MAX_FILTER_SIZE); + memset((*secfilter)->filter_mode, 0xff, DMX_MAX_FILTER_SIZE); + + (*secfilter)->filter_value[0]=0x3e; + (*secfilter)->filter_value[3]=mac[5]; + (*secfilter)->filter_value[4]=mac[4]; + (*secfilter)->filter_value[8]=mac[3]; + (*secfilter)->filter_value[9]=mac[2]; + (*secfilter)->filter_value[10]=mac[1]; + (*secfilter)->filter_value[11]=mac[0]; + + (*secfilter)->filter_mask[0] = 0xff; + (*secfilter)->filter_mask[3] = mac_mask[5]; + (*secfilter)->filter_mask[4] = mac_mask[4]; + (*secfilter)->filter_mask[8] = mac_mask[3]; + (*secfilter)->filter_mask[9] = mac_mask[2]; + (*secfilter)->filter_mask[10] = mac_mask[1]; + (*secfilter)->filter_mask[11]=mac_mask[0]; + + dprintk("%s: filter mac=%pM\n", dev->name, mac); + dprintk("%s: filter mask=%pM\n", dev->name, mac_mask); + + return 0; +} + +static int dvb_net_feed_start(struct net_device *dev) +{ + int ret = 0, i; + struct dvb_net_priv *priv = netdev_priv(dev); + struct dmx_demux *demux = priv->demux; + unsigned char *mac = (unsigned char *) dev->dev_addr; + + dprintk("%s: rx_mode %i\n", __func__, priv->rx_mode); + mutex_lock(&priv->mutex); + if (priv->tsfeed || priv->secfeed || priv->secfilter || priv->multi_secfilter[0]) + printk("%s: BUG %d\n", __func__, __LINE__); + + priv->secfeed=NULL; + priv->secfilter=NULL; + priv->tsfeed = NULL; + + if (priv->feedtype == DVB_NET_FEEDTYPE_MPE) { + dprintk("%s: alloc secfeed\n", __func__); + ret=demux->allocate_section_feed(demux, &priv->secfeed, + dvb_net_sec_callback); + if (ret<0) { + printk("%s: could not allocate section feed\n", dev->name); + goto error; + } + + ret = priv->secfeed->set(priv->secfeed, priv->pid, 32768, 1); + + if (ret<0) { + printk("%s: could not set section feed\n", dev->name); + priv->demux->release_section_feed(priv->demux, priv->secfeed); + priv->secfeed=NULL; + goto error; + } + + if (priv->rx_mode != RX_MODE_PROMISC) { + dprintk("%s: set secfilter\n", __func__); + dvb_net_filter_sec_set(dev, &priv->secfilter, mac, mask_normal); + } + + switch (priv->rx_mode) { + case RX_MODE_MULTI: + for (i = 0; i < priv->multi_num; i++) { + dprintk("%s: set multi_secfilter[%d]\n", __func__, i); + dvb_net_filter_sec_set(dev, &priv->multi_secfilter[i], + priv->multi_macs[i], mask_normal); + } + break; + case RX_MODE_ALL_MULTI: + priv->multi_num=1; + dprintk("%s: set multi_secfilter[0]\n", __func__); + dvb_net_filter_sec_set(dev, &priv->multi_secfilter[0], + mac_allmulti, mask_allmulti); + break; + case RX_MODE_PROMISC: + priv->multi_num=0; + dprintk("%s: set secfilter\n", __func__); + dvb_net_filter_sec_set(dev, &priv->secfilter, mac, mask_promisc); + break; + } + + dprintk("%s: start filtering\n", __func__); + priv->secfeed->start_filtering(priv->secfeed); + } else if (priv->feedtype == DVB_NET_FEEDTYPE_ULE) { + struct timespec timeout = { 0, 10000000 }; // 10 msec + + /* we have payloads encapsulated in TS */ + dprintk("%s: alloc tsfeed\n", __func__); + ret = demux->allocate_ts_feed(demux, &priv->tsfeed, dvb_net_ts_callback); + if (ret < 0) { + printk("%s: could not allocate ts feed\n", dev->name); + goto error; + } + + /* Set netdevice pointer for ts decaps callback. */ + priv->tsfeed->priv = (void *)dev; + ret = priv->tsfeed->set(priv->tsfeed, + priv->pid, /* pid */ + TS_PACKET, /* type */ + DMX_PES_OTHER, /* pes type */ + 32768, /* circular buffer size */ + timeout /* timeout */ + ); + + if (ret < 0) { + printk("%s: could not set ts feed\n", dev->name); + priv->demux->release_ts_feed(priv->demux, priv->tsfeed); + priv->tsfeed = NULL; + goto error; + } + + dprintk("%s: start filtering\n", __func__); + priv->tsfeed->start_filtering(priv->tsfeed); + } else + ret = -EINVAL; + +error: + mutex_unlock(&priv->mutex); + return ret; +} + +static int dvb_net_feed_stop(struct net_device *dev) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + int i, ret = 0; + + dprintk("%s\n", __func__); + mutex_lock(&priv->mutex); + if (priv->feedtype == DVB_NET_FEEDTYPE_MPE) { + if (priv->secfeed) { + if (priv->secfeed->is_filtering) { + dprintk("%s: stop secfeed\n", __func__); + priv->secfeed->stop_filtering(priv->secfeed); + } + + if (priv->secfilter) { + dprintk("%s: release secfilter\n", __func__); + priv->secfeed->release_filter(priv->secfeed, + priv->secfilter); + priv->secfilter=NULL; + } + + for (i=0; imulti_num; i++) { + if (priv->multi_secfilter[i]) { + dprintk("%s: release multi_filter[%d]\n", + __func__, i); + priv->secfeed->release_filter(priv->secfeed, + priv->multi_secfilter[i]); + priv->multi_secfilter[i] = NULL; + } + } + + priv->demux->release_section_feed(priv->demux, priv->secfeed); + priv->secfeed = NULL; + } else + printk("%s: no feed to stop\n", dev->name); + } else if (priv->feedtype == DVB_NET_FEEDTYPE_ULE) { + if (priv->tsfeed) { + if (priv->tsfeed->is_filtering) { + dprintk("%s: stop tsfeed\n", __func__); + priv->tsfeed->stop_filtering(priv->tsfeed); + } + priv->demux->release_ts_feed(priv->demux, priv->tsfeed); + priv->tsfeed = NULL; + } + else + printk("%s: no ts feed to stop\n", dev->name); + } else + ret = -EINVAL; + mutex_unlock(&priv->mutex); + return ret; +} + + +static int dvb_set_mc_filter(struct net_device *dev, unsigned char *addr) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + + if (priv->multi_num == DVB_NET_MULTICAST_MAX) + return -ENOMEM; + + memcpy(priv->multi_macs[priv->multi_num], addr, ETH_ALEN); + + priv->multi_num++; + return 0; +} + + +static void wq_set_multicast_list (struct work_struct *work) +{ + struct dvb_net_priv *priv = + container_of(work, struct dvb_net_priv, set_multicast_list_wq); + struct net_device *dev = priv->net; + + dvb_net_feed_stop(dev); + priv->rx_mode = RX_MODE_UNI; + netif_addr_lock_bh(dev); + + if (dev->flags & IFF_PROMISC) { + dprintk("%s: promiscuous mode\n", dev->name); + priv->rx_mode = RX_MODE_PROMISC; + } else if ((dev->flags & IFF_ALLMULTI)) { + dprintk("%s: allmulti mode\n", dev->name); + priv->rx_mode = RX_MODE_ALL_MULTI; + } else if (!netdev_mc_empty(dev)) { + struct netdev_hw_addr *ha; + + dprintk("%s: set_mc_list, %d entries\n", + dev->name, netdev_mc_count(dev)); + + priv->rx_mode = RX_MODE_MULTI; + priv->multi_num = 0; + + netdev_for_each_mc_addr(ha, dev) + dvb_set_mc_filter(dev, ha->addr); + } + + netif_addr_unlock_bh(dev); + dvb_net_feed_start(dev); +} + + +static void dvb_net_set_multicast_list (struct net_device *dev) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + schedule_work(&priv->set_multicast_list_wq); +} + + +static void wq_restart_net_feed (struct work_struct *work) +{ + struct dvb_net_priv *priv = + container_of(work, struct dvb_net_priv, restart_net_feed_wq); + struct net_device *dev = priv->net; + + if (netif_running(dev)) { + dvb_net_feed_stop(dev); + dvb_net_feed_start(dev); + } +} + + +static int dvb_net_set_mac (struct net_device *dev, void *p) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + struct sockaddr *addr=p; + + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + if (netif_running(dev)) + schedule_work(&priv->restart_net_feed_wq); + + return 0; +} + + +static int dvb_net_open(struct net_device *dev) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + + priv->in_use++; + dvb_net_feed_start(dev); + return 0; +} + + +static int dvb_net_stop(struct net_device *dev) +{ + struct dvb_net_priv *priv = netdev_priv(dev); + + priv->in_use--; + return dvb_net_feed_stop(dev); +} + +static const struct header_ops dvb_header_ops = { + .create = eth_header, + .parse = eth_header_parse, + .rebuild = eth_rebuild_header, +}; + + +static const struct net_device_ops dvb_netdev_ops = { + .ndo_open = dvb_net_open, + .ndo_stop = dvb_net_stop, + .ndo_start_xmit = dvb_net_tx, + .ndo_set_rx_mode = dvb_net_set_multicast_list, + .ndo_set_mac_address = dvb_net_set_mac, + .ndo_change_mtu = eth_change_mtu, + .ndo_validate_addr = eth_validate_addr, +}; + +static void dvb_net_setup(struct net_device *dev) +{ + ether_setup(dev); + + dev->header_ops = &dvb_header_ops; + dev->netdev_ops = &dvb_netdev_ops; + dev->mtu = 4096; + + dev->flags |= IFF_NOARP; +} + +static int get_if(struct dvb_net *dvbnet) +{ + int i; + + for (i=0; istate[i]) + break; + + if (i == DVB_NET_DEVICES_MAX) + return -1; + + dvbnet->state[i]=1; + return i; +} + +static int dvb_net_add_if(struct dvb_net *dvbnet, u16 pid, u8 feedtype) +{ + struct net_device *net; + struct dvb_net_priv *priv; + int result; + int if_num; + + if (feedtype != DVB_NET_FEEDTYPE_MPE && feedtype != DVB_NET_FEEDTYPE_ULE) + return -EINVAL; + if ((if_num = get_if(dvbnet)) < 0) + return -EINVAL; + + net = alloc_netdev(sizeof(struct dvb_net_priv), "dvb", dvb_net_setup); + if (!net) + return -ENOMEM; + + if (dvbnet->dvbdev->id) + snprintf(net->name, IFNAMSIZ, "dvb%d%u%d", + dvbnet->dvbdev->adapter->num, dvbnet->dvbdev->id, if_num); + else + /* compatibility fix to keep dvb0_0 format */ + snprintf(net->name, IFNAMSIZ, "dvb%d_%d", + dvbnet->dvbdev->adapter->num, if_num); + + net->addr_len = 6; + memcpy(net->dev_addr, dvbnet->dvbdev->adapter->proposed_mac, 6); + + dvbnet->device[if_num] = net; + + priv = netdev_priv(net); + priv->net = net; + priv->demux = dvbnet->demux; + priv->pid = pid; + priv->rx_mode = RX_MODE_UNI; + priv->need_pusi = 1; + priv->tscc = 0; + priv->feedtype = feedtype; + reset_ule(priv); + + INIT_WORK(&priv->set_multicast_list_wq, wq_set_multicast_list); + INIT_WORK(&priv->restart_net_feed_wq, wq_restart_net_feed); + mutex_init(&priv->mutex); + + net->base_addr = pid; + + if ((result = register_netdev(net)) < 0) { + dvbnet->device[if_num] = NULL; + free_netdev(net); + return result; + } + printk("dvb_net: created network interface %s\n", net->name); + + return if_num; +} + +static int dvb_net_remove_if(struct dvb_net *dvbnet, unsigned long num) +{ + struct net_device *net = dvbnet->device[num]; + struct dvb_net_priv *priv; + + if (!dvbnet->state[num]) + return -EINVAL; + priv = netdev_priv(net); + if (priv->in_use) + return -EBUSY; + + dvb_net_stop(net); + flush_work(&priv->set_multicast_list_wq); + flush_work(&priv->restart_net_feed_wq); + printk("dvb_net: removed network interface %s\n", net->name); + unregister_netdev(net); + dvbnet->state[num]=0; + dvbnet->device[num] = NULL; + free_netdev(net); + + return 0; +} + +static int dvb_net_do_ioctl(struct file *file, + unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_net *dvbnet = dvbdev->priv; + int ret = 0; + + if (((file->f_flags&O_ACCMODE)==O_RDONLY)) + return -EPERM; + + if (mutex_lock_interruptible(&dvbnet->ioctl_mutex)) + return -ERESTARTSYS; + + switch (cmd) { + case NET_ADD_IF: + { + struct dvb_net_if *dvbnetif = parg; + int result; + + if (!capable(CAP_SYS_ADMIN)) { + ret = -EPERM; + goto ioctl_error; + } + + if (!try_module_get(dvbdev->adapter->module)) { + ret = -EPERM; + goto ioctl_error; + } + + result=dvb_net_add_if(dvbnet, dvbnetif->pid, dvbnetif->feedtype); + if (result<0) { + module_put(dvbdev->adapter->module); + ret = result; + goto ioctl_error; + } + dvbnetif->if_num=result; + break; + } + case NET_GET_IF: + { + struct net_device *netdev; + struct dvb_net_priv *priv_data; + struct dvb_net_if *dvbnetif = parg; + + if (dvbnetif->if_num >= DVB_NET_DEVICES_MAX || + !dvbnet->state[dvbnetif->if_num]) { + ret = -EINVAL; + goto ioctl_error; + } + + netdev = dvbnet->device[dvbnetif->if_num]; + + priv_data = netdev_priv(netdev); + dvbnetif->pid=priv_data->pid; + dvbnetif->feedtype=priv_data->feedtype; + break; + } + case NET_REMOVE_IF: + { + if (!capable(CAP_SYS_ADMIN)) { + ret = -EPERM; + goto ioctl_error; + } + if ((unsigned long) parg >= DVB_NET_DEVICES_MAX) { + ret = -EINVAL; + goto ioctl_error; + } + ret = dvb_net_remove_if(dvbnet, (unsigned long) parg); + if (!ret) + module_put(dvbdev->adapter->module); + break; + } + + /* binary compatibility cruft */ + case __NET_ADD_IF_OLD: + { + struct __dvb_net_if_old *dvbnetif = parg; + int result; + + if (!capable(CAP_SYS_ADMIN)) { + ret = -EPERM; + goto ioctl_error; + } + + if (!try_module_get(dvbdev->adapter->module)) { + ret = -EPERM; + goto ioctl_error; + } + + result=dvb_net_add_if(dvbnet, dvbnetif->pid, DVB_NET_FEEDTYPE_MPE); + if (result<0) { + module_put(dvbdev->adapter->module); + ret = result; + goto ioctl_error; + } + dvbnetif->if_num=result; + break; + } + case __NET_GET_IF_OLD: + { + struct net_device *netdev; + struct dvb_net_priv *priv_data; + struct __dvb_net_if_old *dvbnetif = parg; + + if (dvbnetif->if_num >= DVB_NET_DEVICES_MAX || + !dvbnet->state[dvbnetif->if_num]) { + ret = -EINVAL; + goto ioctl_error; + } + + netdev = dvbnet->device[dvbnetif->if_num]; + + priv_data = netdev_priv(netdev); + dvbnetif->pid=priv_data->pid; + break; + } + default: + ret = -ENOTTY; + break; + } + +ioctl_error: + mutex_unlock(&dvbnet->ioctl_mutex); + return ret; +} + +static long dvb_net_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return dvb_usercopy(file, cmd, arg, dvb_net_do_ioctl); +} + +static int dvb_net_close(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_net *dvbnet = dvbdev->priv; + + dvb_generic_release(inode, file); + + if(dvbdev->users == 1 && dvbnet->exit == 1) + wake_up(&dvbdev->wait_queue); + return 0; +} + + +static const struct file_operations dvb_net_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = dvb_net_ioctl, + .open = dvb_generic_open, + .release = dvb_net_close, + .llseek = noop_llseek, +}; + +static struct dvb_device dvbdev_net = { + .priv = NULL, + .users = 1, + .writers = 1, + .fops = &dvb_net_fops, +}; + + +void dvb_net_release (struct dvb_net *dvbnet) +{ + int i; + + dvbnet->exit = 1; + if (dvbnet->dvbdev->users < 1) + wait_event(dvbnet->dvbdev->wait_queue, + dvbnet->dvbdev->users==1); + + dvb_unregister_device(dvbnet->dvbdev); + + for (i=0; istate[i]) + continue; + dvb_net_remove_if(dvbnet, i); + } +} +EXPORT_SYMBOL(dvb_net_release); + + +int dvb_net_init (struct dvb_adapter *adap, struct dvb_net *dvbnet, + struct dmx_demux *dmx) +{ + int i; + + mutex_init(&dvbnet->ioctl_mutex); + dvbnet->demux = dmx; + + for (i=0; istate[i] = 0; + + return dvb_register_device(adap, &dvbnet->dvbdev, &dvbdev_net, + dvbnet, DVB_DEVICE_NET); +} +EXPORT_SYMBOL(dvb_net_init); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_net.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,67 @@ +/* + * dvb_net.h + * + * Copyright (C) 2001 Ralph Metzler for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVB_NET_H_ +#define _DVB_NET_H_ + +#include +#include +#include +#include +#include + +#include "dvbdev.h" + +#define DVB_NET_DEVICES_MAX 10 + +#ifdef CONFIG_DVB_NET + +struct dvb_net { + struct dvb_device *dvbdev; + struct net_device *device[DVB_NET_DEVICES_MAX]; + int state[DVB_NET_DEVICES_MAX]; + unsigned int exit:1; + struct dmx_demux *demux; + struct mutex ioctl_mutex; +}; + +void dvb_net_release(struct dvb_net *); +int dvb_net_init(struct dvb_adapter *, struct dvb_net *, struct dmx_demux *); + +#else + +struct dvb_net { + struct dvb_device *dvbdev; +}; + +static inline void dvb_net_release(struct dvb_net *dvbnet) +{ +} + +static inline int dvb_net_init(struct dvb_adapter *adap, + struct dvb_net *dvbnet, struct dmx_demux *dmx) +{ + return 0; +} + +#endif /* ifdef CONFIG_DVB_NET */ + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,235 @@ +#include +#include "dvb_netstream.h" + +static ssize_t ns_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + printk("%s\n", __func__); + return 0; +} + +static ssize_t ns_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ + printk("%s\n", __func__); + return 0; +} + +static unsigned int ns_poll(struct file *file, poll_table *wait) +{ + printk("%s\n", __func__); + return 0; +} + +static int ns_stop(struct dvbnss *nss) +{ + struct dvb_netstream *ns = nss->ns; + + mutex_lock(&ns->mutex); + if (nss->running && ns->stop) { + ns->stop(nss); + nss->running = 0; + } + mutex_unlock(&ns->mutex); + return 0; +} + +static int ns_release(struct inode *inode, struct file *file) +{ + struct dvbnss *nss = file->private_data; + struct dvb_netstream *ns = nss->ns; + + ns_stop(nss); + if (ns->free) + ns->free(nss); + mutex_lock(&ns->mutex); + list_del(&nss->nssl); + mutex_unlock(&ns->mutex); + vfree(nss); + return 0; +} + +static int ns_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_netstream *ns = dvbdev->priv; + struct dvbnss *nss; + + nss = vmalloc(sizeof(*nss)); + if (!nss) + return -ENOMEM; + nss->ns = ns; + if (ns->alloc && ns->alloc(nss) < 0) { + vfree(nss); + return -EBUSY; + } + file->private_data = nss; + nss->running = 0; + mutex_lock(&ns->mutex); + list_add(&nss->nssl, &ns->nssl); + mutex_unlock(&ns->mutex); + return 0; +} + +static int set_net(struct dvbnss *nss, struct dvb_ns_params *p) +{ + return 0; +} + +static int do_ioctl(struct file *file, unsigned int cmd, void *parg) +{ + struct dvbnss *nss = file->private_data; + struct dvb_netstream *ns = nss->ns; + //unsigned long arg = (unsigned long) parg; + int ret = 0; + + switch (cmd) { + case NS_SET_RTCP_MSG: + { + struct dvb_ns_rtcp *rtcpm = parg; + + if (ns->set_rtcp_msg) { + //printk("%s calling NS_SET_RTCP_MSG\n", __func__); + ret = ns->set_rtcp_msg(nss, rtcpm->msg, rtcpm->len); + } + break; + } + + case NS_SET_NET: + memcpy(&nss->params, parg, sizeof(nss->params)); + if (ns->set_net) { + ret = ns->set_net(nss); + } else + ret = set_net(nss, (struct dvb_ns_params *) parg); + break; + + case NS_START: + mutex_lock(&ns->mutex); + if (nss->running) { + ret = -EBUSY; + } else if (ns->start) { + ret = ns->start(nss); + nss->running = 1; + } + mutex_unlock(&ns->mutex); + break; + + case NS_STOP: + ns_stop(nss); + break; + + case NS_SET_PACKETS: + { + struct dvb_ns_packet *packet = parg; + if (ns->set_ts_packets) { + ret = ns->set_ts_packets(nss, packet->buf, packet->count * 188); + } + break; + } + + case NS_INSERT_PACKETS: + { + u8 count = *(u8 *) parg; + if (ns->insert_ts_packets) + ret = ns->insert_ts_packets(nss, count); + break; + } + + case NS_SET_PID: + { + u16 pid = *(u16 *) parg; + u16 byte = (pid & 0x1fff) >> 3; + u8 bit = 1 << (pid & 7); + + if (pid & 0x2000) { + if (pid & 0x8000) + memset(nss->pids, 0xff, 0x400); + else + memset(nss->pids, 0x00, 0x400); + } else { + if (pid & 0x8000) + nss->pids[byte] |= bit; + else + nss->pids[byte] &= ~bit; + } + if (ns->set_pid) + ret = ns->set_pid(nss, pid); + break; + } + + case NS_SET_PIDS: + ret = copy_from_user(nss->pids, *(u8 **) parg, 0x400); + if (ret < 0) + return ret; + if (ns->set_pids) + ret = ns->set_pids(nss); + break; + + case NS_SET_CI: + { + u8 ci = *(u8 *) parg; + + if (nss->running) + ret = -EBUSY; + else if (ns->set_ci) + ret = ns->set_ci(nss, ci); + break; + } + + default: + ret = -EINVAL; + break; + } + return ret; +} + +static long ns_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return dvb_usercopy(file, cmd, arg, do_ioctl); +} + +static const struct file_operations ns_fops = { + .owner = THIS_MODULE, + .read = ns_read, + .write = ns_write, + .open = ns_open, + .release = ns_release, + .poll = ns_poll, + .mmap = 0, + .unlocked_ioctl = ns_ioctl, +}; + +static struct dvb_device ns_dev = { + .priv = 0, + .readers = 1, + .writers = 1, + .users = 1, + .fops = &ns_fops, +}; + + +int dvb_netstream_init(struct dvb_adapter *dvb_adapter, struct dvb_netstream *ns) +{ + mutex_init(&ns->mutex); + spin_lock_init(&ns->lock); + ns->exit = 0; + dvb_register_device(dvb_adapter, &ns->dvbdev, &ns_dev, ns, + DVB_DEVICE_NS); + INIT_LIST_HEAD(&ns->nssl); + return 0; +} + +EXPORT_SYMBOL(dvb_netstream_init); + +void dvb_netstream_release(struct dvb_netstream *ns) +{ + ns->exit=1; + if (ns->dvbdev->users > 1) { + wait_event(ns->dvbdev->wait_queue, + ns->dvbdev->users == 1); + } + dvb_unregister_device(ns->dvbdev); +} + +EXPORT_SYMBOL(dvb_netstream_release); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_netstream.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,70 @@ +#ifndef _DVB_NETSTREAM_H_ +#define _DVB_NETSTREAM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvbdev.h" + +#define DVBNS_MAXPIDS 32 + +struct dvbnss { + struct dvb_netstream *ns; + void *priv; + + u8 pids[1024]; + u8 packet[1328]; + u32 pp; + + struct socket *sock; + struct sockaddr_in sadr; + u32 sn; + + struct dvb_ns_params params; + + struct list_head nssl; + int running; +}; + +#define MAX_DVBNSS 32 + +struct dvb_netstream { + void *priv; + + struct mutex mutex; + spinlock_t lock; + struct dvb_device *dvbdev; + int exit; + + struct list_head nssl; + + int (*set_net) (struct dvbnss *); + int (*set_pid) (struct dvbnss *, u16); + int (*set_pids) (struct dvbnss *); + int (*set_ci) (struct dvbnss *, u8); + int (*set_rtcp_msg) (struct dvbnss *, u8 *, u32); + int (*set_ts_packets) (struct dvbnss *, u8 *, u32); + int (*insert_ts_packets) (struct dvbnss *, u8); + int (*start) (struct dvbnss *); + int (*stop) (struct dvbnss *); + int (*alloc) (struct dvbnss *); + void (*free) (struct dvbnss *); + +}; + + +void dvb_netstream_release(struct dvb_netstream *); +int dvb_netstream_init(struct dvb_adapter *, struct dvb_netstream *); + + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,299 @@ +/* + * + * dvb_ringbuffer.c: ring buffer implementation for the dvb driver + * + * Copyright (C) 2003 Oliver Endriss + * Copyright (C) 2004 Andrew de Quincey + * + * based on code originally found in av7110.c & dvb_ci.c: + * Copyright (C) 1999-2003 Ralph Metzler + * & Marcus Metzler for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + + + +#include +#include +#include +#include +#include +#include + +#include "dvb_ringbuffer.h" + +#define PKT_READY 0 +#define PKT_DISPOSED 1 + + +void dvb_ringbuffer_init(struct dvb_ringbuffer *rbuf, void *data, size_t len) +{ + rbuf->pread=rbuf->pwrite=0; + rbuf->data=data; + rbuf->size=len; + rbuf->error=0; + + init_waitqueue_head(&rbuf->queue); + + spin_lock_init(&(rbuf->lock)); +} + + + +int dvb_ringbuffer_empty(struct dvb_ringbuffer *rbuf) +{ + return (rbuf->pread==rbuf->pwrite); +} + + + +ssize_t dvb_ringbuffer_free(struct dvb_ringbuffer *rbuf) +{ + ssize_t free; + + free = rbuf->pread - rbuf->pwrite; + if (free <= 0) + free += rbuf->size; + return free-1; +} + + + +ssize_t dvb_ringbuffer_avail(struct dvb_ringbuffer *rbuf) +{ + ssize_t avail; + + avail = rbuf->pwrite - rbuf->pread; + if (avail < 0) + avail += rbuf->size; + return avail; +} + + + +void dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf) +{ + rbuf->pread = rbuf->pwrite; + rbuf->error = 0; +} +EXPORT_SYMBOL(dvb_ringbuffer_flush); + +void dvb_ringbuffer_reset(struct dvb_ringbuffer *rbuf) +{ + rbuf->pread = rbuf->pwrite = 0; + rbuf->error = 0; +} + +void dvb_ringbuffer_flush_spinlock_wakeup(struct dvb_ringbuffer *rbuf) +{ + unsigned long flags; + + spin_lock_irqsave(&rbuf->lock, flags); + dvb_ringbuffer_flush(rbuf); + spin_unlock_irqrestore(&rbuf->lock, flags); + + wake_up(&rbuf->queue); +} + +ssize_t dvb_ringbuffer_read_user(struct dvb_ringbuffer *rbuf, u8 __user *buf, size_t len) +{ + size_t todo = len; + size_t split; + + split = (rbuf->pread + len > rbuf->size) ? rbuf->size - rbuf->pread : 0; + if (split > 0) { + if (copy_to_user(buf, rbuf->data+rbuf->pread, split)) + return -EFAULT; + buf += split; + todo -= split; + rbuf->pread = 0; + } + if (copy_to_user(buf, rbuf->data+rbuf->pread, todo)) + return -EFAULT; + + rbuf->pread = (rbuf->pread + todo) % rbuf->size; + + return len; +} + +void dvb_ringbuffer_read(struct dvb_ringbuffer *rbuf, u8 *buf, size_t len) +{ + size_t todo = len; + size_t split; + + split = (rbuf->pread + len > rbuf->size) ? rbuf->size - rbuf->pread : 0; + if (split > 0) { + memcpy(buf, rbuf->data+rbuf->pread, split); + buf += split; + todo -= split; + rbuf->pread = 0; + } + memcpy(buf, rbuf->data+rbuf->pread, todo); + + rbuf->pread = (rbuf->pread + todo) % rbuf->size; +} + + +ssize_t dvb_ringbuffer_write(struct dvb_ringbuffer *rbuf, const u8 *buf, size_t len) +{ + size_t todo = len; + size_t split; + + split = (rbuf->pwrite + len > rbuf->size) ? rbuf->size - rbuf->pwrite : 0; + + if (split > 0) { + memcpy(rbuf->data+rbuf->pwrite, buf, split); + buf += split; + todo -= split; + rbuf->pwrite = 0; + } + memcpy(rbuf->data+rbuf->pwrite, buf, todo); + rbuf->pwrite = (rbuf->pwrite + todo) % rbuf->size; + + return len; +} + +ssize_t dvb_ringbuffer_pkt_write(struct dvb_ringbuffer *rbuf, u8* buf, size_t len) +{ + int status; + ssize_t oldpwrite = rbuf->pwrite; + + DVB_RINGBUFFER_WRITE_BYTE(rbuf, len >> 8); + DVB_RINGBUFFER_WRITE_BYTE(rbuf, len & 0xff); + DVB_RINGBUFFER_WRITE_BYTE(rbuf, PKT_READY); + status = dvb_ringbuffer_write(rbuf, buf, len); + + if (status < 0) rbuf->pwrite = oldpwrite; + return status; +} + +ssize_t dvb_ringbuffer_pkt_read_user(struct dvb_ringbuffer *rbuf, size_t idx, + int offset, u8 __user *buf, size_t len) +{ + size_t todo; + size_t split; + size_t pktlen; + + pktlen = rbuf->data[idx] << 8; + pktlen |= rbuf->data[(idx + 1) % rbuf->size]; + if (offset > pktlen) return -EINVAL; + if ((offset + len) > pktlen) len = pktlen - offset; + + idx = (idx + DVB_RINGBUFFER_PKTHDRSIZE + offset) % rbuf->size; + todo = len; + split = ((idx + len) > rbuf->size) ? rbuf->size - idx : 0; + if (split > 0) { + if (copy_to_user(buf, rbuf->data+idx, split)) + return -EFAULT; + buf += split; + todo -= split; + idx = 0; + } + if (copy_to_user(buf, rbuf->data+idx, todo)) + return -EFAULT; + + return len; +} + +ssize_t dvb_ringbuffer_pkt_read(struct dvb_ringbuffer *rbuf, size_t idx, + int offset, u8* buf, size_t len) +{ + size_t todo; + size_t split; + size_t pktlen; + + pktlen = rbuf->data[idx] << 8; + pktlen |= rbuf->data[(idx + 1) % rbuf->size]; + if (offset > pktlen) return -EINVAL; + if ((offset + len) > pktlen) len = pktlen - offset; + + idx = (idx + DVB_RINGBUFFER_PKTHDRSIZE + offset) % rbuf->size; + todo = len; + split = ((idx + len) > rbuf->size) ? rbuf->size - idx : 0; + if (split > 0) { + memcpy(buf, rbuf->data+idx, split); + buf += split; + todo -= split; + idx = 0; + } + memcpy(buf, rbuf->data+idx, todo); + return len; +} + +void dvb_ringbuffer_pkt_dispose(struct dvb_ringbuffer *rbuf, size_t idx) +{ + size_t pktlen; + + rbuf->data[(idx + 2) % rbuf->size] = PKT_DISPOSED; + + // clean up disposed packets + while(dvb_ringbuffer_avail(rbuf) > DVB_RINGBUFFER_PKTHDRSIZE) { + if (DVB_RINGBUFFER_PEEK(rbuf, 2) == PKT_DISPOSED) { + pktlen = DVB_RINGBUFFER_PEEK(rbuf, 0) << 8; + pktlen |= DVB_RINGBUFFER_PEEK(rbuf, 1); + DVB_RINGBUFFER_SKIP(rbuf, pktlen + DVB_RINGBUFFER_PKTHDRSIZE); + } else { + // first packet is not disposed, so we stop cleaning now + break; + } + } +} + +ssize_t dvb_ringbuffer_pkt_next(struct dvb_ringbuffer *rbuf, size_t idx, size_t* pktlen) +{ + int consumed; + int curpktlen; + int curpktstatus; + + if (idx == -1) { + idx = rbuf->pread; + } else { + curpktlen = rbuf->data[idx] << 8; + curpktlen |= rbuf->data[(idx + 1) % rbuf->size]; + idx = (idx + curpktlen + DVB_RINGBUFFER_PKTHDRSIZE) % rbuf->size; + } + + consumed = (idx - rbuf->pread) % rbuf->size; + + while((dvb_ringbuffer_avail(rbuf) - consumed) > DVB_RINGBUFFER_PKTHDRSIZE) { + + curpktlen = rbuf->data[idx] << 8; + curpktlen |= rbuf->data[(idx + 1) % rbuf->size]; + curpktstatus = rbuf->data[(idx + 2) % rbuf->size]; + + if (curpktstatus == PKT_READY) { + *pktlen = curpktlen; + return idx; + } + + consumed += curpktlen + DVB_RINGBUFFER_PKTHDRSIZE; + idx = (idx + curpktlen + DVB_RINGBUFFER_PKTHDRSIZE) % rbuf->size; + } + + // no packets available + return -1; +} + + + +EXPORT_SYMBOL(dvb_ringbuffer_init); +EXPORT_SYMBOL(dvb_ringbuffer_empty); +EXPORT_SYMBOL(dvb_ringbuffer_free); +EXPORT_SYMBOL(dvb_ringbuffer_avail); +EXPORT_SYMBOL(dvb_ringbuffer_flush_spinlock_wakeup); +EXPORT_SYMBOL(dvb_ringbuffer_read_user); +EXPORT_SYMBOL(dvb_ringbuffer_read); +EXPORT_SYMBOL(dvb_ringbuffer_write); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvb_ringbuffer.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,186 @@ +/* + * + * dvb_ringbuffer.h: ring buffer implementation for the dvb driver + * + * Copyright (C) 2003 Oliver Endriss + * Copyright (C) 2004 Andrew de Quincey + * + * based on code originally found in av7110.c & dvb_ci.c: + * Copyright (C) 1999-2003 Ralph Metzler & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _DVB_RINGBUFFER_H_ +#define _DVB_RINGBUFFER_H_ + +#include +#include + +struct dvb_ringbuffer { + u8 *data; + ssize_t size; + ssize_t pread; + ssize_t pwrite; + int error; + + wait_queue_head_t queue; + spinlock_t lock; +}; + +#define DVB_RINGBUFFER_PKTHDRSIZE 3 + + +/* +** Notes: +** ------ +** (1) For performance reasons read and write routines don't check buffer sizes +** and/or number of bytes free/available. This has to be done before these +** routines are called. For example: +** +** *** write bytes *** +** free = dvb_ringbuffer_free(rbuf); +** if (free >= buflen) +** count = dvb_ringbuffer_write(rbuf, buffer, buflen); +** else +** ... +** +** *** read min. 1000, max. bytes *** +** avail = dvb_ringbuffer_avail(rbuf); +** if (avail >= 1000) +** count = dvb_ringbuffer_read(rbuf, buffer, min(avail, bufsize)); +** else +** ... +** +** (2) If there is exactly one reader and one writer, there is no need +** to lock read or write operations. +** Two or more readers must be locked against each other. +** Flushing the buffer counts as a read operation. +** Resetting the buffer counts as a read and write operation. +** Two or more writers must be locked against each other. +*/ + +/* initialize ring buffer, lock and queue */ +extern void dvb_ringbuffer_init(struct dvb_ringbuffer *rbuf, void *data, size_t len); + +/* test whether buffer is empty */ +extern int dvb_ringbuffer_empty(struct dvb_ringbuffer *rbuf); + +/* return the number of free bytes in the buffer */ +extern ssize_t dvb_ringbuffer_free(struct dvb_ringbuffer *rbuf); + +/* return the number of bytes waiting in the buffer */ +extern ssize_t dvb_ringbuffer_avail(struct dvb_ringbuffer *rbuf); + + +/* +** Reset the read and write pointers to zero and flush the buffer +** This counts as a read and write operation +*/ +extern void dvb_ringbuffer_reset(struct dvb_ringbuffer *rbuf); + + +/* read routines & macros */ +/* ---------------------- */ +/* flush buffer */ +extern void dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf); + +/* flush buffer protected by spinlock and wake-up waiting task(s) */ +extern void dvb_ringbuffer_flush_spinlock_wakeup(struct dvb_ringbuffer *rbuf); + +/* peek at byte in the buffer */ +#define DVB_RINGBUFFER_PEEK(rbuf,offs) \ + (rbuf)->data[((rbuf)->pread+(offs))%(rbuf)->size] + +/* advance read ptr by bytes */ +#define DVB_RINGBUFFER_SKIP(rbuf,num) \ + (rbuf)->pread=((rbuf)->pread+(num))%(rbuf)->size + +/* +** read bytes from ring buffer into +** specifies whether resides in user space +** returns number of bytes transferred or -EFAULT +*/ +extern ssize_t dvb_ringbuffer_read_user(struct dvb_ringbuffer *rbuf, + u8 __user *buf, size_t len); +extern void dvb_ringbuffer_read(struct dvb_ringbuffer *rbuf, + u8 *buf, size_t len); + + +/* write routines & macros */ +/* ----------------------- */ +/* write single byte to ring buffer */ +#define DVB_RINGBUFFER_WRITE_BYTE(rbuf,byte) \ + { (rbuf)->data[(rbuf)->pwrite]=(byte); \ + (rbuf)->pwrite=((rbuf)->pwrite+1)%(rbuf)->size; } +/* +** write bytes to ring buffer +** specifies whether resides in user space +** returns number of bytes transferred or -EFAULT +*/ +extern ssize_t dvb_ringbuffer_write(struct dvb_ringbuffer *rbuf, const u8 *buf, + size_t len); + + +/** + * Write a packet into the ringbuffer. + * + * Ringbuffer to write to. + * Buffer to write. + * Length of buffer (currently limited to 65535 bytes max). + * returns Number of bytes written, or -EFAULT, -ENOMEM, -EVINAL. + */ +extern ssize_t dvb_ringbuffer_pkt_write(struct dvb_ringbuffer *rbuf, u8* buf, + size_t len); + +/** + * Read from a packet in the ringbuffer. Note: unlike dvb_ringbuffer_read(), this + * does NOT update the read pointer in the ringbuffer. You must use + * dvb_ringbuffer_pkt_dispose() to mark a packet as no longer required. + * + * Ringbuffer concerned. + * Packet index as returned by dvb_ringbuffer_pkt_next(). + * Offset into packet to read from. + * Destination buffer for data. + * Size of destination buffer. + * Set to 1 if is in userspace. + * returns Number of bytes read, or -EFAULT. + */ +extern ssize_t dvb_ringbuffer_pkt_read_user(struct dvb_ringbuffer *rbuf, size_t idx, + int offset, u8 __user *buf, size_t len); +extern ssize_t dvb_ringbuffer_pkt_read(struct dvb_ringbuffer *rbuf, size_t idx, + int offset, u8 *buf, size_t len); + +/** + * Dispose of a packet in the ring buffer. + * + * Ring buffer concerned. + * Packet index as returned by dvb_ringbuffer_pkt_next(). + */ +extern void dvb_ringbuffer_pkt_dispose(struct dvb_ringbuffer *rbuf, size_t idx); + +/** + * Get the index of the next packet in a ringbuffer. + * + * Ringbuffer concerned. + * Previous packet index, or -1 to return the first packet index. + * On success, will be updated to contain the length of the packet in bytes. + * returns Packet index (if >=0), or -1 if no packets available. + */ +extern ssize_t dvb_ringbuffer_pkt_next(struct dvb_ringbuffer *rbuf, size_t idx, size_t* pktlen); + + +#endif /* _DVB_RINGBUFFER_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,513 @@ +/* + * dvbdev.c + * + * Copyright (C) 2000 Ralph Metzler + * & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dvbdev.h" + +static DEFINE_MUTEX(dvbdev_mutex); +static int dvbdev_debug; + +module_param(dvbdev_debug, int, 0644); +MODULE_PARM_DESC(dvbdev_debug, "Turn on/off device debugging (default:off)."); + +#define dprintk if (dvbdev_debug) printk + +static LIST_HEAD(dvb_adapter_list); +static DEFINE_MUTEX(dvbdev_register_lock); + +static const char * const dnames[] = { + "video", "audio", "sec", "frontend", "demux", "dvr", "ca", + "net", "osd", "ci", "mod", "ns", "nsd" +}; + +#ifdef CONFIG_DVB_DYNAMIC_MINORS +#define MAX_DVB_MINORS 256 +#define DVB_MAX_IDS MAX_DVB_MINORS +#else +#define DVB_MAX_IDS 4 +#define nums2minor(num,type,id) ((num << 6) | (id << 4) | type) +#define MAX_DVB_MINORS (DVB_MAX_ADAPTERS*64) +#endif + +static struct class *dvb_class; + +static struct dvb_device *dvb_minors[MAX_DVB_MINORS]; +static DECLARE_RWSEM(minor_rwsem); + +static int dvb_device_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev; + + //mutex_lock(&dvbdev_mutex); + down_read(&minor_rwsem); + dvbdev = dvb_minors[iminor(inode)]; + + if (dvbdev && dvbdev->fops) { + int err = 0; + const struct file_operations *old_fops; + + file->private_data = dvbdev; + old_fops = file->f_op; + file->f_op = fops_get(dvbdev->fops); + if (file->f_op == NULL) { + file->f_op = old_fops; + goto fail; + } + if(file->f_op->open) + err = file->f_op->open(inode,file); + if (err) { + fops_put(file->f_op); + file->f_op = fops_get(old_fops); + } + fops_put(old_fops); + up_read(&minor_rwsem); + //mutex_unlock(&dvbdev_mutex); + return err; + } +fail: + up_read(&minor_rwsem); + //mutex_unlock(&dvbdev_mutex); + return -ENODEV; +} + + +static const struct file_operations dvb_device_fops = +{ + .owner = THIS_MODULE, + .open = dvb_device_open, + .llseek = noop_llseek, +}; + +static struct cdev dvb_device_cdev; + +int dvb_generic_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + + if (!dvbdev) + return -ENODEV; + + if (!dvbdev->users) + return -EBUSY; + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + if (!dvbdev->readers) + return -EBUSY; + dvbdev->readers--; + } else { + if (!dvbdev->writers) + return -EBUSY; + dvbdev->writers--; + } + + dvbdev->users--; + return 0; +} +EXPORT_SYMBOL(dvb_generic_open); + + +int dvb_generic_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + + if (!dvbdev) + return -ENODEV; + + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + dvbdev->readers++; + } else { + dvbdev->writers++; + } + + dvbdev->users++; + return 0; +} +EXPORT_SYMBOL(dvb_generic_release); + + +long dvb_generic_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct dvb_device *dvbdev = file->private_data; + + if (!dvbdev) + return -ENODEV; + + if (!dvbdev->kernel_ioctl) + return -EINVAL; + + return dvb_usercopy(file, cmd, arg, dvbdev->kernel_ioctl); +} +EXPORT_SYMBOL(dvb_generic_ioctl); + + +static int dvbdev_get_free_id (struct dvb_adapter *adap, int type) +{ + u32 id = 0; + + while (id < DVB_MAX_IDS) { + struct dvb_device *dev; + list_for_each_entry(dev, &adap->device_list, list_head) + if (dev->type == type && dev->id == id) + goto skip; + return id; +skip: + id++; + } + return -ENFILE; +} + + +int dvb_register_device(struct dvb_adapter *adap, struct dvb_device **pdvbdev, + const struct dvb_device *template, void *priv, int type) +{ + struct dvb_device *dvbdev; + struct file_operations *dvbdevfops; + struct device *clsdev; + int minor; + int id; + + mutex_lock(&dvbdev_register_lock); + + if ((id = dvbdev_get_free_id (adap, type)) < 0){ + mutex_unlock(&dvbdev_register_lock); + *pdvbdev = NULL; + printk(KERN_ERR "%s: couldn't find free device id\n", __func__); + return -ENFILE; + } + + *pdvbdev = dvbdev = kmalloc(sizeof(struct dvb_device), GFP_KERNEL); + + if (!dvbdev){ + mutex_unlock(&dvbdev_register_lock); + return -ENOMEM; + } + + dvbdevfops = kzalloc(sizeof(struct file_operations), GFP_KERNEL); + + if (!dvbdevfops){ + kfree (dvbdev); + mutex_unlock(&dvbdev_register_lock); + return -ENOMEM; + } + + memcpy(dvbdev, template, sizeof(struct dvb_device)); + dvbdev->type = type; + dvbdev->id = id; + dvbdev->adapter = adap; + dvbdev->priv = priv; + dvbdev->fops = dvbdevfops; + init_waitqueue_head (&dvbdev->wait_queue); + + memcpy(dvbdevfops, template->fops, sizeof(struct file_operations)); + dvbdevfops->owner = adap->module; + + list_add_tail (&dvbdev->list_head, &adap->device_list); + + down_write(&minor_rwsem); +#ifdef CONFIG_DVB_DYNAMIC_MINORS + for (minor = 0; minor < MAX_DVB_MINORS; minor++) + if (dvb_minors[minor] == NULL) + break; + + if (minor == MAX_DVB_MINORS) { + kfree(dvbdevfops); + kfree(dvbdev); + up_write(&minor_rwsem); + mutex_unlock(&dvbdev_register_lock); + return -EINVAL; + } +#else + minor = nums2minor(adap->num, type, id); +#endif + + dvbdev->minor = minor; + dvb_minors[minor] = dvbdev; + up_write(&minor_rwsem); + + mutex_unlock(&dvbdev_register_lock); + + clsdev = device_create(dvb_class, adap->device, + MKDEV(DVB_MAJOR, minor), + dvbdev, "dvb%d.%s%d", adap->num, dnames[type], id); + if (IS_ERR(clsdev)) { + printk(KERN_ERR "%s: failed to create device dvb%d.%s%d (%ld)\n", + __func__, adap->num, dnames[type], id, PTR_ERR(clsdev)); + return PTR_ERR(clsdev); + } + + dprintk(KERN_DEBUG "DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n", + adap->num, dnames[type], id, minor, minor); + + return 0; +} +EXPORT_SYMBOL(dvb_register_device); + + +void dvb_unregister_device(struct dvb_device *dvbdev) +{ + if (!dvbdev) + return; + + down_write(&minor_rwsem); + dvb_minors[dvbdev->minor] = NULL; + up_write(&minor_rwsem); + + device_destroy(dvb_class, MKDEV(DVB_MAJOR, dvbdev->minor)); + + list_del (&dvbdev->list_head); + kfree (dvbdev->fops); + kfree (dvbdev); +} +EXPORT_SYMBOL(dvb_unregister_device); + +static int dvbdev_check_free_adapter_num(int num) +{ + struct list_head *entry; + list_for_each(entry, &dvb_adapter_list) { + struct dvb_adapter *adap; + adap = list_entry(entry, struct dvb_adapter, list_head); + if (adap->num == num) + return 0; + } + return 1; +} + +static int dvbdev_get_free_adapter_num (void) +{ + int num = 0; + + while (num < DVB_MAX_ADAPTERS) { + if (dvbdev_check_free_adapter_num(num)) + return num; + num++; + } + + return -ENFILE; +} + + +int dvb_register_adapter(struct dvb_adapter *adap, const char *name, + struct module *module, struct device *device, + short *adapter_nums) +{ + int i, num; + + mutex_lock(&dvbdev_register_lock); + + for (i = 0; i < DVB_MAX_ADAPTERS; ++i) { + num = adapter_nums[i]; + if (num >= 0 && num < DVB_MAX_ADAPTERS) { + /* use the one the driver asked for */ + if (dvbdev_check_free_adapter_num(num)) + break; + } else { + num = dvbdev_get_free_adapter_num(); + break; + } + num = -1; + } + + if (num < 0) { + mutex_unlock(&dvbdev_register_lock); + return -ENFILE; + } + + memset (adap, 0, sizeof(struct dvb_adapter)); + INIT_LIST_HEAD (&adap->device_list); + + printk(KERN_INFO "DVB: registering new adapter (%s)\n", name); + + adap->num = num; + adap->name = name; + adap->module = module; + adap->device = device; + adap->mfe_shared = 0; + adap->mfe_dvbdev = NULL; + mutex_init (&adap->mfe_lock); + + list_add_tail (&adap->list_head, &dvb_adapter_list); + + mutex_unlock(&dvbdev_register_lock); + + return num; +} +EXPORT_SYMBOL(dvb_register_adapter); + + +int dvb_unregister_adapter(struct dvb_adapter *adap) +{ + mutex_lock(&dvbdev_register_lock); + list_del (&adap->list_head); + mutex_unlock(&dvbdev_register_lock); + return 0; +} +EXPORT_SYMBOL(dvb_unregister_adapter); + +/* if the miracle happens and "generic_usercopy()" is included into + the kernel, then this can vanish. please don't make the mistake and + define this as video_usercopy(). this will introduce a dependecy + to the v4l "videodev.o" module, which is unnecessary for some + cards (ie. the budget dvb-cards don't need the v4l module...) */ +int dvb_usercopy(struct file *file, + unsigned int cmd, unsigned long arg, + int (*func)(struct file *file, + unsigned int cmd, void *arg)) +{ + char sbuf[128]; + void *mbuf = NULL; + void *parg = NULL; + int err = -EINVAL; + + /* Copy arguments into temp kernel buffer */ + switch (_IOC_DIR(cmd)) { + case _IOC_NONE: + /* + * For this command, the pointer is actually an integer + * argument. + */ + parg = (void *) arg; + break; + case _IOC_READ: /* some v4l ioctls are marked wrong ... */ + case _IOC_WRITE: + case (_IOC_WRITE | _IOC_READ): + if (_IOC_SIZE(cmd) <= sizeof(sbuf)) { + parg = sbuf; + } else { + /* too big to allocate from stack */ + mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL); + if (NULL == mbuf) + return -ENOMEM; + parg = mbuf; + } + + err = -EFAULT; + if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) + goto out; + break; + } + + /* call driver */ + //mutex_lock(&dvbdev_mutex); + if ((err = func(file, cmd, parg)) == -ENOIOCTLCMD) + err = -ENOTTY; + //mutex_unlock(&dvbdev_mutex); + + if (err < 0) + goto out; + + /* Copy results into user buffer */ + switch (_IOC_DIR(cmd)) + { + case _IOC_READ: + case (_IOC_WRITE | _IOC_READ): + if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) + err = -EFAULT; + break; + } + +out: + kfree(mbuf); + return err; +} +EXPORT_SYMBOL(dvb_usercopy); + +static int dvb_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct dvb_device *dvbdev = dev_get_drvdata(dev); + + add_uevent_var(env, "DVB_ADAPTER_NUM=%d", dvbdev->adapter->num); + add_uevent_var(env, "DVB_DEVICE_TYPE=%s", dnames[dvbdev->type]); + add_uevent_var(env, "DVB_DEVICE_NUM=%d", dvbdev->id); + return 0; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) +static char *dvb_devnode(struct device *dev, mode_t *mode) +#else +static char *dvb_devnode(struct device *dev, umode_t *mode) +#endif +{ + struct dvb_device *dvbdev = dev_get_drvdata(dev); + + return kasprintf(GFP_KERNEL, "dvb/adapter%d/%s%d", + dvbdev->adapter->num, dnames[dvbdev->type], dvbdev->id); +} + + +static int __init init_dvbdev(void) +{ + int retval; + dev_t dev = MKDEV(DVB_MAJOR, 0); + + if ((retval = register_chrdev_region(dev, MAX_DVB_MINORS, "DVB")) != 0) { + printk(KERN_ERR "dvb-core: unable to get major %d\n", DVB_MAJOR); + return retval; + } + + cdev_init(&dvb_device_cdev, &dvb_device_fops); + if ((retval = cdev_add(&dvb_device_cdev, dev, MAX_DVB_MINORS)) != 0) { + printk(KERN_ERR "dvb-core: unable register character device\n"); + goto error; + } + + dvb_class = class_create(THIS_MODULE, "dvb"); + if (IS_ERR(dvb_class)) { + retval = PTR_ERR(dvb_class); + goto error; + } + dvb_class->dev_uevent = dvb_uevent; + dvb_class->devnode = dvb_devnode; + return 0; + +error: + cdev_del(&dvb_device_cdev); + unregister_chrdev_region(dev, MAX_DVB_MINORS); + return retval; +} + + +static void __exit exit_dvbdev(void) +{ + class_destroy(dvb_class); + cdev_del(&dvb_device_cdev); + unregister_chrdev_region(MKDEV(DVB_MAJOR, 0), MAX_DVB_MINORS); +} + +subsys_initcall(init_dvbdev); +module_exit(exit_dvbdev); + +MODULE_DESCRIPTION("DVB Core Driver"); +MODULE_AUTHOR("Marcus Metzler, Ralph Metzler, Holger Waechtler"); +MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/dvb-core/dvbdev.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,150 @@ +/* + * dvbdev.h + * + * Copyright (C) 2000 Ralph Metzler & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Lesser Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVBDEV_H_ +#define _DVBDEV_H_ + +#include +#include +#include +#include + +#define DVB_MAJOR 212 + +#if defined(CONFIG_DVB_MAX_ADAPTERS) && CONFIG_DVB_MAX_ADAPTERS > 0 + #define DVB_MAX_ADAPTERS CONFIG_DVB_MAX_ADAPTERS +#else + #define DVB_MAX_ADAPTERS 8 +#endif + +#define DVB_UNSET (-1) + +#define DVB_DEVICE_VIDEO 0 +#define DVB_DEVICE_AUDIO 1 +#define DVB_DEVICE_SEC 2 +#define DVB_DEVICE_FRONTEND 3 +#define DVB_DEVICE_DEMUX 4 +#define DVB_DEVICE_DVR 5 +#define DVB_DEVICE_CA 6 +#define DVB_DEVICE_NET 7 +#define DVB_DEVICE_OSD 8 +#define DVB_DEVICE_CI 9 +#define DVB_DEVICE_MOD 10 +#define DVB_DEVICE_NS 11 +#define DVB_DEVICE_NSD 12 + +#define DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr) \ + static short adapter_nr[] = \ + {[0 ... (DVB_MAX_ADAPTERS - 1)] = DVB_UNSET }; \ + module_param_array(adapter_nr, short, NULL, 0444); \ + MODULE_PARM_DESC(adapter_nr, "DVB adapter numbers") + +struct dvb_frontend; + +struct dvb_adapter { + int num; + struct list_head list_head; + struct list_head device_list; + const char *name; + u8 proposed_mac [6]; + void* priv; + + struct device *device; + + struct module *module; + + int mfe_shared; /* indicates mutually exclusive frontends */ + struct dvb_device *mfe_dvbdev; /* frontend device in use */ + struct mutex mfe_lock; /* access lock for thread creation */ +}; + + +struct dvb_device { + struct list_head list_head; + const struct file_operations *fops; + struct dvb_adapter *adapter; + int type; + int minor; + u32 id; + + /* in theory, 'users' can vanish now, + but I don't want to change too much now... */ + int readers; + int writers; + int users; + + wait_queue_head_t wait_queue; + /* don't really need those !? -- FIXME: use video_usercopy */ + int (*kernel_ioctl)(struct file *file, unsigned int cmd, void *arg); + + void *priv; +}; + + +extern int dvb_register_adapter(struct dvb_adapter *adap, const char *name, + struct module *module, struct device *device, + short *adapter_nums); +extern int dvb_unregister_adapter (struct dvb_adapter *adap); + +extern int dvb_register_device (struct dvb_adapter *adap, + struct dvb_device **pdvbdev, + const struct dvb_device *template, + void *priv, + int type); + +extern void dvb_unregister_device (struct dvb_device *dvbdev); + +extern int dvb_generic_open (struct inode *inode, struct file *file); +extern int dvb_generic_release (struct inode *inode, struct file *file); +extern long dvb_generic_ioctl (struct file *file, + unsigned int cmd, unsigned long arg); + +/* we don't mess with video_usercopy() any more, +we simply define out own dvb_usercopy(), which will hopefully become +generic_usercopy() someday... */ + +extern int dvb_usercopy(struct file *file, unsigned int cmd, unsigned long arg, + int (*func)(struct file *file, unsigned int cmd, void *arg)); + +/** generic DVB attach function. */ +#ifdef CONFIG_MEDIA_ATTACH +#define dvb_attach(FUNCTION, ARGS...) ({ \ + void *__r = NULL; \ + typeof(&FUNCTION) __a = symbol_request(FUNCTION); \ + if (__a) { \ + __r = (void *) __a(ARGS); \ + if (__r == NULL) \ + symbol_put(FUNCTION); \ + } else { \ + printk(KERN_ERR "DVB: Unable to find symbol "#FUNCTION"()\n"); \ + } \ + __r; \ +}) + +#else +#define dvb_attach(FUNCTION, ARGS...) ({ \ + FUNCTION(ARGS); \ +}) + +#endif + +#endif /* #ifndef _DVBDEV_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/Makefile dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/Makefile --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/Makefile 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,28 @@ +# +# Makefile for the kernel DVB frontend device drivers. +# + +EXTRA_CFLAGS += -DCONFIG_DVB_LNBP21 +EXTRA_CFLAGS += -DCONFIG_DVB_STV090x +EXTRA_CFLAGS += -DCONFIG_DVB_STV6110x +#EXTRA_CFLAGS += -DCONFIG_DVB_STV0367 +EXTRA_CFLAGS += -DCONFIG_DVB_STV0367DD +#EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212 +EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212DD +EXTRA_CFLAGS += -DCONFIG_DVB_CXD2843 +EXTRA_CFLAGS += -DDBVALS +NOSTDINC_FLAGS += -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core + +drxk-objs := drxk_hard.o +obj-$(CONFIG_DVB_DRXK) += drxk.o + +obj-$(CONFIG_DVB_LNBP21) += lnbp21.o +obj-$(CONFIG_DVB_STV090x) += stv090x.o +obj-$(CONFIG_DVB_STV6110x) += stv6110x.o +obj-$(CONFIG_DVB_CXD2099) += cxd2099.o +obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o +#obj-$(CONFIG_DVB_STV0367) += stv0367.o +obj-$(CONFIG_DVB_STV0367DD) += stv0367dd.o +#obj-$(CONFIG_DVB_TDA18212) += tda18212.o +obj-$(CONFIG_DVB_TDA18212DD) += tda18212dd.o +obj-$(CONFIG_DVB_CXD2843) += cxd2843.o diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,703 @@ +/* + * cxd2099.c: Driver for the CXD2099AR Common Interface Controller + * + * Copyright (C) 2010-2013 Digital Devices GmbH + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cxd2099.h" + +//#define BUFFER_MODE 1 + +#define MAX_BUFFER_SIZE 248 + +static int read_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount); + +struct cxd { + struct dvb_ca_en50221 en; + + struct i2c_adapter *i2c; + struct cxd2099_cfg cfg; + + u8 regs[0x23]; + u8 lastaddress; + u8 clk_reg_f; + u8 clk_reg_b; + int mode; + int ready; + int dr; + int write_busy; + int slot_stat; + + u8 amem[1024]; + int amem_read; + + int cammode; + struct mutex lock; + + u8 rbuf[1028]; + u8 wbuf[1028]; +}; + +static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr, + u8 reg, u8 data) +{ + u8 m[2] = {reg, data}; + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2}; + + if (i2c_transfer(adapter, &msg, 1) != 1) { + printk(KERN_ERR "Failed to write to I2C register %02x@%02x!\n", + reg, adr); + return -1; + } + return 0; +} + +static int i2c_write(struct i2c_adapter *adapter, u8 adr, + u8 *data, u8 len) +{ + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adapter, &msg, 1) != 1) { + printk(KERN_ERR "Failed to write to I2C!\n"); + return -1; + } + return 0; +} + +static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, + u8 reg, u8 *val) +{ + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = ®, .len = 1}, + {.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1} }; + + if (i2c_transfer(adapter, msgs, 2) != 2) { + printk(KERN_ERR "error in i2c_read_reg\n"); + return -1; + } + return 0; +} + +static int i2c_read(struct i2c_adapter *adapter, u8 adr, + u8 reg, u8 *data, u8 n) +{ + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = ®, .len = 1}, + {.addr = adr, .flags = I2C_M_RD, + .buf = data, .len = n} }; + + if (i2c_transfer(adapter, msgs, 2) != 2) { + printk(KERN_ERR "error in i2c_read\n"); + return -1; + } + return 0; +} + +static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n) +{ + int status = 0; + + if (ci->lastaddress != adr) + status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); + if (!status) { + ci->lastaddress = adr; + status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n); + } + return status; +} + +static int read_reg(struct cxd *ci, u8 reg, u8 *val) +{ + return read_block(ci, reg, val, 1); +} + + +static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) +{ + int status; + u8 addr[3] = {2, address & 0xff, address >> 8}; + + status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); + if (!status) + status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n); + return status; +} + +static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) +{ + int status; + u8 addr[3] = {2, address & 0xff, address >> 8}; + + status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); + if (!status) { + u8 buf[256] = {3}; + memcpy(buf+1, data, n); + status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1); + } + return status; +} + +static int read_io(struct cxd *ci, u16 address, u8 *val) +{ + int status; + u8 addr[3] = {2, address & 0xff, address >> 8}; + + status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); + if (!status) + status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1); + return status; +} + +static int write_io(struct cxd *ci, u16 address, u8 val) +{ + int status; + u8 addr[3] = {2, address & 0xff, address >> 8}; + u8 buf[2] = {3, val}; + + status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); + if (!status) + status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2); + return status; +} + +#if 0 +static int read_io_data(struct cxd *ci, u8 *data, u8 n) +{ + int status; + u8 addr[3] = { 2, 0, 0 }; + + status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); + if (!status) + status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n); + return 0; +} + +static int write_io_data(struct cxd *ci, u8 *data, u8 n) +{ + int status; + u8 addr[3] = {2, 0, 0}; + + status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); + if (!status) { + u8 buf[256] = {3}; + memcpy(buf+1, data, n); + status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); + } + return 0; + +} +#endif + +static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) +{ + int status = 0; + + if (ci->lastaddress != reg) + status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg); + if (!status && reg >= 6 && reg <=8 && mask != 0xff) + status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]); + ci->lastaddress = reg; + ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; + if (!status) { + status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]); + } + if (reg == 0x20) + ci->regs[reg] &= 0x7f; + return status; +} + +static int write_reg(struct cxd *ci, u8 reg, u8 val) +{ + return write_regm(ci, reg, val, 0xff); +} + +static int write_block(struct cxd *ci, u8 adr, u8 *data, int n) +{ + int status = 0; + u8 *buf = ci->wbuf; + + if (ci->lastaddress != adr) + status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); + if (!status) { + ci->lastaddress = adr; + buf[0] = 1; + memcpy(buf + 1, data, n); + status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); + } + return status; +} + +static void set_mode(struct cxd *ci, int mode) +{ + if (mode == ci->mode) + return; + + switch (mode) { + case 0x00: /* IO mem */ + write_regm(ci, 0x06, 0x00, 0x07); + break; + case 0x01: /* ATT mem */ + write_regm(ci, 0x06, 0x02, 0x07); + break; + default: + break; + } + ci->mode = mode; +} + +static void cam_mode(struct cxd *ci, int mode) +{ + u8 dummy; + + if (mode == ci->cammode) + return; + + switch (mode) { + case 0x00: + write_regm(ci, 0x20, 0x80, 0x80); + break; + case 0x01: + if (!ci->en.read_data) + return; + ci->write_busy = 0; + printk(KERN_INFO "enable cam buffer mode\n"); + write_reg(ci, 0x0d, 0x00); + write_reg(ci, 0x0e, 0x01); + write_regm(ci, 0x08, 0x40, 0x40); + read_reg(ci, 0x12, &dummy); + write_regm(ci, 0x08, 0x80, 0x80); + break; + default: + break; + } + ci->cammode = mode; +} + + + +#define CHK_ERROR(s) if( (status = s) ) break + +static int init(struct cxd *ci) +{ + int status; + + mutex_lock(&ci->lock); + ci->mode=-1; + do { + CHK_ERROR(write_reg(ci, 0x00, 0x00)); + CHK_ERROR(write_reg(ci, 0x01, 0x00)); + CHK_ERROR(write_reg(ci, 0x02, 0x10)); + CHK_ERROR(write_reg(ci, 0x03, 0x00)); + CHK_ERROR(write_reg(ci, 0x05, 0xFF)); + CHK_ERROR(write_reg(ci, 0x06, 0x1F)); + CHK_ERROR(write_reg(ci, 0x07, 0x1F)); + CHK_ERROR(write_reg(ci, 0x08, 0x28)); + CHK_ERROR(write_reg(ci, 0x14, 0x20)); + + CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */ + + CHK_ERROR(write_reg(ci, 0x0B, 0x33)); + CHK_ERROR(write_reg(ci, 0x0C, 0x33)); + + CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F)); + CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b)); + CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F)); + CHK_ERROR(write_reg(ci, 0x17,ci->clk_reg_f)); + + if (ci->cfg.clock_mode == 2) { + u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000; // bitrate*2^13/ 72000 + + if (ci->cfg.polarity) { + CHK_ERROR(write_reg(ci, 0x09, 0x6f)); /* mode D */ + } else { + CHK_ERROR(write_reg(ci, 0x09, 0x6d)); + } + CHK_ERROR(write_reg(ci, 0x20, 0x08)); + CHK_ERROR(write_reg(ci, 0x21, (reg >> 8) & 0xff)); + CHK_ERROR(write_reg(ci, 0x22, reg & 0xff)); + } else if (ci->cfg.clock_mode == 1) { + if (ci->cfg.polarity) { + CHK_ERROR(write_reg(ci, 0x09, 0x6f)); /* mode D */ + } else { + CHK_ERROR(write_reg(ci, 0x09, 0x6d)); + } + CHK_ERROR(write_reg(ci, 0x20, 0x68)); + CHK_ERROR(write_reg(ci, 0x21, 0x00)); + CHK_ERROR(write_reg(ci, 0x22, 0x02)); + } else { + if (ci->cfg.polarity) { + CHK_ERROR(write_reg(ci, 0x09, 0x4f)); /* mode C */ + } else { + CHK_ERROR(write_reg(ci, 0x09, 0x4d)); + } + + CHK_ERROR(write_reg(ci, 0x20, 0x28)); + CHK_ERROR(write_reg(ci, 0x21, 0x00)); + CHK_ERROR(write_reg(ci, 0x22, 0x07)); + } + + CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80)); + CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02)); + CHK_ERROR(write_reg(ci, 0x01, 0x04)); + CHK_ERROR(write_reg(ci, 0x00, 0x31)); + + /* Put TS in bypass */ + CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08)); + ci->cammode=-1; + cam_mode(ci, 0); + } while(0); + mutex_unlock(&ci->lock); + + return 0; +} + +static int read_attribute_mem(struct dvb_ca_en50221 *ca, + int slot, int address) +{ + struct cxd *ci = ca->data; +#if 0 + if (ci->amem_read) { + if (address <=0 || address>1024) + return -EIO; + return ci->amem[address]; + } + + mutex_lock(&ci->lock); + write_regm(ci, 0x06, 0x00, 0x05); + read_pccard(ci, 0, &ci->amem[0], 128); + read_pccard(ci, 128, &ci->amem[0], 128); + read_pccard(ci, 256, &ci->amem[0], 128); + read_pccard(ci, 384, &ci->amem[0], 128); + write_regm(ci, 0x06, 0x05, 0x05); + mutex_unlock(&ci->lock); + return ci->amem[address]; +#else + u8 val; + mutex_lock(&ci->lock); + set_mode(ci, 1); + read_pccard(ci, address, &val, 1); + mutex_unlock(&ci->lock); + //printk("%02x:%02x\n", address,val); + return val; +#endif +} + +static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, + int address, u8 value) +{ + struct cxd *ci = ca->data; + + mutex_lock(&ci->lock); + set_mode(ci, 1); + write_pccard(ci, address, &value, 1); + mutex_unlock(&ci->lock); + return 0; +} + +static int read_cam_control(struct dvb_ca_en50221 *ca, + int slot, u8 address) +{ + struct cxd *ci = ca->data; + u8 val; + + mutex_lock(&ci->lock); + set_mode(ci, 0); + read_io(ci, address, &val); + mutex_unlock(&ci->lock); + return val; +} + +static int write_cam_control(struct dvb_ca_en50221 *ca, int slot, + u8 address, u8 value) +{ + struct cxd *ci = ca->data; + + mutex_lock(&ci->lock); + set_mode(ci, 0); + write_io(ci, address, value); + mutex_unlock(&ci->lock); + return 0; +} + +static int slot_reset(struct dvb_ca_en50221 *ca, int slot) +{ + struct cxd *ci = ca->data; + + if (ci->cammode) + read_data(ca, slot, ci->rbuf, 0); + + mutex_lock(&ci->lock); + printk("slot_reset\n"); +#if 0 + write_reg(ci, 0x00, 0x21); + write_reg(ci, 0x06, 0x1F); + write_reg(ci, 0x00, 0x31); +#else +#if 0 + write_reg(ci, 0x06, 0x1F); + write_reg(ci, 0x06, 0x2F); +#else + cam_mode(ci, 0); + write_reg(ci, 0x00, 0x21); + write_reg(ci, 0x06, 0x1F); + //msleep(300); + write_reg(ci, 0x00, 0x31); + write_regm(ci, 0x20, 0x80, 0x80); + write_reg(ci, 0x03, 0x02); + ci->ready=0; +#endif +#endif + ci->mode=-1; + { + int i; +#if 0 + u8 val; +#endif + for (i=0; i<100;i++) { + msleep(10); +#if 0 + read_reg(ci, 0x06,&val); + printk(KERN_INFO "%d:%02x\n", i, val); + if (!(val&0x10)) + break; +#else + if (ci->ready) + break; +#endif + } + } + mutex_unlock(&ci->lock); + /* msleep(500); */ + return 0; +} + +static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) +{ + struct cxd *ci = ca->data; + + printk(KERN_INFO "slot_shutdown\n"); + if (ci->cammode) + read_data(ca, slot, ci->rbuf, 0); + mutex_lock(&ci->lock); + write_reg(ci, 0x00, 0x21); + write_reg(ci, 0x06, 0x1F); + msleep(300); + + write_regm(ci, 0x09, 0x08, 0x08); + write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */ + write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */ + + ci->mode = -1; + ci->write_busy = 0; + mutex_unlock(&ci->lock); + return 0; +} + +static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) +{ + struct cxd *ci = ca->data; + + mutex_lock(&ci->lock); + write_regm(ci, 0x09, 0x00, 0x08); + set_mode(ci, 0); + cam_mode(ci, 1); + mutex_unlock(&ci->lock); + return 0; +} + + +static int campoll(struct cxd *ci) +{ + u8 istat; + + read_reg(ci, 0x04, &istat); + if (!istat) + return 0; + write_reg(ci, 0x05, istat); + + if (istat & 0x40) { + ci->dr = 1; + //printk(KERN_INFO "DR\n"); + } + if (istat & 0x20) { + //printk(KERN_INFO "WC\n"); + ci->write_busy = 0; + } + + if (istat & 2) { + u8 slotstat; + + read_reg(ci, 0x01, &slotstat); + if (!(2 & slotstat)) { + if (!ci->slot_stat) { + ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; + write_regm(ci, 0x03, 0x08, 0x08); + } + + } else { + if (ci->slot_stat) { + ci->slot_stat = 0; + write_regm(ci, 0x03, 0x00, 0x08); + printk(KERN_INFO "NO CAM\n"); + ci->ready = 0; + } + } + if (istat&8 && ci->slot_stat==DVB_CA_EN50221_POLL_CAM_PRESENT) { + ci->ready=1; + ci->slot_stat|=DVB_CA_EN50221_POLL_CAM_READY; + } + } + return 0; +} + + +static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) +{ + struct cxd *ci = ca->data; + u8 slotstat; + + mutex_lock(&ci->lock); + campoll(ci); + read_reg(ci, 0x01, &slotstat); + mutex_unlock(&ci->lock); + + return ci->slot_stat; +} + +static int read_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount) +{ + struct cxd *ci = ca->data; + u8 msb, lsb; + u16 len; + + mutex_lock(&ci->lock); + campoll(ci); + mutex_unlock(&ci->lock); + + if (!ci->dr) + return 0; + + mutex_lock(&ci->lock); + read_reg(ci, 0x0f, &msb); + read_reg(ci, 0x10, &lsb); + len = ((u16)msb<<8)|lsb; + if (len > ecount || len < 2) { + /* read it anyway or cxd may hang */ + read_block(ci, 0x12, ci->rbuf, len); + mutex_unlock(&ci->lock); + return -EIO; + } + read_block(ci, 0x12, ebuf, len); + ci->dr = 0; + mutex_unlock(&ci->lock); +#if 0 + printk(KERN_INFO "read_data %d\n", len); + { + int i; + + for (i=0; i< len; i++) + printk("%02x ", ebuf[i]); + printk("\n"); + } +#endif + return len; +} + +static int write_data(struct dvb_ca_en50221* ca, int slot, u8 *ebuf, int ecount) +{ + struct cxd *ci = ca->data; + + if (ci->write_busy) + return -EAGAIN; + mutex_lock(&ci->lock); + printk("write_data %d\n", ecount); + write_reg(ci, 0x0d, ecount >> 8); + write_reg(ci, 0x0e, ecount & 0xff); + write_block(ci, 0x11, ebuf, ecount); + ci->write_busy = 1; + mutex_unlock(&ci->lock); + return ecount; +} + +static struct dvb_ca_en50221 en_templ = { + .read_attribute_mem = read_attribute_mem, + .write_attribute_mem = write_attribute_mem, + .read_cam_control = read_cam_control, + .write_cam_control = write_cam_control, + .slot_reset = slot_reset, + .slot_shutdown = slot_shutdown, + .slot_ts_enable = slot_ts_enable, + .poll_slot_status = poll_slot_status, +#ifdef BUFFER_MODE + .read_data = read_data, + .write_data = write_data, +#endif + +}; + +struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, + void *priv, + struct i2c_adapter *i2c) +{ + struct cxd *ci = 0; + u8 val; + + if (i2c_read_reg(i2c, cfg->adr, 0, &val)<0) { + printk("No CXD2099 detected at %02x\n", cfg->adr); + return 0; + } + + ci = kzalloc(sizeof(struct cxd), GFP_KERNEL); + if (!ci) + return 0; + + mutex_init(&ci->lock); + memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg)); + ci->i2c = i2c; + ci->lastaddress = 0xff; + ci->clk_reg_b = 0x4a; + ci->clk_reg_f = 0x1b; + + memcpy(&ci->en, &en_templ, sizeof(en_templ)); + ci->en.data = ci; + init(ci); + printk(KERN_INFO "Attached CXD2099AR at %02x\n", ci->cfg.adr); + return &ci->en; +} + +EXPORT_SYMBOL(cxd2099_attach); + +MODULE_DESCRIPTION("cxd2099"); +MODULE_AUTHOR("Ralph Metzler"); +MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2099.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,41 @@ +/* + * cxd2099.h: Driver for the CXD2099AR Common Interface Controller + * + * Copyright (C) 2010-2011 Digital Devices GmbH + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _CXD2099_H_ +#define _CXD2099_H_ + +#include + +struct cxd2099_cfg { + u32 bitrate; + u8 adr; + u8 polarity; + u8 clock_mode; +}; + +struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, + void *priv, struct i2c_adapter *i2c); + + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1649 @@ +/* + * Driver for the Sony CXD2843ER DVB-T/T2/C/C2 demodulator. + * Also supports the CXD2837ER DVB-T/T2/C and the + * CXD2838ER ISDB-T demodulator. + * + * Copyright (C) 2013 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "cxd2843.h" + + +enum EDemodType { CXD2843, CXD2837, CXD2838 }; +enum EDemodState { Unknown, Shutdown, Sleep, ActiveT, ActiveT2, ActiveC, ActiveC2, ActiveIT }; +enum omode { OM_NONE, OM_DVBT, OM_DVBT2, OM_DVBC, OM_QAM_ITU_C, OM_DVBC2, OM_ISDBT }; + +struct cxd_state { + struct dvb_frontend frontend; + struct i2c_adapter *i2c; + struct mutex mutex; + + u8 adrt; + u8 curbankt; + + u8 adrx; + u8 curbankx; + + enum EDemodType type; + enum EDemodState state; + enum omode omode; + + u8 IF_FS; + int ContinuousClock; + int SerialMode; + u8 SerialClockFrequency; + + u32 LockTimeout; + u32 TSLockTimeout; + u32 L1PostTimeout; + u32 DataSliceID; + int FirstTimeLock; + u32 PLPNumber; + u32 last_status; + + u32 bandwidth; + u32 bw; +}; + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = + {.addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk("cxd2843: i2c_write error\n"); + return -1; + } + return 0; +} + +static int writeregs(struct cxd_state *state, u8 adr, u8 reg, u8 *regd, u16 len) +{ + u8 data[len + 1]; + + data[0] = reg; + memcpy(data + 1, regd, len); + return i2c_write(state->i2c, adr, data, len + 1); +} + +static int writereg(struct cxd_state *state, u8 adr, u8 reg, u8 dat) +{ + u8 mm[2] = {reg, dat}; + + return i2c_write(state->i2c, adr, mm, 2); +} + +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, + .buf = msg, .len = len}, + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { + printk("cxd2843: i2c_read error\n"); + return -1; + } + return 0; +} + +static int readregs(struct cxd_state *state, u8 adr, u8 reg, u8 *val, int count) +{ + return i2c_read(state->i2c, adr, ®, 1, val, count); +} + +static int readregst_unlocked(struct cxd_state *cxd, u8 bank, u8 Address, u8 *pValue, u16 count) +{ + int status = 0; + + if (bank != 0xFF && cxd->curbankt != bank) { + status = writereg(cxd, cxd->adrt, 0, bank); + if (status < 0) { + cxd->curbankt = 0xFF; + return status; + } + cxd->curbankt = bank; + } + status = readregs(cxd, cxd->adrt, Address, pValue, count); + return status; +} + +static int readregst(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) +{ + int status; + + mutex_lock(&cxd->mutex); + status = readregst_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); + return status; +} + +static int readregsx_unlocked(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) +{ + int status = 0; + + if (Bank != 0xFF && cxd->curbankx != Bank) { + status = writereg(cxd, cxd->adrx, 0, Bank); + if (status < 0) { + cxd->curbankx = 0xFF; + return status; + } + cxd->curbankx = Bank; + } + status = readregs(cxd, cxd->adrx, Address, pValue, count); + return status; +} + +static int readregsx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) +{ + int status; + + mutex_lock(&cxd->mutex); + status = readregsx_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); + return status; +} + +static int writeregsx_unlocked(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) +{ + int status = 0; + + if (Bank != 0xFF && cxd->curbankx != Bank) { + status = writereg(cxd, cxd->adrx, 0, Bank); + if (status < 0) { + cxd->curbankx = 0xFF; + return status; + } + cxd->curbankx = Bank; + } + status = writeregs(cxd, cxd->adrx, Address, pValue, count); + return status; +} + +static int writeregsx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) +{ + int status; + + mutex_lock(&cxd->mutex); + status = writeregsx_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); + return status; +} + +static int writeregx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 val) +{ + return writeregsx(cxd, Bank, Address, &val, 1); +} + +static int writeregst_unlocked(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) +{ + int status = 0; + + if (Bank != 0xFF && cxd->curbankt != Bank) { + status = writereg(cxd, cxd->adrt, 0, Bank); + if (status < 0) { + cxd->curbankt = 0xFF; + return status; + } + cxd->curbankt = Bank; + } + status = writeregs(cxd, cxd->adrt, Address, pValue, count); + return status; +} + +static int writeregst(struct cxd_state *cxd, u8 Bank, u8 Address, u8 *pValue, u16 count) +{ + int status; + + mutex_lock(&cxd->mutex); + status = writeregst_unlocked(cxd, Bank, Address, pValue, count); + mutex_unlock(&cxd->mutex); + return status; +} + +static int writeregt(struct cxd_state *cxd, u8 Bank, u8 Address, u8 val) +{ + return writeregst(cxd, Bank, Address, &val, 1); +} + +static int writebitsx(struct cxd_state *cxd, u8 Bank, u8 Address, u8 Value, u8 Mask) +{ + int status = 0; + u8 tmp; + + mutex_lock(&cxd->mutex); + status = readregsx_unlocked(cxd, Bank, Address, &tmp, 1); + if (status < 0) + return status; + tmp = (tmp & ~Mask) | Value; + status = writeregsx_unlocked(cxd, Bank, Address, &tmp, 1); + mutex_unlock(&cxd->mutex); + return status; +} + +static int writebitst(struct cxd_state *cxd, u8 Bank, u8 Address, u8 Value, u8 Mask) +{ + int status = 0; + u8 Tmp = 0x00; + + mutex_lock(&cxd->mutex); + status = readregst_unlocked(cxd, Bank, Address, &Tmp, 1); + if (status < 0) + return status; + Tmp = (Tmp & ~Mask) | Value; + status = writeregst_unlocked(cxd, Bank, Address, &Tmp, 1); + mutex_unlock(&cxd->mutex); + return status; +} + +static int FreezeRegsT(struct cxd_state *cxd) +{ + mutex_lock(&cxd->mutex); + return writereg(cxd, cxd->adrt, 1, 1); +} + +static int UnFreezeRegsT(struct cxd_state *cxd) +{ + int status = 0; + + status = writereg(cxd, cxd->adrt, 1, 0); + mutex_unlock(&cxd->mutex); + return status; +} + +static inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; + + tmp64 = (u64)a * (u64)b; + do_div(tmp64, c); + + return (u32) tmp64; +} + +static void Active_to_Sleep(struct cxd_state *state) +{ + if (state->state <= Sleep ) + return; + + writeregt(state, 0x00,0xC3,0x01); // Disable TS + writeregt(state, 0x00,0x80,0x3F); // Enable HighZ 1 + writeregt(state, 0x00,0x81,0xFF); // Enable HighZ 2 + writeregx(state, 0x00,0x18,0x01); // Disable ADC 4 + writeregt(state, 0x00,0x43,0x0A); // Disable ADC 2 // This looks broken (see enable) + writeregt(state, 0x00,0x41,0x0A); // Disable ADC 1 + writeregt(state, 0x00,0x30,0x00); // Disable ADC Clock + writeregt(state, 0x00,0x2F,0x00); // Disable RF level Monitor + writeregt(state, 0x00,0x2C,0x00); // Disable Demod Clock + state->state = Sleep; +} + +static void ActiveT2_to_Sleep(struct cxd_state *state) +{ + if (state->state <= Sleep ) + return; + + writeregt(state, 0x00,0xC3,0x01); // Disable TS + writeregt(state, 0x00,0x80,0x3F); // Enable HighZ 1 + writeregt(state, 0x00,0x81,0xFF); // Enable HighZ 2 + + writeregt(state, 0x13,0x83,0x40); // + writeregt(state, 0x13,0x86,0x21); // + writebitst(state, 0x13,0x9E,0x09,0x0F); // ... + writeregt(state, 0x13,0x9F,0xFB); // + + writeregx(state, 0x00,0x18,0x01); // Disable ADC 4 + writeregt(state, 0x00,0x43,0x0A); // Disable ADC 2 // This looks broken (see enable) + writeregt(state, 0x00,0x41,0x0A); // Disable ADC 1 + writeregt(state, 0x00,0x30,0x00); // Disable ADC Clock + writeregt(state, 0x00,0x2F,0x00); // Disable RF level Monitor + writeregt(state, 0x00,0x2C,0x00); // Disable Demod Clock + state->state = Sleep; +} + +static void ActiveC2_to_Sleep(struct cxd_state *state) +{ + if (state->state <= Sleep ) + return; + + writeregt(state, 0x00,0xC3,0x01); // Disable TS + writeregt(state, 0x00,0x80,0x3F); // Enable HighZ 1 + writeregt(state, 0x00,0x81,0xFF); // Enable HighZ 2 + + writeregt(state, 0x20,0xC2,0x11); // + writebitst(state, 0x25,0x6A,0x02,0x03); // + { + static u8 data[3] = { 0x07, 0x61, 0x36 }; + writeregst(state, 0x25,0x89,data,sizeof(data)); // + } + writebitst(state, 0x25,0xCB,0x05,0x07); // + { + static u8 data[4] = { 0x2E, 0xE0, 0x2E, 0xE0 }; + writeregst(state, 0x25,0xDC,data,sizeof(data)); // + } + writeregt(state, 0x25,0xE2,0x2F); // + writeregt(state, 0x25,0xE5,0x2F); // + writebitst(state, 0x27,0x20,0x00,0x01); // + writebitst(state, 0x27,0x35,0x00,0x01); // + writebitst(state, 0x27,0xD9,0x19,0x3F); // + writebitst(state, 0x2A,0x78,0x01,0x07); // + writeregt(state, 0x2A,0x86,0x08); // + writeregt(state, 0x2A,0x88,0x14); // + writebitst(state, 0x2B,0x2B,0x00,0x1F); // + { + u8 data[2] = { 0x75, 0x75 }; + writeregst(state, 0x2D,0x24,data,sizeof(data)); + } + + writeregx(state, 0x00,0x18,0x01); // Disable ADC 4 + writeregt(state, 0x00,0x43,0x0A); // Disable ADC 2 // This looks broken (see enable) + writeregt(state, 0x00,0x41,0x0A); // Disable ADC 1 + writeregt(state, 0x00,0x30,0x00); // Disable ADC Clock + writeregt(state, 0x00,0x2F,0x00); // Disable RF level Monitor + writeregt(state, 0x00,0x2C,0x00); // Disable Demod Clock + state->state = Sleep; +} + +static int ConfigureTS(struct cxd_state *state, enum EDemodState newDemodState) +{ + int status = 0; + + ///* OSERCKMODE OSERDUTYMODE OTSCKPERIOD OREG_CKSEL_TSIF */ + // { 1, 1, 8, 0 }, /* High Freq, full rate */ + // { 1, 1, 8, 1 }, /* Mid Freq, full rate */ + // { 1, 1, 8, 2 }, /* Low Freq, full rate */ + // { 2, 2, 16, 0 }, /* High Freq, half rate */ + // { 2, 2, 16, 1 }, /* Mid Freq, half rate */ + // { 2, 2, 16, 2 } /* Low Freq, half rate */ + + u8 OSERCKMODE = 1; + u8 OSERDUTYMODE = 1; + u8 OTSCKPERIOD = 8; + u8 OREG_CKSEL_TSIF = state->SerialClockFrequency; + + if (state->SerialClockFrequency >= 3 ) { + OSERCKMODE = 2; + OSERDUTYMODE = 2; + OTSCKPERIOD = 16; + OREG_CKSEL_TSIF = state->SerialClockFrequency - 3; + } + writebitst(state, 0x00, 0xC4, OSERCKMODE, 0x03); // OSERCKMODE + writebitst(state, 0x00, 0xD1, OSERDUTYMODE, 0x03); // OSERDUTYMODE + writeregt(state, 0x00, 0xD9, OTSCKPERIOD); // OTSCKPERIOD + writebitst(state, 0x00, 0x32, 0x00, 0x01); // Disable TS IF + writebitst(state, 0x00, 0x33, OREG_CKSEL_TSIF, 0x03); // OREG_CKSEL_TSIF + writebitst(state, 0x00, 0x32, 0x01, 0x01); // Enable TS IF + + if (newDemodState == ActiveT) + writebitst(state, 0x10, 0x66, 0x01, 0x01); + if (newDemodState == ActiveC) + writebitst(state, 0x40, 0x66, 0x01, 0x01); + + return status; +} + +static void BandSettingT(struct cxd_state *state, u32 iffreq) +{ + u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; + + switch (state->bw) { + case 8: + { + static u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; + static u8 CL_data[] = { 0x01, 0xE0 }; + static u8 NF_data[] = { 0x01, 0x02 }; + + writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x00,0x07); // System Bandwidth + writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency + writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter + break; + } + case 7: + { + static u8 TR_data[] = { 0x14, 0x80, 0x00, 0x00, 0x00 }; + static u8 CL_data[] = { 0x12, 0xF8 }; + static u8 NF_data[] = { 0x00, 0x03 }; + + writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x02,0x07); // System Bandwidth + writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency + writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter + break; + } + case 6: + { + static u8 TR_data[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA }; + static u8 CL_data[] = { 0x1F, 0xDC }; + static u8 NF_data[] = { 0x00, 0x03 }; + + writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x04,0x07); // System Bandwidth + writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency + writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter + break; + } + case 5: + { + static u8 TR_data[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 }; + static u8 CL_data[] = { 0x26, 0x3C }; + static u8 NF_data[] = { 0x00, 0x03 }; + + writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + + writebitst(state, 0x10,0xD7,0x06,0x07); // System Bandwidth + writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency + writeregst(state, 0x17,0x38,NF_data,sizeof(NF_data)); // notch filter + break; + } + } +} + +static void Sleep_to_ActiveT(struct cxd_state *state, u32 iffreq) +{ + printk("%s\n", __FUNCTION__); + + ConfigureTS(state, ActiveT); + + writeregx(state, 0x00,0x17,0x01); // Mode + writeregt(state, 0x00,0x2C,0x01); // Demod Clock + writeregt(state, 0x00,0x2F,0x00); // Disable RF Monitor + writeregt(state, 0x00,0x30,0x00); // Enable ADC Clock + writeregt(state, 0x00,0x41,0x1A); // Enable ADC1 + + { + u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz + //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz + writeregst(state, 0x00,0x43,data,2); // Enable ADC 2+3 + } + writeregx(state, 0x00,0x18,0x00); // Enable ADC 4 + + // -- till here identical to DVB-C (apart from mode) + + writebitst(state, 0x10,0xD2,0x0C,0x1F); // IF AGC Gain + writeregt(state, 0x11,0x6A,0x48); // BB AGC Target Level + + writebitst(state, 0x10,0xA5,0x00,0x01); // ASCOT Off + + writebitst(state, 0x18,0x36,0x40,0x07); // Pre RS Monitoring + writebitst(state, 0x18,0x30,0x01,0x01); // FEC Autorecover + writebitst(state, 0x18,0x31,0x01,0x01); // FEC Autorecover + + writebitst(state, 0x00,0xCE,0x01,0x01); // TSIF ONOPARITY + writebitst(state, 0x00,0xCF,0x01,0x01); // TSIF ONOPARITY_MANUAL_ON + + BandSettingT(state, iffreq); + + writeregt(state, 0x00,0x80,0x28); // Disable HiZ Setting 1 + writeregt(state, 0x00,0x81,0x00); // Disable HiZ Setting 2 +} + +static void BandSettingT2(struct cxd_state *state, u32 iffreq) +{ + u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; + + switch (state->bw) { + default: + case 8: + { + static u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; + writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x00,0x07); // System Bandwidth + } + break; + case 7: + { + static u8 TR_data[] = { 0x14, 0x80, 0x00, 0x00, 0x00 }; + writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x02,0x07); // System Bandwidth + } + break; + case 6: + { + static u8 TR_data[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA }; + writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x04,0x07); // System Bandwidth + } + break; + case 5: + { + static u8 TR_data[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 }; + writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x06,0x07); // System Bandwidth + } + break; + case 1: // 1.7 MHz + { + static u8 TR_data[] = { 0x58, 0xE2, 0xAF, 0xE0, 0xBC }; + writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + + writebitst(state, 0x10,0xD7,0x03,0x07); // System Bandwidth + } + break; + } +} + + +static void Sleep_to_ActiveT2(struct cxd_state *state, u32 iffreq) +{ + ConfigureTS(state, ActiveT2); + + writeregx(state, 0x00, 0x17, 0x02); // Mode + writeregt(state, 0x00, 0x2C, 0x01); // Demod Clock + writeregt(state, 0x00, 0x2F, 0x00); // Disable RF Monitor + writeregt(state, 0x00, 0x30, 0x00); // Enable ADC Clock + writeregt(state, 0x00, 0x41, 0x1A); // Enable ADC1 + + { + u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz + //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz + writeregst(state, 0x00, 0x43,data,2); // Enable ADC 2+3 + } + writeregx(state, 0x00, 0x18, 0x00); // Enable ADC 4 + + writebitst(state, 0x10, 0xD2, 0x0C, 0x1F); //IFAGC coarse gain + writeregt(state, 0x11, 0x6A, 0x50); // BB AGC Target Level + writebitst(state, 0x10, 0xA5, 0x00, 0x01); // ASCOT Off + + writeregt(state, 0x20, 0x8B, 0x3C); // SNR Good count + writebitst(state, 0x2B, 0x76, 0x20, 0x70); // Noise Gain ACQ + + writebitst(state, 0x00, 0xCE, 0x01, 0x01); // TSIF ONOPARITY + writebitst(state, 0x00, 0xCF, 0x01, 0x01); // TSIF ONOPARITY_MANUAL_ON + + writeregt(state, 0x13, 0x83, 0x10); // T2 Inital settings + writeregt(state, 0x13, 0x86, 0x34); // ... + writebitst(state, 0x13, 0x9E, 0x09, 0x0F); // ... + writeregt(state, 0x13, 0x9F, 0xD8); // ... + + BandSettingT2(state, iffreq); + + writeregt(state, 0x00, 0x80, 0x28); // Disable HiZ Setting 1 + writeregt(state, 0x00, 0x81, 0x00); // Disable HiZ Setting 2 +} + + +static void BandSettingC(struct cxd_state *state, u32 iffreq) +{ + u8 data[3]; + data[0] = (iffreq >> 16) & 0xFF; + data[1] = (iffreq >> 8) & 0xFF; + data[2] = (iffreq ) & 0xFF; + writeregst(state, 0x10, 0xB6, data, 3); // iffreq +} + +static void Sleep_to_ActiveC(struct cxd_state *state, u32 iffreq) +{ + ConfigureTS(state, ActiveC); + + writeregx(state, 0x00, 0x17, 0x04); // Mode + writeregt(state, 0x00, 0x2C, 0x01); // Demod Clock + writeregt(state, 0x00, 0x2F, 0x00); // Disable RF Monitor + writeregt(state, 0x00, 0x30, 0x00); // Enable ADC Clock + writeregt(state, 0x00, 0x41, 0x1A); // Enable ADC1 + + { + u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz + //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz + writeregst(state, 0x00, 0x43,data,2); // Enable ADC 2+3 + } + writeregx(state, 0x00, 0x18, 0x00); // Enable ADC 4 + + writebitst(state, 0x10, 0xD2, 0x09, 0x1F); // IF AGC Gain + writeregt(state, 0x11, 0x6A, 0x48); // BB AGC Target Level + writebitst(state, 0x10, 0xA5, 0x00, 0x01); // ASCOT Off + + writebitst(state, 0x40, 0xC3, 0x00, 0x04); // OREG_BNDET_EN_64 + + writebitst(state, 0x00, 0xCE, 0x01, 0x01); // TSIF ONOPARITY + writebitst(state, 0x00, 0xCF, 0x01, 0x01); // TSIF ONOPARITY_MANUAL_ON + + BandSettingC(state, iffreq); + + writeregt(state, 0x00, 0x80, 0x28); // Disable HiZ Setting 1 + writeregt(state, 0x00, 0x81, 0x00); // Disable HiZ Setting 2 +} + +static void BandSettingC2(struct cxd_state *state, u32 iffreq) +{ + u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; + + switch (state->bw) { + case 8: + { + static u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; + static u8 data[2] = { 0x11, 0x9E }; + + writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + + writebitst(state, 0x10,0xD7,0x00,0x07); // System Bandwidth + + writeregst(state, 0x50,0xEC,data,sizeof(data)); // timeout + writeregt(state, 0x50,0xEF,0x11); + writeregt(state, 0x50,0xF1,0x9E); + } + break; + case 6: + { + static u8 TR_data[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA }; + static u8 data[2] = { 0x17, 0x70 }; + + writeregst(state, 0x20,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + writebitst(state, 0x10,0xD7,0x04,0x07); // System Bandwidth + + writeregst(state, 0x50,0xEC,data,sizeof(data)); // timeout + writeregt(state, 0x50,0xEF,0x17); + writeregt(state, 0x50,0xF1,0x70); + } + break; + } +} + +static void Sleep_to_ActiveC2(struct cxd_state *state, u32 iffreq) +{ + ConfigureTS(state, ActiveC2); + + writeregx(state, 0x00,0x17,0x05); // Mode + writeregt(state, 0x00,0x2C,0x01); // Demod Clock + writeregt(state, 0x00,0x2F,0x00); // Disable RF Monitor + writeregt(state, 0x00,0x30,0x00); // Enable ADC Clock + writeregt(state, 0x00,0x41,0x1A); // Enable ADC1 + + { + u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz + //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz + writeregst(state, 0x00,0x43,data,sizeof(data)); // Enable ADC 2+3 + } + writeregx(state, 0x00,0x18,0x00); // Enable ADC 4 + + writebitst(state, 0x10,0xD2,0x0C,0x1F); //IFAGC coarse gain + writeregt(state, 0x11,0x6A,0x50); // BB AGC Target Level + writebitst(state, 0x10,0xA5,0x00,0x01); // ASCOT Off + + writebitst(state, 0x00,0xCE,0x01,0x01); // TSIF ONOPARITY + writebitst(state, 0x00,0xCF,0x01,0x01); // TSIF ONOPARITY_MANUAL_ON + + writeregt(state, 0x20,0xC2,0x00); // + writebitst(state, 0x25,0x6A,0x00,0x03); // + { + u8 data[3] = { 0x0C, 0xD1, 0x40 }; + writeregst(state, 0x25,0x89,data,sizeof(data)); + } + writebitst(state, 0x25,0xCB,0x01,0x07); // + { + u8 data[4] = { 0x7B, 0x00, 0x7B, 0x00 }; + writeregst(state, 0x25,0xDC,data,sizeof(data)); + } + writeregt(state, 0x25,0xE2,0x30); // + writeregt(state, 0x25,0xE5,0x30); // + writebitst(state, 0x27,0x20,0x01,0x01); // + writebitst(state, 0x27,0x35,0x01,0x01); // + writebitst(state, 0x27,0xD9,0x18,0x3F); // + writebitst(state, 0x2A,0x78,0x00,0x07); // + writeregt(state, 0x2A,0x86,0x20); // + writeregt(state, 0x2A,0x88,0x32); // + writebitst(state, 0x2B,0x2B,0x10,0x1F); // + { + u8 data[2] = { 0x01, 0x01 }; + writeregst(state, 0x2D,0x24,data,sizeof(data)); + } + + BandSettingC2(state, iffreq); + + writeregt(state, 0x00,0x80,0x28); // Disable HiZ Setting 1 + writeregt(state, 0x00,0x81,0x00); // Disable HiZ Setting 2 +} + + +static void BandSettingIT(struct cxd_state *state, u32 iffreq) +{ + u8 IF_data[3] = { (iffreq >> 16) & 0xff, (iffreq >> 8) & 0xff, iffreq & 0xff}; + + switch (state->bw) { + default: + case 8: + { + static u8 TR_data[] = { 0x0F, 0x22, 0x80, 0x00, 0x00 }; // 20.5/41 + static u8 CL_data[] = { 0x15, 0xA8 }; + + // static u8 TR_data[] = { 0x11, 0xB8, 0x00, 0x00, 0x00 }; // 24 + writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + + writeregt(state, 0x10,0xD7,0x00); // System Bandwidth + //static u8 CL_data[] = { 0x13, 0xFC }; + writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency + } + break; + case 7: + { + static u8 TR_data[] = { 0x11, 0x4c, 0x00, 0x00, 0x00 }; + static u8 CL_data[] = { 0x1B, 0x5D }; + + //static u8 TR_data[] = { 0x14, 0x40, 0x00, 0x00, 0x00 }; + writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + + writeregt(state, 0x10,0xD7,0x02); // System Bandwidth + //static u8 CL_data[] = { 0x1A, 0xFA }; + writeregst(state, 0x10,0xD9,CL_data,sizeof(CL_data)); // core latency + } + break; + case 6: + { + static u8 TR_data[] = { 0x14, 0x2E, 0x00, 0x00, 0x00 }; + static u8 CL_data[] = { 0x1F, 0xEC }; + //static u8 TR_data[] = { 0x17, 0xA0, 0x00, 0x00, 0x00 }; + //static u8 CL_data[] = { 0x1F, 0x79 }; + + writeregst(state, 0x10,0x9F,TR_data,sizeof(TR_data)); // Timing recovery + // Add EQ Optimisation for tuner here + writeregst(state, 0x10,0xB6,IF_data,sizeof(IF_data)); // iffreq + + writeregt(state, 0x10,0xD7,0x04); // System Bandwidth + writeregst(state, 0x10, 0xD9, CL_data, sizeof(CL_data)); // core latency + } + break; + } +} + +static void Sleep_to_ActiveIT(struct cxd_state *state, u32 iffreq) +{ + static u8 data2[3] = { 0xB9,0xBA,0x63 }; // 20.5/41 MHz + //static u8 data2[3] = { 0xB7,0x1B,0x00 }; // 24 MHz + static u8 TSIF_data[2] = { 0x61,0x60 } ; // 20.5/41 MHz + //static u8 TSIF_data[2] = { 0x60,0x00 } ; // 24 MHz + + printk("%s\n", __FUNCTION__); + + ConfigureTS(state, ActiveIT); + + // writeregx(state, 0x00,0x17,0x01); // 2838 has only one Mode + writeregt(state, 0x00,0x2C,0x01); // Demod Clock + writeregt(state, 0x00,0x2F,0x00); // Disable RF Monitor + writeregt(state, 0x00,0x30,0x00); // Enable ADC Clock + writeregt(state, 0x00,0x41,0x1A); // Enable ADC1 + + { + u8 data[2] = { 0x09, 0x54 }; // 20.5 MHz, 24 MHz + //u8 data[2] = { 0x0A, 0xD4 }; // 41 MHz + writeregst(state, 0x00,0x43,data,2); // Enable ADC 2+3 + } + writeregx(state, 0x00,0x18,0x00); // Enable ADC 4 + + writeregst(state, 0x60,0xA8,data2,sizeof(data2)); + + writeregst(state, 0x10,0xBF,TSIF_data,sizeof(TSIF_data)); + + writeregt(state, 0x10,0xE2,0xCE); // OREG_PNC_DISABLE + writebitst(state, 0x10,0xA5,0x00,0x01); // ASCOT Off + + BandSettingIT(state, iffreq); + + writeregt(state, 0x00,0x80,0x28); // Disable HiZ Setting 1 + writeregt(state, 0x00,0x81,0x00); // Disable HiZ Setting 2 +} + +static void T2_SetParameters(struct cxd_state *state) +{ + u8 Profile = 0x01; // Profile Base + u8 notT2time = 12; // early unlock detection time + + //u8 Profile = 0x05; // Lite + //u8 notT2time = 40; + + //u8 Profile = 0x00; // Any + //u8 notT2time = 40; + + + if (state->PLPNumber != 0xffffffff) { + writeregt(state, 0x23, 0xAF, state->PLPNumber); + writeregt(state, 0x23, 0xAD, 0x01); + } else { + writeregt(state, 0x23, 0xAD, 0x00); + } + + writebitst(state, 0x2E, 0x10, Profile, 0x07); + writeregt(state, 0x2B, 0x19, notT2time); +} + +static void C2_ReleasePreset(struct cxd_state *state) +{ + { + static u8 data[2] = { 0x02, 0x80}; + writeregst(state, 0x27,0xF4,data,sizeof(data)); + } + writebitst(state, 0x27,0x51,0x40,0xF0); + writebitst(state, 0x27,0x73,0x07,0x0F); + writebitst(state, 0x27,0x74,0x19,0x3F); + writebitst(state, 0x27,0x75,0x19,0x3F); + writebitst(state, 0x27,0x76,0x19,0x3F); + if (state->bw == 6 ) { + static u8 data[5] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA}; + writeregst(state, 0x20,0x9F,data,sizeof(data)); + } else { + static u8 data[5] = { 0x11, 0xF0, 0x00, 0x00, 0x00}; + writeregst(state, 0x20,0x9F,data,sizeof(data)); + } + writebitst(state, 0x27,0xC9,0x07,0x07); + writebitst(state, 0x20,0xC2,0x11,0x33); + { + static u8 data[10] = { 0x16, 0xF0, 0x2B, 0xD8, 0x16, 0x16, 0xF0, 0x2C, 0xD8, 0x16 }; + writeregst(state, 0x2A,0x20,data,sizeof(data)); + } + { + static u8 data[4] = { 0x00, 0x00, 0x00, 0x00 }; + writeregst(state, 0x50,0x6B,data,sizeof(data)); + } + writebitst(state, 0x50,0x6F,0x00,0x40); // Disable Preset +} + +static void C2_DemodSetting2(struct cxd_state *state) +{ + u8 data[6]; + u32 TunePosition = state->frontend.dtv_property_cache.frequency / 1000; + + if (state->bw == 6) { + TunePosition = ((TunePosition * 1792) / 3) / 1000; + } else { + TunePosition = (TunePosition * 448) / 1000; + } + TunePosition = ((TunePosition + 6) / 12) * 12; + + printk("TunePosition = %u\n", TunePosition); + + data[0] = ( (TunePosition >> 16) & 0xFF ); + data[1] = ( (TunePosition >> 8) & 0xFF ); + data[2] = ( (TunePosition ) & 0xFF ); + data[3] = 0x02; + data[4] = (state->DataSliceID & 0xFF); + data[5] = (state->PLPNumber & 0xFF); + writeregst(state, 0x50, 0x7A, data, sizeof(data)); + writebitst(state, 0x50, 0x87, 0x01, 0x01); /* Preset Clear */ +} + +static void Stop(struct cxd_state *state) +{ + writeregt(state, 0x00,0xC3,0x01); /* Disable TS */ +} + +static void ShutDown(struct cxd_state *state) +{ + switch (state->state) { + case ActiveT2: + ActiveT2_to_Sleep(state); + break; + case ActiveC2: + ActiveC2_to_Sleep(state); + break; + default: + Active_to_Sleep(state); + break; + } +} + +static int gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct cxd_state *state = fe->demodulator_priv; + + return writebitsx(state, 0xFF, 0x08, enable ? 0x01 : 0x00, 0x01); +} + +static void release(struct dvb_frontend* fe) +{ + struct cxd_state *state = fe->demodulator_priv; + + Stop(state); + ShutDown(state); + kfree(state); +} + +static int Start(struct cxd_state *state, u32 IntermediateFrequency) +{ + enum EDemodState newDemodState = Unknown; + u32 iffreq; + + if (state->state < Sleep ) { + return -EINVAL; + } + + iffreq = MulDiv32(IntermediateFrequency, 16777216, 41000000); + + switch(state->omode) { + case OM_DVBT: + if (state->type == CXD2838 ) + return -EINVAL; + newDemodState = ActiveT; + break; + case OM_DVBT2: + if (state->type == CXD2838 ) + return -EINVAL; + newDemodState = ActiveT2; + break; + case OM_DVBC: + case OM_QAM_ITU_C: + if (state->type == CXD2838 ) + return -EINVAL; + newDemodState = ActiveC; + break; + case OM_DVBC2: + if (state->type != CXD2843 ) + return -EINVAL; + newDemodState = ActiveC2; + break; + case OM_ISDBT: + if (state->type != CXD2838 ) + return -EINVAL; + newDemodState = ActiveIT; + break; + default: + return -EINVAL; + } + + state->LockTimeout = 0; + state->TSLockTimeout = 0; + state->L1PostTimeout = 0; + state->FirstTimeLock = 1; + + if (state->state == newDemodState ) { + writeregt(state, 0x00, 0xC3, 0x01); /* Disable TS Output */ + switch (newDemodState) { + case ActiveT: + writeregt(state, 0x10,0x67, 0x00); /* Stick with HP ( 0x01 = LP ) */ + BandSettingT(state, iffreq); + break; + case ActiveT2: + T2_SetParameters(state); + BandSettingT2(state, iffreq); + break; + case ActiveC: + BandSettingC(state, iffreq); + break; + case ActiveC2: + BandSettingC2(state, iffreq); + C2_ReleasePreset(state); + C2_DemodSetting2(state); + break; + case ActiveIT: + BandSettingIT(state, iffreq); + break; + default: + break; + } + } else { + if (state->state > Sleep ) { + switch (state->state) { + case ActiveT2: + ActiveT2_to_Sleep(state); + break; + case ActiveC2: + ActiveC2_to_Sleep(state); + break; + default: + Active_to_Sleep(state); + break; + } + } + switch (newDemodState) { + case ActiveT: + writeregt(state, 0x10,0x67, 0x00); // Stick with HP ( 0x01 = LP ) + Sleep_to_ActiveT(state, iffreq); + break; + case ActiveT2: + T2_SetParameters(state); + Sleep_to_ActiveT2(state, iffreq); + break; + case ActiveC: + Sleep_to_ActiveC(state, iffreq); + break; + case ActiveC2: + Sleep_to_ActiveC2(state, iffreq); + C2_ReleasePreset(state); + C2_DemodSetting2(state); + break; + case ActiveIT: + Sleep_to_ActiveIT(state, iffreq); + break; + default: + break; + } + } + state->state = newDemodState; + writeregt(state, 0x00, 0xFE, 0x01); // SW Reset + writeregt(state, 0x00, 0xC3, 0x00); // Enable TS Output + + return 0; +} + +static int set_parameters(struct dvb_frontend *fe) +{ + int stat; + struct cxd_state *state = fe->demodulator_priv; + u32 IF; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: + state->omode = OM_DVBC; + break; + case SYS_DVBC2: + state->omode = OM_DVBC2; + break; + case SYS_DVBT: + state->omode = OM_DVBT; + break; + case SYS_DVBT2: + state->omode = OM_DVBT2; + break; + case SYS_ISDBT: + state->omode = OM_ISDBT; + break; + default: + return -EINVAL; + } + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe); + state->bandwidth = fe->dtv_property_cache.bandwidth_hz; + state->bw = (fe->dtv_property_cache.bandwidth_hz + 999999) / 1000000; + state->DataSliceID = 0;//fe->dtv_property_cache.slice_id; + state->PLPNumber = fe->dtv_property_cache.stream_id; + fe->ops.tuner_ops.get_if_frequency(fe, &IF); + stat = Start(state, IF); + return stat; +} + + +static void init(struct cxd_state *state) +{ + u8 data[2] = {0x00, 0x00}; // 20.5 MHz + + state->omode = OM_NONE; + state->state = Unknown; + + writeregx(state, 0xFF, 0x02, 0x00); + msleep(4); + writeregx(state, 0x00, 0x10, 0x01); + + writeregsx(state, 0x00, 0x13, data, 2); + writeregx(state, 0x00, 0x10, 0x00); + msleep(2); + state->curbankx = 0xFF; + state->curbankt = 0xFF; + + writeregt(state, 0x00, 0x43, 0x0A); + writeregt(state, 0x00, 0x41, 0x0A); + if (state->type == CXD2838) + writeregt(state, 0x60, 0x5A, 0x00); + + writebitst(state, 0x10, 0xCB, 0x00, 0x40); + writeregt(state, 0x10, 0xCD, state->IF_FS); + + writebitst(state, 0x00, 0xC4, 0x80, 0x98); + writebitst(state, 0x00, 0xC5, 0x00, 0x07); + writebitst(state, 0x00, 0xCB, 0x00, 0x01); + writebitst(state, 0x00, 0xC6, 0x00, 0x1D); + writebitst(state, 0x00, 0xC8, 0x00, 0x1D); + writebitst(state, 0x00, 0xC9, 0x00, 0x1D); + writebitst(state, 0x00, 0x83, 0x00, 0x07); + writeregt(state, 0x00, 0x84, 0x00); + writebitst(state, 0x00, 0xD3, (state->type == CXD2838) ? 0x01 : 0x00, 0x01); + writebitst(state, 0x00, 0xDE, 0x00, 0x01); + + state->state = Sleep; +} + + +static void init_state(struct cxd_state *state, struct cxd2843_cfg *cfg) +{ + state->adrt = cfg->adr; + state->adrx = cfg->adr + 0x02; + state->curbankt = 0xff; + state->curbankx = 0xff; + + mutex_init(&state->mutex); + + state->SerialMode = 1; + state->ContinuousClock = 1; + state->SerialClockFrequency = + (cfg->ts_clock >= 1 && cfg->ts_clock <= 5) ? cfg->ts_clock : 1; // 1 = fastest (82 MBit/s), 5 = slowest + state->SerialClockFrequency = 1; + state->IF_FS = 0x50; // IF Fullscale 0x50 = 1.4V, 0x39 = 1V, 0x28 = 0.7V +} + +static int get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + //return c_get_tune_settings(fe, sets); + default: + /* DVB-T: Use info.frequency_stepsize. */ + return -EINVAL; + } +} + +static int read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct cxd_state *state = fe->demodulator_priv; + u8 rdata; + + *status=0; + switch (state->state) { + case ActiveC: + readregst(state, 0x40, 0x88, &rdata, 1); + if (rdata & 0x02) + break; + if (rdata & 0x01) { + *status |= 0x07; + readregst(state, 0x40, 0x10, &rdata, 1); + if (rdata & 0x20) + *status |= 0x1f; + } + break; + case ActiveT: + readregst(state, 0x10, 0x10, &rdata, 1) ; + if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { + *status |= 0x07; + if (rdata & 0x20) + *status |= 0x1f; + } + break; + case ActiveT2: + readregst(state, 0x20, 0x10, &rdata, 1); + if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { + *status |= 0x07; + if (rdata & 0x20) + *status |= 0x08; + } + if (*status & 0x08) { + readregst(state, 0x22, 0x12, &rdata, 1); + if (rdata & 0x01) + *status |= 0x10; + } + break; + case ActiveC2: + readregst(state, 0x20, 0x10, &rdata, 1); + if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { + *status |= 0x07; + if (rdata & 0x20) + *status |= 0x18; + } + if ((*status & 0x10) && state->FirstTimeLock) { + u8 data; + + // Change1stTrial + readregst(state, 0x28, 0xE6, &rdata, 1); + data = rdata & 1; + readregst(state, 0x50, 0x15, &rdata, 1); + data |= ((rdata & 0x18) >> 2); + //writebitst(state, 0x50,0x6F,rdata,0x07); + state->FirstTimeLock = 0; + } + break; + case ActiveIT: + readregst(state, 0x60, 0x10, &rdata, 1); + if (rdata & 0x10) + break; + if (rdata & 0x02) { + *status |= 0x07; + if (rdata & 0x01) + *status |= 0x18; + } + break; + default: + break; + } + state->last_status = *status; + return 0; +} + +static int read_ber(struct dvb_frontend *fe, u32 *ber) +{ + //struct cxd_state *state = fe->demodulator_priv; + + *ber = 0; + return 0; +} + +static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + if (fe->ops.tuner_ops.get_rf_strength) + fe->ops.tuner_ops.get_rf_strength(fe, strength); + else + *strength = 0; + return 0; +} + +static s32 Log10x100(u32 x) +{ + static u32 LookupTable[100] = { + 101157945, 103514217, 105925373, 108392691, 110917482, + 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 + 127350308, 130316678, 133352143, 136458314, 139636836, + 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 + 160324539, 164058977, 167880402, 171790839, 175792361, + 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 + 201836636, 206538016, 211348904, 216271852, 221309471, + 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 + 254097271, 260015956, 266072506, 272270131, 278612117, + 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 + 319889511, 327340695, 334965439, 342767787, 350751874, + 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 + 402717034, 412097519, 421696503, 431519077, 441570447, + 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 + 506990708, 518800039, 530884444, 543250331, 555904257, + 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 + 638263486, 653130553, 668343918, 683911647, 699841996, + 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 + 803526122, 822242650, 841395142, 860993752, 881048873, + 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 + }; + s32 y; + int i; + + if (x == 0) + return 0; + y = 800; + if (x >= 1000000000) { + x /= 10; + y += 100; + } + + while (x < 100000000) { + x *= 10; + y -= 100; + } + i = 0; + while (i < 100 && x > LookupTable[i]) + i += 1; + y += i; + return y; +} + +#if 0 +static void GetPLPIds(struct cxd_state *state, u32 nValues, u8 *Values, u32 *Returned) +{ + u8 nPids = 0; + + *Returned = 0; + if (state->state != ActiveT2 ) + return; + if (state->last_status != 0x1f) + return; + + FreezeRegsT(state); + readregst_unlocked(state, 0x22, 0x7F, &nPids, 1); + + Values[0] = nPids; + if( nPids >= nValues ) + nPids = nValues - 1; + + readregst_unlocked(state, 0x22, 0x80, &Values[1], nPids > 128 ? 128 : nPids); + + if( nPids > 128 ) + readregst_unlocked(state, 0x23, 0x10, &Values[129], nPids - 128); + + *Returned = nPids + 1; + + UnFreezeRegsT(state); +} +#endif + +static void GetSignalToNoiseIT(struct cxd_state *state, u32 *SignalToNoise) +{ + u8 Data[2]; + u32 reg; + + FreezeRegsT(state); + readregst_unlocked(state, 0x60, 0x28, Data, sizeof(Data)); + UnFreezeRegsT(state); + + reg = (Data[0] << 8) | Data[1]; + if (reg > 51441) + reg = 51441; + + if (state->bw == 8) { + if (reg > 1143) + reg = 1143; + *SignalToNoise = (Log10x100(reg) - Log10x100(1200 - reg)) + 220; + } else + *SignalToNoise = Log10x100(reg) - 90; +} + +static void GetSignalToNoiseC2(struct cxd_state *state, u32 *SignalToNoise) +{ + u8 Data[2]; + u32 reg; + + FreezeRegsT(state); + readregst_unlocked(state, 0x20, 0x28, Data, sizeof(Data)); + UnFreezeRegsT(state); + + reg = (Data[0] << 8) | Data[1]; + if (reg > 51441) + reg = 51441; + + *SignalToNoise = (Log10x100(reg) - Log10x100(55000 - reg)) + 384; +} + + +static void GetSignalToNoiseT2(struct cxd_state *state, u32 *SignalToNoise) +{ + u8 Data[2]; + u32 reg; + + FreezeRegsT(state); + readregst_unlocked(state, 0x20, 0x28, Data, sizeof(Data)); + UnFreezeRegsT(state); + + reg = (Data[0] << 8) | Data[1]; + if (reg > 10876) + reg = 10876; + + *SignalToNoise = (Log10x100(reg) - Log10x100(12600 - reg)) + 320; +} + +static void GetSignalToNoiseT(struct cxd_state *state, u32 *SignalToNoise) +{ + u8 Data[2]; + u32 reg; + + FreezeRegsT(state); + readregst_unlocked(state, 0x10, 0x28, Data, sizeof(Data)); + UnFreezeRegsT(state); + + reg = (Data[0] << 8) | Data[1]; + if (reg > 4996) + reg = 4996; + + *SignalToNoise = (Log10x100(reg) - Log10x100(5350 - reg)) + 285; +} + +static void GetSignalToNoiseC(struct cxd_state *state, u32 *SignalToNoise) +{ + u8 Data[2]; + u8 Constellation = 0; + u32 reg; + + *SignalToNoise = 0; + + FreezeRegsT(state); + readregst_unlocked(state, 0x40, 0x19, &Constellation, 1); + readregst_unlocked(state, 0x40, 0x4C, Data, sizeof(Data)); + UnFreezeRegsT(state); + + reg = ((u32)(Data[0] & 0x1F) << 8) | (Data[1]); + if (reg == 0) + return; + + switch (Constellation & 0x07) { + case 0: // QAM 16 + case 2: // QAM 64 + case 4: // QAM 256 + if (reg < 126) + reg = 126; + *SignalToNoise = ((439 - Log10x100(reg)) * 2134 + 500) / 1000; + break; + case 1: // QAM 32 + case 3: // QAM 128 + if (reg < 69) + reg = 69; + *SignalToNoise = ((432 - Log10x100(reg)) * 2015 + 500) / 1000; + break; + } +} + +static int read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct cxd_state *state = fe->demodulator_priv; + u32 SNR = 0; + + *snr = 0; + if (state->last_status != 0x1f) + return 0; + + switch (state->state) { + case ActiveC: + GetSignalToNoiseC(state, &SNR); + break; + case ActiveC2: + GetSignalToNoiseC2(state, &SNR); + break; + case ActiveT: + GetSignalToNoiseT(state, &SNR); + break; + case ActiveT2: + GetSignalToNoiseT2(state, &SNR); + break; + case ActiveIT: + GetSignalToNoiseIT(state, &SNR); + break; + default: + break; + } + *snr = SNR; + return 0; +} + +static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + return 0; +} + +static struct dvb_frontend_ops common_ops_2843 = { + .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2, SYS_DVBC2 }, + .info = { + .name = "CXD2843 DVB-C/C2 DVB-T/T2", + .frequency_stepsize = 166667, /* DVB-T only */ + .frequency_min = 47000000, /* DVB-T: 47125000 */ + .frequency_max = 865000000, /* DVB-C: 862000000 */ + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = /* DVB-C */ + FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | + FE_CAN_FEC_AUTO | + /* DVB-T */ + FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS + }, + .release = release, + .i2c_gate_ctrl = gate_ctrl, + .set_frontend = set_parameters, + + .get_tune_settings = get_tune_settings, + .read_status = read_status, + .read_ber = read_ber, + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, +}; + +static struct dvb_frontend_ops common_ops_2837 = { + .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2}, + .info = { + .name = "CXD2837 DVB-C DVB-T/T2", + .frequency_stepsize = 166667, /* DVB-T only */ + .frequency_min = 47000000, /* DVB-T: 47125000 */ + .frequency_max = 865000000, /* DVB-C: 862000000 */ + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = /* DVB-C */ + FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | + FE_CAN_FEC_AUTO | + /* DVB-T */ + FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS + }, + .release = release, + .i2c_gate_ctrl = gate_ctrl, + .set_frontend = set_parameters, + + .get_tune_settings = get_tune_settings, + .read_status = read_status, + .read_ber = read_ber, + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, +}; + +static struct dvb_frontend_ops common_ops_2838 = { + .delsys = { SYS_ISDBT }, + .info = { + .name = "CXD2838 ISDB-T", + .frequency_stepsize = 166667, + .frequency_min = 47000000, + .frequency_max = 865000000, + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS + }, + .release = release, + .i2c_gate_ctrl = gate_ctrl, + .set_frontend = set_parameters, + + .get_tune_settings = get_tune_settings, + .read_status = read_status, + .read_ber = read_ber, + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, +}; + +static int probe(struct cxd_state *state) +{ + u8 ChipID = 0x00; + int status; + + status = readregst(state, 0x00, 0xFD, &ChipID, 1); + + if (status) { + status = readregsx(state, 0x00, 0xFD, &ChipID, 1); + } + if (status) + return status; + + //printk("ChipID = %02X\n", ChipID); + switch (ChipID) { + case 0xa4: + state->type = CXD2843; + memcpy(&state->frontend.ops, &common_ops_2843, sizeof(struct dvb_frontend_ops)); + break; + case 0xb1: + state->type = CXD2837; + memcpy(&state->frontend.ops, &common_ops_2837, sizeof(struct dvb_frontend_ops)); + break; + case 0xb0: + state->type = CXD2838; + memcpy(&state->frontend.ops, &common_ops_2838, sizeof(struct dvb_frontend_ops)); + break; + default: + return -1; + } + state->frontend.demodulator_priv = state; + return 0; +} + +struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, struct cxd2843_cfg *cfg) +{ + struct cxd_state *state = NULL; + + state = kzalloc(sizeof(struct cxd_state), GFP_KERNEL); + if (!state) + return NULL; + + state->i2c = i2c; + init_state(state, cfg); + if (probe(state) == 0) { + init(state); + return &state->frontend; + } + printk("cxd2843: not found\n"); + kfree(state); + return NULL; +} + +MODULE_DESCRIPTION("CXD2843/37/38 driver"); +MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(cxd2843_attach); + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/cxd2843.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,14 @@ +#ifndef _CXD2843_H_ +#define _CXD2843_H_ + +#include +#include + +struct cxd2843_cfg { + u8 adr; + u32 ts_clock; +}; + +extern struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, struct cxd2843_cfg *cfg); + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,10 @@ +#ifndef _DRXK_H_ +#define _DRXK_H_ + +#include +#include + +extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, + u8 adr, + struct dvb_frontend **fe_t); +#endif Binary files /tmp/E8GjFYYGeu/dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_a3.mc and /tmp/G28E6P4D0c/dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_a3.mc differ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,5097 @@ +/* + * drxk_hard: DRX-K DVB-C/T demodulator driver + * + * Copyright (C) 2010-2011 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "drxk.h" +#include "drxk_hard.h" + +static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); +static int PowerDownQAM(struct drxk_state *state); +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode); +static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, + s32 tunerFreqOffset); +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +static int DVBTStart(struct drxk_state *state); +static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, + s32 tunerFreqOffset); +static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); +static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); +static int SwitchAntennaToQAM(struct drxk_state *state); +static int SwitchAntennaToDVBT(struct drxk_state *state); + +static bool IsDVBT(struct drxk_state *state) +{ + return state->m_OperationMode == OM_DVBT; +} + +static bool IsQAM(struct drxk_state *state) +{ + return state->m_OperationMode == OM_QAM_ITU_A || + state->m_OperationMode == OM_QAM_ITU_B || + state->m_OperationMode == OM_QAM_ITU_C; +} + +bool IsA1WithPatchCode(struct drxk_state *state) +{ + return state->m_DRXK_A1_PATCH_CODE; +} + +bool IsA1WithRomCode(struct drxk_state *state) +{ + return state->m_DRXK_A1_ROM_CODE; +} + +#define NOA1ROM 0 + +#ifndef CHK_ERROR + #define CHK_ERROR(s) if ((status = s) < 0) break +#endif + +#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) +#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) + +#define DEFAULT_MER_83 165 +#define DEFAULT_MER_93 250 + +#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) +#endif + +#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) +#endif + +#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH +#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06) +#endif + +#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 +#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 + +#ifndef DRXK_KI_RAGC_ATV +#define DRXK_KI_RAGC_ATV 4 +#endif +#ifndef DRXK_KI_IAGC_ATV +#define DRXK_KI_IAGC_ATV 6 +#endif +#ifndef DRXK_KI_DAGC_ATV +#define DRXK_KI_DAGC_ATV 7 +#endif + +#ifndef DRXK_KI_RAGC_QAM +#define DRXK_KI_RAGC_QAM 3 +#endif +#ifndef DRXK_KI_IAGC_QAM +#define DRXK_KI_IAGC_QAM 4 +#endif +#ifndef DRXK_KI_DAGC_QAM +#define DRXK_KI_DAGC_QAM 7 +#endif +#ifndef DRXK_KI_RAGC_DVBT +#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) +#endif +#ifndef DRXK_KI_IAGC_DVBT +#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) +#endif +#ifndef DRXK_KI_DAGC_DVBT +#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) +#endif + +#ifndef DRXK_AGC_DAC_OFFSET +#define DRXK_AGC_DAC_OFFSET (0x800) +#endif + +#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ +#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) +#endif + +#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ +#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) +#endif + +#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ +#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) +#endif + +#ifndef DRXK_QAM_SYMBOLRATE_MAX +#define DRXK_QAM_SYMBOLRATE_MAX (7233000) +#endif + +#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 +#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 +#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 +#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 +#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 +#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 +#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 +#define DRXK_BL_ROM_OFFSET_UCODE 0 + +#define DRXK_BLC_TIMEOUT 100 + +#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 +#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 + +#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 + +#ifndef DRXK_OFDM_NE_NOTCH_WIDTH +#define DRXK_OFDM_NE_NOTCH_WIDTH (4) +#endif + +#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) +#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) +#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) +#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) +#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) + +static inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; + + tmp64 = (u64)a * (u64)b; + do_div(tmp64, c); + + return (u32) tmp64; +} + +inline u32 Frac28a(u32 a, u32 c) +{ + int i = 0; + u32 Q1 = 0; + u32 R0 = 0; + + R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ + Q1 = a / c; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i = 0; i < 7; i++) { + Q1 = (Q1 << 4) | (R0 / c); + R0 = (R0 % c) << 4; + } + /* rounding */ + if ((R0 >> 3) >= c) + Q1++; + + return Q1; +} + +static u32 Log10Times100(u32 x) +{ + static const u8 scale = 15; + static const u8 indexWidth = 5; + u8 i = 0; + u32 y = 0; + u32 d = 0; + u32 k = 0; + u32 r = 0; + /* + log2lut[n] = (1< 0; k--) { + if (x & (((u32)1) << scale)) + break; + x <<= 1; + } + } else { + for (k = scale; k < 31 ; k++) { + if ((x & (((u32)(-1)) << (scale+1))) == 0) + break; + x >>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for divison: log(x) = log(x/y)+log(y) */ + y = k * ((((u32)1) << scale) * 200); + + /* remove integer part */ + x &= ((((u32)1) << scale)-1); + /* get index */ + i = (u8) (x >> (scale - indexWidth)); + /* compute delta (x - a) */ + d = x & ((((u32)1) << (scale - indexWidth)) - 1); + /* compute log, multiplication (d* (..)) must be within range ! */ + y += log2lut[i] + + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y >> 1); + /* rounding */ + if (y & ((u32)1)) + r++; + return (r); +} + +/****************************************************************************/ +/* I2C **********************************************************************/ +/****************************************************************************/ + +static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) +{ + struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 }}; + return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +} + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = + {.addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk("i2c_write error\n"); + return -1; + } + return 0; +} + +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, + .buf = msg, .len = len}, + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { + printk("i2c_read error\n"); + return -1; + } + return 0; +} + +static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) +{ + u8 adr=state->demod_address, mm1[4], mm2[2], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm1[0] = (((reg << 1) & 0xFF) | 0x01); + mm1[1] = ((reg >> 16) & 0xFF); + mm1[2] = ((reg >> 24) & 0xFF) | flags; + mm1[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm1[0] = ((reg << 1) & 0xFF); + mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) + return -1; + if (data) + *data = mm2[0] | (mm2[1] << 8); + return 0; +} + +static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) +{ + return Read16(state, reg, data, 0); +} + +static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) +{ + u8 adr = state->demod_address, mm1[4], mm2[4], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm1[0] = (((reg << 1) & 0xFF) | 0x01); + mm1[1] = ((reg >> 16) & 0xFF); + mm1[2] = ((reg >> 24) & 0xFF) | flags; + mm1[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm1[0] = ((reg << 1) & 0xFF); + mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) + return -1; + if (data) + *data = mm2[0] | (mm2[1] << 8) | + (mm2[2] << 16) | (mm2[3] << 24); + return 0; +} + +static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) +{ + u8 adr = state->demod_address, mm[6], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm[0] = (((reg << 1) & 0xFF) | 0x01); + mm[1] = ((reg >> 16) & 0xFF); + mm[2] = ((reg >> 24) & 0xFF) | flags; + mm[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm[0] = ((reg << 1) & 0xFF); + mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + mm[len] = data & 0xff; + mm[len+1] = (data >>8) & 0xff; + if (i2c_write(state->i2c, adr, mm, len + 2) < 0) + return -1; + return 0; +} + +static int Write16_0(struct drxk_state *state, u32 reg, u16 data) +{ + return Write16(state, reg, data, 0); +} + +static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) +{ + u8 adr = state->demod_address, mm[8], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm[0] = (((reg << 1) & 0xFF) | 0x01); + mm[1] = ((reg >> 16) & 0xFF); + mm[2] = ((reg >> 24) & 0xFF) | flags; + mm[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm[0] = ((reg << 1) & 0xFF); + mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + mm[len] = data & 0xff; + mm[len+1] = (data >> 8) & 0xff; + mm[len+2] = (data >> 16) & 0xff; + mm[len+3] = (data >> 24) & 0xff; + if (i2c_write(state->i2c, adr, mm, len+4) < 0) + return -1; + return 0; +} + +static int WriteBlock(struct drxk_state *state, u32 Address, + const int BlockSize, const u8 pBlock[], u8 Flags) +{ + int status = 0, BlkSize = BlockSize; +#ifdef I2C_LONG_ADR + Flags |= 0xC0; +#endif + while (BlkSize > 0) { + int Chunk = BlkSize > state->m_ChunkSize ? + state->m_ChunkSize : BlkSize ; + u8 *AdrBuf = &state->Chunk[0]; + u32 AdrLength = 0; + + if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { + AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); + AdrBuf[1] = ((Address >> 16) & 0xFF); + AdrBuf[2] = ((Address >> 24) & 0xFF); + AdrBuf[3] = ((Address >> 7) & 0xFF); + AdrBuf[2] |= Flags; + AdrLength = 4; + if (Chunk == state->m_ChunkSize) + Chunk -= 2; + } else { + AdrBuf[0] = ((Address << 1) & 0xFF); + AdrBuf[1] = (((Address >> 16) & 0x0F) | + ((Address >> 18) & 0xF0)); + AdrLength = 2; + } + memcpy(&state->Chunk[AdrLength], pBlock, Chunk); + status = i2c_write(state->i2c, state->demod_address, + &state->Chunk[0], Chunk+AdrLength); + if (status<0) { + printk("I2C Write error\n"); + break; + } + pBlock += Chunk; + Address += (Chunk >> 1); + BlkSize -= Chunk; + } + return status; +} + +#ifndef DRXK_MAX_RETRIES_POWERUP +#define DRXK_MAX_RETRIES_POWERUP 20 +#endif + +int PowerUpDevice(struct drxk_state *state) +{ + int status; + u8 data = 0; + u16 retryCount = 0; + + status = i2c_read1(state->i2c, state->demod_address, &data); + if (status<0) + do { + data = 0; + if (i2c_write(state->i2c, + state->demod_address, &data, 1) < 0) + printk("powerup failed\n"); + msleep(10); + retryCount++ ; + } while (i2c_read1(state->i2c, + state->demod_address, &data) < 0 && + (retryCount < DRXK_MAX_RETRIES_POWERUP)); + if (retryCount >= DRXK_MAX_RETRIES_POWERUP) + return -1; + do { + /* Make sure all clk domains are active */ + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, + SIO_CC_PWD_MODE_LEVEL_NONE)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, + SIO_CC_UPDATE_KEY)); + /* Enable pll lock tests */ + CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); + state->m_currentPowerMode = DRX_POWER_UP; + } while (0); + return status; +} + + +static int init_state(struct drxk_state *state) +{ + u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulVSBIfAgcOutputLevel = 0; + u32 ulVSBIfAgcMinLevel = 0; + u32 ulVSBIfAgcMaxLevel = 0x7FFF; + u32 ulVSBIfAgcSpeed = 3; + + u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulVSBRfAgcOutputLevel = 0; + u32 ulVSBRfAgcMinLevel = 0; + u32 ulVSBRfAgcMaxLevel = 0x7FFF; + u32 ulVSBRfAgcSpeed = 3; + u32 ulVSBRfAgcTop = 9500; + u32 ulVSBRfAgcCutOffCurrent = 4000; + + u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulATVIfAgcOutputLevel = 0; + u32 ulATVIfAgcMinLevel = 0; + u32 ulATVIfAgcMaxLevel = 0; + u32 ulATVIfAgcSpeed = 3; + + u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; + u32 ulATVRfAgcOutputLevel = 0; + u32 ulATVRfAgcMinLevel = 0; + u32 ulATVRfAgcMaxLevel = 0; + u32 ulATVRfAgcTop = 9500; + u32 ulATVRfAgcCutOffCurrent = 4000; + u32 ulATVRfAgcSpeed = 3; + + u32 ulQual83 = DEFAULT_MER_83; + u32 ulQual93 = DEFAULT_MER_93; + + u32 ulDVBTStaticTSClock = 1; + u32 ulDVBCStaticTSClock = 1; + + u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; + u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; + + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + u32 ulGPIOCfg = 0x0113; + u32 ulGPIO = 0; + u32 ulSerialMode = 1; + u32 ulInvertTSClock = 0; + u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; + u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; + u32 ulDVBTBitrate = 50000000; + u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; + + u32 ulInsertRSByte = 0; + + u32 ulRfMirror = 1; + u32 ulPowerDown = 0; + + u32 ulAntennaDVBT = 1; + u32 ulAntennaDVBC = 0; + u32 ulAntennaSwitchDVBTDVBC = 0; + + state->m_hasLNA = false; + state->m_hasDVBT= false; + state->m_hasDVBC= false; + state->m_hasATV= false; + state->m_hasOOB = false; + state->m_hasAudio = false; + + state->m_ChunkSize = 124; + + state->m_oscClockFreq = 0; + state->m_smartAntInverted = false; + state->m_bPDownOpenBridge = false; + + /* real system clock frequency in kHz */ + state->m_sysClockFreq = 151875; + /* Timing div, 250ns/Psys */ + /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ + state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * + HI_I2C_DELAY) / 1000; + /* Clipping */ + if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) + state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + state->m_HICfgWakeUpKey = (state->demod_address << 1); + /* port/bridge/power down ctrl */ + state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; + + state->m_bPowerDown = (ulPowerDown != 0); + + state->m_DRXK_A1_PATCH_CODE = false; + state->m_DRXK_A1_ROM_CODE = false; + state->m_DRXK_A2_ROM_CODE = false; + state->m_DRXK_A3_ROM_CODE = false; + state->m_DRXK_A2_PATCH_CODE = false; + state->m_DRXK_A3_PATCH_CODE = false; + + /* Init AGC and PGA parameters */ + /* VSB IF */ + state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); + state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); + state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); + state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); + state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); + state->m_vsbPgaCfg = 140; + + /* VSB RF */ + state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); + state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); + state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); + state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); + state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); + state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); + state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); + state->m_vsbPreSawCfg.reference = 0x07; + state->m_vsbPreSawCfg.usePreSaw = true; + + state->m_Quality83percent = DEFAULT_MER_83; + state->m_Quality93percent = DEFAULT_MER_93; + if (ulQual93 <= 500 && ulQual83 < ulQual93) { + state->m_Quality83percent = ulQual83; + state->m_Quality93percent = ulQual93; + } + + /* ATV IF */ + state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); + state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); + state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); + state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); + state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); + + /* ATV RF */ + state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); + state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); + state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); + state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); + state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); + state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); + state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); + state->m_atvPreSawCfg.reference = 0x04; + state->m_atvPreSawCfg.usePreSaw = true; + + + /* DVBT RF */ + state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; + state->m_dvbtRfAgcCfg.outputLevel = 0; + state->m_dvbtRfAgcCfg.minOutputLevel = 0; + state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; + state->m_dvbtRfAgcCfg.top = 0x2100; + state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; + state->m_dvbtRfAgcCfg.speed = 1; + + + /* DVBT IF */ + state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; + state->m_dvbtIfAgcCfg.outputLevel = 0; + state->m_dvbtIfAgcCfg.minOutputLevel = 0; + state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; + state->m_dvbtIfAgcCfg.top = 13424; + state->m_dvbtIfAgcCfg.cutOffCurrent = 0; + state->m_dvbtIfAgcCfg.speed = 3; + state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; + state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; + // state->m_dvbtPgaCfg = 140; + + state->m_dvbtPreSawCfg.reference = 4; + state->m_dvbtPreSawCfg.usePreSaw = false; + + /* QAM RF */ + state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; + state->m_qamRfAgcCfg.outputLevel = 0; + state->m_qamRfAgcCfg.minOutputLevel = 6023; + state->m_qamRfAgcCfg.maxOutputLevel = 27000; + state->m_qamRfAgcCfg.top = 0x2380; + state->m_qamRfAgcCfg.cutOffCurrent = 4000; + state->m_qamRfAgcCfg.speed = 3; + + /* QAM IF */ + state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; + state->m_qamIfAgcCfg.outputLevel = 0; + state->m_qamIfAgcCfg.minOutputLevel = 0; + state->m_qamIfAgcCfg.maxOutputLevel = 9000; + state->m_qamIfAgcCfg.top = 0x0511; + state->m_qamIfAgcCfg.cutOffCurrent = 0; + state->m_qamIfAgcCfg.speed = 3; + state->m_qamIfAgcCfg.IngainTgtMax = 5119; + state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; + + state->m_qamPgaCfg = 140; + state->m_qamPreSawCfg.reference = 4; + state->m_qamPreSawCfg.usePreSaw = false; + + state->m_OperationMode = OM_NONE; + state->m_DrxkState = DRXK_UNINITIALIZED; + + /* MPEG output configuration */ + state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ + state->m_insertRSByte = false; /* If TRUE; insert RS byte */ + state->m_enableParallel = true; /* If TRUE; + parallel out otherwise serial */ + state->m_invertDATA = false; /* If TRUE; invert DATA signals */ + state->m_invertERR = false; /* If TRUE; invert ERR signal */ + state->m_invertSTR = false; /* If TRUE; invert STR signals */ + state->m_invertVAL = false; /* If TRUE; invert VAL signals */ + state->m_invertCLK = + (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ + state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); + state->m_DVBCStaticCLK = + (ulDVBCStaticTSClock != 0); + /* If TRUE; static MPEG clockrate will be used; + otherwise clockrate will adapt to the bitrate of the TS */ + + state->m_DVBTBitrate = ulDVBTBitrate; + state->m_DVBCBitrate = ulDVBCBitrate; + + state->m_TSDataStrength = (ulTSDataStrength & 0x07); + state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); + + /* Maximum bitrate in b/s in case static clockrate is selected */ + state->m_mpegTsStaticBitrate = 19392658; + state->m_disableTEIhandling = false; + + if (ulInsertRSByte) + state->m_insertRSByte = true; + + state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; + if (ulMpegLockTimeOut < 10000) + state->m_MpegLockTimeOut = ulMpegLockTimeOut; + state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; + if (ulDemodLockTimeOut < 10000) + state->m_DemodLockTimeOut = ulDemodLockTimeOut; + + // QAM defaults + state->m_Constellation = DRX_CONSTELLATION_AUTO; + state->m_qamInterleaveMode = DRXK_QAM_I12_J17; + state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/ + state->m_fecRsPrescale = 1; + + state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; + state->m_agcFastClipCtrlDelay = 0; + + state->m_GPIOCfg = (ulGPIOCfg); + state->m_GPIO = (ulGPIO == 0 ? 0 : 1); + + state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1); + state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1); + state->m_AntennaSwitchDVBTDVBC = + (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1); + + state->m_bPowerDown = false; + state->m_currentPowerMode = DRX_POWER_DOWN; + + state->m_enableParallel = (ulSerialMode == 0); + + state->m_rfmirror = (ulRfMirror == 0); + state->m_IfAgcPol = false; + return 0; +} + +static int DRXX_Open(struct drxk_state *state) +{ + int status = 0; + u32 jtag = 0; + u16 bid = 0; + u16 key = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + /* Check device id */ + CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, + SIO_TOP_COMM_KEY_KEY)); + CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); + CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); + } while(0); + return status; +} + +static int GetDeviceCapabilities(struct drxk_state *state) +{ + u16 sioPdrOhwCfg = 0; + u32 sioTopJtagidLo = 0; + int status; + + do { + /* driver 0.9.0 */ + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); + CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + + switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { + case 0: + /* ignore (bypass ?) */ + break; + case 1: + /* 27 MHz */ + state->m_oscClockFreq = 27000; + break; + case 2: + /* 20.25 MHz */ + state->m_oscClockFreq = 20250; + break; + case 3: + /* 4 MHz */ + state->m_oscClockFreq = 20250; + break; + default: + return -1; + } + /* + Determine device capabilities + Based on pinning v14 + */ + CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, + &sioTopJtagidLo, 0)); + /* driver 0.9.0 */ + switch((sioTopJtagidLo >> 29) & 0xF) { + case 0: + state->m_deviceSpin = DRXK_SPIN_A1; + break; + case 2: + state->m_deviceSpin = DRXK_SPIN_A2; + break; + case 3: + state->m_deviceSpin = DRXK_SPIN_A3; + break; + default: + state->m_deviceSpin = DRXK_SPIN_UNKNOWN; + status = -1; + break; + } + switch ((sioTopJtagidLo>>12)&0xFF) { + case 0x13: + /* typeId = DRX3913K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = false; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = false; + state->m_hasGPIO1 = false; + state->m_hasIRQN = false; + break; + case 0x15: + /* typeId = DRX3915K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x16: + /* typeId = DRX3916K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x18: + /* typeId = DRX3918K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x21: + /* typeId = DRX3921K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x23: + /* typeId = DRX3923K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x25: + /* typeId = DRX3925K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x26: + /* typeId = DRX3926K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + default: + printk("DeviceID not supported = %02x\n", + ((sioTopJtagidLo>>12)&0xFF)); + status = -1; + break; + } + } while(0); + return status; +} + +static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) +{ + int status; + bool powerdown_cmd; + + //printk("%s\n", __FUNCTION__); + + /* Write command */ + status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); + if (status < 0) + return status; + if (cmd == SIO_HI_RA_RAM_CMD_RESET) + msleep(1); + + powerdown_cmd = + (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && + ((state->m_HICfgCtrl) & + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); + if (powerdown_cmd == false) { + /* Wait until command rdy */ + u32 retryCount = 0; + u16 waitCmd; + + do { + msleep(1); + retryCount += 1; + status = Read16(state, SIO_HI_RA_RAM_CMD__A, + &waitCmd, 0); + } while ((status < 0) && + (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0)); + + if (status == 0) + status = Read16(state, SIO_HI_RA_RAM_RES__A, + pResult, 0); + } + return status; +} + +static int HI_CfgCommand(struct drxk_state *state) +{ + int status; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A, + state->m_HICfgTimeout)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A, + state->m_HICfgCtrl)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A, + state->m_HICfgWakeUpKey)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A, + state->m_HICfgBridgeDelay)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A, + state->m_HICfgTimingDiv)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A, + SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); + CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); + + state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + } while(0); + mutex_unlock(&state->mutex); + return status; +} + +static int InitHI(struct drxk_state *state) +{ + state->m_HICfgWakeUpKey = (state->demod_address<<1); + state->m_HICfgTimeout = 0x96FF; + /* port/bridge/power down ctrl */ + state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; + return HI_CfgCommand(state); +} + +static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) +{ + int status = -1; + u16 sioPdrMclkCfg = 0; + u16 sioPdrMdxCfg = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + /* MPEG TS pad configuration */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); + + if (mpegEnable == false) { + /* Set MPEG TS pads to inputmode */ + CHK_ERROR(Write16_0(state, + SIO_PDR_MSTRT_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MERR_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MCLK_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MVAL_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000)); + } else { + /* Enable MPEG output */ + sioPdrMdxCfg = + ((state->m_TSDataStrength << + SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); + sioPdrMclkCfg = ((state->m_TSClockkStrength << + SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); + + CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, + 0x0000)); // Disable + CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, + 0x0000)); // Disable + if (state->m_enableParallel == true) { + /* paralel -> enable MD1 to MD7 */ + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, + sioPdrMdxCfg)); + } else { + sioPdrMdxCfg = ((state->m_TSDataStrength << + SIO_PDR_MD0_CFG_DRIVE__B) | + 0x0003); + /* serial -> disable MD1 to MD7 */ + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, + 0x0000)); + } + CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, + sioPdrMclkCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, + sioPdrMdxCfg)); + } + /* Enable MB output over MPEG pads and ctl input */ + CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); + /* Write nomagic word to enable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + } while(0); + return status; +} + +static int MPEGTSDisable(struct drxk_state *state) +{ + return MPEGTSConfigurePins(state, false); +} + +static int BLChainCmd(struct drxk_state *state, + u16 romOffset, u16 nrOfElements, u32 timeOut) +{ + u16 blStatus = 0; + int status; + unsigned long end; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, + SIO_BL_MODE_CHAIN)); + CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, + romOffset)); + CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, + nrOfElements)); + CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, + SIO_BL_ENABLE_ON)); + end=jiffies+msecs_to_jiffies(timeOut); + + do { + msleep(1); + CHK_ERROR(Read16(state, SIO_BL_STATUS__A, + &blStatus, 0)); + } while ((blStatus == 0x1) && + ((time_is_after_jiffies(end)))); + if (blStatus == 0x1) { + printk("SIO not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + } while(0); + mutex_unlock(&state->mutex); + return status; +} + + +static int DownloadMicrocode(struct drxk_state *state, + const u8 pMCImage[], + u32 Length) +{ + const u8 *pSrc = pMCImage; + u16 Flags; + u16 Drain; + u32 Address; + u16 nBlocks; + u16 BlockSize; + u16 BlockCRC; + u32 offset = 0; + u32 i; + int status; + + /* down the drain (we don care about MAGIC_WORD) */ + Drain = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + nBlocks = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + for (i = 0; i < nBlocks; i += 1) { + Address = (pSrc[0] << 24) | (pSrc[1] << 16) | + (pSrc[2] << 8) | pSrc[3]; + pSrc += sizeof(u32); offset += sizeof(u32); + + BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); + pSrc += sizeof(u16); offset += sizeof(u16); + + Flags = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + BlockCRC = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + status = WriteBlock(state, Address, BlockSize, pSrc, 0); + if (status<0) + break; + pSrc += BlockSize; + offset += BlockSize; + } + return status; +} + +static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) +{ + int status; + u16 data = 0; + u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; + u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; + unsigned long end; + + if (enable == false) { + desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; + desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; + } + + status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); + + if (data == desiredStatus) { + /* tokenring already has correct status */ + return status; + } + /* Disable/enable dvbt tokenring bridge */ + status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); + + end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); + do + CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); + while ((data != desiredStatus) && + ((time_is_after_jiffies(end)))); + if (data != desiredStatus) { + printk("SIO not ready\n"); + return -1; + } + return status; +} + +static int MPEGTSStop(struct drxk_state *state) +{ + int status = 0; + u16 fecOcSncMode = 0; + u16 fecOcIprMode = 0; + + do { + /* Gracefull shutdown (byte boundaries) */ + CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); + fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; + CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); + + /* Suppress MCLK during absence of data */ + CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); + fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; + CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode)); + } while (0); + return status; +} + +static int scu_command(struct drxk_state *state, + u16 cmd, u8 parameterLen, + u16 * parameter, u8 resultLen, u16 * result) +{ +#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 +#error DRXK register mapping no longer compatible with this routine! +#endif + u16 curCmd = 0; + int status; + unsigned long end; + + if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || + ((resultLen > 0) && (result == NULL))) + return -1; + + mutex_lock(&state->mutex); + do { + /* assume that the command register is ready + since it is checked afterwards */ + u8 buffer[34]; + int cnt = 0, ii; + + for (ii=parameterLen-1; ii >= 0; ii -= 1) { + buffer[cnt++] = (parameter[ii] & 0xFF); + buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); + } + buffer[cnt++] = (cmd & 0xFF); + buffer[cnt++] = ((cmd >> 8) & 0xFF); + + WriteBlock(state, SCU_RAM_PARAM_0__A - + (parameterLen-1), cnt, buffer, 0x00); + /* Wait until SCU has processed command */ + end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME); + do { + msleep(1); + CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd)); + } while (! (curCmd == DRX_SCU_READY) && + (time_is_after_jiffies(end))); + if (curCmd != DRX_SCU_READY) { + printk("SCU not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + /* read results */ + if ((resultLen > 0) && (result != NULL)) { + s16 err; + int ii; + + for(ii=resultLen-1; ii >= 0; ii -= 1) { + CHK_ERROR(Read16_0(state, + SCU_RAM_PARAM_0__A - ii, + &result[ii])); + } + + /* Check if an error was reported by SCU */ + err = (s16)result[0]; + + /* check a few fixed error codes */ + if (err == SCU_RESULT_UNKSTD) { + printk("SCU_RESULT_UNKSTD\n"); + mutex_unlock(&state->mutex); + return -1; + } else if (err == SCU_RESULT_UNKCMD) { + printk("SCU_RESULT_UNKCMD\n"); + mutex_unlock(&state->mutex); + return -1; + } + /* here it is assumed that negative means error, + and positive no error */ + else if (err < 0) { + printk("%s ERROR\n", __FUNCTION__); + mutex_unlock(&state->mutex); + return -1; + } + } + } while(0); + mutex_unlock(&state->mutex); + if (status<0) + { + printk("%s: status = %d\n", __FUNCTION__, status); + } + + return status; +} + +static int SetIqmAf(struct drxk_state *state, bool active) +{ + u16 data = 0; + int status; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active)); + //printk("%s\n", __FUNCTION__); + + do + { + /* Configure IQM */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));; + if (!active) { + data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY + | IQM_AF_STDBY_STDBY_AMP_STANDBY + | IQM_AF_STDBY_STDBY_PD_STANDBY + | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY + | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY + ); + // break; + //default: + // break; + //} + } else /* active */ { + data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) + & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) + & (~IQM_AF_STDBY_STDBY_PD_STANDBY) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) + ); + // break; + //default: + // break; + //} + } + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + }while(0); + return status; +} + +static int CtrlPowerMode(struct drxk_state *state, + pDRXPowerMode_t mode) +{ + int status = 0; + u16 sioCcPwdMode = 0; + + //printk("%s\n", __FUNCTION__); + /* Check arguments */ + if (mode == NULL) + return -1; + + switch (*mode) { + case DRX_POWER_UP: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXK_POWER_DOWN_OFDM: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; + break; + case DRXK_POWER_DOWN_CORE: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXK_POWER_DOWN_PLL: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return -1; + break; + } + + /* If already in requested power mode, do nothing */ + if (state->m_currentPowerMode == *mode) + return 0; + + /* For next steps make sure to start from DRX_POWER_UP mode */ + if (state->m_currentPowerMode != DRX_POWER_UP) + { + do { + CHK_ERROR(PowerUpDevice(state)); + CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); + } while(0); + } + + if (*mode == DRX_POWER_UP) { + /* Restore analog & pin configuartion */ + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected + to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* Stop and power down previous standard */ + do { + switch (state->m_OperationMode) { + case OM_DVBT: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownDVBT(state, false)); + break; + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownQAM(state)); + break; + default: + break; + } + CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, + sioCcPwdMode)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, + SIO_CC_UPDATE_KEY)); + + if (*mode != DRXK_POWER_DOWN_OFDM) { + state->m_HICfgCtrl |= + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(HI_CfgCommand(state)); + } + } while(0); + } + state->m_currentPowerMode = *mode; + return (status); +} + +static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) +{ + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + u16 cmdResult = 0; + u16 data = 0; + int status; + + do { + CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); + if (data == SCU_COMM_EXEC_ACTIVE) { + /* Send OFDM stop command */ + CHK_ERROR(scu_command(state, + SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP, + 0, NULL, 1, &cmdResult)); + /* Send OFDM reset command */ + CHK_ERROR(scu_command(state, + SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET, + 0, NULL, 1, &cmdResult)); + } + + /* Reset datapath for OFDM, processors first */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, + OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, + OFDM_LC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, + IQM_COMM_EXEC_B_STOP)); + + /* powerdown AFE */ + CHK_ERROR(SetIqmAf(state,false)); + + /* powerdown to OFDM mode */ + if (setPowerMode) { + CHK_ERROR(CtrlPowerMode(state,&powerMode)); + } + } while(0); + return status; +} + +static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode) +{ + int status = 0; + + /* + Stop and power down previous standard + TODO investigate total power down instead of partial + power down depending on "previous" standard. + */ + do { + /* disable HW lock indicator */ + CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + if (state->m_OperationMode != oMode) { + switch (state->m_OperationMode) { + // OM_NONE was added for start up + case OM_NONE: + break; + case OM_DVBT: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownDVBT(state,true)); + state->m_OperationMode = OM_NONE; + break; + case OM_QAM_ITU_B: + status = -1; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownQAM(state)); + state->m_OperationMode = OM_NONE; + break; + default: + status = -1; + } + CHK_ERROR(status); + + /* + Power up new standard + */ + switch (oMode) + { + case OM_DVBT: + state->m_OperationMode = oMode; + CHK_ERROR(SetDVBTStandard(state, oMode)); + break; + case OM_QAM_ITU_B: + status = -1; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + state->m_OperationMode = oMode; + CHK_ERROR(SetQAMStandard(state,oMode)); + break; + default: + status = -1; + } + } + CHK_ERROR(status); + } while(0); + return 0; +} + +static int Start(struct drxk_state *state, s32 offsetFreq, + s32 IntermediateFrequency) +{ + int status; + + do { + u16 IFreqkHz; + s32 OffsetkHz = offsetFreq / 1000; + + if (state->m_DrxkState != DRXK_STOPPED && + state->m_DrxkState != DRXK_DTV_STARTED) { + status = -1; + break; + } + state->m_bMirrorFreqSpect = +#ifndef USE_API3 + (state->props.inversion == INVERSION_ON); +#else + (state->param.inversion == INVERSION_ON); +#endif + if (IntermediateFrequency < 0) { + state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; + IntermediateFrequency = -IntermediateFrequency; + } + + switch(state->m_OperationMode) { + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + IFreqkHz = (IntermediateFrequency / 1000); + CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz)); + state->m_DrxkState = DRXK_DTV_STARTED; + break; + case OM_DVBT: + IFreqkHz = (IntermediateFrequency / 1000); + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz)); + CHK_ERROR(DVBTStart(state)); + state->m_DrxkState = DRXK_DTV_STARTED; + break; + default: + break; + } + } while(0); + return status; +} + +static int ShutDown(struct drxk_state *state) +{ + MPEGTSStop(state); + return 0; +} + +static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time) +{ + int status; + + if (pLockStatus == NULL) + return -1; + + *pLockStatus = NOT_LOCKED; + + /* define the SCU command code */ + switch (state->m_OperationMode) { + case OM_QAM_ITU_A: + case OM_QAM_ITU_B: + case OM_QAM_ITU_C: + status = GetQAMLockStatus(state, pLockStatus); + break; + case OM_DVBT: + status = GetDVBTLockStatus(state, pLockStatus); + break; + default: + break; + } + return status; +} + +static int MPEGTSStart(struct drxk_state *state) +{ + int status = 0; + + u16 fecOcSncMode = 0; + + do { + /* Allow OC to sync again */ + CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); + fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; + CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); + } while (0); + return status; +} + +static int MPEGTSDtoInit(struct drxk_state *state) +{ + int status = -1; + + do { + /* Rate integration settings */ + CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); + CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); + CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); + CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); + CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); + + /* Additional configuration */ + CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); + } while (0); + return status; +} + +static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode) +{ + int status = -1; + + u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ + u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ + u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ + u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcTmdMode = 0; + u16 fecOcTmdIntUpdRate = 0; + u32 maxBitRate = 0; + bool staticCLK = false; + + do { + /* Check insertion of the Reed-Solomon parity bytes */ + CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); + CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, + &fecOcRegIprMode)); + fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); + fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + if (state->m_insertRSByte == true) { + /* enable parity symbol forward */ + fecOcRegMode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + /* TS burst length to 204 */ + fecOcDtoBurstLen = 204 ; + } + + /* Check serial or parrallel output */ + fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + if (state->m_enableParallel == false) { + /* MPEG data output is serial -> set ipr_mode[0] */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + switch (oMode) { + case OM_DVBT: + maxBitRate = state->m_DVBTBitrate; + fecOcTmdMode = 3; + fecOcRcnCtlRate = 0xC00000; + staticCLK = state->m_DVBTStaticCLK; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + fecOcTmdMode = 0x0004; + fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ + maxBitRate = state->m_DVBCBitrate; + staticCLK = state->m_DVBCStaticCLK; + break; + default: + status = -1; + } /* switch (standard) */ + CHK_ERROR(status); + + /* Configure DTO's */ + if (staticCLK ) { + u32 bitRate = 0; + + /* Rational DTO for MCLK source (static MCLK rate), + Dynamic DTO for optimal grouping + (avoid intra-packet gaps), + DTO offset enable to sync TS burst with MSTRT */ + fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | + FEC_OC_DTO_MODE_OFFSET_ENABLE__M); + fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | + FEC_OC_FCT_MODE_VIRT_ENA__M); + + /* Check user defined bitrate */ + bitRate = maxBitRate; + if (bitRate > 75900000UL) + { /* max is 75.9 Mb/s */ + bitRate = 75900000UL; + } + /* Rational DTO period: + dto_period = (Fsys / bitrate) - 2 + + Result should be floored, + to make sure >= requested bitrate + */ + fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) + * 1000) / bitRate); + if (fecOcDtoPeriod <= 2) + fecOcDtoPeriod = 0; + else + fecOcDtoPeriod -= 2; + fecOcTmdIntUpdRate = 8; + } else { + /* (commonAttr->staticCLK == false) => dynamic mode */ + fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; + fecOcFctMode = FEC_OC_FCT_MODE__PRE; + fecOcTmdIntUpdRate = 5; + } + + /* Write appropriate registers with requested configuration */ + CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, + fecOcDtoBurstLen)); + CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, + fecOcDtoPeriod)); + CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, + fecOcDtoMode)); + CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, + fecOcFctMode)); + CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, + fecOcRegMode)); + CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, + fecOcRegIprMode)); + + /* Rate integration settings */ + CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, + fecOcRcnCtlRate ,0)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, + fecOcTmdIntUpdRate)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, + fecOcTmdMode)); + } while (0); + return status; +} + +static int MPEGTSConfigurePolarity(struct drxk_state *state) +{ + int status; + u16 fecOcRegIprInvert = 0; + + /* Data mask for the output data byte */ + u16 InvertDataMask = + FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + + /* Control selective inversion of output bits */ + fecOcRegIprInvert &= (~(InvertDataMask)); + if (state->m_invertDATA == true) + fecOcRegIprInvert |= InvertDataMask; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + if (state->m_invertERR == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + if (state->m_invertSTR == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + if (state->m_invertVAL == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + if (state->m_invertCLK == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; + status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); + return status; +} + +#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 + +static int SetAgcRf(struct drxk_state *state, + struct SCfgAgc *pAgcCfg, bool isDTV) +{ + int status = 0; + struct SCfgAgc *pIfAgcSettings; + + if (pAgcCfg == NULL) + return -1; + + do { + u16 data = 0; + + switch (pAgcCfg->ctrlMode) { + case DRXK_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); + + CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, + &data, 0)); + + /* Enable SCU RF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + + /* Polarity */ + if (state->m_RfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, + &data, 0)); + + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + data |= (~(pAgcCfg->speed << + SCU_RAM_AGC_KI_RED_RAGC_RED__B) + & SCU_RAM_AGC_KI_RED_RAGC_RED__M); + + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_KI_RED__A, data)); + + if (IsDVBT(state)) + pIfAgcSettings = &state->m_dvbtIfAgcCfg; + else if (IsQAM(state)) + pIfAgcSettings = &state->m_qamIfAgcCfg; + else + pIfAgcSettings = &state->m_atvIfAgcCfg; + if (pIfAgcSettings == NULL) + return -1; + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcCfg->top)); + + /* Cut-Off current */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_RF_IACCU_HI_CO__A, + pAgcCfg->cutOffCurrent)); + + /* Max. output level */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, + pAgcCfg->maxOutputLevel)); + + break; + + case DRXK_AGC_CTRL_USER: + /* Enable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); + + /* Disable SCU RF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + if (state->m_RfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, + data)); + + /* SCU c.o.c. to 0, enabling full control range */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, + 0)); + + /* Write value to output pin */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, + pAgcCfg->outputLevel)); + break; + + case DRXK_AGC_CTRL_OFF: + /* Disable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + /* Disable SCU RF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + break; + + default: + return -1; + + } /* switch (agcsettings->ctrlMode) */ + } while(0); + return status; +} + +#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 + +static int SetAgcIf (struct drxk_state *state, + struct SCfgAgc *pAgcCfg, bool isDTV) +{ + u16 data = 0; + int status = 0; + struct SCfgAgc *pRfAgcSettings; + + do { + switch (pAgcCfg->ctrlMode) { + case DRXK_AGC_CTRL_AUTO: + + /* Enable IF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, + &data)); + + /* Enable SCU IF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + + /* Polarity */ + if (state->m_IfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, + &data)); + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + data |= (~(pAgcCfg->speed << + SCU_RAM_AGC_KI_RED_IAGC_RED__B) + & SCU_RAM_AGC_KI_RED_IAGC_RED__M); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A , + data)); + + if (IsQAM(state)) + pRfAgcSettings = &state->m_qamRfAgcCfg; + else + pRfAgcSettings = &state->m_atvRfAgcCfg; + if (pRfAgcSettings == NULL) + return -1; + /* Restore TOP */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pRfAgcSettings->top)); + break; + + case DRXK_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + + /* Disable SCU IF AGC loop */ + data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + + /* Polarity */ + if (state->m_IfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Write value to output pin */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcCfg->outputLevel)); + break; + + case DRXK_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + /* Disable SCU IF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + break; + } /* switch (agcSettingsIf->ctrlMode) */ + + /* always set the top to support + configurations without if-loop */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, + pAgcCfg->top)); + + + } while(0); + return status; +} + +static int ReadIFAgc(struct drxk_state *state, u32 *pValue) +{ + u16 agcDacLvl; + int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); + + *pValue = 0; + + if (status==0) { + u16 Level = 0; + if (agcDacLvl > DRXK_AGC_DAC_OFFSET) + Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; + if (Level < 14000) + *pValue = (14000 - Level) / 4 ; + else + *pValue = 0; + } + return status; +} + +static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + int status = 0; + + do { + /* MER calculation */ + u16 qamSlErrPower = 0; /* accum. error between + raw and sliced symbols */ + u32 qamSlSigPower = 0; /* used for MER, depends of + QAM constellation */ + u32 qamSlMer = 0; /* QAM MER */ + + /* get the register value needed for MER */ + CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower)); + +#ifndef USE_API3 + switch(state->props.modulation) { +#else + switch(state->param.u.qam.modulation) { +#endif + case QAM_16: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case QAM_32: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case QAM_64: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case QAM_128: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; + break; + default: + case QAM_256: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; + break; + } + + if (qamSlErrPower > 0) { + qamSlMer = Log10Times100(qamSlSigPower) - + Log10Times100((u32) qamSlErrPower); + } + *pSignalToNoise = qamSlMer; + } while(0); + return status; +} + +static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + int status = 0; + + u16 regData = 0; + u32 EqRegTdSqrErrI = 0; + u32 EqRegTdSqrErrQ = 0; + u16 EqRegTdSqrErrExp = 0; + u16 EqRegTdTpsPwrOfs = 0; + u16 EqRegTdReqSmbCnt = 0; + u32 tpsCnt = 0; + u32 SqrErrIQ = 0; + u32 a = 0; + u32 b = 0; + u32 c = 0; + u32 iMER = 0; + u16 transmissionParams = 0; + + do { + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, + &EqRegTdTpsPwrOfs)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, + &EqRegTdReqSmbCnt)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, + &EqRegTdSqrErrExp)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, + ®Data)); + /* Extend SQR_ERR_I operational range */ + EqRegTdSqrErrI = (u32) regData; + if ((EqRegTdSqrErrExp > 11) && + (EqRegTdSqrErrI < 0x00000FFFUL)) { + EqRegTdSqrErrI += 0x00010000UL; + } + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A, + ®Data)); + /* Extend SQR_ERR_Q operational range */ + EqRegTdSqrErrQ = (u32)regData; + if ((EqRegTdSqrErrExp > 11) && + (EqRegTdSqrErrQ < 0x00000FFFUL)) + EqRegTdSqrErrQ += 0x00010000UL; + + CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A, + &transmissionParams)); + + /* Check input data for MER */ + + /* MER calculation (in 0.1 dB) without math.h */ + if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) + iMER = 0; + else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { + /* No error at all, this must be the HW reset value + * Apparently no first measurement yet + * Set MER to 0.0 */ + iMER = 0; + } else { + SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << + EqRegTdSqrErrExp; + if ((transmissionParams & + OFDM_SC_RA_RAM_OP_PARAM_MODE__M) + == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) + tpsCnt = 17; + else + tpsCnt = 68; + + /* IMER = 100 * log10 (x) + where x = (EqRegTdTpsPwrOfs^2 * + EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ + + => IMER = a + b -c + where a = 100 * log10 (EqRegTdTpsPwrOfs^2) + b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) + c = 100 * log10 (SqrErrIQ) + */ + + /* log(x) x = 9bits * 9bits->18 bits */ + a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs); + /* log(x) x = 16bits * 7bits->23 bits */ + b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt); + /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ + c = Log10Times100(SqrErrIQ); + + iMER = a + b; + /* No negative MER, clip to zero */ + if (iMER > c) + iMER -= c; + else + iMER = 0; + } + *pSignalToNoise = iMER; + } while(0); + + return status; +} + +static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + *pSignalToNoise = 0; + switch(state->m_OperationMode) { + case OM_DVBT: + return GetDVBTSignalToNoise(state, pSignalToNoise); + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + return GetQAMSignalToNoise(state, pSignalToNoise); + default: + break; + } + return 0; +} + +#if 0 +static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) +{ + /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ + int status = 0; + + static s32 QE_SN[] = + { + 51, // QPSK 1/2 + 69, // QPSK 2/3 + 79, // QPSK 3/4 + 89, // QPSK 5/6 + 97, // QPSK 7/8 + 108, // 16-QAM 1/2 + 131, // 16-QAM 2/3 + 146, // 16-QAM 3/4 + 156, // 16-QAM 5/6 + 160, // 16-QAM 7/8 + 165, // 64-QAM 1/2 + 187, // 64-QAM 2/3 + 202, // 64-QAM 3/4 + 216, // 64-QAM 5/6 + 225, // 64-QAM 7/8 + }; + + *pQuality = 0; + + do { + s32 SignalToNoise = 0; + u16 Constellation = 0; + u16 CodeRate = 0; + u32 SignalToNoiseRel; + u32 BERQuality; + + CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise)); + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A, + &Constellation)); + Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; + + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A, + &CodeRate)); + CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; + + if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || + CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) + break; + SignalToNoiseRel = SignalToNoise - + QE_SN[Constellation * 5 + CodeRate]; + BERQuality = 100; + + if (SignalToNoiseRel < -70) *pQuality = 0; + else if (SignalToNoiseRel < 30) + *pQuality = ((SignalToNoiseRel + 70) * + BERQuality) / 100; + else + *pQuality = BERQuality; + } while(0); + return 0; +}; + +static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) +{ + int status = 0; + *pQuality = 0; + + do { + u32 SignalToNoise = 0; + u32 BERQuality = 100; + u32 SignalToNoiseRel = 0; + + CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); + +#ifndef USE_API3 + switch(state->props.modulation) { +#else + switch(state->param.u.qam.modulation) { +#endif + case QAM_16: + SignalToNoiseRel = SignalToNoise - 200; + break; + case QAM_32: + SignalToNoiseRel = SignalToNoise - 230; + break; /* Not in NorDig */ + case QAM_64: + SignalToNoiseRel = SignalToNoise - 260; + break; + case QAM_128: + SignalToNoiseRel = SignalToNoise - 290; + break; + default: + case QAM_256: + SignalToNoiseRel = SignalToNoise - 320; + break; + } + + if (SignalToNoiseRel < -70) + *pQuality = 0; + else if (SignalToNoiseRel < 30) + *pQuality = ((SignalToNoiseRel + 70) * + BERQuality) / 100; + else + *pQuality = BERQuality; + } while(0); + + return status; +} + +static int GetQuality(struct drxk_state *state, s32 *pQuality) +{ + switch(state->m_OperationMode) { + case OM_DVBT: + return GetDVBTQuality(state, pQuality); + case OM_QAM_ITU_A: + return GetDVBCQuality(state, pQuality); + default: + break; + } + + return 0; +} +#endif + +/* Free data ram in SIO HI */ +#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define SIO_HI_RA_RAM_USR_END__A 0x420060 + +#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE + +#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) +#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) +#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) + +static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) +{ + int status; + + if (state->m_DrxkState == DRXK_UNINITIALIZED) + return -1; + if (state->m_DrxkState == DRXK_POWERED_DOWN) + return -1; + + do { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, + SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); + if (bEnableBridge) { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, + SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); + } else { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, + SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); + } + + CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0)); + } while(0); + return status; +} + +static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg) +{ + int status; + + if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M)) + return -1; + + status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); + return status; +} + +static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, + u16 romOffset, u16 nrOfElements, u32 timeOut) +{ + u16 blStatus = 0; + u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF); + u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF); + int status ; + unsigned long end; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); + CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); + CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); + CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); + CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements)); + CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); + + end=jiffies+msecs_to_jiffies(timeOut); + do { + CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus)); + } while ((blStatus == 0x1) && + time_is_after_jiffies(end)); + if (blStatus == 0x1) { + printk("SIO not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + } while(0); + mutex_unlock(&state->mutex); + return status; + +} + +static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) +{ + u16 data = 0; + int status; + + do { + /* Start measurement */ + CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, + IQM_AF_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1)); + + *count = 0; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data)); + if (data == 127) + *count = *count+1; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data)); + if (data == 127) + *count = *count+1; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data)); + if (data == 127) + *count = *count+1; + } while(0); + return status; +} + +static int ADCSynchronization(struct drxk_state *state) +{ + u16 count = 0; + int status; + + do { + CHK_ERROR(ADCSyncMeasurement(state, &count)); + + if (count==1) { + /* Try sampling on a diffrent edge */ + u16 clkNeg = 0; + + CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg)); + if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { + clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); + clkNeg |= + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; + } else { + clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); + clkNeg |= + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; + } + CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg)); + CHK_ERROR(ADCSyncMeasurement(state, &count)); + } + + if (count < 2) + status = -1; + } while (0); + return status; +} + +static int SetFrequencyShifter(struct drxk_state *state, + u16 intermediateFreqkHz, + s32 tunerFreqOffset, + bool isDTV) +{ + bool selectPosImage = false; + u32 rfFreqResidual = tunerFreqOffset; + u32 fmFrequencyShift = 0; + bool tunerMirror = !state->m_bMirrorFreqSpect; + u32 adcFreq; + bool adcFlip; + int status; + u32 ifFreqActual; + u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3); + u32 frequencyShift; + bool imageToSelect; + + /* + Program frequency shifter + No need to account for mirroring on RF + */ + if (isDTV) { + if ((state->m_OperationMode == OM_QAM_ITU_A) || + (state->m_OperationMode == OM_QAM_ITU_C) || + (state->m_OperationMode == OM_DVBT)) + selectPosImage = true; + else + selectPosImage = false; + } + if (tunerMirror) + /* tuner doesn't mirror */ + ifFreqActual = intermediateFreqkHz + + rfFreqResidual + fmFrequencyShift; + else + /* tuner mirrors */ + ifFreqActual = intermediateFreqkHz - + rfFreqResidual - fmFrequencyShift; + if (ifFreqActual > samplingFrequency / 2) { + /* adc mirrors */ + adcFreq = samplingFrequency - ifFreqActual; + adcFlip = true; + } else { + /* adc doesn't mirror */ + adcFreq = ifFreqActual; + adcFlip = false; + } + + frequencyShift = adcFreq; + imageToSelect = state->m_rfmirror ^ tunerMirror ^ + adcFlip ^ selectPosImage; + state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency); + + if (imageToSelect) + state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequencyShift += tunerFreqOffset; TODO */ + status = Write32(state, IQM_FS_RATE_OFS_LO__A , + state->m_IqmFsRateOfs, 0); + return status; +} + +static int InitAGC(struct drxk_state *state, bool isDTV) +{ + u16 ingainTgt = 0; + u16 ingainTgtMin = 0; + u16 ingainTgtMax = 0; + u16 clpCyclen = 0; + u16 clpSumMin = 0; + u16 clpDirTo = 0; + u16 snsSumMin = 0; + u16 snsSumMax = 0; + u16 clpSumMax = 0; + u16 snsDirTo = 0; + u16 kiInnergainMin = 0; + u16 ifIaccuHiTgt = 0; + u16 ifIaccuHiTgtMin = 0; + u16 ifIaccuHiTgtMax = 0; + u16 data = 0; + u16 fastClpCtrlDelay = 0; + u16 clpCtrlMode = 0; + int status = 0; + + do { + /* Common settings */ + snsSumMax = 1023; + ifIaccuHiTgtMin = 2047; + clpCyclen = 500; + clpSumMax = 1023; + + if (IsQAM(state)) { + /* Standard specific settings */ + clpSumMin = 8; + clpDirTo = (u16) - 9; + clpCtrlMode = 0; + snsSumMin = 8; + snsDirTo = (u16) - 9; + kiInnergainMin = (u16) - 1030; + } else + status = -1; + CHK_ERROR((status)); + if (IsQAM(state)) { + ifIaccuHiTgtMax = 0x2380; + ifIaccuHiTgt = 0x2380; + ingainTgtMin = 0x0511; + ingainTgt = 0x0511; + ingainTgtMax = 5119; + fastClpCtrlDelay = + state->m_qamIfAgcCfg.FastClipCtrlDelay; + } else { + ifIaccuHiTgtMax = 0x1200; + ifIaccuHiTgt = 0x1200; + ingainTgtMin = 13424; + ingainTgt = 13424; + ingainTgtMax = 30000; + fastClpCtrlDelay = + state->m_dvbtIfAgcCfg.FastClipCtrlDelay; + } + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, + fastClpCtrlDelay)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, + clpCtrlMode)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, + ingainTgt)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, + ingainTgtMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, + ingainTgtMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, + ifIaccuHiTgtMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + ifIaccuHiTgtMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, + clpSumMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, + snsSumMax)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, + kiInnergainMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + ifIaccuHiTgt)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, + clpCyclen)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, + 1023)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, + (u16) -1023)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, + 50)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, + 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, + clpSumMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, + snsSumMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, + clpDirTo)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, + snsDirTo)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); + + /* Initialize inner-loop KI gain factors */ + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); + if (IsQAM(state)) { + data = 0x0657; + data &= ~SCU_RAM_AGC_KI_RF__M; + data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); + data &= ~SCU_RAM_AGC_KI_IF__M; + data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); + } + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); + } while(0); + return status; +} + +static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr) +{ + int status; + + do { + if (packetErr == NULL) { + CHK_ERROR(Write16_0(state, + SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, + 0)); + } else { + CHK_ERROR(Read16_0(state, + SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, + packetErr)); + } + } while (0); + return status; +} + +static int DVBTScCommand(struct drxk_state *state, + u16 cmd, u16 subcmd, + u16 param0, u16 param1, u16 param2, + u16 param3, u16 param4) +{ + u16 curCmd = 0; + u16 errCode = 0; + u16 retryCnt = 0; + u16 scExec = 0; + int status; + + status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); + if (scExec != 1) { + /* SC is not running */ + return -1; + } + + /* Wait until sc is ready to receive command */ + retryCnt =0; + do { + msleep(1); + status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); + retryCnt++; + } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); + if (retryCnt >= DRXK_MAX_RETRIES) + return -1; + /* Write sub-command */ + switch (cmd) { + /* All commands using sub-cmd */ + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); + break; + default: + /* Do nothing */ + break; + } /* switch (cmd->cmd) */ + + /* Write needed parameters and the command */ + switch (cmd) { + /* All commands using 5 parameters */ + /* All commands using 4 parameters */ + /* All commands using 3 parameters */ + /* All commands using 2 parameters */ + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); + /* All commands using 1 parameters */ + case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: + case OFDM_SC_RA_RAM_CMD_USER_IO: + status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); + /* All commands using 0 parameters */ + case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: + case OFDM_SC_RA_RAM_CMD_NULL: + /* Write command */ + status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); + break; + default: + /* Unknown command */ + return -EINVAL; + } /* switch (cmd->cmd) */ + + /* Wait until sc is ready processing command */ + retryCnt = 0; + do{ + msleep(1); + status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); + retryCnt++; + } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); + if (retryCnt >= DRXK_MAX_RETRIES) + return -1; + + /* Check for illegal cmd */ + status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); + if (errCode == 0xFFFF) + { + /* illegal command */ + return -EINVAL; + } + + /* Retreive results parameters from SC */ + switch (cmd) { + /* All commands yielding 5 results */ + /* All commands yielding 4 results */ + /* All commands yielding 3 results */ + /* All commands yielding 2 results */ + /* All commands yielding 1 result */ + case OFDM_SC_RA_RAM_CMD_USER_IO: + case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: + status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); + /* All commands yielding 0 results */ + case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: + case OFDM_SC_RA_RAM_CMD_SET_TIMER: + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + case OFDM_SC_RA_RAM_CMD_NULL: + break; + default: + /* Unknown command */ + return -EINVAL; + break; + } /* switch (cmd->cmd) */ + return status; +} + +static int PowerUpDVBT (struct drxk_state *state) +{ + DRXPowerMode_t powerMode = DRX_POWER_UP; + int status; + + do { + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + } while (0); + return status; +} + +static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled) +{ + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + if (*enabled == true) + { + status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); + } + else + { + status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); + } + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + #define DEFAULT_FR_THRES_8K 4000 +static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled) +{ + + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + if (*enabled == true) + { + /* write mask to 1 */ + status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, + DEFAULT_FR_THRES_8K); + } + else + { + /* write mask to 0 */ + status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); + } + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int DVBTCtrlSetEchoThreshold (struct drxk_state *state, + struct DRXKCfgDvbtEchoThres_t* echoThres) +{ + u16 data = 0; + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + do { + CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); + + switch (echoThres->fftMode) + { + case DRX_FFTMODE_2K: + data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M; + data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) & + (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); + break; + case DRX_FFTMODE_8K: + data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M; + data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & + (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); + break; + default: + return -1; + break; + } + + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); + } while (0); + + if (status<0) + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, + enum DRXKCfgDvbtSqiSpeed* speed) +{ + int status; + + switch (*speed) { + case DRXK_DVBT_SQI_SPEED_FAST: + case DRXK_DVBT_SQI_SPEED_MEDIUM: + case DRXK_DVBT_SQI_SPEED_SLOW: + break; + default: + return -EINVAL; + } + status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, + (u16) *speed); + return status; +} + +/*============================================================================*/ + +/** +* \brief Activate DVBT specific presets +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +* Called in DVBTSetStandard +* +*/ +static int DVBTActivatePresets (struct drxk_state *state) +{ + int status; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K}; + struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K}; + + do { + bool setincenable = false; + bool setfrenable = true; + CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable)); + CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable)); + CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); + CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, + state->m_dvbtIfAgcCfg.IngainTgtMax)); + } while (0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} +/*============================================================================*/ + +/** +* \brief Initialize channelswitch-independent settings for DVBT. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +* For ROM code channel filter taps are loaded from the bootloader. For microcode +* the DVB-T taps from the drxk_filters.h are used. +*/ +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode) +{ + u16 cmdResult = 0; + u16 data = 0; + int status; + + //printk("%s\n", __FUNCTION__); + + PowerUpDVBT(state); + + do { + /* added antenna switch */ + SwitchAntennaToDVBT(state); + /* send OFDM reset command */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); + + /* send OFDM setenv command */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult)); + + /* reset datapath for OFDM, processors first */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP )); + + /* IQM setup */ + /* synchronize on ofdstate->m_festart */ + CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); + /* window size for clipping ADC detection */ + CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); + /* window size for for sense pre-SAW detection */ + CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); + /* sense threshold for sense pre-SAW detection */ + CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); + CHK_ERROR(SetIqmAf(state,true)); + + CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); + + /* Impulse noise cruncher setup */ + CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ + CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ + CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ + + CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); + CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ + CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ + CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); + CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); + + /* virtual clipping threshold for clipping ADC detection */ + CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); + CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ + + CHK_ERROR(BLChainCmd(state, + DRXK_BL_ROM_OFFSET_TAPS_DVBT, + DRXK_BLCC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + + CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ + CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); + /* enable power measurement interrupt */ + CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); + + /* IQM will not be reset from here, sync ADC and update/init AGC */ + CHK_ERROR(ADCSynchronization(state)); + CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ; + CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true)); + + /* Set Noise Estimation notch width and enable DC fix */ + CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data)); + data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data)); + + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + + if (!state->m_DRXK_A3_ROM_CODE) + { + /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, + state->m_dvbtIfAgcCfg.FastClipCtrlDelay)); + } + + /* OFDM_SC setup */ +#ifdef COMPILE_FOR_NONRT + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); +#endif + + /* FEC setup */ + CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ + + +#ifdef COMPILE_FOR_NONRT + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400)); +#else + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000)); +#endif + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001)); + + /* Setup MPEG bus */ + CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT)); + /* Set DVBT Presets */ + CHK_ERROR (DVBTActivatePresets (state)); + + } while (0); + + if (status<0) + { + printk("%s status - %08x\n",__FUNCTION__,status); + } + + return status; +} + +/*============================================================================*/ +/** +* \brief Start dvbt demodulating for channel. +* \param demod instance of demodulator. +* \return DRXStatus_t. +*/ +static int DVBTStart(struct drxk_state *state) +{ + u16 param1; + + int status; +// DRXKOfdmScCmd_t scCmd; + + //printk("%s\n",__FUNCTION__); + /* Start correct processes to get in lock */ + /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ + do { + param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; + CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0)); + /* Start FEC OC */ + CHK_ERROR(MPEGTSStart(state)); + CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); + } while (0); + return (status); +} + + +/*============================================================================*/ + +/** +* \brief Set up dvbt demodulator for channel. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* // original DVBTSetChannel() +*/ +static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +{ + u16 cmdResult = 0; + u16 transmissionParams = 0; + u16 operationMode = 0; + u32 iqmRcRateOfs = 0; + u32 bandwidth = 0; + u16 param1; + int status; + + //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset); + do { + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP, + 0,NULL,1,&cmdResult)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* Stop processors */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); + + /* Mandatory fix, always stop CP, required to set spl offset back to + hardware default (is set to 0 by ucode during pilot detection */ + CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP)); + + /*== Write channel settings to device =====================================*/ + + /* mode */ +#ifndef USE_API3 + switch(state->props.transmission_mode) { +#else + switch(state->param.u.ofdm.transmission_mode) { +#endif + case TRANSMISSION_MODE_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; + /* fall through , try first guess DRX_FFTMODE_8K */ + case TRANSMISSION_MODE_8K: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; + break; + case TRANSMISSION_MODE_2K: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; + break; + } + + /* guard */ +#ifndef USE_API3 + switch(state->props.guard_interval) { +#else + switch(state->param.u.ofdm.guard_interval) { +#endif + default: + case GUARD_INTERVAL_AUTO: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; + /* fall through , try first guess DRX_GUARD_1DIV4 */ + case GUARD_INTERVAL_1_4: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; + break; + case GUARD_INTERVAL_1_32: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; + break; + case GUARD_INTERVAL_1_16: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; + break; + case GUARD_INTERVAL_1_8: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; + break; + } + + /* hierarchy */ +#ifndef USE_API3 + switch(state->props.hierarchy) { +#else + switch(state->param.u.ofdm.hierarchy_information) { +#endif + case HIERARCHY_AUTO: + case HIERARCHY_NONE: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; + /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ + // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; + //break; + case HIERARCHY_1: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; + break; + case HIERARCHY_2: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; + break; + case HIERARCHY_4: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; + break; + } + + + /* constellation */ +#ifndef USE_API3 + switch(state->props.modulation) { +#else + switch(state->param.u.ofdm.constellation) { +#endif + case QAM_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; + /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ + case QAM_64: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; + break; + case QPSK: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; + break; + case QAM_16: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; + break; + } +#if 0 + // No hierachical channels support in BDA + /* Priority (only for hierarchical channels) */ + switch (channel->priority) { + case DRX_PRIORITY_LOW : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; + WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO); + break; + case DRX_PRIORITY_HIGH : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; + WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); + break; + case DRX_PRIORITY_UNKNOWN : /* fall through */ + default: + return (DRX_STS_INVALID_ARG); + break; + } +#else + // Set Priorty high + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; + CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); +#endif + + /* coderate */ +#ifndef USE_API3 + switch(state->props.code_rate_HP) { +#else + switch(state->param.u.ofdm.code_rate_HP) { +#endif + case FEC_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; + /* fall through , try first guess DRX_CODERATE_2DIV3 */ + case FEC_2_3 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; + break; + case FEC_1_2 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; + break; + case FEC_3_4 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; + break; + case FEC_5_6 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; + break; + case FEC_7_8 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; + break; + } + + /* SAW filter selection: normaly not necesarry, but if wanted + the application can select a SAW filter via the driver by using UIOs */ + /* First determine real bandwidth (Hz) */ + /* Also set delay for impulse noise cruncher */ + /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed + by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC + functions */ +#ifndef USE_API3 + switch(state->props.bandwidth_hz) { +#else + switch(state->param.u.ofdm.bandwidth) { +#endif +#ifndef USE_API3 + case 0: + case 8000000: +#else + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: +#endif + bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052)); + /* cochannel protection for PAL 8 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; +#ifndef USE_API3 + case 7000000: +#else + case BANDWIDTH_7_MHZ: +#endif + bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491)); + /* cochannel protection for PAL 7 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; +#ifndef USE_API3 + case 6000000: +#else + case BANDWIDTH_6_MHZ: +#endif + bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073)); + /* cochannel protection for NTSC 6 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; + } + + if (iqmRcRateOfs == 0) + { + /* Now compute IQM_RC_RATE_OFS + (((SysFreq/BandWidth)/2)/2) -1) * 2^23) + => + ((SysFreq / BandWidth) * (2^21)) - (2^23) + */ + /* (SysFreq / BandWidth) * (2^28) */ + /* assert (MAX(sysClk)/MIN(bandwidth) < 16) + => assert(MAX(sysClk) < 16*MIN(bandwidth)) + => assert(109714272 > 48000000) = true so Frac 28 can be used */ + iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth); + /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ + if ((iqmRcRateOfs & 0x7fL) >= 0x40) + { + iqmRcRateOfs += 0x80L; + } + iqmRcRateOfs = iqmRcRateOfs >> 7 ; + /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ + iqmRcRateOfs = iqmRcRateOfs - (1<<23); + } + + iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<m_DRXK_A3_ROM_CODE) + CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed)); + + } while(0); + if (status<0) { + //printk("%s status - %08x\n",__FUNCTION__,status); + } + + return status; +} + + +/*============================================================================*/ + +/** +* \brief Retreive lock status . +* \param demod Pointer to demodulator instance. +* \param lockStat Pointer to lock status structure. +* \return DRXStatus_t. +* +*/ +static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) +{ + int status; + const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | + OFDM_SC_RA_RAM_LOCK_FEC__M ); + const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); + const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ; + + u16 ScRaRamLock = 0; + u16 ScCommExec = 0; + + /* driver 0.9.0 */ + /* Check if SC is running */ + status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); + if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) + { + /* SC not active; return DRX_NOT_LOCKED */ + *pLockStatus = NOT_LOCKED; + return status; + } + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock)); + + if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { + *pLockStatus = MPEG_LOCK; + } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) { + *pLockStatus = FEC_LOCK; + } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) { + *pLockStatus = DEMOD_LOCK; + } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) { + *pLockStatus = NEVER_LOCK; + } else { + *pLockStatus = NOT_LOCKED; + } + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int PowerUpQAM (struct drxk_state *state) +{ + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + + +/// Power Down QAM +static int PowerDownQAM(struct drxk_state *state) +{ + u16 data = 0; + u16 cmdResult; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); + if (data == SCU_COMM_EXEC_ACTIVE) + { + /* + STOP demodulator + QAM and HW blocks + */ + /* stop all comstate->m_exec */ + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult)); + } + /* powerdown AFE */ + CHK_ERROR(SetIqmAf(state, false)); + } + while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} +/*============================================================================*/ + +/** +* \brief Setup of the QAM Measurement intervals for signal quality +* \param demod instance of demod. +* \param constellation current constellation. +* \return DRXStatus_t. +* +* NOTE: +* Take into account that for certain settings the errorcounters can overflow. +* The implementation does not check this. +* +*/ +static int SetQAMMeasurement(struct drxk_state *state, + enum EDrxkConstellation constellation, + u32 symbolRate) +{ + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode)); + + u32 fecBitsDesired = 0; /* BER accounting period */ + u32 fecRsPeriodTotal = 0; /* Total period */ + u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ + int status = 0; + + fecRsPrescale = 1; + + do { + + /* fecBitsDesired = symbolRate [kHz] * + FrameLenght [ms] * + (constellation + 1) * + SyncLoss (== 1) * + ViterbiLoss (==1) + */ + switch (constellation) + { + case DRX_CONSTELLATION_QAM16: + fecBitsDesired = 4 * symbolRate; + break; + case DRX_CONSTELLATION_QAM32: + fecBitsDesired = 5 * symbolRate; + break; + case DRX_CONSTELLATION_QAM64: + fecBitsDesired = 6 * symbolRate; + break; + case DRX_CONSTELLATION_QAM128: + fecBitsDesired = 7 * symbolRate; + break; + case DRX_CONSTELLATION_QAM256: + fecBitsDesired = 8 * symbolRate; + break; + default: + status = -EINVAL; + } + CHK_ERROR(status); + + fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ + fecBitsDesired *= 500; /* meas. period [ms] */ + + /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ + /* fecRsPeriodTotal = fecBitsDesired / 1632 */ + fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/ + + /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ + fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); + if (fecRsPrescale == 0) { + /* Divide by zero (though impossible) */ + status = -1; + } + CHK_ERROR(status); + fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) / + fecRsPrescale; + + /* write corresponding registers */ + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod)); + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); + + } while (0); + + if (status<0) { + printk("%s: status - %08x\n",__FUNCTION__,status); + } + return status; +} + +static int SetQAM16 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16)); + + /* QAM Loop Controller Coeficients */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM32 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM32 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM64 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM64 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM128 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM128(struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM256 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM256(struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + + +/*============================================================================*/ +/** +* \brief Reset QAM block. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static int QAMResetQAM(struct drxk_state *state) +{ + int status; + u16 cmdResult; + + //printk("%s\n", __FUNCTION__); + do + { + /* Stop QAM comstate->m_exec */ + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); + + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); + } while (0); + + /* All done, all OK */ + return status; +} + +/*============================================================================*/ + +/** +* \brief Set QAM symbolrate. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static int QAMSetSymbolrate(struct drxk_state *state) +{ + u32 adcFrequency = 0; + u32 symbFreq = 0; + u32 iqmRcRate = 0; + u16 ratesel = 0; + u32 lcSymbRate = 0; + int status; + u32 srate = +#ifndef USE_API3 + state->props.symbol_rate; +#else + state->param.u.qam.symbol_rate; +#endif + + do + { + /* Select & calculate correct IQM rate */ + adcFrequency = (state->m_sysClockFreq * 1000) / 3; + ratesel = 0; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate)); + //printk("SR %d\n", state->param.u.qam.symbol_rate); + if (srate <= 1188750) + { + ratesel = 3; + } + else if (srate <= 2377500) + { + ratesel = 2; + } + else if (srate <= 4755000) + { + ratesel = 1; + } + CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel)); + + /* + IqmRcRate = ((Fadc / (symbolrate * (4<> 7) - + (1 << 23); + CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0)); + state->m_iqmRcRate = iqmRcRate; + /* + LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) + */ + symbFreq = srate; + if (adcFrequency == 0) + { + /* Divide by zero */ + return -1; + } + lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + + (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16); + if (lcSymbRate > 511) + { + lcSymbRate = 511; + } + CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate)); + } while (0); + + return status; +} + +/*============================================================================*/ + +/** +* \brief Get QAM lock status. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ + +static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) +{ + int status; + u16 Result[2] = {0,0}; + + status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result); + if (status<0) + { + printk("%s status = %08x\n",__FUNCTION__,status); + } + if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) + { + /* 0x0000 NOT LOCKED */ + *pLockStatus = NOT_LOCKED; + } + else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) + { + /* 0x4000 DEMOD LOCKED */ + *pLockStatus = DEMOD_LOCK; + } + else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) + { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *pLockStatus = MPEG_LOCK; + } + else + { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + /* TODO: check this, intermediate & standard specific lock states are not + taken into account here */ + *pLockStatus = NEVER_LOCK; + } + return status; +} + +#define QAM_MIRROR__M 0x03 +#define QAM_MIRROR_NORMAL 0x00 +#define QAM_MIRRORED 0x01 +#define QAM_MIRROR_AUTO_ON 0x02 +#define QAM_LOCKRANGE__M 0x10 +#define QAM_LOCKRANGE_NORMAL 0x10 + +static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + u8 parameterLen; + u16 setEnvParameters[5]; + u16 setParamParameters[4]={0,0,0,0}; + u16 cmdResult; + + //printk("%s\n", __FUNCTION__); + + do { + /* + STEP 1: reset demodulator + resets FEC DI and FEC RS + resets QAM block + resets SCU variables + */ + CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP)); + CHK_ERROR(QAMResetQAM(state)); + + /* + STEP 2: configure demodulator + -set env + -set params; resets IQM,QAM,FEC HW; initializes some SCU variables + */ + CHK_ERROR(QAMSetSymbolrate(state)); + + /* Env parameters */ + setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ + if (state->m_OperationMode == OM_QAM_ITU_C) + { + setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ + } + setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); +// check for LOCKRANGE Extented + // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; + parameterLen = 4; + + /* Set params */ +#ifndef USE_API3 + switch(state->props.modulation) +#else + switch(state->param.u.qam.modulation) +#endif + { + case QAM_256: + state->m_Constellation = DRX_CONSTELLATION_QAM256; + break; + case QAM_AUTO: + case QAM_64: + state->m_Constellation = DRX_CONSTELLATION_QAM64; + break; + case QAM_16: + state->m_Constellation = DRX_CONSTELLATION_QAM16; + break; + case QAM_32: + state->m_Constellation = DRX_CONSTELLATION_QAM32; + break; + case QAM_128: + state->m_Constellation = DRX_CONSTELLATION_QAM128; + break; + default: + status = -EINVAL; + break; + } + CHK_ERROR(status); + setParamParameters[0] = state->m_Constellation; /* constellation */ + setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ + + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult)); + + + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ +// CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); + CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true)); + + /* Setup BER measurement */ + CHK_ERROR(SetQAMMeasurement (state, + state->m_Constellation, +#ifndef USE_API3 + state->props.symbol_rate)); +#else + state->param.u.qam.symbol_rate)); +#endif + + /* Reset default values */ + CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE)); + CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); + + /* Reset default LC values */ + CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); + + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); + + /* Mirroring, QAM-block starting point not inverted */ + CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* STEP 4: constellation specific setup */ +#ifndef USE_API3 + switch (state->props.modulation) +#else + switch (state->param.u.qam.modulation) +#endif + { + case QAM_16: + CHK_ERROR(SetQAM16(state)); + break; + case QAM_32: + CHK_ERROR(SetQAM32(state)); + break; + case QAM_AUTO: + case QAM_64: + CHK_ERROR(SetQAM64(state)); + break; + case QAM_128: + CHK_ERROR(SetQAM128(state)); + break; + case QAM_256: + //printk("SETQAM256\n"); + CHK_ERROR(SetQAM256(state)); + break; + default: + return -1; + break; + } /* switch */ + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + + + /* Re-configure MPEG output, requires knowledge of channel bitrate */ +// extAttr->currentChannel.constellation = channel->constellation; +// extAttr->currentChannel.symbolrate = channel->symbolrate; + CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); + + /* Start processes */ + CHK_ERROR(MPEGTSStart(state)); + CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); + + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START,0, + NULL,1,&cmdResult)); + + /* update global DRXK data container */ +//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; + + /* All done, all OK */ + } while(0); + + if (status<0) { + printk("%s %d\n", __FUNCTION__, status); + } + return status; +} + +static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode) +{ +#ifdef DRXK_QAM_TAPS +#define DRXK_QAMA_TAPS_SELECT +#include "drxk_filters.h" +#undef DRXK_QAMA_TAPS_SELECT +#else + int status; +#endif + + //printk("%s\n", __FUNCTION__); + do + { + /* added antenna switch */ + SwitchAntennaToQAM(state); + + /* Ensure correct power-up mode */ + CHK_ERROR(PowerUpQAM(state)); + /* Reset QAM block */ + CHK_ERROR(QAMResetQAM(state)); + + /* Setup IQM */ + + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); + CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); + + /* Upload IQM Channel Filter settings by + boot loader from ROM table */ + switch (oMode) + { + case OM_QAM_ITU_A: + CHK_ERROR(BLChainCmd(state, + DRXK_BL_ROM_OFFSET_TAPS_ITU_A, + DRXK_BLCC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + break; + case OM_QAM_ITU_C: + CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, + DRXK_BL_ROM_OFFSET_TAPS_ITU_C, + DRXK_BLDC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, + DRXK_BL_ROM_OFFSET_TAPS_ITU_C, + DRXK_BLDC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + break; + default: + status=-EINVAL; + } + CHK_ERROR (status); + + CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, + (1 << IQM_CF_OUT_ENA_QAM__B))); + CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, + ((1 << IQM_CF_MIDTAP_RE__B) | + (1 << IQM_CF_MIDTAP_IM__B)))); + + CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); + CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); + CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); + CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); + + CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); + + /* IQM Impulse Noise Processing Unit */ + CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); + CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); + CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); + CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); + + /* turn on IQMAF. Must be done before setAgc**() */ + CHK_ERROR(SetIqmAf(state, true)); + CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); + + /* IQM will not be reset from here, sync ADC and update/init AGC */ + CHK_ERROR(ADCSynchronization (state)); + + /* Set the FSM step period */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + + CHK_ERROR(InitAGC(state,true)); + CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); + + /* Configure AGC's */ + CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); + CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true)); + + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + } while (0); + return status; +} + +static int WriteGPIO(struct drxk_state *state) +{ + int status; + u16 value = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + /* Write magic word to enable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, + SIO_TOP_COMM_KEY_KEY)); + + if (state->m_hasSAWSW) { + /* write to io pad configuration register - output mode */ + CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, + state->m_GPIOCfg)); + + /* use corresponding bit in io data output registar */ + CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value)); + if (state->m_GPIO == 0) { + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + } else { + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + } + /* write back to io data output register */ + CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value)); + + } + /* Write magic word to disable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + } while (0); + return status; +} + +static int SwitchAntennaToQAM(struct drxk_state *state) +{ + int status = -1; + + if (state->m_AntennaSwitchDVBTDVBC != 0) { + if (state->m_GPIO != state->m_AntennaDVBC) { + state->m_GPIO = state->m_AntennaDVBC; + status = WriteGPIO(state); + } + } + return status; +} + +static int SwitchAntennaToDVBT(struct drxk_state *state) +{ + int status = -1; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + if (state->m_AntennaSwitchDVBTDVBC != 0) { + if (state->m_GPIO != state->m_AntennaDVBT) { + state->m_GPIO = state->m_AntennaDVBT; + status = WriteGPIO(state); + } + } + return status; +} + + +static int PowerDownDevice(struct drxk_state *state) +{ + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + int status; + do { + if (state->m_bPDownOpenBridge) { + // Open I2C bridge before power down of DRXK + CHK_ERROR(ConfigureI2CBridge(state, true)); + } + // driver 0.9.0 + CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); + + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY)); + state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(HI_CfgCommand(state)); + } + while(0); + + if (status<0) { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + return -1; + } + return 0; +} + +static int load_microcode(struct drxk_state *state, char *mc_name) +{ + const struct firmware *fw = NULL; + int err=0; + + err = request_firmware(&fw, mc_name, state->i2c->dev.parent); + if (err < 0) { + printk(KERN_ERR + ": Could not load firmware file %s.\n", mc_name); + printk(KERN_INFO + ": Copy %s to your hotplug directory!\n", mc_name); + return err; + } + err=DownloadMicrocode(state, fw->data, fw->size); + release_firmware(fw); + return err; +} + +static int init_drxk(struct drxk_state *state) +{ + int status; + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + u16 driverVersion; + + //printk("init_drxk\n"); + if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { + do { + CHK_ERROR(PowerUpDevice(state)); + CHK_ERROR (DRXX_Open(state)); + /* Soft reset of OFDM-, sys- and osc-clockdomain */ + CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, + SIO_CC_SOFT_RST_OFDM__M | + SIO_CC_SOFT_RST_SYS__M | + SIO_CC_SOFT_RST_OSC__M)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); + /* TODO is this needed, if yes how much delay in worst case scenario */ + msleep(1); + state->m_DRXK_A3_PATCH_CODE = true; + CHK_ERROR(GetDeviceCapabilities(state)); + + /* Bridge delay, uses oscilator clock */ + /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ + /* SDA brdige delay */ + state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000; + /* Clipping */ + if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) + { + state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + } + /* SCL bridge delay, same as SDA for now */ + state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; + + CHK_ERROR(InitHI(state)); + /* disable various processes */ +#if NOA1ROM + if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) ) +#endif + { + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + } + + /* disable MPEG port */ + CHK_ERROR(MPEGTSDisable(state)); + + /* Stop AUD and SCU */ + CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP)); + + /* enable token-ring bus through OFDM block for possible ucode upload */ + CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); + + /* include boot loader section */ + CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE)); + CHK_ERROR(BLChainCmd(state, 0, 6, 100)); + +#if 0 + if (state->m_DRXK_A3_PATCH_CODE) + CHK_ERROR(DownloadMicrocode(state, + DRXK_A3_microcode, + DRXK_A3_microcode_length)); +#else + load_microcode(state, "drxk_a3.mc"); +#endif +#if NOA1ROM + if (state->m_DRXK_A2_PATCH_CODE) + CHK_ERROR(DownloadMicrocode(state, + DRXK_A2_microcode, + DRXK_A2_microcode_length)); +#endif + /* disable token-ring bus through OFDM block for possible ucode upload */ + CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); + + /* Run SCU for a little while to initialize microcode version numbers */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + CHK_ERROR (DRXX_Open(state)); + // added for test + msleep(30); + + powerMode = DRXK_POWER_DOWN_OFDM; + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retreive drxdriver version + via I2C from SCU RAM. + Not using SCU command interface for SCU register access since no + microcode may be present. + */ + driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) + + (((DRXK_VERSION_MAJOR/10) % 10) << 8) + + ((DRXK_VERSION_MAJOR%10) << 4) + + (DRXK_VERSION_MINOR%10); + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion )); + driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) + + (((DRXK_VERSION_PATCH/100) % 10) << 8) + + (((DRXK_VERSION_PATCH/10) % 10) << 4) + + (DRXK_VERSION_PATCH%10); + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion )); + + printk("DRXK driver version:%d.%d.%d\n", + DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH); + + /* Dirty fix of default values for ROM/PATCH microcode + Dirty because this fix makes it impossible to setup suitable values + before calling DRX_Open. This solution requires changes to RF AGC speed + to be done via the CTRL function after calling DRX_Open */ + + // m_dvbtRfAgcCfg.speed=3; + + /* Reset driver debug flags to 0 */ + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0)); + /* driver 0.9.0 */ + /* Setup FEC OC: + NOTE: No more full FEC resets allowed afterwards!! */ + CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP)); + // MPEGTS functions are still the same + CHK_ERROR(MPEGTSDtoInit(state)); + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(MPEGTSConfigurePolarity(state)); + CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput)); + // added: configure GPIO + CHK_ERROR(WriteGPIO(state)); + + state->m_DrxkState = DRXK_STOPPED; + + if (state->m_bPowerDown) { + CHK_ERROR(PowerDownDevice(state)); + state->m_DrxkState = DRXK_POWERED_DOWN; + } + else + state->m_DrxkState = DRXK_STOPPED; + } while(0); + //printk("%s=%d\n", __FUNCTION__, status); + } + else + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n")); + } + + return 0; +} + +static void drxk_c_release(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + printk("%s\n", __FUNCTION__); + kfree(state); +} + +static int drxk_c_init (struct dvb_frontend *fe) +{ + struct drxk_state *state=fe->demodulator_priv; + + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + SetOperationMode(state, OM_QAM_ITU_A); + return 0; +} + +static int drxk_c_sleep(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + + ShutDown(state); + mutex_unlock(&state->ctlock); + return 0; +} + +static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable) +{ + struct drxk_state *state = fe->demodulator_priv; + + //printk("drxk_gate %d\n", enable); + return ConfigureI2CBridge(state, enable ? true : false); +} + +#ifndef USE_API3 +static int drxk_set_parameters (struct dvb_frontend *fe) +#else +static int drxk_set_parameters (struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +#endif +{ +#ifndef USE_API3 + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + u32 delsys = p->delivery_system, old_delsys; +#endif + struct drxk_state *state = fe->demodulator_priv; + u32 IF; + + //printk("%s\n", __FUNCTION__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (fe->ops.tuner_ops.set_params) +#ifndef USE_API3 + fe->ops.tuner_ops.set_params(fe); +#else + fe->ops.tuner_ops.set_params(fe, p); +#endif + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); +#ifndef USE_API3 +#else + state->param=*p; +#endif + fe->ops.tuner_ops.get_if_frequency(fe, &IF); /* WTF is a frequency frequency? */ + Start(state, 0, IF); + + //printk("%s IF=%d done\n", __FUNCTION__, IF); + return 0; +} + +static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct drxk_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct drxk_state *state = fe->demodulator_priv; + u32 stat; + + *status=0; + GetLockStatus(state, &stat, 0); + if (stat==MPEG_LOCK) + *status|=0x1f; + if (stat==FEC_LOCK) + *status|=0x0f; + if (stat==DEMOD_LOCK) + *status|=0x07; + return 0; +} + +static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + //struct drxk_state *state = fe->demodulator_priv; + *ber=0; + return 0; +} + +static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct drxk_state *state = fe->demodulator_priv; + u32 val; + + ReadIFAgc(state, &val); + *strength = val & 0xffff;; + return 0; +} + +static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct drxk_state *state = fe->demodulator_priv; + s32 snr2; + + GetSignalToNoise(state, &snr2); + *snr = snr2&0xffff; + return 0; +} + +static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct drxk_state *state = fe->demodulator_priv; + u16 err; + + DVBTQAMGetAccPktErr(state, &err); + *ucblocks = (u32) err; + return 0; +} + +static int drxk_c_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + sets->min_delay_ms=3000; + sets->max_drift=0; + sets->step_size=0; + return 0; +} + +static void drxk_t_release(struct dvb_frontend* fe) +{ + //struct drxk_state *state=fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + //kfree(state); +} + +static int drxk_t_init (struct dvb_frontend *fe) +{ + struct drxk_state *state=fe->demodulator_priv; + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + //printk("%s\n", __FUNCTION__); + SetOperationMode(state, OM_DVBT); + //printk("%s done\n", __FUNCTION__); + return 0; +} + +static int drxk_t_sleep(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + mutex_unlock(&state->ctlock); + return 0; +} + +static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct drxk_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static struct dvb_frontend_ops drxk_c_ops = { + .info = { + .name = "DRXK DVB-C", + .type = FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 47000000, + .frequency_max = 862000000, + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO + }, + .release = drxk_c_release, + .init = drxk_c_init, + .sleep = drxk_c_sleep, + .i2c_gate_ctrl = drxk_gate_ctrl, + + .set_frontend = drxk_set_parameters, + .get_frontend = drxk_c_get_frontend, + .get_tune_settings = drxk_c_get_tune_settings, + + .read_status = drxk_read_status, + .read_ber = drxk_read_ber, + .read_signal_strength = drxk_read_signal_strength, + .read_snr = drxk_read_snr, + .read_ucblocks = drxk_read_ucblocks, +}; + +static struct dvb_frontend_ops drxk_t_ops = { + .info = { + .name = "DRXK DVB-T", + .type = FE_OFDM, + .frequency_min = 47125000, + .frequency_max = 865000000, + .frequency_stepsize = 166667, + .frequency_tolerance = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | + FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | + FE_CAN_MUTE_TS + }, + .release = drxk_t_release, + .init = drxk_t_init, + .sleep = drxk_t_sleep, + .i2c_gate_ctrl = drxk_gate_ctrl, + + .set_frontend = drxk_set_parameters, + .get_frontend = drxk_t_get_frontend, + + .read_status = drxk_read_status, + .read_ber = drxk_read_ber, + .read_signal_strength = drxk_read_signal_strength, + .read_snr = drxk_read_snr, + .read_ucblocks = drxk_read_ucblocks, +}; + +struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, + struct dvb_frontend **fe_t) +{ + struct drxk_state *state = NULL; + + state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL); + if (!state) + return NULL; + + state->i2c=i2c; + state->demod_address=adr; + + mutex_init(&state->mutex); + mutex_init(&state->ctlock); + + memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops)); + memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops)); + state->c_frontend.demodulator_priv=state; + state->t_frontend.demodulator_priv=state; + + init_state(state); + if (init_drxk(state)<0) + goto error; + *fe_t = &state->t_frontend; + return &state->c_frontend; + +error: + printk("drxk: not found\n"); + kfree(state); + return NULL; +} + +MODULE_DESCRIPTION("DRX-K driver"); +MODULE_AUTHOR("Ralph Metzler"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(drxk_attach); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_hard.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,343 @@ +#include "drxk_map.h" + +#define DRXK_VERSION_MAJOR 0 +#define DRXK_VERSION_MINOR 9 +#define DRXK_VERSION_PATCH 4300 + +#define HI_I2C_DELAY 42 +#define HI_I2C_BRIDGE_DELAY 350 +#define DRXK_MAX_RETRIES 100 + +#define DRIVER_4400 1 + +#define DRXX_JTAGID 0x039210D9 +#define DRXX_J_JTAGID 0x239310D9 +#define DRXX_K_JTAGID 0x039210D9 + +#define DRX_UNKNOWN 254 +#define DRX_AUTO 255 + +#define DRX_SCU_READY 0 +#define DRXK_MAX_WAITTIME (200) +#define SCU_RESULT_OK 0 +#define SCU_RESULT_UNKSTD -2 +#define SCU_RESULT_UNKCMD -1 + +#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT +#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) +#endif + +#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ +#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ +#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ +#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ +#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ +#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ +#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ +#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ + +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 + +enum OperationMode { + OM_NONE, + OM_QAM_ITU_A, + OM_QAM_ITU_B, + OM_QAM_ITU_C, + OM_DVBT +}; + +typedef enum { + DRX_POWER_UP = 0, + DRX_POWER_MODE_1, + DRX_POWER_MODE_2, + DRX_POWER_MODE_3, + DRX_POWER_MODE_4, + DRX_POWER_MODE_5, + DRX_POWER_MODE_6, + DRX_POWER_MODE_7, + DRX_POWER_MODE_8, + + DRX_POWER_MODE_9, + DRX_POWER_MODE_10, + DRX_POWER_MODE_11, + DRX_POWER_MODE_12, + DRX_POWER_MODE_13, + DRX_POWER_MODE_14, + DRX_POWER_MODE_15, + DRX_POWER_MODE_16, + DRX_POWER_DOWN = 255 +}DRXPowerMode_t, *pDRXPowerMode_t; + + +/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ +#ifndef DRXK_POWER_DOWN_OFDM +#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 +#endif + +/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ +#ifndef DRXK_POWER_DOWN_CORE +#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 +#endif + +/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ +#ifndef DRXK_POWER_DOWN_PLL +#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 +#endif + + +enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; +enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; +enum EDrxkCoefArrayIndex { + DRXK_COEF_IDX_MN = 0, + DRXK_COEF_IDX_FM , + DRXK_COEF_IDX_L , + DRXK_COEF_IDX_LP , + DRXK_COEF_IDX_BG , + DRXK_COEF_IDX_DK , + DRXK_COEF_IDX_I , + DRXK_COEF_IDX_MAX +}; +enum EDrxkSifAttenuation { + DRXK_SIF_ATTENUATION_0DB, + DRXK_SIF_ATTENUATION_3DB, + DRXK_SIF_ATTENUATION_6DB, + DRXK_SIF_ATTENUATION_9DB +}; +enum EDrxkConstellation { + DRX_CONSTELLATION_BPSK = 0, + DRX_CONSTELLATION_QPSK, + DRX_CONSTELLATION_PSK8, + DRX_CONSTELLATION_QAM16, + DRX_CONSTELLATION_QAM32, + DRX_CONSTELLATION_QAM64, + DRX_CONSTELLATION_QAM128, + DRX_CONSTELLATION_QAM256, + DRX_CONSTELLATION_QAM512, + DRX_CONSTELLATION_QAM1024, + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, + DRX_CONSTELLATION_AUTO = DRX_AUTO +}; +enum EDrxkInterleaveMode { + DRXK_QAM_I12_J17 = 16, + DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN +}; +enum { + DRXK_SPIN_A1 = 0, + DRXK_SPIN_A2, + DRXK_SPIN_A3, + DRXK_SPIN_UNKNOWN +}; + +enum DRXKCfgDvbtSqiSpeed { + DRXK_DVBT_SQI_SPEED_FAST = 0, + DRXK_DVBT_SQI_SPEED_MEDIUM, + DRXK_DVBT_SQI_SPEED_SLOW, + DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +} ; + +enum DRXFftmode_t { + DRX_FFTMODE_2K = 0, + DRX_FFTMODE_4K, + DRX_FFTMODE_8K, + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, + DRX_FFTMODE_AUTO = DRX_AUTO +}; + +enum DRXMPEGStrWidth_t { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 +}; + +enum DRXQamLockRange_t { + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED +}; + +struct DRXKCfgDvbtEchoThres_t { + u16 threshold; + enum DRXFftmode_t fftMode; +} ; + +struct SCfgAgc +{ + enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ + u16 outputLevel; /* range dependent on AGC */ + u16 minOutputLevel; /* range dependent on AGC */ + u16 maxOutputLevel; /* range dependent on AGC */ + u16 speed; /* range dependent on AGC */ + u16 top; /* rf-agc take over point */ + u16 cutOffCurrent; /* rf-agc is accelerated if output current + is below cut-off current */ + u16 IngainTgtMax; + u16 FastClipCtrlDelay; +}; + +struct SCfgPreSaw +{ + u16 reference; /* pre SAW reference value, range 0 .. 31 */ + bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ +}; + +struct DRXKOfdmScCmd_t +{ + u16 cmd; /**< Command number */ + u16 subcmd; /**< Sub-command parameter*/ + u16 param0; /**< General purpous param */ + u16 param1; /**< General purpous param */ + u16 param2; /**< General purpous param */ + u16 param3; /**< General purpous param */ + u16 param4; /**< General purpous param */ +}; + +struct drxk_state { + struct dvb_frontend c_frontend; + struct dvb_frontend t_frontend; +#ifndef USE_API3 + struct dtv_frontend_properties props; +#else + struct dvb_frontend_parameters param; +#endif + struct device *dev; + + struct i2c_adapter *i2c; + u8 demod_address; + void *priv; + + struct mutex mutex; + struct mutex ctlock; + + u32 m_Instance; ///< Channel 1,2,3 or 4 + + int m_ChunkSize; + u8 Chunk[256]; + + bool m_hasLNA; + bool m_hasDVBT; + bool m_hasDVBC; + bool m_hasAudio; + bool m_hasATV; + bool m_hasOOB; + bool m_hasSAWSW; /**< TRUE if mat_tx is available */ + bool m_hasGPIO1; /**< TRUE if mat_rx is available */ + bool m_hasGPIO2; /**< TRUE if GPIO is available */ + bool m_hasIRQN; /**< TRUE if IRQN is available */ + u16 m_oscClockFreq; + u16 m_HICfgTimingDiv; + u16 m_HICfgBridgeDelay; + u16 m_HICfgWakeUpKey; + u16 m_HICfgTimeout; + u16 m_HICfgCtrl; + s32 m_sysClockFreq ; ///< system clock frequency in kHz + + enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started) + enum OperationMode m_OperationMode; ///< digital standards + struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC + struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC + u16 m_vsbPgaCfg; ///< settings for VSB PGA + struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense + s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication + s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication + bool m_smartAntInverted; + bool m_bDebugEnableBridge; + bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed + bool m_bPowerDown; ///< Power down when not used + + u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint) + + bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ + bool m_insertRSByte; /**< If TRUE, insert RS byte */ + bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ + bool m_invertDATA; /**< If TRUE, invert DATA signals */ + bool m_invertERR; /**< If TRUE, invert ERR signal */ + bool m_invertSTR; /**< If TRUE, invert STR signals */ + bool m_invertVAL; /**< If TRUE, invert VAL signals */ + bool m_invertCLK; /**< If TRUE, invert CLK signals */ + bool m_DVBCStaticCLK; + bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + u32 m_DVBTBitrate; + u32 m_DVBCBitrate; + + u8 m_TSDataStrength; + u8 m_TSClockkStrength; + + enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/ + u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case + static clockrate is selected */ + + //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start + s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) + s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) + + bool m_disableTEIhandling; + + bool m_RfAgcPol; + bool m_IfAgcPol; + + struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC + struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC + struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense + bool m_phaseCorrectionBypass; + s16 m_atvTopVidPeak; + u16 m_atvTopNoiseTh; + enum EDrxkSifAttenuation m_sifAttenuation; + bool m_enableCVBSOutput; + bool m_enableSIFOutput; + bool m_bMirrorFreqSpect; + enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel + u32 m_CurrSymbolRate; ///< Current QAM symbol rate + struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC + struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC + u16 m_qamPgaCfg; ///< settings for QAM PGA + struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense + enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode + u16 m_fecRsPlen; + u16 m_fecRsPrescale; + + enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; + + u16 m_GPIO; + u16 m_GPIOCfg; + + struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC + struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC + struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense + + u16 m_agcFastClipCtrlDelay; + bool m_adcCompPassed; + u16 m_adcCompCoef[64]; + u16 m_adcState; + + u8 *m_microcode; + int m_microcode_length; + bool m_DRXK_A1_PATCH_CODE; + bool m_DRXK_A1_ROM_CODE; + bool m_DRXK_A2_ROM_CODE; + bool m_DRXK_A3_ROM_CODE; + bool m_DRXK_A2_PATCH_CODE; + bool m_DRXK_A3_PATCH_CODE; + + bool m_rfmirror; + u8 m_deviceSpin; + u32 m_iqmRcRate; + + u16 m_AntennaDVBC; + u16 m_AntennaDVBT; + u16 m_AntennaSwitchDVBTDVBC; + + DRXPowerMode_t m_currentPowerMode; +}; + +#define NEVER_LOCK 0 +#define NOT_LOCKED 1 +#define DEMOD_LOCK 2 +#define FEC_LOCK 3 +#define MPEG_LOCK 4 + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,16438 @@ +#ifndef __DRXK_MAP__H__ +#define __DRXK_MAP__H__ 1 + +#define AUD_COMM_EXEC__A 0x1000000 +#define AUD_COMM_EXEC__W 2 +#define AUD_COMM_EXEC__M 0x3 +#define AUD_COMM_EXEC__PRE 0x0 +#define AUD_COMM_EXEC_STOP 0x0 + +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_COMM_EXEC__W 2 +#define FEC_COMM_EXEC__M 0x3 +#define FEC_COMM_EXEC__PRE 0x0 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_HOLD 0x2 + +#define FEC_COMM_MB__A 0x1C00002 +#define FEC_COMM_MB__W 16 +#define FEC_COMM_MB__M 0xFFFF +#define FEC_COMM_MB__PRE 0x0 +#define FEC_COMM_INT_REQ__A 0x1C00003 +#define FEC_COMM_INT_REQ__W 16 +#define FEC_COMM_INT_REQ__M 0xFFFF +#define FEC_COMM_INT_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_OC_REQ__B 0 +#define FEC_COMM_INT_REQ_OC_REQ__W 1 +#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_RS_REQ__B 1 +#define FEC_COMM_INT_REQ_RS_REQ__W 1 +#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_DI_REQ__B 2 +#define FEC_COMM_INT_REQ_DI_REQ__W 1 +#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 + +#define FEC_COMM_INT_STA__A 0x1C00005 +#define FEC_COMM_INT_STA__W 16 +#define FEC_COMM_INT_STA__M 0xFFFF +#define FEC_COMM_INT_STA__PRE 0x0 +#define FEC_COMM_INT_MSK__A 0x1C00006 +#define FEC_COMM_INT_MSK__W 16 +#define FEC_COMM_INT_MSK__M 0xFFFF +#define FEC_COMM_INT_MSK__PRE 0x0 +#define FEC_COMM_INT_STM__A 0x1C00007 +#define FEC_COMM_INT_STM__W 16 +#define FEC_COMM_INT_STM__M 0xFFFF +#define FEC_COMM_INT_STM__PRE 0x0 + + + +#define FEC_TOP_COMM_EXEC__A 0x1C10000 +#define FEC_TOP_COMM_EXEC__W 2 +#define FEC_TOP_COMM_EXEC__M 0x3 +#define FEC_TOP_COMM_EXEC__PRE 0x0 +#define FEC_TOP_COMM_EXEC_STOP 0x0 +#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +#define FEC_TOP_COMM_EXEC_HOLD 0x2 + +#define FEC_TOP_ANNEX__A 0x1C10010 +#define FEC_TOP_ANNEX__W 2 +#define FEC_TOP_ANNEX__M 0x3 +#define FEC_TOP_ANNEX__PRE 0x0 +#define FEC_TOP_ANNEX_A 0x0 +#define FEC_TOP_ANNEX_B 0x1 +#define FEC_TOP_ANNEX_C 0x2 +#define FEC_TOP_ANNEX_D 0x3 + + + +#define FEC_DI_COMM_EXEC__A 0x1C20000 +#define FEC_DI_COMM_EXEC__W 2 +#define FEC_DI_COMM_EXEC__M 0x3 +#define FEC_DI_COMM_EXEC__PRE 0x0 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +#define FEC_DI_COMM_EXEC_HOLD 0x2 + +#define FEC_DI_COMM_MB__A 0x1C20002 +#define FEC_DI_COMM_MB__W 2 +#define FEC_DI_COMM_MB__M 0x3 +#define FEC_DI_COMM_MB__PRE 0x0 +#define FEC_DI_COMM_MB_CTL__B 0 +#define FEC_DI_COMM_MB_CTL__W 1 +#define FEC_DI_COMM_MB_CTL__M 0x1 +#define FEC_DI_COMM_MB_CTL__PRE 0x0 +#define FEC_DI_COMM_MB_CTL_OFF 0x0 +#define FEC_DI_COMM_MB_CTL_ON 0x1 +#define FEC_DI_COMM_MB_OBS__B 1 +#define FEC_DI_COMM_MB_OBS__W 1 +#define FEC_DI_COMM_MB_OBS__M 0x2 +#define FEC_DI_COMM_MB_OBS__PRE 0x0 +#define FEC_DI_COMM_MB_OBS_OFF 0x0 +#define FEC_DI_COMM_MB_OBS_ON 0x2 + +#define FEC_DI_COMM_INT_REQ__A 0x1C20003 +#define FEC_DI_COMM_INT_REQ__W 1 +#define FEC_DI_COMM_INT_REQ__M 0x1 +#define FEC_DI_COMM_INT_REQ__PRE 0x0 +#define FEC_DI_COMM_INT_STA__A 0x1C20005 +#define FEC_DI_COMM_INT_STA__W 2 +#define FEC_DI_COMM_INT_STA__M 0x3 +#define FEC_DI_COMM_INT_STA__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_MSK__A 0x1C20006 +#define FEC_DI_COMM_INT_MSK__W 2 +#define FEC_DI_COMM_INT_MSK__M 0x3 +#define FEC_DI_COMM_INT_MSK__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STM__A 0x1C20007 +#define FEC_DI_COMM_INT_STM__W 2 +#define FEC_DI_COMM_INT_STM__M 0x3 +#define FEC_DI_COMM_INT_STM__PRE 0x0 +#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 + + +#define FEC_DI_STATUS__A 0x1C20010 +#define FEC_DI_STATUS__W 1 +#define FEC_DI_STATUS__M 0x1 +#define FEC_DI_STATUS__PRE 0x0 +#define FEC_DI_MODE__A 0x1C20011 +#define FEC_DI_MODE__W 3 +#define FEC_DI_MODE__M 0x7 +#define FEC_DI_MODE__PRE 0x0 + +#define FEC_DI_MODE_NO_SYNC__B 0 +#define FEC_DI_MODE_NO_SYNC__W 1 +#define FEC_DI_MODE_NO_SYNC__M 0x1 +#define FEC_DI_MODE_NO_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 + + +#define FEC_DI_CONTROL_WORD__A 0x1C20012 +#define FEC_DI_CONTROL_WORD__W 4 +#define FEC_DI_CONTROL_WORD__M 0xF +#define FEC_DI_CONTROL_WORD__PRE 0x0 + +#define FEC_DI_RESTART__A 0x1C20013 +#define FEC_DI_RESTART__W 1 +#define FEC_DI_RESTART__M 0x1 +#define FEC_DI_RESTART__PRE 0x0 + +#define FEC_DI_TIMEOUT_LO__A 0x1C20014 +#define FEC_DI_TIMEOUT_LO__W 16 +#define FEC_DI_TIMEOUT_LO__M 0xFFFF +#define FEC_DI_TIMEOUT_LO__PRE 0x0 + +#define FEC_DI_TIMEOUT_HI__A 0x1C20015 +#define FEC_DI_TIMEOUT_HI__W 8 +#define FEC_DI_TIMEOUT_HI__M 0xFF +#define FEC_DI_TIMEOUT_HI__PRE 0xA + +#define FEC_DI_INPUT_CTL__A 0x1C20016 +#define FEC_DI_INPUT_CTL__W 1 +#define FEC_DI_INPUT_CTL__M 0x1 +#define FEC_DI_INPUT_CTL__PRE 0x0 + + + +#define FEC_RS_COMM_EXEC__A 0x1C30000 +#define FEC_RS_COMM_EXEC__W 2 +#define FEC_RS_COMM_EXEC__M 0x3 +#define FEC_RS_COMM_EXEC__PRE 0x0 +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +#define FEC_RS_COMM_EXEC_HOLD 0x2 + +#define FEC_RS_COMM_MB__A 0x1C30002 +#define FEC_RS_COMM_MB__W 2 +#define FEC_RS_COMM_MB__M 0x3 +#define FEC_RS_COMM_MB__PRE 0x0 +#define FEC_RS_COMM_MB_CTL__B 0 +#define FEC_RS_COMM_MB_CTL__W 1 +#define FEC_RS_COMM_MB_CTL__M 0x1 +#define FEC_RS_COMM_MB_CTL__PRE 0x0 +#define FEC_RS_COMM_MB_CTL_OFF 0x0 +#define FEC_RS_COMM_MB_CTL_ON 0x1 +#define FEC_RS_COMM_MB_OBS__B 1 +#define FEC_RS_COMM_MB_OBS__W 1 +#define FEC_RS_COMM_MB_OBS__M 0x2 +#define FEC_RS_COMM_MB_OBS__PRE 0x0 +#define FEC_RS_COMM_MB_OBS_OFF 0x0 +#define FEC_RS_COMM_MB_OBS_ON 0x2 + +#define FEC_RS_COMM_INT_REQ__A 0x1C30003 +#define FEC_RS_COMM_INT_REQ__W 1 +#define FEC_RS_COMM_INT_REQ__M 0x1 +#define FEC_RS_COMM_INT_REQ__PRE 0x0 +#define FEC_RS_COMM_INT_STA__A 0x1C30005 +#define FEC_RS_COMM_INT_STA__W 2 +#define FEC_RS_COMM_INT_STA__M 0x3 +#define FEC_RS_COMM_INT_STA__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_MSK__A 0x1C30006 +#define FEC_RS_COMM_INT_MSK__W 2 +#define FEC_RS_COMM_INT_MSK__M 0x3 +#define FEC_RS_COMM_INT_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_COMM_INT_STM__A 0x1C30007 +#define FEC_RS_COMM_INT_STM__W 2 +#define FEC_RS_COMM_INT_STM__M 0x3 +#define FEC_RS_COMM_INT_STM__PRE 0x0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_STATUS__A 0x1C30010 +#define FEC_RS_STATUS__W 1 +#define FEC_RS_STATUS__M 0x1 +#define FEC_RS_STATUS__PRE 0x0 +#define FEC_RS_MODE__A 0x1C30011 +#define FEC_RS_MODE__W 1 +#define FEC_RS_MODE__M 0x1 +#define FEC_RS_MODE__PRE 0x0 + +#define FEC_RS_MODE_BYPASS__B 0 +#define FEC_RS_MODE_BYPASS__W 1 +#define FEC_RS_MODE_BYPASS__M 0x1 +#define FEC_RS_MODE_BYPASS__PRE 0x0 + +#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +#define FEC_RS_MEASUREMENT_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993 + +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993 + +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 + +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 + +#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 +#define FEC_RS_NR_BIT_ERRORS__W 16 +#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015 +#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016 +#define FEC_RS_NR_PACKET_ERRORS__W 16 +#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_FAILURES__A 0x1C30017 +#define FEC_RS_NR_FAILURES__W 16 +#define FEC_RS_NR_FAILURES__M 0xFFFF +#define FEC_RS_NR_FAILURES__PRE 0x0 + +#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 + +#define FEC_RS_NR_FAILURES_EXP__B 12 +#define FEC_RS_NR_FAILURES_EXP__W 4 +#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 + + + +#define FEC_OC_COMM_EXEC__A 0x1C40000 +#define FEC_OC_COMM_EXEC__W 2 +#define FEC_OC_COMM_EXEC__M 0x3 +#define FEC_OC_COMM_EXEC__PRE 0x0 +#define FEC_OC_COMM_EXEC_STOP 0x0 +#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +#define FEC_OC_COMM_EXEC_HOLD 0x2 + +#define FEC_OC_COMM_MB__A 0x1C40002 +#define FEC_OC_COMM_MB__W 2 +#define FEC_OC_COMM_MB__M 0x3 +#define FEC_OC_COMM_MB__PRE 0x0 +#define FEC_OC_COMM_MB_CTL__B 0 +#define FEC_OC_COMM_MB_CTL__W 1 +#define FEC_OC_COMM_MB_CTL__M 0x1 +#define FEC_OC_COMM_MB_CTL__PRE 0x0 +#define FEC_OC_COMM_MB_CTL_OFF 0x0 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB_OBS__B 1 +#define FEC_OC_COMM_MB_OBS__W 1 +#define FEC_OC_COMM_MB_OBS__M 0x2 +#define FEC_OC_COMM_MB_OBS__PRE 0x0 +#define FEC_OC_COMM_MB_OBS_OFF 0x0 +#define FEC_OC_COMM_MB_OBS_ON 0x2 + +#define FEC_OC_COMM_INT_REQ__A 0x1C40003 +#define FEC_OC_COMM_INT_REQ__W 1 +#define FEC_OC_COMM_INT_REQ__M 0x1 +#define FEC_OC_COMM_INT_REQ__PRE 0x0 +#define FEC_OC_COMM_INT_STA__A 0x1C40005 +#define FEC_OC_COMM_INT_STA__W 8 +#define FEC_OC_COMM_INT_STA__M 0xFF +#define FEC_OC_COMM_INT_STA__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_MSK__A 0x1C40006 +#define FEC_OC_COMM_INT_MSK__W 8 +#define FEC_OC_COMM_INT_MSK__M 0xFF +#define FEC_OC_COMM_INT_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_COMM_INT_STM__A 0x1C40007 +#define FEC_OC_COMM_INT_STM__W 8 +#define FEC_OC_COMM_INT_STM__M 0xFF +#define FEC_OC_COMM_INT_STM__PRE 0x0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_STATUS__A 0x1C40010 +#define FEC_OC_STATUS__W 5 +#define FEC_OC_STATUS__M 0x1F +#define FEC_OC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_DPR_STATUS__B 0 +#define FEC_OC_STATUS_DPR_STATUS__W 1 +#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_SNC_STATUS__B 1 +#define FEC_OC_STATUS_SNC_STATUS__W 2 +#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 +#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0 +#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2 +#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4 + +#define FEC_OC_STATUS_FIFO_FULL__B 3 +#define FEC_OC_STATUS_FIFO_FULL__W 1 +#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 + +#define FEC_OC_MODE__A 0x1C40011 +#define FEC_OC_MODE__W 4 +#define FEC_OC_MODE__M 0xF +#define FEC_OC_MODE__PRE 0x0 + +#define FEC_OC_MODE_PARITY__B 0 +#define FEC_OC_MODE_PARITY__W 1 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE_PARITY__PRE 0x0 + +#define FEC_OC_MODE_TRANSPARENT__B 1 +#define FEC_OC_MODE_TRANSPARENT__W 1 +#define FEC_OC_MODE_TRANSPARENT__M 0x2 +#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 + +#define FEC_OC_MODE_CLEAR__B 2 +#define FEC_OC_MODE_CLEAR__W 1 +#define FEC_OC_MODE_CLEAR__M 0x4 +#define FEC_OC_MODE_CLEAR__PRE 0x0 + +#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 + +#define FEC_OC_DPR_MODE__A 0x1C40012 +#define FEC_OC_DPR_MODE__W 2 +#define FEC_OC_DPR_MODE__M 0x3 +#define FEC_OC_DPR_MODE__PRE 0x0 + +#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 + +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 + + +#define FEC_OC_DPR_UNLOCK__A 0x1C40013 +#define FEC_OC_DPR_UNLOCK__W 1 +#define FEC_OC_DPR_UNLOCK__M 0x1 +#define FEC_OC_DPR_UNLOCK__PRE 0x0 +#define FEC_OC_DTO_MODE__A 0x1C40014 +#define FEC_OC_DTO_MODE__W 3 +#define FEC_OC_DTO_MODE__M 0x7 +#define FEC_OC_DTO_MODE__PRE 0x0 + +#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 + +#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 + +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 + + +#define FEC_OC_DTO_PERIOD__A 0x1C40015 +#define FEC_OC_DTO_PERIOD__W 8 +#define FEC_OC_DTO_PERIOD__M 0xFF +#define FEC_OC_DTO_PERIOD__PRE 0x0 +#define FEC_OC_DTO_RATE_LO__A 0x1C40016 +#define FEC_OC_DTO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_HI__A 0x1C40017 +#define FEC_OC_DTO_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 +#define FEC_OC_DTO_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN__PRE 0xBC + +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC + +#define FEC_OC_FCT_MODE__A 0x1C4001A +#define FEC_OC_FCT_MODE__W 2 +#define FEC_OC_FCT_MODE__M 0x3 +#define FEC_OC_FCT_MODE__PRE 0x0 + +#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 + +#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 + +#define FEC_OC_FCT_USAGE__A 0x1C4001B +#define FEC_OC_FCT_USAGE__W 3 +#define FEC_OC_FCT_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE__PRE 0x7 + +#define FEC_OC_FCT_USAGE_USAGE__B 0 +#define FEC_OC_FCT_USAGE_USAGE__W 3 +#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7 + +#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C +#define FEC_OC_FCT_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION__PRE 0x0 + +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 + +#define FEC_OC_TMD_MODE__A 0x1C4001E +#define FEC_OC_TMD_MODE__W 3 +#define FEC_OC_TMD_MODE__M 0x7 +#define FEC_OC_TMD_MODE__PRE 0x4 + +#define FEC_OC_TMD_MODE_MODE__B 0 +#define FEC_OC_TMD_MODE_MODE__W 3 +#define FEC_OC_TMD_MODE_MODE__M 0x7 +#define FEC_OC_TMD_MODE_MODE__PRE 0x4 + +#define FEC_OC_TMD_COUNT__A 0x1C4001F +#define FEC_OC_TMD_COUNT__W 10 +#define FEC_OC_TMD_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_COUNT_COUNT__B 0 +#define FEC_OC_TMD_COUNT_COUNT__W 10 +#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 +#define FEC_OC_TMD_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN__PRE 0x500 + +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500 + +#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 +#define FEC_OC_TMD_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN__PRE 0x300 + +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300 + +#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022 +#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 + +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 + +#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 +#define FEC_OC_TMD_INT_UPD_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 + +#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 + +#define FEC_OC_AVR_PARM_A__A 0x1C40026 +#define FEC_OC_AVR_PARM_A__W 4 +#define FEC_OC_AVR_PARM_A__M 0xF +#define FEC_OC_AVR_PARM_A__PRE 0x6 + +#define FEC_OC_AVR_PARM_A_PARM__B 0 +#define FEC_OC_AVR_PARM_A_PARM__W 4 +#define FEC_OC_AVR_PARM_A_PARM__M 0xF +#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 + +#define FEC_OC_AVR_PARM_B__A 0x1C40027 +#define FEC_OC_AVR_PARM_B__W 4 +#define FEC_OC_AVR_PARM_B__M 0xF +#define FEC_OC_AVR_PARM_B__PRE 0x4 + +#define FEC_OC_AVR_PARM_B_PARM__B 0 +#define FEC_OC_AVR_PARM_B_PARM__W 4 +#define FEC_OC_AVR_PARM_B_PARM__M 0xF +#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 + +#define FEC_OC_AVR_AVG_LO__A 0x1C40028 +#define FEC_OC_AVR_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI__A 0x1C40029 +#define FEC_OC_AVR_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 + +#define FEC_OC_RCN_MODE__A 0x1C4002C +#define FEC_OC_RCN_MODE__W 5 +#define FEC_OC_RCN_MODE__M 0x1F +#define FEC_OC_RCN_MODE__PRE 0x1F + +#define FEC_OC_RCN_MODE_MODE__B 0 +#define FEC_OC_RCN_MODE_MODE__W 5 +#define FEC_OC_RCN_MODE_MODE__M 0x1F +#define FEC_OC_RCN_MODE_MODE__PRE 0x1F + +#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D +#define FEC_OC_RCN_OCC_SETTLE__W 11 +#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400 + +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400 + +#define FEC_OC_RCN_GAIN__A 0x1C4002E +#define FEC_OC_RCN_GAIN__W 4 +#define FEC_OC_RCN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN__PRE 0xC + +#define FEC_OC_RCN_GAIN_GAIN__B 0 +#define FEC_OC_RCN_GAIN_GAIN__W 4 +#define FEC_OC_RCN_GAIN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC + +#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 +#define FEC_OC_RCN_CTL_RATE_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031 +#define FEC_OC_RCN_CTL_RATE_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 +#define FEC_OC_RCN_CTL_STEP_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 +#define FEC_OC_RCN_CTL_STEP_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 + +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 + +#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034 +#define FEC_OC_RCN_DTO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035 +#define FEC_OC_RCN_DTO_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036 +#define FEC_OC_RCN_DTO_RATE_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037 +#define FEC_OC_RCN_DTO_RATE_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038 +#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039 +#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A +#define FEC_OC_RCN_DYN_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B +#define FEC_OC_RCN_DYN_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 + +#define FEC_OC_SNC_MODE__A 0x1C40040 +#define FEC_OC_SNC_MODE__W 5 +#define FEC_OC_SNC_MODE__M 0x1F +#define FEC_OC_SNC_MODE__PRE 0x0 + +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 + +#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_SHUTDOWN__B 4 +#define FEC_OC_SNC_MODE_SHUTDOWN__W 1 +#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0 + +#define FEC_OC_SNC_LWM__A 0x1C40041 +#define FEC_OC_SNC_LWM__W 4 +#define FEC_OC_SNC_LWM__M 0xF +#define FEC_OC_SNC_LWM__PRE 0x3 + +#define FEC_OC_SNC_LWM_MARK__B 0 +#define FEC_OC_SNC_LWM_MARK__W 4 +#define FEC_OC_SNC_LWM_MARK__M 0xF +#define FEC_OC_SNC_LWM_MARK__PRE 0x3 + +#define FEC_OC_SNC_HWM__A 0x1C40042 +#define FEC_OC_SNC_HWM__W 4 +#define FEC_OC_SNC_HWM__M 0xF +#define FEC_OC_SNC_HWM__PRE 0x5 + +#define FEC_OC_SNC_HWM_MARK__B 0 +#define FEC_OC_SNC_HWM_MARK__W 4 +#define FEC_OC_SNC_HWM_MARK__M 0xF +#define FEC_OC_SNC_HWM_MARK__PRE 0x5 + +#define FEC_OC_SNC_UNLOCK__A 0x1C40043 +#define FEC_OC_SNC_UNLOCK__W 1 +#define FEC_OC_SNC_UNLOCK__M 0x1 +#define FEC_OC_SNC_UNLOCK__PRE 0x0 + +#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044 +#define FEC_OC_SNC_LOCK_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045 +#define FEC_OC_SNC_FAIL_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 +#define FEC_OC_SNC_FAIL_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 + +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_OC_EMS_MODE__A 0x1C40047 +#define FEC_OC_EMS_MODE__W 2 +#define FEC_OC_EMS_MODE__M 0x3 +#define FEC_OC_EMS_MODE__PRE 0x0 + +#define FEC_OC_EMS_MODE_MODE__B 0 +#define FEC_OC_EMS_MODE_MODE__W 2 +#define FEC_OC_EMS_MODE_MODE__M 0x3 +#define FEC_OC_EMS_MODE_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE__A 0x1C40048 +#define FEC_OC_IPR_MODE__W 12 +#define FEC_OC_IPR_MODE__M 0xFFF +#define FEC_OC_IPR_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE_SERIAL__B 0 +#define FEC_OC_IPR_MODE_SERIAL__W 1 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 + +#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT__A 0x1C40049 +#define FEC_OC_IPR_INVERT__W 12 +#define FEC_OC_IPR_INVERT__M 0xFFF +#define FEC_OC_IPR_INVERT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MERR__B 8 +#define FEC_OC_IPR_INVERT_MERR__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MSTRT__B 9 +#define FEC_OC_IPR_INVERT_MSTRT__W 1 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MVAL__B 10 +#define FEC_OC_IPR_INVERT_MVAL__W 1 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MCLK__B 11 +#define FEC_OC_IPR_INVERT_MCLK__W 1 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 + +#define FEC_OC_OCR_MODE__A 0x1C40050 +#define FEC_OC_OCR_MODE__W 4 +#define FEC_OC_OCR_MODE__M 0xF +#define FEC_OC_OCR_MODE__PRE 0x0 + +#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 + +#define FEC_OC_OCR_RATE__A 0x1C40051 +#define FEC_OC_OCR_RATE__W 4 +#define FEC_OC_OCR_RATE__M 0xF +#define FEC_OC_OCR_RATE__PRE 0x0 + +#define FEC_OC_OCR_RATE_RATE__B 0 +#define FEC_OC_OCR_RATE_RATE__W 4 +#define FEC_OC_OCR_RATE_RATE__M 0xF +#define FEC_OC_OCR_RATE_RATE__PRE 0x0 + +#define FEC_OC_OCR_INVERT__A 0x1C40052 +#define FEC_OC_OCR_INVERT__W 12 +#define FEC_OC_OCR_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT__PRE 0x800 + +#define FEC_OC_OCR_INVERT_INVERT__B 0 +#define FEC_OC_OCR_INVERT_INVERT__W 12 +#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 + +#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053 +#define FEC_OC_OCR_GRAB_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054 +#define FEC_OC_OCR_GRAB_SYNC__W 8 +#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055 +#define FEC_OC_OCR_GRAB_RD0__W 10 +#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056 +#define FEC_OC_OCR_GRAB_RD1__W 10 +#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057 +#define FEC_OC_OCR_GRAB_RD2__W 10 +#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058 +#define FEC_OC_OCR_GRAB_RD3__W 10 +#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059 +#define FEC_OC_OCR_GRAB_RD4__W 10 +#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A +#define FEC_OC_OCR_GRAB_RD5__W 10 +#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 + + + +#define FEC_DI_RAM__A 0x1C50000 + + + +#define FEC_RS_RAM__A 0x1C60000 + + + +#define FEC_OC_RAM__A 0x1C70000 + + + + + +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__W 2 +#define IQM_COMM_EXEC__M 0x3 +#define IQM_COMM_EXEC__PRE 0x0 +#define IQM_COMM_EXEC_B__B 0 +#define IQM_COMM_EXEC_B__W 2 +#define IQM_COMM_EXEC_B__M 0x3 +#define IQM_COMM_EXEC_B__PRE 0x0 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC_B_ACTIVE 0x1 +#define IQM_COMM_EXEC_B_HOLD 0x2 + +#define IQM_COMM_MB__A 0x1800002 +#define IQM_COMM_MB__W 16 +#define IQM_COMM_MB__M 0xFFFF +#define IQM_COMM_MB__PRE 0x0 +#define IQM_COMM_MB_B__B 0 +#define IQM_COMM_MB_B__W 16 +#define IQM_COMM_MB_B__M 0xFFFF +#define IQM_COMM_MB_B__PRE 0x0 + +#define IQM_COMM_INT_REQ__A 0x1800003 +#define IQM_COMM_INT_REQ__W 3 +#define IQM_COMM_INT_REQ__M 0x7 +#define IQM_COMM_INT_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_AF_REQ__B 0 +#define IQM_COMM_INT_REQ_AF_REQ__W 1 +#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CF_REQ__B 1 +#define IQM_COMM_INT_REQ_CF_REQ__W 1 +#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CW_REQ__B 2 +#define IQM_COMM_INT_REQ_CW_REQ__W 1 +#define IQM_COMM_INT_REQ_CW_REQ__M 0x4 +#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0 + +#define IQM_COMM_INT_STA__A 0x1800005 +#define IQM_COMM_INT_STA__W 16 +#define IQM_COMM_INT_STA__M 0xFFFF +#define IQM_COMM_INT_STA__PRE 0x0 +#define IQM_COMM_INT_STA_B__B 0 +#define IQM_COMM_INT_STA_B__W 16 +#define IQM_COMM_INT_STA_B__M 0xFFFF +#define IQM_COMM_INT_STA_B__PRE 0x0 + +#define IQM_COMM_INT_MSK__A 0x1800006 +#define IQM_COMM_INT_MSK__W 16 +#define IQM_COMM_INT_MSK__M 0xFFFF +#define IQM_COMM_INT_MSK__PRE 0x0 +#define IQM_COMM_INT_MSK_B__B 0 +#define IQM_COMM_INT_MSK_B__W 16 +#define IQM_COMM_INT_MSK_B__M 0xFFFF +#define IQM_COMM_INT_MSK_B__PRE 0x0 + +#define IQM_COMM_INT_STM__A 0x1800007 +#define IQM_COMM_INT_STM__W 16 +#define IQM_COMM_INT_STM__M 0xFFFF +#define IQM_COMM_INT_STM__PRE 0x0 +#define IQM_COMM_INT_STM_B__B 0 +#define IQM_COMM_INT_STM_B__W 16 +#define IQM_COMM_INT_STM_B__M 0xFFFF +#define IQM_COMM_INT_STM_B__PRE 0x0 + + + +#define IQM_FS_COMM_EXEC__A 0x1820000 +#define IQM_FS_COMM_EXEC__W 2 +#define IQM_FS_COMM_EXEC__M 0x3 +#define IQM_FS_COMM_EXEC__PRE 0x0 +#define IQM_FS_COMM_EXEC_STOP 0x0 +#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +#define IQM_FS_COMM_EXEC_HOLD 0x2 + +#define IQM_FS_COMM_MB__A 0x1820002 +#define IQM_FS_COMM_MB__W 4 +#define IQM_FS_COMM_MB__M 0xF +#define IQM_FS_COMM_MB__PRE 0x0 +#define IQM_FS_COMM_MB_CTL__B 0 +#define IQM_FS_COMM_MB_CTL__W 1 +#define IQM_FS_COMM_MB_CTL__M 0x1 +#define IQM_FS_COMM_MB_CTL__PRE 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FS_COMM_MB_OBS__B 1 +#define IQM_FS_COMM_MB_OBS__W 1 +#define IQM_FS_COMM_MB_OBS__M 0x2 +#define IQM_FS_COMM_MB_OBS__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_FS_COMM_MB_CTL_MUX__B 2 +#define IQM_FS_COMM_MB_CTL_MUX__W 1 +#define IQM_FS_COMM_MB_CTL_MUX__M 0x4 +#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_MUX__B 3 +#define IQM_FS_COMM_MB_OBS_MUX__W 1 +#define IQM_FS_COMM_MB_OBS_MUX__M 0x8 +#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0 + +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_FS_RATE_OFS_LO__W 16 +#define IQM_FS_RATE_OFS_LO__M 0xFFFF +#define IQM_FS_RATE_OFS_LO__PRE 0x0 +#define IQM_FS_RATE_OFS_LO_B__B 0 +#define IQM_FS_RATE_OFS_LO_B__W 16 +#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF +#define IQM_FS_RATE_OFS_LO_B__PRE 0x0 + +#define IQM_FS_RATE_OFS_HI__A 0x1820011 +#define IQM_FS_RATE_OFS_HI__W 12 +#define IQM_FS_RATE_OFS_HI__M 0xFFF +#define IQM_FS_RATE_OFS_HI__PRE 0x0 +#define IQM_FS_RATE_OFS_HI_B__B 0 +#define IQM_FS_RATE_OFS_HI_B__W 12 +#define IQM_FS_RATE_OFS_HI_B__M 0xFFF +#define IQM_FS_RATE_OFS_HI_B__PRE 0x0 + +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_LO__W 16 +#define IQM_FS_RATE_LO__M 0xFFFF +#define IQM_FS_RATE_LO__PRE 0x0 +#define IQM_FS_RATE_LO_B__B 0 +#define IQM_FS_RATE_LO_B__W 16 +#define IQM_FS_RATE_LO_B__M 0xFFFF +#define IQM_FS_RATE_LO_B__PRE 0x0 + +#define IQM_FS_RATE_HI__A 0x1820013 +#define IQM_FS_RATE_HI__W 12 +#define IQM_FS_RATE_HI__M 0xFFF +#define IQM_FS_RATE_HI__PRE 0x0 +#define IQM_FS_RATE_HI_B__B 0 +#define IQM_FS_RATE_HI_B__W 12 +#define IQM_FS_RATE_HI_B__M 0xFFF +#define IQM_FS_RATE_HI_B__PRE 0x0 + +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_ADJ_SEL__W 2 +#define IQM_FS_ADJ_SEL__M 0x3 +#define IQM_FS_ADJ_SEL__PRE 0x0 + +#define IQM_FS_ADJ_SEL_B__B 0 +#define IQM_FS_ADJ_SEL_B__W 2 +#define IQM_FS_ADJ_SEL_B__M 0x3 +#define IQM_FS_ADJ_SEL_B__PRE 0x0 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 + + + +#define IQM_FD_COMM_EXEC__A 0x1830000 +#define IQM_FD_COMM_EXEC__W 2 +#define IQM_FD_COMM_EXEC__M 0x3 +#define IQM_FD_COMM_EXEC__PRE 0x0 +#define IQM_FD_COMM_EXEC_STOP 0x0 +#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +#define IQM_FD_COMM_EXEC_HOLD 0x2 + +#define IQM_FD_COMM_MB__A 0x1830002 +#define IQM_FD_COMM_MB__W 2 +#define IQM_FD_COMM_MB__M 0x3 +#define IQM_FD_COMM_MB__PRE 0x0 +#define IQM_FD_COMM_MB_CTL__B 0 +#define IQM_FD_COMM_MB_CTL__W 1 +#define IQM_FD_COMM_MB_CTL__M 0x1 +#define IQM_FD_COMM_MB_CTL__PRE 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FD_COMM_MB_OBS__B 1 +#define IQM_FD_COMM_MB_OBS__W 1 +#define IQM_FD_COMM_MB_OBS__M 0x2 +#define IQM_FD_COMM_MB_OBS__PRE 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_FD_RATESEL__A 0x1830010 +#define IQM_FD_RATESEL__W 2 +#define IQM_FD_RATESEL__M 0x3 +#define IQM_FD_RATESEL__PRE 0x0 +#define IQM_FD_RATESEL_B__B 0 +#define IQM_FD_RATESEL_B__W 2 +#define IQM_FD_RATESEL_B__M 0x3 +#define IQM_FD_RATESEL_B__PRE 0x0 +#define IQM_FD_RATESEL_B_DS0 0x0 +#define IQM_FD_RATESEL_B_DS1 0x1 +#define IQM_FD_RATESEL_B_DS2 0x2 +#define IQM_FD_RATESEL_B_DS3 0x3 + + + +#define IQM_RC_COMM_EXEC__A 0x1840000 +#define IQM_RC_COMM_EXEC__W 2 +#define IQM_RC_COMM_EXEC__M 0x3 +#define IQM_RC_COMM_EXEC__PRE 0x0 +#define IQM_RC_COMM_EXEC_STOP 0x0 +#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +#define IQM_RC_COMM_EXEC_HOLD 0x2 + +#define IQM_RC_COMM_MB__A 0x1840002 +#define IQM_RC_COMM_MB__W 2 +#define IQM_RC_COMM_MB__M 0x3 +#define IQM_RC_COMM_MB__PRE 0x0 +#define IQM_RC_COMM_MB_CTL__B 0 +#define IQM_RC_COMM_MB_CTL__W 1 +#define IQM_RC_COMM_MB_CTL__M 0x1 +#define IQM_RC_COMM_MB_CTL__PRE 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RC_COMM_MB_OBS__B 1 +#define IQM_RC_COMM_MB_OBS__W 1 +#define IQM_RC_COMM_MB_OBS__M 0x2 +#define IQM_RC_COMM_MB_OBS__PRE 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__PRE 0x0 +#define IQM_RC_RATE_OFS_LO_B__B 0 +#define IQM_RC_RATE_OFS_LO_B__W 16 +#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF +#define IQM_RC_RATE_OFS_LO_B__PRE 0x0 + +#define IQM_RC_RATE_OFS_HI__A 0x1840011 +#define IQM_RC_RATE_OFS_HI__W 8 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_HI__PRE 0x0 +#define IQM_RC_RATE_OFS_HI_B__B 0 +#define IQM_RC_RATE_OFS_HI_B__W 8 +#define IQM_RC_RATE_OFS_HI_B__M 0xFF +#define IQM_RC_RATE_OFS_HI_B__PRE 0x0 + +#define IQM_RC_RATE_LO__A 0x1840012 +#define IQM_RC_RATE_LO__W 16 +#define IQM_RC_RATE_LO__M 0xFFFF +#define IQM_RC_RATE_LO__PRE 0x0 +#define IQM_RC_RATE_LO_B__B 0 +#define IQM_RC_RATE_LO_B__W 16 +#define IQM_RC_RATE_LO_B__M 0xFFFF +#define IQM_RC_RATE_LO_B__PRE 0x0 + +#define IQM_RC_RATE_HI__A 0x1840013 +#define IQM_RC_RATE_HI__W 8 +#define IQM_RC_RATE_HI__M 0xFF +#define IQM_RC_RATE_HI__PRE 0x0 +#define IQM_RC_RATE_HI_B__B 0 +#define IQM_RC_RATE_HI_B__W 8 +#define IQM_RC_RATE_HI_B__M 0xFF +#define IQM_RC_RATE_HI_B__PRE 0x0 + +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_ADJ_SEL__W 2 +#define IQM_RC_ADJ_SEL__M 0x3 +#define IQM_RC_ADJ_SEL__PRE 0x0 + +#define IQM_RC_ADJ_SEL_B__B 0 +#define IQM_RC_ADJ_SEL_B__W 2 +#define IQM_RC_ADJ_SEL_B__M 0x3 +#define IQM_RC_ADJ_SEL_B__PRE 0x0 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 + +#define IQM_RC_CROUT_ENA__A 0x1840015 +#define IQM_RC_CROUT_ENA__W 1 +#define IQM_RC_CROUT_ENA__M 0x1 +#define IQM_RC_CROUT_ENA__PRE 0x0 + +#define IQM_RC_CROUT_ENA_ENA__B 0 +#define IQM_RC_CROUT_ENA_ENA__W 1 +#define IQM_RC_CROUT_ENA_ENA__M 0x1 +#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 + +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__W 5 +#define IQM_RC_STRETCH__M 0x1F +#define IQM_RC_STRETCH__PRE 0x0 + +#define IQM_RC_STRETCH_B__B 0 +#define IQM_RC_STRETCH_B__W 5 +#define IQM_RC_STRETCH_B__M 0x1F +#define IQM_RC_STRETCH_B__PRE 0x0 + + + +#define IQM_RT_COMM_EXEC__A 0x1850000 +#define IQM_RT_COMM_EXEC__W 2 +#define IQM_RT_COMM_EXEC__M 0x3 +#define IQM_RT_COMM_EXEC__PRE 0x0 +#define IQM_RT_COMM_EXEC_STOP 0x0 +#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +#define IQM_RT_COMM_EXEC_HOLD 0x2 + +#define IQM_RT_COMM_MB__A 0x1850002 +#define IQM_RT_COMM_MB__W 2 +#define IQM_RT_COMM_MB__M 0x3 +#define IQM_RT_COMM_MB__PRE 0x0 +#define IQM_RT_COMM_MB_CTL__B 0 +#define IQM_RT_COMM_MB_CTL__W 1 +#define IQM_RT_COMM_MB_CTL__M 0x1 +#define IQM_RT_COMM_MB_CTL__PRE 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RT_COMM_MB_OBS__B 1 +#define IQM_RT_COMM_MB_OBS__W 1 +#define IQM_RT_COMM_MB_OBS__M 0x2 +#define IQM_RT_COMM_MB_OBS__PRE 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RT_ACTIVE__A 0x1850010 +#define IQM_RT_ACTIVE__W 2 +#define IQM_RT_ACTIVE__M 0x3 +#define IQM_RT_ACTIVE__PRE 0x0 + +#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 + +#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 + + +#define IQM_RT_LO_INCR__A 0x1850011 +#define IQM_RT_LO_INCR__W 12 +#define IQM_RT_LO_INCR__M 0xFFF +#define IQM_RT_LO_INCR__PRE 0x588 +#define IQM_RT_LO_INCR_FM 0x0 +#define IQM_RT_LO_INCR_MN 0x588 + +#define IQM_RT_ROT_BP__A 0x1850012 +#define IQM_RT_ROT_BP__W 3 +#define IQM_RT_ROT_BP__M 0x7 +#define IQM_RT_ROT_BP__PRE 0x0 + +#define IQM_RT_ROT_BP_ROT_OFF__B 0 +#define IQM_RT_ROT_BP_ROT_OFF__W 1 +#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 + +#define IQM_RT_ROT_BP_ROT_BPF__B 1 +#define IQM_RT_ROT_BP_ROT_BPF__W 1 +#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 + +#define IQM_RT_ROT_BP_MIX_BP__B 2 +#define IQM_RT_ROT_BP_MIX_BP__W 1 +#define IQM_RT_ROT_BP_MIX_BP__M 0x4 +#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0 + + +#define IQM_RT_LP_BP__A 0x1850013 +#define IQM_RT_LP_BP__W 1 +#define IQM_RT_LP_BP__M 0x1 +#define IQM_RT_LP_BP__PRE 0x0 + +#define IQM_RT_DELAY__A 0x1850014 +#define IQM_RT_DELAY__W 7 +#define IQM_RT_DELAY__M 0x7F +#define IQM_RT_DELAY__PRE 0x45 + + + +#define IQM_CF_COMM_EXEC__A 0x1860000 +#define IQM_CF_COMM_EXEC__W 2 +#define IQM_CF_COMM_EXEC__M 0x3 +#define IQM_CF_COMM_EXEC__PRE 0x0 +#define IQM_CF_COMM_EXEC_STOP 0x0 +#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +#define IQM_CF_COMM_EXEC_HOLD 0x2 + +#define IQM_CF_COMM_MB__A 0x1860002 +#define IQM_CF_COMM_MB__W 2 +#define IQM_CF_COMM_MB__M 0x3 +#define IQM_CF_COMM_MB__PRE 0x0 +#define IQM_CF_COMM_MB_CTL__B 0 +#define IQM_CF_COMM_MB_CTL__W 1 +#define IQM_CF_COMM_MB_CTL__M 0x1 +#define IQM_CF_COMM_MB_CTL__PRE 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_CF_COMM_MB_OBS__B 1 +#define IQM_CF_COMM_MB_OBS__W 1 +#define IQM_CF_COMM_MB_OBS__M 0x2 +#define IQM_CF_COMM_MB_OBS__PRE 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_CF_COMM_INT_REQ__A 0x1860003 +#define IQM_CF_COMM_INT_REQ__W 1 +#define IQM_CF_COMM_INT_REQ__M 0x1 +#define IQM_CF_COMM_INT_REQ__PRE 0x0 +#define IQM_CF_COMM_INT_STA__A 0x1860005 +#define IQM_CF_COMM_INT_STA__W 2 +#define IQM_CF_COMM_INT_STA__M 0x3 +#define IQM_CF_COMM_INT_STA__PRE 0x0 +#define IQM_CF_COMM_INT_STA_PM__B 0 +#define IQM_CF_COMM_INT_STA_PM__W 1 +#define IQM_CF_COMM_INT_STA_PM__M 0x1 +#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 +#define IQM_CF_COMM_INT_STA_INC__B 1 +#define IQM_CF_COMM_INT_STA_INC__W 1 +#define IQM_CF_COMM_INT_STA_INC__M 0x2 +#define IQM_CF_COMM_INT_STA_INC__PRE 0x0 + +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_COMM_INT_MSK__W 2 +#define IQM_CF_COMM_INT_MSK__M 0x3 +#define IQM_CF_COMM_INT_MSK__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_PM__B 0 +#define IQM_CF_COMM_INT_MSK_PM__W 1 +#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_INC__B 1 +#define IQM_CF_COMM_INT_MSK_INC__W 1 +#define IQM_CF_COMM_INT_MSK_INC__M 0x2 +#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0 + +#define IQM_CF_COMM_INT_STM__A 0x1860007 +#define IQM_CF_COMM_INT_STM__W 2 +#define IQM_CF_COMM_INT_STM__M 0x3 +#define IQM_CF_COMM_INT_STM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_PM__B 0 +#define IQM_CF_COMM_INT_STM_PM__W 1 +#define IQM_CF_COMM_INT_STM_PM__M 0x1 +#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_INC__B 1 +#define IQM_CF_COMM_INT_STM_INC__W 1 +#define IQM_CF_COMM_INT_STM_INC__M 0x2 +#define IQM_CF_COMM_INT_STM_INC__PRE 0x0 + +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_SYMMETRIC__W 2 +#define IQM_CF_SYMMETRIC__M 0x3 +#define IQM_CF_SYMMETRIC__PRE 0x0 + +#define IQM_CF_SYMMETRIC_RE__B 0 +#define IQM_CF_SYMMETRIC_RE__W 1 +#define IQM_CF_SYMMETRIC_RE__M 0x1 +#define IQM_CF_SYMMETRIC_RE__PRE 0x0 + +#define IQM_CF_SYMMETRIC_IM__B 1 +#define IQM_CF_SYMMETRIC_IM__W 1 +#define IQM_CF_SYMMETRIC_IM__M 0x2 +#define IQM_CF_SYMMETRIC_IM__PRE 0x0 + +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_MIDTAP__W 3 +#define IQM_CF_MIDTAP__M 0x7 +#define IQM_CF_MIDTAP__PRE 0x3 + +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP_RE__W 1 +#define IQM_CF_MIDTAP_RE__M 0x1 +#define IQM_CF_MIDTAP_RE__PRE 0x1 + +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_IM__W 1 +#define IQM_CF_MIDTAP_IM__M 0x2 +#define IQM_CF_MIDTAP_IM__PRE 0x2 + +#define IQM_CF_MIDTAP_SCALE__B 2 +#define IQM_CF_MIDTAP_SCALE__W 1 +#define IQM_CF_MIDTAP_SCALE__M 0x4 +#define IQM_CF_MIDTAP_SCALE__PRE 0x0 + +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__W 3 +#define IQM_CF_OUT_ENA__M 0x7 +#define IQM_CF_OUT_ENA__PRE 0x0 + +#define IQM_CF_OUT_ENA_ATV__B 0 +#define IQM_CF_OUT_ENA_ATV__W 1 +#define IQM_CF_OUT_ENA_ATV__M 0x1 +#define IQM_CF_OUT_ENA_ATV__PRE 0x0 + +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA_QAM__W 1 +#define IQM_CF_OUT_ENA_QAM__M 0x2 +#define IQM_CF_OUT_ENA_QAM__PRE 0x0 + +#define IQM_CF_OUT_ENA_OFDM__B 2 +#define IQM_CF_OUT_ENA_OFDM__W 1 +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_CF_OUT_ENA_OFDM__PRE 0x0 + +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_ADJ_SEL__W 2 +#define IQM_CF_ADJ_SEL__M 0x3 +#define IQM_CF_ADJ_SEL__PRE 0x0 + +#define IQM_CF_ADJ_SEL_B__B 0 +#define IQM_CF_ADJ_SEL_B__W 2 +#define IQM_CF_ADJ_SEL_B__M 0x3 +#define IQM_CF_ADJ_SEL_B__PRE 0x0 + +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SCALE__W 14 +#define IQM_CF_SCALE__M 0x3FFF +#define IQM_CF_SCALE__PRE 0x400 +#define IQM_CF_SCALE_B__B 0 +#define IQM_CF_SCALE_B__W 14 +#define IQM_CF_SCALE_B__M 0x3FFF +#define IQM_CF_SCALE_B__PRE 0x400 + +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__W 2 +#define IQM_CF_SCALE_SH__M 0x3 +#define IQM_CF_SCALE_SH__PRE 0x0 + +#define IQM_CF_SCALE_SH_B__B 0 +#define IQM_CF_SCALE_SH_B__W 2 +#define IQM_CF_SCALE_SH_B__M 0x3 +#define IQM_CF_SCALE_SH_B__PRE 0x0 + +#define IQM_CF_AMP__A 0x1860016 +#define IQM_CF_AMP__W 14 +#define IQM_CF_AMP__M 0x3FFF +#define IQM_CF_AMP__PRE 0x0 + +#define IQM_CF_AMP_B__B 0 +#define IQM_CF_AMP_B__W 14 +#define IQM_CF_AMP_B__M 0x3FFF +#define IQM_CF_AMP_B__PRE 0x0 + +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__W 3 +#define IQM_CF_POW_MEAS_LEN__M 0x7 +#define IQM_CF_POW_MEAS_LEN__PRE 0x2 + +#define IQM_CF_POW_MEAS_LEN_B__B 0 +#define IQM_CF_POW_MEAS_LEN_B__W 3 +#define IQM_CF_POW_MEAS_LEN_B__M 0x7 +#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2 + +#define IQM_CF_POW__A 0x1860018 +#define IQM_CF_POW__W 16 +#define IQM_CF_POW__M 0xFFFF +#define IQM_CF_POW__PRE 0x2 +#define IQM_CF_POW_B__B 0 +#define IQM_CF_POW_B__W 16 +#define IQM_CF_POW_B__M 0xFFFF +#define IQM_CF_POW_B__PRE 0x2 + +#define IQM_CF_DS_ENA__A 0x1860019 +#define IQM_CF_DS_ENA__W 3 +#define IQM_CF_DS_ENA__M 0x7 +#define IQM_CF_DS_ENA__PRE 0x4 + +#define IQM_CF_DS_ENA_ATV__B 0 +#define IQM_CF_DS_ENA_ATV__W 1 +#define IQM_CF_DS_ENA_ATV__M 0x1 +#define IQM_CF_DS_ENA_ATV__PRE 0x0 + +#define IQM_CF_DS_ENA_QAM__B 1 +#define IQM_CF_DS_ENA_QAM__W 1 +#define IQM_CF_DS_ENA_QAM__M 0x2 +#define IQM_CF_DS_ENA_QAM__PRE 0x0 + +#define IQM_CF_DS_ENA_VSB__B 2 +#define IQM_CF_DS_ENA_VSB__W 1 +#define IQM_CF_DS_ENA_VSB__M 0x4 +#define IQM_CF_DS_ENA_VSB__PRE 0x4 + + +#define IQM_CF_POW_UPD__A 0x186001A +#define IQM_CF_POW_UPD__W 1 +#define IQM_CF_POW_UPD__M 0x1 +#define IQM_CF_POW_UPD__PRE 0x0 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE0_B__B 0 +#define IQM_CF_TAP_RE0_B__W 7 +#define IQM_CF_TAP_RE0_B__M 0x7F +#define IQM_CF_TAP_RE0_B__PRE 0x2 + +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE1_B__B 0 +#define IQM_CF_TAP_RE1_B__W 7 +#define IQM_CF_TAP_RE1_B__M 0x7F +#define IQM_CF_TAP_RE1_B__PRE 0x2 + +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE2_B__B 0 +#define IQM_CF_TAP_RE2_B__W 7 +#define IQM_CF_TAP_RE2_B__M 0x7F +#define IQM_CF_TAP_RE2_B__PRE 0x2 + +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE3_B__B 0 +#define IQM_CF_TAP_RE3_B__W 7 +#define IQM_CF_TAP_RE3_B__M 0x7F +#define IQM_CF_TAP_RE3_B__PRE 0x2 + +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE4_B__B 0 +#define IQM_CF_TAP_RE4_B__W 7 +#define IQM_CF_TAP_RE4_B__M 0x7F +#define IQM_CF_TAP_RE4_B__PRE 0x2 + +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE5_B__B 0 +#define IQM_CF_TAP_RE5_B__W 7 +#define IQM_CF_TAP_RE5_B__M 0x7F +#define IQM_CF_TAP_RE5_B__PRE 0x2 + +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE6_B__B 0 +#define IQM_CF_TAP_RE6_B__W 7 +#define IQM_CF_TAP_RE6_B__M 0x7F +#define IQM_CF_TAP_RE6_B__PRE 0x2 + +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE7_B__B 0 +#define IQM_CF_TAP_RE7_B__W 9 +#define IQM_CF_TAP_RE7_B__M 0x1FF +#define IQM_CF_TAP_RE7_B__PRE 0x2 + +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE8_B__B 0 +#define IQM_CF_TAP_RE8_B__W 9 +#define IQM_CF_TAP_RE8_B__M 0x1FF +#define IQM_CF_TAP_RE8_B__PRE 0x2 + +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE9_B__B 0 +#define IQM_CF_TAP_RE9_B__W 9 +#define IQM_CF_TAP_RE9_B__M 0x1FF +#define IQM_CF_TAP_RE9_B__PRE 0x2 + +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE10_B__B 0 +#define IQM_CF_TAP_RE10_B__W 9 +#define IQM_CF_TAP_RE10_B__M 0x1FF +#define IQM_CF_TAP_RE10_B__PRE 0x2 + +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE11_B__B 0 +#define IQM_CF_TAP_RE11_B__W 9 +#define IQM_CF_TAP_RE11_B__M 0x1FF +#define IQM_CF_TAP_RE11_B__PRE 0x2 + +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE12_B__B 0 +#define IQM_CF_TAP_RE12_B__W 9 +#define IQM_CF_TAP_RE12_B__M 0x1FF +#define IQM_CF_TAP_RE12_B__PRE 0x2 + +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE13_B__B 0 +#define IQM_CF_TAP_RE13_B__W 9 +#define IQM_CF_TAP_RE13_B__M 0x1FF +#define IQM_CF_TAP_RE13_B__PRE 0x2 + +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE14_B__B 0 +#define IQM_CF_TAP_RE14_B__W 9 +#define IQM_CF_TAP_RE14_B__M 0x1FF +#define IQM_CF_TAP_RE14_B__PRE 0x2 + +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE15_B__B 0 +#define IQM_CF_TAP_RE15_B__W 9 +#define IQM_CF_TAP_RE15_B__M 0x1FF +#define IQM_CF_TAP_RE15_B__PRE 0x2 + +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE16_B__B 0 +#define IQM_CF_TAP_RE16_B__W 9 +#define IQM_CF_TAP_RE16_B__M 0x1FF +#define IQM_CF_TAP_RE16_B__PRE 0x2 + +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE17_B__B 0 +#define IQM_CF_TAP_RE17_B__W 9 +#define IQM_CF_TAP_RE17_B__M 0x1FF +#define IQM_CF_TAP_RE17_B__PRE 0x2 + +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE18_B__B 0 +#define IQM_CF_TAP_RE18_B__W 9 +#define IQM_CF_TAP_RE18_B__M 0x1FF +#define IQM_CF_TAP_RE18_B__PRE 0x2 + +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE19_B__B 0 +#define IQM_CF_TAP_RE19_B__W 9 +#define IQM_CF_TAP_RE19_B__M 0x1FF +#define IQM_CF_TAP_RE19_B__PRE 0x2 + +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE20_B__B 0 +#define IQM_CF_TAP_RE20_B__W 9 +#define IQM_CF_TAP_RE20_B__M 0x1FF +#define IQM_CF_TAP_RE20_B__PRE 0x2 + +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE21_B__B 0 +#define IQM_CF_TAP_RE21_B__W 11 +#define IQM_CF_TAP_RE21_B__M 0x7FF +#define IQM_CF_TAP_RE21_B__PRE 0x2 + +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE22_B__B 0 +#define IQM_CF_TAP_RE22_B__W 11 +#define IQM_CF_TAP_RE22_B__M 0x7FF +#define IQM_CF_TAP_RE22_B__PRE 0x2 + +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE23_B__B 0 +#define IQM_CF_TAP_RE23_B__W 11 +#define IQM_CF_TAP_RE23_B__M 0x7FF +#define IQM_CF_TAP_RE23_B__PRE 0x2 + +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE24_B__B 0 +#define IQM_CF_TAP_RE24_B__W 11 +#define IQM_CF_TAP_RE24_B__M 0x7FF +#define IQM_CF_TAP_RE24_B__PRE 0x2 + +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE25_B__B 0 +#define IQM_CF_TAP_RE25_B__W 11 +#define IQM_CF_TAP_RE25_B__M 0x7FF +#define IQM_CF_TAP_RE25_B__PRE 0x2 + +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE26_B__B 0 +#define IQM_CF_TAP_RE26_B__W 11 +#define IQM_CF_TAP_RE26_B__M 0x7FF +#define IQM_CF_TAP_RE26_B__PRE 0x2 + +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_RE27_B__B 0 +#define IQM_CF_TAP_RE27_B__W 11 +#define IQM_CF_TAP_RE27_B__M 0x7FF +#define IQM_CF_TAP_RE27_B__PRE 0x2 + +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM0_B__B 0 +#define IQM_CF_TAP_IM0_B__W 7 +#define IQM_CF_TAP_IM0_B__M 0x7F +#define IQM_CF_TAP_IM0_B__PRE 0x2 + +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM1_B__B 0 +#define IQM_CF_TAP_IM1_B__W 7 +#define IQM_CF_TAP_IM1_B__M 0x7F +#define IQM_CF_TAP_IM1_B__PRE 0x2 + +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM2_B__B 0 +#define IQM_CF_TAP_IM2_B__W 7 +#define IQM_CF_TAP_IM2_B__M 0x7F +#define IQM_CF_TAP_IM2_B__PRE 0x2 + +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM3_B__B 0 +#define IQM_CF_TAP_IM3_B__W 7 +#define IQM_CF_TAP_IM3_B__M 0x7F +#define IQM_CF_TAP_IM3_B__PRE 0x2 + +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM4_B__B 0 +#define IQM_CF_TAP_IM4_B__W 7 +#define IQM_CF_TAP_IM4_B__M 0x7F +#define IQM_CF_TAP_IM4_B__PRE 0x2 + +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM5_B__B 0 +#define IQM_CF_TAP_IM5_B__W 7 +#define IQM_CF_TAP_IM5_B__M 0x7F +#define IQM_CF_TAP_IM5_B__PRE 0x2 + +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM6_B__B 0 +#define IQM_CF_TAP_IM6_B__W 7 +#define IQM_CF_TAP_IM6_B__M 0x7F +#define IQM_CF_TAP_IM6_B__PRE 0x2 + +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM7_B__B 0 +#define IQM_CF_TAP_IM7_B__W 9 +#define IQM_CF_TAP_IM7_B__M 0x1FF +#define IQM_CF_TAP_IM7_B__PRE 0x2 + +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM8_B__B 0 +#define IQM_CF_TAP_IM8_B__W 9 +#define IQM_CF_TAP_IM8_B__M 0x1FF +#define IQM_CF_TAP_IM8_B__PRE 0x2 + +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM9_B__B 0 +#define IQM_CF_TAP_IM9_B__W 9 +#define IQM_CF_TAP_IM9_B__M 0x1FF +#define IQM_CF_TAP_IM9_B__PRE 0x2 + +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM10_B__B 0 +#define IQM_CF_TAP_IM10_B__W 9 +#define IQM_CF_TAP_IM10_B__M 0x1FF +#define IQM_CF_TAP_IM10_B__PRE 0x2 + +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM11_B__B 0 +#define IQM_CF_TAP_IM11_B__W 9 +#define IQM_CF_TAP_IM11_B__M 0x1FF +#define IQM_CF_TAP_IM11_B__PRE 0x2 + +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM12_B__B 0 +#define IQM_CF_TAP_IM12_B__W 9 +#define IQM_CF_TAP_IM12_B__M 0x1FF +#define IQM_CF_TAP_IM12_B__PRE 0x2 + +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM13_B__B 0 +#define IQM_CF_TAP_IM13_B__W 9 +#define IQM_CF_TAP_IM13_B__M 0x1FF +#define IQM_CF_TAP_IM13_B__PRE 0x2 + +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM14_B__B 0 +#define IQM_CF_TAP_IM14_B__W 9 +#define IQM_CF_TAP_IM14_B__M 0x1FF +#define IQM_CF_TAP_IM14_B__PRE 0x2 + +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM15_B__B 0 +#define IQM_CF_TAP_IM15_B__W 9 +#define IQM_CF_TAP_IM15_B__M 0x1FF +#define IQM_CF_TAP_IM15_B__PRE 0x2 + +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM16_B__B 0 +#define IQM_CF_TAP_IM16_B__W 9 +#define IQM_CF_TAP_IM16_B__M 0x1FF +#define IQM_CF_TAP_IM16_B__PRE 0x2 + +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM17_B__B 0 +#define IQM_CF_TAP_IM17_B__W 9 +#define IQM_CF_TAP_IM17_B__M 0x1FF +#define IQM_CF_TAP_IM17_B__PRE 0x2 + +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM18_B__B 0 +#define IQM_CF_TAP_IM18_B__W 9 +#define IQM_CF_TAP_IM18_B__M 0x1FF +#define IQM_CF_TAP_IM18_B__PRE 0x2 + +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM19_B__B 0 +#define IQM_CF_TAP_IM19_B__W 9 +#define IQM_CF_TAP_IM19_B__M 0x1FF +#define IQM_CF_TAP_IM19_B__PRE 0x2 + +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM20_B__B 0 +#define IQM_CF_TAP_IM20_B__W 9 +#define IQM_CF_TAP_IM20_B__M 0x1FF +#define IQM_CF_TAP_IM20_B__PRE 0x2 + +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM21_B__B 0 +#define IQM_CF_TAP_IM21_B__W 11 +#define IQM_CF_TAP_IM21_B__M 0x7FF +#define IQM_CF_TAP_IM21_B__PRE 0x2 + +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM22_B__B 0 +#define IQM_CF_TAP_IM22_B__W 11 +#define IQM_CF_TAP_IM22_B__M 0x7FF +#define IQM_CF_TAP_IM22_B__PRE 0x2 + +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM23_B__B 0 +#define IQM_CF_TAP_IM23_B__W 11 +#define IQM_CF_TAP_IM23_B__M 0x7FF +#define IQM_CF_TAP_IM23_B__PRE 0x2 + +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM24_B__B 0 +#define IQM_CF_TAP_IM24_B__W 11 +#define IQM_CF_TAP_IM24_B__M 0x7FF +#define IQM_CF_TAP_IM24_B__PRE 0x2 + +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM25_B__B 0 +#define IQM_CF_TAP_IM25_B__W 11 +#define IQM_CF_TAP_IM25_B__M 0x7FF +#define IQM_CF_TAP_IM25_B__PRE 0x2 + +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM26_B__B 0 +#define IQM_CF_TAP_IM26_B__W 11 +#define IQM_CF_TAP_IM26_B__M 0x7FF +#define IQM_CF_TAP_IM26_B__PRE 0x2 + +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 +#define IQM_CF_TAP_IM27_B__B 0 +#define IQM_CF_TAP_IM27_B__W 11 +#define IQM_CF_TAP_IM27_B__M 0x7FF +#define IQM_CF_TAP_IM27_B__PRE 0x2 + + +#define IQM_CF_CLP_VAL__A 0x1860060 +#define IQM_CF_CLP_VAL__W 9 +#define IQM_CF_CLP_VAL__M 0x1FF +#define IQM_CF_CLP_VAL__PRE 0x3C + +#define IQM_CF_DATATH__A 0x1860061 +#define IQM_CF_DATATH__W 10 +#define IQM_CF_DATATH__M 0x3FF +#define IQM_CF_DATATH__PRE 0x180 + +#define IQM_CF_PKDTH__A 0x1860062 +#define IQM_CF_PKDTH__W 5 +#define IQM_CF_PKDTH__M 0x1F +#define IQM_CF_PKDTH__PRE 0x1 + +#define IQM_CF_WND_LEN__A 0x1860063 +#define IQM_CF_WND_LEN__W 4 +#define IQM_CF_WND_LEN__M 0xF +#define IQM_CF_WND_LEN__PRE 0x1 + +#define IQM_CF_DET_LCT__A 0x1860064 +#define IQM_CF_DET_LCT__W 1 +#define IQM_CF_DET_LCT__M 0x1 +#define IQM_CF_DET_LCT__PRE 0x1 + +#define IQM_CF_SNS_LEN__A 0x1860065 +#define IQM_CF_SNS_LEN__W 16 +#define IQM_CF_SNS_LEN__M 0xFFFF +#define IQM_CF_SNS_LEN__PRE 0x0 + +#define IQM_CF_SNS_SENSE__A 0x1860066 +#define IQM_CF_SNS_SENSE__W 16 +#define IQM_CF_SNS_SENSE__M 0xFFFF +#define IQM_CF_SNS_SENSE__PRE 0x0 + +#define IQM_CF_BYPASSDET__A 0x1860067 +#define IQM_CF_BYPASSDET__W 1 +#define IQM_CF_BYPASSDET__M 0x1 +#define IQM_CF_BYPASSDET__PRE 0x0 + +#define IQM_CF_UPD_ENA__A 0x1860068 +#define IQM_CF_UPD_ENA__W 1 +#define IQM_CF_UPD_ENA__M 0x1 +#define IQM_CF_UPD_ENA__PRE 0x0 +#define IQM_CF_UPD_ENA_DISABLE 0x0 +#define IQM_CF_UPD_ENA_ENABLE 0x1 + + + +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_COMM_EXEC__W 2 +#define IQM_AF_COMM_EXEC__M 0x3 +#define IQM_AF_COMM_EXEC__PRE 0x0 +#define IQM_AF_COMM_EXEC_STOP 0x0 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC_HOLD 0x2 + +#define IQM_AF_COMM_MB__A 0x1870002 +#define IQM_AF_COMM_MB__W 8 +#define IQM_AF_COMM_MB__M 0xFF +#define IQM_AF_COMM_MB__PRE 0x0 +#define IQM_AF_COMM_MB_CTL__B 0 +#define IQM_AF_COMM_MB_CTL__W 1 +#define IQM_AF_COMM_MB_CTL__M 0x1 +#define IQM_AF_COMM_MB_CTL__PRE 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_AF_COMM_MB_OBS__B 1 +#define IQM_AF_COMM_MB_OBS__W 1 +#define IQM_AF_COMM_MB_OBS__M 0x2 +#define IQM_AF_COMM_MB_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14 +#define IQM_AF_COMM_MB_MUX_OBS__B 5 +#define IQM_AF_COMM_MB_MUX_OBS__W 3 +#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 +#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0 + +#define IQM_AF_COMM_INT_REQ__A 0x1870003 +#define IQM_AF_COMM_INT_REQ__W 1 +#define IQM_AF_COMM_INT_REQ__M 0x1 +#define IQM_AF_COMM_INT_REQ__PRE 0x0 +#define IQM_AF_COMM_INT_STA__A 0x1870005 +#define IQM_AF_COMM_INT_STA__W 3 +#define IQM_AF_COMM_INT_STA__M 0x7 +#define IQM_AF_COMM_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0 + +#define IQM_AF_COMM_INT_MSK__A 0x1870006 +#define IQM_AF_COMM_INT_MSK__W 3 +#define IQM_AF_COMM_INT_MSK__M 0x7 +#define IQM_AF_COMM_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0 + +#define IQM_AF_COMM_INT_STM__A 0x1870007 +#define IQM_AF_COMM_INT_STM__W 3 +#define IQM_AF_COMM_INT_STM__M 0x7 +#define IQM_AF_COMM_INT_STM__PRE 0x0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0 + + +#define IQM_AF_FDB_SEL__A 0x1870010 +#define IQM_AF_FDB_SEL__W 2 +#define IQM_AF_FDB_SEL__M 0x3 +#define IQM_AF_FDB_SEL__PRE 0x0 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLKNEG__W 2 +#define IQM_AF_CLKNEG__M 0x3 +#define IQM_AF_CLKNEG__PRE 0x0 + +#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 + +#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 + + +#define IQM_AF_MON_IN_MUX__A 0x1870013 +#define IQM_AF_MON_IN_MUX__W 2 +#define IQM_AF_MON_IN_MUX__M 0x3 +#define IQM_AF_MON_IN_MUX__PRE 0x0 + +#define IQM_AF_MON_IN5__A 0x1870014 +#define IQM_AF_MON_IN5__W 10 +#define IQM_AF_MON_IN5__M 0x3FF +#define IQM_AF_MON_IN5__PRE 0x0 + +#define IQM_AF_MON_IN4__A 0x1870015 +#define IQM_AF_MON_IN4__W 10 +#define IQM_AF_MON_IN4__M 0x3FF +#define IQM_AF_MON_IN4__PRE 0x0 + +#define IQM_AF_MON_IN3__A 0x1870016 +#define IQM_AF_MON_IN3__W 10 +#define IQM_AF_MON_IN3__M 0x3FF +#define IQM_AF_MON_IN3__PRE 0x0 + +#define IQM_AF_MON_IN2__A 0x1870017 +#define IQM_AF_MON_IN2__W 10 +#define IQM_AF_MON_IN2__M 0x3FF +#define IQM_AF_MON_IN2__PRE 0x0 + +#define IQM_AF_MON_IN1__A 0x1870018 +#define IQM_AF_MON_IN1__W 10 +#define IQM_AF_MON_IN1__M 0x3FF +#define IQM_AF_MON_IN1__PRE 0x0 + +#define IQM_AF_MON_IN0__A 0x1870019 +#define IQM_AF_MON_IN0__W 10 +#define IQM_AF_MON_IN0__M 0x3FF +#define IQM_AF_MON_IN0__PRE 0x0 + +#define IQM_AF_MON_IN_VAL__A 0x187001A +#define IQM_AF_MON_IN_VAL__W 1 +#define IQM_AF_MON_IN_VAL__M 0x1 +#define IQM_AF_MON_IN_VAL__PRE 0x0 + +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__W 1 +#define IQM_AF_START_LOCK__M 0x1 +#define IQM_AF_START_LOCK__PRE 0x0 + +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 + +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 + +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 + +#define IQM_AF_SCU_PHASE__A 0x187001F +#define IQM_AF_SCU_PHASE__W 2 +#define IQM_AF_SCU_PHASE__M 0x3 +#define IQM_AF_SCU_PHASE__PRE 0x0 + +#define IQM_AF_SYNC_SEL__A 0x1870020 +#define IQM_AF_SYNC_SEL__W 2 +#define IQM_AF_SYNC_SEL__M 0x3 +#define IQM_AF_SYNC_SEL__PRE 0x0 +#define IQM_AF_ADC_CONF__A 0x1870021 +#define IQM_AF_ADC_CONF__W 4 +#define IQM_AF_ADC_CONF__M 0xF +#define IQM_AF_ADC_CONF__PRE 0x0 + +#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 + +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 + + +#define IQM_AF_CLP_CLIP__A 0x1870022 +#define IQM_AF_CLP_CLIP__W 16 +#define IQM_AF_CLP_CLIP__M 0xFFFF +#define IQM_AF_CLP_CLIP__PRE 0x0 + +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__W 16 +#define IQM_AF_CLP_LEN__M 0xFFFF +#define IQM_AF_CLP_LEN__PRE 0x0 + +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__W 9 +#define IQM_AF_CLP_TH__M 0x1FF +#define IQM_AF_CLP_TH__PRE 0x0 + +#define IQM_AF_DCF_BYPASS__A 0x1870025 +#define IQM_AF_DCF_BYPASS__W 1 +#define IQM_AF_DCF_BYPASS__M 0x1 +#define IQM_AF_DCF_BYPASS__PRE 0x0 +#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +#define IQM_AF_DCF_BYPASS_BYPASS 0x1 + + +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__W 16 +#define IQM_AF_SNS_LEN__M 0xFFFF +#define IQM_AF_SNS_LEN__PRE 0x0 + +#define IQM_AF_SNS_SENSE__A 0x1870027 +#define IQM_AF_SNS_SENSE__W 16 +#define IQM_AF_SNS_SENSE__M 0xFFFF +#define IQM_AF_SNS_SENSE__PRE 0x0 + +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_IF__W 15 +#define IQM_AF_AGC_IF__M 0x7FFF +#define IQM_AF_AGC_IF__PRE 0x0 + +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AGC_RF__W 15 +#define IQM_AF_AGC_RF__M 0x7FFF +#define IQM_AF_AGC_RF__PRE 0x0 + +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__W 5 +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PDREF__PRE 0x0 +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__W 6 +#define IQM_AF_STDBY__M 0x3F +#define IQM_AF_STDBY__PRE 0x3E + +#define IQM_AF_STDBY_STDBY_BIAS__B 0 +#define IQM_AF_STDBY_STDBY_BIAS__W 1 +#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 + +#define IQM_AF_STDBY_STDBY_ADC__B 1 +#define IQM_AF_STDBY_STDBY_ADC__W 1 +#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2 +#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 + +#define IQM_AF_STDBY_STDBY_AMP__B 2 +#define IQM_AF_STDBY_STDBY_AMP__W 1 +#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4 +#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 + +#define IQM_AF_STDBY_STDBY_PD__B 3 +#define IQM_AF_STDBY_STDBY_PD__W 1 +#define IQM_AF_STDBY_STDBY_PD__M 0x8 +#define IQM_AF_STDBY_STDBY_PD__PRE 0x8 +#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 + +#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 + +#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 + + +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__W 1 +#define IQM_AF_AMUX__M 0x1 +#define IQM_AF_AMUX__PRE 0x0 +#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +#define IQM_AF_AMUX_SIGNAL2ADC 0x1 + + +#define IQM_AF_TST_AFEMAIN__A 0x187002E +#define IQM_AF_TST_AFEMAIN__W 8 +#define IQM_AF_TST_AFEMAIN__M 0xFF +#define IQM_AF_TST_AFEMAIN__PRE 0x0 + +#define IQM_AF_UPD_SEL__A 0x187002F +#define IQM_AF_UPD_SEL__W 1 +#define IQM_AF_UPD_SEL__M 0x1 +#define IQM_AF_UPD_SEL__PRE 0x0 + +#define IQM_AF_INC_DATATH__A 0x1870030 +#define IQM_AF_INC_DATATH__W 9 +#define IQM_AF_INC_DATATH__M 0x1FF +#define IQM_AF_INC_DATATH__PRE 0x180 + +#define IQM_AF_INC_PKDTH__A 0x1870031 +#define IQM_AF_INC_PKDTH__W 5 +#define IQM_AF_INC_PKDTH__M 0x1F +#define IQM_AF_INC_PKDTH__PRE 0x3 + +#define IQM_AF_INC_WND_LEN__A 0x1870032 +#define IQM_AF_INC_WND_LEN__W 4 +#define IQM_AF_INC_WND_LEN__M 0xF +#define IQM_AF_INC_WND_LEN__PRE 0xA + +#define IQM_AF_INC_DLY__A 0x1870033 +#define IQM_AF_INC_DLY__W 7 +#define IQM_AF_INC_DLY__M 0x7F +#define IQM_AF_INC_DLY__PRE 0x14 + +#define IQM_AF_INC_LCT__A 0x1870034 +#define IQM_AF_INC_LCT__W 1 +#define IQM_AF_INC_LCT__M 0x1 +#define IQM_AF_INC_LCT__PRE 0x1 + +#define IQM_AF_INC_CLP_VAL__A 0x1870035 +#define IQM_AF_INC_CLP_VAL__W 9 +#define IQM_AF_INC_CLP_VAL__M 0x1FF +#define IQM_AF_INC_CLP_VAL__PRE 0x3C + +#define IQM_AF_INC_BYPASS__A 0x1870036 +#define IQM_AF_INC_BYPASS__W 1 +#define IQM_AF_INC_BYPASS__M 0x1 +#define IQM_AF_INC_BYPASS__PRE 0x1 + +#define IQM_AF_INC_MODE_SEL__A 0x1870037 +#define IQM_AF_INC_MODE_SEL__W 2 +#define IQM_AF_INC_MODE_SEL__M 0x3 +#define IQM_AF_INC_MODE_SEL__PRE 0x1 + +#define IQM_AF_INC_A_DLY__A 0x1870038 +#define IQM_AF_INC_A_DLY__W 6 +#define IQM_AF_INC_A_DLY__M 0x3F +#define IQM_AF_INC_A_DLY__PRE 0xF + +#define IQM_AF_ISNS_LEN__A 0x1870039 +#define IQM_AF_ISNS_LEN__W 16 +#define IQM_AF_ISNS_LEN__M 0xFFFF +#define IQM_AF_ISNS_LEN__PRE 0x0 + +#define IQM_AF_ISNS_SENSE__A 0x187003A +#define IQM_AF_ISNS_SENSE__W 16 +#define IQM_AF_ISNS_SENSE__M 0xFFFF +#define IQM_AF_ISNS_SENSE__PRE 0x0 +#define IQM_AF_CMP_STATE__A 0x187003B +#define IQM_AF_CMP_STATE__W 7 +#define IQM_AF_CMP_STATE__M 0x7F +#define IQM_AF_CMP_STATE__PRE 0x0 + +#define IQM_AF_CMP_STATE_STATE__B 0 +#define IQM_AF_CMP_STATE_STATE__W 2 +#define IQM_AF_CMP_STATE_STATE__M 0x3 +#define IQM_AF_CMP_STATE_STATE__PRE 0x0 + +#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2 +#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1 +#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4 +#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0 + +#define IQM_AF_CMP_STATE_FILTERGAIN__B 3 +#define IQM_AF_CMP_STATE_FILTERGAIN__W 2 +#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18 +#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18 + +#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5 +#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1 +#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20 +#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0 + +#define IQM_AF_CMP_STATE_SEG64__B 6 +#define IQM_AF_CMP_STATE_SEG64__W 1 +#define IQM_AF_CMP_STATE_SEG64__M 0x40 +#define IQM_AF_CMP_STATE_SEG64__PRE 0x0 +#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0 +#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40 + + +#define IQM_AF_CMP_DC_OUT__A 0x187003C +#define IQM_AF_CMP_DC_OUT__W 12 +#define IQM_AF_CMP_DC_OUT__M 0xFFF +#define IQM_AF_CMP_DC_OUT__PRE 0x0 +#define IQM_AF_CMP_DC_IN__A 0x187003D +#define IQM_AF_CMP_DC_IN__W 13 +#define IQM_AF_CMP_DC_IN__M 0x1FFF +#define IQM_AF_CMP_DC_IN__PRE 0x0 + +#define IQM_AF_CMP_DC_IN_DC__B 0 +#define IQM_AF_CMP_DC_IN_DC__W 12 +#define IQM_AF_CMP_DC_IN_DC__M 0xFFF +#define IQM_AF_CMP_DC_IN_DC__PRE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN__B 12 +#define IQM_AF_CMP_DC_IN_DC_EN__W 1 +#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000 +#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000 + + +#define IQM_AF_CMP_AMP__A 0x187003E +#define IQM_AF_CMP_AMP__W 10 +#define IQM_AF_CMP_AMP__M 0x3FF +#define IQM_AF_CMP_AMP__PRE 0x0 +#define IQM_AF_CMP_DN_AVG__A 0x187003F +#define IQM_AF_CMP_DN_AVG__W 8 +#define IQM_AF_CMP_DN_AVG__M 0xFF +#define IQM_AF_CMP_DN_AVG__PRE 0x0 + +#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0 +#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8 +#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF +#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0 + + +#define IQM_AF_CMP_ACTIVE__A 0x1870040 +#define IQM_AF_CMP_ACTIVE__W 1 +#define IQM_AF_CMP_ACTIVE__M 0x1 +#define IQM_AF_CMP_ACTIVE__PRE 0x0 +#define IQM_AF_CMP_MEM0__A 0x1870080 +#define IQM_AF_CMP_MEM0__W 13 +#define IQM_AF_CMP_MEM0__M 0x1FFF +#define IQM_AF_CMP_MEM0__PRE 0x0 + +#define IQM_AF_CMP_MEM0_COEF__B 0 +#define IQM_AF_CMP_MEM0_COEF__W 13 +#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM0_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM1__A 0x1870081 +#define IQM_AF_CMP_MEM1__W 13 +#define IQM_AF_CMP_MEM1__M 0x1FFF +#define IQM_AF_CMP_MEM1__PRE 0x0 + +#define IQM_AF_CMP_MEM1_COEF__B 0 +#define IQM_AF_CMP_MEM1_COEF__W 13 +#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM1_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM2__A 0x1870082 +#define IQM_AF_CMP_MEM2__W 13 +#define IQM_AF_CMP_MEM2__M 0x1FFF +#define IQM_AF_CMP_MEM2__PRE 0x0 + +#define IQM_AF_CMP_MEM2_COEF__B 0 +#define IQM_AF_CMP_MEM2_COEF__W 13 +#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM2_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM3__A 0x1870083 +#define IQM_AF_CMP_MEM3__W 13 +#define IQM_AF_CMP_MEM3__M 0x1FFF +#define IQM_AF_CMP_MEM3__PRE 0x0 + +#define IQM_AF_CMP_MEM3_COEF__B 0 +#define IQM_AF_CMP_MEM3_COEF__W 13 +#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM3_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM4__A 0x1870084 +#define IQM_AF_CMP_MEM4__W 13 +#define IQM_AF_CMP_MEM4__M 0x1FFF +#define IQM_AF_CMP_MEM4__PRE 0x0 + +#define IQM_AF_CMP_MEM4_COEF__B 0 +#define IQM_AF_CMP_MEM4_COEF__W 13 +#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM4_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM5__A 0x1870085 +#define IQM_AF_CMP_MEM5__W 13 +#define IQM_AF_CMP_MEM5__M 0x1FFF +#define IQM_AF_CMP_MEM5__PRE 0x0 + +#define IQM_AF_CMP_MEM5_COEF__B 0 +#define IQM_AF_CMP_MEM5_COEF__W 13 +#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM5_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM6__A 0x1870086 +#define IQM_AF_CMP_MEM6__W 13 +#define IQM_AF_CMP_MEM6__M 0x1FFF +#define IQM_AF_CMP_MEM6__PRE 0x0 + +#define IQM_AF_CMP_MEM6_COEF__B 0 +#define IQM_AF_CMP_MEM6_COEF__W 13 +#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM6_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM7__A 0x1870087 +#define IQM_AF_CMP_MEM7__W 13 +#define IQM_AF_CMP_MEM7__M 0x1FFF +#define IQM_AF_CMP_MEM7__PRE 0x0 + +#define IQM_AF_CMP_MEM7_COEF__B 0 +#define IQM_AF_CMP_MEM7_COEF__W 13 +#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM7_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM8__A 0x1870088 +#define IQM_AF_CMP_MEM8__W 13 +#define IQM_AF_CMP_MEM8__M 0x1FFF +#define IQM_AF_CMP_MEM8__PRE 0x0 + +#define IQM_AF_CMP_MEM8_COEF__B 0 +#define IQM_AF_CMP_MEM8_COEF__W 13 +#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM8_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM9__A 0x1870089 +#define IQM_AF_CMP_MEM9__W 13 +#define IQM_AF_CMP_MEM9__M 0x1FFF +#define IQM_AF_CMP_MEM9__PRE 0x0 + +#define IQM_AF_CMP_MEM9_COEF__B 0 +#define IQM_AF_CMP_MEM9_COEF__W 13 +#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM9_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM10__A 0x187008A +#define IQM_AF_CMP_MEM10__W 13 +#define IQM_AF_CMP_MEM10__M 0x1FFF +#define IQM_AF_CMP_MEM10__PRE 0x0 + +#define IQM_AF_CMP_MEM10_COEF__B 0 +#define IQM_AF_CMP_MEM10_COEF__W 13 +#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM10_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM11__A 0x187008B +#define IQM_AF_CMP_MEM11__W 13 +#define IQM_AF_CMP_MEM11__M 0x1FFF +#define IQM_AF_CMP_MEM11__PRE 0x0 + +#define IQM_AF_CMP_MEM11_COEF__B 0 +#define IQM_AF_CMP_MEM11_COEF__W 13 +#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM11_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM12__A 0x187008C +#define IQM_AF_CMP_MEM12__W 13 +#define IQM_AF_CMP_MEM12__M 0x1FFF +#define IQM_AF_CMP_MEM12__PRE 0x0 + +#define IQM_AF_CMP_MEM12_COEF__B 0 +#define IQM_AF_CMP_MEM12_COEF__W 13 +#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM12_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM13__A 0x187008D +#define IQM_AF_CMP_MEM13__W 13 +#define IQM_AF_CMP_MEM13__M 0x1FFF +#define IQM_AF_CMP_MEM13__PRE 0x0 + +#define IQM_AF_CMP_MEM13_COEF__B 0 +#define IQM_AF_CMP_MEM13_COEF__W 13 +#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM13_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM14__A 0x187008E +#define IQM_AF_CMP_MEM14__W 13 +#define IQM_AF_CMP_MEM14__M 0x1FFF +#define IQM_AF_CMP_MEM14__PRE 0x0 + +#define IQM_AF_CMP_MEM14_COEF__B 0 +#define IQM_AF_CMP_MEM14_COEF__W 13 +#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM14_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM15__A 0x187008F +#define IQM_AF_CMP_MEM15__W 13 +#define IQM_AF_CMP_MEM15__M 0x1FFF +#define IQM_AF_CMP_MEM15__PRE 0x0 + +#define IQM_AF_CMP_MEM15_COEF__B 0 +#define IQM_AF_CMP_MEM15_COEF__W 13 +#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM15_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM16__A 0x1870090 +#define IQM_AF_CMP_MEM16__W 13 +#define IQM_AF_CMP_MEM16__M 0x1FFF +#define IQM_AF_CMP_MEM16__PRE 0x0 + +#define IQM_AF_CMP_MEM16_COEF__B 0 +#define IQM_AF_CMP_MEM16_COEF__W 13 +#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM16_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM17__A 0x1870091 +#define IQM_AF_CMP_MEM17__W 13 +#define IQM_AF_CMP_MEM17__M 0x1FFF +#define IQM_AF_CMP_MEM17__PRE 0x0 + +#define IQM_AF_CMP_MEM17_COEF__B 0 +#define IQM_AF_CMP_MEM17_COEF__W 13 +#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM17_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM18__A 0x1870092 +#define IQM_AF_CMP_MEM18__W 13 +#define IQM_AF_CMP_MEM18__M 0x1FFF +#define IQM_AF_CMP_MEM18__PRE 0x0 + +#define IQM_AF_CMP_MEM18_COEF__B 0 +#define IQM_AF_CMP_MEM18_COEF__W 13 +#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM18_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM19__A 0x1870093 +#define IQM_AF_CMP_MEM19__W 13 +#define IQM_AF_CMP_MEM19__M 0x1FFF +#define IQM_AF_CMP_MEM19__PRE 0x0 + +#define IQM_AF_CMP_MEM19_COEF__B 0 +#define IQM_AF_CMP_MEM19_COEF__W 13 +#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM19_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM20__A 0x1870094 +#define IQM_AF_CMP_MEM20__W 13 +#define IQM_AF_CMP_MEM20__M 0x1FFF +#define IQM_AF_CMP_MEM20__PRE 0x0 + +#define IQM_AF_CMP_MEM20_COEF__B 0 +#define IQM_AF_CMP_MEM20_COEF__W 13 +#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM20_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM21__A 0x1870095 +#define IQM_AF_CMP_MEM21__W 13 +#define IQM_AF_CMP_MEM21__M 0x1FFF +#define IQM_AF_CMP_MEM21__PRE 0x0 + +#define IQM_AF_CMP_MEM21_COEF__B 0 +#define IQM_AF_CMP_MEM21_COEF__W 13 +#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM21_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM22__A 0x1870096 +#define IQM_AF_CMP_MEM22__W 13 +#define IQM_AF_CMP_MEM22__M 0x1FFF +#define IQM_AF_CMP_MEM22__PRE 0x0 + +#define IQM_AF_CMP_MEM22_COEF__B 0 +#define IQM_AF_CMP_MEM22_COEF__W 13 +#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM22_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM23__A 0x1870097 +#define IQM_AF_CMP_MEM23__W 13 +#define IQM_AF_CMP_MEM23__M 0x1FFF +#define IQM_AF_CMP_MEM23__PRE 0x0 + +#define IQM_AF_CMP_MEM23_COEF__B 0 +#define IQM_AF_CMP_MEM23_COEF__W 13 +#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM23_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM24__A 0x1870098 +#define IQM_AF_CMP_MEM24__W 13 +#define IQM_AF_CMP_MEM24__M 0x1FFF +#define IQM_AF_CMP_MEM24__PRE 0x0 + +#define IQM_AF_CMP_MEM24_COEF__B 0 +#define IQM_AF_CMP_MEM24_COEF__W 13 +#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM24_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM25__A 0x1870099 +#define IQM_AF_CMP_MEM25__W 13 +#define IQM_AF_CMP_MEM25__M 0x1FFF +#define IQM_AF_CMP_MEM25__PRE 0x0 + +#define IQM_AF_CMP_MEM25_COEF__B 0 +#define IQM_AF_CMP_MEM25_COEF__W 13 +#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM25_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM26__A 0x187009A +#define IQM_AF_CMP_MEM26__W 13 +#define IQM_AF_CMP_MEM26__M 0x1FFF +#define IQM_AF_CMP_MEM26__PRE 0x0 + +#define IQM_AF_CMP_MEM26_COEF__B 0 +#define IQM_AF_CMP_MEM26_COEF__W 13 +#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM26_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM27__A 0x187009B +#define IQM_AF_CMP_MEM27__W 13 +#define IQM_AF_CMP_MEM27__M 0x1FFF +#define IQM_AF_CMP_MEM27__PRE 0x0 + +#define IQM_AF_CMP_MEM27_COEF__B 0 +#define IQM_AF_CMP_MEM27_COEF__W 13 +#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM27_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM28__A 0x187009C +#define IQM_AF_CMP_MEM28__W 13 +#define IQM_AF_CMP_MEM28__M 0x1FFF +#define IQM_AF_CMP_MEM28__PRE 0x0 + +#define IQM_AF_CMP_MEM28_COEF__B 0 +#define IQM_AF_CMP_MEM28_COEF__W 13 +#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM28_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM29__A 0x187009D +#define IQM_AF_CMP_MEM29__W 13 +#define IQM_AF_CMP_MEM29__M 0x1FFF +#define IQM_AF_CMP_MEM29__PRE 0x0 + +#define IQM_AF_CMP_MEM29_COEF__B 0 +#define IQM_AF_CMP_MEM29_COEF__W 13 +#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM29_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM30__A 0x187009E +#define IQM_AF_CMP_MEM30__W 13 +#define IQM_AF_CMP_MEM30__M 0x1FFF +#define IQM_AF_CMP_MEM30__PRE 0x0 + +#define IQM_AF_CMP_MEM30_COEF__B 0 +#define IQM_AF_CMP_MEM30_COEF__W 13 +#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM30_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM31__A 0x187009F +#define IQM_AF_CMP_MEM31__W 13 +#define IQM_AF_CMP_MEM31__M 0x1FFF +#define IQM_AF_CMP_MEM31__PRE 0x0 + +#define IQM_AF_CMP_MEM31_COEF__B 0 +#define IQM_AF_CMP_MEM31_COEF__W 13 +#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM31_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM32__A 0x18700A0 +#define IQM_AF_CMP_MEM32__W 13 +#define IQM_AF_CMP_MEM32__M 0x1FFF +#define IQM_AF_CMP_MEM32__PRE 0x0 + +#define IQM_AF_CMP_MEM32_COEF__B 0 +#define IQM_AF_CMP_MEM32_COEF__W 13 +#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM32_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM33__A 0x18700A1 +#define IQM_AF_CMP_MEM33__W 13 +#define IQM_AF_CMP_MEM33__M 0x1FFF +#define IQM_AF_CMP_MEM33__PRE 0x0 + +#define IQM_AF_CMP_MEM33_COEF__B 0 +#define IQM_AF_CMP_MEM33_COEF__W 13 +#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM33_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM34__A 0x18700A2 +#define IQM_AF_CMP_MEM34__W 13 +#define IQM_AF_CMP_MEM34__M 0x1FFF +#define IQM_AF_CMP_MEM34__PRE 0x0 + +#define IQM_AF_CMP_MEM34_COEF__B 0 +#define IQM_AF_CMP_MEM34_COEF__W 13 +#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM34_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM35__A 0x18700A3 +#define IQM_AF_CMP_MEM35__W 13 +#define IQM_AF_CMP_MEM35__M 0x1FFF +#define IQM_AF_CMP_MEM35__PRE 0x0 + +#define IQM_AF_CMP_MEM35_COEF__B 0 +#define IQM_AF_CMP_MEM35_COEF__W 13 +#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM35_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM36__A 0x18700A4 +#define IQM_AF_CMP_MEM36__W 13 +#define IQM_AF_CMP_MEM36__M 0x1FFF +#define IQM_AF_CMP_MEM36__PRE 0x0 + +#define IQM_AF_CMP_MEM36_COEF__B 0 +#define IQM_AF_CMP_MEM36_COEF__W 13 +#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM36_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM37__A 0x18700A5 +#define IQM_AF_CMP_MEM37__W 13 +#define IQM_AF_CMP_MEM37__M 0x1FFF +#define IQM_AF_CMP_MEM37__PRE 0x0 + +#define IQM_AF_CMP_MEM37_COEF__B 0 +#define IQM_AF_CMP_MEM37_COEF__W 13 +#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM37_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM38__A 0x18700A6 +#define IQM_AF_CMP_MEM38__W 13 +#define IQM_AF_CMP_MEM38__M 0x1FFF +#define IQM_AF_CMP_MEM38__PRE 0x0 + +#define IQM_AF_CMP_MEM38_COEF__B 0 +#define IQM_AF_CMP_MEM38_COEF__W 13 +#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM38_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM39__A 0x18700A7 +#define IQM_AF_CMP_MEM39__W 13 +#define IQM_AF_CMP_MEM39__M 0x1FFF +#define IQM_AF_CMP_MEM39__PRE 0x0 + +#define IQM_AF_CMP_MEM39_COEF__B 0 +#define IQM_AF_CMP_MEM39_COEF__W 13 +#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM39_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM40__A 0x18700A8 +#define IQM_AF_CMP_MEM40__W 13 +#define IQM_AF_CMP_MEM40__M 0x1FFF +#define IQM_AF_CMP_MEM40__PRE 0x0 + +#define IQM_AF_CMP_MEM40_COEF__B 0 +#define IQM_AF_CMP_MEM40_COEF__W 13 +#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM40_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM41__A 0x18700A9 +#define IQM_AF_CMP_MEM41__W 13 +#define IQM_AF_CMP_MEM41__M 0x1FFF +#define IQM_AF_CMP_MEM41__PRE 0x0 + +#define IQM_AF_CMP_MEM41_COEF__B 0 +#define IQM_AF_CMP_MEM41_COEF__W 13 +#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM41_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM42__A 0x18700AA +#define IQM_AF_CMP_MEM42__W 13 +#define IQM_AF_CMP_MEM42__M 0x1FFF +#define IQM_AF_CMP_MEM42__PRE 0x0 + +#define IQM_AF_CMP_MEM42_COEF__B 0 +#define IQM_AF_CMP_MEM42_COEF__W 13 +#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM42_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM43__A 0x18700AB +#define IQM_AF_CMP_MEM43__W 13 +#define IQM_AF_CMP_MEM43__M 0x1FFF +#define IQM_AF_CMP_MEM43__PRE 0x0 + +#define IQM_AF_CMP_MEM43_COEF__B 0 +#define IQM_AF_CMP_MEM43_COEF__W 13 +#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM43_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM44__A 0x18700AC +#define IQM_AF_CMP_MEM44__W 13 +#define IQM_AF_CMP_MEM44__M 0x1FFF +#define IQM_AF_CMP_MEM44__PRE 0x0 + +#define IQM_AF_CMP_MEM44_COEF__B 0 +#define IQM_AF_CMP_MEM44_COEF__W 13 +#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM44_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM45__A 0x18700AD +#define IQM_AF_CMP_MEM45__W 13 +#define IQM_AF_CMP_MEM45__M 0x1FFF +#define IQM_AF_CMP_MEM45__PRE 0x0 + +#define IQM_AF_CMP_MEM45_COEF__B 0 +#define IQM_AF_CMP_MEM45_COEF__W 13 +#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM45_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM46__A 0x18700AE +#define IQM_AF_CMP_MEM46__W 13 +#define IQM_AF_CMP_MEM46__M 0x1FFF +#define IQM_AF_CMP_MEM46__PRE 0x0 + +#define IQM_AF_CMP_MEM46_COEF__B 0 +#define IQM_AF_CMP_MEM46_COEF__W 13 +#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM46_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM47__A 0x18700AF +#define IQM_AF_CMP_MEM47__W 13 +#define IQM_AF_CMP_MEM47__M 0x1FFF +#define IQM_AF_CMP_MEM47__PRE 0x0 + +#define IQM_AF_CMP_MEM47_COEF__B 0 +#define IQM_AF_CMP_MEM47_COEF__W 13 +#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM47_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM48__A 0x18700B0 +#define IQM_AF_CMP_MEM48__W 13 +#define IQM_AF_CMP_MEM48__M 0x1FFF +#define IQM_AF_CMP_MEM48__PRE 0x0 + +#define IQM_AF_CMP_MEM48_COEF__B 0 +#define IQM_AF_CMP_MEM48_COEF__W 13 +#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM48_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM49__A 0x18700B1 +#define IQM_AF_CMP_MEM49__W 13 +#define IQM_AF_CMP_MEM49__M 0x1FFF +#define IQM_AF_CMP_MEM49__PRE 0x0 + +#define IQM_AF_CMP_MEM49_COEF__B 0 +#define IQM_AF_CMP_MEM49_COEF__W 13 +#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM49_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM50__A 0x18700B2 +#define IQM_AF_CMP_MEM50__W 13 +#define IQM_AF_CMP_MEM50__M 0x1FFF +#define IQM_AF_CMP_MEM50__PRE 0x0 + +#define IQM_AF_CMP_MEM50_COEF__B 0 +#define IQM_AF_CMP_MEM50_COEF__W 13 +#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM50_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM51__A 0x18700B3 +#define IQM_AF_CMP_MEM51__W 13 +#define IQM_AF_CMP_MEM51__M 0x1FFF +#define IQM_AF_CMP_MEM51__PRE 0x0 + +#define IQM_AF_CMP_MEM51_COEF__B 0 +#define IQM_AF_CMP_MEM51_COEF__W 13 +#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM51_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM52__A 0x18700B4 +#define IQM_AF_CMP_MEM52__W 13 +#define IQM_AF_CMP_MEM52__M 0x1FFF +#define IQM_AF_CMP_MEM52__PRE 0x0 + +#define IQM_AF_CMP_MEM52_COEF__B 0 +#define IQM_AF_CMP_MEM52_COEF__W 13 +#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM52_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM53__A 0x18700B5 +#define IQM_AF_CMP_MEM53__W 13 +#define IQM_AF_CMP_MEM53__M 0x1FFF +#define IQM_AF_CMP_MEM53__PRE 0x0 + +#define IQM_AF_CMP_MEM53_COEF__B 0 +#define IQM_AF_CMP_MEM53_COEF__W 13 +#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM53_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM54__A 0x18700B6 +#define IQM_AF_CMP_MEM54__W 13 +#define IQM_AF_CMP_MEM54__M 0x1FFF +#define IQM_AF_CMP_MEM54__PRE 0x0 + +#define IQM_AF_CMP_MEM54_COEF__B 0 +#define IQM_AF_CMP_MEM54_COEF__W 13 +#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM54_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM55__A 0x18700B7 +#define IQM_AF_CMP_MEM55__W 13 +#define IQM_AF_CMP_MEM55__M 0x1FFF +#define IQM_AF_CMP_MEM55__PRE 0x0 + +#define IQM_AF_CMP_MEM55_COEF__B 0 +#define IQM_AF_CMP_MEM55_COEF__W 13 +#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM55_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM56__A 0x18700B8 +#define IQM_AF_CMP_MEM56__W 13 +#define IQM_AF_CMP_MEM56__M 0x1FFF +#define IQM_AF_CMP_MEM56__PRE 0x0 + +#define IQM_AF_CMP_MEM56_COEF__B 0 +#define IQM_AF_CMP_MEM56_COEF__W 13 +#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM56_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM57__A 0x18700B9 +#define IQM_AF_CMP_MEM57__W 13 +#define IQM_AF_CMP_MEM57__M 0x1FFF +#define IQM_AF_CMP_MEM57__PRE 0x0 + +#define IQM_AF_CMP_MEM57_COEF__B 0 +#define IQM_AF_CMP_MEM57_COEF__W 13 +#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM57_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM58__A 0x18700BA +#define IQM_AF_CMP_MEM58__W 13 +#define IQM_AF_CMP_MEM58__M 0x1FFF +#define IQM_AF_CMP_MEM58__PRE 0x0 + +#define IQM_AF_CMP_MEM58_COEF__B 0 +#define IQM_AF_CMP_MEM58_COEF__W 13 +#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM58_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM59__A 0x18700BB +#define IQM_AF_CMP_MEM59__W 13 +#define IQM_AF_CMP_MEM59__M 0x1FFF +#define IQM_AF_CMP_MEM59__PRE 0x0 + +#define IQM_AF_CMP_MEM59_COEF__B 0 +#define IQM_AF_CMP_MEM59_COEF__W 13 +#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM59_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM60__A 0x18700BC +#define IQM_AF_CMP_MEM60__W 13 +#define IQM_AF_CMP_MEM60__M 0x1FFF +#define IQM_AF_CMP_MEM60__PRE 0x0 + +#define IQM_AF_CMP_MEM60_COEF__B 0 +#define IQM_AF_CMP_MEM60_COEF__W 13 +#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM60_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM61__A 0x18700BD +#define IQM_AF_CMP_MEM61__W 13 +#define IQM_AF_CMP_MEM61__M 0x1FFF +#define IQM_AF_CMP_MEM61__PRE 0x0 + +#define IQM_AF_CMP_MEM61_COEF__B 0 +#define IQM_AF_CMP_MEM61_COEF__W 13 +#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM61_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM62__A 0x18700BE +#define IQM_AF_CMP_MEM62__W 13 +#define IQM_AF_CMP_MEM62__M 0x1FFF +#define IQM_AF_CMP_MEM62__PRE 0x0 + +#define IQM_AF_CMP_MEM62_COEF__B 0 +#define IQM_AF_CMP_MEM62_COEF__W 13 +#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM62_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM63__A 0x18700BF +#define IQM_AF_CMP_MEM63__W 13 +#define IQM_AF_CMP_MEM63__M 0x1FFF +#define IQM_AF_CMP_MEM63__PRE 0x0 + +#define IQM_AF_CMP_MEM63_COEF__B 0 +#define IQM_AF_CMP_MEM63_COEF__W 13 +#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM63_COEF__PRE 0x0 + + + +#define IQM_RT_RAM__A 0x1880000 + +#define IQM_RT_RAM_DLY__B 0 +#define IQM_RT_RAM_DLY__W 13 +#define IQM_RT_RAM_DLY__M 0x1FFF +#define IQM_RT_RAM_DLY__PRE 0x0 + + + + + +#define OFDM_CE_COMM_EXEC__A 0x2C00000 +#define OFDM_CE_COMM_EXEC__W 3 +#define OFDM_CE_COMM_EXEC__M 0x7 +#define OFDM_CE_COMM_EXEC__PRE 0x0 +#define OFDM_CE_COMM_EXEC_STOP 0x0 +#define OFDM_CE_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_COMM_EXEC_STEP 0x3 +#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_CE_COMM_STATE__A 0x2C00001 +#define OFDM_CE_COMM_STATE__W 16 +#define OFDM_CE_COMM_STATE__M 0xFFFF +#define OFDM_CE_COMM_STATE__PRE 0x0 +#define OFDM_CE_COMM_MB__A 0x2C00002 +#define OFDM_CE_COMM_MB__W 16 +#define OFDM_CE_COMM_MB__M 0xFFFF +#define OFDM_CE_COMM_MB__PRE 0x0 +#define OFDM_CE_COMM_INT_REQ__A 0x2C00004 +#define OFDM_CE_COMM_INT_REQ__W 16 +#define OFDM_CE_COMM_INT_REQ__M 0xFFFF +#define OFDM_CE_COMM_INT_REQ__PRE 0x0 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_CE_COMM_INT_STA__A 0x2C00005 +#define OFDM_CE_COMM_INT_STA__W 16 +#define OFDM_CE_COMM_INT_STA__M 0xFFFF +#define OFDM_CE_COMM_INT_STA__PRE 0x0 +#define OFDM_CE_COMM_INT_MSK__A 0x2C00006 +#define OFDM_CE_COMM_INT_MSK__W 16 +#define OFDM_CE_COMM_INT_MSK__M 0xFFFF +#define OFDM_CE_COMM_INT_MSK__PRE 0x0 +#define OFDM_CE_COMM_INT_STM__A 0x2C00007 +#define OFDM_CE_COMM_INT_STM__W 16 +#define OFDM_CE_COMM_INT_STM__M 0xFFFF +#define OFDM_CE_COMM_INT_STM__PRE 0x0 +#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000 +#define OFDM_CE_TOP_COMM_EXEC__W 3 +#define OFDM_CE_TOP_COMM_EXEC__M 0x7 +#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_CE_TOP_COMM_MB__A 0x2C10002 +#define OFDM_CE_TOP_COMM_MB__W 4 +#define OFDM_CE_TOP_COMM_MB__M 0xF +#define OFDM_CE_TOP_COMM_MB__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL__B 0 +#define OFDM_CE_TOP_COMM_MB_CTL__W 1 +#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_CE_TOP_COMM_MB_OBS__B 1 +#define OFDM_CE_TOP_COMM_MB_OBS__W 1 +#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC + +#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004 +#define OFDM_CE_TOP_COMM_INT_REQ__W 1 +#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005 +#define OFDM_CE_TOP_COMM_INT_STA__W 3 +#define OFDM_CE_TOP_COMM_INT_STA__M 0x7 +#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0 + +#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006 +#define OFDM_CE_TOP_COMM_INT_MSK__W 3 +#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7 +#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0 + +#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007 +#define OFDM_CE_TOP_COMM_INT_STM__W 3 +#define OFDM_CE_TOP_COMM_INT_STM__M 0x7 +#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0 + + +#define OFDM_CE_TOP_MODE_2K__A 0x2C10010 +#define OFDM_CE_TOP_MODE_2K__W 1 +#define OFDM_CE_TOP_MODE_2K__M 0x1 +#define OFDM_CE_TOP_MODE_2K__PRE 0x0 + +#define OFDM_CE_TOP_TAPSET__A 0x2C10011 +#define OFDM_CE_TOP_TAPSET__W 4 +#define OFDM_CE_TOP_TAPSET__M 0xF +#define OFDM_CE_TOP_TAPSET__PRE 0x1 +#define OFDM_CE_TOP_AVG_POW__A 0x2C10012 +#define OFDM_CE_TOP_AVG_POW__W 8 +#define OFDM_CE_TOP_AVG_POW__M 0xFF +#define OFDM_CE_TOP_AVG_POW__PRE 0x65 +#define OFDM_CE_TOP_MAX_POW__A 0x2C10013 +#define OFDM_CE_TOP_MAX_POW__W 8 +#define OFDM_CE_TOP_MAX_POW__M 0xFF +#define OFDM_CE_TOP_MAX_POW__PRE 0x80 +#define OFDM_CE_TOP_ATT__A 0x2C10014 +#define OFDM_CE_TOP_ATT__W 8 +#define OFDM_CE_TOP_ATT__M 0xFF +#define OFDM_CE_TOP_ATT__PRE 0x70 +#define OFDM_CE_TOP_NRED__A 0x2C10015 +#define OFDM_CE_TOP_NRED__W 6 +#define OFDM_CE_TOP_NRED__M 0x3F +#define OFDM_CE_TOP_NRED__PRE 0x9 + +#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020 +#define OFDM_CE_TOP_PU_SIGN__W 1 +#define OFDM_CE_TOP_PU_SIGN__M 0x1 +#define OFDM_CE_TOP_PU_SIGN__PRE 0x0 + +#define OFDM_CE_TOP_PU_MIX__A 0x2C10021 +#define OFDM_CE_TOP_PU_MIX__W 1 +#define OFDM_CE_TOP_PU_MIX__M 0x1 +#define OFDM_CE_TOP_PU_MIX__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030 +#define OFDM_CE_TOP_PB_PILOT_REQ__W 15 +#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF +#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0 + + +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0 + +#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032 +#define OFDM_CE_TOP_PB_FREEZE__W 1 +#define OFDM_CE_TOP_PB_FREEZE__M 0x1 +#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038 +#define OFDM_CE_TOP_PB_PILOT_EXP__W 4 +#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF +#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039 +#define OFDM_CE_TOP_PB_PILOT_REAL__W 10 +#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF +#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A +#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10 +#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF +#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0 + +#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B +#define OFDM_CE_TOP_PB_SMBNR__W 5 +#define OFDM_CE_TOP_PB_SMBNR__M 0x1F +#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0 + +#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040 +#define OFDM_CE_TOP_NE_PILOT_REQ__W 12 +#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF +#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0 + + +#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042 +#define OFDM_CE_TOP_NE_PILOT_DATA__W 10 +#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF +#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0 +#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043 +#define OFDM_CE_TOP_NE_ERR_SELECT__W 5 +#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F +#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7 + +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0 + +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0 + +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4 + +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2 + +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1 + + +#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044 +#define OFDM_CE_TOP_NE_TD_CAL__W 9 +#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF +#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8 + +#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045 +#define OFDM_CE_TOP_NE_FD_CAL__W 9 +#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF +#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9 + +#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046 +#define OFDM_CE_TOP_NE_MIXAVG__W 3 +#define OFDM_CE_TOP_NE_MIXAVG__M 0x7 +#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6 + +#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047 +#define OFDM_CE_TOP_NE_NUPD_OFS__W 4 +#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF +#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4 +#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048 +#define OFDM_CE_TOP_NE_TD_POW__W 15 +#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF +#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0 + +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0 +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10 +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049 +#define OFDM_CE_TOP_NE_FD_POW__W 15 +#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF +#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0 +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10 +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0 + + +#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A +#define OFDM_CE_TOP_NE_NEXP_AVG__W 8 +#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF +#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0 + +#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B +#define OFDM_CE_TOP_NE_OFFSET__W 9 +#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF +#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0 + +#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C +#define OFDM_CE_TOP_NE_NUPD_TRH__W 5 +#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F +#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14 + +#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050 +#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8 +#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF +#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0 + +#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051 +#define OFDM_CE_TOP_PE_TIMESHIFT__W 14 +#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF +#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052 +#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16 +#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053 +#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16 +#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054 +#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16 +#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055 +#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16 +#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056 +#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16 +#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057 +#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16 +#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058 +#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16 +#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059 +#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16 +#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A +#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5 +#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F +#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B +#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5 +#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F +#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0 + +#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060 +#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1 +#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1 +#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0 + +#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064 +#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100 + +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066 +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5 +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE + +#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067 +#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068 +#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5 +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA + +#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B +#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0 +#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C +#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0 + + +#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072 +#define OFDM_CE_TOP_TI_SYM_CNT__W 6 +#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F +#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20 + +#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073 +#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1 +#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1 +#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1 + +#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074 +#define OFDM_CE_TOP_TI_SHIFT__W 2 +#define OFDM_CE_TOP_TI_SHIFT__M 0x3 +#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0 + +#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075 +#define OFDM_CE_TOP_TI_SLOW__W 1 +#define OFDM_CE_TOP_TI_SLOW__M 0x1 +#define OFDM_CE_TOP_TI_SLOW__PRE 0x1 + +#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076 +#define OFDM_CE_TOP_TI_MGAIN__W 8 +#define OFDM_CE_TOP_TI_MGAIN__M 0xFF +#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0 + +#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077 +#define OFDM_CE_TOP_TI_ACCU1__W 8 +#define OFDM_CE_TOP_TI_ACCU1__M 0xFF +#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0 + +#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0 +#define OFDM_CE_TOP_NI_PER_LEFT__W 5 +#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F +#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE + +#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1 +#define OFDM_CE_TOP_NI_PER_RIGHT__W 5 +#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F +#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7 + +#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2 +#define OFDM_CE_TOP_NI_POS_LR__W 9 +#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF +#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0 + +#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090 +#define OFDM_CE_TOP_FI_SHT_INCR__W 9 +#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF +#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E + +#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091 +#define OFDM_CE_TOP_FI_EXP_NORM__W 4 +#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF +#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC + +#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092 +#define OFDM_CE_TOP_FI_SUPR_VAL__W 1 +#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1 +#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0 + +#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0 +#define OFDM_CE_TOP_IR_INPUTSEL__W 1 +#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1 +#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0 + +#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1 +#define OFDM_CE_TOP_IR_STARTPOS__W 8 +#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF +#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0 + +#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2 +#define OFDM_CE_TOP_IR_NEXP_THRES__W 8 +#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF +#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF + +#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3 +#define OFDM_CE_TOP_IR_LENGTH__W 4 +#define OFDM_CE_TOP_IR_LENGTH__M 0xF +#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9 + +#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4 +#define OFDM_CE_TOP_IR_FREQ__W 11 +#define OFDM_CE_TOP_IR_FREQ__M 0x7FF +#define OFDM_CE_TOP_IR_FREQ__PRE 0x0 + +#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5 +#define OFDM_CE_TOP_IR_FREQINC__W 11 +#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF +#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4 + +#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6 +#define OFDM_CE_TOP_IR_KAISINC__W 15 +#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF +#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100 + +#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7 +#define OFDM_CE_TOP_IR_CTL__W 3 +#define OFDM_CE_TOP_IR_CTL__M 0x7 +#define OFDM_CE_TOP_IR_CTL__PRE 0x0 + +#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8 +#define OFDM_CE_TOP_IR_REAL__W 16 +#define OFDM_CE_TOP_IR_REAL__M 0xFFFF +#define OFDM_CE_TOP_IR_REAL__PRE 0x0 + +#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9 +#define OFDM_CE_TOP_IR_IMAG__W 16 +#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF +#define OFDM_CE_TOP_IR_IMAG__PRE 0x0 + +#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA +#define OFDM_CE_TOP_IR_INDEX__W 12 +#define OFDM_CE_TOP_IR_INDEX__M 0xFFF +#define OFDM_CE_TOP_IR_INDEX__PRE 0x0 + + + +#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000 +#define OFDM_CE_FR_COMM_EXEC__W 3 +#define OFDM_CE_FR_COMM_EXEC__M 0x7 +#define OFDM_CE_FR_COMM_EXEC__PRE 0x0 +#define OFDM_CE_FR_COMM_EXEC_STOP 0x0 +#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_FR_COMM_EXEC_STEP 0x3 + + +#define OFDM_CE_FR_TREAL00__A 0x2C20010 +#define OFDM_CE_FR_TREAL00__W 11 +#define OFDM_CE_FR_TREAL00__M 0x7FF +#define OFDM_CE_FR_TREAL00__PRE 0x52 + +#define OFDM_CE_FR_TIMAG00__A 0x2C20011 +#define OFDM_CE_FR_TIMAG00__W 11 +#define OFDM_CE_FR_TIMAG00__M 0x7FF +#define OFDM_CE_FR_TIMAG00__PRE 0x0 + +#define OFDM_CE_FR_TREAL01__A 0x2C20012 +#define OFDM_CE_FR_TREAL01__W 11 +#define OFDM_CE_FR_TREAL01__M 0x7FF +#define OFDM_CE_FR_TREAL01__PRE 0x52 + +#define OFDM_CE_FR_TIMAG01__A 0x2C20013 +#define OFDM_CE_FR_TIMAG01__W 11 +#define OFDM_CE_FR_TIMAG01__M 0x7FF +#define OFDM_CE_FR_TIMAG01__PRE 0x0 + +#define OFDM_CE_FR_TREAL02__A 0x2C20014 +#define OFDM_CE_FR_TREAL02__W 11 +#define OFDM_CE_FR_TREAL02__M 0x7FF +#define OFDM_CE_FR_TREAL02__PRE 0x52 + +#define OFDM_CE_FR_TIMAG02__A 0x2C20015 +#define OFDM_CE_FR_TIMAG02__W 11 +#define OFDM_CE_FR_TIMAG02__M 0x7FF +#define OFDM_CE_FR_TIMAG02__PRE 0x0 + +#define OFDM_CE_FR_TREAL03__A 0x2C20016 +#define OFDM_CE_FR_TREAL03__W 11 +#define OFDM_CE_FR_TREAL03__M 0x7FF +#define OFDM_CE_FR_TREAL03__PRE 0x52 + +#define OFDM_CE_FR_TIMAG03__A 0x2C20017 +#define OFDM_CE_FR_TIMAG03__W 11 +#define OFDM_CE_FR_TIMAG03__M 0x7FF +#define OFDM_CE_FR_TIMAG03__PRE 0x0 + +#define OFDM_CE_FR_TREAL04__A 0x2C20018 +#define OFDM_CE_FR_TREAL04__W 11 +#define OFDM_CE_FR_TREAL04__M 0x7FF +#define OFDM_CE_FR_TREAL04__PRE 0x52 + +#define OFDM_CE_FR_TIMAG04__A 0x2C20019 +#define OFDM_CE_FR_TIMAG04__W 11 +#define OFDM_CE_FR_TIMAG04__M 0x7FF +#define OFDM_CE_FR_TIMAG04__PRE 0x0 + +#define OFDM_CE_FR_TREAL05__A 0x2C2001A +#define OFDM_CE_FR_TREAL05__W 11 +#define OFDM_CE_FR_TREAL05__M 0x7FF +#define OFDM_CE_FR_TREAL05__PRE 0x52 + +#define OFDM_CE_FR_TIMAG05__A 0x2C2001B +#define OFDM_CE_FR_TIMAG05__W 11 +#define OFDM_CE_FR_TIMAG05__M 0x7FF +#define OFDM_CE_FR_TIMAG05__PRE 0x0 + +#define OFDM_CE_FR_TREAL06__A 0x2C2001C +#define OFDM_CE_FR_TREAL06__W 11 +#define OFDM_CE_FR_TREAL06__M 0x7FF +#define OFDM_CE_FR_TREAL06__PRE 0x52 + +#define OFDM_CE_FR_TIMAG06__A 0x2C2001D +#define OFDM_CE_FR_TIMAG06__W 11 +#define OFDM_CE_FR_TIMAG06__M 0x7FF +#define OFDM_CE_FR_TIMAG06__PRE 0x0 + +#define OFDM_CE_FR_TREAL07__A 0x2C2001E +#define OFDM_CE_FR_TREAL07__W 11 +#define OFDM_CE_FR_TREAL07__M 0x7FF +#define OFDM_CE_FR_TREAL07__PRE 0x52 + +#define OFDM_CE_FR_TIMAG07__A 0x2C2001F +#define OFDM_CE_FR_TIMAG07__W 11 +#define OFDM_CE_FR_TIMAG07__M 0x7FF +#define OFDM_CE_FR_TIMAG07__PRE 0x0 + +#define OFDM_CE_FR_TREAL08__A 0x2C20020 +#define OFDM_CE_FR_TREAL08__W 11 +#define OFDM_CE_FR_TREAL08__M 0x7FF +#define OFDM_CE_FR_TREAL08__PRE 0x52 + +#define OFDM_CE_FR_TIMAG08__A 0x2C20021 +#define OFDM_CE_FR_TIMAG08__W 11 +#define OFDM_CE_FR_TIMAG08__M 0x7FF +#define OFDM_CE_FR_TIMAG08__PRE 0x0 + +#define OFDM_CE_FR_TREAL09__A 0x2C20022 +#define OFDM_CE_FR_TREAL09__W 11 +#define OFDM_CE_FR_TREAL09__M 0x7FF +#define OFDM_CE_FR_TREAL09__PRE 0x52 + +#define OFDM_CE_FR_TIMAG09__A 0x2C20023 +#define OFDM_CE_FR_TIMAG09__W 11 +#define OFDM_CE_FR_TIMAG09__M 0x7FF +#define OFDM_CE_FR_TIMAG09__PRE 0x0 + +#define OFDM_CE_FR_TREAL10__A 0x2C20024 +#define OFDM_CE_FR_TREAL10__W 11 +#define OFDM_CE_FR_TREAL10__M 0x7FF +#define OFDM_CE_FR_TREAL10__PRE 0x52 + +#define OFDM_CE_FR_TIMAG10__A 0x2C20025 +#define OFDM_CE_FR_TIMAG10__W 11 +#define OFDM_CE_FR_TIMAG10__M 0x7FF +#define OFDM_CE_FR_TIMAG10__PRE 0x0 + +#define OFDM_CE_FR_TREAL11__A 0x2C20026 +#define OFDM_CE_FR_TREAL11__W 11 +#define OFDM_CE_FR_TREAL11__M 0x7FF +#define OFDM_CE_FR_TREAL11__PRE 0x52 + +#define OFDM_CE_FR_TIMAG11__A 0x2C20027 +#define OFDM_CE_FR_TIMAG11__W 11 +#define OFDM_CE_FR_TIMAG11__M 0x7FF +#define OFDM_CE_FR_TIMAG11__PRE 0x0 + +#define OFDM_CE_FR_MID_TAP__A 0x2C20028 +#define OFDM_CE_FR_MID_TAP__W 11 +#define OFDM_CE_FR_MID_TAP__M 0x7FF +#define OFDM_CE_FR_MID_TAP__PRE 0x51 + +#define OFDM_CE_FR_SQS_G00__A 0x2C20029 +#define OFDM_CE_FR_SQS_G00__W 8 +#define OFDM_CE_FR_SQS_G00__M 0xFF +#define OFDM_CE_FR_SQS_G00__PRE 0xB + +#define OFDM_CE_FR_SQS_G01__A 0x2C2002A +#define OFDM_CE_FR_SQS_G01__W 8 +#define OFDM_CE_FR_SQS_G01__M 0xFF +#define OFDM_CE_FR_SQS_G01__PRE 0xB + +#define OFDM_CE_FR_SQS_G02__A 0x2C2002B +#define OFDM_CE_FR_SQS_G02__W 8 +#define OFDM_CE_FR_SQS_G02__M 0xFF +#define OFDM_CE_FR_SQS_G02__PRE 0xB + +#define OFDM_CE_FR_SQS_G03__A 0x2C2002C +#define OFDM_CE_FR_SQS_G03__W 8 +#define OFDM_CE_FR_SQS_G03__M 0xFF +#define OFDM_CE_FR_SQS_G03__PRE 0xB + +#define OFDM_CE_FR_SQS_G04__A 0x2C2002D +#define OFDM_CE_FR_SQS_G04__W 8 +#define OFDM_CE_FR_SQS_G04__M 0xFF +#define OFDM_CE_FR_SQS_G04__PRE 0xB + +#define OFDM_CE_FR_SQS_G05__A 0x2C2002E +#define OFDM_CE_FR_SQS_G05__W 8 +#define OFDM_CE_FR_SQS_G05__M 0xFF +#define OFDM_CE_FR_SQS_G05__PRE 0xB + +#define OFDM_CE_FR_SQS_G06__A 0x2C2002F +#define OFDM_CE_FR_SQS_G06__W 8 +#define OFDM_CE_FR_SQS_G06__M 0xFF +#define OFDM_CE_FR_SQS_G06__PRE 0xB + +#define OFDM_CE_FR_SQS_G07__A 0x2C20030 +#define OFDM_CE_FR_SQS_G07__W 8 +#define OFDM_CE_FR_SQS_G07__M 0xFF +#define OFDM_CE_FR_SQS_G07__PRE 0xB + +#define OFDM_CE_FR_SQS_G08__A 0x2C20031 +#define OFDM_CE_FR_SQS_G08__W 8 +#define OFDM_CE_FR_SQS_G08__M 0xFF +#define OFDM_CE_FR_SQS_G08__PRE 0xB + +#define OFDM_CE_FR_SQS_G09__A 0x2C20032 +#define OFDM_CE_FR_SQS_G09__W 8 +#define OFDM_CE_FR_SQS_G09__M 0xFF +#define OFDM_CE_FR_SQS_G09__PRE 0xB + +#define OFDM_CE_FR_SQS_G10__A 0x2C20033 +#define OFDM_CE_FR_SQS_G10__W 8 +#define OFDM_CE_FR_SQS_G10__M 0xFF +#define OFDM_CE_FR_SQS_G10__PRE 0xB + +#define OFDM_CE_FR_SQS_G11__A 0x2C20034 +#define OFDM_CE_FR_SQS_G11__W 8 +#define OFDM_CE_FR_SQS_G11__M 0xFF +#define OFDM_CE_FR_SQS_G11__PRE 0xB + +#define OFDM_CE_FR_SQS_G12__A 0x2C20035 +#define OFDM_CE_FR_SQS_G12__W 8 +#define OFDM_CE_FR_SQS_G12__M 0xFF +#define OFDM_CE_FR_SQS_G12__PRE 0x5 + +#define OFDM_CE_FR_RIO_G00__A 0x2C20036 +#define OFDM_CE_FR_RIO_G00__W 9 +#define OFDM_CE_FR_RIO_G00__M 0x1FF +#define OFDM_CE_FR_RIO_G00__PRE 0x1FF + +#define OFDM_CE_FR_RIO_G01__A 0x2C20037 +#define OFDM_CE_FR_RIO_G01__W 9 +#define OFDM_CE_FR_RIO_G01__M 0x1FF +#define OFDM_CE_FR_RIO_G01__PRE 0x190 + +#define OFDM_CE_FR_RIO_G02__A 0x2C20038 +#define OFDM_CE_FR_RIO_G02__W 9 +#define OFDM_CE_FR_RIO_G02__M 0x1FF +#define OFDM_CE_FR_RIO_G02__PRE 0x10B + +#define OFDM_CE_FR_RIO_G03__A 0x2C20039 +#define OFDM_CE_FR_RIO_G03__W 9 +#define OFDM_CE_FR_RIO_G03__M 0x1FF +#define OFDM_CE_FR_RIO_G03__PRE 0xC8 + +#define OFDM_CE_FR_RIO_G04__A 0x2C2003A +#define OFDM_CE_FR_RIO_G04__W 9 +#define OFDM_CE_FR_RIO_G04__M 0x1FF +#define OFDM_CE_FR_RIO_G04__PRE 0xA0 + +#define OFDM_CE_FR_RIO_G05__A 0x2C2003B +#define OFDM_CE_FR_RIO_G05__W 9 +#define OFDM_CE_FR_RIO_G05__M 0x1FF +#define OFDM_CE_FR_RIO_G05__PRE 0x85 + +#define OFDM_CE_FR_RIO_G06__A 0x2C2003C +#define OFDM_CE_FR_RIO_G06__W 9 +#define OFDM_CE_FR_RIO_G06__M 0x1FF +#define OFDM_CE_FR_RIO_G06__PRE 0x72 + +#define OFDM_CE_FR_RIO_G07__A 0x2C2003D +#define OFDM_CE_FR_RIO_G07__W 9 +#define OFDM_CE_FR_RIO_G07__M 0x1FF +#define OFDM_CE_FR_RIO_G07__PRE 0x64 + +#define OFDM_CE_FR_RIO_G08__A 0x2C2003E +#define OFDM_CE_FR_RIO_G08__W 9 +#define OFDM_CE_FR_RIO_G08__M 0x1FF +#define OFDM_CE_FR_RIO_G08__PRE 0x59 + +#define OFDM_CE_FR_RIO_G09__A 0x2C2003F +#define OFDM_CE_FR_RIO_G09__W 9 +#define OFDM_CE_FR_RIO_G09__M 0x1FF +#define OFDM_CE_FR_RIO_G09__PRE 0x50 + +#define OFDM_CE_FR_RIO_G10__A 0x2C20040 +#define OFDM_CE_FR_RIO_G10__W 9 +#define OFDM_CE_FR_RIO_G10__M 0x1FF +#define OFDM_CE_FR_RIO_G10__PRE 0x49 +#define OFDM_CE_FR_MODE__A 0x2C20041 +#define OFDM_CE_FR_MODE__W 9 +#define OFDM_CE_FR_MODE__M 0x1FF +#define OFDM_CE_FR_MODE__PRE 0xDE + +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0 + +#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2 + +#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4 + +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8 + +#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4 +#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1 +#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10 +#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10 + +#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5 +#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1 +#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20 +#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0 + +#define OFDM_CE_FR_MODE_MID_MODE__B 6 +#define OFDM_CE_FR_MODE_MID_MODE__W 1 +#define OFDM_CE_FR_MODE_MID_MODE__M 0x40 +#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40 + +#define OFDM_CE_FR_MODE_NOISE_MODE__B 7 +#define OFDM_CE_FR_MODE_NOISE_MODE__W 1 +#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80 +#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80 + +#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8 +#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1 +#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100 +#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0 + + +#define OFDM_CE_FR_SQS_TRH__A 0x2C20042 +#define OFDM_CE_FR_SQS_TRH__W 8 +#define OFDM_CE_FR_SQS_TRH__M 0xFF +#define OFDM_CE_FR_SQS_TRH__PRE 0x80 + +#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043 +#define OFDM_CE_FR_RIO_GAIN__W 3 +#define OFDM_CE_FR_RIO_GAIN__M 0x7 +#define OFDM_CE_FR_RIO_GAIN__PRE 0x7 +#define OFDM_CE_FR_BYPASS__A 0x2C20044 +#define OFDM_CE_FR_BYPASS__W 10 +#define OFDM_CE_FR_BYPASS__M 0x3FF +#define OFDM_CE_FR_BYPASS__PRE 0x13B + +#define OFDM_CE_FR_BYPASS_RUN_IN__B 0 +#define OFDM_CE_FR_BYPASS_RUN_IN__W 4 +#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF +#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB + +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130 + +#define OFDM_CE_FR_BYPASS_TOTAL__B 9 +#define OFDM_CE_FR_BYPASS_TOTAL__W 1 +#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200 +#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0 + + +#define OFDM_CE_FR_PM_SET__A 0x2C20045 +#define OFDM_CE_FR_PM_SET__W 4 +#define OFDM_CE_FR_PM_SET__M 0xF +#define OFDM_CE_FR_PM_SET__PRE 0xD + +#define OFDM_CE_FR_ERR_SH__A 0x2C20046 +#define OFDM_CE_FR_ERR_SH__W 4 +#define OFDM_CE_FR_ERR_SH__M 0xF +#define OFDM_CE_FR_ERR_SH__PRE 0x4 + +#define OFDM_CE_FR_MAN_SH__A 0x2C20047 +#define OFDM_CE_FR_MAN_SH__W 4 +#define OFDM_CE_FR_MAN_SH__M 0xF +#define OFDM_CE_FR_MAN_SH__PRE 0x7 + +#define OFDM_CE_FR_TAP_SH__A 0x2C20048 +#define OFDM_CE_FR_TAP_SH__W 3 +#define OFDM_CE_FR_TAP_SH__M 0x7 +#define OFDM_CE_FR_TAP_SH__PRE 0x3 + +#define OFDM_CE_FR_CLIP__A 0x2C20049 +#define OFDM_CE_FR_CLIP__W 9 +#define OFDM_CE_FR_CLIP__M 0x1FF +#define OFDM_CE_FR_CLIP__PRE 0x49 + +#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A +#define OFDM_CE_FR_LEAK_UPD__W 3 +#define OFDM_CE_FR_LEAK_UPD__M 0x7 +#define OFDM_CE_FR_LEAK_UPD__PRE 0x0 + +#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B +#define OFDM_CE_FR_LEAK_SH__W 3 +#define OFDM_CE_FR_LEAK_SH__M 0x7 +#define OFDM_CE_FR_LEAK_SH__PRE 0x1 + + + +#define OFDM_CE_NE_RAM__A 0x2C30000 + + + +#define OFDM_CE_PB_RAM__A 0x2C40000 + + + + + +#define OFDM_CP_COMM_EXEC__A 0x2800000 +#define OFDM_CP_COMM_EXEC__W 3 +#define OFDM_CP_COMM_EXEC__M 0x7 +#define OFDM_CP_COMM_EXEC__PRE 0x0 +#define OFDM_CP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CP_COMM_EXEC_HOLD 0x2 +#define OFDM_CP_COMM_EXEC_STEP 0x3 +#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_CP_COMM_STATE__A 0x2800001 +#define OFDM_CP_COMM_STATE__W 16 +#define OFDM_CP_COMM_STATE__M 0xFFFF +#define OFDM_CP_COMM_STATE__PRE 0x0 +#define OFDM_CP_COMM_MB__A 0x2800002 +#define OFDM_CP_COMM_MB__W 16 +#define OFDM_CP_COMM_MB__M 0xFFFF +#define OFDM_CP_COMM_MB__PRE 0x0 +#define OFDM_CP_COMM_INT_REQ__A 0x2800004 +#define OFDM_CP_COMM_INT_REQ__W 16 +#define OFDM_CP_COMM_INT_REQ__M 0xFFFF +#define OFDM_CP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_CP_COMM_INT_STA__A 0x2800005 +#define OFDM_CP_COMM_INT_STA__W 16 +#define OFDM_CP_COMM_INT_STA__M 0xFFFF +#define OFDM_CP_COMM_INT_STA__PRE 0x0 +#define OFDM_CP_COMM_INT_MSK__A 0x2800006 +#define OFDM_CP_COMM_INT_MSK__W 16 +#define OFDM_CP_COMM_INT_MSK__M 0xFFFF +#define OFDM_CP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CP_COMM_INT_STM__A 0x2800007 +#define OFDM_CP_COMM_INT_STM__W 16 +#define OFDM_CP_COMM_INT_STM__M 0xFFFF +#define OFDM_CP_COMM_INT_STM__PRE 0x0 +#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000 +#define OFDM_CP_TOP_COMM_EXEC__W 3 +#define OFDM_CP_TOP_COMM_EXEC__M 0x7 +#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_CP_TOP_COMM_MB__A 0x2810002 +#define OFDM_CP_TOP_COMM_MB__W 3 +#define OFDM_CP_TOP_COMM_MB__M 0x7 +#define OFDM_CP_TOP_COMM_MB__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL__B 0 +#define OFDM_CP_TOP_COMM_MB_CTL__W 1 +#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_CP_TOP_COMM_MB_OBS__B 1 +#define OFDM_CP_TOP_COMM_MB_OBS__W 1 +#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4 + +#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004 +#define OFDM_CP_TOP_COMM_INT_REQ__W 1 +#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005 +#define OFDM_CP_TOP_COMM_INT_STA__W 1 +#define OFDM_CP_TOP_COMM_INT_STA__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0 + +#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006 +#define OFDM_CP_TOP_COMM_INT_MSK__W 1 +#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1 +#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0 + +#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007 +#define OFDM_CP_TOP_COMM_INT_STM__W 1 +#define OFDM_CP_TOP_COMM_INT_STM__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0 + + +#define OFDM_CP_TOP_MODE_2K__A 0x2810010 +#define OFDM_CP_TOP_MODE_2K__W 1 +#define OFDM_CP_TOP_MODE_2K__M 0x1 +#define OFDM_CP_TOP_MODE_2K__PRE 0x0 + +#define OFDM_CP_TOP_INTERVAL__A 0x2810011 +#define OFDM_CP_TOP_INTERVAL__W 4 +#define OFDM_CP_TOP_INTERVAL__M 0xF +#define OFDM_CP_TOP_INTERVAL__PRE 0x5 +#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012 +#define OFDM_CP_TOP_DETECT_ENA__W 2 +#define OFDM_CP_TOP_DETECT_ENA__M 0x3 +#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0 + +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0 + +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0 + +#define OFDM_CP_TOP_FIX__A 0x2810013 +#define OFDM_CP_TOP_FIX__W 4 +#define OFDM_CP_TOP_FIX__M 0xF +#define OFDM_CP_TOP_FIX__PRE 0xF + +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1 + +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2 + +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4 + +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8 + +#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021 +#define OFDM_CP_TOP_BR_SMB_NR__W 4 +#define OFDM_CP_TOP_BR_SMB_NR__M 0xF +#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0 + + +#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022 +#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2 +#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3 +#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0 + +#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023 +#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4 +#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF +#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8 + +#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024 +#define OFDM_CP_TOP_BR_STR_DEL__W 10 +#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF +#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA + +#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025 +#define OFDM_CP_TOP_BR_EXP_ADJ__W 5 +#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F +#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10 + +#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030 +#define OFDM_CP_TOP_RT_ANG_INC0__W 16 +#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF +#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0 + +#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031 +#define OFDM_CP_TOP_RT_ANG_INC1__W 8 +#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF +#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032 +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5 +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5 + +#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033 +#define OFDM_CP_TOP_RT_DETECT_TRH__W 2 +#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3 +#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3 + +#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036 +#define OFDM_CP_TOP_RT_SPD_MOD__W 2 +#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3 +#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037 +#define OFDM_CP_TOP_RT_SPD_SMB__W 2 +#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3 +#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0 +#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038 +#define OFDM_CP_TOP_RT_CPD_MODE__W 3 +#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7 +#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0 + + +#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A +#define OFDM_CP_TOP_RT_CPD_BIN__W 5 +#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F +#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B +#define OFDM_CP_TOP_RT_CPD_MAX__W 4 +#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF +#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0 +#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C +#define OFDM_CP_TOP_RT_SUPR_VAL__W 2 +#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3 +#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0 + +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0 + +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0 + + +#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D +#define OFDM_CP_TOP_RT_EXP_AVE__W 5 +#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F +#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5 +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3 + +#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040 +#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8 +#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF +#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0 + +#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041 +#define OFDM_CP_TOP_AC_AVER_POW__W 8 +#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF +#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F + +#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042 +#define OFDM_CP_TOP_AC_MAX_POW__W 8 +#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF +#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A + +#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043 +#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6 +#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F +#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31 + +#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044 +#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5 +#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F +#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10 + +#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045 +#define OFDM_CP_TOP_AC_GAIN_MAN__W 16 +#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF +#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046 +#define OFDM_CP_TOP_AC_GAIN_EXP__W 5 +#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F +#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047 +#define OFDM_CP_TOP_AC_AMP_MODE__W 2 +#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3 +#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2 +#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0 +#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1 +#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2 + +#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048 +#define OFDM_CP_TOP_AC_AMP_FIX__W 14 +#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF +#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0 +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10 +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049 +#define OFDM_CP_TOP_AC_AMP_READ__W 14 +#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF +#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0 +#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10 +#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF +#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0 + + +#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A +#define OFDM_CP_TOP_AC_ANG_MODE__W 2 +#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3 +#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3 +#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0 +#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1 +#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2 +#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3 + + +#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B +#define OFDM_CP_TOP_AC_ANG_OFFS__W 16 +#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF +#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0 + +#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C +#define OFDM_CP_TOP_AC_ANG_READ__W 16 +#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF +#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060 +#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8 +#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061 +#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8 +#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062 +#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8 +#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063 +#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8 +#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050 +#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15 +#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF +#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0 +#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051 +#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5 +#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F +#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2 +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3 +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0 + + +#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052 +#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15 +#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF +#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0 +#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053 +#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11 +#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF +#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3 +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0 + + + +#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000 + + + +#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000 + + + +#define OFDM_CP_DL_0_RAM__A 0x2840000 + + + +#define OFDM_CP_DL_1_RAM__A 0x2850000 + + + +#define OFDM_CP_DL_2_RAM__A 0x2860000 + + + + + +#define OFDM_EC_COMM_EXEC__A 0x3400000 +#define OFDM_EC_COMM_EXEC__W 3 +#define OFDM_EC_COMM_EXEC__M 0x7 +#define OFDM_EC_COMM_EXEC__PRE 0x0 +#define OFDM_EC_COMM_EXEC_STOP 0x0 +#define OFDM_EC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_COMM_EXEC_STEP 0x3 +#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_EC_COMM_STATE__A 0x3400001 +#define OFDM_EC_COMM_STATE__W 16 +#define OFDM_EC_COMM_STATE__M 0xFFFF +#define OFDM_EC_COMM_STATE__PRE 0x0 +#define OFDM_EC_COMM_MB__A 0x3400002 +#define OFDM_EC_COMM_MB__W 16 +#define OFDM_EC_COMM_MB__M 0xFFFF +#define OFDM_EC_COMM_MB__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ__A 0x3400004 +#define OFDM_EC_COMM_INT_REQ__W 16 +#define OFDM_EC_COMM_INT_REQ__M 0xFFFF +#define OFDM_EC_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define OFDM_EC_COMM_INT_STA__A 0x3400005 +#define OFDM_EC_COMM_INT_STA__W 16 +#define OFDM_EC_COMM_INT_STA__M 0xFFFF +#define OFDM_EC_COMM_INT_STA__PRE 0x0 +#define OFDM_EC_COMM_INT_MSK__A 0x3400006 +#define OFDM_EC_COMM_INT_MSK__W 16 +#define OFDM_EC_COMM_INT_MSK__M 0xFFFF +#define OFDM_EC_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_COMM_INT_STM__A 0x3400007 +#define OFDM_EC_COMM_INT_STM__W 16 +#define OFDM_EC_COMM_INT_STM__M 0xFFFF +#define OFDM_EC_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_EC_SB_COMM_EXEC__A 0x3410000 +#define OFDM_EC_SB_COMM_EXEC__W 3 +#define OFDM_EC_SB_COMM_EXEC__M 0x7 +#define OFDM_EC_SB_COMM_EXEC__PRE 0x0 +#define OFDM_EC_SB_COMM_EXEC_STOP 0x0 +#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_SB_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_SB_COMM_STATE__A 0x3410001 +#define OFDM_EC_SB_COMM_STATE__W 4 +#define OFDM_EC_SB_COMM_STATE__M 0xF +#define OFDM_EC_SB_COMM_STATE__PRE 0x0 +#define OFDM_EC_SB_COMM_MB__A 0x3410002 +#define OFDM_EC_SB_COMM_MB__W 2 +#define OFDM_EC_SB_COMM_MB__M 0x3 +#define OFDM_EC_SB_COMM_MB__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_CTL__B 0 +#define OFDM_EC_SB_COMM_MB_CTL__W 1 +#define OFDM_EC_SB_COMM_MB_CTL__M 0x1 +#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_SB_COMM_MB_OBS__B 1 +#define OFDM_EC_SB_COMM_MB_OBS__W 1 +#define OFDM_EC_SB_COMM_MB_OBS__M 0x2 +#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2 + + +#define OFDM_EC_SB_TR_MODE__A 0x3410010 +#define OFDM_EC_SB_TR_MODE__W 1 +#define OFDM_EC_SB_TR_MODE__M 0x1 +#define OFDM_EC_SB_TR_MODE__PRE 0x0 +#define OFDM_EC_SB_TR_MODE_8K 0x0 +#define OFDM_EC_SB_TR_MODE_2K 0x1 + + +#define OFDM_EC_SB_CONST__A 0x3410011 +#define OFDM_EC_SB_CONST__W 2 +#define OFDM_EC_SB_CONST__M 0x3 +#define OFDM_EC_SB_CONST__PRE 0x2 +#define OFDM_EC_SB_CONST_QPSK 0x0 +#define OFDM_EC_SB_CONST_16QAM 0x1 +#define OFDM_EC_SB_CONST_64QAM 0x2 + + +#define OFDM_EC_SB_ALPHA__A 0x3410012 +#define OFDM_EC_SB_ALPHA__W 3 +#define OFDM_EC_SB_ALPHA__M 0x7 +#define OFDM_EC_SB_ALPHA__PRE 0x0 +#define OFDM_EC_SB_ALPHA_NH 0x0 +#define OFDM_EC_SB_ALPHA_H1 0x1 +#define OFDM_EC_SB_ALPHA_H2 0x2 +#define OFDM_EC_SB_ALPHA_H4 0x3 + + +#define OFDM_EC_SB_PRIOR__A 0x3410013 +#define OFDM_EC_SB_PRIOR__W 1 +#define OFDM_EC_SB_PRIOR__M 0x1 +#define OFDM_EC_SB_PRIOR__PRE 0x0 +#define OFDM_EC_SB_PRIOR_HI 0x0 +#define OFDM_EC_SB_PRIOR_LO 0x1 + + +#define OFDM_EC_SB_CSI_HI__A 0x3410014 +#define OFDM_EC_SB_CSI_HI__W 5 +#define OFDM_EC_SB_CSI_HI__M 0x1F +#define OFDM_EC_SB_CSI_HI__PRE 0x18 +#define OFDM_EC_SB_CSI_HI_MAX 0x1F +#define OFDM_EC_SB_CSI_HI_MIN 0x0 +#define OFDM_EC_SB_CSI_HI_TAG 0x0 + + +#define OFDM_EC_SB_CSI_LO__A 0x3410015 +#define OFDM_EC_SB_CSI_LO__W 5 +#define OFDM_EC_SB_CSI_LO__M 0x1F +#define OFDM_EC_SB_CSI_LO__PRE 0xC +#define OFDM_EC_SB_CSI_LO_MAX 0x1F +#define OFDM_EC_SB_CSI_LO_MIN 0x0 +#define OFDM_EC_SB_CSI_LO_TAG 0x0 + + +#define OFDM_EC_SB_SMB_TGL__A 0x3410016 +#define OFDM_EC_SB_SMB_TGL__W 1 +#define OFDM_EC_SB_SMB_TGL__M 0x1 +#define OFDM_EC_SB_SMB_TGL__PRE 0x1 +#define OFDM_EC_SB_SMB_TGL_OFF 0x0 +#define OFDM_EC_SB_SMB_TGL_ON 0x1 + + +#define OFDM_EC_SB_SNR_HI__A 0x3410017 +#define OFDM_EC_SB_SNR_HI__W 7 +#define OFDM_EC_SB_SNR_HI__M 0x7F +#define OFDM_EC_SB_SNR_HI__PRE 0x7F +#define OFDM_EC_SB_SNR_HI_MAX 0x7F +#define OFDM_EC_SB_SNR_HI_MIN 0x0 +#define OFDM_EC_SB_SNR_HI_TAG 0x0 + + +#define OFDM_EC_SB_SNR_MID__A 0x3410018 +#define OFDM_EC_SB_SNR_MID__W 7 +#define OFDM_EC_SB_SNR_MID__M 0x7F +#define OFDM_EC_SB_SNR_MID__PRE 0x7F +#define OFDM_EC_SB_SNR_MID_MAX 0x7F +#define OFDM_EC_SB_SNR_MID_MIN 0x0 +#define OFDM_EC_SB_SNR_MID_TAG 0x0 + + +#define OFDM_EC_SB_SNR_LO__A 0x3410019 +#define OFDM_EC_SB_SNR_LO__W 7 +#define OFDM_EC_SB_SNR_LO__M 0x7F +#define OFDM_EC_SB_SNR_LO__PRE 0x7F +#define OFDM_EC_SB_SNR_LO_MAX 0x7F +#define OFDM_EC_SB_SNR_LO_MIN 0x0 +#define OFDM_EC_SB_SNR_LO_TAG 0x0 + + +#define OFDM_EC_SB_SCALE_MSB__A 0x341001A +#define OFDM_EC_SB_SCALE_MSB__W 6 +#define OFDM_EC_SB_SCALE_MSB__M 0x3F +#define OFDM_EC_SB_SCALE_MSB__PRE 0x30 +#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F + + +#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B +#define OFDM_EC_SB_SCALE_BIT2__W 6 +#define OFDM_EC_SB_SCALE_BIT2__M 0x3F +#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC +#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F + + +#define OFDM_EC_SB_SCALE_LSB__A 0x341001C +#define OFDM_EC_SB_SCALE_LSB__W 6 +#define OFDM_EC_SB_SCALE_LSB__M 0x3F +#define OFDM_EC_SB_SCALE_LSB__PRE 0x3 +#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F + + +#define OFDM_EC_SB_CSI_OFS0__A 0x341001D +#define OFDM_EC_SB_CSI_OFS0__W 4 +#define OFDM_EC_SB_CSI_OFS0__M 0xF +#define OFDM_EC_SB_CSI_OFS0__PRE 0x1 + +#define OFDM_EC_SB_CSI_OFS1__A 0x341001E +#define OFDM_EC_SB_CSI_OFS1__W 4 +#define OFDM_EC_SB_CSI_OFS1__M 0xF +#define OFDM_EC_SB_CSI_OFS1__PRE 0x1 + +#define OFDM_EC_SB_CSI_OFS2__A 0x341001F +#define OFDM_EC_SB_CSI_OFS2__W 4 +#define OFDM_EC_SB_CSI_OFS2__M 0xF +#define OFDM_EC_SB_CSI_OFS2__PRE 0x1 + +#define OFDM_EC_SB_MAX0__A 0x3410020 +#define OFDM_EC_SB_MAX0__W 6 +#define OFDM_EC_SB_MAX0__M 0x3F +#define OFDM_EC_SB_MAX0__PRE 0x3F + +#define OFDM_EC_SB_MAX1__A 0x3410021 +#define OFDM_EC_SB_MAX1__W 6 +#define OFDM_EC_SB_MAX1__M 0x3F +#define OFDM_EC_SB_MAX1__PRE 0x3F +#define OFDM_EC_SB_MAX1_INIT 0x3F + + +#define OFDM_EC_SB_MAX2__A 0x3410022 +#define OFDM_EC_SB_MAX2__W 6 +#define OFDM_EC_SB_MAX2__M 0x3F +#define OFDM_EC_SB_MAX2__PRE 0x3F + +#define OFDM_EC_SB_CSI_DIS__A 0x3410023 +#define OFDM_EC_SB_CSI_DIS__W 1 +#define OFDM_EC_SB_CSI_DIS__M 0x1 +#define OFDM_EC_SB_CSI_DIS__PRE 0x0 + + + +#define OFDM_EC_VD_COMM_EXEC__A 0x3420000 +#define OFDM_EC_VD_COMM_EXEC__W 3 +#define OFDM_EC_VD_COMM_EXEC__M 0x7 +#define OFDM_EC_VD_COMM_EXEC__PRE 0x0 +#define OFDM_EC_VD_COMM_EXEC_STOP 0x0 +#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_VD_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_VD_COMM_STATE__A 0x3420001 +#define OFDM_EC_VD_COMM_STATE__W 4 +#define OFDM_EC_VD_COMM_STATE__M 0xF +#define OFDM_EC_VD_COMM_STATE__PRE 0x0 +#define OFDM_EC_VD_COMM_MB__A 0x3420002 +#define OFDM_EC_VD_COMM_MB__W 2 +#define OFDM_EC_VD_COMM_MB__M 0x3 +#define OFDM_EC_VD_COMM_MB__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_CTL__B 0 +#define OFDM_EC_VD_COMM_MB_CTL__W 1 +#define OFDM_EC_VD_COMM_MB_CTL__M 0x1 +#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_VD_COMM_MB_OBS__B 1 +#define OFDM_EC_VD_COMM_MB_OBS__W 1 +#define OFDM_EC_VD_COMM_MB_OBS__M 0x2 +#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2 + +#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003 +#define OFDM_EC_VD_COMM_INT_REQ__W 1 +#define OFDM_EC_VD_COMM_INT_REQ__M 0x1 +#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005 +#define OFDM_EC_VD_COMM_INT_STA__W 1 +#define OFDM_EC_VD_COMM_INT_STA__M 0x1 +#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0 + +#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006 +#define OFDM_EC_VD_COMM_INT_MSK__W 1 +#define OFDM_EC_VD_COMM_INT_MSK__M 0x1 +#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0 + +#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007 +#define OFDM_EC_VD_COMM_INT_STM__W 1 +#define OFDM_EC_VD_COMM_INT_STM__M 0x1 +#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0 + + +#define OFDM_EC_VD_FORCE__A 0x3420010 +#define OFDM_EC_VD_FORCE__W 2 +#define OFDM_EC_VD_FORCE__M 0x3 +#define OFDM_EC_VD_FORCE__PRE 0x2 +#define OFDM_EC_VD_FORCE_FREE 0x0 +#define OFDM_EC_VD_FORCE_PROP 0x1 +#define OFDM_EC_VD_FORCE_FORCED 0x2 +#define OFDM_EC_VD_FORCE_FIXED 0x3 + + +#define OFDM_EC_VD_SET_CODERATE__A 0x3420011 +#define OFDM_EC_VD_SET_CODERATE__W 3 +#define OFDM_EC_VD_SET_CODERATE__M 0x7 +#define OFDM_EC_VD_SET_CODERATE__PRE 0x1 +#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0 +#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1 +#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2 +#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3 +#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4 + + +#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012 +#define OFDM_EC_VD_REQ_SMB_CNT__W 16 +#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1 + +#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013 +#define OFDM_EC_VD_REQ_BIT_CNT__W 16 +#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF + +#define OFDM_EC_VD_RLK_ENA__A 0x3420014 +#define OFDM_EC_VD_RLK_ENA__W 1 +#define OFDM_EC_VD_RLK_ENA__M 0x1 +#define OFDM_EC_VD_RLK_ENA__PRE 0x1 +#define OFDM_EC_VD_RLK_ENA_OFF 0x0 +#define OFDM_EC_VD_RLK_ENA_ON 0x1 + + +#define OFDM_EC_VD_VAL__A 0x3420015 +#define OFDM_EC_VD_VAL__W 2 +#define OFDM_EC_VD_VAL__M 0x3 +#define OFDM_EC_VD_VAL__PRE 0x0 +#define OFDM_EC_VD_VAL_CODE 0x1 +#define OFDM_EC_VD_VAL_CNT 0x2 + + +#define OFDM_EC_VD_GET_CODERATE__A 0x3420016 +#define OFDM_EC_VD_GET_CODERATE__W 3 +#define OFDM_EC_VD_GET_CODERATE__M 0x7 +#define OFDM_EC_VD_GET_CODERATE__PRE 0x0 +#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0 +#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1 +#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2 +#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3 +#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4 + + +#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 +#define OFDM_EC_VD_ERR_BIT_CNT__W 16 +#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF + +#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 +#define OFDM_EC_VD_IN_BIT_CNT__W 16 +#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0 + +#define OFDM_EC_VD_STS__A 0x3420019 +#define OFDM_EC_VD_STS__W 1 +#define OFDM_EC_VD_STS__M 0x1 +#define OFDM_EC_VD_STS__PRE 0x0 +#define OFDM_EC_VD_STS_NO_LOCK 0x0 +#define OFDM_EC_VD_STS_IN_LOCK 0x1 + + +#define OFDM_EC_VD_RLK_CNT__A 0x342001A +#define OFDM_EC_VD_RLK_CNT__W 16 +#define OFDM_EC_VD_RLK_CNT__M 0xFFFF +#define OFDM_EC_VD_RLK_CNT__PRE 0x0 + + + +#define OFDM_EC_SY_COMM_EXEC__A 0x3430000 +#define OFDM_EC_SY_COMM_EXEC__W 2 +#define OFDM_EC_SY_COMM_EXEC__M 0x3 +#define OFDM_EC_SY_COMM_EXEC__PRE 0x0 +#define OFDM_EC_SY_COMM_EXEC_STOP 0x0 +#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_SY_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_SY_COMM_MB__A 0x3430002 +#define OFDM_EC_SY_COMM_MB__W 2 +#define OFDM_EC_SY_COMM_MB__M 0x3 +#define OFDM_EC_SY_COMM_MB__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_CTL__B 0 +#define OFDM_EC_SY_COMM_MB_CTL__W 1 +#define OFDM_EC_SY_COMM_MB_CTL__M 0x1 +#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_SY_COMM_MB_OBS__B 1 +#define OFDM_EC_SY_COMM_MB_OBS__W 1 +#define OFDM_EC_SY_COMM_MB_OBS__M 0x2 +#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2 + +#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003 +#define OFDM_EC_SY_COMM_INT_REQ__W 1 +#define OFDM_EC_SY_COMM_INT_REQ__M 0x1 +#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005 +#define OFDM_EC_SY_COMM_INT_STA__W 3 +#define OFDM_EC_SY_COMM_INT_STA__M 0x7 +#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006 +#define OFDM_EC_SY_COMM_INT_MSK__W 3 +#define OFDM_EC_SY_COMM_INT_MSK__M 0x7 +#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007 +#define OFDM_EC_SY_COMM_INT_STM__W 3 +#define OFDM_EC_SY_COMM_INT_STM__M 0x7 +#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 + +#define OFDM_EC_SY_STATUS__A 0x3430010 +#define OFDM_EC_SY_STATUS__W 2 +#define OFDM_EC_SY_STATUS__M 0x3 +#define OFDM_EC_SY_STATUS__PRE 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0 +#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2 +#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3 +#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1 +#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2 + + +#define OFDM_EC_SY_TIMEOUT__A 0x3430011 +#define OFDM_EC_SY_TIMEOUT__W 16 +#define OFDM_EC_SY_TIMEOUT__M 0xFFFF +#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98 + +#define OFDM_EC_SY_SYNC_LWM__A 0x3430012 +#define OFDM_EC_SY_SYNC_LWM__W 4 +#define OFDM_EC_SY_SYNC_LWM__M 0xF +#define OFDM_EC_SY_SYNC_LWM__PRE 0x2 + +#define OFDM_EC_SY_SYNC_AWM__A 0x3430013 +#define OFDM_EC_SY_SYNC_AWM__W 4 +#define OFDM_EC_SY_SYNC_AWM__M 0xF +#define OFDM_EC_SY_SYNC_AWM__PRE 0x3 + +#define OFDM_EC_SY_SYNC_HWM__A 0x3430014 +#define OFDM_EC_SY_SYNC_HWM__W 4 +#define OFDM_EC_SY_SYNC_HWM__M 0xF +#define OFDM_EC_SY_SYNC_HWM__PRE 0x5 + +#define OFDM_EC_SY_UNLOCK__A 0x3430015 +#define OFDM_EC_SY_UNLOCK__W 1 +#define OFDM_EC_SY_UNLOCK__M 0x1 +#define OFDM_EC_SY_UNLOCK__PRE 0x0 + + + +#define OFDM_EC_SB_BD0_RAM__A 0x3440000 + + + +#define OFDM_EC_SB_BD1_RAM__A 0x3450000 + + + +#define OFDM_EC_SB_SD_RAM__A 0x3460000 + + + +#define OFDM_EC_VD_RE_RAM__A 0x3470000 + + + +#define OFDM_EC_VD_TB0_RAM__A 0x3480000 + + + +#define OFDM_EC_VD_TB1_RAM__A 0x3490000 + + + +#define OFDM_EC_VD_TB2_RAM__A 0x34A0000 + + + +#define OFDM_EC_VD_TB3_RAM__A 0x34B0000 + + + + + +#define OFDM_EQ_COMM_EXEC__A 0x3000000 +#define OFDM_EQ_COMM_EXEC__W 3 +#define OFDM_EQ_COMM_EXEC__M 0x7 +#define OFDM_EQ_COMM_EXEC__PRE 0x0 +#define OFDM_EQ_COMM_EXEC_STOP 0x0 +#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EQ_COMM_EXEC_HOLD 0x2 +#define OFDM_EQ_COMM_EXEC_STEP 0x3 +#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_EQ_COMM_STATE__A 0x3000001 +#define OFDM_EQ_COMM_STATE__W 16 +#define OFDM_EQ_COMM_STATE__M 0xFFFF +#define OFDM_EQ_COMM_STATE__PRE 0x0 +#define OFDM_EQ_COMM_MB__A 0x3000002 +#define OFDM_EQ_COMM_MB__W 16 +#define OFDM_EQ_COMM_MB__M 0xFFFF +#define OFDM_EQ_COMM_MB__PRE 0x0 +#define OFDM_EQ_COMM_INT_REQ__A 0x3000004 +#define OFDM_EQ_COMM_INT_REQ__W 16 +#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF +#define OFDM_EQ_COMM_INT_REQ__PRE 0x0 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_EQ_COMM_INT_STA__A 0x3000005 +#define OFDM_EQ_COMM_INT_STA__W 16 +#define OFDM_EQ_COMM_INT_STA__M 0xFFFF +#define OFDM_EQ_COMM_INT_STA__PRE 0x0 +#define OFDM_EQ_COMM_INT_MSK__A 0x3000006 +#define OFDM_EQ_COMM_INT_MSK__W 16 +#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF +#define OFDM_EQ_COMM_INT_MSK__PRE 0x0 +#define OFDM_EQ_COMM_INT_STM__A 0x3000007 +#define OFDM_EQ_COMM_INT_STM__W 16 +#define OFDM_EQ_COMM_INT_STM__M 0xFFFF +#define OFDM_EQ_COMM_INT_STM__PRE 0x0 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000 +#define OFDM_EQ_TOP_COMM_EXEC__W 3 +#define OFDM_EQ_TOP_COMM_EXEC__M 0x7 +#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001 +#define OFDM_EQ_TOP_COMM_STATE__W 4 +#define OFDM_EQ_TOP_COMM_STATE__M 0xF +#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB__A 0x3010002 +#define OFDM_EQ_TOP_COMM_MB__W 6 +#define OFDM_EQ_TOP_COMM_MB__M 0x3F +#define OFDM_EQ_TOP_COMM_MB__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL__B 0 +#define OFDM_EQ_TOP_COMM_MB_CTL__W 1 +#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_EQ_TOP_COMM_MB_OBS__B 1 +#define OFDM_EQ_TOP_COMM_MB_OBS__W 1 +#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30 + +#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004 +#define OFDM_EQ_TOP_COMM_INT_REQ__W 1 +#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005 +#define OFDM_EQ_TOP_COMM_INT_STA__W 2 +#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006 +#define OFDM_EQ_TOP_COMM_INT_MSK__W 2 +#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007 +#define OFDM_EQ_TOP_COMM_INT_STM__W 2 +#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_IS_MODE__A 0x3010014 +#define OFDM_EQ_TOP_IS_MODE__W 4 +#define OFDM_EQ_TOP_IS_MODE__M 0xF +#define OFDM_EQ_TOP_IS_MODE__PRE 0x0 + +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8 + + +#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015 +#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10 +#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF +#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114 + +#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016 +#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5 +#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F +#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5 + +#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017 +#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5 +#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F +#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10 +#define OFDM_EQ_TOP_DV_MODE__A 0x301001E +#define OFDM_EQ_TOP_DV_MODE__W 4 +#define OFDM_EQ_TOP_DV_MODE__M 0xF +#define OFDM_EQ_TOP_DV_MODE__PRE 0xF + +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1 + +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2 + +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4 + +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8 + + +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16 +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE__A 0x3010028 +#define OFDM_EQ_TOP_SN_MODE__W 8 +#define OFDM_EQ_TOP_SN_MODE__M 0xFF +#define OFDM_EQ_TOP_SN_MODE__PRE 0x18 + +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1 + +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2 + +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4 + +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8 + +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10 + +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20 + +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40 + +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80 + + +#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029 +#define OFDM_EQ_TOP_SN_PFIX__W 8 +#define OFDM_EQ_TOP_SN_PFIX__M 0xFF +#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0 + +#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A +#define OFDM_EQ_TOP_SN_CEGAIN__W 8 +#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF +#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30 + +#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B +#define OFDM_EQ_TOP_SN_OFFSET__W 6 +#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F +#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39 + +#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C +#define OFDM_EQ_TOP_SN_NULLIFY__W 6 +#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F +#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0 +#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D +#define OFDM_EQ_TOP_SN_SQUASH__W 10 +#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF +#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7 + +#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0 +#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6 +#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F +#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7 + +#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0 + +#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032 +#define OFDM_EQ_TOP_RC_SEL_CAR__W 8 +#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF +#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1 + +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6 + +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18 + +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60 + +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80 + +#define OFDM_EQ_TOP_RC_STS__A 0x3010033 +#define OFDM_EQ_TOP_RC_STS__W 16 +#define OFDM_EQ_TOP_RC_STS__M 0xFFFF +#define OFDM_EQ_TOP_RC_STS__PRE 0x0 + +#define OFDM_EQ_TOP_RC_STS_DIFF__B 0 +#define OFDM_EQ_TOP_RC_STS_DIFF__W 11 +#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF +#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0 + +#define OFDM_EQ_TOP_RC_STS_FIRST__B 11 +#define OFDM_EQ_TOP_RC_STS_FIRST__W 1 +#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800 +#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0 +#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800 + +#define OFDM_EQ_TOP_RC_STS_SELEC__B 12 +#define OFDM_EQ_TOP_RC_STS_SELEC__W 1 +#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000 +#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0 +#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000 + +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000 + +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000 + +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000 + + +#define OFDM_EQ_TOP_OT_CONST__A 0x3010046 +#define OFDM_EQ_TOP_OT_CONST__W 2 +#define OFDM_EQ_TOP_OT_CONST__M 0x3 +#define OFDM_EQ_TOP_OT_CONST__PRE 0x2 + +#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047 +#define OFDM_EQ_TOP_OT_ALPHA__W 2 +#define OFDM_EQ_TOP_OT_ALPHA__M 0x3 +#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0 + +#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048 +#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5 +#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F +#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E + +#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049 +#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5 +#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F +#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F + +#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A +#define OFDM_EQ_TOP_OT_CSI_STEP__W 4 +#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF +#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5 + +#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B +#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8 +#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF +#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5 + +#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C +#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8 +#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF +#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B + +#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D +#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7 +#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F +#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0 + +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7 +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050 +#define OFDM_EQ_TOP_TD_TPS_INIT__W 1 +#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1 +#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0 +#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1 + + +#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051 +#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16 +#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF +#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE +#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11 + + +#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052 +#define OFDM_EQ_TOP_TD_TPS_LEN__W 6 +#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F +#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17 +#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F + + +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 +#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 +#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 + + +#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055 +#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3 +#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4 + + +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 + + +#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058 +#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2 +#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0 +#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1 +#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2 +#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1 + + +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8 +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8 +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C +#define OFDM_EQ_TOP_TD_TPS_RSV__W 6 +#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F +#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D +#define OFDM_EQ_TOP_TD_TPS_BCH__W 14 +#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF +#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E +#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16 +#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF +#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16 +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0 + +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200 + +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F + + + + + +#define OFDM_FE_COMM_EXEC__A 0x2000000 +#define OFDM_FE_COMM_EXEC__W 3 +#define OFDM_FE_COMM_EXEC__M 0x7 +#define OFDM_FE_COMM_EXEC__PRE 0x0 +#define OFDM_FE_COMM_EXEC_STOP 0x0 +#define OFDM_FE_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FE_COMM_EXEC_HOLD 0x2 +#define OFDM_FE_COMM_EXEC_STEP 0x3 + +#define OFDM_FE_COMM_STATE__A 0x2000001 +#define OFDM_FE_COMM_STATE__W 16 +#define OFDM_FE_COMM_STATE__M 0xFFFF +#define OFDM_FE_COMM_STATE__PRE 0x0 +#define OFDM_FE_COMM_MB__A 0x2000002 +#define OFDM_FE_COMM_MB__W 16 +#define OFDM_FE_COMM_MB__M 0xFFFF +#define OFDM_FE_COMM_MB__PRE 0x0 +#define OFDM_FE_COMM_INT_REQ__A 0x2000004 +#define OFDM_FE_COMM_INT_REQ__W 16 +#define OFDM_FE_COMM_INT_REQ__M 0xFFFF +#define OFDM_FE_COMM_INT_REQ__PRE 0x0 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0 + +#define OFDM_FE_COMM_INT_STA__A 0x2000005 +#define OFDM_FE_COMM_INT_STA__W 16 +#define OFDM_FE_COMM_INT_STA__M 0xFFFF +#define OFDM_FE_COMM_INT_STA__PRE 0x0 +#define OFDM_FE_COMM_INT_MSK__A 0x2000006 +#define OFDM_FE_COMM_INT_MSK__W 16 +#define OFDM_FE_COMM_INT_MSK__M 0xFFFF +#define OFDM_FE_COMM_INT_MSK__PRE 0x0 +#define OFDM_FE_COMM_INT_STM__A 0x2000007 +#define OFDM_FE_COMM_INT_STM__W 16 +#define OFDM_FE_COMM_INT_STM__M 0xFFFF +#define OFDM_FE_COMM_INT_STM__PRE 0x0 +#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_FE_CU_COMM_EXEC__A 0x2010000 +#define OFDM_FE_CU_COMM_EXEC__W 3 +#define OFDM_FE_CU_COMM_EXEC__M 0x7 +#define OFDM_FE_CU_COMM_EXEC__PRE 0x0 +#define OFDM_FE_CU_COMM_EXEC_STOP 0x0 +#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2 +#define OFDM_FE_CU_COMM_EXEC_STEP 0x3 + +#define OFDM_FE_CU_COMM_STATE__A 0x2010001 +#define OFDM_FE_CU_COMM_STATE__W 4 +#define OFDM_FE_CU_COMM_STATE__M 0xF +#define OFDM_FE_CU_COMM_STATE__PRE 0x0 +#define OFDM_FE_CU_COMM_MB__A 0x2010002 +#define OFDM_FE_CU_COMM_MB__W 2 +#define OFDM_FE_CU_COMM_MB__M 0x3 +#define OFDM_FE_CU_COMM_MB__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_CTL__B 0 +#define OFDM_FE_CU_COMM_MB_CTL__W 1 +#define OFDM_FE_CU_COMM_MB_CTL__M 0x1 +#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0 +#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1 +#define OFDM_FE_CU_COMM_MB_OBS__B 1 +#define OFDM_FE_CU_COMM_MB_OBS__W 1 +#define OFDM_FE_CU_COMM_MB_OBS__M 0x2 +#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0 +#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2 + +#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004 +#define OFDM_FE_CU_COMM_INT_REQ__W 1 +#define OFDM_FE_CU_COMM_INT_REQ__M 0x1 +#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005 +#define OFDM_FE_CU_COMM_INT_STA__W 4 +#define OFDM_FE_CU_COMM_INT_STA__M 0xF +#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006 +#define OFDM_FE_CU_COMM_INT_MSK__W 4 +#define OFDM_FE_CU_COMM_INT_MSK__M 0xF +#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007 +#define OFDM_FE_CU_COMM_INT_STM__W 4 +#define OFDM_FE_CU_COMM_INT_STM__M 0xF +#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_MODE__A 0x2010010 +#define OFDM_FE_CU_MODE__W 8 +#define OFDM_FE_CU_MODE__M 0xFF +#define OFDM_FE_CU_MODE__PRE 0x20 + +#define OFDM_FE_CU_MODE_FFT__B 0 +#define OFDM_FE_CU_MODE_FFT__W 1 +#define OFDM_FE_CU_MODE_FFT__M 0x1 +#define OFDM_FE_CU_MODE_FFT__PRE 0x0 +#define OFDM_FE_CU_MODE_FFT_M8K 0x0 +#define OFDM_FE_CU_MODE_FFT_M2K 0x1 + +#define OFDM_FE_CU_MODE_COR__B 1 +#define OFDM_FE_CU_MODE_COR__W 1 +#define OFDM_FE_CU_MODE_COR__M 0x2 +#define OFDM_FE_CU_MODE_COR__PRE 0x0 +#define OFDM_FE_CU_MODE_COR_OFF 0x0 +#define OFDM_FE_CU_MODE_COR_ON 0x2 + +#define OFDM_FE_CU_MODE_IFD__B 2 +#define OFDM_FE_CU_MODE_IFD__W 1 +#define OFDM_FE_CU_MODE_IFD__M 0x4 +#define OFDM_FE_CU_MODE_IFD__PRE 0x0 +#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0 +#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4 + +#define OFDM_FE_CU_MODE_SEL__B 3 +#define OFDM_FE_CU_MODE_SEL__W 1 +#define OFDM_FE_CU_MODE_SEL__M 0x8 +#define OFDM_FE_CU_MODE_SEL__PRE 0x0 +#define OFDM_FE_CU_MODE_SEL_COR 0x0 +#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8 + +#define OFDM_FE_CU_MODE_FES__B 4 +#define OFDM_FE_CU_MODE_FES__W 1 +#define OFDM_FE_CU_MODE_FES__M 0x10 +#define OFDM_FE_CU_MODE_FES__PRE 0x0 +#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0 +#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10 +#define OFDM_FE_CU_MODE_AVG__B 5 +#define OFDM_FE_CU_MODE_AVG__W 1 +#define OFDM_FE_CU_MODE_AVG__M 0x20 +#define OFDM_FE_CU_MODE_AVG__PRE 0x20 +#define OFDM_FE_CU_MODE_AVG_OFF 0x0 +#define OFDM_FE_CU_MODE_AVG_ON 0x20 +#define OFDM_FE_CU_MODE_SHF_ENA__B 6 +#define OFDM_FE_CU_MODE_SHF_ENA__W 1 +#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40 +#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0 +#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0 +#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40 +#define OFDM_FE_CU_MODE_SHF_DIR__B 7 +#define OFDM_FE_CU_MODE_SHF_DIR__W 1 +#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80 +#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0 +#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0 +#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80 + + +#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011 +#define OFDM_FE_CU_FRM_CNT_RST__W 15 +#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF + +#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012 +#define OFDM_FE_CU_FRM_CNT_STR__W 15 +#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E + +#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013 +#define OFDM_FE_CU_FRM_SMP_CNT__W 15 +#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF +#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0 + +#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014 +#define OFDM_FE_CU_FRM_SMB_CNT__W 16 +#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF +#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015 +#define OFDM_FE_CU_CMP_MAX_DAT__W 12 +#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016 +#define OFDM_FE_CU_CMP_MAX_ADR__W 10 +#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF +#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017 +#define OFDM_FE_CU_CMP_MAX_RE__W 12 +#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018 +#define OFDM_FE_CU_CMP_MAX_IM__W 12 +#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0 + +#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F +#define OFDM_FE_CU_BUF_NFC_DEL__W 14 +#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF +#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0 + +#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020 +#define OFDM_FE_CU_CTR_NFC_ICR__W 5 +#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F +#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1 + +#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021 +#define OFDM_FE_CU_CTR_NFC_OCR__W 15 +#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF +#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8 + +#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022 +#define OFDM_FE_CU_CTR_NFC_CNT__W 15 +#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF +#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0 + +#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023 +#define OFDM_FE_CU_CTR_NFC_STS__W 3 +#define OFDM_FE_CU_CTR_NFC_STS__M 0x7 +#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0 +#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0 +#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1 +#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2 +#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4 + + +#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024 +#define OFDM_FE_CU_DIV_NFC_REA__W 14 +#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF +#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0 + +#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025 +#define OFDM_FE_CU_DIV_NFC_IMA__W 14 +#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF +#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0 + +#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026 +#define OFDM_FE_CU_FRM_CNT_UPD__W 15 +#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF + +#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027 +#define OFDM_FE_CU_DIV_NFC_CLP__W 2 +#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3 +#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3 + + +#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028 +#define OFDM_FE_CU_CMP_MAX_32__W 12 +#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029 +#define OFDM_FE_CU_CMP_MAX_16__W 12 +#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A +#define OFDM_FE_CU_CMP_MAX_8__W 12 +#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B +#define OFDM_FE_CU_CMP_MAX_4__W 12 +#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C +#define OFDM_FE_CU_CMP_SUM_32_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D +#define OFDM_FE_CU_CMP_SUM_32_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E +#define OFDM_FE_CU_CMP_SUM_16_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F +#define OFDM_FE_CU_CMP_SUM_16_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030 +#define OFDM_FE_CU_CMP_SUM_8_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031 +#define OFDM_FE_CU_CMP_SUM_8_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032 +#define OFDM_FE_CU_CMP_SUM_4_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033 +#define OFDM_FE_CU_CMP_SUM_4_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0 + + + +#define OFDM_FE_CU_BUF_RAM__A 0x2020000 + + + +#define OFDM_FE_CU_CMP_RAM__A 0x2030000 + + + + + +#define OFDM_FT_COMM_EXEC__A 0x2400000 +#define OFDM_FT_COMM_EXEC__W 3 +#define OFDM_FT_COMM_EXEC__M 0x7 +#define OFDM_FT_COMM_EXEC__PRE 0x0 +#define OFDM_FT_COMM_EXEC_STOP 0x0 +#define OFDM_FT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FT_COMM_EXEC_HOLD 0x2 +#define OFDM_FT_COMM_EXEC_STEP 0x3 +#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_FT_COMM_STATE__A 0x2400001 +#define OFDM_FT_COMM_STATE__W 16 +#define OFDM_FT_COMM_STATE__M 0xFFFF +#define OFDM_FT_COMM_STATE__PRE 0x0 +#define OFDM_FT_COMM_MB__A 0x2400002 +#define OFDM_FT_COMM_MB__W 16 +#define OFDM_FT_COMM_MB__M 0xFFFF +#define OFDM_FT_COMM_MB__PRE 0x0 + + + +#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000 +#define OFDM_FT_TOP_COMM_EXEC__W 3 +#define OFDM_FT_TOP_COMM_EXEC__M 0x7 +#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_FT_TOP_COMM_MB__A 0x2410002 +#define OFDM_FT_TOP_COMM_MB__W 2 +#define OFDM_FT_TOP_COMM_MB__M 0x3 +#define OFDM_FT_TOP_COMM_MB__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL__B 0 +#define OFDM_FT_TOP_COMM_MB_CTL__W 1 +#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_FT_TOP_COMM_MB_OBS__B 1 +#define OFDM_FT_TOP_COMM_MB_OBS__W 1 +#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2 + + +#define OFDM_FT_TOP_MODE_2K__A 0x2410010 +#define OFDM_FT_TOP_MODE_2K__W 1 +#define OFDM_FT_TOP_MODE_2K__M 0x1 +#define OFDM_FT_TOP_MODE_2K__PRE 0x0 +#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0 +#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1 + + +#define OFDM_FT_TOP_NORM_OFF__A 0x2410016 +#define OFDM_FT_TOP_NORM_OFF__W 4 +#define OFDM_FT_TOP_NORM_OFF__M 0xF +#define OFDM_FT_TOP_NORM_OFF__PRE 0x2 + + + +#define OFDM_FT_0TO2_0_RAM__A 0x2420000 + + + +#define OFDM_FT_0TO2_1_RAM__A 0x2430000 + + + +#define OFDM_FT_0TO2_2_RAM__A 0x2440000 + + + +#define OFDM_FT_3TO7_0_RAM__A 0x2450000 + + + +#define OFDM_FT_3TO7_1_RAM__A 0x2460000 + + + + + +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_LC_COMM_EXEC__W 3 +#define OFDM_LC_COMM_EXEC__M 0x7 +#define OFDM_LC_COMM_EXEC__PRE 0x0 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_LC_COMM_EXEC_HOLD 0x2 +#define OFDM_LC_COMM_EXEC_STEP 0x3 +#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_LC_COMM_STATE__A 0x3800001 +#define OFDM_LC_COMM_STATE__W 16 +#define OFDM_LC_COMM_STATE__M 0xFFFF +#define OFDM_LC_COMM_STATE__PRE 0x0 +#define OFDM_LC_COMM_MB__A 0x3800002 +#define OFDM_LC_COMM_MB__W 16 +#define OFDM_LC_COMM_MB__M 0xFFFF +#define OFDM_LC_COMM_MB__PRE 0x0 +#define OFDM_LC_COMM_INT_REQ__A 0x3800004 +#define OFDM_LC_COMM_INT_REQ__W 16 +#define OFDM_LC_COMM_INT_REQ__M 0xFFFF +#define OFDM_LC_COMM_INT_REQ__PRE 0x0 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0 + +#define OFDM_LC_COMM_INT_STA__A 0x3800005 +#define OFDM_LC_COMM_INT_STA__W 16 +#define OFDM_LC_COMM_INT_STA__M 0xFFFF +#define OFDM_LC_COMM_INT_STA__PRE 0x0 +#define OFDM_LC_COMM_INT_MSK__A 0x3800006 +#define OFDM_LC_COMM_INT_MSK__W 16 +#define OFDM_LC_COMM_INT_MSK__M 0xFFFF +#define OFDM_LC_COMM_INT_MSK__PRE 0x0 +#define OFDM_LC_COMM_INT_STM__A 0x3800007 +#define OFDM_LC_COMM_INT_STM__W 16 +#define OFDM_LC_COMM_INT_STM__M 0xFFFF +#define OFDM_LC_COMM_INT_STM__PRE 0x0 +#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_LC_CT_COMM_EXEC__A 0x3810000 +#define OFDM_LC_CT_COMM_EXEC__W 3 +#define OFDM_LC_CT_COMM_EXEC__M 0x7 +#define OFDM_LC_CT_COMM_EXEC__PRE 0x0 +#define OFDM_LC_CT_COMM_EXEC_STOP 0x0 +#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2 +#define OFDM_LC_CT_COMM_EXEC_STEP 0x3 + + +#define OFDM_LC_CT_COMM_STATE__A 0x3810001 +#define OFDM_LC_CT_COMM_STATE__W 10 +#define OFDM_LC_CT_COMM_STATE__M 0x3FF +#define OFDM_LC_CT_COMM_STATE__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004 +#define OFDM_LC_CT_COMM_INT_REQ__W 1 +#define OFDM_LC_CT_COMM_INT_REQ__M 0x1 +#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005 +#define OFDM_LC_CT_COMM_INT_STA__W 1 +#define OFDM_LC_CT_COMM_INT_STA__M 0x1 +#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0 + +#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006 +#define OFDM_LC_CT_COMM_INT_MSK__W 1 +#define OFDM_LC_CT_COMM_INT_MSK__M 0x1 +#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 + +#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007 +#define OFDM_LC_CT_COMM_INT_STM__W 1 +#define OFDM_LC_CT_COMM_INT_STM__M 0x1 +#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0 + + +#define OFDM_LC_CT_CTL_STK_0__A 0x3810010 +#define OFDM_LC_CT_CTL_STK_0__W 10 +#define OFDM_LC_CT_CTL_STK_0__M 0x3FF +#define OFDM_LC_CT_CTL_STK_0__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_1__A 0x3810011 +#define OFDM_LC_CT_CTL_STK_1__W 10 +#define OFDM_LC_CT_CTL_STK_1__M 0x3FF +#define OFDM_LC_CT_CTL_STK_1__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_2__A 0x3810012 +#define OFDM_LC_CT_CTL_STK_2__W 10 +#define OFDM_LC_CT_CTL_STK_2__M 0x3FF +#define OFDM_LC_CT_CTL_STK_2__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_3__A 0x3810013 +#define OFDM_LC_CT_CTL_STK_3__W 10 +#define OFDM_LC_CT_CTL_STK_3__M 0x3FF +#define OFDM_LC_CT_CTL_STK_3__PRE 0x0 + +#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F +#define OFDM_LC_CT_CTL_BPT_IDX__W 1 +#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1 +#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0 + +#define OFDM_LC_CT_CTL_BPT__A 0x3810020 +#define OFDM_LC_CT_CTL_BPT__W 10 +#define OFDM_LC_CT_CTL_BPT__M 0x3FF +#define OFDM_LC_CT_CTL_BPT__PRE 0x0 + + + +#define OFDM_LC_RA_RAM__A 0x3820000 + + + + +#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000 +#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12 +#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001 +#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12 +#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002 +#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12 +#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004 +#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12 +#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006 +#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12 +#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007 +#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12 +#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0 + + + + + + + +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006 +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16 +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A +#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16 +#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0 +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16 +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0 +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16 +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0 +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16 +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0 +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16 +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0 +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16 +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010 +#define OFDM_LC_RA_RAM_MODE_2K__W 16 +#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011 +#define OFDM_LC_RA_RAM_MODE_GUARD__W 16 +#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1 +#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2 +#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3 + +#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012 +#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16 +#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0 + +#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014 +#define OFDM_LC_RA_RAM_RC_STS__W 16 +#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF +#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16 +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16 +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16 +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16 +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E +#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16 +#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0 + + + + + +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__W 3 +#define OFDM_SC_COMM_EXEC__M 0x7 +#define OFDM_SC_COMM_EXEC__PRE 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_SC_COMM_EXEC_HOLD 0x2 +#define OFDM_SC_COMM_EXEC_STEP 0x3 +#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_SC_COMM_STATE__A 0x3C00001 +#define OFDM_SC_COMM_STATE__W 16 +#define OFDM_SC_COMM_STATE__M 0xFFFF +#define OFDM_SC_COMM_STATE__PRE 0x0 +#define OFDM_SC_COMM_MB__A 0x3C00002 +#define OFDM_SC_COMM_MB__W 16 +#define OFDM_SC_COMM_MB__M 0xFFFF +#define OFDM_SC_COMM_MB__PRE 0x0 +#define OFDM_SC_COMM_INT_REQ__A 0x3C00004 +#define OFDM_SC_COMM_INT_REQ__W 16 +#define OFDM_SC_COMM_INT_REQ__M 0xFFFF +#define OFDM_SC_COMM_INT_REQ__PRE 0x0 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0 + +#define OFDM_SC_COMM_INT_STA__A 0x3C00005 +#define OFDM_SC_COMM_INT_STA__W 16 +#define OFDM_SC_COMM_INT_STA__M 0xFFFF +#define OFDM_SC_COMM_INT_STA__PRE 0x0 +#define OFDM_SC_COMM_INT_MSK__A 0x3C00006 +#define OFDM_SC_COMM_INT_MSK__W 16 +#define OFDM_SC_COMM_INT_MSK__M 0xFFFF +#define OFDM_SC_COMM_INT_MSK__PRE 0x0 +#define OFDM_SC_COMM_INT_STM__A 0x3C00007 +#define OFDM_SC_COMM_INT_STM__W 16 +#define OFDM_SC_COMM_INT_STM__M 0xFFFF +#define OFDM_SC_COMM_INT_STM__PRE 0x0 +#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000 +#define OFDM_SC_CT_COMM_EXEC__W 3 +#define OFDM_SC_CT_COMM_EXEC__M 0x7 +#define OFDM_SC_CT_COMM_EXEC__PRE 0x0 +#define OFDM_SC_CT_COMM_EXEC_STOP 0x0 +#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2 +#define OFDM_SC_CT_COMM_EXEC_STEP 0x3 + + +#define OFDM_SC_CT_COMM_STATE__A 0x3C10001 +#define OFDM_SC_CT_COMM_STATE__W 10 +#define OFDM_SC_CT_COMM_STATE__M 0x3FF +#define OFDM_SC_CT_COMM_STATE__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004 +#define OFDM_SC_CT_COMM_INT_REQ__W 1 +#define OFDM_SC_CT_COMM_INT_REQ__M 0x1 +#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005 +#define OFDM_SC_CT_COMM_INT_STA__W 1 +#define OFDM_SC_CT_COMM_INT_STA__M 0x1 +#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0 + +#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006 +#define OFDM_SC_CT_COMM_INT_MSK__W 1 +#define OFDM_SC_CT_COMM_INT_MSK__M 0x1 +#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 + +#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007 +#define OFDM_SC_CT_COMM_INT_STM__W 1 +#define OFDM_SC_CT_COMM_INT_STM__M 0x1 +#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0 + + +#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010 +#define OFDM_SC_CT_CTL_STK_0__W 10 +#define OFDM_SC_CT_CTL_STK_0__M 0x3FF +#define OFDM_SC_CT_CTL_STK_0__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011 +#define OFDM_SC_CT_CTL_STK_1__W 10 +#define OFDM_SC_CT_CTL_STK_1__M 0x3FF +#define OFDM_SC_CT_CTL_STK_1__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012 +#define OFDM_SC_CT_CTL_STK_2__W 10 +#define OFDM_SC_CT_CTL_STK_2__M 0x3FF +#define OFDM_SC_CT_CTL_STK_2__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013 +#define OFDM_SC_CT_CTL_STK_3__W 10 +#define OFDM_SC_CT_CTL_STK_3__M 0x3FF +#define OFDM_SC_CT_CTL_STK_3__PRE 0x0 + +#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F +#define OFDM_SC_CT_CTL_BPT_IDX__W 1 +#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1 +#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0 + +#define OFDM_SC_CT_CTL_BPT__A 0x3C10020 +#define OFDM_SC_CT_CTL_BPT__W 13 +#define OFDM_SC_CT_CTL_BPT__M 0x1FFF +#define OFDM_SC_CT_CTL_BPT__PRE 0x0 + + + +#define OFDM_SC_RA_RAM__A 0x3C20000 + + + + +#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000 +#define OFDM_SC_IF_RAM_TRP_RST_0__W 12 +#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001 +#define OFDM_SC_IF_RAM_TRP_RST_1__W 12 +#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002 +#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12 +#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004 +#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12 +#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004 +#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12 +#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005 +#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12 +#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE +#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12 +#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF +#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0 + +#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF +#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12 +#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF +#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0 + + + + + + + +#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +#define OFDM_SC_RA_RAM_PARAM0__W 16 +#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +#define OFDM_SC_RA_RAM_PARAM1__W 16 +#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 +#define OFDM_SC_RA_RAM_CMD_ADDR__W 16 +#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF +#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 +#define OFDM_SC_RA_RAM_CMD__W 16 +#define OFDM_SC_RA_RAM_CMD__M 0xFFFF +#define OFDM_SC_RA_RAM_CMD__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD_NULL 0x0 +#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 +#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 +#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define OFDM_SC_RA_RAM_CMD_MAX 0x9 +#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4 + +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044 +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16 +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045 +#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16 +#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046 +#define OFDM_SC_RA_RAM_SW_EVENT__W 14 +#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF +#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0 + +#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047 +#define OFDM_SC_RA_RAM_LOCKTRACK__W 16 +#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF +#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0 +#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1 +#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3 +#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4 +#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5 +#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6 +#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7 +#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8 +#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9 + +#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 +#define OFDM_SC_RA_RAM_OP_PARAM__W 13 +#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF +#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 + +#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049 +#define OFDM_SC_RA_RAM_OP_AUTO__W 6 +#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F +#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0 + +#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A +#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16 +#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0 +#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0 +#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 +#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 + +#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B +#define OFDM_SC_RA_RAM_LOCK__W 4 +#define OFDM_SC_RA_RAM_LOCK__M 0xF +#define OFDM_SC_RA_RAM_LOCK__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_FEC__B 1 +#define OFDM_SC_RA_RAM_LOCK_FEC__W 1 +#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 +#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2 +#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1 +#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 +#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0 + +#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C +#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5 +#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F +#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10 + +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16 +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80 +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 +#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 + +#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 +#define OFDM_SC_RA_RAM_CONFIG__W 16 +#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF +#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14 +#define OFDM_SC_RA_RAM_CONFIG_ID__B 0 +#define OFDM_SC_RA_RAM_CONFIG_ID__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1 +#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0 + +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054 +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1 +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16 +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16 +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 +#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F +#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16 +#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16 +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16 +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 +#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C +#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 +#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D +#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C +#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E +#define OFDM_SC_RA_RAM_STATUS__W 16 +#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF +#define OFDM_SC_RA_RAM_STATUS__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16 +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 +#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080 +#define OFDM_SC_RA_RAM_TIMER__W 16 +#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF +#define OFDM_SC_RA_RAM_TIMER__PRE 0x0 +#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081 +#define OFDM_SC_RA_RAM_FI_OFFSET__W 16 +#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF +#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382 +#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082 +#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16 +#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18 +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16 +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640 +#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E +#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16 +#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF +#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0 +#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F +#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16 +#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF +#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2 +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16 +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400 + +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3 +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16 +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6 +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28 +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6 +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14 +#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0 +#define OFDM_SC_RA_RAM_IR_FREQ__W 16 +#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400 + +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC +#define OFDM_SC_RA_RAM_BAND__W 16 +#define OFDM_SC_RA_RAM_BAND__M 0xFFFF +#define OFDM_SC_RA_RAM_BAND__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF +#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0 + +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B +#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0 +#define OFDM_SC_RA_RAM_REG_0__W 16 +#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF +#define OFDM_SC_RA_RAM_REG_0__PRE 0x0 +#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1 +#define OFDM_SC_RA_RAM_REG_1__W 16 +#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF +#define OFDM_SC_RA_RAM_REG_1__PRE 0x0 +#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2 +#define OFDM_SC_RA_RAM_BREAK__W 16 +#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF +#define OFDM_SC_RA_RAM_BREAK__PRE 0x0 +#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3 +#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16 +#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0 +#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4 +#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16 +#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F +#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5 +#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16 +#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6 +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16 +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F + +#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9 +#define OFDM_SC_RA_RAM_LC_CP__W 16 +#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1 +#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA +#define OFDM_SC_RA_RAM_LC_DIFF__W 16 +#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7 +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16 +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58 +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16 +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0 + +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16 +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38 +#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE +#define OFDM_SC_RA_RAM_RELOCK__W 16 +#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF +#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0 +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16 +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149 +#define OFDM_SC_RA_RAM_NF_PREPOST__W 16 +#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A +#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16 +#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B +#define OFDM_SC_RA_RAM_NF_START__W 16 +#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_START__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C +#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16 +#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D +#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16 +#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F +#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16 +#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0 + + + + + +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__W 2 +#define QAM_COMM_EXEC__M 0x3 +#define QAM_COMM_EXEC__PRE 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_HOLD 0x2 + +#define QAM_COMM_MB__A 0x1400002 +#define QAM_COMM_MB__W 16 +#define QAM_COMM_MB__M 0xFFFF +#define QAM_COMM_MB__PRE 0x0 +#define QAM_COMM_INT_REQ__A 0x1400003 +#define QAM_COMM_INT_REQ__W 16 +#define QAM_COMM_INT_REQ__M 0xFFFF +#define QAM_COMM_INT_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SL_REQ__B 0 +#define QAM_COMM_INT_REQ_SL_REQ__W 1 +#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_LC_REQ__B 1 +#define QAM_COMM_INT_REQ_LC_REQ__W 1 +#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_VD_REQ__B 2 +#define QAM_COMM_INT_REQ_VD_REQ__W 1 +#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SY_REQ__B 3 +#define QAM_COMM_INT_REQ_SY_REQ__W 1 +#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define QAM_COMM_INT_STA__A 0x1400005 +#define QAM_COMM_INT_STA__W 16 +#define QAM_COMM_INT_STA__M 0xFFFF +#define QAM_COMM_INT_STA__PRE 0x0 +#define QAM_COMM_INT_MSK__A 0x1400006 +#define QAM_COMM_INT_MSK__W 16 +#define QAM_COMM_INT_MSK__M 0xFFFF +#define QAM_COMM_INT_MSK__PRE 0x0 +#define QAM_COMM_INT_STM__A 0x1400007 +#define QAM_COMM_INT_STM__W 16 +#define QAM_COMM_INT_STM__M 0xFFFF +#define QAM_COMM_INT_STM__PRE 0x0 + + + +#define QAM_TOP_COMM_EXEC__A 0x1410000 +#define QAM_TOP_COMM_EXEC__W 2 +#define QAM_TOP_COMM_EXEC__M 0x3 +#define QAM_TOP_COMM_EXEC__PRE 0x0 +#define QAM_TOP_COMM_EXEC_STOP 0x0 +#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +#define QAM_TOP_COMM_EXEC_HOLD 0x2 + + +#define QAM_TOP_ANNEX__A 0x1410010 +#define QAM_TOP_ANNEX__W 2 +#define QAM_TOP_ANNEX__M 0x3 +#define QAM_TOP_ANNEX__PRE 0x0 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_B 0x1 +#define QAM_TOP_ANNEX_C 0x2 +#define QAM_TOP_ANNEX_D 0x3 + + +#define QAM_TOP_CONSTELLATION__A 0x1410011 +#define QAM_TOP_CONSTELLATION__W 3 +#define QAM_TOP_CONSTELLATION__M 0x7 +#define QAM_TOP_CONSTELLATION__PRE 0x5 +#define QAM_TOP_CONSTELLATION_NONE 0x0 +#define QAM_TOP_CONSTELLATION_QPSK 0x1 +#define QAM_TOP_CONSTELLATION_QAM8 0x2 +#define QAM_TOP_CONSTELLATION_QAM16 0x3 +#define QAM_TOP_CONSTELLATION_QAM32 0x4 +#define QAM_TOP_CONSTELLATION_QAM64 0x5 +#define QAM_TOP_CONSTELLATION_QAM128 0x6 +#define QAM_TOP_CONSTELLATION_QAM256 0x7 + + + +#define QAM_FQ_COMM_EXEC__A 0x1420000 +#define QAM_FQ_COMM_EXEC__W 2 +#define QAM_FQ_COMM_EXEC__M 0x3 +#define QAM_FQ_COMM_EXEC__PRE 0x0 +#define QAM_FQ_COMM_EXEC_STOP 0x0 +#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_FQ_COMM_EXEC_HOLD 0x2 + +#define QAM_FQ_MODE__A 0x1420010 +#define QAM_FQ_MODE__W 3 +#define QAM_FQ_MODE__M 0x7 +#define QAM_FQ_MODE__PRE 0x0 + +#define QAM_FQ_MODE_TAPRESET__B 0 +#define QAM_FQ_MODE_TAPRESET__W 1 +#define QAM_FQ_MODE_TAPRESET__M 0x1 +#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +#define QAM_FQ_MODE_TAPRESET_RST 0x1 + +#define QAM_FQ_MODE_TAPLMS__B 1 +#define QAM_FQ_MODE_TAPLMS__W 1 +#define QAM_FQ_MODE_TAPLMS__M 0x2 +#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +#define QAM_FQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_FQ_MODE_TAPDRAIN__B 2 +#define QAM_FQ_MODE_TAPDRAIN__W 1 +#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 + + +#define QAM_FQ_MU_FACTOR__A 0x1420011 +#define QAM_FQ_MU_FACTOR__W 3 +#define QAM_FQ_MU_FACTOR__M 0x7 +#define QAM_FQ_MU_FACTOR__PRE 0x0 + +#define QAM_FQ_LA_FACTOR__A 0x1420012 +#define QAM_FQ_LA_FACTOR__W 4 +#define QAM_FQ_LA_FACTOR__M 0xF +#define QAM_FQ_LA_FACTOR__PRE 0xC +#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +#define QAM_FQ_CENTTAP_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +#define QAM_FQ_CENTTAP_VALUE__W 12 +#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 + +#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +#define QAM_FQ_TAP_RE_EL0__W 12 +#define QAM_FQ_TAP_RE_EL0__M 0xFFF +#define QAM_FQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +#define QAM_FQ_TAP_IM_EL0__W 12 +#define QAM_FQ_TAP_IM_EL0__M 0xFFF +#define QAM_FQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +#define QAM_FQ_TAP_RE_EL1__W 12 +#define QAM_FQ_TAP_RE_EL1__M 0xFFF +#define QAM_FQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +#define QAM_FQ_TAP_IM_EL1__W 12 +#define QAM_FQ_TAP_IM_EL1__M 0xFFF +#define QAM_FQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +#define QAM_FQ_TAP_RE_EL2__W 12 +#define QAM_FQ_TAP_RE_EL2__M 0xFFF +#define QAM_FQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +#define QAM_FQ_TAP_IM_EL2__W 12 +#define QAM_FQ_TAP_IM_EL2__M 0xFFF +#define QAM_FQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +#define QAM_FQ_TAP_RE_EL3__W 12 +#define QAM_FQ_TAP_RE_EL3__M 0xFFF +#define QAM_FQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +#define QAM_FQ_TAP_IM_EL3__W 12 +#define QAM_FQ_TAP_IM_EL3__M 0xFFF +#define QAM_FQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +#define QAM_FQ_TAP_RE_EL4__W 12 +#define QAM_FQ_TAP_RE_EL4__M 0xFFF +#define QAM_FQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +#define QAM_FQ_TAP_IM_EL4__W 12 +#define QAM_FQ_TAP_IM_EL4__M 0xFFF +#define QAM_FQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5__A 0x142002A +#define QAM_FQ_TAP_RE_EL5__W 12 +#define QAM_FQ_TAP_RE_EL5__M 0xFFF +#define QAM_FQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5__A 0x142002B +#define QAM_FQ_TAP_IM_EL5__W 12 +#define QAM_FQ_TAP_IM_EL5__M 0xFFF +#define QAM_FQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6__A 0x142002C +#define QAM_FQ_TAP_RE_EL6__W 12 +#define QAM_FQ_TAP_RE_EL6__M 0xFFF +#define QAM_FQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6__A 0x142002D +#define QAM_FQ_TAP_IM_EL6__W 12 +#define QAM_FQ_TAP_IM_EL6__M 0xFFF +#define QAM_FQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7__A 0x142002E +#define QAM_FQ_TAP_RE_EL7__W 12 +#define QAM_FQ_TAP_RE_EL7__M 0xFFF +#define QAM_FQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7__A 0x142002F +#define QAM_FQ_TAP_IM_EL7__W 12 +#define QAM_FQ_TAP_IM_EL7__M 0xFFF +#define QAM_FQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +#define QAM_FQ_TAP_RE_EL8__W 12 +#define QAM_FQ_TAP_RE_EL8__M 0xFFF +#define QAM_FQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +#define QAM_FQ_TAP_IM_EL8__W 12 +#define QAM_FQ_TAP_IM_EL8__M 0xFFF +#define QAM_FQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +#define QAM_FQ_TAP_RE_EL9__W 12 +#define QAM_FQ_TAP_RE_EL9__M 0xFFF +#define QAM_FQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +#define QAM_FQ_TAP_IM_EL9__W 12 +#define QAM_FQ_TAP_IM_EL9__M 0xFFF +#define QAM_FQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +#define QAM_FQ_TAP_RE_EL10__W 12 +#define QAM_FQ_TAP_RE_EL10__M 0xFFF +#define QAM_FQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +#define QAM_FQ_TAP_IM_EL10__W 12 +#define QAM_FQ_TAP_IM_EL10__M 0xFFF +#define QAM_FQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +#define QAM_FQ_TAP_RE_EL11__W 12 +#define QAM_FQ_TAP_RE_EL11__M 0xFFF +#define QAM_FQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +#define QAM_FQ_TAP_IM_EL11__W 12 +#define QAM_FQ_TAP_IM_EL11__M 0xFFF +#define QAM_FQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +#define QAM_FQ_TAP_RE_EL12__W 12 +#define QAM_FQ_TAP_RE_EL12__M 0xFFF +#define QAM_FQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +#define QAM_FQ_TAP_IM_EL12__W 12 +#define QAM_FQ_TAP_IM_EL12__M 0xFFF +#define QAM_FQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13__A 0x142003A +#define QAM_FQ_TAP_RE_EL13__W 12 +#define QAM_FQ_TAP_RE_EL13__M 0xFFF +#define QAM_FQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13__A 0x142003B +#define QAM_FQ_TAP_IM_EL13__W 12 +#define QAM_FQ_TAP_IM_EL13__M 0xFFF +#define QAM_FQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14__A 0x142003C +#define QAM_FQ_TAP_RE_EL14__W 12 +#define QAM_FQ_TAP_RE_EL14__M 0xFFF +#define QAM_FQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14__A 0x142003D +#define QAM_FQ_TAP_IM_EL14__W 12 +#define QAM_FQ_TAP_IM_EL14__M 0xFFF +#define QAM_FQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15__A 0x142003E +#define QAM_FQ_TAP_RE_EL15__W 12 +#define QAM_FQ_TAP_RE_EL15__M 0xFFF +#define QAM_FQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15__A 0x142003F +#define QAM_FQ_TAP_IM_EL15__W 12 +#define QAM_FQ_TAP_IM_EL15__M 0xFFF +#define QAM_FQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +#define QAM_FQ_TAP_RE_EL16__W 12 +#define QAM_FQ_TAP_RE_EL16__M 0xFFF +#define QAM_FQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +#define QAM_FQ_TAP_IM_EL16__W 12 +#define QAM_FQ_TAP_IM_EL16__M 0xFFF +#define QAM_FQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +#define QAM_FQ_TAP_RE_EL17__W 12 +#define QAM_FQ_TAP_RE_EL17__M 0xFFF +#define QAM_FQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +#define QAM_FQ_TAP_IM_EL17__W 12 +#define QAM_FQ_TAP_IM_EL17__M 0xFFF +#define QAM_FQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +#define QAM_FQ_TAP_RE_EL18__W 12 +#define QAM_FQ_TAP_RE_EL18__M 0xFFF +#define QAM_FQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +#define QAM_FQ_TAP_IM_EL18__W 12 +#define QAM_FQ_TAP_IM_EL18__M 0xFFF +#define QAM_FQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +#define QAM_FQ_TAP_RE_EL19__W 12 +#define QAM_FQ_TAP_RE_EL19__M 0xFFF +#define QAM_FQ_TAP_RE_EL19__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 + +#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +#define QAM_FQ_TAP_IM_EL19__W 12 +#define QAM_FQ_TAP_IM_EL19__M 0xFFF +#define QAM_FQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +#define QAM_FQ_TAP_RE_EL20__W 12 +#define QAM_FQ_TAP_RE_EL20__M 0xFFF +#define QAM_FQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +#define QAM_FQ_TAP_IM_EL20__W 12 +#define QAM_FQ_TAP_IM_EL20__M 0xFFF +#define QAM_FQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21__A 0x142004A +#define QAM_FQ_TAP_RE_EL21__W 12 +#define QAM_FQ_TAP_RE_EL21__M 0xFFF +#define QAM_FQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21__A 0x142004B +#define QAM_FQ_TAP_IM_EL21__W 12 +#define QAM_FQ_TAP_IM_EL21__M 0xFFF +#define QAM_FQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22__A 0x142004C +#define QAM_FQ_TAP_RE_EL22__W 12 +#define QAM_FQ_TAP_RE_EL22__M 0xFFF +#define QAM_FQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22__A 0x142004D +#define QAM_FQ_TAP_IM_EL22__W 12 +#define QAM_FQ_TAP_IM_EL22__M 0xFFF +#define QAM_FQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23__A 0x142004E +#define QAM_FQ_TAP_RE_EL23__W 12 +#define QAM_FQ_TAP_RE_EL23__M 0xFFF +#define QAM_FQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23__A 0x142004F +#define QAM_FQ_TAP_IM_EL23__W 12 +#define QAM_FQ_TAP_IM_EL23__M 0xFFF +#define QAM_FQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 + + + +#define QAM_SL_COMM_EXEC__A 0x1430000 +#define QAM_SL_COMM_EXEC__W 2 +#define QAM_SL_COMM_EXEC__M 0x3 +#define QAM_SL_COMM_EXEC__PRE 0x0 +#define QAM_SL_COMM_EXEC_STOP 0x0 +#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +#define QAM_SL_COMM_EXEC_HOLD 0x2 + +#define QAM_SL_COMM_MB__A 0x1430002 +#define QAM_SL_COMM_MB__W 4 +#define QAM_SL_COMM_MB__M 0xF +#define QAM_SL_COMM_MB__PRE 0x0 +#define QAM_SL_COMM_MB_CTL__B 0 +#define QAM_SL_COMM_MB_CTL__W 1 +#define QAM_SL_COMM_MB_CTL__M 0x1 +#define QAM_SL_COMM_MB_CTL__PRE 0x0 +#define QAM_SL_COMM_MB_CTL_OFF 0x0 +#define QAM_SL_COMM_MB_CTL_ON 0x1 +#define QAM_SL_COMM_MB_OBS__B 1 +#define QAM_SL_COMM_MB_OBS__W 1 +#define QAM_SL_COMM_MB_OBS__M 0x2 +#define QAM_SL_COMM_MB_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_OBS_OFF 0x0 +#define QAM_SL_COMM_MB_OBS_ON 0x2 +#define QAM_SL_COMM_MB_MUX_OBS__B 2 +#define QAM_SL_COMM_MB_MUX_OBS__W 2 +#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC + +#define QAM_SL_COMM_INT_REQ__A 0x1430003 +#define QAM_SL_COMM_INT_REQ__W 1 +#define QAM_SL_COMM_INT_REQ__M 0x1 +#define QAM_SL_COMM_INT_REQ__PRE 0x0 +#define QAM_SL_COMM_INT_STA__A 0x1430005 +#define QAM_SL_COMM_INT_STA__W 2 +#define QAM_SL_COMM_INT_STA__M 0x3 +#define QAM_SL_COMM_INT_STA__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_MSK__A 0x1430006 +#define QAM_SL_COMM_INT_MSK__W 2 +#define QAM_SL_COMM_INT_MSK__M 0x3 +#define QAM_SL_COMM_INT_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 + +#define QAM_SL_COMM_INT_STM__A 0x1430007 +#define QAM_SL_COMM_INT_STM__W 2 +#define QAM_SL_COMM_INT_STM__M 0x3 +#define QAM_SL_COMM_INT_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 + +#define QAM_SL_MODE__A 0x1430010 +#define QAM_SL_MODE__W 11 +#define QAM_SL_MODE__M 0x7FF +#define QAM_SL_MODE__PRE 0xA + +#define QAM_SL_MODE_SLICER4LC__B 0 +#define QAM_SL_MODE_SLICER4LC__W 2 +#define QAM_SL_MODE_SLICER4LC__M 0x3 +#define QAM_SL_MODE_SLICER4LC__PRE 0x2 +#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +#define QAM_SL_MODE_SLICER4LC_RAD 0x2 + +#define QAM_SL_MODE_SLICER4DQ__B 2 +#define QAM_SL_MODE_SLICER4DQ__W 2 +#define QAM_SL_MODE_SLICER4DQ__M 0xC +#define QAM_SL_MODE_SLICER4DQ__PRE 0x8 +#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 + +#define QAM_SL_MODE_SLICER4VD__B 4 +#define QAM_SL_MODE_SLICER4VD__W 2 +#define QAM_SL_MODE_SLICER4VD__M 0x30 +#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +#define QAM_SL_MODE_SLICER4VD_RAD 0x20 + +#define QAM_SL_MODE_ROT_DIS__B 6 +#define QAM_SL_MODE_ROT_DIS__W 1 +#define QAM_SL_MODE_ROT_DIS__M 0x40 +#define QAM_SL_MODE_ROT_DIS__PRE 0x0 +#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0 +#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40 + +#define QAM_SL_MODE_DQROT_DIS__B 7 +#define QAM_SL_MODE_DQROT_DIS__W 1 +#define QAM_SL_MODE_DQROT_DIS__M 0x80 +#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 +#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0 +#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80 + +#define QAM_SL_MODE_DFE_DIS__B 8 +#define QAM_SL_MODE_DFE_DIS__W 1 +#define QAM_SL_MODE_DFE_DIS__M 0x100 +#define QAM_SL_MODE_DFE_DIS__PRE 0x0 +#define QAM_SL_MODE_DFE_DIS_DQ 0x0 +#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100 + +#define QAM_SL_MODE_RADIUS_MIX__B 9 +#define QAM_SL_MODE_RADIUS_MIX__W 1 +#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 +#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0 +#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200 + +#define QAM_SL_MODE_TILT_COMP__B 10 +#define QAM_SL_MODE_TILT_COMP__W 1 +#define QAM_SL_MODE_TILT_COMP__M 0x400 +#define QAM_SL_MODE_TILT_COMP__PRE 0x0 +#define QAM_SL_MODE_TILT_COMP_OFF 0x0 +#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400 + + +#define QAM_SL_K_FACTOR__A 0x1430011 +#define QAM_SL_K_FACTOR__W 4 +#define QAM_SL_K_FACTOR__M 0xF +#define QAM_SL_K_FACTOR__PRE 0xC +#define QAM_SL_MEDIAN__A 0x1430012 +#define QAM_SL_MEDIAN__W 14 +#define QAM_SL_MEDIAN__M 0x3FFF +#define QAM_SL_MEDIAN__PRE 0x2C86 + +#define QAM_SL_MEDIAN_LENGTH__B 0 +#define QAM_SL_MEDIAN_LENGTH__W 2 +#define QAM_SL_MEDIAN_LENGTH__M 0x3 +#define QAM_SL_MEDIAN_LENGTH__PRE 0x2 +#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0 +#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1 +#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2 +#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3 + +#define QAM_SL_MEDIAN_CORRECT__B 2 +#define QAM_SL_MEDIAN_CORRECT__W 4 +#define QAM_SL_MEDIAN_CORRECT__M 0x3C +#define QAM_SL_MEDIAN_CORRECT__PRE 0x4 + +#define QAM_SL_MEDIAN_TOLERANCE__B 6 +#define QAM_SL_MEDIAN_TOLERANCE__W 7 +#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80 + +#define QAM_SL_MEDIAN_FAST__B 13 +#define QAM_SL_MEDIAN_FAST__W 1 +#define QAM_SL_MEDIAN_FAST__M 0x2000 +#define QAM_SL_MEDIAN_FAST__PRE 0x2000 +#define QAM_SL_MEDIAN_FAST_AVER 0x0 +#define QAM_SL_MEDIAN_FAST_LAST 0x2000 + + +#define QAM_SL_ALPHA__A 0x1430013 +#define QAM_SL_ALPHA__W 3 +#define QAM_SL_ALPHA__M 0x7 +#define QAM_SL_ALPHA__PRE 0x0 + +#define QAM_SL_PHASELIMIT__A 0x1430014 +#define QAM_SL_PHASELIMIT__W 9 +#define QAM_SL_PHASELIMIT__M 0x1FF +#define QAM_SL_PHASELIMIT__PRE 0x0 +#define QAM_SL_MTA_LENGTH__A 0x1430015 +#define QAM_SL_MTA_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH__PRE 0x1 + +#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 + +#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +#define QAM_SL_MEDIAN_ERROR__W 10 +#define QAM_SL_MEDIAN_ERROR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR__PRE 0x0 + +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 + + +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SL_ERR_POWER__W 16 +#define QAM_SL_ERR_POWER__M 0xFFFF +#define QAM_SL_ERR_POWER__PRE 0x0 +#define QAM_SL_QUAL_QAM_4_0__A 0x1430018 +#define QAM_SL_QUAL_QAM_4_0__W 3 +#define QAM_SL_QUAL_QAM_4_0__M 0x7 +#define QAM_SL_QUAL_QAM_4_0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_4_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_4_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_8_0__A 0x1430019 +#define QAM_SL_QUAL_QAM_8_0__W 6 +#define QAM_SL_QUAL_QAM_8_0__M 0x3F +#define QAM_SL_QUAL_QAM_8_0__PRE 0xD + +#define QAM_SL_QUAL_QAM_8_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_8_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_8_0_Q1__B 3 +#define QAM_SL_QUAL_QAM_8_0_Q1__W 3 +#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_16_0__A 0x143001A +#define QAM_SL_QUAL_QAM_16_0__W 3 +#define QAM_SL_QUAL_QAM_16_0__M 0x7 +#define QAM_SL_QUAL_QAM_16_0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_16_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_16_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_16_1__A 0x143001B +#define QAM_SL_QUAL_QAM_16_1__W 6 +#define QAM_SL_QUAL_QAM_16_1__M 0x3F +#define QAM_SL_QUAL_QAM_16_1__PRE 0x5 + +#define QAM_SL_QUAL_QAM_16_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_16_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_16_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_16_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_0__A 0x143001C +#define QAM_SL_QUAL_QAM_32_0__W 3 +#define QAM_SL_QUAL_QAM_32_0__M 0x7 +#define QAM_SL_QUAL_QAM_32_0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_32_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_32_1__A 0x143001D +#define QAM_SL_QUAL_QAM_32_1__W 6 +#define QAM_SL_QUAL_QAM_32_1__M 0x3F +#define QAM_SL_QUAL_QAM_32_1__PRE 0x3 + +#define QAM_SL_QUAL_QAM_32_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_32_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_32_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2__A 0x143001E +#define QAM_SL_QUAL_QAM_32_2__W 9 +#define QAM_SL_QUAL_QAM_32_2__M 0x1FF +#define QAM_SL_QUAL_QAM_32_2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_32_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_32_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_0__A 0x143001F +#define QAM_SL_QUAL_QAM_64_0__W 3 +#define QAM_SL_QUAL_QAM_64_0__M 0x7 +#define QAM_SL_QUAL_QAM_64_0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_1__A 0x1430020 +#define QAM_SL_QUAL_QAM_64_1__W 6 +#define QAM_SL_QUAL_QAM_64_1__M 0x3F +#define QAM_SL_QUAL_QAM_64_1__PRE 0x2 + +#define QAM_SL_QUAL_QAM_64_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2 + +#define QAM_SL_QUAL_QAM_64_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_2__A 0x1430021 +#define QAM_SL_QUAL_QAM_64_2__W 9 +#define QAM_SL_QUAL_QAM_64_2__M 0x1FF +#define QAM_SL_QUAL_QAM_64_2__PRE 0x9 + +#define QAM_SL_QUAL_QAM_64_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_64_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_64_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_3__A 0x1430022 +#define QAM_SL_QUAL_QAM_64_3__W 12 +#define QAM_SL_QUAL_QAM_64_3__M 0xFFF +#define QAM_SL_QUAL_QAM_64_3__PRE 0xD + +#define QAM_SL_QUAL_QAM_64_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_64_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_64_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_64_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_64_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_0__A 0x1430023 +#define QAM_SL_QUAL_QAM_128_0__W 3 +#define QAM_SL_QUAL_QAM_128_0__M 0x7 +#define QAM_SL_QUAL_QAM_128_0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_128_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_128_1__A 0x1430024 +#define QAM_SL_QUAL_QAM_128_1__W 6 +#define QAM_SL_QUAL_QAM_128_1__M 0x3F +#define QAM_SL_QUAL_QAM_128_1__PRE 0x5 + +#define QAM_SL_QUAL_QAM_128_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_128_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_2__A 0x1430025 +#define QAM_SL_QUAL_QAM_128_2__W 9 +#define QAM_SL_QUAL_QAM_128_2__M 0x1FF +#define QAM_SL_QUAL_QAM_128_2__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3__A 0x1430026 +#define QAM_SL_QUAL_QAM_128_3__W 12 +#define QAM_SL_QUAL_QAM_128_3__M 0xFFF +#define QAM_SL_QUAL_QAM_128_3__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4__A 0x1430027 +#define QAM_SL_QUAL_QAM_128_4__W 15 +#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF +#define QAM_SL_QUAL_QAM_128_4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_4_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_4_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_4_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_4_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q4__B 12 +#define QAM_SL_QUAL_QAM_128_4_Q4__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5__A 0x1430028 +#define QAM_SL_QUAL_QAM_128_5__W 15 +#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF +#define QAM_SL_QUAL_QAM_128_5__PRE 0x90 + +#define QAM_SL_QUAL_QAM_128_5_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_5_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_5_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10 + +#define QAM_SL_QUAL_QAM_128_5_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_5_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80 + +#define QAM_SL_QUAL_QAM_128_5_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_5_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5_Q4__B 12 +#define QAM_SL_QUAL_QAM_128_5_Q4__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029 +#define QAM_SL_QUAL_QAM_128_5H__W 3 +#define QAM_SL_QUAL_QAM_128_5H__M 0x7 +#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0 +#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3 +#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_0__A 0x143002A +#define QAM_SL_QUAL_QAM_256_0__W 3 +#define QAM_SL_QUAL_QAM_256_0__M 0x7 +#define QAM_SL_QUAL_QAM_256_0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_1__A 0x143002B +#define QAM_SL_QUAL_QAM_256_1__W 6 +#define QAM_SL_QUAL_QAM_256_1__M 0x3F +#define QAM_SL_QUAL_QAM_256_1__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_2__A 0x143002C +#define QAM_SL_QUAL_QAM_256_2__W 9 +#define QAM_SL_QUAL_QAM_256_2__M 0x1FF +#define QAM_SL_QUAL_QAM_256_2__PRE 0x9 + +#define QAM_SL_QUAL_QAM_256_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_256_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_3__A 0x143002D +#define QAM_SL_QUAL_QAM_256_3__W 12 +#define QAM_SL_QUAL_QAM_256_3__M 0xFFF +#define QAM_SL_QUAL_QAM_256_3__PRE 0x13 + +#define QAM_SL_QUAL_QAM_256_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10 + +#define QAM_SL_QUAL_QAM_256_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_4__A 0x143002E +#define QAM_SL_QUAL_QAM_256_4__W 15 +#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_4__PRE 0x49 + +#define QAM_SL_QUAL_QAM_256_4_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_4_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_4_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_4_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_256_4_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_4_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40 + +#define QAM_SL_QUAL_QAM_256_4_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_4_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_4_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_4_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5__A 0x143002F +#define QAM_SL_QUAL_QAM_256_5__W 15 +#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_5__PRE 0x59 + +#define QAM_SL_QUAL_QAM_256_5_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_5_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_5_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_5_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_5_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_5_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40 + +#define QAM_SL_QUAL_QAM_256_5_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_5_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_5_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030 +#define QAM_SL_QUAL_QAM_256_5H__W 3 +#define QAM_SL_QUAL_QAM_256_5H__M 0x7 +#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6__A 0x1430031 +#define QAM_SL_QUAL_QAM_256_6__W 15 +#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A + +#define QAM_SL_QUAL_QAM_256_6_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_6_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2 + +#define QAM_SL_QUAL_QAM_256_6_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_6_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_6_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_6_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_6_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200 + +#define QAM_SL_QUAL_QAM_256_6_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_6_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032 +#define QAM_SL_QUAL_QAM_256_6H__W 6 +#define QAM_SL_QUAL_QAM_256_6H__M 0x3F +#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3 +#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3 +#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38 +#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7__A 0x1430033 +#define QAM_SL_QUAL_QAM_256_7__W 15 +#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D + +#define QAM_SL_QUAL_QAM_256_7_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_7_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_256_7_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_7_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_7_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_7_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80 + +#define QAM_SL_QUAL_QAM_256_7_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_7_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200 + +#define QAM_SL_QUAL_QAM_256_7_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_7_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034 +#define QAM_SL_QUAL_QAM_256_7H__W 9 +#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF +#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3 +#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38 +#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6 +#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0 + + + +#define QAM_DQ_COMM_EXEC__A 0x1440000 +#define QAM_DQ_COMM_EXEC__W 2 +#define QAM_DQ_COMM_EXEC__M 0x3 +#define QAM_DQ_COMM_EXEC__PRE 0x0 +#define QAM_DQ_COMM_EXEC_STOP 0x0 +#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_DQ_COMM_EXEC_HOLD 0x2 + +#define QAM_DQ_MODE__A 0x1440010 +#define QAM_DQ_MODE__W 5 +#define QAM_DQ_MODE__M 0x1F +#define QAM_DQ_MODE__PRE 0x0 + +#define QAM_DQ_MODE_TAPRESET__B 0 +#define QAM_DQ_MODE_TAPRESET__W 1 +#define QAM_DQ_MODE_TAPRESET__M 0x1 +#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +#define QAM_DQ_MODE_TAPRESET_RST 0x1 + +#define QAM_DQ_MODE_TAPLMS__B 1 +#define QAM_DQ_MODE_TAPLMS__W 1 +#define QAM_DQ_MODE_TAPLMS__M 0x2 +#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +#define QAM_DQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_DQ_MODE_TAPDRAIN__B 2 +#define QAM_DQ_MODE_TAPDRAIN__W 1 +#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_DQ_MODE_FB__B 3 +#define QAM_DQ_MODE_FB__W 2 +#define QAM_DQ_MODE_FB__M 0x18 +#define QAM_DQ_MODE_FB__PRE 0x0 +#define QAM_DQ_MODE_FB_CMA 0x0 +#define QAM_DQ_MODE_FB_RADIUS 0x8 +#define QAM_DQ_MODE_FB_DFB 0x10 +#define QAM_DQ_MODE_FB_TRELLIS 0x18 + + +#define QAM_DQ_MU_FACTOR__A 0x1440011 +#define QAM_DQ_MU_FACTOR__W 3 +#define QAM_DQ_MU_FACTOR__M 0x7 +#define QAM_DQ_MU_FACTOR__PRE 0x0 + +#define QAM_DQ_LA_FACTOR__A 0x1440012 +#define QAM_DQ_LA_FACTOR__W 4 +#define QAM_DQ_LA_FACTOR__M 0xF +#define QAM_DQ_LA_FACTOR__PRE 0xC + +#define QAM_DQ_CMA_RATIO__A 0x1440013 +#define QAM_DQ_CMA_RATIO__W 14 +#define QAM_DQ_CMA_RATIO__M 0x3FFF +#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 + +#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +#define QAM_DQ_QUAL_RADSEL__W 3 +#define QAM_DQ_QUAL_RADSEL__M 0x7 +#define QAM_DQ_QUAL_RADSEL__PRE 0x0 + +#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 + +#define QAM_DQ_QUAL_ENA__A 0x1440015 +#define QAM_DQ_QUAL_ENA__W 1 +#define QAM_DQ_QUAL_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA__PRE 0x0 + +#define QAM_DQ_QUAL_ENA_ENA__B 0 +#define QAM_DQ_QUAL_ENA_ENA__W 1 +#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 + +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 + +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 + +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 + +#define QAM_DQ_RAW_LIM__A 0x144001E +#define QAM_DQ_RAW_LIM__W 5 +#define QAM_DQ_RAW_LIM__M 0x1F +#define QAM_DQ_RAW_LIM__PRE 0x1F + +#define QAM_DQ_RAW_LIM_BIT__B 0 +#define QAM_DQ_RAW_LIM_BIT__W 5 +#define QAM_DQ_RAW_LIM_BIT__M 0x1F +#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F + +#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +#define QAM_DQ_TAP_RE_EL0__W 12 +#define QAM_DQ_TAP_RE_EL0__M 0xFFF +#define QAM_DQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +#define QAM_DQ_TAP_IM_EL0__W 12 +#define QAM_DQ_TAP_IM_EL0__M 0xFFF +#define QAM_DQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +#define QAM_DQ_TAP_RE_EL1__W 12 +#define QAM_DQ_TAP_RE_EL1__M 0xFFF +#define QAM_DQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +#define QAM_DQ_TAP_IM_EL1__W 12 +#define QAM_DQ_TAP_IM_EL1__M 0xFFF +#define QAM_DQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +#define QAM_DQ_TAP_RE_EL2__W 12 +#define QAM_DQ_TAP_RE_EL2__M 0xFFF +#define QAM_DQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +#define QAM_DQ_TAP_IM_EL2__W 12 +#define QAM_DQ_TAP_IM_EL2__M 0xFFF +#define QAM_DQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +#define QAM_DQ_TAP_RE_EL3__W 12 +#define QAM_DQ_TAP_RE_EL3__M 0xFFF +#define QAM_DQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +#define QAM_DQ_TAP_IM_EL3__W 12 +#define QAM_DQ_TAP_IM_EL3__M 0xFFF +#define QAM_DQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +#define QAM_DQ_TAP_RE_EL4__W 12 +#define QAM_DQ_TAP_RE_EL4__M 0xFFF +#define QAM_DQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +#define QAM_DQ_TAP_IM_EL4__W 12 +#define QAM_DQ_TAP_IM_EL4__M 0xFFF +#define QAM_DQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5__A 0x144002A +#define QAM_DQ_TAP_RE_EL5__W 12 +#define QAM_DQ_TAP_RE_EL5__M 0xFFF +#define QAM_DQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5__A 0x144002B +#define QAM_DQ_TAP_IM_EL5__W 12 +#define QAM_DQ_TAP_IM_EL5__M 0xFFF +#define QAM_DQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6__A 0x144002C +#define QAM_DQ_TAP_RE_EL6__W 12 +#define QAM_DQ_TAP_RE_EL6__M 0xFFF +#define QAM_DQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6__A 0x144002D +#define QAM_DQ_TAP_IM_EL6__W 12 +#define QAM_DQ_TAP_IM_EL6__M 0xFFF +#define QAM_DQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7__A 0x144002E +#define QAM_DQ_TAP_RE_EL7__W 12 +#define QAM_DQ_TAP_RE_EL7__M 0xFFF +#define QAM_DQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7__A 0x144002F +#define QAM_DQ_TAP_IM_EL7__W 12 +#define QAM_DQ_TAP_IM_EL7__M 0xFFF +#define QAM_DQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +#define QAM_DQ_TAP_RE_EL8__W 12 +#define QAM_DQ_TAP_RE_EL8__M 0xFFF +#define QAM_DQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +#define QAM_DQ_TAP_IM_EL8__W 12 +#define QAM_DQ_TAP_IM_EL8__M 0xFFF +#define QAM_DQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +#define QAM_DQ_TAP_RE_EL9__W 12 +#define QAM_DQ_TAP_RE_EL9__M 0xFFF +#define QAM_DQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +#define QAM_DQ_TAP_IM_EL9__W 12 +#define QAM_DQ_TAP_IM_EL9__M 0xFFF +#define QAM_DQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +#define QAM_DQ_TAP_RE_EL10__W 12 +#define QAM_DQ_TAP_RE_EL10__M 0xFFF +#define QAM_DQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +#define QAM_DQ_TAP_IM_EL10__W 12 +#define QAM_DQ_TAP_IM_EL10__M 0xFFF +#define QAM_DQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +#define QAM_DQ_TAP_RE_EL11__W 12 +#define QAM_DQ_TAP_RE_EL11__M 0xFFF +#define QAM_DQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +#define QAM_DQ_TAP_IM_EL11__W 12 +#define QAM_DQ_TAP_IM_EL11__M 0xFFF +#define QAM_DQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +#define QAM_DQ_TAP_RE_EL12__W 12 +#define QAM_DQ_TAP_RE_EL12__M 0xFFF +#define QAM_DQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +#define QAM_DQ_TAP_IM_EL12__W 12 +#define QAM_DQ_TAP_IM_EL12__M 0xFFF +#define QAM_DQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13__A 0x144003A +#define QAM_DQ_TAP_RE_EL13__W 12 +#define QAM_DQ_TAP_RE_EL13__M 0xFFF +#define QAM_DQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13__A 0x144003B +#define QAM_DQ_TAP_IM_EL13__W 12 +#define QAM_DQ_TAP_IM_EL13__M 0xFFF +#define QAM_DQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14__A 0x144003C +#define QAM_DQ_TAP_RE_EL14__W 12 +#define QAM_DQ_TAP_RE_EL14__M 0xFFF +#define QAM_DQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14__A 0x144003D +#define QAM_DQ_TAP_IM_EL14__W 12 +#define QAM_DQ_TAP_IM_EL14__M 0xFFF +#define QAM_DQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15__A 0x144003E +#define QAM_DQ_TAP_RE_EL15__W 12 +#define QAM_DQ_TAP_RE_EL15__M 0xFFF +#define QAM_DQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15__A 0x144003F +#define QAM_DQ_TAP_IM_EL15__W 12 +#define QAM_DQ_TAP_IM_EL15__M 0xFFF +#define QAM_DQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +#define QAM_DQ_TAP_RE_EL16__W 12 +#define QAM_DQ_TAP_RE_EL16__M 0xFFF +#define QAM_DQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +#define QAM_DQ_TAP_IM_EL16__W 12 +#define QAM_DQ_TAP_IM_EL16__M 0xFFF +#define QAM_DQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +#define QAM_DQ_TAP_RE_EL17__W 12 +#define QAM_DQ_TAP_RE_EL17__M 0xFFF +#define QAM_DQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +#define QAM_DQ_TAP_IM_EL17__W 12 +#define QAM_DQ_TAP_IM_EL17__M 0xFFF +#define QAM_DQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +#define QAM_DQ_TAP_RE_EL18__W 12 +#define QAM_DQ_TAP_RE_EL18__M 0xFFF +#define QAM_DQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +#define QAM_DQ_TAP_IM_EL18__W 12 +#define QAM_DQ_TAP_IM_EL18__M 0xFFF +#define QAM_DQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +#define QAM_DQ_TAP_RE_EL19__W 12 +#define QAM_DQ_TAP_RE_EL19__M 0xFFF +#define QAM_DQ_TAP_RE_EL19__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +#define QAM_DQ_TAP_IM_EL19__W 12 +#define QAM_DQ_TAP_IM_EL19__M 0xFFF +#define QAM_DQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +#define QAM_DQ_TAP_RE_EL20__W 12 +#define QAM_DQ_TAP_RE_EL20__M 0xFFF +#define QAM_DQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +#define QAM_DQ_TAP_IM_EL20__W 12 +#define QAM_DQ_TAP_IM_EL20__M 0xFFF +#define QAM_DQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21__A 0x144004A +#define QAM_DQ_TAP_RE_EL21__W 12 +#define QAM_DQ_TAP_RE_EL21__M 0xFFF +#define QAM_DQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21__A 0x144004B +#define QAM_DQ_TAP_IM_EL21__W 12 +#define QAM_DQ_TAP_IM_EL21__M 0xFFF +#define QAM_DQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22__A 0x144004C +#define QAM_DQ_TAP_RE_EL22__W 12 +#define QAM_DQ_TAP_RE_EL22__M 0xFFF +#define QAM_DQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22__A 0x144004D +#define QAM_DQ_TAP_IM_EL22__W 12 +#define QAM_DQ_TAP_IM_EL22__M 0xFFF +#define QAM_DQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23__A 0x144004E +#define QAM_DQ_TAP_RE_EL23__W 12 +#define QAM_DQ_TAP_RE_EL23__M 0xFFF +#define QAM_DQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23__A 0x144004F +#define QAM_DQ_TAP_IM_EL23__W 12 +#define QAM_DQ_TAP_IM_EL23__M 0xFFF +#define QAM_DQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +#define QAM_DQ_TAP_RE_EL24__W 12 +#define QAM_DQ_TAP_RE_EL24__M 0xFFF +#define QAM_DQ_TAP_RE_EL24__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +#define QAM_DQ_TAP_IM_EL24__W 12 +#define QAM_DQ_TAP_IM_EL24__M 0xFFF +#define QAM_DQ_TAP_IM_EL24__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +#define QAM_DQ_TAP_RE_EL25__W 12 +#define QAM_DQ_TAP_RE_EL25__M 0xFFF +#define QAM_DQ_TAP_RE_EL25__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +#define QAM_DQ_TAP_IM_EL25__W 12 +#define QAM_DQ_TAP_IM_EL25__M 0xFFF +#define QAM_DQ_TAP_IM_EL25__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +#define QAM_DQ_TAP_RE_EL26__W 12 +#define QAM_DQ_TAP_RE_EL26__M 0xFFF +#define QAM_DQ_TAP_RE_EL26__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +#define QAM_DQ_TAP_IM_EL26__W 12 +#define QAM_DQ_TAP_IM_EL26__M 0xFFF +#define QAM_DQ_TAP_IM_EL26__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +#define QAM_DQ_TAP_RE_EL27__W 12 +#define QAM_DQ_TAP_RE_EL27__M 0xFFF +#define QAM_DQ_TAP_RE_EL27__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +#define QAM_DQ_TAP_IM_EL27__W 12 +#define QAM_DQ_TAP_IM_EL27__M 0xFFF +#define QAM_DQ_TAP_IM_EL27__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 + + + +#define QAM_LC_COMM_EXEC__A 0x1450000 +#define QAM_LC_COMM_EXEC__W 2 +#define QAM_LC_COMM_EXEC__M 0x3 +#define QAM_LC_COMM_EXEC__PRE 0x0 +#define QAM_LC_COMM_EXEC_STOP 0x0 +#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +#define QAM_LC_COMM_EXEC_HOLD 0x2 + +#define QAM_LC_COMM_MB__A 0x1450002 +#define QAM_LC_COMM_MB__W 2 +#define QAM_LC_COMM_MB__M 0x3 +#define QAM_LC_COMM_MB__PRE 0x0 +#define QAM_LC_COMM_MB_CTL__B 0 +#define QAM_LC_COMM_MB_CTL__W 1 +#define QAM_LC_COMM_MB_CTL__M 0x1 +#define QAM_LC_COMM_MB_CTL__PRE 0x0 +#define QAM_LC_COMM_MB_CTL_OFF 0x0 +#define QAM_LC_COMM_MB_CTL_ON 0x1 +#define QAM_LC_COMM_MB_OBS__B 1 +#define QAM_LC_COMM_MB_OBS__W 1 +#define QAM_LC_COMM_MB_OBS__M 0x2 +#define QAM_LC_COMM_MB_OBS__PRE 0x0 +#define QAM_LC_COMM_MB_OBS_OFF 0x0 +#define QAM_LC_COMM_MB_OBS_ON 0x2 + +#define QAM_LC_COMM_INT_REQ__A 0x1450003 +#define QAM_LC_COMM_INT_REQ__W 1 +#define QAM_LC_COMM_INT_REQ__M 0x1 +#define QAM_LC_COMM_INT_REQ__PRE 0x0 +#define QAM_LC_COMM_INT_STA__A 0x1450005 +#define QAM_LC_COMM_INT_STA__W 3 +#define QAM_LC_COMM_INT_STA__M 0x7 +#define QAM_LC_COMM_INT_STA__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_READY__B 0 +#define QAM_LC_COMM_INT_STA_READY__W 1 +#define QAM_LC_COMM_INT_STA_READY__M 0x1 +#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_MSK__A 0x1450006 +#define QAM_LC_COMM_INT_MSK__W 3 +#define QAM_LC_COMM_INT_MSK__M 0x7 +#define QAM_LC_COMM_INT_MSK__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_READY__B 0 +#define QAM_LC_COMM_INT_MSK_READY__W 1 +#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_STM__A 0x1450007 +#define QAM_LC_COMM_INT_STM__W 3 +#define QAM_LC_COMM_INT_STM__M 0x7 +#define QAM_LC_COMM_INT_STM__PRE 0x0 +#define QAM_LC_COMM_INT_STM_READY__B 0 +#define QAM_LC_COMM_INT_STM_READY__W 1 +#define QAM_LC_COMM_INT_STM_READY__M 0x1 +#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_MODE__W 4 +#define QAM_LC_MODE__M 0xF +#define QAM_LC_MODE__PRE 0xE + +#define QAM_LC_MODE_ENABLE_A__B 0 +#define QAM_LC_MODE_ENABLE_A__W 1 +#define QAM_LC_MODE_ENABLE_A__M 0x1 +#define QAM_LC_MODE_ENABLE_A__PRE 0x0 + +#define QAM_LC_MODE_ENABLE_F__B 1 +#define QAM_LC_MODE_ENABLE_F__W 1 +#define QAM_LC_MODE_ENABLE_F__M 0x2 +#define QAM_LC_MODE_ENABLE_F__PRE 0x2 + +#define QAM_LC_MODE_ENABLE_R__B 2 +#define QAM_LC_MODE_ENABLE_R__W 1 +#define QAM_LC_MODE_ENABLE_R__M 0x4 +#define QAM_LC_MODE_ENABLE_R__PRE 0x4 + +#define QAM_LC_MODE_ENABLE_PQUAL__B 3 +#define QAM_LC_MODE_ENABLE_PQUAL__W 1 +#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8 +#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8 + +#define QAM_LC_CA__A 0x1450011 +#define QAM_LC_CA__W 6 +#define QAM_LC_CA__M 0x3F +#define QAM_LC_CA__PRE 0x28 + +#define QAM_LC_CA_COEF__B 0 +#define QAM_LC_CA_COEF__W 6 +#define QAM_LC_CA_COEF__M 0x3F +#define QAM_LC_CA_COEF__PRE 0x28 + +#define QAM_LC_CF__A 0x1450012 +#define QAM_LC_CF__W 8 +#define QAM_LC_CF__M 0xFF +#define QAM_LC_CF__PRE 0x30 + +#define QAM_LC_CF_COEF__B 0 +#define QAM_LC_CF_COEF__W 8 +#define QAM_LC_CF_COEF__M 0xFF +#define QAM_LC_CF_COEF__PRE 0x30 + +#define QAM_LC_CF1__A 0x1450013 +#define QAM_LC_CF1__W 8 +#define QAM_LC_CF1__M 0xFF +#define QAM_LC_CF1__PRE 0x14 + +#define QAM_LC_CF1_COEF__B 0 +#define QAM_LC_CF1_COEF__W 8 +#define QAM_LC_CF1_COEF__M 0xFF +#define QAM_LC_CF1_COEF__PRE 0x14 + +#define QAM_LC_CP__A 0x1450014 +#define QAM_LC_CP__W 8 +#define QAM_LC_CP__M 0xFF +#define QAM_LC_CP__PRE 0x64 + +#define QAM_LC_CP_COEF__B 0 +#define QAM_LC_CP_COEF__W 8 +#define QAM_LC_CP_COEF__M 0xFF +#define QAM_LC_CP_COEF__PRE 0x64 + +#define QAM_LC_CI__A 0x1450015 +#define QAM_LC_CI__W 8 +#define QAM_LC_CI__M 0xFF +#define QAM_LC_CI__PRE 0x32 + +#define QAM_LC_CI_COEF__B 0 +#define QAM_LC_CI_COEF__W 8 +#define QAM_LC_CI_COEF__M 0xFF +#define QAM_LC_CI_COEF__PRE 0x32 + +#define QAM_LC_EP__A 0x1450016 +#define QAM_LC_EP__W 6 +#define QAM_LC_EP__M 0x3F +#define QAM_LC_EP__PRE 0x0 + +#define QAM_LC_EP_COEF__B 0 +#define QAM_LC_EP_COEF__W 6 +#define QAM_LC_EP_COEF__M 0x3F +#define QAM_LC_EP_COEF__PRE 0x0 + +#define QAM_LC_EI__A 0x1450017 +#define QAM_LC_EI__W 6 +#define QAM_LC_EI__M 0x3F +#define QAM_LC_EI__PRE 0x0 + +#define QAM_LC_EI_COEF__B 0 +#define QAM_LC_EI_COEF__W 6 +#define QAM_LC_EI_COEF__M 0x3F +#define QAM_LC_EI_COEF__PRE 0x0 + +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x0 + +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 + +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 + +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x2 + +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 + +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x3 + +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 + +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x4 + +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 + +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x5 + +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 + +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x6 + +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 + +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x8 + +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 + +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x9 + +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 + +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0xA + +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA + +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0xC + +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC + +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0xF + +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF + +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x10 + +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 + +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x14 + +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 + +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x19 + +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 + +#define QAM_LC_EQ_TIMING__A 0x1450027 +#define QAM_LC_EQ_TIMING__W 10 +#define QAM_LC_EQ_TIMING__M 0x3FF +#define QAM_LC_EQ_TIMING__PRE 0x0 + +#define QAM_LC_EQ_TIMING_OFFS__B 0 +#define QAM_LC_EQ_TIMING_OFFS__W 10 +#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 + +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_LPF_FACTORP__W 3 +#define QAM_LC_LPF_FACTORP__M 0x7 +#define QAM_LC_LPF_FACTORP__PRE 0x3 + +#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 + +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORI__W 3 +#define QAM_LC_LPF_FACTORI__M 0x7 +#define QAM_LC_LPF_FACTORI__PRE 0x3 + +#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 + +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_RATE_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT__PRE 0x3 + +#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 + +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_LC_SYMBOL_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF + +#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF + +#define QAM_LC_MTA_LENGTH__A 0x145002C +#define QAM_LC_MTA_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH__PRE 0x2 + +#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 + +#define QAM_LC_AMP_ACCU__A 0x145002D +#define QAM_LC_AMP_ACCU__W 14 +#define QAM_LC_AMP_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU__PRE 0x600 + +#define QAM_LC_AMP_ACCU_ACCU__B 0 +#define QAM_LC_AMP_ACCU_ACCU__W 14 +#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 + +#define QAM_LC_FREQ_ACCU__A 0x145002E +#define QAM_LC_FREQ_ACCU__W 10 +#define QAM_LC_FREQ_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU__PRE 0x0 + +#define QAM_LC_FREQ_ACCU_ACCU__B 0 +#define QAM_LC_FREQ_ACCU_ACCU__W 10 +#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU__A 0x145002F +#define QAM_LC_RATE_ACCU__W 10 +#define QAM_LC_RATE_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU_ACCU__B 0 +#define QAM_LC_RATE_ACCU_ACCU__W 10 +#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_AMPLITUDE__A 0x1450030 +#define QAM_LC_AMPLITUDE__W 10 +#define QAM_LC_AMPLITUDE__M 0x3FF +#define QAM_LC_AMPLITUDE__PRE 0x0 + +#define QAM_LC_AMPLITUDE_SIZE__B 0 +#define QAM_LC_AMPLITUDE_SIZE__W 10 +#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 + +#define QAM_LC_RAD_ERROR__A 0x1450031 +#define QAM_LC_RAD_ERROR__W 10 +#define QAM_LC_RAD_ERROR__M 0x3FF +#define QAM_LC_RAD_ERROR__PRE 0x0 + +#define QAM_LC_RAD_ERROR_SIZE__B 0 +#define QAM_LC_RAD_ERROR_SIZE__W 10 +#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 + +#define QAM_LC_FREQ_OFFS__A 0x1450032 +#define QAM_LC_FREQ_OFFS__W 10 +#define QAM_LC_FREQ_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS__PRE 0x0 + +#define QAM_LC_FREQ_OFFS_OFFS__B 0 +#define QAM_LC_FREQ_OFFS_OFFS__W 10 +#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 + +#define QAM_LC_PHASE_ERROR__A 0x1450033 +#define QAM_LC_PHASE_ERROR__W 10 +#define QAM_LC_PHASE_ERROR__M 0x3FF +#define QAM_LC_PHASE_ERROR__PRE 0x0 + +#define QAM_LC_PHASE_ERROR_SIZE__B 0 +#define QAM_LC_PHASE_ERROR_SIZE__W 10 +#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 + + + +#define QAM_SY_COMM_EXEC__A 0x1470000 +#define QAM_SY_COMM_EXEC__W 2 +#define QAM_SY_COMM_EXEC__M 0x3 +#define QAM_SY_COMM_EXEC__PRE 0x0 +#define QAM_SY_COMM_EXEC_STOP 0x0 +#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +#define QAM_SY_COMM_EXEC_HOLD 0x2 + +#define QAM_SY_COMM_MB__A 0x1470002 +#define QAM_SY_COMM_MB__W 4 +#define QAM_SY_COMM_MB__M 0xF +#define QAM_SY_COMM_MB__PRE 0x0 +#define QAM_SY_COMM_MB_CTL__B 0 +#define QAM_SY_COMM_MB_CTL__W 1 +#define QAM_SY_COMM_MB_CTL__M 0x1 +#define QAM_SY_COMM_MB_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_CTL_OFF 0x0 +#define QAM_SY_COMM_MB_CTL_ON 0x1 +#define QAM_SY_COMM_MB_OBS__B 1 +#define QAM_SY_COMM_MB_OBS__W 1 +#define QAM_SY_COMM_MB_OBS__M 0x2 +#define QAM_SY_COMM_MB_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_OBS_OFF 0x0 +#define QAM_SY_COMM_MB_OBS_ON 0x2 +#define QAM_SY_COMM_MB_MUX_CTL__B 2 +#define QAM_SY_COMM_MB_MUX_CTL__W 1 +#define QAM_SY_COMM_MB_MUX_CTL__M 0x4 +#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0 +#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4 +#define QAM_SY_COMM_MB_MUX_OBS__B 3 +#define QAM_SY_COMM_MB_MUX_OBS__W 1 +#define QAM_SY_COMM_MB_MUX_OBS__M 0x8 +#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0 +#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8 + +#define QAM_SY_COMM_INT_REQ__A 0x1470003 +#define QAM_SY_COMM_INT_REQ__W 1 +#define QAM_SY_COMM_INT_REQ__M 0x1 +#define QAM_SY_COMM_INT_REQ__PRE 0x0 +#define QAM_SY_COMM_INT_STA__A 0x1470005 +#define QAM_SY_COMM_INT_STA__W 4 +#define QAM_SY_COMM_INT_STA__M 0xF +#define QAM_SY_COMM_INT_STA__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_MSK__A 0x1470006 +#define QAM_SY_COMM_INT_MSK__W 4 +#define QAM_SY_COMM_INT_MSK__M 0xF +#define QAM_SY_COMM_INT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_COMM_INT_STM__A 0x1470007 +#define QAM_SY_COMM_INT_STM__W 4 +#define QAM_SY_COMM_INT_STM__M 0xF +#define QAM_SY_COMM_INT_STM__PRE 0x0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_STATUS__A 0x1470010 +#define QAM_SY_STATUS__W 2 +#define QAM_SY_STATUS__M 0x3 +#define QAM_SY_STATUS__PRE 0x0 + +#define QAM_SY_STATUS_SYNC_STATE__B 0 +#define QAM_SY_STATUS_SYNC_STATE__W 2 +#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 + + +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__W 16 +#define QAM_SY_TIMEOUT__M 0xFFFF +#define QAM_SY_TIMEOUT__PRE 0x3A98 + +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__W 4 +#define QAM_SY_SYNC_LWM__M 0xF +#define QAM_SY_SYNC_LWM__PRE 0x2 + +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__W 4 +#define QAM_SY_SYNC_AWM__M 0xF +#define QAM_SY_SYNC_AWM__PRE 0x3 + +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__W 4 +#define QAM_SY_SYNC_HWM__M 0xF +#define QAM_SY_SYNC_HWM__PRE 0x5 + +#define QAM_SY_UNLOCK__A 0x1470015 +#define QAM_SY_UNLOCK__W 1 +#define QAM_SY_UNLOCK__M 0x1 +#define QAM_SY_UNLOCK__PRE 0x0 +#define QAM_SY_CONTROL_WORD__A 0x1470016 +#define QAM_SY_CONTROL_WORD__W 4 +#define QAM_SY_CONTROL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD__PRE 0x0 + +#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 + + +#define QAM_SY_SP_INV__A 0x1470017 +#define QAM_SY_SP_INV__W 1 +#define QAM_SY_SP_INV__M 0x1 +#define QAM_SY_SP_INV__PRE 0x0 +#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 +#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1 + + + +#define QAM_VD_ISS_RAM__A 0x1480000 + + + +#define QAM_VD_QSS_RAM__A 0x1490000 + + + +#define QAM_VD_SYM_RAM__A 0x14A0000 + + + + + +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__W 2 +#define SCU_COMM_EXEC__M 0x3 +#define SCU_COMM_EXEC__PRE 0x0 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 + +#define SCU_COMM_STATE__A 0x800001 +#define SCU_COMM_STATE__W 16 +#define SCU_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE__PRE 0x0 + +#define SCU_COMM_STATE_COMM_STATE__B 0 +#define SCU_COMM_STATE_COMM_STATE__W 16 +#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 + + + +#define SCU_TOP_COMM_EXEC__A 0x810000 +#define SCU_TOP_COMM_EXEC__W 2 +#define SCU_TOP_COMM_EXEC__M 0x3 +#define SCU_TOP_COMM_EXEC__PRE 0x0 +#define SCU_TOP_COMM_EXEC_STOP 0x0 +#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +#define SCU_TOP_COMM_EXEC_HOLD 0x2 + + +#define SCU_TOP_COMM_STATE__A 0x810001 +#define SCU_TOP_COMM_STATE__W 16 +#define SCU_TOP_COMM_STATE__M 0xFFFF +#define SCU_TOP_COMM_STATE__PRE 0x0 +#define SCU_TOP_MWAIT_CTR__A 0x810010 +#define SCU_TOP_MWAIT_CTR__W 2 +#define SCU_TOP_MWAIT_CTR__M 0x3 +#define SCU_TOP_MWAIT_CTR__PRE 0x0 + +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 + +#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 + + + +#define SCU_LOW_RAM__A 0x820000 + +#define SCU_LOW_RAM_LOW__B 0 +#define SCU_LOW_RAM_LOW__W 16 +#define SCU_LOW_RAM_LOW__M 0xFFFF +#define SCU_LOW_RAM_LOW__PRE 0x0 + + + +#define SCU_HIGH_RAM__A 0x830000 + +#define SCU_HIGH_RAM_HIGH__B 0 +#define SCU_HIGH_RAM_HIGH__W 16 +#define SCU_HIGH_RAM_HIGH__M 0xFFFF +#define SCU_HIGH_RAM_HIGH__PRE 0x0 + + + + + + +#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF +#define SCU_RAM_DRIVER_DEBUG__W 16 +#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF +#define SCU_RAM_DRIVER_DEBUG__PRE 0x0 + +#define SCU_RAM_SP__A 0x831EC0 +#define SCU_RAM_SP__W 16 +#define SCU_RAM_SP__M 0xFFFF +#define SCU_RAM_SP__PRE 0x0 + +#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1 +#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16 +#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF +#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0 + +#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2 +#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16 +#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF +#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0 + +#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3 +#define SCU_RAM_QAM_NO_ACQ_CNT__W 16 +#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF +#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 +#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16 +#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF +#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0 + +#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__W 2 +#define SCU_RAM_GPIO__M 0x3 +#define SCU_RAM_GPIO__PRE 0x0 + +#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 + +#define SCU_RAM_GPIO_VSYNC_IND__B 1 +#define SCU_RAM_GPIO_VSYNC_IND__W 1 +#define SCU_RAM_GPIO_VSYNC_IND__M 0x2 +#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0 +#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 + + +#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 + +#define SCU_RAM_INHIBIT_1__A 0x831ECC +#define SCU_RAM_INHIBIT_1__W 16 +#define SCU_RAM_INHIBIT_1__M 0xFFFF +#define SCU_RAM_INHIBIT_1__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +#define SCU_RAM_HTOL_BUF_0__W 16 +#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +#define SCU_RAM_HTOL_BUF_0__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +#define SCU_RAM_HTOL_BUF_1__W 16 +#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +#define SCU_RAM_HTOL_BUF_1__PRE 0x0 + +#define SCU_RAM_INHIBIT_2__A 0x831ECF +#define SCU_RAM_INHIBIT_2__W 16 +#define SCU_RAM_INHIBIT_2__M 0xFFFF +#define SCU_RAM_INHIBIT_2__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +#define SCU_RAM_TR_SHORT_BUF_0__W 16 +#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +#define SCU_RAM_TR_SHORT_BUF_1__W 16 +#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +#define SCU_RAM_TR_LONG_BUF_0__W 16 +#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +#define SCU_RAM_TR_LONG_BUF_1__W 16 +#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +#define SCU_RAM_TR_LONG_BUF_2__W 16 +#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +#define SCU_RAM_TR_LONG_BUF_3__W 16 +#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +#define SCU_RAM_TR_LONG_BUF_4__W 16 +#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +#define SCU_RAM_TR_LONG_BUF_5__W 16 +#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +#define SCU_RAM_TR_LONG_BUF_6__W 16 +#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +#define SCU_RAM_TR_LONG_BUF_7__W 16 +#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +#define SCU_RAM_TR_LONG_BUF_8__W 16 +#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +#define SCU_RAM_TR_LONG_BUF_9__W 16 +#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +#define SCU_RAM_TR_LONG_BUF_10__W 16 +#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +#define SCU_RAM_TR_LONG_BUF_11__W 16 +#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +#define SCU_RAM_TR_LONG_BUF_12__W 16 +#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +#define SCU_RAM_TR_LONG_BUF_13__W 16 +#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +#define SCU_RAM_TR_LONG_BUF_14__W 16 +#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +#define SCU_RAM_TR_LONG_BUF_15__W 16 +#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +#define SCU_RAM_TR_LONG_BUF_16__W 16 +#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +#define SCU_RAM_TR_LONG_BUF_17__W 16 +#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +#define SCU_RAM_TR_LONG_BUF_18__W 16 +#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +#define SCU_RAM_TR_LONG_BUF_19__W 16 +#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +#define SCU_RAM_TR_LONG_BUF_20__W 16 +#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +#define SCU_RAM_TR_LONG_BUF_21__W 16 +#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +#define SCU_RAM_TR_LONG_BUF_22__W 16 +#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +#define SCU_RAM_TR_LONG_BUF_23__W 16 +#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +#define SCU_RAM_TR_LONG_BUF_24__W 16 +#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +#define SCU_RAM_TR_LONG_BUF_25__W 16 +#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +#define SCU_RAM_TR_LONG_BUF_26__W 16 +#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +#define SCU_RAM_TR_LONG_BUF_27__W 16 +#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +#define SCU_RAM_TR_LONG_BUF_28__W 16 +#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +#define SCU_RAM_TR_LONG_BUF_29__W 16 +#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +#define SCU_RAM_TR_LONG_BUF_30__W 16 +#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +#define SCU_RAM_TR_LONG_BUF_31__W 16 +#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +#define SCU_RAM_ATV_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +#define SCU_RAM_ATV_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF + +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF + +#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +#define SCU_RAM_ATV_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +#define SCU_RAM_ATV_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 + +#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +#define SCU_RAM_ATV_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +#define SCU_RAM_ATV_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +#define SCU_RAM_ATV_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +#define SCU_RAM_ATV_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF__A 0x831EFA +#define SCU_RAM_ATV_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +#define SCU_RAM_ATV_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64 + +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64 + +#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +#define SCU_RAM_ATV_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104 + +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104 + +#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +#define SCU_RAM_ATV_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +#define SCU_RAM_ATV_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445 + +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445 + +#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223 + +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223 + + +#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01 +#define SCU_RAM_OFDM_AGC_POW_TGT__W 15 +#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF +#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848 + +#define SCU_RAM_OFDM_RSV_01__A 0x831F02 +#define SCU_RAM_OFDM_RSV_01__W 16 +#define SCU_RAM_OFDM_RSV_01__M 0xFFFF +#define SCU_RAM_OFDM_RSV_01__PRE 0x0 + +#define SCU_RAM_OFDM_RSV_02__A 0x831F03 +#define SCU_RAM_OFDM_RSV_02__W 16 +#define SCU_RAM_OFDM_RSV_02__M 0xFFFF +#define SCU_RAM_OFDM_RSV_02__PRE 0x0 +#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04 +#define SCU_RAM_FEC_PRE_RS_BER__W 16 +#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0 +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06 +#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16 +#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16 +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07 +#define SCU_RAM_ATV_VSYNC_PERIOD__W 16 +#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16 +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_FREE_7944__A 0x831F08 +#define SCU_RAM_FREE_7944__W 16 +#define SCU_RAM_FREE_7944__M 0xFFFF +#define SCU_RAM_FREE_7944__PRE 0x0 + +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7945__A 0x831F09 +#define SCU_RAM_FREE_7945__W 16 +#define SCU_RAM_FREE_7945__M 0xFFFF +#define SCU_RAM_FREE_7945__PRE 0x0 + +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7946__A 0x831F0A +#define SCU_RAM_FREE_7946__W 16 +#define SCU_RAM_FREE_7946__M 0xFFFF +#define SCU_RAM_FREE_7946__PRE 0x0 + +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7947__A 0x831F0B +#define SCU_RAM_FREE_7947__W 16 +#define SCU_RAM_FREE_7947__M 0xFFFF +#define SCU_RAM_FREE_7947__PRE 0x0 + +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7948__A 0x831F0C +#define SCU_RAM_FREE_7948__W 16 +#define SCU_RAM_FREE_7948__M 0xFFFF +#define SCU_RAM_FREE_7948__PRE 0x0 + +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7949__A 0x831F0D +#define SCU_RAM_FREE_7949__W 16 +#define SCU_RAM_FREE_7949__M 0xFFFF +#define SCU_RAM_FREE_7949__PRE 0x0 + +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7950__A 0x831F0E +#define SCU_RAM_FREE_7950__W 16 +#define SCU_RAM_FREE_7950__M 0xFFFF +#define SCU_RAM_FREE_7950__PRE 0x0 + +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7951__A 0x831F0F +#define SCU_RAM_FREE_7951__W 16 +#define SCU_RAM_FREE_7951__M 0xFFFF +#define SCU_RAM_FREE_7951__PRE 0x0 + +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7952__A 0x831F10 +#define SCU_RAM_FREE_7952__W 16 +#define SCU_RAM_FREE_7952__M 0xFFFF +#define SCU_RAM_FREE_7952__PRE 0x0 + +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7953__A 0x831F11 +#define SCU_RAM_FREE_7953__W 16 +#define SCU_RAM_FREE_7953__M 0xFFFF +#define SCU_RAM_FREE_7953__PRE 0x0 + +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7954__A 0x831F12 +#define SCU_RAM_FREE_7954__W 16 +#define SCU_RAM_FREE_7954__M 0xFFFF +#define SCU_RAM_FREE_7954__PRE 0x0 + +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7955__A 0x831F13 +#define SCU_RAM_FREE_7955__W 16 +#define SCU_RAM_FREE_7955__M 0xFFFF +#define SCU_RAM_FREE_7955__PRE 0x0 + +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0 + + +#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14 +#define SCU_RAM_ADC_COMP_CONTROL__W 3 +#define SCU_RAM_ADC_COMP_CONTROL__M 0x7 +#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0 +#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0 +#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1 +#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2 +#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3 + + +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32 + +#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16 +#define SCU_RAM_AGC_KI_CYCCNT__W 16 +#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 +#define SCU_RAM_AGC_KI_CYCLEN__W 16 +#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 +#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF + +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01 + +#define SCU_RAM_AGC_RF_MAX__A 0x831F1B +#define SCU_RAM_AGC_RF_MAX__W 15 +#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF +#define SCU_RAM_FREE_7964__A 0x831F1C +#define SCU_RAM_FREE_7964__W 16 +#define SCU_RAM_FREE_7964__M 0xFFFF +#define SCU_RAM_FREE_7964__PRE 0x0 + +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7965__A 0x831F1D +#define SCU_RAM_FREE_7965__W 16 +#define SCU_RAM_FREE_7965__M 0xFFFF +#define SCU_RAM_FREE_7965__PRE 0x0 + +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7966__A 0x831F1E +#define SCU_RAM_FREE_7966__W 16 +#define SCU_RAM_FREE_7966__M 0xFFFF +#define SCU_RAM_FREE_7966__PRE 0x0 + +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7967__A 0x831F1F +#define SCU_RAM_FREE_7967__W 16 +#define SCU_RAM_FREE_7967__M 0xFFFF +#define SCU_RAM_FREE_7967__PRE 0x0 + +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20 +#define SCU_RAM_QAM_PARAM_MIRRORING__W 8 +#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF +#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1 + +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2 + +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4 + +#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21 +#define SCU_RAM_QAM_PARAM_OPTIONS__W 8 +#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF +#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1 + +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2 + +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10 + +#define SCU_RAM_FREE_7970__A 0x831F22 +#define SCU_RAM_FREE_7970__W 16 +#define SCU_RAM_FREE_7970__M 0xFFFF +#define SCU_RAM_FREE_7970__PRE 0x0 + +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7971__A 0x831F23 +#define SCU_RAM_FREE_7971__W 16 +#define SCU_RAM_FREE_7971__M 0xFFFF +#define SCU_RAM_FREE_7971__PRE 0x0 + +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG__A 0x831F24 +#define SCU_RAM_AGC_CONFIG__W 16 +#define SCU_RAM_AGC_CONFIG__M 0xFFFF +#define SCU_RAM_AGC_CONFIG__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI__A 0x831F25 +#define SCU_RAM_AGC_KI__W 15 +#define SCU_RAM_AGC_KI__M 0x7FFF +#define SCU_RAM_AGC_KI__PRE 0x22A + +#define SCU_RAM_AGC_KI_DGAIN__B 0 +#define SCU_RAM_AGC_KI_DGAIN__W 4 +#define SCU_RAM_AGC_KI_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA + +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__W 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI_RF__PRE 0x20 + +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__W 4 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_IF__PRE 0x200 + +#define SCU_RAM_AGC_KI_RED__A 0x831F26 +#define SCU_RAM_AGC_KI_RED__W 6 +#define SCU_RAM_AGC_KI_RED__M 0x3F +#define SCU_RAM_AGC_KI_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 + + +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 +#define SCU_RAM_AGC_KI_MINGAIN__W 16 +#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 +#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +#define SCU_RAM_AGC_KI_MIN__A 0x831F2B +#define SCU_RAM_AGC_KI_MIN__W 12 +#define SCU_RAM_AGC_KI_MIN__M 0xFFF +#define SCU_RAM_AGC_KI_MIN__PRE 0x111 + +#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1 + +#define SCU_RAM_AGC_KI_MIN_RF__B 4 +#define SCU_RAM_AGC_KI_MIN_RF__W 4 +#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10 + +#define SCU_RAM_AGC_KI_MIN_IF__B 8 +#define SCU_RAM_AGC_KI_MIN_IF__W 4 +#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100 + +#define SCU_RAM_AGC_KI_MAX__A 0x831F2C +#define SCU_RAM_AGC_KI_MAX__W 12 +#define SCU_RAM_AGC_KI_MAX__M 0xFFF +#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF + +#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF + +#define SCU_RAM_AGC_KI_MAX_RF__B 4 +#define SCU_RAM_AGC_KI_MAX_RF__W 4 +#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0 + +#define SCU_RAM_AGC_KI_MAX_IF__B 8 +#define SCU_RAM_AGC_KI_MAX_IF__W 4 +#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00 + + +#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D +#define SCU_RAM_AGC_CLP_SUM__W 16 +#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E +#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8 + +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F +#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400 + +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 +#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 +#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 +#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC + +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 +#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 +#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1 + +#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 +#define SCU_RAM_AGC_SNS_SUM__W 16 +#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 +#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8 + +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 +#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400 + +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 +#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 +#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC + +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A +#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B +#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1 + +#define SCU_RAM_AGC_INGAIN__A 0x831F3C +#define SCU_RAM_AGC_INGAIN__W 16 +#define SCU_RAM_AGC_INGAIN__M 0xFFFF +#define SCU_RAM_AGC_INGAIN__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D +#define SCU_RAM_AGC_INGAIN_TGT__W 15 +#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF + +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 +#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 +#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C + +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 +#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 +#define SCU_RAM_ATV_STANDARD__A 0x831F48 +#define SCU_RAM_ATV_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD__PRE 0x2 + +#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 + +#define SCU_RAM_ATV_DETECT__A 0x831F49 +#define SCU_RAM_ATV_DETECT__W 1 +#define SCU_RAM_ATV_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_DETECT__B 0 +#define SCU_RAM_ATV_DETECT_DETECT__W 1 +#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 + +#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +#define SCU_RAM_ATV_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F + +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F + +#define SCU_RAM_ATV_LOCK__A 0x831F4B +#define SCU_RAM_ATV_LOCK__W 2 +#define SCU_RAM_ATV_LOCK__M 0x3 +#define SCU_RAM_ATV_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 + +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 + +#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +#define SCU_RAM_ATV_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +#define SCU_RAM_ATV_AGC_MODE__W 8 +#define SCU_RAM_ATV_AGC_MODE__M 0xFF +#define SCU_RAM_ATV_AGC_MODE__PRE 0x50 + +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 + +#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 + +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 + +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 + +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 + + +#define SCU_RAM_ATV_RSV_01__A 0x831F4E +#define SCU_RAM_ATV_RSV_01__W 16 +#define SCU_RAM_ATV_RSV_01__M 0xFFFF +#define SCU_RAM_ATV_RSV_01__PRE 0x0 + +#define SCU_RAM_ATV_RSV_02__A 0x831F4F +#define SCU_RAM_ATV_RSV_02__W 16 +#define SCU_RAM_ATV_RSV_02__M 0xFFFF +#define SCU_RAM_ATV_RSV_02__PRE 0x0 + +#define SCU_RAM_ATV_RSV_03__A 0x831F50 +#define SCU_RAM_ATV_RSV_03__W 16 +#define SCU_RAM_ATV_RSV_03__M 0xFFFF +#define SCU_RAM_ATV_RSV_03__PRE 0x0 + +#define SCU_RAM_ATV_RSV_04__A 0x831F51 +#define SCU_RAM_ATV_RSV_04__W 16 +#define SCU_RAM_ATV_RSV_04__M 0xFFFF +#define SCU_RAM_ATV_RSV_04__PRE 0x0 +#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA + +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA + +#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC + +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A + +#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +#define SCU_RAM_ATV_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +#define SCU_RAM_ATV_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56 +#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16 +#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0 +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16 +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57 +#define SCU_RAM_ATV_BPC_REF_CNT__W 16 +#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0 +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16 +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_07__A 0x831F58 +#define SCU_RAM_ATV_RSV_07__W 16 +#define SCU_RAM_ATV_RSV_07__M 0xFFFF +#define SCU_RAM_ATV_RSV_07__PRE 0x0 + +#define SCU_RAM_ATV_RSV_08__A 0x831F59 +#define SCU_RAM_ATV_RSV_08__W 16 +#define SCU_RAM_ATV_RSV_08__M 0xFFFF +#define SCU_RAM_ATV_RSV_08__PRE 0x0 + +#define SCU_RAM_ATV_RSV_09__A 0x831F5A +#define SCU_RAM_ATV_RSV_09__W 16 +#define SCU_RAM_ATV_RSV_09__M 0xFFFF +#define SCU_RAM_ATV_RSV_09__PRE 0x0 + +#define SCU_RAM_ATV_RSV_10__A 0x831F5B +#define SCU_RAM_ATV_RSV_10__W 16 +#define SCU_RAM_ATV_RSV_10__M 0xFFFF +#define SCU_RAM_ATV_RSV_10__PRE 0x0 + +#define SCU_RAM_ATV_RSV_11__A 0x831F5C +#define SCU_RAM_ATV_RSV_11__W 16 +#define SCU_RAM_ATV_RSV_11__M 0xFFFF +#define SCU_RAM_ATV_RSV_11__PRE 0x0 + +#define SCU_RAM_ATV_RSV_12__A 0x831F5D +#define SCU_RAM_ATV_RSV_12__W 16 +#define SCU_RAM_ATV_RSV_12__M 0xFFFF +#define SCU_RAM_ATV_RSV_12__PRE 0x0 +#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000 + +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000 + +#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_13__A 0x831F60 +#define SCU_RAM_ATV_RSV_13__W 16 +#define SCU_RAM_ATV_RSV_13__M 0xFFFF +#define SCU_RAM_ATV_RSV_13__PRE 0x0 + +#define SCU_RAM_ATV_RSV_14__A 0x831F61 +#define SCU_RAM_ATV_RSV_14__W 16 +#define SCU_RAM_ATV_RSV_14__M 0xFFFF +#define SCU_RAM_ATV_RSV_14__PRE 0x0 + +#define SCU_RAM_ATV_RSV_15__A 0x831F62 +#define SCU_RAM_ATV_RSV_15__W 16 +#define SCU_RAM_ATV_RSV_15__M 0xFFFF +#define SCU_RAM_ATV_RSV_15__PRE 0x0 + +#define SCU_RAM_ATV_RSV_16__A 0x831F63 +#define SCU_RAM_ATV_RSV_16__W 16 +#define SCU_RAM_ATV_RSV_16__M 0xFFFF +#define SCU_RAM_ATV_RSV_16__PRE 0x0 +#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +#define SCU_RAM_ATV_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7 + +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7 + +#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +#define SCU_RAM_ATV_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80 + +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80 + + +#define SCU_RAM_ATV_RSV_17__A 0x831F66 +#define SCU_RAM_ATV_RSV_17__W 16 +#define SCU_RAM_ATV_RSV_17__M 0xFFFF +#define SCU_RAM_ATV_RSV_17__PRE 0x0 + +#define SCU_RAM_ATV_RSV_18__A 0x831F67 +#define SCU_RAM_ATV_RSV_18__W 16 +#define SCU_RAM_ATV_RSV_18__M 0xFFFF +#define SCU_RAM_ATV_RSV_18__PRE 0x0 + +#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +#define SCU_RAM_ATV_RATE_OFS__W 12 +#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +#define SCU_RAM_ATV_LO_INCR__W 12 +#define SCU_RAM_ATV_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +#define SCU_RAM_ATV_IIR_CRIT__W 12 +#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 + +#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 +#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +#define SCU_RAM_ATV_MOD_CONTROL__W 12 +#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 + +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667 + +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667 + +#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337 + +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337 + +#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447 + +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447 + +#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225 + +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225 + +#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14 + +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 + +#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1 + +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13 + +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13 + +#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +#define SCU_RAM_QAM_WR_RSV_0__W 16 +#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +#define SCU_RAM_QAM_WR_RSV_5__W 16 +#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +#define SCU_RAM_QAM_WR_RSV_6__W 16 +#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +#define SCU_RAM_QAM_WR_RSV_7__W 16 +#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +#define SCU_RAM_QAM_WR_RSV_8__W 16 +#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +#define SCU_RAM_QAM_WR_RSV_9__W 16 +#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +#define SCU_RAM_QAM_WR_RSV_10__W 16 +#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258 + +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +#define SCU_RAM_QAM_FSM_ATH__W 16 +#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__W 16 +#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B + +#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D + +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__W 16 +#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C + +#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 + +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__W 16 +#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH__PRE 0x64 + +#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 + +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__W 16 +#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E + +#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 + +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__W 16 +#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH__PRE 0x50 + +#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C + +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__W 16 +#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH__PRE 0x96 + +#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 + +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28 + +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF + +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 + +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4 + +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 + +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__W 16 +#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF + +#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF + +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64 + +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64 + +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E + +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E + +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__W 16 +#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32 + +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32 + +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E + +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E + +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__W 16 +#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__W 16 +#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC + +#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC + +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__W 16 +#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC + +#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC + +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 + +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 + +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 + +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 + +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 + +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00 + +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00 + +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 + +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE + +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A + +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 + +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 + +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF + +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 + +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 + +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 + +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D + +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 + +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 + +#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +#define SCU_RAM_QAM_CTL_ENA__W 16 +#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF + +#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1 + +#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2 + +#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4 + +#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8 + +#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10 + +#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20 + +#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40 + +#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80 + +#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100 + +#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200 + +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400 + +#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +#define SCU_RAM_QAM_WR_RSV_1__W 16 +#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +#define SCU_RAM_QAM_WR_RSV_2__W 16 +#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +#define SCU_RAM_QAM_WR_RSV_3__W 16 +#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE + +#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +#define SCU_RAM_QAM_RD_RSV_4__W 16 +#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED__A 0x831FBA +#define SCU_RAM_QAM_LOCKED__W 16 +#define SCU_RAM_QAM_LOCKED__M 0xFFFF +#define SCU_RAM_QAM_LOCKED__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 + +#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 + +#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +#define SCU_RAM_QAM_RD_RSV_5__W 16 +#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +#define SCU_RAM_QAM_RD_RSV_6__W 16 +#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +#define SCU_RAM_QAM_RD_RSV_7__W 16 +#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +#define SCU_RAM_QAM_RD_RSV_8__W 16 +#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +#define SCU_RAM_QAM_RD_RSV_9__W 16 +#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +#define SCU_RAM_QAM_RD_RSV_10__W 16 +#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +#define SCU_RAM_QAM_FSM_STATE__W 4 +#define SCU_RAM_QAM_FSM_STATE__M 0xF +#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E + +#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +#define SCU_RAM_QAM_ERR_STATE__W 4 +#define SCU_RAM_QAM_ERR_STATE__M 0xF +#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +#define SCU_RAM_QAM_EQ_LOCK__W 1 +#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +#define SCU_RAM_QAM_EQ_STATE__W 16 +#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +#define SCU_RAM_QAM_RD_RSV_0__W 16 +#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +#define SCU_RAM_QAM_RD_RSV_1__W 16 +#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +#define SCU_RAM_QAM_RD_RSV_2__W 16 +#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +#define SCU_RAM_QAM_RD_RSV_3__W 16 +#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 + + +#define SCU_RAM_FREE_8151__A 0x831FD7 +#define SCU_RAM_FREE_8151__W 16 +#define SCU_RAM_FREE_8151__M 0xFFFF +#define SCU_RAM_FREE_8151__PRE 0x0 + +#define SCU_RAM_FREE_8152__A 0x831FD8 +#define SCU_RAM_FREE_8152__W 16 +#define SCU_RAM_FREE_8152__M 0xFFFF +#define SCU_RAM_FREE_8152__PRE 0x0 + +#define SCU_RAM_FREE_8153__A 0x831FD9 +#define SCU_RAM_FREE_8153__W 16 +#define SCU_RAM_FREE_8153__M 0xFFFF +#define SCU_RAM_FREE_8153__PRE 0x0 + +#define SCU_RAM_FREE_8154__A 0x831FDA +#define SCU_RAM_FREE_8154__W 16 +#define SCU_RAM_FREE_8154__M 0xFFFF +#define SCU_RAM_FREE_8154__PRE 0x0 + +#define SCU_RAM_FREE_8155__A 0x831FDB +#define SCU_RAM_FREE_8155__W 16 +#define SCU_RAM_FREE_8155__M 0xFFFF +#define SCU_RAM_FREE_8155__PRE 0x0 + +#define SCU_RAM_FREE_8156__A 0x831FDC +#define SCU_RAM_FREE_8156__W 16 +#define SCU_RAM_FREE_8156__M 0xFFFF +#define SCU_RAM_FREE_8156__PRE 0x0 + +#define SCU_RAM_FREE_8157__A 0x831FDD +#define SCU_RAM_FREE_8157__W 16 +#define SCU_RAM_FREE_8157__M 0xFFFF +#define SCU_RAM_FREE_8157__PRE 0x0 + +#define SCU_RAM_FREE_8158__A 0x831FDE +#define SCU_RAM_FREE_8158__W 16 +#define SCU_RAM_FREE_8158__M 0xFFFF +#define SCU_RAM_FREE_8158__PRE 0x0 + +#define SCU_RAM_FREE_8159__A 0x831FDF +#define SCU_RAM_FREE_8159__W 16 +#define SCU_RAM_FREE_8159__M 0xFFFF +#define SCU_RAM_FREE_8159__PRE 0x0 + +#define SCU_RAM_FREE_8160__A 0x831FE0 +#define SCU_RAM_FREE_8160__W 16 +#define SCU_RAM_FREE_8160__M 0xFFFF +#define SCU_RAM_FREE_8160__PRE 0x0 + +#define SCU_RAM_FREE_8161__A 0x831FE1 +#define SCU_RAM_FREE_8161__W 16 +#define SCU_RAM_FREE_8161__M 0xFFFF +#define SCU_RAM_FREE_8161__PRE 0x0 + +#define SCU_RAM_FREE_8162__A 0x831FE2 +#define SCU_RAM_FREE_8162__W 16 +#define SCU_RAM_FREE_8162__M 0xFFFF +#define SCU_RAM_FREE_8162__PRE 0x0 + +#define SCU_RAM_FREE_8163__A 0x831FE3 +#define SCU_RAM_FREE_8163__W 16 +#define SCU_RAM_FREE_8163__M 0xFFFF +#define SCU_RAM_FREE_8163__PRE 0x0 + +#define SCU_RAM_FREE_8164__A 0x831FE4 +#define SCU_RAM_FREE_8164__W 16 +#define SCU_RAM_FREE_8164__M 0xFFFF +#define SCU_RAM_FREE_8164__PRE 0x0 + +#define SCU_RAM_FREE_8165__A 0x831FE5 +#define SCU_RAM_FREE_8165__W 16 +#define SCU_RAM_FREE_8165__M 0xFFFF +#define SCU_RAM_FREE_8165__PRE 0x0 + +#define SCU_RAM_FREE_8166__A 0x831FE6 +#define SCU_RAM_FREE_8166__W 16 +#define SCU_RAM_FREE_8166__M 0xFFFF +#define SCU_RAM_FREE_8166__PRE 0x0 + +#define SCU_RAM_FREE_8167__A 0x831FE7 +#define SCU_RAM_FREE_8167__W 16 +#define SCU_RAM_FREE_8167__M 0xFFFF +#define SCU_RAM_FREE_8167__PRE 0x0 + +#define SCU_RAM_FREE_8168__A 0x831FE8 +#define SCU_RAM_FREE_8168__W 16 +#define SCU_RAM_FREE_8168__M 0xFFFF +#define SCU_RAM_FREE_8168__PRE 0x0 + +#define SCU_RAM_FREE_8169__A 0x831FE9 +#define SCU_RAM_FREE_8169__W 16 +#define SCU_RAM_FREE_8169__M 0xFFFF +#define SCU_RAM_FREE_8169__PRE 0x0 + +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E + +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_HI__W 16 +#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_DRIVER_VER_LO__W 16 +#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 + +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 + +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 + +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 + +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 + +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 + +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 + +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 + +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 + +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 + +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 + +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 + +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 + +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 + +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 + +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 + + +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC + + +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_COMMAND__W 16 +#define SCU_RAM_COMMAND__M 0xFFFF +#define SCU_RAM_COMMAND__PRE 0x0 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87 +#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 +#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1 + +#define SCU_RAM_COMMAND_STANDARD__B 8 +#define SCU_RAM_COMMAND_STANDARD__W 8 +#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 + +#define SCU_RAM_VERSION_HI__A 0x831FFE +#define SCU_RAM_VERSION_HI__W 16 +#define SCU_RAM_VERSION_HI__M 0xFFFF +#define SCU_RAM_VERSION_HI__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_LO__A 0x831FFF +#define SCU_RAM_VERSION_LO__W 16 +#define SCU_RAM_VERSION_LO__M 0xFFFF +#define SCU_RAM_VERSION_LO__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 + + + + + +#define SIO_COMM_EXEC__A 0x400000 +#define SIO_COMM_EXEC__W 2 +#define SIO_COMM_EXEC__M 0x3 +#define SIO_COMM_EXEC__PRE 0x0 +#define SIO_COMM_EXEC_STOP 0x0 +#define SIO_COMM_EXEC_ACTIVE 0x1 +#define SIO_COMM_EXEC_HOLD 0x2 + +#define SIO_COMM_STATE__A 0x400001 +#define SIO_COMM_STATE__W 16 +#define SIO_COMM_STATE__M 0xFFFF +#define SIO_COMM_STATE__PRE 0x0 +#define SIO_COMM_MB__A 0x400002 +#define SIO_COMM_MB__W 16 +#define SIO_COMM_MB__M 0xFFFF +#define SIO_COMM_MB__PRE 0x0 +#define SIO_COMM_INT_REQ__A 0x400003 +#define SIO_COMM_INT_REQ__W 16 +#define SIO_COMM_INT_REQ__M 0xFFFF +#define SIO_COMM_INT_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_HI_REQ__B 0 +#define SIO_COMM_INT_REQ_HI_REQ__W 1 +#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_SA_REQ__B 1 +#define SIO_COMM_INT_REQ_SA_REQ__W 1 +#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_BL_REQ__B 2 +#define SIO_COMM_INT_REQ_BL_REQ__W 1 +#define SIO_COMM_INT_REQ_BL_REQ__M 0x4 +#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0 + +#define SIO_COMM_INT_STA__A 0x400005 +#define SIO_COMM_INT_STA__W 16 +#define SIO_COMM_INT_STA__M 0xFFFF +#define SIO_COMM_INT_STA__PRE 0x0 +#define SIO_COMM_INT_MSK__A 0x400006 +#define SIO_COMM_INT_MSK__W 16 +#define SIO_COMM_INT_MSK__M 0xFFFF +#define SIO_COMM_INT_MSK__PRE 0x0 +#define SIO_COMM_INT_STM__A 0x400007 +#define SIO_COMM_INT_STM__W 16 +#define SIO_COMM_INT_STM__M 0xFFFF +#define SIO_COMM_INT_STM__PRE 0x0 + + + +#define SIO_TOP_COMM_EXEC__A 0x410000 +#define SIO_TOP_COMM_EXEC__W 2 +#define SIO_TOP_COMM_EXEC__M 0x3 +#define SIO_TOP_COMM_EXEC__PRE 0x0 +#define SIO_TOP_COMM_EXEC_STOP 0x0 +#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +#define SIO_TOP_COMM_EXEC_HOLD 0x2 + + +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__W 16 +#define SIO_TOP_COMM_KEY__M 0xFFFF +#define SIO_TOP_COMM_KEY__PRE 0x0 +#define SIO_TOP_COMM_KEY_KEY 0xFABA + + +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__W 16 +#define SIO_TOP_JTAGID_LO__M 0xFFFF +#define SIO_TOP_JTAGID_LO__PRE 0x0 + +#define SIO_TOP_JTAGID_HI__A 0x410013 +#define SIO_TOP_JTAGID_HI__W 16 +#define SIO_TOP_JTAGID_HI__M 0xFFFF +#define SIO_TOP_JTAGID_HI__PRE 0x0 + + + + +#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +#define SIO_HI_RA_RAM_S0_STATE__W 1 +#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +#define SIO_HI_RA_RAM_S0_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +#define SIO_HI_RA_RAM_S0_CRC__W 16 +#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +#define SIO_HI_RA_RAM_S1_STATE__W 1 +#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +#define SIO_HI_RA_RAM_S1_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +#define SIO_HI_RA_RAM_S1_CRC__W 16 +#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA__A 0x420030 +#define SIO_HI_RA_RAM_SEMA__W 1 +#define SIO_HI_RA_RAM_SEMA__M 0x1 +#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 + +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_HI_RA_RAM_RES__W 3 +#define SIO_HI_RA_RAM_RES__M 0x7 +#define SIO_HI_RA_RAM_RES__PRE 0x0 +#define SIO_HI_RA_RAM_RES_OK 0x0 +#define SIO_HI_RA_RAM_RES_ERROR 0x1 +#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 + +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_CMD__W 4 +#define SIO_HI_RA_RAM_CMD__M 0xF +#define SIO_HI_RA_RAM_CMD__PRE 0x0 +#define SIO_HI_RA_RAM_CMD_NULL 0x0 +#define SIO_HI_RA_RAM_CMD_UIO 0x1 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 + +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 + +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 + +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 + +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 + +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 + +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 + +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 + +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF + +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 + + +#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +#define SIO_HI_RA_RAM_AB_TEMP__W 16 +#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 + +#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +#define SIO_HI_RA_RAM_I2C_CTL__W 16 +#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 + + + +#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +#define SIO_HI_IF_RAM_FUN_BASE__W 12 +#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 + + + +#define SIO_HI_IF_COMM_EXEC__A 0x440000 +#define SIO_HI_IF_COMM_EXEC__W 2 +#define SIO_HI_IF_COMM_EXEC__M 0x3 +#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +#define SIO_HI_IF_COMM_EXEC_STEP 0x3 + + +#define SIO_HI_IF_COMM_STATE__A 0x440001 +#define SIO_HI_IF_COMM_STATE__W 10 +#define SIO_HI_IF_COMM_STATE__M 0x3FF +#define SIO_HI_IF_COMM_STATE__PRE 0x0 +#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +#define SIO_HI_IF_COMM_INT_REQ__W 1 +#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +#define SIO_HI_IF_COMM_INT_STA__W 1 +#define SIO_HI_IF_COMM_INT_STA__M 0x1 +#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +#define SIO_HI_IF_COMM_INT_MSK__W 1 +#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +#define SIO_HI_IF_COMM_INT_STM__W 1 +#define SIO_HI_IF_COMM_INT_STM__M 0x1 +#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 + +#define SIO_HI_IF_STK_0__A 0x440010 +#define SIO_HI_IF_STK_0__W 10 +#define SIO_HI_IF_STK_0__M 0x3FF +#define SIO_HI_IF_STK_0__PRE 0x2 + +#define SIO_HI_IF_STK_0_ADDR__B 0 +#define SIO_HI_IF_STK_0_ADDR__W 10 +#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_1__A 0x440011 +#define SIO_HI_IF_STK_1__W 10 +#define SIO_HI_IF_STK_1__M 0x3FF +#define SIO_HI_IF_STK_1__PRE 0x2 +#define SIO_HI_IF_STK_1_ADDR__B 0 +#define SIO_HI_IF_STK_1_ADDR__W 10 +#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_2__A 0x440012 +#define SIO_HI_IF_STK_2__W 10 +#define SIO_HI_IF_STK_2__M 0x3FF +#define SIO_HI_IF_STK_2__PRE 0x2 +#define SIO_HI_IF_STK_2_ADDR__B 0 +#define SIO_HI_IF_STK_2_ADDR__W 10 +#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_3__A 0x440013 +#define SIO_HI_IF_STK_3__W 10 +#define SIO_HI_IF_STK_3__M 0x3FF +#define SIO_HI_IF_STK_3__PRE 0x2 + +#define SIO_HI_IF_STK_3_ADDR__B 0 +#define SIO_HI_IF_STK_3_ADDR__W 10 +#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 + +#define SIO_HI_IF_BPT_IDX__A 0x44001F +#define SIO_HI_IF_BPT_IDX__W 1 +#define SIO_HI_IF_BPT_IDX__M 0x1 +#define SIO_HI_IF_BPT_IDX__PRE 0x0 + +#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 + +#define SIO_HI_IF_BPT__A 0x440020 +#define SIO_HI_IF_BPT__W 10 +#define SIO_HI_IF_BPT__M 0x3FF +#define SIO_HI_IF_BPT__PRE 0x2 + +#define SIO_HI_IF_BPT_ADDR__B 0 +#define SIO_HI_IF_BPT_ADDR__W 10 +#define SIO_HI_IF_BPT_ADDR__M 0x3FF +#define SIO_HI_IF_BPT_ADDR__PRE 0x2 + + + +#define SIO_CC_COMM_EXEC__A 0x450000 +#define SIO_CC_COMM_EXEC__W 2 +#define SIO_CC_COMM_EXEC__M 0x3 +#define SIO_CC_COMM_EXEC__PRE 0x0 +#define SIO_CC_COMM_EXEC_STOP 0x0 +#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +#define SIO_CC_COMM_EXEC_HOLD 0x2 + +#define SIO_CC_PLL_MODE__A 0x450010 +#define SIO_CC_PLL_MODE__W 6 +#define SIO_CC_PLL_MODE__M 0x3F +#define SIO_CC_PLL_MODE__PRE 0x0 + +#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 + +#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 + +#define SIO_CC_PLL_MODE_BYPASS__B 4 +#define SIO_CC_PLL_MODE_BYPASS__W 2 +#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 + + +#define SIO_CC_PLL_TEST__A 0x450011 +#define SIO_CC_PLL_TEST__W 8 +#define SIO_CC_PLL_TEST__M 0xFF +#define SIO_CC_PLL_TEST__PRE 0x0 + +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PLL_LOCK__W 1 +#define SIO_CC_PLL_LOCK__M 0x1 +#define SIO_CC_PLL_LOCK__PRE 0x0 +#define SIO_CC_CLK_TEST__A 0x450013 +#define SIO_CC_CLK_TEST__W 8 +#define SIO_CC_CLK_TEST__M 0xFF +#define SIO_CC_CLK_TEST__PRE 0x0 + +#define SIO_CC_CLK_TEST_SEL1__B 0 +#define SIO_CC_CLK_TEST_SEL1__W 3 +#define SIO_CC_CLK_TEST_SEL1__M 0x7 +#define SIO_CC_CLK_TEST_SEL1__PRE 0x0 + +#define SIO_CC_CLK_TEST_ENAB1__B 3 +#define SIO_CC_CLK_TEST_ENAB1__W 1 +#define SIO_CC_CLK_TEST_ENAB1__M 0x8 +#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0 + +#define SIO_CC_CLK_TEST_SEL2__B 4 +#define SIO_CC_CLK_TEST_SEL2__W 3 +#define SIO_CC_CLK_TEST_SEL2__M 0x70 +#define SIO_CC_CLK_TEST_SEL2__PRE 0x0 + +#define SIO_CC_CLK_TEST_ENAB2__B 7 +#define SIO_CC_CLK_TEST_ENAB2__W 1 +#define SIO_CC_CLK_TEST_ENAB2__M 0x80 +#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0 + +#define SIO_CC_CLK_MODE__A 0x450014 +#define SIO_CC_CLK_MODE__W 7 +#define SIO_CC_CLK_MODE__M 0x7F +#define SIO_CC_CLK_MODE__PRE 0x0 + +#define SIO_CC_CLK_MODE_DELAY__B 0 +#define SIO_CC_CLK_MODE_DELAY__W 4 +#define SIO_CC_CLK_MODE_DELAY__M 0xF +#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 + +#define SIO_CC_CLK_MODE_INVERT__B 4 +#define SIO_CC_CLK_MODE_INVERT__W 1 +#define SIO_CC_CLK_MODE_INVERT__M 0x10 +#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 + +#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0 + +#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0 + +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__W 4 +#define SIO_CC_PWD_MODE__M 0xF +#define SIO_CC_PWD_MODE__PRE 0x0 + +#define SIO_CC_PWD_MODE_LEVEL__B 0 +#define SIO_CC_PWD_MODE_LEVEL__W 3 +#define SIO_CC_PWD_MODE_LEVEL__M 0x7 +#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 + +#define SIO_CC_PWD_MODE_USE_LOCK__B 3 +#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8 +#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 + +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_SOFT_RST__W 3 +#define SIO_CC_SOFT_RST__M 0x7 +#define SIO_CC_SOFT_RST__PRE 0x0 + +#define SIO_CC_SOFT_RST_OFDM__B 0 +#define SIO_CC_SOFT_RST_OFDM__W 1 +#define SIO_CC_SOFT_RST_OFDM__M 0x1 +#define SIO_CC_SOFT_RST_OFDM__PRE 0x0 + +#define SIO_CC_SOFT_RST_SYS__B 1 +#define SIO_CC_SOFT_RST_SYS__W 1 +#define SIO_CC_SOFT_RST_SYS__M 0x2 +#define SIO_CC_SOFT_RST_SYS__PRE 0x0 + +#define SIO_CC_SOFT_RST_OSC__B 2 +#define SIO_CC_SOFT_RST_OSC__W 1 +#define SIO_CC_SOFT_RST_OSC__M 0x4 +#define SIO_CC_SOFT_RST_OSC__PRE 0x0 + + +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__W 16 +#define SIO_CC_UPDATE__M 0xFFFF +#define SIO_CC_UPDATE__PRE 0x0 +#define SIO_CC_UPDATE_KEY 0xFABA + + + +#define SIO_SA_COMM_EXEC__A 0x460000 +#define SIO_SA_COMM_EXEC__W 2 +#define SIO_SA_COMM_EXEC__M 0x3 +#define SIO_SA_COMM_EXEC__PRE 0x0 +#define SIO_SA_COMM_EXEC_STOP 0x0 +#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +#define SIO_SA_COMM_EXEC_HOLD 0x2 + +#define SIO_SA_COMM_INT_REQ__A 0x460003 +#define SIO_SA_COMM_INT_REQ__W 1 +#define SIO_SA_COMM_INT_REQ__M 0x1 +#define SIO_SA_COMM_INT_REQ__PRE 0x0 +#define SIO_SA_COMM_INT_STA__A 0x460005 +#define SIO_SA_COMM_INT_STA__W 4 +#define SIO_SA_COMM_INT_STA__M 0xF +#define SIO_SA_COMM_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK__A 0x460006 +#define SIO_SA_COMM_INT_MSK__W 4 +#define SIO_SA_COMM_INT_MSK__M 0xF +#define SIO_SA_COMM_INT_MSK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM__A 0x460007 +#define SIO_SA_COMM_INT_STM__W 4 +#define SIO_SA_COMM_INT_STM__M 0xF +#define SIO_SA_COMM_INT_STM__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_PRESCALER__A 0x460010 +#define SIO_SA_PRESCALER__W 13 +#define SIO_SA_PRESCALER__M 0x1FFF +#define SIO_SA_PRESCALER__PRE 0x18B7 +#define SIO_SA_TX_DATA0__A 0x460011 +#define SIO_SA_TX_DATA0__W 16 +#define SIO_SA_TX_DATA0__M 0xFFFF +#define SIO_SA_TX_DATA0__PRE 0x0 +#define SIO_SA_TX_DATA1__A 0x460012 +#define SIO_SA_TX_DATA1__W 16 +#define SIO_SA_TX_DATA1__M 0xFFFF +#define SIO_SA_TX_DATA1__PRE 0x0 +#define SIO_SA_TX_DATA2__A 0x460013 +#define SIO_SA_TX_DATA2__W 16 +#define SIO_SA_TX_DATA2__M 0xFFFF +#define SIO_SA_TX_DATA2__PRE 0x0 +#define SIO_SA_TX_DATA3__A 0x460014 +#define SIO_SA_TX_DATA3__W 16 +#define SIO_SA_TX_DATA3__M 0xFFFF +#define SIO_SA_TX_DATA3__PRE 0x0 +#define SIO_SA_TX_LENGTH__A 0x460015 +#define SIO_SA_TX_LENGTH__W 6 +#define SIO_SA_TX_LENGTH__M 0x3F +#define SIO_SA_TX_LENGTH__PRE 0x0 +#define SIO_SA_TX_COMMAND__A 0x460016 +#define SIO_SA_TX_COMMAND__W 2 +#define SIO_SA_TX_COMMAND__M 0x3 +#define SIO_SA_TX_COMMAND__PRE 0x3 + +#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 + +#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 + +#define SIO_SA_TX_STATUS__A 0x460017 +#define SIO_SA_TX_STATUS__W 2 +#define SIO_SA_TX_STATUS__M 0x3 +#define SIO_SA_TX_STATUS__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUSY__B 0 +#define SIO_SA_TX_STATUS_BUSY__W 1 +#define SIO_SA_TX_STATUS_BUSY__M 0x1 +#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_SA_RX_DATA0__A 0x460018 +#define SIO_SA_RX_DATA0__W 16 +#define SIO_SA_RX_DATA0__M 0xFFFF +#define SIO_SA_RX_DATA0__PRE 0x0 +#define SIO_SA_RX_DATA1__A 0x460019 +#define SIO_SA_RX_DATA1__W 16 +#define SIO_SA_RX_DATA1__M 0xFFFF +#define SIO_SA_RX_DATA1__PRE 0x0 +#define SIO_SA_RX_LENGTH__A 0x46001A +#define SIO_SA_RX_LENGTH__W 6 +#define SIO_SA_RX_LENGTH__M 0x3F +#define SIO_SA_RX_LENGTH__PRE 0x0 +#define SIO_SA_RX_COMMAND__A 0x46001B +#define SIO_SA_RX_COMMAND__W 1 +#define SIO_SA_RX_COMMAND__M 0x1 +#define SIO_SA_RX_COMMAND__PRE 0x1 + +#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 + +#define SIO_SA_RX_STATUS__A 0x46001C +#define SIO_SA_RX_STATUS__W 2 +#define SIO_SA_RX_STATUS__M 0x3 +#define SIO_SA_RX_STATUS__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUSY__B 0 +#define SIO_SA_RX_STATUS_BUSY__W 1 +#define SIO_SA_RX_STATUS_BUSY__M 0x1 +#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 + + + +#define SIO_OFDM_SH_COMM_EXEC__A 0x470000 +#define SIO_OFDM_SH_COMM_EXEC__W 2 +#define SIO_OFDM_SH_COMM_EXEC__M 0x3 +#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0 +#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0 +#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1 +#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2 + +#define SIO_OFDM_SH_COMM_MB__A 0x470002 +#define SIO_OFDM_SH_COMM_MB__W 2 +#define SIO_OFDM_SH_COMM_MB__M 0x3 +#define SIO_OFDM_SH_COMM_MB__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL__B 0 +#define SIO_OFDM_SH_COMM_MB_CTL__W 1 +#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1 +#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1 +#define SIO_OFDM_SH_COMM_MB_OBS__B 1 +#define SIO_OFDM_SH_COMM_MB_OBS__W 1 +#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2 +#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0 +#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2 + +#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2 + +#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 +#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 + +#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013 +#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3 +#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7 +#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6 + + + +#define SIO_BL_COMM_EXEC__A 0x480000 +#define SIO_BL_COMM_EXEC__W 2 +#define SIO_BL_COMM_EXEC__M 0x3 +#define SIO_BL_COMM_EXEC__PRE 0x0 +#define SIO_BL_COMM_EXEC_STOP 0x0 +#define SIO_BL_COMM_EXEC_ACTIVE 0x1 +#define SIO_BL_COMM_EXEC_HOLD 0x2 + +#define SIO_BL_COMM_INT_REQ__A 0x480003 +#define SIO_BL_COMM_INT_REQ__W 1 +#define SIO_BL_COMM_INT_REQ__M 0x1 +#define SIO_BL_COMM_INT_REQ__PRE 0x0 +#define SIO_BL_COMM_INT_STA__A 0x480005 +#define SIO_BL_COMM_INT_STA__W 1 +#define SIO_BL_COMM_INT_STA__M 0x1 +#define SIO_BL_COMM_INT_STA__PRE 0x0 + +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0 + +#define SIO_BL_COMM_INT_MSK__A 0x480006 +#define SIO_BL_COMM_INT_MSK__W 1 +#define SIO_BL_COMM_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_MSK__PRE 0x0 + +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0 + +#define SIO_BL_COMM_INT_STM__A 0x480007 +#define SIO_BL_COMM_INT_STM__W 1 +#define SIO_BL_COMM_INT_STM__M 0x1 +#define SIO_BL_COMM_INT_STM__PRE 0x0 + +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0 + +#define SIO_BL_STATUS__A 0x480010 +#define SIO_BL_STATUS__W 1 +#define SIO_BL_STATUS__M 0x1 +#define SIO_BL_STATUS__PRE 0x0 +#define SIO_BL_MODE__A 0x480011 +#define SIO_BL_MODE__W 1 +#define SIO_BL_MODE__M 0x1 +#define SIO_BL_MODE__PRE 0x1 +#define SIO_BL_MODE_DIRECT 0x0 +#define SIO_BL_MODE_CHAIN 0x1 + +#define SIO_BL_ENABLE__A 0x480012 +#define SIO_BL_ENABLE__W 1 +#define SIO_BL_ENABLE__M 0x1 +#define SIO_BL_ENABLE__PRE 0x0 +#define SIO_BL_ENABLE_OFF 0x0 +#define SIO_BL_ENABLE_ON 0x1 + +#define SIO_BL_TGT_HDR__A 0x480014 +#define SIO_BL_TGT_HDR__W 12 +#define SIO_BL_TGT_HDR__M 0xFFF +#define SIO_BL_TGT_HDR__PRE 0x0 +#define SIO_BL_TGT_HDR_BANK__B 0 +#define SIO_BL_TGT_HDR_BANK__W 6 +#define SIO_BL_TGT_HDR_BANK__M 0x3F +#define SIO_BL_TGT_HDR_BANK__PRE 0x0 +#define SIO_BL_TGT_HDR_BLOCK__B 6 +#define SIO_BL_TGT_HDR_BLOCK__W 6 +#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0 +#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0 + +#define SIO_BL_TGT_ADDR__A 0x480015 +#define SIO_BL_TGT_ADDR__W 16 +#define SIO_BL_TGT_ADDR__M 0xFFFF +#define SIO_BL_TGT_ADDR__PRE 0x0 +#define SIO_BL_SRC_ADDR__A 0x480016 +#define SIO_BL_SRC_ADDR__W 16 +#define SIO_BL_SRC_ADDR__M 0xFFFF +#define SIO_BL_SRC_ADDR__PRE 0x0 +#define SIO_BL_SRC_LEN__A 0x480017 +#define SIO_BL_SRC_LEN__W 16 +#define SIO_BL_SRC_LEN__M 0xFFFF +#define SIO_BL_SRC_LEN__PRE 0x0 + +#define SIO_BL_CHAIN_ADDR__A 0x480018 +#define SIO_BL_CHAIN_ADDR__W 16 +#define SIO_BL_CHAIN_ADDR__M 0xFFFF +#define SIO_BL_CHAIN_ADDR__PRE 0x0 + +#define SIO_BL_CHAIN_LEN__A 0x480019 +#define SIO_BL_CHAIN_LEN__W 4 +#define SIO_BL_CHAIN_LEN__M 0xF +#define SIO_BL_CHAIN_LEN__PRE 0x2 + + + +#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000 + + + +#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000 + + + +#define SIO_BL_ROM__A 0x4E0000 + + + +#define SIO_PDR_COMM_EXEC__A 0x7F0000 +#define SIO_PDR_COMM_EXEC__W 2 +#define SIO_PDR_COMM_EXEC__M 0x3 +#define SIO_PDR_COMM_EXEC__PRE 0x0 +#define SIO_PDR_COMM_EXEC_STOP 0x0 +#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +#define SIO_PDR_COMM_EXEC_HOLD 0x2 + +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MON_CFG__W 4 +#define SIO_PDR_MON_CFG__M 0xF +#define SIO_PDR_MON_CFG__PRE 0x0 + +#define SIO_PDR_MON_CFG_OSEL__B 0 +#define SIO_PDR_MON_CFG_OSEL__W 1 +#define SIO_PDR_MON_CFG_OSEL__M 0x1 +#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_IACT__B 1 +#define SIO_PDR_MON_CFG_IACT__W 1 +#define SIO_PDR_MON_CFG_IACT__M 0x2 +#define SIO_PDR_MON_CFG_IACT__PRE 0x0 + +#define SIO_PDR_MON_CFG_ISEL__B 2 +#define SIO_PDR_MON_CFG_ISEL__W 1 +#define SIO_PDR_MON_CFG_ISEL__M 0x4 +#define SIO_PDR_MON_CFG_ISEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_INV_CLK__B 3 +#define SIO_PDR_MON_CFG_INV_CLK__W 1 +#define SIO_PDR_MON_CFG_INV_CLK__M 0x8 +#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +#define SIO_PDR_SMA_RX_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 + +#define SIO_PDR_SILENT__A 0x7F0013 +#define SIO_PDR_SILENT__W 13 +#define SIO_PDR_SILENT__M 0x1FFF +#define SIO_PDR_SILENT__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_WS__B 0 +#define SIO_PDR_SILENT_I2S_WS__W 1 +#define SIO_PDR_SILENT_I2S_WS__M 0x1 +#define SIO_PDR_SILENT_I2S_WS__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_DA__B 1 +#define SIO_PDR_SILENT_I2S_DA__W 1 +#define SIO_PDR_SILENT_I2S_DA__M 0x2 +#define SIO_PDR_SILENT_I2S_DA__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_CL__B 2 +#define SIO_PDR_SILENT_I2S_CL__W 1 +#define SIO_PDR_SILENT_I2S_CL__M 0x4 +#define SIO_PDR_SILENT_I2S_CL__PRE 0x0 + +#define SIO_PDR_SILENT_I2C_SCL2__B 3 +#define SIO_PDR_SILENT_I2C_SCL2__W 1 +#define SIO_PDR_SILENT_I2C_SCL2__M 0x8 +#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0 + +#define SIO_PDR_SILENT_I2C_SDA2__B 4 +#define SIO_PDR_SILENT_I2C_SDA2__W 1 +#define SIO_PDR_SILENT_I2C_SDA2__M 0x10 +#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0 + +#define SIO_PDR_SILENT_SMA_TX__B 8 +#define SIO_PDR_SILENT_SMA_TX__W 1 +#define SIO_PDR_SILENT_SMA_TX__M 0x100 +#define SIO_PDR_SILENT_SMA_TX__PRE 0x0 + +#define SIO_PDR_SILENT_SMA_RX__B 9 +#define SIO_PDR_SILENT_SMA_RX__W 1 +#define SIO_PDR_SILENT_SMA_RX__M 0x200 +#define SIO_PDR_SILENT_SMA_RX__PRE 0x0 + +#define SIO_PDR_SILENT_GPIO__B 10 +#define SIO_PDR_SILENT_GPIO__W 1 +#define SIO_PDR_SILENT_GPIO__M 0x400 +#define SIO_PDR_SILENT_GPIO__PRE 0x0 + +#define SIO_PDR_SILENT_VSYNC__B 11 +#define SIO_PDR_SILENT_VSYNC__W 1 +#define SIO_PDR_SILENT_VSYNC__M 0x800 +#define SIO_PDR_SILENT_VSYNC__PRE 0x0 + +#define SIO_PDR_SILENT_IRQN__B 12 +#define SIO_PDR_SILENT_IRQN__W 1 +#define SIO_PDR_SILENT_IRQN__M 0x1000 +#define SIO_PDR_SILENT_IRQN__PRE 0x0 + +#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +#define SIO_PDR_UIO_IN_LO__W 16 +#define SIO_PDR_UIO_IN_LO__M 0xFFFF +#define SIO_PDR_UIO_IN_LO__PRE 0x0 +#define SIO_PDR_UIO_IN_LO_DATA__B 0 +#define SIO_PDR_UIO_IN_LO_DATA__W 16 +#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_IN_HI__W 14 +#define SIO_PDR_UIO_IN_HI__M 0x3FFF +#define SIO_PDR_UIO_IN_HI__PRE 0x0 +#define SIO_PDR_UIO_IN_HI_DATA__B 0 +#define SIO_PDR_UIO_IN_HI_DATA__W 14 +#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_PDR_UIO_OUT_LO__W 16 +#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +#define SIO_PDR_UIO_OUT_HI__W 14 +#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 + +#define SIO_PDR_PWM1_MODE__A 0x7F0018 +#define SIO_PDR_PWM1_MODE__W 2 +#define SIO_PDR_PWM1_MODE__M 0x3 +#define SIO_PDR_PWM1_MODE__PRE 0x0 +#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +#define SIO_PDR_PWM1_PRESCALE__W 6 +#define SIO_PDR_PWM1_PRESCALE__M 0x3F +#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM1_VALUE__A 0x7F001A +#define SIO_PDR_PWM1_VALUE__W 11 +#define SIO_PDR_PWM1_VALUE__M 0x7FF +#define SIO_PDR_PWM1_VALUE__PRE 0x0 + +#define SIO_PDR_IRQN_SEL__A 0x7F001B +#define SIO_PDR_IRQN_SEL__W 4 +#define SIO_PDR_IRQN_SEL__M 0xF +#define SIO_PDR_IRQN_SEL__PRE 0x3 +#define SIO_PDR_PWM2_MODE__A 0x7F001C +#define SIO_PDR_PWM2_MODE__W 2 +#define SIO_PDR_PWM2_MODE__M 0x3 +#define SIO_PDR_PWM2_MODE__PRE 0x0 +#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +#define SIO_PDR_PWM2_PRESCALE__W 6 +#define SIO_PDR_PWM2_PRESCALE__M 0x3F +#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM2_VALUE__A 0x7F001E +#define SIO_PDR_PWM2_VALUE__W 11 +#define SIO_PDR_PWM2_VALUE__M 0x7FF +#define SIO_PDR_PWM2_VALUE__PRE 0x0 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_OHW_CFG__W 7 +#define SIO_PDR_OHW_CFG__M 0x7F +#define SIO_PDR_OHW_CFG__PRE 0x0 + +#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_BYPASS__B 2 +#define SIO_PDR_OHW_CFG_BYPASS__W 1 +#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 + +#define SIO_PDR_OHW_CFG_ASEL__B 3 +#define SIO_PDR_OHW_CFG_ASEL__W 3 +#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_SPEED__B 6 +#define SIO_PDR_OHW_CFG_SPEED__W 1 +#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 + +#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +#define SIO_PDR_I2S_WS_CFG__W 9 +#define SIO_PDR_I2S_WS_CFG__M 0x1FF +#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_CFG__A 0x7F0021 +#define SIO_PDR_GPIO_CFG__W 9 +#define SIO_PDR_GPIO_CFG__M 0x1FF +#define SIO_PDR_GPIO_CFG__PRE 0x10 +#define SIO_PDR_GPIO_CFG_MODE__B 0 +#define SIO_PDR_GPIO_CFG_MODE__W 3 +#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_GPIO_CFG_KEEP__B 6 +#define SIO_PDR_GPIO_CFG_KEEP__W 2 +#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +#define SIO_PDR_GPIO_CFG_UIO__B 8 +#define SIO_PDR_GPIO_CFG_UIO__W 1 +#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MSTRT_CFG__W 9 +#define SIO_PDR_MSTRT_CFG__M 0x1FF +#define SIO_PDR_MSTRT_CFG__PRE 0x50 +#define SIO_PDR_MSTRT_CFG_MODE__B 0 +#define SIO_PDR_MSTRT_CFG_MODE__W 3 +#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MSTRT_CFG_UIO__B 8 +#define SIO_PDR_MSTRT_CFG_UIO__W 1 +#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MERR_CFG__W 9 +#define SIO_PDR_MERR_CFG__M 0x1FF +#define SIO_PDR_MERR_CFG__PRE 0x50 +#define SIO_PDR_MERR_CFG_MODE__B 0 +#define SIO_PDR_MERR_CFG_MODE__W 3 +#define SIO_PDR_MERR_CFG_MODE__M 0x7 +#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +#define SIO_PDR_MERR_CFG_DRIVE__B 3 +#define SIO_PDR_MERR_CFG_DRIVE__W 3 +#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MERR_CFG_KEEP__B 6 +#define SIO_PDR_MERR_CFG_KEEP__W 2 +#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MERR_CFG_UIO__B 8 +#define SIO_PDR_MERR_CFG_UIO__W 1 +#define SIO_PDR_MERR_CFG_UIO__M 0x100 +#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MCLK_CFG__W 9 +#define SIO_PDR_MCLK_CFG__M 0x1FF +#define SIO_PDR_MCLK_CFG__PRE 0x50 +#define SIO_PDR_MCLK_CFG_MODE__B 0 +#define SIO_PDR_MCLK_CFG_MODE__W 3 +#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MCLK_CFG_KEEP__B 6 +#define SIO_PDR_MCLK_CFG_KEEP__W 2 +#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MCLK_CFG_UIO__B 8 +#define SIO_PDR_MCLK_CFG_UIO__W 1 +#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_MVAL_CFG__W 9 +#define SIO_PDR_MVAL_CFG__M 0x1FF +#define SIO_PDR_MVAL_CFG__PRE 0x50 +#define SIO_PDR_MVAL_CFG_MODE__B 0 +#define SIO_PDR_MVAL_CFG_MODE__W 3 +#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MVAL_CFG_KEEP__B 6 +#define SIO_PDR_MVAL_CFG_KEEP__W 2 +#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MVAL_CFG_UIO__B 8 +#define SIO_PDR_MVAL_CFG_UIO__W 1 +#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +#define SIO_PDR_I2C_SCL1_CFG__W 9 +#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +#define SIO_PDR_I2C_SDA1_CFG__W 9 +#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +#define SIO_PDR_VSYNC_CFG__W 9 +#define SIO_PDR_VSYNC_CFG__M 0x1FF +#define SIO_PDR_VSYNC_CFG__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_MODE__B 0 +#define SIO_PDR_VSYNC_CFG_MODE__W 3 +#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_UIO__B 8 +#define SIO_PDR_VSYNC_CFG_UIO__W 1 +#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +#define SIO_PDR_SMA_RX_CFG__W 9 +#define SIO_PDR_SMA_RX_CFG__M 0x1FF +#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_SMA_TX_CFG__W 9 +#define SIO_PDR_SMA_TX_CFG__M 0x1FF +#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +#define SIO_PDR_I2C_SDA2_CFG__W 9 +#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +#define SIO_PDR_I2C_SCL2_CFG__W 9 +#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +#define SIO_PDR_I2S_CL_CFG__W 9 +#define SIO_PDR_I2S_CL_CFG__M 0x1FF +#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +#define SIO_PDR_I2S_DA_CFG__W 9 +#define SIO_PDR_I2S_DA_CFG__M 0x1FF +#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +#define SIO_PDR_GPIO_GPIO_FNC__W 2 +#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +#define SIO_PDR_MERR_GPIO_FNC__W 2 +#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +#define SIO_PDR_MCLK_GPIO_FNC__W 2 +#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +#define SIO_PDR_MVAL_GPIO_FNC__W 2 +#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 + +#endif + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map_b.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map_b.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map_b.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/drxk_map_b.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,4340 @@ +#define AUD_COMM_EXEC_STOP 0x0 +#define AUD_COMM_EXEC__A 0x1000000 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC__A 0x1C20000 +#define FEC_DI_INPUT_CTL__A 0x1C20016 +#define FEC_OC_AVR_PARM_A__A 0x1C40026 +#define FEC_OC_AVR_PARM_B__A 0x1C40027 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB__A 0x1C40002 +#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE__A 0x1C40014 +#define FEC_OC_DTO_PERIOD__A 0x1C40015 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE__A 0x1C4001A +#define FEC_OC_FCT_MODE__PRE 0x0 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT__A 0x1C40049 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE__A 0x1C40048 +#define FEC_OC_IPR_MODE__A 0x1C40048 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE__A 0x1C40011 +#define FEC_OC_OCR_INVERT__A 0x1C40052 +#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 +#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 +#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 +#define FEC_OC_RCN_GAIN__A 0x1C4002E +#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 +#define FEC_OC_SNC_HWM__A 0x1C40042 +#define FEC_OC_SNC_LWM__A 0x1C40041 +#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +#define FEC_OC_SNC_MODE__A 0x1C40040 +#define FEC_OC_SNC_MODE__A 0x1C40040 +#define FEC_OC_SNC_UNLOCK__A 0x1C40043 +#define FEC_OC_TMD_COUNT__A 0x1C4001F +#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 +#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 +#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 +#define FEC_OC_TMD_MODE__A 0x1C4001E +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC__A 0x1C30000 +#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AMUX_SIGNAL2ADC 0x1 +#define IQM_AF_AMUX_SIGNAL2ADC 0x1 +#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_INC_BYPASS__A 0x1870036 +#define IQM_AF_INC_LCT__A 0x1870034 +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 +#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 +#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 +#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_UPD_SEL__A 0x187002F +#define IQM_AF_UPD_SEL__A 0x187002F +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_BYPASSDET__A 0x1860067 +#define IQM_CF_BYPASSDET__A 0x1860067 +#define IQM_CF_CLP_VAL__A 0x1860060 +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_DATATH__A 0x1860061 +#define IQM_CF_DATATH__A 0x1860061 +#define IQM_CF_DET_LCT__A 0x1860064 +#define IQM_CF_DET_LCT__A 0x1860064 +#define IQM_CF_DS_ENA__A 0x1860019 +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_PKDTH__A 0x1860062 +#define IQM_CF_PKDTH__A 0x1860062 +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__PRE 0x0 +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_TAP_IM0_B__B 0 +#define IQM_CF_TAP_IM0_B__M 0x7F +#define IQM_CF_TAP_IM0_B__PRE 0x2 +#define IQM_CF_TAP_IM0_B__W 7 +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM10_B__B 0 +#define IQM_CF_TAP_IM10_B__M 0x1FF +#define IQM_CF_TAP_IM10_B__PRE 0x2 +#define IQM_CF_TAP_IM10_B__W 9 +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM11_B__B 0 +#define IQM_CF_TAP_IM11_B__M 0x1FF +#define IQM_CF_TAP_IM11_B__PRE 0x2 +#define IQM_CF_TAP_IM11_B__W 9 +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM12_B__B 0 +#define IQM_CF_TAP_IM12_B__M 0x1FF +#define IQM_CF_TAP_IM12_B__PRE 0x2 +#define IQM_CF_TAP_IM12_B__W 9 +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM13_B__B 0 +#define IQM_CF_TAP_IM13_B__M 0x1FF +#define IQM_CF_TAP_IM13_B__PRE 0x2 +#define IQM_CF_TAP_IM13_B__W 9 +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM14_B__B 0 +#define IQM_CF_TAP_IM14_B__M 0x1FF +#define IQM_CF_TAP_IM14_B__PRE 0x2 +#define IQM_CF_TAP_IM14_B__W 9 +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM15_B__B 0 +#define IQM_CF_TAP_IM15_B__M 0x1FF +#define IQM_CF_TAP_IM15_B__PRE 0x2 +#define IQM_CF_TAP_IM15_B__W 9 +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM16_B__B 0 +#define IQM_CF_TAP_IM16_B__M 0x1FF +#define IQM_CF_TAP_IM16_B__PRE 0x2 +#define IQM_CF_TAP_IM16_B__W 9 +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM17_B__B 0 +#define IQM_CF_TAP_IM17_B__M 0x1FF +#define IQM_CF_TAP_IM17_B__PRE 0x2 +#define IQM_CF_TAP_IM17_B__W 9 +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM18_B__B 0 +#define IQM_CF_TAP_IM18_B__M 0x1FF +#define IQM_CF_TAP_IM18_B__PRE 0x2 +#define IQM_CF_TAP_IM18_B__W 9 +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM19_B__B 0 +#define IQM_CF_TAP_IM19_B__M 0x1FF +#define IQM_CF_TAP_IM19_B__PRE 0x2 +#define IQM_CF_TAP_IM19_B__W 9 +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM1_B__B 0 +#define IQM_CF_TAP_IM1_B__M 0x7F +#define IQM_CF_TAP_IM1_B__PRE 0x2 +#define IQM_CF_TAP_IM1_B__W 7 +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM20_B__B 0 +#define IQM_CF_TAP_IM20_B__M 0x1FF +#define IQM_CF_TAP_IM20_B__PRE 0x2 +#define IQM_CF_TAP_IM20_B__W 9 +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM21_B__B 0 +#define IQM_CF_TAP_IM21_B__M 0x7FF +#define IQM_CF_TAP_IM21_B__PRE 0x2 +#define IQM_CF_TAP_IM21_B__W 11 +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM22_B__B 0 +#define IQM_CF_TAP_IM22_B__M 0x7FF +#define IQM_CF_TAP_IM22_B__PRE 0x2 +#define IQM_CF_TAP_IM22_B__W 11 +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM23_B__B 0 +#define IQM_CF_TAP_IM23_B__M 0x7FF +#define IQM_CF_TAP_IM23_B__PRE 0x2 +#define IQM_CF_TAP_IM23_B__W 11 +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM24_B__B 0 +#define IQM_CF_TAP_IM24_B__M 0x7FF +#define IQM_CF_TAP_IM24_B__PRE 0x2 +#define IQM_CF_TAP_IM24_B__W 11 +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM25_B__B 0 +#define IQM_CF_TAP_IM25_B__M 0x7FF +#define IQM_CF_TAP_IM25_B__PRE 0x2 +#define IQM_CF_TAP_IM25_B__W 11 +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM26_B__B 0 +#define IQM_CF_TAP_IM26_B__M 0x7FF +#define IQM_CF_TAP_IM26_B__PRE 0x2 +#define IQM_CF_TAP_IM26_B__W 11 +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM27_B__B 0 +#define IQM_CF_TAP_IM27_B__M 0x7FF +#define IQM_CF_TAP_IM27_B__PRE 0x2 +#define IQM_CF_TAP_IM27_B__W 11 +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM2_B__B 0 +#define IQM_CF_TAP_IM2_B__M 0x7F +#define IQM_CF_TAP_IM2_B__PRE 0x2 +#define IQM_CF_TAP_IM2_B__W 7 +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM3_B__B 0 +#define IQM_CF_TAP_IM3_B__M 0x7F +#define IQM_CF_TAP_IM3_B__PRE 0x2 +#define IQM_CF_TAP_IM3_B__W 7 +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM4_B__B 0 +#define IQM_CF_TAP_IM4_B__M 0x7F +#define IQM_CF_TAP_IM4_B__PRE 0x2 +#define IQM_CF_TAP_IM4_B__W 7 +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM5_B__B 0 +#define IQM_CF_TAP_IM5_B__M 0x7F +#define IQM_CF_TAP_IM5_B__PRE 0x2 +#define IQM_CF_TAP_IM5_B__W 7 +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM6_B__B 0 +#define IQM_CF_TAP_IM6_B__M 0x7F +#define IQM_CF_TAP_IM6_B__PRE 0x2 +#define IQM_CF_TAP_IM6_B__W 7 +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM7_B__B 0 +#define IQM_CF_TAP_IM7_B__M 0x1FF +#define IQM_CF_TAP_IM7_B__PRE 0x2 +#define IQM_CF_TAP_IM7_B__W 9 +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM8_B__B 0 +#define IQM_CF_TAP_IM8_B__M 0x1FF +#define IQM_CF_TAP_IM8_B__PRE 0x2 +#define IQM_CF_TAP_IM8_B__W 9 +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM9_B__B 0 +#define IQM_CF_TAP_IM9_B__M 0x1FF +#define IQM_CF_TAP_IM9_B__PRE 0x2 +#define IQM_CF_TAP_IM9_B__W 9 +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_RE0_B__B 0 +#define IQM_CF_TAP_RE0_B__M 0x7F +#define IQM_CF_TAP_RE0_B__PRE 0x2 +#define IQM_CF_TAP_RE0_B__W 7 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE10_B__B 0 +#define IQM_CF_TAP_RE10_B__M 0x1FF +#define IQM_CF_TAP_RE10_B__PRE 0x2 +#define IQM_CF_TAP_RE10_B__W 9 +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE11_B__B 0 +#define IQM_CF_TAP_RE11_B__M 0x1FF +#define IQM_CF_TAP_RE11_B__PRE 0x2 +#define IQM_CF_TAP_RE11_B__W 9 +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE12_B__B 0 +#define IQM_CF_TAP_RE12_B__M 0x1FF +#define IQM_CF_TAP_RE12_B__PRE 0x2 +#define IQM_CF_TAP_RE12_B__W 9 +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE13_B__B 0 +#define IQM_CF_TAP_RE13_B__M 0x1FF +#define IQM_CF_TAP_RE13_B__PRE 0x2 +#define IQM_CF_TAP_RE13_B__W 9 +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE14_B__B 0 +#define IQM_CF_TAP_RE14_B__M 0x1FF +#define IQM_CF_TAP_RE14_B__PRE 0x2 +#define IQM_CF_TAP_RE14_B__W 9 +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE15_B__B 0 +#define IQM_CF_TAP_RE15_B__M 0x1FF +#define IQM_CF_TAP_RE15_B__PRE 0x2 +#define IQM_CF_TAP_RE15_B__W 9 +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE16_B__B 0 +#define IQM_CF_TAP_RE16_B__M 0x1FF +#define IQM_CF_TAP_RE16_B__PRE 0x2 +#define IQM_CF_TAP_RE16_B__W 9 +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE17_B__B 0 +#define IQM_CF_TAP_RE17_B__M 0x1FF +#define IQM_CF_TAP_RE17_B__PRE 0x2 +#define IQM_CF_TAP_RE17_B__W 9 +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE18_B__B 0 +#define IQM_CF_TAP_RE18_B__M 0x1FF +#define IQM_CF_TAP_RE18_B__PRE 0x2 +#define IQM_CF_TAP_RE18_B__W 9 +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE19_B__B 0 +#define IQM_CF_TAP_RE19_B__M 0x1FF +#define IQM_CF_TAP_RE19_B__PRE 0x2 +#define IQM_CF_TAP_RE19_B__W 9 +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE1_B__B 0 +#define IQM_CF_TAP_RE1_B__M 0x7F +#define IQM_CF_TAP_RE1_B__PRE 0x2 +#define IQM_CF_TAP_RE1_B__W 7 +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE20_B__B 0 +#define IQM_CF_TAP_RE20_B__M 0x1FF +#define IQM_CF_TAP_RE20_B__PRE 0x2 +#define IQM_CF_TAP_RE20_B__W 9 +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE21_B__B 0 +#define IQM_CF_TAP_RE21_B__M 0x7FF +#define IQM_CF_TAP_RE21_B__PRE 0x2 +#define IQM_CF_TAP_RE21_B__W 11 +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE22_B__B 0 +#define IQM_CF_TAP_RE22_B__M 0x7FF +#define IQM_CF_TAP_RE22_B__PRE 0x2 +#define IQM_CF_TAP_RE22_B__W 11 +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE23_B__B 0 +#define IQM_CF_TAP_RE23_B__M 0x7FF +#define IQM_CF_TAP_RE23_B__PRE 0x2 +#define IQM_CF_TAP_RE23_B__W 11 +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE24_B__B 0 +#define IQM_CF_TAP_RE24_B__M 0x7FF +#define IQM_CF_TAP_RE24_B__PRE 0x2 +#define IQM_CF_TAP_RE24_B__W 11 +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE25_B__B 0 +#define IQM_CF_TAP_RE25_B__M 0x7FF +#define IQM_CF_TAP_RE25_B__PRE 0x2 +#define IQM_CF_TAP_RE25_B__W 11 +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE26_B__B 0 +#define IQM_CF_TAP_RE26_B__M 0x7FF +#define IQM_CF_TAP_RE26_B__PRE 0x2 +#define IQM_CF_TAP_RE26_B__W 11 +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE27_B__B 0 +#define IQM_CF_TAP_RE27_B__M 0x7FF +#define IQM_CF_TAP_RE27_B__PRE 0x2 +#define IQM_CF_TAP_RE27_B__W 11 +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE2_B__B 0 +#define IQM_CF_TAP_RE2_B__M 0x7F +#define IQM_CF_TAP_RE2_B__PRE 0x2 +#define IQM_CF_TAP_RE2_B__W 7 +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE3_B__B 0 +#define IQM_CF_TAP_RE3_B__M 0x7F +#define IQM_CF_TAP_RE3_B__PRE 0x2 +#define IQM_CF_TAP_RE3_B__W 7 +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE4_B__B 0 +#define IQM_CF_TAP_RE4_B__M 0x7F +#define IQM_CF_TAP_RE4_B__PRE 0x2 +#define IQM_CF_TAP_RE4_B__W 7 +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE5_B__B 0 +#define IQM_CF_TAP_RE5_B__M 0x7F +#define IQM_CF_TAP_RE5_B__PRE 0x2 +#define IQM_CF_TAP_RE5_B__W 7 +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE6_B__B 0 +#define IQM_CF_TAP_RE6_B__M 0x7F +#define IQM_CF_TAP_RE6_B__PRE 0x2 +#define IQM_CF_TAP_RE6_B__W 7 +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE7_B__B 0 +#define IQM_CF_TAP_RE7_B__M 0x1FF +#define IQM_CF_TAP_RE7_B__PRE 0x2 +#define IQM_CF_TAP_RE7_B__W 9 +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE8_B__B 0 +#define IQM_CF_TAP_RE8_B__M 0x1FF +#define IQM_CF_TAP_RE8_B__PRE 0x2 +#define IQM_CF_TAP_RE8_B__W 9 +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE9_B__B 0 +#define IQM_CF_TAP_RE9_B__M 0x1FF +#define IQM_CF_TAP_RE9_B__PRE 0x2 +#define IQM_CF_TAP_RE9_B__W 9 +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_WND_LEN__A 0x1860063 +#define IQM_CF_WND_LEN__A 0x1860063 +#define IQM_COMM_EXEC_B_ACTIVE 0x1 +#define IQM_COMM_EXEC_B_ACTIVE 0x1 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_FD_RATESEL__A 0x1830010 +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__A 0x1840016 +#define OFDM_CP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_COMM_EXEC__A 0x2800000 +#define OFDM_EC_SB_PRIOR_HI 0x0 +#define OFDM_EC_SB_PRIOR__A 0x3410013 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 +#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 +#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 +#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_STATE__A 0x3C00001 +#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 +#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define OFDM_SC_RA_RAM_CMD_NULL 0x0 +#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 +#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 +#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 +#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 +#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C +#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 +#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D +#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C +#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 +#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 +#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 +#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 +#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM0__W 16 +#define OFDM_SC_RA_RAM_PARAM0__W 16 +#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM1__W 16 +#define OFDM_SC_RA_RAM_PARAM1__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__PRE 0x4 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__PRE 0x4 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__PRE 0x4 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__PRE 0x4 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__PRE 0x6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__PRE 0x6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x0 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0xA +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0xC +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0xF +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x10 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x14 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x19 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x2 +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x3 +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x4 +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x5 +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x6 +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x8 +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x9 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 +#define QAM_SY_SP_INV__A 0x1470017 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__PRE 0x3A98 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_C 0x2 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_HOLD 0x2 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E +#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 +#define SCU_RAM_AGC_CONFIG__A 0x831F24 +#define SCU_RAM_AGC_CONFIG__A 0x831F24 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A +#define SCU_RAM_AGC_KI_MAX__A 0x831F2C +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 +#define SCU_RAM_AGC_KI_MIN__A 0x831F2B +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED__A 0x831F26 +#define SCU_RAM_AGC_KI_RED__A 0x831F26 +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI__A 0x831F25 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 +#define SCU_RAM_AGC_RF_MAX__A 0x831F1B +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 +#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SIO_BL_CHAIN_ADDR__A 0x480018 +#define SIO_BL_CHAIN_LEN__A 0x480019 +#define SIO_BL_COMM_EXEC_ACTIVE 0x1 +#define SIO_BL_COMM_EXEC__A 0x480000 +#define SIO_BL_ENABLE_ON 0x1 +#define SIO_BL_ENABLE_ON 0x1 +#define SIO_BL_ENABLE__A 0x480012 +#define SIO_BL_ENABLE__A 0x480012 +#define SIO_BL_MODE_CHAIN 0x1 +#define SIO_BL_MODE_DIRECT 0x0 +#define SIO_BL_MODE__A 0x480011 +#define SIO_BL_MODE__A 0x480011 +#define SIO_BL_SRC_ADDR__A 0x480016 +#define SIO_BL_SRC_LEN__A 0x480017 +#define SIO_BL_STATUS__A 0x480010 +#define SIO_BL_STATUS__A 0x480010 +#define SIO_BL_TGT_ADDR__A 0x480015 +#define SIO_BL_TGT_HDR__A 0x480014 +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_SOFT_RST_OFDM__M 0x1 +#define SIO_CC_SOFT_RST_OSC__M 0x4 +#define SIO_CC_SOFT_RST_SYS__M 0x2 +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE_KEY 0xFABA +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_TOP_COMM_KEY_KEY 0xFABA +#define SIO_TOP_COMM_KEY_KEY 0xFABA +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__A 0x410012 diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbh24.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbh24.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbh24.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbh24.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,55 @@ +/* + * lnbh24.h - driver for lnb supply and control ic lnbh24 + * + * Copyright (C) 2009 NetUP Inc. + * Copyright (C) 2009 Igor M. Liplianin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _LNBH24_H +#define _LNBH24_H + +/* system register bits */ +#define LNBH24_OLF 0x01 +#define LNBH24_OTF 0x02 +#define LNBH24_EN 0x04 +#define LNBH24_VSEL 0x08 +#define LNBH24_LLC 0x10 +#define LNBH24_TEN 0x20 +#define LNBH24_TTX 0x40 +#define LNBH24_PCL 0x80 + +#include + +#if defined(CONFIG_DVB_LNBP21) || (defined(CONFIG_DVB_LNBP21_MODULE) \ + && defined(MODULE)) +/* override_set and override_clear control which + system register bits (above) to always set & clear */ +extern struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 override_set, + u8 override_clear, u8 i2c_addr); +#else +static inline struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 override_set, + u8 override_clear, u8 i2c_addr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,188 @@ +/* + * lnbp21.c - driver for lnb supply and control ic lnbp21 + * + * Copyright (C) 2006, 2009 Oliver Endriss + * Copyright (C) 2009 Igor M. Liplianin + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + * + * + * the project's page is at http://www.linuxtv.org + */ +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "lnbp21.h" +#include "lnbh24.h" + +struct lnbp21 { + u8 config; + u8 override_or; + u8 override_and; + struct i2c_adapter *i2c; + u8 i2c_addr; +}; + +static int lnbp21_set_voltage(struct dvb_frontend *fe, + fe_sec_voltage_t voltage) +{ + struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv; + struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0, + .buf = &lnbp21->config, + .len = sizeof(lnbp21->config) }; + + lnbp21->config &= ~(LNBP21_VSEL | LNBP21_EN); + + switch(voltage) { + case SEC_VOLTAGE_OFF: + break; + case SEC_VOLTAGE_13: + lnbp21->config |= LNBP21_EN; + break; + case SEC_VOLTAGE_18: + lnbp21->config |= (LNBP21_EN | LNBP21_VSEL); + break; + default: + return -EINVAL; + }; + + lnbp21->config |= lnbp21->override_or; + lnbp21->config &= lnbp21->override_and; + + return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO; +} + +static int lnbp21_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg) +{ + struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv; + struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0, + .buf = &lnbp21->config, + .len = sizeof(lnbp21->config) }; + + if (arg) + lnbp21->config |= LNBP21_LLC; + else + lnbp21->config &= ~LNBP21_LLC; + + lnbp21->config |= lnbp21->override_or; + lnbp21->config &= lnbp21->override_and; + + return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO; +} + +static int lnbp21_set_tone(struct dvb_frontend *fe, + fe_sec_tone_mode_t tone) +{ + struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv; + struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0, + .buf = &lnbp21->config, + .len = sizeof(lnbp21->config) }; + + switch (tone) { + case SEC_TONE_OFF: + lnbp21->config &= ~LNBP21_TEN; + break; + case SEC_TONE_ON: + lnbp21->config |= LNBP21_TEN; + break; + default: + return -EINVAL; + }; + + lnbp21->config |= lnbp21->override_or; + lnbp21->config &= lnbp21->override_and; + + return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO; +} + +static void lnbp21_release(struct dvb_frontend *fe) +{ + /* LNBP power off */ + lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF); + + /* free data */ + kfree(fe->sec_priv); + fe->sec_priv = NULL; +} + +static struct dvb_frontend *lnbx2x_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 override_set, + u8 override_clear, u8 i2c_addr, u8 config) +{ + struct lnbp21 *lnbp21 = kmalloc(sizeof(struct lnbp21), GFP_KERNEL); + if (!lnbp21) + return NULL; + + /* default configuration */ + lnbp21->config = config; + lnbp21->i2c = i2c; + lnbp21->i2c_addr = i2c_addr; + fe->sec_priv = lnbp21; + + /* bits which should be forced to '1' */ + lnbp21->override_or = override_set; + + /* bits which should be forced to '0' */ + lnbp21->override_and = ~override_clear; + + /* detect if it is present or not */ + if (lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF)) { + kfree(lnbp21); + return NULL; + } + + /* install release callback */ + fe->ops.release_sec = lnbp21_release; + + /* override frontend ops */ + fe->ops.set_voltage = lnbp21_set_voltage; + fe->ops.enable_high_lnb_voltage = lnbp21_enable_high_lnb_voltage; + if (!(override_clear & LNBH24_TEN)) /*22kHz logic controlled by demod*/ + fe->ops.set_tone = lnbp21_set_tone; + printk(KERN_INFO "LNBx2x attached on addr=%x\n", lnbp21->i2c_addr); + + return fe; +} + +struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 override_set, + u8 override_clear, u8 i2c_addr) +{ + return lnbx2x_attach(fe, i2c, override_set, override_clear, + i2c_addr, LNBH24_TTX); +} +EXPORT_SYMBOL(lnbh24_attach); + +struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 override_set, + u8 override_clear) +{ + return lnbx2x_attach(fe, i2c, override_set, override_clear, + 0x08, LNBP21_ISEL); +} +EXPORT_SYMBOL(lnbp21_attach); + +MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp21, lnbh24"); +MODULE_AUTHOR("Oliver Endriss, Igor M. Liplianin"); +MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/lnbp21.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,75 @@ +/* + * lnbp21.h - driver for lnb supply and control ic lnbp21 + * + * Copyright (C) 2006 Oliver Endriss + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + * + * + * the project's page is at http://www.linuxtv.org + */ + +#ifndef _LNBP21_H +#define _LNBP21_H + +/* system register bits */ +/* [RO] 0=OK; 1=over current limit flag */ +#define LNBP21_OLF 0x01 +/* [RO] 0=OK; 1=over temperature flag (150 C) */ +#define LNBP21_OTF 0x02 +/* [RW] 0=disable LNB power, enable loopthrough + 1=enable LNB power, disable loopthrough */ +#define LNBP21_EN 0x04 +/* [RW] 0=low voltage (13/14V, vert pol) + 1=high voltage (18/19V,horiz pol) */ +#define LNBP21_VSEL 0x08 +/* [RW] increase LNB voltage by 1V: + 0=13/18V; 1=14/19V */ +#define LNBP21_LLC 0x10 +/* [RW] 0=tone controlled by DSQIN pin + 1=tone enable, disable DSQIN */ +#define LNBP21_TEN 0x20 +/* [RW] current limit select: + 0:Iout=500-650mA Isc=300mA + 1:Iout=400-550mA Isc=200mA */ +#define LNBP21_ISEL 0x40 +/* [RW] short-circuit protect: + 0=pulsed (dynamic) curr limiting + 1=static curr limiting */ +#define LNBP21_PCL 0x80 + +#include + +#if defined(CONFIG_DVB_LNBP21) || (defined(CONFIG_DVB_LNBP21_MODULE) \ + && defined(MODULE)) +/* override_set and override_clear control which + system register bits (above) to always set & clear */ +extern struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 override_set, + u8 override_clear); +#else +static inline struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 override_set, + u8 override_clear) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,3472 @@ +/* + * stv0367.c + * + * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. + * + * Copyright (C) ST Microelectronics. + * Copyright (C) 2010,2011 NetUP Inc. + * Copyright (C) 2010,2011 Igor M. Liplianin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include "stv0367.h" +#include "stv0367_regs.h" +#include "stv0367_priv.h" + +static int stvdebug; +module_param_named(debug, stvdebug, int, 0644); + +static int i2cdebug; +module_param_named(i2c_debug, i2cdebug, int, 0644); + +#define dprintk(args...) \ + do { \ + if (stvdebug) \ + printk(KERN_DEBUG args); \ + } while (0) + /* DVB-C */ + +struct stv0367cab_state { + enum stv0367_cab_signal_type state; + u32 mclk; + u32 adc_clk; + s32 search_range; + s32 derot_offset; + /* results */ + int locked; /* channel found */ + u32 freq_khz; /* found frequency (in kHz) */ + u32 symbol_rate; /* found symbol rate (in Bds) */ + enum stv0367cab_mod modulation; /* modulation */ + fe_spectral_inversion_t spect_inv; /* Spectrum Inversion */ +}; + +struct stv0367ter_state { + /* DVB-T */ + enum stv0367_ter_signal_type state; + enum stv0367_ter_if_iq_mode if_iq_mode; + enum stv0367_ter_mode mode;/* mode 2K or 8K */ + fe_guard_interval_t guard; + enum stv0367_ter_hierarchy hierarchy; + u32 frequency; + fe_spectral_inversion_t sense; /* current search spectrum */ + u8 force; /* force mode/guard */ + u8 bw; /* channel width 6, 7 or 8 in MHz */ + u8 pBW; /* channel width used during previous lock */ + u32 pBER; + u32 pPER; + u32 ucblocks; + s8 echo_pos; /* echo position */ + u8 first_lock; + u8 unlock_counter; + u32 agc_val; +}; + +struct stv0367_state { + struct dvb_frontend fe; + struct i2c_adapter *i2c; + /* config settings */ + const struct stv0367_config *config; + u8 chip_id; + /* DVB-C */ + struct stv0367cab_state *cab_state; + /* DVB-T */ + struct stv0367ter_state *ter_state; + s32 IF; +}; + +struct st_register { + u16 addr; + u8 value; +}; + +/* values for STV4100 XTAL=30M int clk=53.125M*/ +static struct st_register def0367ter[STV0367TER_NBREGS] = { + {R367TER_ID, 0x60}, + {R367TER_I2CRPT, 0x38}, + /* {R367TER_I2CRPT, 0x22},*/ + {R367TER_TOPCTRL, 0x00},/* for xc5000; was 0x02 */ + {R367TER_IOCFG0, 0x40}, + {R367TER_DAC0R, 0x00}, + {R367TER_IOCFG1, 0x00}, + {R367TER_DAC1R, 0x00}, + {R367TER_IOCFG2, 0x62}, + {R367TER_SDFR, 0x00}, + {R367TER_STATUS, 0xf8}, + {R367TER_AUX_CLK, 0x0a}, + {R367TER_FREESYS1, 0x00}, + {R367TER_FREESYS2, 0x00}, + {R367TER_FREESYS3, 0x00}, + {R367TER_GPIO_CFG, 0x55}, + {R367TER_GPIO_CMD, 0x00}, + {R367TER_AGC2MAX, 0xff}, + {R367TER_AGC2MIN, 0x00}, + {R367TER_AGC1MAX, 0xff}, + {R367TER_AGC1MIN, 0x00}, + {R367TER_AGCR, 0xbc}, + {R367TER_AGC2TH, 0x00}, + {R367TER_AGC12C, 0x00}, + {R367TER_AGCCTRL1, 0x85}, + {R367TER_AGCCTRL2, 0x1f}, + {R367TER_AGC1VAL1, 0x00}, + {R367TER_AGC1VAL2, 0x00}, + {R367TER_AGC2VAL1, 0x6f}, + {R367TER_AGC2VAL2, 0x05}, + {R367TER_AGC2PGA, 0x00}, + {R367TER_OVF_RATE1, 0x00}, + {R367TER_OVF_RATE2, 0x00}, + {R367TER_GAIN_SRC1, 0xaa},/* for xc5000; was 0x2b */ + {R367TER_GAIN_SRC2, 0xd6},/* for xc5000; was 0x04 */ + {R367TER_INC_DEROT1, 0x55}, + {R367TER_INC_DEROT2, 0x55}, + {R367TER_PPM_CPAMP_DIR, 0x2c}, + {R367TER_PPM_CPAMP_INV, 0x00}, + {R367TER_FREESTFE_1, 0x00}, + {R367TER_FREESTFE_2, 0x1c}, + {R367TER_DCOFFSET, 0x00}, + {R367TER_EN_PROCESS, 0x05}, + {R367TER_SDI_SMOOTHER, 0x80}, + {R367TER_FE_LOOP_OPEN, 0x1c}, + {R367TER_FREQOFF1, 0x00}, + {R367TER_FREQOFF2, 0x00}, + {R367TER_FREQOFF3, 0x00}, + {R367TER_TIMOFF1, 0x00}, + {R367TER_TIMOFF2, 0x00}, + {R367TER_EPQ, 0x02}, + {R367TER_EPQAUTO, 0x01}, + {R367TER_SYR_UPDATE, 0xf5}, + {R367TER_CHPFREE, 0x00}, + {R367TER_PPM_STATE_MAC, 0x23}, + {R367TER_INR_THRESHOLD, 0xff}, + {R367TER_EPQ_TPS_ID_CELL, 0xf9}, + {R367TER_EPQ_CFG, 0x00}, + {R367TER_EPQ_STATUS, 0x01}, + {R367TER_AUTORELOCK, 0x81}, + {R367TER_BER_THR_VMSB, 0x00}, + {R367TER_BER_THR_MSB, 0x00}, + {R367TER_BER_THR_LSB, 0x00}, + {R367TER_CCD, 0x83}, + {R367TER_SPECTR_CFG, 0x00}, + {R367TER_CHC_DUMMY, 0x18}, + {R367TER_INC_CTL, 0x88}, + {R367TER_INCTHRES_COR1, 0xb4}, + {R367TER_INCTHRES_COR2, 0x96}, + {R367TER_INCTHRES_DET1, 0x0e}, + {R367TER_INCTHRES_DET2, 0x11}, + {R367TER_IIR_CELLNB, 0x8d}, + {R367TER_IIRCX_COEFF1_MSB, 0x00}, + {R367TER_IIRCX_COEFF1_LSB, 0x00}, + {R367TER_IIRCX_COEFF2_MSB, 0x09}, + {R367TER_IIRCX_COEFF2_LSB, 0x18}, + {R367TER_IIRCX_COEFF3_MSB, 0x14}, + {R367TER_IIRCX_COEFF3_LSB, 0x9c}, + {R367TER_IIRCX_COEFF4_MSB, 0x00}, + {R367TER_IIRCX_COEFF4_LSB, 0x00}, + {R367TER_IIRCX_COEFF5_MSB, 0x36}, + {R367TER_IIRCX_COEFF5_LSB, 0x42}, + {R367TER_FEPATH_CFG, 0x00}, + {R367TER_PMC1_FUNC, 0x65}, + {R367TER_PMC1_FOR, 0x00}, + {R367TER_PMC2_FUNC, 0x00}, + {R367TER_STATUS_ERR_DA, 0xe0}, + {R367TER_DIG_AGC_R, 0xfe}, + {R367TER_COMAGC_TARMSB, 0x0b}, + {R367TER_COM_AGC_TAR_ENMODE, 0x41}, + {R367TER_COM_AGC_CFG, 0x3e}, + {R367TER_COM_AGC_GAIN1, 0x39}, + {R367TER_AUT_AGC_TARGETMSB, 0x0b}, + {R367TER_LOCK_DET_MSB, 0x01}, + {R367TER_AGCTAR_LOCK_LSBS, 0x40}, + {R367TER_AUT_GAIN_EN, 0xf4}, + {R367TER_AUT_CFG, 0xf0}, + {R367TER_LOCKN, 0x23}, + {R367TER_INT_X_3, 0x00}, + {R367TER_INT_X_2, 0x03}, + {R367TER_INT_X_1, 0x8d}, + {R367TER_INT_X_0, 0xa0}, + {R367TER_MIN_ERRX_MSB, 0x00}, + {R367TER_COR_CTL, 0x23}, + {R367TER_COR_STAT, 0xf6}, + {R367TER_COR_INTEN, 0x00}, + {R367TER_COR_INTSTAT, 0x3f}, + {R367TER_COR_MODEGUARD, 0x03}, + {R367TER_AGC_CTL, 0x08}, + {R367TER_AGC_MANUAL1, 0x00}, + {R367TER_AGC_MANUAL2, 0x00}, + {R367TER_AGC_TARG, 0x16}, + {R367TER_AGC_GAIN1, 0x53}, + {R367TER_AGC_GAIN2, 0x1d}, + {R367TER_RESERVED_1, 0x00}, + {R367TER_RESERVED_2, 0x00}, + {R367TER_RESERVED_3, 0x00}, + {R367TER_CAS_CTL, 0x44}, + {R367TER_CAS_FREQ, 0xb3}, + {R367TER_CAS_DAGCGAIN, 0x12}, + {R367TER_SYR_CTL, 0x04}, + {R367TER_SYR_STAT, 0x10}, + {R367TER_SYR_NCO1, 0x00}, + {R367TER_SYR_NCO2, 0x00}, + {R367TER_SYR_OFFSET1, 0x00}, + {R367TER_SYR_OFFSET2, 0x00}, + {R367TER_FFT_CTL, 0x00}, + {R367TER_SCR_CTL, 0x70}, + {R367TER_PPM_CTL1, 0xf8}, + {R367TER_TRL_CTL, 0x14},/* for xc5000; was 0xac */ + {R367TER_TRL_NOMRATE1, 0xae},/* for xc5000; was 0x1e */ + {R367TER_TRL_NOMRATE2, 0x56},/* for xc5000; was 0x58 */ + {R367TER_TRL_TIME1, 0x1d}, + {R367TER_TRL_TIME2, 0xfc}, + {R367TER_CRL_CTL, 0x24}, + {R367TER_CRL_FREQ1, 0xad}, + {R367TER_CRL_FREQ2, 0x9d}, + {R367TER_CRL_FREQ3, 0xff}, + {R367TER_CHC_CTL, 0x01}, + {R367TER_CHC_SNR, 0xf0}, + {R367TER_BDI_CTL, 0x00}, + {R367TER_DMP_CTL, 0x00}, + {R367TER_TPS_RCVD1, 0x30}, + {R367TER_TPS_RCVD2, 0x02}, + {R367TER_TPS_RCVD3, 0x01}, + {R367TER_TPS_RCVD4, 0x00}, + {R367TER_TPS_ID_CELL1, 0x00}, + {R367TER_TPS_ID_CELL2, 0x00}, + {R367TER_TPS_RCVD5_SET1, 0x02}, + {R367TER_TPS_SET2, 0x02}, + {R367TER_TPS_SET3, 0x01}, + {R367TER_TPS_CTL, 0x00}, + {R367TER_CTL_FFTOSNUM, 0x34}, + {R367TER_TESTSELECT, 0x09}, + {R367TER_MSC_REV, 0x0a}, + {R367TER_PIR_CTL, 0x00}, + {R367TER_SNR_CARRIER1, 0xa1}, + {R367TER_SNR_CARRIER2, 0x9a}, + {R367TER_PPM_CPAMP, 0x2c}, + {R367TER_TSM_AP0, 0x00}, + {R367TER_TSM_AP1, 0x00}, + {R367TER_TSM_AP2 , 0x00}, + {R367TER_TSM_AP3, 0x00}, + {R367TER_TSM_AP4, 0x00}, + {R367TER_TSM_AP5, 0x00}, + {R367TER_TSM_AP6, 0x00}, + {R367TER_TSM_AP7, 0x00}, + {R367TER_TSTRES, 0x00}, + {R367TER_ANACTRL, 0x0D},/* PLL stoped, restart at init!!! */ + {R367TER_TSTBUS, 0x00}, + {R367TER_TSTRATE, 0x00}, + {R367TER_CONSTMODE, 0x01}, + {R367TER_CONSTCARR1, 0x00}, + {R367TER_CONSTCARR2, 0x00}, + {R367TER_ICONSTEL, 0x0a}, + {R367TER_QCONSTEL, 0x15}, + {R367TER_TSTBISTRES0, 0x00}, + {R367TER_TSTBISTRES1, 0x00}, + {R367TER_TSTBISTRES2, 0x28}, + {R367TER_TSTBISTRES3, 0x00}, + {R367TER_RF_AGC1, 0xff}, + {R367TER_RF_AGC2, 0x83}, + {R367TER_ANADIGCTRL, 0x19}, + {R367TER_PLLMDIV, 0x01},/* for xc5000; was 0x0c */ + {R367TER_PLLNDIV, 0x06},/* for xc5000; was 0x55 */ + {R367TER_PLLSETUP, 0x18}, + {R367TER_DUAL_AD12, 0x0C},/* for xc5000 AGC voltage 1.6V */ + {R367TER_TSTBIST, 0x00}, + {R367TER_PAD_COMP_CTRL, 0x00}, + {R367TER_PAD_COMP_WR, 0x00}, + {R367TER_PAD_COMP_RD, 0xe0}, + {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00}, + {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00}, + {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00}, + {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00}, + {R367TER_SYR_FLAG, 0x00}, + {R367TER_CRL_TARGET1, 0x00}, + {R367TER_CRL_TARGET2, 0x00}, + {R367TER_CRL_TARGET3, 0x00}, + {R367TER_CRL_TARGET4, 0x00}, + {R367TER_CRL_FLAG, 0x00}, + {R367TER_TRL_TARGET1, 0x00}, + {R367TER_TRL_TARGET2, 0x00}, + {R367TER_TRL_CHC, 0x00}, + {R367TER_CHC_SNR_TARG, 0x00}, + {R367TER_TOP_TRACK, 0x00}, + {R367TER_TRACKER_FREE1, 0x00}, + {R367TER_ERROR_CRL1, 0x00}, + {R367TER_ERROR_CRL2, 0x00}, + {R367TER_ERROR_CRL3, 0x00}, + {R367TER_ERROR_CRL4, 0x00}, + {R367TER_DEC_NCO1, 0x2c}, + {R367TER_DEC_NCO2, 0x0f}, + {R367TER_DEC_NCO3, 0x20}, + {R367TER_SNR, 0xf1}, + {R367TER_SYR_FFTADJ1, 0x00}, + {R367TER_SYR_FFTADJ2, 0x00}, + {R367TER_SYR_CHCADJ1, 0x00}, + {R367TER_SYR_CHCADJ2, 0x00}, + {R367TER_SYR_OFF, 0x00}, + {R367TER_PPM_OFFSET1, 0x00}, + {R367TER_PPM_OFFSET2, 0x03}, + {R367TER_TRACKER_FREE2, 0x00}, + {R367TER_DEBG_LT10, 0x00}, + {R367TER_DEBG_LT11, 0x00}, + {R367TER_DEBG_LT12, 0x00}, + {R367TER_DEBG_LT13, 0x00}, + {R367TER_DEBG_LT14, 0x00}, + {R367TER_DEBG_LT15, 0x00}, + {R367TER_DEBG_LT16, 0x00}, + {R367TER_DEBG_LT17, 0x00}, + {R367TER_DEBG_LT18, 0x00}, + {R367TER_DEBG_LT19, 0x00}, + {R367TER_DEBG_LT1A, 0x00}, + {R367TER_DEBG_LT1B, 0x00}, + {R367TER_DEBG_LT1C, 0x00}, + {R367TER_DEBG_LT1D, 0x00}, + {R367TER_DEBG_LT1E, 0x00}, + {R367TER_DEBG_LT1F, 0x00}, + {R367TER_RCCFGH, 0x00}, + {R367TER_RCCFGM, 0x00}, + {R367TER_RCCFGL, 0x00}, + {R367TER_RCINSDELH, 0x00}, + {R367TER_RCINSDELM, 0x00}, + {R367TER_RCINSDELL, 0x00}, + {R367TER_RCSTATUS, 0x00}, + {R367TER_RCSPEED, 0x6f}, + {R367TER_RCDEBUGM, 0xe7}, + {R367TER_RCDEBUGL, 0x9b}, + {R367TER_RCOBSCFG, 0x00}, + {R367TER_RCOBSM, 0x00}, + {R367TER_RCOBSL, 0x00}, + {R367TER_RCFECSPY, 0x00}, + {R367TER_RCFSPYCFG, 0x00}, + {R367TER_RCFSPYDATA, 0x00}, + {R367TER_RCFSPYOUT, 0x00}, + {R367TER_RCFSTATUS, 0x00}, + {R367TER_RCFGOODPACK, 0x00}, + {R367TER_RCFPACKCNT, 0x00}, + {R367TER_RCFSPYMISC, 0x00}, + {R367TER_RCFBERCPT4, 0x00}, + {R367TER_RCFBERCPT3, 0x00}, + {R367TER_RCFBERCPT2, 0x00}, + {R367TER_RCFBERCPT1, 0x00}, + {R367TER_RCFBERCPT0, 0x00}, + {R367TER_RCFBERERR2, 0x00}, + {R367TER_RCFBERERR1, 0x00}, + {R367TER_RCFBERERR0, 0x00}, + {R367TER_RCFSTATESM, 0x00}, + {R367TER_RCFSTATESL, 0x00}, + {R367TER_RCFSPYBER, 0x00}, + {R367TER_RCFSPYDISTM, 0x00}, + {R367TER_RCFSPYDISTL, 0x00}, + {R367TER_RCFSPYOBS7, 0x00}, + {R367TER_RCFSPYOBS6, 0x00}, + {R367TER_RCFSPYOBS5, 0x00}, + {R367TER_RCFSPYOBS4, 0x00}, + {R367TER_RCFSPYOBS3, 0x00}, + {R367TER_RCFSPYOBS2, 0x00}, + {R367TER_RCFSPYOBS1, 0x00}, + {R367TER_RCFSPYOBS0, 0x00}, + {R367TER_TSGENERAL, 0x00}, + {R367TER_RC1SPEED, 0x6f}, + {R367TER_TSGSTATUS, 0x18}, + {R367TER_FECM, 0x01}, + {R367TER_VTH12, 0xff}, + {R367TER_VTH23, 0xa1}, + {R367TER_VTH34, 0x64}, + {R367TER_VTH56, 0x40}, + {R367TER_VTH67, 0x00}, + {R367TER_VTH78, 0x2c}, + {R367TER_VITCURPUN, 0x12}, + {R367TER_VERROR, 0x01}, + {R367TER_PRVIT, 0x3f}, + {R367TER_VAVSRVIT, 0x00}, + {R367TER_VSTATUSVIT, 0xbd}, + {R367TER_VTHINUSE, 0xa1}, + {R367TER_KDIV12, 0x20}, + {R367TER_KDIV23, 0x40}, + {R367TER_KDIV34, 0x20}, + {R367TER_KDIV56, 0x30}, + {R367TER_KDIV67, 0x00}, + {R367TER_KDIV78, 0x30}, + {R367TER_SIGPOWER, 0x54}, + {R367TER_DEMAPVIT, 0x40}, + {R367TER_VITSCALE, 0x00}, + {R367TER_FFEC1PRG, 0x00}, + {R367TER_FVITCURPUN, 0x12}, + {R367TER_FVERROR, 0x01}, + {R367TER_FVSTATUSVIT, 0xbd}, + {R367TER_DEBUG_LT1, 0x00}, + {R367TER_DEBUG_LT2, 0x00}, + {R367TER_DEBUG_LT3, 0x00}, + {R367TER_TSTSFMET, 0x00}, + {R367TER_SELOUT, 0x00}, + {R367TER_TSYNC, 0x00}, + {R367TER_TSTERR, 0x00}, + {R367TER_TSFSYNC, 0x00}, + {R367TER_TSTSFERR, 0x00}, + {R367TER_TSTTSSF1, 0x01}, + {R367TER_TSTTSSF2, 0x1f}, + {R367TER_TSTTSSF3, 0x00}, + {R367TER_TSTTS1, 0x00}, + {R367TER_TSTTS2, 0x1f}, + {R367TER_TSTTS3, 0x01}, + {R367TER_TSTTS4, 0x00}, + {R367TER_TSTTSRC, 0x00}, + {R367TER_TSTTSRS, 0x00}, + {R367TER_TSSTATEM, 0xb0}, {R367TER_TSSTATEL, 0x40}, + {R367TER_TSCFGH, 0x70}, + {R367TER_TSCFGM, 0xc0},/* for xc5000; was 0x00 */ + {R367TER_TSCFGL, 0x20}, + {R367TER_TSSYNC, 0x00}, + {R367TER_TSINSDELH, 0x00}, + {R367TER_TSINSDELM, 0x00}, + {R367TER_TSINSDELL, 0x00}, + {R367TER_TSDIVN, 0x03}, + {R367TER_TSDIVPM, 0x00}, + {R367TER_TSDIVPL, 0x00}, + {R367TER_TSDIVQM, 0x00}, + {R367TER_TSDIVQL, 0x00}, + {R367TER_TSDILSTKM, 0x00}, + {R367TER_TSDILSTKL, 0x00}, + {R367TER_TSSPEED, 0x40},/* for xc5000; was 0x6f */ + {R367TER_TSSTATUS, 0x81}, + {R367TER_TSSTATUS2, 0x6a}, + {R367TER_TSBITRATEM, 0x0f}, + {R367TER_TSBITRATEL, 0xc6}, + {R367TER_TSPACKLENM, 0x00}, + {R367TER_TSPACKLENL, 0xfc}, + {R367TER_TSBLOCLENM, 0x0a}, + {R367TER_TSBLOCLENL, 0x80}, + {R367TER_TSDLYH, 0x90}, + {R367TER_TSDLYM, 0x68}, + {R367TER_TSDLYL, 0x01}, + {R367TER_TSNPDAV, 0x00}, + {R367TER_TSBUFSTATH, 0x00}, + {R367TER_TSBUFSTATM, 0x00}, + {R367TER_TSBUFSTATL, 0x00}, + {R367TER_TSDEBUGM, 0xcf}, + {R367TER_TSDEBUGL, 0x1e}, + {R367TER_TSDLYSETH, 0x00}, + {R367TER_TSDLYSETM, 0x68}, + {R367TER_TSDLYSETL, 0x00}, + {R367TER_TSOBSCFG, 0x00}, + {R367TER_TSOBSM, 0x47}, + {R367TER_TSOBSL, 0x1f}, + {R367TER_ERRCTRL1, 0x95}, + {R367TER_ERRCNT1H, 0x80}, + {R367TER_ERRCNT1M, 0x00}, + {R367TER_ERRCNT1L, 0x00}, + {R367TER_ERRCTRL2, 0x95}, + {R367TER_ERRCNT2H, 0x00}, + {R367TER_ERRCNT2M, 0x00}, + {R367TER_ERRCNT2L, 0x00}, + {R367TER_FECSPY, 0x88}, + {R367TER_FSPYCFG, 0x2c}, + {R367TER_FSPYDATA, 0x3a}, + {R367TER_FSPYOUT, 0x06}, + {R367TER_FSTATUS, 0x61}, + {R367TER_FGOODPACK, 0xff}, + {R367TER_FPACKCNT, 0xff}, + {R367TER_FSPYMISC, 0x66}, + {R367TER_FBERCPT4, 0x00}, + {R367TER_FBERCPT3, 0x00}, + {R367TER_FBERCPT2, 0x36}, + {R367TER_FBERCPT1, 0x36}, + {R367TER_FBERCPT0, 0x14}, + {R367TER_FBERERR2, 0x00}, + {R367TER_FBERERR1, 0x03}, + {R367TER_FBERERR0, 0x28}, + {R367TER_FSTATESM, 0x00}, + {R367TER_FSTATESL, 0x02}, + {R367TER_FSPYBER, 0x00}, + {R367TER_FSPYDISTM, 0x01}, + {R367TER_FSPYDISTL, 0x9f}, + {R367TER_FSPYOBS7, 0xc9}, + {R367TER_FSPYOBS6, 0x99}, + {R367TER_FSPYOBS5, 0x08}, + {R367TER_FSPYOBS4, 0xec}, + {R367TER_FSPYOBS3, 0x01}, + {R367TER_FSPYOBS2, 0x0f}, + {R367TER_FSPYOBS1, 0xf5}, + {R367TER_FSPYOBS0, 0x08}, + {R367TER_SFDEMAP, 0x40}, + {R367TER_SFERROR, 0x00}, + {R367TER_SFAVSR, 0x30}, + {R367TER_SFECSTATUS, 0xcc}, + {R367TER_SFKDIV12, 0x20}, + {R367TER_SFKDIV23, 0x40}, + {R367TER_SFKDIV34, 0x20}, + {R367TER_SFKDIV56, 0x20}, + {R367TER_SFKDIV67, 0x00}, + {R367TER_SFKDIV78, 0x20}, + {R367TER_SFDILSTKM, 0x00}, + {R367TER_SFDILSTKL, 0x00}, + {R367TER_SFSTATUS, 0xb5}, + {R367TER_SFDLYH, 0x90}, + {R367TER_SFDLYM, 0x60}, + {R367TER_SFDLYL, 0x01}, + {R367TER_SFDLYSETH, 0xc0}, + {R367TER_SFDLYSETM, 0x60}, + {R367TER_SFDLYSETL, 0x00}, + {R367TER_SFOBSCFG, 0x00}, + {R367TER_SFOBSM, 0x47}, + {R367TER_SFOBSL, 0x05}, + {R367TER_SFECINFO, 0x40}, + {R367TER_SFERRCTRL, 0x74}, + {R367TER_SFERRCNTH, 0x80}, + {R367TER_SFERRCNTM , 0x00}, + {R367TER_SFERRCNTL, 0x00}, + {R367TER_SYMBRATEM, 0x2f}, + {R367TER_SYMBRATEL, 0x50}, + {R367TER_SYMBSTATUS, 0x7f}, + {R367TER_SYMBCFG, 0x00}, + {R367TER_SYMBFIFOM, 0xf4}, + {R367TER_SYMBFIFOL, 0x0d}, + {R367TER_SYMBOFFSM, 0xf0}, + {R367TER_SYMBOFFSL, 0x2d}, + {R367TER_DEBUG_LT4, 0x00}, + {R367TER_DEBUG_LT5, 0x00}, + {R367TER_DEBUG_LT6, 0x00}, + {R367TER_DEBUG_LT7, 0x00}, + {R367TER_DEBUG_LT8, 0x00}, + {R367TER_DEBUG_LT9, 0x00}, +}; + +#define RF_LOOKUP_TABLE_SIZE 31 +#define RF_LOOKUP_TABLE2_SIZE 16 +/* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/ +s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = { + {/*AGC1*/ + 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, + 76, 77, 78, 80, 83, 85, 88, + }, {/*RF(dbm)*/ + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47, + 49, 50, 52, 53, 54, 55, 56, + } +}; +/* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/ +s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = { + {/*AGC2*/ + 28, 29, 31, 32, 34, 35, 36, 37, + 38, 39, 40, 41, 42, 43, 44, 45, + }, {/*RF(dbm)*/ + 57, 58, 59, 60, 61, 62, 63, 64, + 65, 66, 67, 68, 69, 70, 71, 72, + } +}; + +static struct st_register def0367cab[STV0367CAB_NBREGS] = { + {R367CAB_ID, 0x60}, + {R367CAB_I2CRPT, 0x38}, + /*{R367CAB_I2CRPT, 0x22},*/ + {R367CAB_TOPCTRL, 0x10}, + {R367CAB_IOCFG0, 0x80}, + {R367CAB_DAC0R, 0x00}, + {R367CAB_IOCFG1, 0x00}, + {R367CAB_DAC1R, 0x00}, + {R367CAB_IOCFG2, 0x00}, + {R367CAB_SDFR, 0x00}, + {R367CAB_AUX_CLK, 0x00}, + {R367CAB_FREESYS1, 0x00}, + {R367CAB_FREESYS2, 0x00}, + {R367CAB_FREESYS3, 0x00}, + {R367CAB_GPIO_CFG, 0x55}, + {R367CAB_GPIO_CMD, 0x01}, + {R367CAB_TSTRES, 0x00}, + {R367CAB_ANACTRL, 0x0d},/* was 0x00 need to check - I.M.L.*/ + {R367CAB_TSTBUS, 0x00}, + {R367CAB_RF_AGC1, 0xea}, + {R367CAB_RF_AGC2, 0x82}, + {R367CAB_ANADIGCTRL, 0x0b}, + {R367CAB_PLLMDIV, 0x01}, + {R367CAB_PLLNDIV, 0x08}, + {R367CAB_PLLSETUP, 0x18}, + {R367CAB_DUAL_AD12, 0x0C}, /* for xc5000 AGC voltage 1.6V */ + {R367CAB_TSTBIST, 0x00}, + {R367CAB_CTRL_1, 0x00}, + {R367CAB_CTRL_2, 0x03}, + {R367CAB_IT_STATUS1, 0x2b}, + {R367CAB_IT_STATUS2, 0x08}, + {R367CAB_IT_EN1, 0x00}, + {R367CAB_IT_EN2, 0x00}, + {R367CAB_CTRL_STATUS, 0x04}, + {R367CAB_TEST_CTL, 0x00}, + {R367CAB_AGC_CTL, 0x73}, + {R367CAB_AGC_IF_CFG, 0x50}, + {R367CAB_AGC_RF_CFG, 0x00}, + {R367CAB_AGC_PWM_CFG, 0x03}, + {R367CAB_AGC_PWR_REF_L, 0x5a}, + {R367CAB_AGC_PWR_REF_H, 0x00}, + {R367CAB_AGC_RF_TH_L, 0xff}, + {R367CAB_AGC_RF_TH_H, 0x07}, + {R367CAB_AGC_IF_LTH_L, 0x00}, + {R367CAB_AGC_IF_LTH_H, 0x08}, + {R367CAB_AGC_IF_HTH_L, 0xff}, + {R367CAB_AGC_IF_HTH_H, 0x07}, + {R367CAB_AGC_PWR_RD_L, 0xa0}, + {R367CAB_AGC_PWR_RD_M, 0xe9}, + {R367CAB_AGC_PWR_RD_H, 0x03}, + {R367CAB_AGC_PWM_IFCMD_L, 0xe4}, + {R367CAB_AGC_PWM_IFCMD_H, 0x00}, + {R367CAB_AGC_PWM_RFCMD_L, 0xff}, + {R367CAB_AGC_PWM_RFCMD_H, 0x07}, + {R367CAB_IQDEM_CFG, 0x01}, + {R367CAB_MIX_NCO_LL, 0x22}, + {R367CAB_MIX_NCO_HL, 0x96}, + {R367CAB_MIX_NCO_HH, 0x55}, + {R367CAB_SRC_NCO_LL, 0xff}, + {R367CAB_SRC_NCO_LH, 0x0c}, + {R367CAB_SRC_NCO_HL, 0xf5}, + {R367CAB_SRC_NCO_HH, 0x20}, + {R367CAB_IQDEM_GAIN_SRC_L, 0x06}, + {R367CAB_IQDEM_GAIN_SRC_H, 0x01}, + {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe}, + {R367CAB_IQDEM_DCRM_CFG_LH, 0xff}, + {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f}, + {R367CAB_IQDEM_DCRM_CFG_HH, 0x00}, + {R367CAB_IQDEM_ADJ_COEFF0, 0x34}, + {R367CAB_IQDEM_ADJ_COEFF1, 0xae}, + {R367CAB_IQDEM_ADJ_COEFF2, 0x46}, + {R367CAB_IQDEM_ADJ_COEFF3, 0x77}, + {R367CAB_IQDEM_ADJ_COEFF4, 0x96}, + {R367CAB_IQDEM_ADJ_COEFF5, 0x69}, + {R367CAB_IQDEM_ADJ_COEFF6, 0xc7}, + {R367CAB_IQDEM_ADJ_COEFF7, 0x01}, + {R367CAB_IQDEM_ADJ_EN, 0x04}, + {R367CAB_IQDEM_ADJ_AGC_REF, 0x94}, + {R367CAB_ALLPASSFILT1, 0xc9}, + {R367CAB_ALLPASSFILT2, 0x2d}, + {R367CAB_ALLPASSFILT3, 0xa3}, + {R367CAB_ALLPASSFILT4, 0xfb}, + {R367CAB_ALLPASSFILT5, 0xf6}, + {R367CAB_ALLPASSFILT6, 0x45}, + {R367CAB_ALLPASSFILT7, 0x6f}, + {R367CAB_ALLPASSFILT8, 0x7e}, + {R367CAB_ALLPASSFILT9, 0x05}, + {R367CAB_ALLPASSFILT10, 0x0a}, + {R367CAB_ALLPASSFILT11, 0x51}, + {R367CAB_TRL_AGC_CFG, 0x20}, + {R367CAB_TRL_LPF_CFG, 0x28}, + {R367CAB_TRL_LPF_ACQ_GAIN, 0x44}, + {R367CAB_TRL_LPF_TRK_GAIN, 0x22}, + {R367CAB_TRL_LPF_OUT_GAIN, 0x03}, + {R367CAB_TRL_LOCKDET_LTH, 0x04}, + {R367CAB_TRL_LOCKDET_HTH, 0x11}, + {R367CAB_TRL_LOCKDET_TRGVAL, 0x20}, + {R367CAB_IQ_QAM, 0x01}, + {R367CAB_FSM_STATE, 0xa0}, + {R367CAB_FSM_CTL, 0x08}, + {R367CAB_FSM_STS, 0x0c}, + {R367CAB_FSM_SNR0_HTH, 0x00}, + {R367CAB_FSM_SNR1_HTH, 0x00}, + {R367CAB_FSM_SNR2_HTH, 0x23},/* 0x00 */ + {R367CAB_FSM_SNR0_LTH, 0x00}, + {R367CAB_FSM_SNR1_LTH, 0x00}, + {R367CAB_FSM_EQA1_HTH, 0x00}, + {R367CAB_FSM_TEMPO, 0x32}, + {R367CAB_FSM_CONFIG, 0x03}, + {R367CAB_EQU_I_TESTTAP_L, 0x11}, + {R367CAB_EQU_I_TESTTAP_M, 0x00}, + {R367CAB_EQU_I_TESTTAP_H, 0x00}, + {R367CAB_EQU_TESTAP_CFG, 0x00}, + {R367CAB_EQU_Q_TESTTAP_L, 0xff}, + {R367CAB_EQU_Q_TESTTAP_M, 0x00}, + {R367CAB_EQU_Q_TESTTAP_H, 0x00}, + {R367CAB_EQU_TAP_CTRL, 0x00}, + {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11}, + {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05}, + {R367CAB_EQU_CTR_HIPOW_L, 0x00}, + {R367CAB_EQU_CTR_HIPOW_H, 0x00}, + {R367CAB_EQU_I_EQU_LO, 0xef}, + {R367CAB_EQU_I_EQU_HI, 0x00}, + {R367CAB_EQU_Q_EQU_LO, 0xee}, + {R367CAB_EQU_Q_EQU_HI, 0x00}, + {R367CAB_EQU_MAPPER, 0xc5}, + {R367CAB_EQU_SWEEP_RATE, 0x80}, + {R367CAB_EQU_SNR_LO, 0x64}, + {R367CAB_EQU_SNR_HI, 0x03}, + {R367CAB_EQU_GAMMA_LO, 0x00}, + {R367CAB_EQU_GAMMA_HI, 0x00}, + {R367CAB_EQU_ERR_GAIN, 0x36}, + {R367CAB_EQU_RADIUS, 0xaa}, + {R367CAB_EQU_FFE_MAINTAP, 0x00}, + {R367CAB_EQU_FFE_LEAKAGE, 0x63}, + {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf}, + {R367CAB_EQU_GAIN_WIDE, 0x88}, + {R367CAB_EQU_GAIN_NARROW, 0x41}, + {R367CAB_EQU_CTR_LPF_GAIN, 0xd1}, + {R367CAB_EQU_CRL_LPF_GAIN, 0xa7}, + {R367CAB_EQU_GLOBAL_GAIN, 0x06}, + {R367CAB_EQU_CRL_LD_SEN, 0x85}, + {R367CAB_EQU_CRL_LD_VAL, 0xe2}, + {R367CAB_EQU_CRL_TFR, 0x20}, + {R367CAB_EQU_CRL_BISTH_LO, 0x00}, + {R367CAB_EQU_CRL_BISTH_HI, 0x00}, + {R367CAB_EQU_SWEEP_RANGE_LO, 0x00}, + {R367CAB_EQU_SWEEP_RANGE_HI, 0x00}, + {R367CAB_EQU_CRL_LIMITER, 0x40}, + {R367CAB_EQU_MODULUS_MAP, 0x90}, + {R367CAB_EQU_PNT_GAIN, 0xa7}, + {R367CAB_FEC_AC_CTR_0, 0x16}, + {R367CAB_FEC_AC_CTR_1, 0x0b}, + {R367CAB_FEC_AC_CTR_2, 0x88}, + {R367CAB_FEC_AC_CTR_3, 0x02}, + {R367CAB_FEC_STATUS, 0x12}, + {R367CAB_RS_COUNTER_0, 0x7d}, + {R367CAB_RS_COUNTER_1, 0xd0}, + {R367CAB_RS_COUNTER_2, 0x19}, + {R367CAB_RS_COUNTER_3, 0x0b}, + {R367CAB_RS_COUNTER_4, 0xa3}, + {R367CAB_RS_COUNTER_5, 0x00}, + {R367CAB_BERT_0, 0x01}, + {R367CAB_BERT_1, 0x25}, + {R367CAB_BERT_2, 0x41}, + {R367CAB_BERT_3, 0x39}, + {R367CAB_OUTFORMAT_0, 0xc2}, + {R367CAB_OUTFORMAT_1, 0x22}, + {R367CAB_SMOOTHER_2, 0x28}, + {R367CAB_TSMF_CTRL_0, 0x01}, + {R367CAB_TSMF_CTRL_1, 0xc6}, + {R367CAB_TSMF_CTRL_3, 0x43}, + {R367CAB_TS_ON_ID_0, 0x00}, + {R367CAB_TS_ON_ID_1, 0x00}, + {R367CAB_TS_ON_ID_2, 0x00}, + {R367CAB_TS_ON_ID_3, 0x00}, + {R367CAB_RE_STATUS_0, 0x00}, + {R367CAB_RE_STATUS_1, 0x00}, + {R367CAB_RE_STATUS_2, 0x00}, + {R367CAB_RE_STATUS_3, 0x00}, + {R367CAB_TS_STATUS_0, 0x00}, + {R367CAB_TS_STATUS_1, 0x00}, + {R367CAB_TS_STATUS_2, 0xa0}, + {R367CAB_TS_STATUS_3, 0x00}, + {R367CAB_T_O_ID_0, 0x00}, + {R367CAB_T_O_ID_1, 0x00}, + {R367CAB_T_O_ID_2, 0x00}, + {R367CAB_T_O_ID_3, 0x00}, +}; + +static +int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len) +{ + u8 buf[len + 2]; + struct i2c_msg msg = { + .addr = state->config->demod_address, + .flags = 0, + .buf = buf, + .len = len + 2 + }; + int ret; + + buf[0] = MSB(reg); + buf[1] = LSB(reg); + memcpy(buf + 2, data, len); + + if (i2cdebug) + printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]); + + ret = i2c_transfer(state->i2c, &msg, 1); + if (ret != 1) + printk(KERN_ERR "%s: i2c write error!\n", __func__); + + return (ret != 1) ? -EREMOTEIO : 0; +} + +static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) +{ + return stv0367_writeregs(state, reg, &data, 1); +} + +static u8 stv0367_readreg(struct stv0367_state *state, u16 reg) +{ + u8 b0[] = { 0, 0 }; + u8 b1[] = { 0 }; + struct i2c_msg msg[] = { + { + .addr = state->config->demod_address, + .flags = 0, + .buf = b0, + .len = 2 + }, { + .addr = state->config->demod_address, + .flags = I2C_M_RD, + .buf = b1, + .len = 1 + } + }; + int ret; + + b0[0] = MSB(reg); + b0[1] = LSB(reg); + + ret = i2c_transfer(state->i2c, msg, 2); + if (ret != 2) + printk(KERN_ERR "%s: i2c read error\n", __func__); + + if (i2cdebug) + printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]); + + return b1[0]; +} + +static void extract_mask_pos(u32 label, u8 *mask, u8 *pos) +{ + u8 position = 0, i = 0; + + (*mask) = label & 0xff; + + while ((position == 0) && (i < 8)) { + position = ((*mask) >> i) & 0x01; + i++; + } + + (*pos) = (i - 1); +} + +static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val) +{ + u8 reg, mask, pos; + + reg = stv0367_readreg(state, (label >> 16) & 0xffff); + extract_mask_pos(label, &mask, &pos); + + val = mask & (val << pos); + + reg = (reg & (~mask)) | val; + stv0367_writereg(state, (label >> 16) & 0xffff, reg); + +} + +static void stv0367_setbits(u8 *reg, u32 label, u8 val) +{ + u8 mask, pos; + + extract_mask_pos(label, &mask, &pos); + + val = mask & (val << pos); + + (*reg) = ((*reg) & (~mask)) | val; +} + +static u8 stv0367_readbits(struct stv0367_state *state, u32 label) +{ + u8 val = 0xff; + u8 mask, pos; + + extract_mask_pos(label, &mask, &pos); + + val = stv0367_readreg(state, label >> 16); + val = (val & mask) >> pos; + + return val; +} + +u8 stv0367_getbits(u8 reg, u32 label) +{ + u8 mask, pos; + + extract_mask_pos(label, &mask, &pos); + + return (reg & mask) >> pos; +} + +static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct stv0367_state *state = fe->demodulator_priv; + u8 tmp = stv0367_readreg(state, R367TER_I2CRPT); + + dprintk("%s:\n", __func__); + printk("%s: %d %02x\n", __func__, enable, tmp); + + tmp=0x58; + if (enable) { + stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0); + stv0367_setbits(&tmp, F367TER_I2CT_ON, 1); + } else { + //stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1); + stv0367_setbits(&tmp, F367TER_I2CT_ON, 0); + } + + stv0367_writereg(state, R367TER_I2CRPT, tmp); + + printk("%s: %02x\n", __func__, tmp); + + return 0; +} + +static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe) +{ + struct dvb_frontend_ops *frontend_ops = NULL; + struct dvb_tuner_ops *tuner_ops = NULL; + u32 freq = 0; + int err = 0; + + dprintk("%s:\n", __func__); + + + if (&fe->ops) + frontend_ops = &fe->ops; + if (&frontend_ops->tuner_ops) + tuner_ops = &frontend_ops->tuner_ops; + if (tuner_ops->get_frequency) { + err = tuner_ops->get_frequency(fe, &freq); + if (err < 0) { + printk(KERN_ERR "%s: Invalid parameter\n", __func__); + return err; + } + + dprintk("%s: frequency=%d\n", __func__, freq); + + } else + return -1; + + return freq; +} + +static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = { + { + {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/ + {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */ + {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */ + {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */ + {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */ + {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */ + }, { + {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/ + {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29}, + {0x2532, 0xC000, 0x251D, 0xC391, 0x706F}, + {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F}, + {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193}, + {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */ + }, { + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + } +}; + +static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = { + { + {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/ + {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */ + {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */ + {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */ + {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */ + {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */ + }, { + {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/ + {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206}, + {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3}, + {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F}, + {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB}, + {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF} + }, { + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + } +}; + +static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = { + { + {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/ + {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */ + {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */ + {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */ + {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */ + {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */ + }, { + {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/ + {0x225E, 0xC000, 0x2256, 0xC589, 0x7489}, + {0x2293, 0xC000, 0x2295, 0xC209, 0x767E}, + {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746}, + {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799}, + {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757} + + }, { + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + } +}; + +static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz) +{ + u32 mclk_Hz = 0; /* master clock frequency (Hz) */ + u32 m, n, p; + + dprintk("%s:\n", __func__); + + if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) { + n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV); + if (n == 0) + n = n + 1; + + m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV); + if (m == 0) + m = m + 1; + + p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV); + if (p > 5) + p = 5; + + mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p)); + + dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n", + n, m, p, mclk_Hz, ExtClk_Hz); + } else + mclk_Hz = ExtClk_Hz; + + dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz); + + return mclk_Hz; +} + +static int stv0367ter_filt_coeff_init(struct stv0367_state *state, + u16 CellsCoeffs[3][6][5], u32 DemodXtal) +{ + int i, j, k, freq; + + dprintk("%s:\n", __func__); + + freq = stv0367ter_get_mclk(state, DemodXtal); + + if (freq == 53125000) + k = 1; /* equivalent to Xtal 25M on 362*/ + else if (freq == 54000000) + k = 0; /* equivalent to Xtal 27M on 362*/ + else if (freq == 52500000) + k = 2; /* equivalent to Xtal 30M on 362*/ + else + return 0; + + for (i = 1; i <= 6; i++) { + stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1); + + for (j = 1; j <= 5; j++) { + stv0367_writereg(state, + (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)), + MSB(CellsCoeffs[k][i-1][j-1])); + stv0367_writereg(state, + (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)), + LSB(CellsCoeffs[k][i-1][j-1])); + } + } + + return 1; + +} + +static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state) +{ + dprintk("%s:\n", __func__); + + stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00); + + /* Lock detect 1 */ + stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00); + stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); + stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); + + /* Lock detect 2 */ + stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01); + stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); + stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); + + /* Lock detect 3 */ + stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02); + stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); + stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); + + /* Lock detect 4 */ + stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03); + stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); + stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); + +} + +static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth, + u32 DemodXtalValue) +{ + dprintk("%s:\n", __func__); + + stv0367_writebits(state, F367TER_NRST_IIR, 0); + + switch (Bandwidth) { + case 6: + if (!stv0367ter_filt_coeff_init(state, + CellsCoeffs_6MHz_367cofdm, + DemodXtalValue)) + return 0; + break; + case 7: + if (!stv0367ter_filt_coeff_init(state, + CellsCoeffs_7MHz_367cofdm, + DemodXtalValue)) + return 0; + break; + case 8: + if (!stv0367ter_filt_coeff_init(state, + CellsCoeffs_8MHz_367cofdm, + DemodXtalValue)) + return 0; + break; + default: + return 0; + } + + stv0367_writebits(state, F367TER_NRST_IIR, 1); + + return 1; +} + +static void stv0367ter_agc_iir_rst(struct stv0367_state *state) +{ + + u8 com_n; + + dprintk("%s:\n", __func__); + + com_n = stv0367_readbits(state, F367TER_COM_N); + + stv0367_writebits(state, F367TER_COM_N, 0x07); + + stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00); + stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00); + + stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01); + stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01); + + stv0367_writebits(state, F367TER_COM_N, com_n); + +} + +static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3) +{ + int local_tempo = 0; + switch (mode) { + case 0: + local_tempo = tempo1; + break; + case 1: + local_tempo = tempo2; + break ; + + case 2: + local_tempo = tempo3; + break; + + default: + break; + } + /* msleep(local_tempo); */ + return local_tempo; +} + +static enum +stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state) +{ + int wd = 100; + unsigned short int SYR_var; + s32 SYRStatus; + + dprintk("%s:\n", __func__); + + SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); + + while ((!SYR_var) && (wd > 0)) { + usleep_range(2000, 3000); + wd -= 2; + SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); + } + + if (!SYR_var) + SYRStatus = FE_TER_NOSYMBOL; + else + SYRStatus = FE_TER_SYMBOLOK; + + dprintk("stv0367ter_check_syr SYRStatus %s\n", + SYR_var == 0 ? "No Symbol" : "OK"); + + return SYRStatus; +} + +static enum +stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state, + s32 FFTmode) +{ + + s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin; + int wd = 0; + + dprintk("%s:\n", __func__); + + switch (FFTmode) { + case 0: /*2k mode*/ + CPAMPMin = 20; + wd = 10; + break; + case 1: /*8k mode*/ + CPAMPMin = 80; + wd = 55; + break; + case 2: /*4k mode*/ + CPAMPMin = 40; + wd = 30; + break; + default: + CPAMPMin = 0xffff; /*drives to NOCPAMP */ + break; + } + + dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd); + + CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); + while ((CPAMPvalue < CPAMPMin) && (wd > 0)) { + usleep_range(1000, 2000); + wd -= 1; + CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); + /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */ + } + dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd); + if (CPAMPvalue < CPAMPMin) { + CPAMPStatus = FE_TER_NOCPAMP; + printk(KERN_ERR "CPAMP failed\n"); + } else { + printk(KERN_ERR "CPAMP OK !\n"); + CPAMPStatus = FE_TER_CPAMPOK; + } + + return CPAMPStatus; +} + +enum +stv0367_ter_signal_type stv0367ter_lock_algo(struct stv0367_state *state) +{ + enum stv0367_ter_signal_type ret_flag; + short int wd, tempo; + u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard; + u8 tmp, tmp2; + + dprintk("%s:\n", __func__); + + if (state == NULL) + return FE_TER_SWNOK; + + try = 0; + do { + ret_flag = FE_TER_LOCKOK; + + stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); + + if (state->config->if_iq_mode != 0) + stv0367_writebits(state, F367TER_COM_N, 0x07); + + stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */ + stv0367_writebits(state, F367TER_MODE, 0); + stv0367_writebits(state, F367TER_SYR_TR_DIS, 0); + usleep_range(5000, 10000); + + stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); + + + if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL) + return FE_TER_NOSYMBOL; + else { /* + if chip locked on wrong mode first try, + it must lock correctly second try */ + mode = stv0367_readbits(state, F367TER_SYR_MODE); + if (stv0367ter_check_cpamp(state, mode) == + FE_TER_NOCPAMP) { + if (try == 0) + ret_flag = FE_TER_NOCPAMP; + + } + } + + try++; + } while ((try < 10) && (ret_flag != FE_TER_LOCKOK)); + + tmp = stv0367_readreg(state, R367TER_SYR_STAT); + tmp2 = stv0367_readreg(state, R367TER_STATUS); + dprintk("state=%p\n", state); + dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n", + mode, tmp, tmp2); + + tmp = stv0367_readreg(state, R367TER_PRVIT); + tmp2 = stv0367_readreg(state, R367TER_I2CRPT); + dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2); + + tmp = stv0367_readreg(state, R367TER_GAIN_SRC1); + dprintk("GAIN_SRC1=0x%x\n", tmp); + + if ((mode != 0) && (mode != 1) && (mode != 2)) + return FE_TER_SWNOK; + + /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */ + + /*suppress EPQ auto for SYR_GARD 1/16 or 1/32 + and set channel predictor in automatic */ +#if 0 + switch (guard) { + + case 0: + case 1: + stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); + stv0367_writereg(state, R367TER_CHC_CTL, 0x01); + break; + case 2: + case 3: + stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); + stv0367_writereg(state, R367TER_CHC_CTL, 0x11); + break; + + default: + return FE_TER_SWNOK; + } +#endif + + /*reset fec an reedsolo FOR 367 only*/ + stv0367_writebits(state, F367TER_RST_SFEC, 1); + stv0367_writebits(state, F367TER_RST_REEDSOLO, 1); + usleep_range(1000, 2000); + stv0367_writebits(state, F367TER_RST_SFEC, 0); + stv0367_writebits(state, F367TER_RST_REEDSOLO, 0); + + u_var1 = stv0367_readbits(state, F367TER_LK); + u_var2 = stv0367_readbits(state, F367TER_PRF); + u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); + /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */ + + wd = stv0367ter_duration(mode, 125, 500, 250); + tempo = stv0367ter_duration(mode, 4, 16, 8); + + /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */ + while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) { + usleep_range(1000 * tempo, 1000 * (tempo + 1)); + wd -= tempo; + u_var1 = stv0367_readbits(state, F367TER_LK); + u_var2 = stv0367_readbits(state, F367TER_PRF); + u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); + /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */ + } + + if (!u_var1) + return FE_TER_NOLOCK; + + + if (!u_var2) + return FE_TER_NOPRFOUND; + + if (!u_var3) + return FE_TER_NOTPS; + + guard = stv0367_readbits(state, F367TER_SYR_GUARD); + stv0367_writereg(state, R367TER_CHC_CTL, 0x11); + switch (guard) { + case 0: + case 1: + stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); + /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/ + stv0367_writebits(state, F367TER_SYR_FILTER, 0); + break; + case 2: + case 3: + stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); + /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/ + stv0367_writebits(state, F367TER_SYR_FILTER, 1); + break; + + default: + return FE_TER_SWNOK; + } + + /* apply Sfec workaround if 8K 64QAM CR!=1/2*/ + if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) && + (mode == 1) && + (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) { + stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0); + stv0367_writereg(state, R367TER_SFDLYSETM, 0x60); + stv0367_writereg(state, R367TER_SFDLYSETL, 0x0); + } else + stv0367_writereg(state, R367TER_SFDLYSETH, 0x0); + + wd = stv0367ter_duration(mode, 125, 500, 250); + u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); + + while ((!u_var4) && (wd >= 0)) { + usleep_range(1000 * tempo, 1000 * (tempo + 1)); + wd -= tempo; + u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); + } + + if (!u_var4) + return FE_TER_NOLOCK; + + /* for 367 leave COM_N at 0x7 for IQ_mode*/ + /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) { + tempo=0; + while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) && + (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) { + ChipWaitOrAbort(state,1); + tempo+=1; + } + + stv0367_writebits(state,F367TER_COM_N,0x17); + } */ + + stv0367_writebits(state, F367TER_SYR_TR_DIS, 1); + + dprintk("FE_TER_LOCKOK !!!\n"); + + return FE_TER_LOCKOK; + +} + +static void stv0367ter_set_ts_mode(struct stv0367_state *state, + enum stv0367_ts_mode PathTS) +{ + + dprintk("%s:\n", __func__); + + if (state == NULL) + return; + + stv0367_writebits(state, F367TER_TS_DIS, 0); + switch (PathTS) { + default: + /*for removing warning :default we can assume in parallel mode*/ + case STV0367_PARALLEL_PUNCT_CLOCK: + stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0); + stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0); + break; + case STV0367_SERIAL_PUNCT_CLOCK: + stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1); +// stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1); + break; + } +} + +static void stv0367ter_set_clk_pol(struct stv0367_state *state, + enum stv0367_clk_pol clock) +{ + + dprintk("%s:\n", __func__); + + if (state == NULL) + return; + + switch (clock) { + case STV0367_RISINGEDGE_CLOCK: + stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1); + break; + case STV0367_FALLINGEDGE_CLOCK: + stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); + break; + /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/ + default: + stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); + break; + } +} + +#if 0 +static void stv0367ter_core_sw(struct stv0367_state *state) +{ + + dprintk("%s:\n", __func__); + + stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); + stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); + msleep(350); +} +#endif +static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on) +{ + struct stv0367_state *state = fe->demodulator_priv; + + dprintk("%s:\n", __func__); + + if (standby_on) { + stv0367_writebits(state, F367TER_STDBY, 1); + stv0367_writebits(state, F367TER_STDBY_FEC, 1); + stv0367_writebits(state, F367TER_STDBY_CORE, 1); + } else { + stv0367_writebits(state, F367TER_STDBY, 0); + stv0367_writebits(state, F367TER_STDBY_FEC, 0); + stv0367_writebits(state, F367TER_STDBY_CORE, 0); + } + + return 0; +} + +static int stv0367ter_sleep(struct dvb_frontend *fe) +{ + return stv0367ter_standby(fe, 1); +} + +int stv0367ter_init(struct dvb_frontend *fe) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367ter_state *ter_state = state->ter_state; + int i; + + dprintk("%s:\n", __func__); + + ter_state->pBER = 0; + + for (i = 0; i < STV0367TER_NBREGS; i++) + stv0367_writereg(state, def0367ter[i].addr, + def0367ter[i].value); + + switch (state->config->xtal) { + /*set internal freq to 53.125MHz */ + case 25000000: + stv0367_writereg(state, R367TER_PLLMDIV, 0xa); + stv0367_writereg(state, R367TER_PLLNDIV, 0x55); + stv0367_writereg(state, R367TER_PLLSETUP, 0x18); + break; + default: + case 27000000: + dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n"); + stv0367_writereg(state, R367TER_PLLMDIV, 0x1); + stv0367_writereg(state, R367TER_PLLNDIV, 0x8); + stv0367_writereg(state, R367TER_PLLSETUP, 0x18); + break; + case 30000000: + stv0367_writereg(state, R367TER_PLLMDIV, 0xc); + stv0367_writereg(state, R367TER_PLLNDIV, 0x55); + stv0367_writereg(state, R367TER_PLLSETUP, 0x18); + break; + } + + stv0367_writereg(state, R367TER_I2CRPT, 0x38); + stv0367_writereg(state, R367TER_ANACTRL, 0x00); + + /*Set TS1 and TS2 to serial or parallel mode */ + stv0367ter_set_ts_mode(state, state->config->ts_mode); + stv0367ter_set_clk_pol(state, state->config->clk_pol); + + state->chip_id = stv0367_readreg(state, R367TER_ID); + ter_state->first_lock = 0; + ter_state->unlock_counter = 2; + + return 0; +} + +static int stv0367ter_algo(struct dvb_frontend *fe, + struct dvb_frontend_parameters *param) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367ter_state *ter_state = state->ter_state; + int offset = 0, tempo = 0; + u8 u_var; + u8 /*constell,*/ counter, tps_rcvd[2]; + s8 step; + s32 timing_offset = 0; + u32 trl_nomrate = 0, InternalFreq = 0, temp = 0; + + dprintk("%s:\n", __func__); + + ter_state->frequency = param->frequency; + ter_state->force = FE_TER_FORCENONE + + stv0367_readbits(state, F367TER_FORCE) * 2; + ter_state->if_iq_mode = state->config->if_iq_mode; + switch (state->config->if_iq_mode) { + case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */ + dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n"); + stv0367_writebits(state, F367TER_TUNER_BB, 0); + stv0367_writebits(state, F367TER_LONGPATH_IF, 0); + stv0367_writebits(state, F367TER_DEMUX_SWAP, 0); + break; + case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */ + dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n"); + stv0367_writebits(state, F367TER_TUNER_BB, 0); + stv0367_writebits(state, F367TER_LONGPATH_IF, 1); + stv0367_writebits(state, F367TER_DEMUX_SWAP, 1); + break; + case FE_TER_IQ_TUNER: /* IQ mode */ + dprintk("ALGO: FE_TER_IQ_TUNER selected\n"); + stv0367_writebits(state, F367TER_TUNER_BB, 1); + stv0367_writebits(state, F367TER_PPM_INVSEL, 0); + break; + default: + printk(KERN_ERR "ALGO: wrong TUNER type selected\n"); + return -EINVAL; + } + + usleep_range(5000, 7000); + + switch (param->inversion) { + case INVERSION_AUTO: + default: + dprintk("%s: inversion AUTO\n", __func__); + if (ter_state->if_iq_mode == FE_TER_IQ_TUNER) + stv0367_writebits(state, F367TER_IQ_INVERT, + ter_state->sense); + else + stv0367_writebits(state, F367TER_INV_SPECTR, + ter_state->sense); + + break; + case INVERSION_ON: + case INVERSION_OFF: + if (ter_state->if_iq_mode == FE_TER_IQ_TUNER) + stv0367_writebits(state, F367TER_IQ_INVERT, + param->inversion); + else + stv0367_writebits(state, F367TER_INV_SPECTR, + param->inversion); + + break; + } + + if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) && + (ter_state->pBW != ter_state->bw)) { + stv0367ter_agc_iir_lock_detect_set(state); + + /*set fine agc target to 180 for LPIF or IQ mode*/ + /* set Q_AGCTarget */ + stv0367_writebits(state, F367TER_SEL_IQNTAR, 1); + stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); + /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ + + /* set Q_AGCTarget */ + stv0367_writebits(state, F367TER_SEL_IQNTAR, 0); + stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); + /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ + + if (!stv0367_iir_filt_init(state, ter_state->bw, + state->config->xtal)) + return -EINVAL; + /*set IIR filter once for 6,7 or 8MHz BW*/ + ter_state->pBW = ter_state->bw; + + stv0367ter_agc_iir_rst(state); + } + + if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO) + stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01); + else + stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00); + + InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000; + temp = (int) + ((((ter_state->bw * 64 * (1 << 15) * 100) + / (InternalFreq)) * 10) / 7); + + stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2); + temp = temp / 2; + stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256); + stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256); + + temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 + + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 + + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB); + temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq))); + stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256); + stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256); + temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 + + stv0367_readbits(state, F367TER_GAIN_SRC_LO); + + temp = (int) + ((InternalFreq - state->IF) * (1 << 16) / (InternalFreq)); + + dprintk("DEROT temp=0x%x\n", temp); + stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256); + stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256); + + ter_state->echo_pos = 0; + ter_state->ucblocks = 0; /* liplianin */ + ter_state->pBER = 0; /* liplianin */ + stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos); + + if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK) + return 0; + + ter_state->state = FE_TER_LOCKOK; + /* update results */ + tps_rcvd[0] = stv0367_readreg(state, R367TER_TPS_RCVD2); + tps_rcvd[1] = stv0367_readreg(state, R367TER_TPS_RCVD3); + + ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE); + ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD); + + ter_state->first_lock = 1; /* we know sense now :) */ + + ter_state->agc_val = + (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) + + (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) + + stv0367_readbits(state, F367TER_AGC2_VAL_LO) + + (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8); + + /* Carrier offset calculation */ + stv0367_writebits(state, F367TER_FREEZE, 1); + offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ; + offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8); + offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO)); + stv0367_writebits(state, F367TER_FREEZE, 0); + if (offset > 8388607) + offset -= 16777216; + + offset = offset * 2 / 16384; + + if (ter_state->mode == FE_TER_MODE_2K) + offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/ + else if (ter_state->mode == FE_TER_MODE_4K) + offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/ + else if (ter_state->mode == FE_TER_MODE_8K) + offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/ + + if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) { + if ((stv0367_readbits(state, F367TER_INV_SPECTR) == + (stv0367_readbits(state, + F367TER_STATUS_INV_SPECRUM) == 1))) + offset = offset * -1; + } + + if (ter_state->bw == 6) + offset = (offset * 6) / 8; + else if (ter_state->bw == 7) + offset = (offset * 7) / 8; + + ter_state->frequency += offset; + + tempo = 10; /* exit even if timing_offset stays null */ + while ((timing_offset == 0) && (tempo > 0)) { + usleep_range(10000, 20000); /*was 20ms */ + /* fine tuning of timing offset if required */ + timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO) + + 256 * stv0367_readbits(state, + F367TER_TRL_TOFFSET_HI); + if (timing_offset >= 32768) + timing_offset -= 65536; + trl_nomrate = (512 * stv0367_readbits(state, + F367TER_TRL_NOMRATE_HI) + + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 + + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB)); + + timing_offset = ((signed)(1000000 / trl_nomrate) * + timing_offset) / 2048; + tempo--; + } + + if (timing_offset <= 0) { + timing_offset = (timing_offset - 11) / 22; + step = -1; + } else { + timing_offset = (timing_offset + 11) / 22; + step = 1; + } + + for (counter = 0; counter < abs(timing_offset); counter++) { + trl_nomrate += step; + stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, + trl_nomrate % 2); + stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, + trl_nomrate / 2); + usleep_range(1000, 2000); + } + + usleep_range(5000, 6000); + /* unlocks could happen in case of trl centring big step, + then a core off/on restarts demod */ + u_var = stv0367_readbits(state, F367TER_LK); + + if (!u_var) { + stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); + msleep(20); + stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); + } + + return 0; +} + +static int stv0367ter_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *param) +{ + struct dvb_ofdm_parameters *op = ¶m->u.ofdm; + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367ter_state *ter_state = state->ter_state; + + /*u8 trials[2]; */ + s8 num_trials, index; + u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF }; + + stv0367ter_init(fe); + + if (fe->ops.tuner_ops.set_params) { + //if (fe->ops.i2c_gate_ctrl) + //fe->ops.i2c_gate_ctrl(fe, 1); + fe->ops.tuner_ops.set_params(fe, param); + //if (fe->ops.i2c_gate_ctrl) + //fe->ops.i2c_gate_ctrl(fe, 0); + } + if (fe->ops.tuner_ops.get_if) { + s32 IF; + fe->ops.tuner_ops.get_if(fe, &IF); + state->IF = IF / 1000; + } + switch (op->transmission_mode) { + default: + case TRANSMISSION_MODE_AUTO: + case TRANSMISSION_MODE_2K: + ter_state->mode = FE_TER_MODE_2K; + break; +/* case TRANSMISSION_MODE_4K: + pLook.mode = FE_TER_MODE_4K; + break;*/ + case TRANSMISSION_MODE_8K: + ter_state->mode = FE_TER_MODE_8K; + break; + } + + switch (op->guard_interval) { + default: + case GUARD_INTERVAL_1_32: + case GUARD_INTERVAL_1_16: + case GUARD_INTERVAL_1_8: + case GUARD_INTERVAL_1_4: + ter_state->guard = op->guard_interval; + break; + case GUARD_INTERVAL_AUTO: + ter_state->guard = GUARD_INTERVAL_1_32; + break; + } + + switch (op->bandwidth) { + case BANDWIDTH_6_MHZ: + ter_state->bw = FE_TER_CHAN_BW_6M; + break; + case BANDWIDTH_7_MHZ: + ter_state->bw = FE_TER_CHAN_BW_7M; + break; + case BANDWIDTH_8_MHZ: + default: + ter_state->bw = FE_TER_CHAN_BW_8M; + } + + ter_state->hierarchy = FE_TER_HIER_NONE; + + switch (param->inversion) { + case INVERSION_OFF: + case INVERSION_ON: + num_trials = 1; + break; + default: + num_trials = 2; + if (ter_state->first_lock) + num_trials = 1; + break; + } + + ter_state->state = FE_TER_NOLOCK; + index = 0; + + while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) { + if (!ter_state->first_lock) { + if (param->inversion == INVERSION_AUTO) + ter_state->sense = SenseTrials[index]; + + } + stv0367ter_algo(fe,/* &pLook, result,*/ param); + + if ((ter_state->state == FE_TER_LOCKOK) && + (param->inversion == INVERSION_AUTO) && + (index == 1)) { + /* invert spectrum sense */ + SenseTrials[index] = SenseTrials[0]; + SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2; + } + + index++; + } + + return 0; +} + +static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367ter_state *ter_state = state->ter_state; + u32 errs = 0; + + /*wait for counting completion*/ + if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) { + errs = + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1) + * (1 << 16)) + + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI) + * (1 << 8)) + + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO)); + ter_state->ucblocks = errs; + } + + (*ucblocks) = ter_state->ucblocks; + + return 0; +} + +static int stv0367ter_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *param) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367ter_state *ter_state = state->ter_state; + struct dvb_ofdm_parameters *op = ¶m->u.ofdm; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + int error = 0; + enum stv0367_ter_mode mode; + int constell = 0,/* snr = 0,*/ Data = 0; + + param->frequency = stv0367_get_tuner_freq(fe); + if ((int)param->frequency < 0) + param->frequency = c->frequency; + + constell = stv0367_readbits(state, F367TER_TPS_CONST); + if (constell == 0) + op->constellation = QPSK; + else if (constell == 1) + op->constellation = QAM_16; + else + op->constellation = QAM_64; + + param->inversion = stv0367_readbits(state, F367TER_INV_SPECTR); + + /* Get the Hierarchical mode */ + Data = stv0367_readbits(state, F367TER_TPS_HIERMODE); + + switch (Data) { + case 0: + op->hierarchy_information = HIERARCHY_NONE; + break; + case 1: + op->hierarchy_information = HIERARCHY_1; + break; + case 2: + op->hierarchy_information = HIERARCHY_2; + break; + case 3: + op->hierarchy_information = HIERARCHY_4; + break; + default: + op->hierarchy_information = HIERARCHY_AUTO; + break; /* error */ + } + + /* Get the FEC Rate */ + if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO) + Data = stv0367_readbits(state, F367TER_TPS_LPCODE); + else + Data = stv0367_readbits(state, F367TER_TPS_HPCODE); + + switch (Data) { + case 0: + op->code_rate_HP = FEC_1_2; + break; + case 1: + op->code_rate_HP = FEC_2_3; + break; + case 2: + op->code_rate_HP = FEC_3_4; + break; + case 3: + op->code_rate_HP = FEC_5_6; + break; + case 4: + op->code_rate_HP = FEC_7_8; + break; + default: + op->code_rate_HP = FEC_AUTO; + break; /* error */ + } + + mode = stv0367_readbits(state, F367TER_SYR_MODE); + + switch (mode) { + case FE_TER_MODE_2K: + op->transmission_mode = TRANSMISSION_MODE_2K; + break; +/* case FE_TER_MODE_4K: + op->transmission_mode = TRANSMISSION_MODE_4K; + break;*/ + case FE_TER_MODE_8K: + op->transmission_mode = TRANSMISSION_MODE_8K; + break; + default: + op->transmission_mode = TRANSMISSION_MODE_AUTO; + } + + op->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD); + + return error; +} + +static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct stv0367_state *state = fe->demodulator_priv; + u32 snru32 = 0; + int cpt = 0; + u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG); + + while (cpt < 10) { + usleep_range(2000, 3000); + if (cut == 0x50) /*cut 1.0 cut 1.1*/ + snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4; + else /*cu2.0*/ + snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR); + + cpt++; + } + + snru32 /= 10;/*average on 10 values*/ + + *snr = snru32 / 1000; + + return 0; +} + +#if 0 +static int stv0367ter_status(struct dvb_frontend *fe) +{ + + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367ter_state *ter_state = state->ter_state; + int locked = FALSE; + + locked = (stv0367_readbits(state, F367TER_LK)); + if (!locked) + ter_state->unlock_counter += 1; + else + ter_state->unlock_counter = 0; + + if (ter_state->unlock_counter > 2) { + if (!stv0367_readbits(state, F367TER_TPS_LOCK) || + (!stv0367_readbits(state, F367TER_LK))) { + stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); + usleep_range(2000, 3000); + stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); + msleep(350); + locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) && + (stv0367_readbits(state, F367TER_LK)); + } + + } + + return locked; +} +#endif + +static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct stv0367_state *state = fe->demodulator_priv; + + dprintk("%s:\n", __func__); + + *status = 0; + + if (stv0367_readbits(state, F367TER_LK)) { + *status |= FE_HAS_LOCK; + dprintk("%s: stv0367 has locked\n", __func__); + } + + return 0; +} + +static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367ter_state *ter_state = state->ter_state; + u32 Errors = 0, tber = 0, temporary = 0; + int abc = 0, def = 0; + + + /*wait for counting completion*/ + if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) + Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT) + * (1 << 16)) + + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI) + * (1 << 8)) + + ((u32)stv0367_readbits(state, + F367TER_SFEC_ERR_CNT_LO)); + /*measurement not completed, load previous value*/ + else { + tber = ter_state->pBER; + return 0; + } + + abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE); + def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT); + + if (Errors == 0) { + tber = 0; + } else if (abc == 0x7) { + if (Errors <= 4) { + temporary = (Errors * 1000000000) / (8 * (1 << 14)); + temporary = temporary; + } else if (Errors <= 42) { + temporary = (Errors * 100000000) / (8 * (1 << 14)); + temporary = temporary * 10; + } else if (Errors <= 429) { + temporary = (Errors * 10000000) / (8 * (1 << 14)); + temporary = temporary * 100; + } else if (Errors <= 4294) { + temporary = (Errors * 1000000) / (8 * (1 << 14)); + temporary = temporary * 1000; + } else if (Errors <= 42949) { + temporary = (Errors * 100000) / (8 * (1 << 14)); + temporary = temporary * 10000; + } else if (Errors <= 429496) { + temporary = (Errors * 10000) / (8 * (1 << 14)); + temporary = temporary * 100000; + } else { /*if (Errors<4294967) 2^22 max error*/ + temporary = (Errors * 1000) / (8 * (1 << 14)); + temporary = temporary * 100000; /* still to *10 */ + } + + /* Byte error*/ + if (def == 2) + /*tber=Errors/(8*(1 <<14));*/ + tber = temporary; + else if (def == 3) + /*tber=Errors/(8*(1 <<16));*/ + tber = temporary / 4; + else if (def == 4) + /*tber=Errors/(8*(1 <<18));*/ + tber = temporary / 16; + else if (def == 5) + /*tber=Errors/(8*(1 <<20));*/ + tber = temporary / 64; + else if (def == 6) + /*tber=Errors/(8*(1 <<22));*/ + tber = temporary / 256; + else + /* should not pass here*/ + tber = 0; + + if ((Errors < 4294967) && (Errors > 429496)) + tber *= 10; + + } + + /* save actual value */ + ter_state->pBER = tber; + + (*ber) = tber; + + return 0; +} +#if 0 +static u32 stv0367ter_get_per(struct stv0367_state *state) +{ + struct stv0367ter_state *ter_state = state->ter_state; + u32 Errors = 0, Per = 0, temporary = 0; + int abc = 0, def = 0, cpt = 0; + + while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) && + (cpt < 400)) || ((Errors == 0) && (cpt < 400))) { + usleep_range(1000, 2000); + Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1) + * (1 << 16)) + + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI) + * (1 << 8)) + + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO)); + cpt++; + } + abc = stv0367_readbits(state, F367TER_ERR_SRC1); + def = stv0367_readbits(state, F367TER_NUM_EVT1); + + if (Errors == 0) + Per = 0; + else if (abc == 0x9) { + if (Errors <= 4) { + temporary = (Errors * 1000000000) / (8 * (1 << 8)); + temporary = temporary; + } else if (Errors <= 42) { + temporary = (Errors * 100000000) / (8 * (1 << 8)); + temporary = temporary * 10; + } else if (Errors <= 429) { + temporary = (Errors * 10000000) / (8 * (1 << 8)); + temporary = temporary * 100; + } else if (Errors <= 4294) { + temporary = (Errors * 1000000) / (8 * (1 << 8)); + temporary = temporary * 1000; + } else if (Errors <= 42949) { + temporary = (Errors * 100000) / (8 * (1 << 8)); + temporary = temporary * 10000; + } else { /*if(Errors<=429496) 2^16 errors max*/ + temporary = (Errors * 10000) / (8 * (1 << 8)); + temporary = temporary * 100000; + } + + /* pkt error*/ + if (def == 2) + /*Per=Errors/(1 << 8);*/ + Per = temporary; + else if (def == 3) + /*Per=Errors/(1 << 10);*/ + Per = temporary / 4; + else if (def == 4) + /*Per=Errors/(1 << 12);*/ + Per = temporary / 16; + else if (def == 5) + /*Per=Errors/(1 << 14);*/ + Per = temporary / 64; + else if (def == 6) + /*Per=Errors/(1 << 16);*/ + Per = temporary / 256; + else + Per = 0; + + } + /* save actual value */ + ter_state->pPER = Per; + + return Per; +} +#endif +static int stv0367_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings + *fe_tune_settings) +{ + fe_tune_settings->min_delay_ms = 1000; + fe_tune_settings->step_size = 0; + fe_tune_settings->max_drift = 0; + + return 0; +} + +static void stv0367_release(struct dvb_frontend *fe) +{ + struct stv0367_state *state = fe->demodulator_priv; + + kfree(state->ter_state); + kfree(state->cab_state); + kfree(state); +} + +static struct dvb_frontend_ops stv0367ter_ops = { + .info = { + .name = "ST STV0367 DVB-T", + .type = FE_OFDM, + .frequency_min = 47000000, + .frequency_max = 862000000, + .frequency_stepsize = 15625, + .frequency_tolerance = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | + FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | + FE_CAN_INVERSION_AUTO | + FE_CAN_MUTE_TS + }, + .release = stv0367_release, + .init = stv0367ter_init, + .sleep = stv0367ter_sleep, + .i2c_gate_ctrl = stv0367ter_gate_ctrl, + .set_frontend = stv0367ter_set_frontend, + .get_frontend = stv0367ter_get_frontend, + .get_tune_settings = stv0367_get_tune_settings, + .read_status = stv0367ter_read_status, + .read_ber = stv0367ter_read_ber,/* too slow */ +/* .read_signal_strength = stv0367_read_signal_strength,*/ + .read_snr = stv0367ter_read_snr, + .read_ucblocks = stv0367ter_read_ucblocks, +}; + +struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, + struct i2c_adapter *i2c) +{ + struct stv0367_state *state = NULL; + struct stv0367ter_state *ter_state = NULL; + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); + if (state == NULL) + goto error; + ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL); + if (ter_state == NULL) + goto error; + + /* setup the state */ + state->i2c = i2c; + state->config = config; + state->ter_state = ter_state; + state->fe.ops = stv0367ter_ops; + state->fe.demodulator_priv = state; + state->chip_id = stv0367_readreg(state, 0xf000); + + dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); + + /* check if the demod is there */ + if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) + goto error; + + return &state->fe; + +error: + kfree(ter_state); + kfree(state); + return NULL; +} +EXPORT_SYMBOL(stv0367ter_attach); + +static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct stv0367_state *state = fe->demodulator_priv; + + dprintk("%s:\n", __func__); + + stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0); + + return 0; +} + +static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz) +{ + struct stv0367_state *state = fe->demodulator_priv; + u32 mclk_Hz = 0; /* master clock frequency (Hz) */ + u32 M, N, P; + + if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) { + N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV); + if (N == 0) + N = N + 1; + + M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV); + if (M == 0) + M = M + 1; + + P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV); + + if (P > 5) + P = 5; + + mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P)); + dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n", + mclk_Hz); + } else + mclk_Hz = ExtClk_Hz; + + dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz); + + return mclk_Hz; +} + +static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz) +{ + u32 ADCClk_Hz = ExtClk_Hz; + + ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz); + + return ADCClk_Hz; +} + +enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state, + u32 SymbolRate, + enum stv0367cab_mod QAMSize) +{ + /* Set QAM size */ + stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize); + + /* Set Registers settings specific to the QAM size */ + switch (QAMSize) { + case FE_CAB_MOD_QAM4: + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); + break; + case FE_CAB_MOD_QAM16: + stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64); + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); + stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); + stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); + stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); + stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a); + break; + case FE_CAB_MOD_QAM32: + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); + stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e); + stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7); + stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d); + stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); + stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); + break; + case FE_CAB_MOD_QAM64: + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82); + stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); + if (SymbolRate > 45000000) { + stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5); + } else if (SymbolRate > 25000000) { + stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); + } else { + stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); + } + stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); + stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); + stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99); + break; + case FE_CAB_MOD_QAM128: + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); + stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76); + stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1); + if (SymbolRate > 45000000) + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); + else if (SymbolRate > 25000000) + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); + else + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97); + + stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e); + stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); + stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); + break; + case FE_CAB_MOD_QAM256: + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94); + stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); + stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); + if (SymbolRate > 45000000) + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); + else if (SymbolRate > 25000000) + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); + else + stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); + + stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); + stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85); + stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); + stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); + break; + case FE_CAB_MOD_QAM512: + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); + break; + case FE_CAB_MOD_QAM1024: + stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); + break; + default: + break; + } + + return QAMSize; +} + +static u32 stv0367cab_set_derot_freq(struct stv0367_state *state, + u32 adc_hz, s32 derot_hz) +{ + u32 sampled_if = 0; + u32 adc_khz; + + adc_khz = adc_hz / 1000; + + dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz); + + if (adc_khz != 0) { + if (derot_hz < 1000000) + derot_hz = adc_hz / 4; /* ZIF operation */ + if (derot_hz > adc_hz) + derot_hz = derot_hz - adc_hz; + sampled_if = (u32)derot_hz / 1000; + sampled_if *= 32768; + sampled_if /= adc_khz; + sampled_if *= 256; + } + + if (sampled_if > 8388607) + sampled_if = 8388607; + + dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if); + + stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if); + stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8)); + stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16)); + + return derot_hz; +} + +static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz) +{ + u32 sampled_if; + + sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) + + (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) + + (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16); + + sampled_if /= 256; + sampled_if *= (adc_hz / 1000); + sampled_if += 1; + sampled_if /= 32768; + + return sampled_if; +} + +static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz, + u32 mclk_hz, u32 SymbolRate, + enum stv0367cab_mod QAMSize) +{ + u32 QamSizeCorr = 0; + u32 u32_tmp = 0, u32_tmp1 = 0; + u32 adp_khz; + + dprintk("%s:\n", __func__); + + /* Set Correction factor of SRC gain */ + switch (QAMSize) { + case FE_CAB_MOD_QAM4: + QamSizeCorr = 1110; + break; + case FE_CAB_MOD_QAM16: + QamSizeCorr = 1032; + break; + case FE_CAB_MOD_QAM32: + QamSizeCorr = 954; + break; + case FE_CAB_MOD_QAM64: + QamSizeCorr = 983; + break; + case FE_CAB_MOD_QAM128: + QamSizeCorr = 957; + break; + case FE_CAB_MOD_QAM256: + QamSizeCorr = 948; + break; + case FE_CAB_MOD_QAM512: + QamSizeCorr = 0; + break; + case FE_CAB_MOD_QAM1024: + QamSizeCorr = 944; + break; + default: + break; + } + + /* Transfer ratio calculation */ + if (adc_hz != 0) { + u32_tmp = 256 * SymbolRate; + u32_tmp = u32_tmp / adc_hz; + } + stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp); + + /* Symbol rate and SRC gain calculation */ + adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */ + if (adp_khz != 0) { + u32_tmp = SymbolRate; + u32_tmp1 = SymbolRate; + + if (u32_tmp < 2097152) { /* 2097152 = 2^21 */ + /* Symbol rate calculation */ + u32_tmp *= 2048; /* 2048 = 2^11 */ + u32_tmp = u32_tmp / adp_khz; + u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */ + u32_tmp /= 125 ; /* 125 = 1000/2^3 */ + u32_tmp = u32_tmp * 8; /* 8 = 2^3 */ + + /* SRC Gain Calculation */ + u32_tmp1 *= 2048; /* *2*2^10 */ + u32_tmp1 /= 439; /* *2/878 */ + u32_tmp1 *= 256; /* *2^8 */ + u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ + u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ + u32_tmp1 = u32_tmp1 / 10000000; + + } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */ + /* Symbol rate calculation */ + u32_tmp *= 1024 ; /* 1024 = 2**10 */ + u32_tmp = u32_tmp / adp_khz; + u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */ + u32_tmp /= 125 ; /* 125 = 1000/2**3 */ + u32_tmp = u32_tmp * 16; /* 16 = 2**4 */ + + /* SRC Gain Calculation */ + u32_tmp1 *= 1024; /* *2*2^9 */ + u32_tmp1 /= 439; /* *2/878 */ + u32_tmp1 *= 256; /* *2^8 */ + u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/ + u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ + u32_tmp1 = u32_tmp1 / 5000000; + } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */ + /* Symbol rate calculation */ + u32_tmp *= 512 ; /* 512 = 2**9 */ + u32_tmp = u32_tmp / adp_khz; + u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */ + u32_tmp /= 125 ; /* 125 = 1000/2**3 */ + u32_tmp = u32_tmp * 32; /* 32 = 2**5 */ + + /* SRC Gain Calculation */ + u32_tmp1 *= 512; /* *2*2^8 */ + u32_tmp1 /= 439; /* *2/878 */ + u32_tmp1 *= 256; /* *2^8 */ + u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ + u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ + u32_tmp1 = u32_tmp1 / 2500000; + } else { + /* Symbol rate calculation */ + u32_tmp *= 256 ; /* 256 = 2**8 */ + u32_tmp = u32_tmp / adp_khz; + u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */ + u32_tmp /= 125 ; /* 125 = 1000/2**3 */ + u32_tmp = u32_tmp * 64; /* 64 = 2**6 */ + + /* SRC Gain Calculation */ + u32_tmp1 *= 256; /* 2*2^7 */ + u32_tmp1 /= 439; /* *2/878 */ + u32_tmp1 *= 256; /* *2^8 */ + u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ + u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ + u32_tmp1 = u32_tmp1 / 1250000; + } + } +#if 0 + /* Filters' coefficients are calculated and written + into registers only if the filters are enabled */ + if (stv0367_readbits(state, F367CAB_ADJ_EN)) { + stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz, + SymbolRate); + /* AllPass filter must be enabled + when the adjacents filter is used */ + stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1); + stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate); + } else + /* AllPass filter must be disabled + when the adjacents filter is not used */ +#endif + stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); + + stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp); + stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8)); + stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16)); + stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24)); + + stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff); + stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff); + + return SymbolRate ; +} + +static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz) +{ + u32 regsym; + u32 adp_khz; + + regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) + + (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) + + (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) + + (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24); + + adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */ + + if (regsym < 134217728) { /* 134217728L = 2**27*/ + regsym = regsym * 32; /* 32 = 2**5 */ + regsym = regsym / 32768; /* 32768L = 2**15 */ + regsym = adp_khz * regsym; /* AdpClk in kHz */ + regsym = regsym / 128; /* 128 = 2**7 */ + regsym *= 125 ; /* 125 = 1000/2**3 */ + regsym /= 2048 ; /* 2048 = 2**11 */ + } else if (regsym < 268435456) { /* 268435456L = 2**28 */ + regsym = regsym * 16; /* 16 = 2**4 */ + regsym = regsym / 32768; /* 32768L = 2**15 */ + regsym = adp_khz * regsym; /* AdpClk in kHz */ + regsym = regsym / 128; /* 128 = 2**7 */ + regsym *= 125 ; /* 125 = 1000/2**3*/ + regsym /= 1024 ; /* 256 = 2**10*/ + } else if (regsym < 536870912) { /* 536870912L = 2**29*/ + regsym = regsym * 8; /* 8 = 2**3 */ + regsym = regsym / 32768; /* 32768L = 2**15 */ + regsym = adp_khz * regsym; /* AdpClk in kHz */ + regsym = regsym / 128; /* 128 = 2**7 */ + regsym *= 125 ; /* 125 = 1000/2**3 */ + regsym /= 512 ; /* 128 = 2**9 */ + } else { + regsym = regsym * 4; /* 4 = 2**2 */ + regsym = regsym / 32768; /* 32768L = 2**15 */ + regsym = adp_khz * regsym; /* AdpClk in kHz */ + regsym = regsym / 128; /* 128 = 2**7 */ + regsym *= 125 ; /* 125 = 1000/2**3 */ + regsym /= 256 ; /* 64 = 2**8 */ + } + + return regsym; +} + +static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct stv0367_state *state = fe->demodulator_priv; + + dprintk("%s:\n", __func__); + + *status = 0; + + if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) { + *status |= FE_HAS_LOCK; + dprintk("%s: stv0367 has locked\n", __func__); + } + + return 0; +} + +static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on) +{ + struct stv0367_state *state = fe->demodulator_priv; + + dprintk("%s:\n", __func__); + + if (standby_on) { + stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03); + stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01); + stv0367_writebits(state, F367CAB_STDBY, 1); + stv0367_writebits(state, F367CAB_STDBY_CORE, 1); + stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0); + stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0); + stv0367_writebits(state, F367CAB_POFFQ, 1); + stv0367_writebits(state, F367CAB_POFFI, 1); + } else { + stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00); + stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00); + stv0367_writebits(state, F367CAB_STDBY, 0); + stv0367_writebits(state, F367CAB_STDBY_CORE, 0); + stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1); + stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1); + stv0367_writebits(state, F367CAB_POFFQ, 0); + stv0367_writebits(state, F367CAB_POFFI, 0); + } + + return 0; +} + +static int stv0367cab_sleep(struct dvb_frontend *fe) +{ + return stv0367cab_standby(fe, 1); +} + +int stv0367cab_init(struct dvb_frontend *fe) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367cab_state *cab_state = state->cab_state; + int i; + + dprintk("%s:\n", __func__); + + for (i = 0; i < STV0367CAB_NBREGS; i++) + stv0367_writereg(state, def0367cab[i].addr, + def0367cab[i].value); + + switch (state->config->ts_mode) { + case STV0367_DVBCI_CLOCK: + dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n"); + stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03); + break; + case STV0367_SERIAL_PUNCT_CLOCK: + case STV0367_SERIAL_CONT_CLOCK: + stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01); + break; + case STV0367_PARALLEL_PUNCT_CLOCK: + case STV0367_OUTPUTMODE_DEFAULT: + stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00); + break; + } + + switch (state->config->clk_pol) { + case STV0367_RISINGEDGE_CLOCK: + stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00); + break; + case STV0367_FALLINGEDGE_CLOCK: + case STV0367_CLOCKPOLARITY_DEFAULT: + stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01); + break; + } + + stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00); + + stv0367_writebits(state, F367CAB_CT_NBST, 0x01); + + stv0367_writebits(state, F367CAB_TS_SWAP, 0x01); + + stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00); + + stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */ + + cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal); + cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal); + + return 0; +} +static +enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state, + struct dvb_frontend_parameters *param) +{ + struct dvb_qam_parameters *op = ¶m->u.qam; + struct stv0367cab_state *cab_state = state->cab_state; + enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC; + u32 QAMFEC_Lock, QAM_Lock, u32_tmp, + LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols, + CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut; + u8 TrackAGCAccum; + s32 tmp; + + dprintk("%s:\n", __func__); + + /* Timeouts calculation */ + /* A max lock time of 25 ms is allowed for delayed AGC */ + AGCTimeOut = 25; + /* 100000 symbols needed by the TRL as a maximum value */ + TRLTimeOut = 100000000 / op->symbol_rate; + /* CRLSymbols is the needed number of symbols to achieve a lock + within [-4%, +4%] of the symbol rate. + CRL timeout is calculated + for a lock within [-search_range, +search_range]. + EQL timeout can be changed depending on + the micro-reflections we want to handle. + A characterization must be performed + with these echoes to get new timeout values. + */ + switch (op->modulation) { + case QAM_16: + CRLSymbols = 150000; + EQLTimeOut = 100; + break; + case QAM_32: + CRLSymbols = 250000; + EQLTimeOut = 100; + break; + case QAM_64: + CRLSymbols = 200000; + EQLTimeOut = 100; + break; + case QAM_128: + CRLSymbols = 250000; + EQLTimeOut = 100; + break; + case QAM_256: + CRLSymbols = 250000; + EQLTimeOut = 100; + break; + default: + CRLSymbols = 200000; + EQLTimeOut = 100; + break; + } +#if 0 + if (pIntParams->search_range < 0) { + CRLTimeOut = (25 * CRLSymbols * + (-pIntParams->search_range / 1000)) / + (pIntParams->symbol_rate / 1000); + } else +#endif + CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) / + (op->symbol_rate / 1000); + + CRLTimeOut = (1000 * CRLTimeOut) / op->symbol_rate; + /* Timeouts below 50ms are coerced */ + if (CRLTimeOut < 50) + CRLTimeOut = 50; + /* A maximum of 100 TS packets is needed to get FEC lock even in case + the spectrum inversion needs to be changed. + This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps + */ + FECTimeOut = 20; + DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; + + dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut); + + /* Reset the TRL to ensure nothing starts until the + AGC is stable which ensures a better lock time + */ + stv0367_writereg(state, R367CAB_CTRL_1, 0x04); + /* Set AGC accumulation time to minimum and lock threshold to maximum + in order to speed up the AGC lock */ + TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL); + stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0); + /* Modulus Mapper is disabled */ + stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0); + /* Disable the sweep function */ + stv0367_writebits(state, F367CAB_SWEEP_EN, 0); + /* The sweep function is never used, Sweep rate must be set to 0 */ + /* Set the derotator frequency in Hz */ + stv0367cab_set_derot_freq(state, cab_state->adc_clk, + (1000 * (s32)state->IF + cab_state->derot_offset)); + /* Disable the Allpass Filter when the symbol rate is out of range */ + if ((op->symbol_rate > 10800000) | (op->symbol_rate < 1800000)) { + stv0367_writebits(state, F367CAB_ADJ_EN, 0); + stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); + } +#if 0 + /* Check if the tuner is locked */ + tuner_lock = stv0367cab_tuner_get_status(fe); + if (tuner_lock == 0) + return FE_367CAB_NOTUNER; +#endif + /* Relase the TRL to start demodulator acquisition */ + /* Wait for QAM lock */ + LockTime = 0; + stv0367_writereg(state, R367CAB_CTRL_1, 0x00); + do { + QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS); + if ((LockTime >= (DemodTimeOut - EQLTimeOut)) && + (QAM_Lock == 0x04)) + /* + * We don't wait longer, the frequency/phase offset + * must be too big + */ + LockTime = DemodTimeOut; + else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) && + (QAM_Lock == 0x02)) + /* + * We don't wait longer, either there is no signal or + * it is not the right symbol rate or it is an analog + * carrier + */ + { + LockTime = DemodTimeOut; + u32_tmp = stv0367_readbits(state, + F367CAB_AGC_PWR_WORD_LO) + + (stv0367_readbits(state, + F367CAB_AGC_PWR_WORD_ME) << 8) + + (stv0367_readbits(state, + F367CAB_AGC_PWR_WORD_HI) << 16); + if (u32_tmp >= 131072) + u32_tmp = 262144 - u32_tmp; + u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state, + F367CAB_AGC_IF_BWSEL))); + + if (u32_tmp < stv0367_readbits(state, + F367CAB_AGC_PWRREF_LO) + + 256 * stv0367_readbits(state, + F367CAB_AGC_PWRREF_HI) - 10) + QAM_Lock = 0x0f; + } else { + usleep_range(10000, 20000); + LockTime += 10; + } + dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime); + tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); + + dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp); + + } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) && + (LockTime < DemodTimeOut)); + + dprintk("QAM_Lock=0x%x\n", QAM_Lock); + + tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); + dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp); + tmp = stv0367_readreg(state, R367CAB_IT_STATUS2); + dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp); + + tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk); + dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp); + + if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) { + /* Wait for FEC lock */ + LockTime = 0; + do { + usleep_range(5000, 7000); + LockTime += 5; + QAMFEC_Lock = stv0367_readbits(state, + F367CAB_QAMFEC_LOCK); + } while (!QAMFEC_Lock && (LockTime < FECTimeOut)); + } else + QAMFEC_Lock = 0; + + if (QAMFEC_Lock) { + signalType = FE_CAB_DATAOK; + cab_state->modulation = op->modulation; + cab_state->spect_inv = stv0367_readbits(state, + F367CAB_QUAD_INV); +#if 0 +/* not clear for me */ + if (state->IF != 0) { + if (state->IF > cab_state->adc_clk / 1000) { + cab_state->freq_khz = + FE_Cab_TunerGetFrequency(pIntParams->hTuner) + - stv0367cab_get_derot_freq(state, cab_state->adc_clk) + - cab_state->adc_clk / 1000 + state->IF; + } else { + cab_state->freq_khz = + FE_Cab_TunerGetFrequency(pIntParams->hTuner) + - stv0367cab_get_derot_freq(state, cab_state->adc_clk) + + state->IF; + } + } else { + cab_state->freq_khz = + FE_Cab_TunerGetFrequency(pIntParams->hTuner) + + stv0367cab_get_derot_freq(state, + cab_state->adc_clk) - + cab_state->adc_clk / 4000; + } +#endif + cab_state->symbol_rate = stv0367cab_GetSymbolRate(state, + cab_state->mclk); + cab_state->locked = 1; + + /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/ + } else { + switch (QAM_Lock) { + case 1: + signalType = FE_CAB_NOAGC; + break; + case 2: + signalType = FE_CAB_NOTIMING; + break; + case 3: + signalType = FE_CAB_TIMINGOK; + break; + case 4: + signalType = FE_CAB_NOCARRIER; + break; + case 5: + signalType = FE_CAB_CARRIEROK; + break; + case 7: + signalType = FE_CAB_NOBLIND; + break; + case 8: + signalType = FE_CAB_BLINDOK; + break; + case 10: + signalType = FE_CAB_NODEMOD; + break; + case 11: + signalType = FE_CAB_DEMODOK; + break; + case 12: + signalType = FE_CAB_DEMODOK; + break; + case 13: + signalType = FE_CAB_NODEMOD; + break; + case 14: + signalType = FE_CAB_NOBLIND; + break; + case 15: + signalType = FE_CAB_NOSIGNAL; + break; + default: + break; + } + + } + + /* Set the AGC control values to tracking values */ + stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum); + return signalType; +} + +static int stv0367cab_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *param) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367cab_state *cab_state = state->cab_state; + struct dvb_qam_parameters *op = ¶m->u.qam; + enum stv0367cab_mod QAMSize = 0; + + dprintk("%s: freq = %d, srate = %d\n", __func__, + param->frequency, op->symbol_rate); + + cab_state->derot_offset = 0; + + switch (op->modulation) { + case QAM_16: + QAMSize = FE_CAB_MOD_QAM16; + break; + case QAM_32: + QAMSize = FE_CAB_MOD_QAM32; + break; + case QAM_64: + QAMSize = FE_CAB_MOD_QAM64; + break; + case QAM_128: + QAMSize = FE_CAB_MOD_QAM128; + break; + case QAM_256: + QAMSize = FE_CAB_MOD_QAM256; + break; + default: + break; + } + + stv0367cab_init(fe); + + /* Tuner Frequency Setting */ + if (fe->ops.tuner_ops.set_params) { + //if (fe->ops.i2c_gate_ctrl) + //fe->ops.i2c_gate_ctrl(fe, 1); + fe->ops.tuner_ops.set_params(fe, param); + //if (fe->ops.i2c_gate_ctrl) + //fe->ops.i2c_gate_ctrl(fe, 0); + } + if (fe->ops.tuner_ops.get_if) { + s32 IF; + fe->ops.tuner_ops.get_if(fe, &IF); + state->IF = IF / 1000; + } + + stv0367cab_SetQamSize( + state, + op->symbol_rate, + QAMSize); + + stv0367cab_set_srate(state, + cab_state->adc_clk, + cab_state->mclk, + op->symbol_rate, + QAMSize); + /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */ + cab_state->state = stv0367cab_algo(state, param); + return 0; +} + +static int stv0367cab_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *param) +{ + struct stv0367_state *state = fe->demodulator_priv; + struct stv0367cab_state *cab_state = state->cab_state; + struct dvb_qam_parameters *op = ¶m->u.qam; + + enum stv0367cab_mod QAMSize; + + dprintk("%s:\n", __func__); + + op->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk); + + QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); + switch (QAMSize) { + case FE_CAB_MOD_QAM16: + op->modulation = QAM_16; + break; + case FE_CAB_MOD_QAM32: + op->modulation = QAM_32; + break; + case FE_CAB_MOD_QAM64: + op->modulation = QAM_64; + break; + case FE_CAB_MOD_QAM128: + op->modulation = QAM_128; + break; + case QAM_256: + op->modulation = QAM_256; + break; + default: + break; + } + + param->frequency = stv0367_get_tuner_freq(fe); + + dprintk("%s: tuner frequency = %d\n", __func__, param->frequency); + + if (state->IF == 0) { + param->frequency += + (stv0367cab_get_derot_freq(state, cab_state->adc_clk) - + cab_state->adc_clk / 4000); + return 0; + } + + if (state->IF > cab_state->adc_clk / 1000) + param->frequency += (state->IF + - stv0367cab_get_derot_freq(state, cab_state->adc_clk) + - cab_state->adc_clk / 1000); + else + param->frequency += (state->IF + - stv0367cab_get_derot_freq(state, cab_state->adc_clk)); + + return 0; +} + +#if 0 +void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize, + u32 symbol_rate, FE_367qam_Monitor *Monitor_results) +{ + stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results); + stv0367cab_GetPacketsCount(state, Monitor_results); + + return; +} + +static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct stv0367_state *state = fe->demodulator_priv; + + return 0; +} +#endif +static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state) +{ + s32 rfLevel = 0; + s32 RfAgcPwm = 0, IfAgcPwm = 0; + u8 i; + + stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0); + + RfAgcPwm = + (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) + + (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2); + RfAgcPwm = 100 * RfAgcPwm / 1023; + + IfAgcPwm = + stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) + + (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8); + if (IfAgcPwm >= 2048) + IfAgcPwm -= 2048; + else + IfAgcPwm += 2048; + + IfAgcPwm = 100 * IfAgcPwm / 4095; + + /* For DTT75467 on NIM */ + if (RfAgcPwm < 90 && IfAgcPwm < 28) { + for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) { + if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) { + rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i]; + break; + } + } + if (i == RF_LOOKUP_TABLE_SIZE) + rfLevel = -56; + } else { /*if IF AGC>10*/ + for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) { + if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) { + rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i]; + break; + } + } + if (i == RF_LOOKUP_TABLE2_SIZE) + rfLevel = -72; + } + return rfLevel; +} + +static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct stv0367_state *state = fe->demodulator_priv; + + s32 signal = stv0367cab_get_rf_lvl(state); + + dprintk("%s: signal=%d dBm\n", __func__, signal); + + if (signal <= -72) + *strength = 65535; + else + *strength = (22 + signal) * (-1311); + + dprintk("%s: strength=%d\n", __func__, (*strength)); + + return 0; +} + +static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct stv0367_state *state = fe->demodulator_priv; + u32 noisepercentage; + enum stv0367cab_mod QAMSize; + u32 regval = 0, temp = 0; + int power, i; + + QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); + switch (QAMSize) { + case FE_CAB_MOD_QAM4: + power = 21904; + break; + case FE_CAB_MOD_QAM16: + power = 20480; + break; + case FE_CAB_MOD_QAM32: + power = 23040; + break; + case FE_CAB_MOD_QAM64: + power = 21504; + break; + case FE_CAB_MOD_QAM128: + power = 23616; + break; + case FE_CAB_MOD_QAM256: + power = 21760; + break; + case FE_CAB_MOD_QAM512: + power = 1; + break; + case FE_CAB_MOD_QAM1024: + power = 21280; + break; + default: + power = 1; + break; + } + + for (i = 0; i < 10; i++) { + regval += (stv0367_readbits(state, F367CAB_SNR_LO) + + 256 * stv0367_readbits(state, F367CAB_SNR_HI)); + } + + regval /= 10; /*for average over 10 times in for loop above*/ + if (regval != 0) { + temp = power + * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER))); + temp /= regval; + } + + /* table values, not needed to calculate logarithms */ + if (temp >= 5012) + noisepercentage = 100; + else if (temp >= 3981) + noisepercentage = 93; + else if (temp >= 3162) + noisepercentage = 86; + else if (temp >= 2512) + noisepercentage = 79; + else if (temp >= 1995) + noisepercentage = 72; + else if (temp >= 1585) + noisepercentage = 65; + else if (temp >= 1259) + noisepercentage = 58; + else if (temp >= 1000) + noisepercentage = 50; + else if (temp >= 794) + noisepercentage = 43; + else if (temp >= 501) + noisepercentage = 36; + else if (temp >= 316) + noisepercentage = 29; + else if (temp >= 200) + noisepercentage = 22; + else if (temp >= 158) + noisepercentage = 14; + else if (temp >= 126) + noisepercentage = 7; + else + noisepercentage = 0; + + dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage); + + *snr = (noisepercentage * 65535) / 100; + + return 0; +} + +static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct stv0367_state *state = fe->demodulator_priv; + int corrected, tscount; + + *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8) + | stv0367_readreg(state, R367CAB_RS_COUNTER_4); + corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8) + | stv0367_readreg(state, R367CAB_RS_COUNTER_2); + tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8) + | stv0367_readreg(state, R367CAB_RS_COUNTER_1); + + dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n", + __func__, *ucblocks, corrected, tscount); + + return 0; +}; + +static struct dvb_frontend_ops stv0367cab_ops = { + .info = { + .name = "ST STV0367 DVB-C", + .type = FE_QAM, + .frequency_min = 47000000, + .frequency_max = 862000000, + .frequency_stepsize = 62500, + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = 0x400 |/* FE_CAN_QAM_4 */ + FE_CAN_QAM_16 | FE_CAN_QAM_32 | + FE_CAN_QAM_64 | FE_CAN_QAM_128 | + FE_CAN_QAM_256 | FE_CAN_FEC_AUTO + }, + .release = stv0367_release, + .init = stv0367cab_init, + .sleep = stv0367cab_sleep, + .i2c_gate_ctrl = stv0367cab_gate_ctrl, + .set_frontend = stv0367cab_set_frontend, + .get_frontend = stv0367cab_get_frontend, + .read_status = stv0367cab_read_status, +/* .read_ber = stv0367cab_read_ber, */ + .read_signal_strength = stv0367cab_read_strength, + .read_snr = stv0367cab_read_snr, + .read_ucblocks = stv0367cab_read_ucblcks, + .get_tune_settings = stv0367_get_tune_settings, +}; + +struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, + struct i2c_adapter *i2c) +{ + struct stv0367_state *state = NULL; + struct stv0367cab_state *cab_state = NULL; + + /* allocate memory for the internal state */ + state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); + if (state == NULL) + goto error; + cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL); + if (cab_state == NULL) + goto error; + + /* setup the state */ + state->i2c = i2c; + state->config = config; + cab_state->search_range = 280000; + state->cab_state = cab_state; + state->fe.ops = stv0367cab_ops; + state->fe.demodulator_priv = state; + state->chip_id = stv0367_readreg(state, 0xf000); + + dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); + + /* check if the demod is there */ + if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) + goto error; + + stv0367_writereg(state, R367TER_I2CRPT, 0x38); + return &state->fe; + +error: + kfree(cab_state); + kfree(state); + return NULL; +} +EXPORT_SYMBOL(stv0367cab_attach); + +MODULE_PARM_DESC(debug, "Set debug"); +MODULE_PARM_DESC(i2c_debug, "Set i2c debug"); + +MODULE_AUTHOR("Igor M. Liplianin"); +MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver"); +MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,89 @@ +/* + * stv0367.h + * + * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. + * + * Copyright (C) ST Microelectronics. + * Copyright (C) 2010,2011 NetUP Inc. + * Copyright (C) 2010,2011 Igor M. Liplianin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef STV0367_H +#define STV0367_H + +#include +#include "dvb_frontend.h" + +enum stv0367_ts_mode { + STV0367_OUTPUTMODE_DEFAULT, + STV0367_SERIAL_PUNCT_CLOCK, + STV0367_SERIAL_CONT_CLOCK, + STV0367_PARALLEL_PUNCT_CLOCK, + STV0367_DVBCI_CLOCK +}; + +enum stv0367_clk_pol { + STV0367_CLOCKPOLARITY_DEFAULT, + STV0367_RISINGEDGE_CLOCK, + STV0367_FALLINGEDGE_CLOCK +}; + +struct stv0367_config { + u8 demod_address; + u32 xtal; + u32 if_khz;/*4500*/ + int if_iq_mode; + int ts_mode; + int clk_pol; +}; + +enum stv0367_ter_if_iq_mode { + FE_TER_NORMAL_IF_TUNER = 0, + FE_TER_LONGPATH_IF_TUNER = 1, + FE_TER_IQ_TUNER = 2 + +}; + + + +#if defined(CONFIG_DVB_STV0367) || (defined(CONFIG_DVB_STV0367_MODULE) \ + && defined(MODULE)) +extern struct +dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, + struct i2c_adapter *i2c); +extern struct +dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, + struct i2c_adapter *i2c); +#else +static inline struct +dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, + struct i2c_adapter *i2c) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +static inline struct +dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, + struct i2c_adapter *i2c) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_priv.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_priv.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,191 @@ +/* + * stv0367_priv.h + * + * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. + * + * Copyright (C) ST Microelectronics. + * Copyright (C) 2010,2011 NetUP Inc. + * Copyright (C) 2010,2011 Igor M. Liplianin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* Common driver error constants */ + +#ifndef STV0367_PRIV_H +#define STV0367_PRIV_H + +#ifndef TRUE + #define TRUE (1 == 1) +#endif +#ifndef FALSE + #define FALSE (!TRUE) +#endif + +#ifndef NULL +#define NULL 0 +#endif + +/* MACRO definitions */ +#define ABS(X) ((X) < 0 ? (-1 * (X)) : (X)) +#define MAX(X, Y) ((X) >= (Y) ? (X) : (Y)) +#define MIN(X, Y) ((X) <= (Y) ? (X) : (Y)) +#define INRANGE(X, Y, Z) \ + ((((X) <= (Y)) && ((Y) <= (Z))) || \ + (((Z) <= (Y)) && ((Y) <= (X))) ? 1 : 0) + +#ifndef MAKEWORD +#define MAKEWORD(X, Y) (((X) << 8) + (Y)) +#endif + +#define LSB(X) (((X) & 0xff)) +#define MSB(Y) (((Y) >> 8) & 0xff) +#define MMSB(Y)(((Y) >> 16) & 0xff) + +enum stv0367_ter_signal_type { + FE_TER_NOAGC = 0, + FE_TER_AGCOK = 5, + FE_TER_NOTPS = 6, + FE_TER_TPSOK = 7, + FE_TER_NOSYMBOL = 8, + FE_TER_BAD_CPQ = 9, + FE_TER_PRFOUNDOK = 10, + FE_TER_NOPRFOUND = 11, + FE_TER_LOCKOK = 12, + FE_TER_NOLOCK = 13, + FE_TER_SYMBOLOK = 15, + FE_TER_CPAMPOK = 16, + FE_TER_NOCPAMP = 17, + FE_TER_SWNOK = 18 +}; + +enum stv0367_ter_bw { + FE_TER_CHAN_BW_6M = 6, + FE_TER_CHAN_BW_7M = 7, + FE_TER_CHAN_BW_8M = 8 +}; + +#if 0 +enum FE_TER_Rate_TPS { + FE_TER_TPS_1_2 = 0, + FE_TER_TPS_2_3 = 1, + FE_TER_TPS_3_4 = 2, + FE_TER_TPS_5_6 = 3, + FE_TER_TPS_7_8 = 4 +}; +#endif + +enum stv0367_ter_mode { + FE_TER_MODE_2K, + FE_TER_MODE_8K, + FE_TER_MODE_4K +}; +#if 0 +enum FE_TER_Hierarchy_Alpha { + FE_TER_HIER_ALPHA_NONE, /* Regular modulation */ + FE_TER_HIER_ALPHA_1, /* Hierarchical modulation a = 1*/ + FE_TER_HIER_ALPHA_2, /* Hierarchical modulation a = 2*/ + FE_TER_HIER_ALPHA_4 /* Hierarchical modulation a = 4*/ +}; +#endif +enum stv0367_ter_hierarchy { + FE_TER_HIER_NONE, /*Hierarchy None*/ + FE_TER_HIER_LOW_PRIO, /*Hierarchy : Low Priority*/ + FE_TER_HIER_HIGH_PRIO, /*Hierarchy : High Priority*/ + FE_TER_HIER_PRIO_ANY /*Hierarchy :Any*/ +}; + +#if 0 +enum fe_stv0367_ter_spec { + FE_TER_INVERSION_NONE = 0, + FE_TER_INVERSION = 1, + FE_TER_INVERSION_AUTO = 2, + FE_TER_INVERSION_UNK = 4 +}; +#endif + +#if 0 +enum FE_TER_FECRate { + FE_TER_FEC_NONE = 0x00, /* no FEC rate specified */ + FE_TER_FEC_ALL = 0xFF, /* Logical OR of all FECs */ + FE_TER_FEC_1_2 = 1, + FE_TER_FEC_2_3 = (1 << 1), + FE_TER_FEC_3_4 = (1 << 2), + FE_TER_FEC_4_5 = (1 << 3), + FE_TER_FEC_5_6 = (1 << 4), + FE_TER_FEC_6_7 = (1 << 5), + FE_TER_FEC_7_8 = (1 << 6), + FE_TER_FEC_8_9 = (1 << 7) +}; + +enum FE_TER_Rate { + FE_TER_FE_1_2 = 0, + FE_TER_FE_2_3 = 1, + FE_TER_FE_3_4 = 2, + FE_TER_FE_5_6 = 3, + FE_TER_FE_6_7 = 4, + FE_TER_FE_7_8 = 5 +}; +#endif + +enum stv0367_ter_force { + FE_TER_FORCENONE = 0, + FE_TER_FORCE_M_G = 1 +}; + +enum stv0367cab_mod { + FE_CAB_MOD_QAM4, + FE_CAB_MOD_QAM16, + FE_CAB_MOD_QAM32, + FE_CAB_MOD_QAM64, + FE_CAB_MOD_QAM128, + FE_CAB_MOD_QAM256, + FE_CAB_MOD_QAM512, + FE_CAB_MOD_QAM1024 +}; +#if 0 +enum { + FE_CAB_FEC_A = 1, /* J83 Annex A */ + FE_CAB_FEC_B = (1 << 1),/* J83 Annex B */ + FE_CAB_FEC_C = (1 << 2) /* J83 Annex C */ +} FE_CAB_FECType_t; +#endif +struct stv0367_cab_signal_info { + int locked; + u32 frequency; /* kHz */ + u32 symbol_rate; /* Mbds */ + enum stv0367cab_mod modulation; + fe_spectral_inversion_t spect_inv; + s32 Power_dBmx10; /* Power of the RF signal (dBm x 10) */ + u32 CN_dBx10; /* Carrier to noise ratio (dB x 10) */ + u32 BER; /* Bit error rate (x 10000000) */ +}; + +enum stv0367_cab_signal_type { + FE_CAB_NOTUNER, + FE_CAB_NOAGC, + FE_CAB_NOSIGNAL, + FE_CAB_NOTIMING, + FE_CAB_TIMINGOK, + FE_CAB_NOCARRIER, + FE_CAB_CARRIEROK, + FE_CAB_NOBLIND, + FE_CAB_BLINDOK, + FE_CAB_NODEMOD, + FE_CAB_DEMODOK, + FE_CAB_DATAOK +}; + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_regs.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_regs.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_regs.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367_regs.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,3614 @@ +/* + * stv0367_regs.h + * + * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. + * + * Copyright (C) ST Microelectronics. + * Copyright (C) 2010,2011 NetUP Inc. + * Copyright (C) 2010,2011 Igor M. Liplianin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef STV0367_REGS_H +#define STV0367_REGS_H + +/* ID */ +#define R367TER_ID 0xf000 +#define F367TER_IDENTIFICATIONREG 0xf00000ff + +/* I2CRPT */ +#define R367TER_I2CRPT 0xf001 +#define F367TER_I2CT_ON 0xf0010080 +#define F367TER_ENARPT_LEVEL 0xf0010070 +#define F367TER_SCLT_DELAY 0xf0010008 +#define F367TER_SCLT_NOD 0xf0010004 +#define F367TER_STOP_ENABLE 0xf0010002 +#define F367TER_SDAT_NOD 0xf0010001 + +/* TOPCTRL */ +#define R367TER_TOPCTRL 0xf002 +#define F367TER_STDBY 0xf0020080 +#define F367TER_STDBY_FEC 0xf0020040 +#define F367TER_STDBY_CORE 0xf0020020 +#define F367TER_QAM_COFDM 0xf0020010 +#define F367TER_TS_DIS 0xf0020008 +#define F367TER_DIR_CLK_216 0xf0020004 +#define F367TER_TUNER_BB 0xf0020002 +#define F367TER_DVBT_H 0xf0020001 + +/* IOCFG0 */ +#define R367TER_IOCFG0 0xf003 +#define F367TER_OP0_SD 0xf0030080 +#define F367TER_OP0_VAL 0xf0030040 +#define F367TER_OP0_OD 0xf0030020 +#define F367TER_OP0_INV 0xf0030010 +#define F367TER_OP0_DACVALUE_HI 0xf003000f + +/* DAc0R */ +#define R367TER_DAC0R 0xf004 +#define F367TER_OP0_DACVALUE_LO 0xf00400ff + +/* IOCFG1 */ +#define R367TER_IOCFG1 0xf005 +#define F367TER_IP0 0xf0050040 +#define F367TER_OP1_OD 0xf0050020 +#define F367TER_OP1_INV 0xf0050010 +#define F367TER_OP1_DACVALUE_HI 0xf005000f + +/* DAC1R */ +#define R367TER_DAC1R 0xf006 +#define F367TER_OP1_DACVALUE_LO 0xf00600ff + +/* IOCFG2 */ +#define R367TER_IOCFG2 0xf007 +#define F367TER_OP2_LOCK_CONF 0xf00700e0 +#define F367TER_OP2_OD 0xf0070010 +#define F367TER_OP2_VAL 0xf0070008 +#define F367TER_OP1_LOCK_CONF 0xf0070007 + +/* SDFR */ +#define R367TER_SDFR 0xf008 +#define F367TER_OP0_FREQ 0xf00800f0 +#define F367TER_OP1_FREQ 0xf008000f + +/* STATUS */ +#define R367TER_STATUS 0xf009 +#define F367TER_TPS_LOCK 0xf0090080 +#define F367TER_SYR_LOCK 0xf0090040 +#define F367TER_AGC_LOCK 0xf0090020 +#define F367TER_PRF 0xf0090010 +#define F367TER_LK 0xf0090008 +#define F367TER_PR 0xf0090007 + +/* AUX_CLK */ +#define R367TER_AUX_CLK 0xf00a +#define F367TER_AUXFEC_CTL 0xf00a00c0 +#define F367TER_DIS_CKX4 0xf00a0020 +#define F367TER_CKSEL 0xf00a0018 +#define F367TER_CKDIV_PROG 0xf00a0006 +#define F367TER_AUXCLK_ENA 0xf00a0001 + +/* FREESYS1 */ +#define R367TER_FREESYS1 0xf00b +#define F367TER_FREE_SYS1 0xf00b00ff + +/* FREESYS2 */ +#define R367TER_FREESYS2 0xf00c +#define F367TER_FREE_SYS2 0xf00c00ff + +/* FREESYS3 */ +#define R367TER_FREESYS3 0xf00d +#define F367TER_FREE_SYS3 0xf00d00ff + +/* GPIO_CFG */ +#define R367TER_GPIO_CFG 0xf00e +#define F367TER_GPIO7_NOD 0xf00e0080 +#define F367TER_GPIO7_CFG 0xf00e0040 +#define F367TER_GPIO6_NOD 0xf00e0020 +#define F367TER_GPIO6_CFG 0xf00e0010 +#define F367TER_GPIO5_NOD 0xf00e0008 +#define F367TER_GPIO5_CFG 0xf00e0004 +#define F367TER_GPIO4_NOD 0xf00e0002 +#define F367TER_GPIO4_CFG 0xf00e0001 + +/* GPIO_CMD */ +#define R367TER_GPIO_CMD 0xf00f +#define F367TER_GPIO7_VAL 0xf00f0008 +#define F367TER_GPIO6_VAL 0xf00f0004 +#define F367TER_GPIO5_VAL 0xf00f0002 +#define F367TER_GPIO4_VAL 0xf00f0001 + +/* AGC2MAX */ +#define R367TER_AGC2MAX 0xf010 +#define F367TER_AGC2_MAX 0xf01000ff + +/* AGC2MIN */ +#define R367TER_AGC2MIN 0xf011 +#define F367TER_AGC2_MIN 0xf01100ff + +/* AGC1MAX */ +#define R367TER_AGC1MAX 0xf012 +#define F367TER_AGC1_MAX 0xf01200ff + +/* AGC1MIN */ +#define R367TER_AGC1MIN 0xf013 +#define F367TER_AGC1_MIN 0xf01300ff + +/* AGCR */ +#define R367TER_AGCR 0xf014 +#define F367TER_RATIO_A 0xf01400e0 +#define F367TER_RATIO_B 0xf0140018 +#define F367TER_RATIO_C 0xf0140007 + +/* AGC2TH */ +#define R367TER_AGC2TH 0xf015 +#define F367TER_AGC2_THRES 0xf01500ff + +/* AGC12c */ +#define R367TER_AGC12C 0xf016 +#define F367TER_AGC1_IV 0xf0160080 +#define F367TER_AGC1_OD 0xf0160040 +#define F367TER_AGC1_LOAD 0xf0160020 +#define F367TER_AGC2_IV 0xf0160010 +#define F367TER_AGC2_OD 0xf0160008 +#define F367TER_AGC2_LOAD 0xf0160004 +#define F367TER_AGC12_MODE 0xf0160003 + +/* AGCCTRL1 */ +#define R367TER_AGCCTRL1 0xf017 +#define F367TER_DAGC_ON 0xf0170080 +#define F367TER_INVERT_AGC12 0xf0170040 +#define F367TER_AGC1_MODE 0xf0170008 +#define F367TER_AGC2_MODE 0xf0170007 + +/* AGCCTRL2 */ +#define R367TER_AGCCTRL2 0xf018 +#define F367TER_FRZ2_CTRL 0xf0180060 +#define F367TER_FRZ1_CTRL 0xf0180018 +#define F367TER_TIME_CST 0xf0180007 + +/* AGC1VAL1 */ +#define R367TER_AGC1VAL1 0xf019 +#define F367TER_AGC1_VAL_LO 0xf01900ff + +/* AGC1VAL2 */ +#define R367TER_AGC1VAL2 0xf01a +#define F367TER_AGC1_VAL_HI 0xf01a000f + +/* AGC2VAL1 */ +#define R367TER_AGC2VAL1 0xf01b +#define F367TER_AGC2_VAL_LO 0xf01b00ff + +/* AGC2VAL2 */ +#define R367TER_AGC2VAL2 0xf01c +#define F367TER_AGC2_VAL_HI 0xf01c000f + +/* AGC2PGA */ +#define R367TER_AGC2PGA 0xf01d +#define F367TER_AGC2_PGA 0xf01d00ff + +/* OVF_RATE1 */ +#define R367TER_OVF_RATE1 0xf01e +#define F367TER_OVF_RATE_HI 0xf01e000f + +/* OVF_RATE2 */ +#define R367TER_OVF_RATE2 0xf01f +#define F367TER_OVF_RATE_LO 0xf01f00ff + +/* GAIN_SRC1 */ +#define R367TER_GAIN_SRC1 0xf020 +#define F367TER_INV_SPECTR 0xf0200080 +#define F367TER_IQ_INVERT 0xf0200040 +#define F367TER_INR_BYPASS 0xf0200020 +#define F367TER_STATUS_INV_SPECRUM 0xf0200010 +#define F367TER_GAIN_SRC_HI 0xf020000f + +/* GAIN_SRC2 */ +#define R367TER_GAIN_SRC2 0xf021 +#define F367TER_GAIN_SRC_LO 0xf02100ff + +/* INC_DEROT1 */ +#define R367TER_INC_DEROT1 0xf022 +#define F367TER_INC_DEROT_HI 0xf02200ff + +/* INC_DEROT2 */ +#define R367TER_INC_DEROT2 0xf023 +#define F367TER_INC_DEROT_LO 0xf02300ff + +/* PPM_CPAMP_DIR */ +#define R367TER_PPM_CPAMP_DIR 0xf024 +#define F367TER_PPM_CPAMP_DIRECT 0xf02400ff + +/* PPM_CPAMP_INV */ +#define R367TER_PPM_CPAMP_INV 0xf025 +#define F367TER_PPM_CPAMP_INVER 0xf02500ff + +/* FREESTFE_1 */ +#define R367TER_FREESTFE_1 0xf026 +#define F367TER_SYMBOL_NUMBER_INC 0xf02600c0 +#define F367TER_SEL_LSB 0xf0260004 +#define F367TER_AVERAGE_ON 0xf0260002 +#define F367TER_DC_ADJ 0xf0260001 + +/* FREESTFE_2 */ +#define R367TER_FREESTFE_2 0xf027 +#define F367TER_SEL_SRCOUT 0xf02700c0 +#define F367TER_SEL_SYRTHR 0xf027001f + +/* DCOFFSET */ +#define R367TER_DCOFFSET 0xf028 +#define F367TER_SELECT_I_Q 0xf0280080 +#define F367TER_DC_OFFSET 0xf028007f + +/* EN_PROCESS */ +#define R367TER_EN_PROCESS 0xf029 +#define F367TER_FREE 0xf02900f0 +#define F367TER_ENAB_MANUAL 0xf0290001 + +/* SDI_SMOOTHER */ +#define R367TER_SDI_SMOOTHER 0xf02a +#define F367TER_DIS_SMOOTH 0xf02a0080 +#define F367TER_SDI_INC_SMOOTHER 0xf02a007f + +/* FE_LOOP_OPEN */ +#define R367TER_FE_LOOP_OPEN 0xf02b +#define F367TER_TRL_LOOP_OP 0xf02b0002 +#define F367TER_CRL_LOOP_OP 0xf02b0001 + +/* FREQOFF1 */ +#define R367TER_FREQOFF1 0xf02c +#define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff + +/* FREQOFF2 */ +#define R367TER_FREQOFF2 0xf02d +#define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff + +/* FREQOFF3 */ +#define R367TER_FREQOFF3 0xf02e +#define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff + +/* TIMOFF1 */ +#define R367TER_TIMOFF1 0xf02f +#define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff + +/* TIMOFF2 */ +#define R367TER_TIMOFF2 0xf030 +#define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff + +/* EPQ */ +#define R367TER_EPQ 0xf031 +#define F367TER_EPQ1 0xf03100ff + +/* EPQAUTO */ +#define R367TER_EPQAUTO 0xf032 +#define F367TER_EPQ2 0xf03200ff + +/* SYR_UPDATE */ +#define R367TER_SYR_UPDATE 0xf033 +#define F367TER_SYR_PROTV 0xf0330080 +#define F367TER_SYR_PROTV_GAIN 0xf0330060 +#define F367TER_SYR_FILTER 0xf0330010 +#define F367TER_SYR_TRACK_THRES 0xf033000c + +/* CHPFREE */ +#define R367TER_CHPFREE 0xf034 +#define F367TER_CHP_FREE 0xf03400ff + +/* PPM_STATE_MAC */ +#define R367TER_PPM_STATE_MAC 0xf035 +#define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f + +/* INR_THRESHOLD */ +#define R367TER_INR_THRESHOLD 0xf036 +#define F367TER_INR_THRESH 0xf03600ff + +/* EPQ_TPS_ID_CELL */ +#define R367TER_EPQ_TPS_ID_CELL 0xf037 +#define F367TER_ENABLE_LGTH_TO_CF 0xf0370080 +#define F367TER_DIS_TPS_RSVD 0xf0370040 +#define F367TER_DIS_BCH 0xf0370020 +#define F367TER_DIS_ID_CEL 0xf0370010 +#define F367TER_TPS_ADJUST_SYM 0xf037000f + +/* EPQ_CFG */ +#define R367TER_EPQ_CFG 0xf038 +#define F367TER_EPQ_RANGE 0xf0380002 +#define F367TER_EPQ_SOFT 0xf0380001 + +/* EPQ_STATUS */ +#define R367TER_EPQ_STATUS 0xf039 +#define F367TER_SLOPE_INC 0xf03900fc +#define F367TER_TPS_FIELD 0xf0390003 + +/* AUTORELOCK */ +#define R367TER_AUTORELOCK 0xf03a +#define F367TER_BYPASS_BER_TEMPO 0xf03a0080 +#define F367TER_BER_TEMPO 0xf03a0070 +#define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008 +#define F367TER_COFDM_TEMPO 0xf03a0007 + +/* BER_THR_VMSB */ +#define R367TER_BER_THR_VMSB 0xf03b +#define F367TER_BER_THRESHOLD_HI 0xf03b00ff + +/* BER_THR_MSB */ +#define R367TER_BER_THR_MSB 0xf03c +#define F367TER_BER_THRESHOLD_MID 0xf03c00ff + +/* BER_THR_LSB */ +#define R367TER_BER_THR_LSB 0xf03d +#define F367TER_BER_THRESHOLD_LO 0xf03d00ff + +/* CCD */ +#define R367TER_CCD 0xf03e +#define F367TER_CCD_DETECTED 0xf03e0080 +#define F367TER_CCD_RESET 0xf03e0040 +#define F367TER_CCD_THRESHOLD 0xf03e000f + +/* SPECTR_CFG */ +#define R367TER_SPECTR_CFG 0xf03f +#define F367TER_SPECT_CFG 0xf03f0003 + +/* CONSTMU_MSB */ +#define R367TER_CONSTMU_MSB 0xf040 +#define F367TER_CONSTMU_FREEZE 0xf0400080 +#define F367TER_CONSTNU_FORCE_EN 0xf0400040 +#define F367TER_CONST_MU_MSB 0xf040003f + +/* CONSTMU_LSB */ +#define R367TER_CONSTMU_LSB 0xf041 +#define F367TER_CONST_MU_LSB 0xf04100ff + +/* CONSTMU_MAX_MSB */ +#define R367TER_CONSTMU_MAX_MSB 0xf042 +#define F367TER_CONST_MU_MAX_MSB 0xf042003f + +/* CONSTMU_MAX_LSB */ +#define R367TER_CONSTMU_MAX_LSB 0xf043 +#define F367TER_CONST_MU_MAX_LSB 0xf04300ff + +/* ALPHANOISE */ +#define R367TER_ALPHANOISE 0xf044 +#define F367TER_USE_ALLFILTER 0xf0440080 +#define F367TER_INTER_ON 0xf0440040 +#define F367TER_ALPHA_NOISE 0xf044001f + +/* MAXGP_MSB */ +#define R367TER_MAXGP_MSB 0xf045 +#define F367TER_MUFILTER_LENGTH 0xf04500f0 +#define F367TER_MAX_GP_MSB 0xf045000f + +/* MAXGP_LSB */ +#define R367TER_MAXGP_LSB 0xf046 +#define F367TER_MAX_GP_LSB 0xf04600ff + +/* ALPHAMSB */ +#define R367TER_ALPHAMSB 0xf047 +#define F367TER_CHC_DATARATE 0xf04700c0 +#define F367TER_ALPHA_MSB 0xf047003f + +/* ALPHALSB */ +#define R367TER_ALPHALSB 0xf048 +#define F367TER_ALPHA_LSB 0xf04800ff + +/* PILOT_ACCU */ +#define R367TER_PILOT_ACCU 0xf049 +#define F367TER_USE_SCAT4ADDAPT 0xf0490080 +#define F367TER_PILOT_ACC 0xf049001f + +/* PILOTMU_ACCU */ +#define R367TER_PILOTMU_ACCU 0xf04a +#define F367TER_DISCARD_BAD_SP 0xf04a0080 +#define F367TER_DISCARD_BAD_CP 0xf04a0040 +#define F367TER_PILOT_MU_ACCU 0xf04a001f + +/* FILT_CHANNEL_EST */ +#define R367TER_FILT_CHANNEL_EST 0xf04b +#define F367TER_USE_FILT_PILOT 0xf04b0080 +#define F367TER_FILT_CHANNEL 0xf04b007f + +/* ALPHA_NOPISE_FREQ */ +#define R367TER_ALPHA_NOPISE_FREQ 0xf04c +#define F367TER_NOISE_FREQ_FILT 0xf04c0040 +#define F367TER_ALPHA_NOISE_FREQ 0xf04c003f + +/* RATIO_PILOT */ +#define R367TER_RATIO_PILOT 0xf04d +#define F367TER_RATIO_MEAN_SP 0xf04d00f0 +#define F367TER_RATIO_MEAN_CP 0xf04d000f + +/* CHC_CTL */ +#define R367TER_CHC_CTL 0xf04e +#define F367TER_TRACK_EN 0xf04e0080 +#define F367TER_NOISE_NORM_EN 0xf04e0040 +#define F367TER_FORCE_CHC_RESET 0xf04e0020 +#define F367TER_SHORT_TIME 0xf04e0010 +#define F367TER_FORCE_STATE_EN 0xf04e0008 +#define F367TER_FORCE_STATE 0xf04e0007 + +/* EPQ_ADJUST */ +#define R367TER_EPQ_ADJUST 0xf04f +#define F367TER_ADJUST_SCAT_IND 0xf04f00c0 +#define F367TER_ONE_SYMBOL 0xf04f0010 +#define F367TER_EPQ_DECAY 0xf04f000e +#define F367TER_HOLD_SLOPE 0xf04f0001 + +/* EPQ_THRES */ +#define R367TER_EPQ_THRES 0xf050 +#define F367TER_EPQ_THR 0xf05000ff + +/* OMEGA_CTL */ +#define R367TER_OMEGA_CTL 0xf051 +#define F367TER_OMEGA_RST 0xf0510080 +#define F367TER_FREEZE_OMEGA 0xf0510040 +#define F367TER_OMEGA_SEL 0xf051003f + +/* GP_CTL */ +#define R367TER_GP_CTL 0xf052 +#define F367TER_CHC_STATE 0xf05200e0 +#define F367TER_FREEZE_GP 0xf0520010 +#define F367TER_GP_SEL 0xf052000f + +/* MUMSB */ +#define R367TER_MUMSB 0xf053 +#define F367TER_MU_MSB 0xf053007f + +/* MULSB */ +#define R367TER_MULSB 0xf054 +#define F367TER_MU_LSB 0xf05400ff + +/* GPMSB */ +#define R367TER_GPMSB 0xf055 +#define F367TER_CSI_THRESHOLD 0xf05500e0 +#define F367TER_GP_MSB 0xf055000f + +/* GPLSB */ +#define R367TER_GPLSB 0xf056 +#define F367TER_GP_LSB 0xf05600ff + +/* OMEGAMSB */ +#define R367TER_OMEGAMSB 0xf057 +#define F367TER_OMEGA_MSB 0xf057007f + +/* OMEGALSB */ +#define R367TER_OMEGALSB 0xf058 +#define F367TER_OMEGA_LSB 0xf05800ff + +/* SCAT_NB */ +#define R367TER_SCAT_NB 0xf059 +#define F367TER_CHC_TEST 0xf05900f8 +#define F367TER_SCAT_NUMB 0xf0590003 + +/* CHC_DUMMY */ +#define R367TER_CHC_DUMMY 0xf05a +#define F367TER_CHC_DUM 0xf05a00ff + +/* INC_CTL */ +#define R367TER_INC_CTL 0xf05b +#define F367TER_INC_BYPASS 0xf05b0080 +#define F367TER_INC_NDEPTH 0xf05b000c +#define F367TER_INC_MADEPTH 0xf05b0003 + +/* INCTHRES_COR1 */ +#define R367TER_INCTHRES_COR1 0xf05c +#define F367TER_INC_THRES_COR1 0xf05c00ff + +/* INCTHRES_COR2 */ +#define R367TER_INCTHRES_COR2 0xf05d +#define F367TER_INC_THRES_COR2 0xf05d00ff + +/* INCTHRES_DET1 */ +#define R367TER_INCTHRES_DET1 0xf05e +#define F367TER_INC_THRES_DET1 0xf05e003f + +/* INCTHRES_DET2 */ +#define R367TER_INCTHRES_DET2 0xf05f +#define F367TER_INC_THRES_DET2 0xf05f003f + +/* IIR_CELLNB */ +#define R367TER_IIR_CELLNB 0xf060 +#define F367TER_NRST_IIR 0xf0600080 +#define F367TER_IIR_CELL_NB 0xf0600007 + +/* IIRCX_COEFF1_MSB */ +#define R367TER_IIRCX_COEFF1_MSB 0xf061 +#define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff + +/* IIRCX_COEFF1_LSB */ +#define R367TER_IIRCX_COEFF1_LSB 0xf062 +#define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff + +/* IIRCX_COEFF2_MSB */ +#define R367TER_IIRCX_COEFF2_MSB 0xf063 +#define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff + +/* IIRCX_COEFF2_LSB */ +#define R367TER_IIRCX_COEFF2_LSB 0xf064 +#define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff + +/* IIRCX_COEFF3_MSB */ +#define R367TER_IIRCX_COEFF3_MSB 0xf065 +#define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff + +/* IIRCX_COEFF3_LSB */ +#define R367TER_IIRCX_COEFF3_LSB 0xf066 +#define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff + +/* IIRCX_COEFF4_MSB */ +#define R367TER_IIRCX_COEFF4_MSB 0xf067 +#define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff + +/* IIRCX_COEFF4_LSB */ +#define R367TER_IIRCX_COEFF4_LSB 0xf068 +#define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff + +/* IIRCX_COEFF5_MSB */ +#define R367TER_IIRCX_COEFF5_MSB 0xf069 +#define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff + +/* IIRCX_COEFF5_LSB */ +#define R367TER_IIRCX_COEFF5_LSB 0xf06a +#define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff + +/* FEPATH_CFG */ +#define R367TER_FEPATH_CFG 0xf06b +#define F367TER_DEMUX_SWAP 0xf06b0004 +#define F367TER_DIGAGC_SWAP 0xf06b0002 +#define F367TER_LONGPATH_IF 0xf06b0001 + +/* PMC1_FUNC */ +#define R367TER_PMC1_FUNC 0xf06c +#define F367TER_SOFT_RSTN 0xf06c0080 +#define F367TER_PMC1_AVERAGE_TIME 0xf06c0078 +#define F367TER_PMC1_WAIT_TIME 0xf06c0006 +#define F367TER_PMC1_2N_SEL 0xf06c0001 + +/* PMC1_FOR */ +#define R367TER_PMC1_FOR 0xf06d +#define F367TER_PMC1_FORCE 0xf06d0080 +#define F367TER_PMC1_FORCE_VALUE 0xf06d007c + +/* PMC2_FUNC */ +#define R367TER_PMC2_FUNC 0xf06e +#define F367TER_PMC2_SOFT_STN 0xf06e0080 +#define F367TER_PMC2_ACCU_TIME 0xf06e0070 +#define F367TER_PMC2_CMDP_MN 0xf06e0008 +#define F367TER_PMC2_SWAP 0xf06e0004 + +/* STATUS_ERR_DA */ +#define R367TER_STATUS_ERR_DA 0xf06f +#define F367TER_COM_USEGAINTRK 0xf06f0080 +#define F367TER_COM_AGCLOCK 0xf06f0040 +#define F367TER_AUT_AGCLOCK 0xf06f0020 +#define F367TER_MIN_ERR_X_LSB 0xf06f000f + +/* DIG_AGC_R */ +#define R367TER_DIG_AGC_R 0xf070 +#define F367TER_COM_SOFT_RSTN 0xf0700080 +#define F367TER_COM_AGC_ON 0xf0700040 +#define F367TER_COM_EARLY 0xf0700020 +#define F367TER_AUT_SOFT_RESETN 0xf0700010 +#define F367TER_AUT_AGC_ON 0xf0700008 +#define F367TER_AUT_EARLY 0xf0700004 +#define F367TER_AUT_ROT_EN 0xf0700002 +#define F367TER_LOCK_SOFT_RESETN 0xf0700001 + +/* COMAGC_TARMSB */ +#define R367TER_COMAGC_TARMSB 0xf071 +#define F367TER_COM_AGC_TARGET_MSB 0xf07100ff + +/* COM_AGC_TAR_ENMODE */ +#define R367TER_COM_AGC_TAR_ENMODE 0xf072 +#define F367TER_COM_AGC_TARGET_LSB 0xf07200f0 +#define F367TER_COM_ENMODE 0xf072000f + +/* COM_AGC_CFG */ +#define R367TER_COM_AGC_CFG 0xf073 +#define F367TER_COM_N 0xf07300f8 +#define F367TER_COM_STABMODE 0xf0730006 +#define F367TER_ERR_SEL 0xf0730001 + +/* COM_AGC_GAIN1 */ +#define R367TER_COM_AGC_GAIN1 0xf074 +#define F367TER_COM_GAIN1aCK 0xf07400f0 +#define F367TER_COM_GAIN1TRK 0xf074000f + +/* AUT_AGC_TARGETMSB */ +#define R367TER_AUT_AGC_TARGETMSB 0xf075 +#define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff + +/* LOCK_DET_MSB */ +#define R367TER_LOCK_DET_MSB 0xf076 +#define F367TER_LOCK_DETECT_MSB 0xf07600ff + +/* AGCTAR_LOCK_LSBS */ +#define R367TER_AGCTAR_LOCK_LSBS 0xf077 +#define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0 +#define F367TER_LOCK_DETECT_LSB 0xf077000f + +/* AUT_GAIN_EN */ +#define R367TER_AUT_GAIN_EN 0xf078 +#define F367TER_AUT_ENMODE 0xf07800f0 +#define F367TER_AUT_GAIN2 0xf078000f + +/* AUT_CFG */ +#define R367TER_AUT_CFG 0xf079 +#define F367TER_AUT_N 0xf07900f8 +#define F367TER_INT_CHOICE 0xf0790006 +#define F367TER_INT_LOAD 0xf0790001 + +/* LOCKN */ +#define R367TER_LOCKN 0xf07a +#define F367TER_LOCK_N 0xf07a00f8 +#define F367TER_SEL_IQNTAR 0xf07a0004 +#define F367TER_LOCK_DETECT_CHOICE 0xf07a0003 + +/* INT_X_3 */ +#define R367TER_INT_X_3 0xf07b +#define F367TER_INT_X3 0xf07b00ff + +/* INT_X_2 */ +#define R367TER_INT_X_2 0xf07c +#define F367TER_INT_X2 0xf07c00ff + +/* INT_X_1 */ +#define R367TER_INT_X_1 0xf07d +#define F367TER_INT_X1 0xf07d00ff + +/* INT_X_0 */ +#define R367TER_INT_X_0 0xf07e +#define F367TER_INT_X0 0xf07e00ff + +/* MIN_ERRX_MSB */ +#define R367TER_MIN_ERRX_MSB 0xf07f +#define F367TER_MIN_ERR_X_MSB 0xf07f00ff + +/* COR_CTL */ +#define R367TER_COR_CTL 0xf080 +#define F367TER_CORE_ACTIVE 0xf0800020 +#define F367TER_HOLD 0xf0800010 +#define F367TER_CORE_STATE_CTL 0xf080000f + +/* COR_STAT */ +#define R367TER_COR_STAT 0xf081 +#define F367TER_SCATT_LOCKED 0xf0810080 +#define F367TER_TPS_LOCKED 0xf0810040 +#define F367TER_SYR_LOCKED_COR 0xf0810020 +#define F367TER_AGC_LOCKED_STAT 0xf0810010 +#define F367TER_CORE_STATE_STAT 0xf081000f + +/* COR_INTEN */ +#define R367TER_COR_INTEN 0xf082 +#define F367TER_INTEN 0xf0820080 +#define F367TER_INTEN_SYR 0xf0820020 +#define F367TER_INTEN_FFT 0xf0820010 +#define F367TER_INTEN_AGC 0xf0820008 +#define F367TER_INTEN_TPS1 0xf0820004 +#define F367TER_INTEN_TPS2 0xf0820002 +#define F367TER_INTEN_TPS3 0xf0820001 + +/* COR_INTSTAT */ +#define R367TER_COR_INTSTAT 0xf083 +#define F367TER_INTSTAT_SYR 0xf0830020 +#define F367TER_INTSTAT_FFT 0xf0830010 +#define F367TER_INTSAT_AGC 0xf0830008 +#define F367TER_INTSTAT_TPS1 0xf0830004 +#define F367TER_INTSTAT_TPS2 0xf0830002 +#define F367TER_INTSTAT_TPS3 0xf0830001 + +/* COR_MODEGUARD */ +#define R367TER_COR_MODEGUARD 0xf084 +#define F367TER_FORCE 0xf0840010 +#define F367TER_MODE 0xf084000c +#define F367TER_GUARD 0xf0840003 + +/* AGC_CTL */ +#define R367TER_AGC_CTL 0xf085 +#define F367TER_AGC_TIMING_FACTOR 0xf08500e0 +#define F367TER_AGC_LAST 0xf0850010 +#define F367TER_AGC_GAIN 0xf085000c +#define F367TER_AGC_NEG 0xf0850002 +#define F367TER_AGC_SET 0xf0850001 + +/* AGC_MANUAL1 */ +#define R367TER_AGC_MANUAL1 0xf086 +#define F367TER_AGC_VAL_LO 0xf08600ff + +/* AGC_MANUAL2 */ +#define R367TER_AGC_MANUAL2 0xf087 +#define F367TER_AGC_VAL_HI 0xf087000f + +/* AGC_TARG */ +#define R367TER_AGC_TARG 0xf088 +#define F367TER_AGC_TARGET 0xf08800ff + +/* AGC_GAIN1 */ +#define R367TER_AGC_GAIN1 0xf089 +#define F367TER_AGC_GAIN_LO 0xf08900ff + +/* AGC_GAIN2 */ +#define R367TER_AGC_GAIN2 0xf08a +#define F367TER_AGC_LOCKED_GAIN2 0xf08a0010 +#define F367TER_AGC_GAIN_HI 0xf08a000f + +/* RESERVED_1 */ +#define R367TER_RESERVED_1 0xf08b +#define F367TER_RESERVED1 0xf08b00ff + +/* RESERVED_2 */ +#define R367TER_RESERVED_2 0xf08c +#define F367TER_RESERVED2 0xf08c00ff + +/* RESERVED_3 */ +#define R367TER_RESERVED_3 0xf08d +#define F367TER_RESERVED3 0xf08d00ff + +/* CAS_CTL */ +#define R367TER_CAS_CTL 0xf08e +#define F367TER_CCS_ENABLE 0xf08e0080 +#define F367TER_ACS_DISABLE 0xf08e0040 +#define F367TER_DAGC_DIS 0xf08e0020 +#define F367TER_DAGC_GAIN 0xf08e0018 +#define F367TER_CCSMU 0xf08e0007 + +/* CAS_FREQ */ +#define R367TER_CAS_FREQ 0xf08f +#define F367TER_CCS_FREQ 0xf08f00ff + +/* CAS_DAGCGAIN */ +#define R367TER_CAS_DAGCGAIN 0xf090 +#define F367TER_CAS_DAGC_GAIN 0xf09000ff + +/* SYR_CTL */ +#define R367TER_SYR_CTL 0xf091 +#define F367TER_SICTH_ENABLE 0xf0910080 +#define F367TER_LONG_ECHO 0xf0910078 +#define F367TER_AUTO_LE_EN 0xf0910004 +#define F367TER_SYR_BYPASS 0xf0910002 +#define F367TER_SYR_TR_DIS 0xf0910001 + +/* SYR_STAT */ +#define R367TER_SYR_STAT 0xf092 +#define F367TER_SYR_LOCKED_STAT 0xf0920010 +#define F367TER_SYR_MODE 0xf092000c +#define F367TER_SYR_GUARD 0xf0920003 + +/* SYR_NCO1 */ +#define R367TER_SYR_NCO1 0xf093 +#define F367TER_SYR_NCO_LO 0xf09300ff + +/* SYR_NCO2 */ +#define R367TER_SYR_NCO2 0xf094 +#define F367TER_SYR_NCO_HI 0xf094003f + +/* SYR_OFFSET1 */ +#define R367TER_SYR_OFFSET1 0xf095 +#define F367TER_SYR_OFFSET_LO 0xf09500ff + +/* SYR_OFFSET2 */ +#define R367TER_SYR_OFFSET2 0xf096 +#define F367TER_SYR_OFFSET_HI 0xf096003f + +/* FFT_CTL */ +#define R367TER_FFT_CTL 0xf097 +#define F367TER_SHIFT_FFT_TRIG 0xf0970018 +#define F367TER_FFT_TRIGGER 0xf0970004 +#define F367TER_FFT_MANUAL 0xf0970002 +#define F367TER_IFFT_MODE 0xf0970001 + +/* SCR_CTL */ +#define R367TER_SCR_CTL 0xf098 +#define F367TER_SYRADJDECAY 0xf0980070 +#define F367TER_SCR_CPEDIS 0xf0980002 +#define F367TER_SCR_DIS 0xf0980001 + +/* PPM_CTL1 */ +#define R367TER_PPM_CTL1 0xf099 +#define F367TER_PPM_MAXFREQ 0xf0990030 +#define F367TER_PPM_MAXTIM 0xf0990008 +#define F367TER_PPM_INVSEL 0xf0990004 +#define F367TER_PPM_SCATDIS 0xf0990002 +#define F367TER_PPM_BYP 0xf0990001 + +/* TRL_CTL */ +#define R367TER_TRL_CTL 0xf09a +#define F367TER_TRL_NOMRATE_LSB 0xf09a0080 +#define F367TER_TRL_GAIN_FACTOR 0xf09a0078 +#define F367TER_TRL_LOOPGAIN 0xf09a0007 + +/* TRL_NOMRATE1 */ +#define R367TER_TRL_NOMRATE1 0xf09b +#define F367TER_TRL_NOMRATE_LO 0xf09b00ff + +/* TRL_NOMRATE2 */ +#define R367TER_TRL_NOMRATE2 0xf09c +#define F367TER_TRL_NOMRATE_HI 0xf09c00ff + +/* TRL_TIME1 */ +#define R367TER_TRL_TIME1 0xf09d +#define F367TER_TRL_TOFFSET_LO 0xf09d00ff + +/* TRL_TIME2 */ +#define R367TER_TRL_TIME2 0xf09e +#define F367TER_TRL_TOFFSET_HI 0xf09e00ff + +/* CRL_CTL */ +#define R367TER_CRL_CTL 0xf09f +#define F367TER_CRL_DIS 0xf09f0080 +#define F367TER_CRL_GAIN_FACTOR 0xf09f0078 +#define F367TER_CRL_LOOPGAIN 0xf09f0007 + +/* CRL_FREQ1 */ +#define R367TER_CRL_FREQ1 0xf0a0 +#define F367TER_CRL_FOFFSET_LO 0xf0a000ff + +/* CRL_FREQ2 */ +#define R367TER_CRL_FREQ2 0xf0a1 +#define F367TER_CRL_FOFFSET_HI 0xf0a100ff + +/* CRL_FREQ3 */ +#define R367TER_CRL_FREQ3 0xf0a2 +#define F367TER_CRL_FOFFSET_VHI 0xf0a200ff + +/* TPS_SFRAME_CTL */ +#define R367TER_TPS_SFRAME_CTL 0xf0a3 +#define F367TER_TPS_SFRAME_SYNC 0xf0a30001 + +/* CHC_SNR */ +#define R367TER_CHC_SNR 0xf0a4 +#define F367TER_CHCSNR 0xf0a400ff + +/* BDI_CTL */ +#define R367TER_BDI_CTL 0xf0a5 +#define F367TER_BDI_LPSEL 0xf0a50002 +#define F367TER_BDI_SERIAL 0xf0a50001 + +/* DMP_CTL */ +#define R367TER_DMP_CTL 0xf0a6 +#define F367TER_DMP_SCALING_FACTOR 0xf0a6001e +#define F367TER_DMP_SDDIS 0xf0a60001 + +/* TPS_RCVD1 */ +#define R367TER_TPS_RCVD1 0xf0a7 +#define F367TER_TPS_CHANGE 0xf0a70040 +#define F367TER_BCH_OK 0xf0a70020 +#define F367TER_TPS_SYNC 0xf0a70010 +#define F367TER_TPS_FRAME 0xf0a70003 + +/* TPS_RCVD2 */ +#define R367TER_TPS_RCVD2 0xf0a8 +#define F367TER_TPS_HIERMODE 0xf0a80070 +#define F367TER_TPS_CONST 0xf0a80003 + +/* TPS_RCVD3 */ +#define R367TER_TPS_RCVD3 0xf0a9 +#define F367TER_TPS_LPCODE 0xf0a90070 +#define F367TER_TPS_HPCODE 0xf0a90007 + +/* TPS_RCVD4 */ +#define R367TER_TPS_RCVD4 0xf0aa +#define F367TER_TPS_GUARD 0xf0aa0030 +#define F367TER_TPS_MODE 0xf0aa0003 + +/* TPS_ID_CELL1 */ +#define R367TER_TPS_ID_CELL1 0xf0ab +#define F367TER_TPS_ID_CELL_LO 0xf0ab00ff + +/* TPS_ID_CELL2 */ +#define R367TER_TPS_ID_CELL2 0xf0ac +#define F367TER_TPS_ID_CELL_HI 0xf0ac00ff + +/* TPS_RCVD5_SET1 */ +#define R367TER_TPS_RCVD5_SET1 0xf0ad +#define F367TER_TPS_NA 0xf0ad00fC +#define F367TER_TPS_SETFRAME 0xf0ad0003 + +/* TPS_SET2 */ +#define R367TER_TPS_SET2 0xf0ae +#define F367TER_TPS_SETHIERMODE 0xf0ae0070 +#define F367TER_TPS_SETCONST 0xf0ae0003 + +/* TPS_SET3 */ +#define R367TER_TPS_SET3 0xf0af +#define F367TER_TPS_SETLPCODE 0xf0af0070 +#define F367TER_TPS_SETHPCODE 0xf0af0007 + +/* TPS_CTL */ +#define R367TER_TPS_CTL 0xf0b0 +#define F367TER_TPS_IMM 0xf0b00004 +#define F367TER_TPS_BCHDIS 0xf0b00002 +#define F367TER_TPS_UPDDIS 0xf0b00001 + +/* CTL_FFTOSNUM */ +#define R367TER_CTL_FFTOSNUM 0xf0b1 +#define F367TER_SYMBOL_NUMBER 0xf0b1007f + +/* TESTSELECT */ +#define R367TER_TESTSELECT 0xf0b2 +#define F367TER_TEST_SELECT 0xf0b2001f + +/* MSC_REV */ +#define R367TER_MSC_REV 0xf0b3 +#define F367TER_REV_NUMBER 0xf0b300ff + +/* PIR_CTL */ +#define R367TER_PIR_CTL 0xf0b4 +#define F367TER_FREEZE 0xf0b40001 + +/* SNR_CARRIER1 */ +#define R367TER_SNR_CARRIER1 0xf0b5 +#define F367TER_SNR_CARRIER_LO 0xf0b500ff + +/* SNR_CARRIER2 */ +#define R367TER_SNR_CARRIER2 0xf0b6 +#define F367TER_MEAN 0xf0b600c0 +#define F367TER_SNR_CARRIER_HI 0xf0b6001f + +/* PPM_CPAMP */ +#define R367TER_PPM_CPAMP 0xf0b7 +#define F367TER_PPM_CPC 0xf0b700ff + +/* TSM_AP0 */ +#define R367TER_TSM_AP0 0xf0b8 +#define F367TER_ADDRESS_BYTE_0 0xf0b800ff + +/* TSM_AP1 */ +#define R367TER_TSM_AP1 0xf0b9 +#define F367TER_ADDRESS_BYTE_1 0xf0b900ff + +/* TSM_AP2 */ +#define R367TER_TSM_AP2 0xf0bA +#define F367TER_DATA_BYTE_0 0xf0ba00ff + +/* TSM_AP3 */ +#define R367TER_TSM_AP3 0xf0bB +#define F367TER_DATA_BYTE_1 0xf0bb00ff + +/* TSM_AP4 */ +#define R367TER_TSM_AP4 0xf0bC +#define F367TER_DATA_BYTE_2 0xf0bc00ff + +/* TSM_AP5 */ +#define R367TER_TSM_AP5 0xf0bD +#define F367TER_DATA_BYTE_3 0xf0bd00ff + +/* TSM_AP6 */ +#define R367TER_TSM_AP6 0xf0bE +#define F367TER_TSM_AP_6 0xf0be00ff + +/* TSM_AP7 */ +#define R367TER_TSM_AP7 0xf0bF +#define F367TER_MEM_SELECT_BYTE 0xf0bf00ff + +/* TSTRES */ +#define R367TER_TSTRES 0xf0c0 +#define F367TER_FRES_DISPLAY 0xf0c00080 +#define F367TER_FRES_FIFO_AD 0xf0c00020 +#define F367TER_FRESRS 0xf0c00010 +#define F367TER_FRESACS 0xf0c00008 +#define F367TER_FRESFEC 0xf0c00004 +#define F367TER_FRES_PRIF 0xf0c00002 +#define F367TER_FRESCORE 0xf0c00001 + +/* ANACTRL */ +#define R367TER_ANACTRL 0xf0c1 +#define F367TER_BYPASS_XTAL 0xf0c10040 +#define F367TER_BYPASS_PLLXN 0xf0c1000c +#define F367TER_DIS_PAD_OSC 0xf0c10002 +#define F367TER_STDBY_PLLXN 0xf0c10001 + +/* TSTBUS */ +#define R367TER_TSTBUS 0xf0c2 +#define F367TER_TS_BYTE_CLK_INV 0xf0c20080 +#define F367TER_CFG_IP 0xf0c20070 +#define F367TER_CFG_TST 0xf0c2000f + +/* TSTRATE */ +#define R367TER_TSTRATE 0xf0c6 +#define F367TER_FORCEPHA 0xf0c60080 +#define F367TER_FNEWPHA 0xf0c60010 +#define F367TER_FROT90 0xf0c60008 +#define F367TER_FR 0xf0c60007 + +/* CONSTMODE */ +#define R367TER_CONSTMODE 0xf0cb +#define F367TER_TST_PRIF 0xf0cb00e0 +#define F367TER_CAR_TYPE 0xf0cb0018 +#define F367TER_CONST_MODE 0xf0cb0003 + +/* CONSTCARR1 */ +#define R367TER_CONSTCARR1 0xf0cc +#define F367TER_CONST_CARR_LO 0xf0cc00ff + +/* CONSTCARR2 */ +#define R367TER_CONSTCARR2 0xf0cd +#define F367TER_CONST_CARR_HI 0xf0cd001f + +/* ICONSTEL */ +#define R367TER_ICONSTEL 0xf0ce +#define F367TER_PICONSTEL 0xf0ce00ff + +/* QCONSTEL */ +#define R367TER_QCONSTEL 0xf0cf +#define F367TER_PQCONSTEL 0xf0cf00ff + +/* TSTBISTRES0 */ +#define R367TER_TSTBISTRES0 0xf0d0 +#define F367TER_BEND_PPM 0xf0d00080 +#define F367TER_BBAD_PPM 0xf0d00040 +#define F367TER_BEND_FFTW 0xf0d00020 +#define F367TER_BBAD_FFTW 0xf0d00010 +#define F367TER_BEND_FFT_BUF 0xf0d00008 +#define F367TER_BBAD_FFT_BUF 0xf0d00004 +#define F367TER_BEND_SYR 0xf0d00002 +#define F367TER_BBAD_SYR 0xf0d00001 + +/* TSTBISTRES1 */ +#define R367TER_TSTBISTRES1 0xf0d1 +#define F367TER_BEND_CHC_CP 0xf0d10080 +#define F367TER_BBAD_CHC_CP 0xf0d10040 +#define F367TER_BEND_CHCI 0xf0d10020 +#define F367TER_BBAD_CHCI 0xf0d10010 +#define F367TER_BEND_BDI 0xf0d10008 +#define F367TER_BBAD_BDI 0xf0d10004 +#define F367TER_BEND_SDI 0xf0d10002 +#define F367TER_BBAD_SDI 0xf0d10001 + +/* TSTBISTRES2 */ +#define R367TER_TSTBISTRES2 0xf0d2 +#define F367TER_BEND_CHC_INC 0xf0d20080 +#define F367TER_BBAD_CHC_INC 0xf0d20040 +#define F367TER_BEND_CHC_SPP 0xf0d20020 +#define F367TER_BBAD_CHC_SPP 0xf0d20010 +#define F367TER_BEND_CHC_CPP 0xf0d20008 +#define F367TER_BBAD_CHC_CPP 0xf0d20004 +#define F367TER_BEND_CHC_SP 0xf0d20002 +#define F367TER_BBAD_CHC_SP 0xf0d20001 + +/* TSTBISTRES3 */ +#define R367TER_TSTBISTRES3 0xf0d3 +#define F367TER_BEND_QAM 0xf0d30080 +#define F367TER_BBAD_QAM 0xf0d30040 +#define F367TER_BEND_SFEC_VIT 0xf0d30020 +#define F367TER_BBAD_SFEC_VIT 0xf0d30010 +#define F367TER_BEND_SFEC_DLINE 0xf0d30008 +#define F367TER_BBAD_SFEC_DLINE 0xf0d30004 +#define F367TER_BEND_SFEC_HW 0xf0d30002 +#define F367TER_BBAD_SFEC_HW 0xf0d30001 + +/* RF_AGC1 */ +#define R367TER_RF_AGC1 0xf0d4 +#define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff + +/* RF_AGC2 */ +#define R367TER_RF_AGC2 0xf0d5 +#define F367TER_REF_ADGP 0xf0d50080 +#define F367TER_STDBY_ADCGP 0xf0d50020 +#define F367TER_CHANNEL_SEL 0xf0d5001c +#define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003 + +/* ANADIGCTRL */ +#define R367TER_ANADIGCTRL 0xf0d7 +#define F367TER_SEL_CLKDEM 0xf0d70020 +#define F367TER_EN_BUFFER_Q 0xf0d70010 +#define F367TER_EN_BUFFER_I 0xf0d70008 +#define F367TER_ADC_RIS_EGDE 0xf0d70004 +#define F367TER_SGN_ADC 0xf0d70002 +#define F367TER_SEL_AD12_SYNC 0xf0d70001 + +/* PLLMDIV */ +#define R367TER_PLLMDIV 0xf0d8 +#define F367TER_PLL_MDIV 0xf0d800ff + +/* PLLNDIV */ +#define R367TER_PLLNDIV 0xf0d9 +#define F367TER_PLL_NDIV 0xf0d900ff + +/* PLLSETUP */ +#define R367TER_PLLSETUP 0xf0dA +#define F367TER_PLL_PDIV 0xf0da0070 +#define F367TER_PLL_KDIV 0xf0da000f + +/* DUAL_AD12 */ +#define R367TER_DUAL_AD12 0xf0dB +#define F367TER_FS20M 0xf0db0020 +#define F367TER_FS50M 0xf0db0010 +#define F367TER_INMODe0 0xf0db0008 +#define F367TER_POFFQ 0xf0db0004 +#define F367TER_POFFI 0xf0db0002 +#define F367TER_INMODE1 0xf0db0001 + +/* TSTBIST */ +#define R367TER_TSTBIST 0xf0dC +#define F367TER_TST_BYP_CLK 0xf0dc0080 +#define F367TER_TST_GCLKENA_STD 0xf0dc0040 +#define F367TER_TST_GCLKENA 0xf0dc0020 +#define F367TER_TST_MEMBIST 0xf0dc001f + +/* PAD_COMP_CTRL */ +#define R367TER_PAD_COMP_CTRL 0xf0dD +#define F367TER_COMPTQ 0xf0dd0010 +#define F367TER_COMPEN 0xf0dd0008 +#define F367TER_FREEZE2 0xf0dd0004 +#define F367TER_SLEEP_INHBT 0xf0dd0002 +#define F367TER_CHIP_SLEEP 0xf0dd0001 + +/* PAD_COMP_WR */ +#define R367TER_PAD_COMP_WR 0xf0de +#define F367TER_WR_ASRC 0xf0de007f + +/* PAD_COMP_RD */ +#define R367TER_PAD_COMP_RD 0xf0df +#define F367TER_COMPOK 0xf0df0080 +#define F367TER_RD_ASRC 0xf0df007f + +/* SYR_TARGET_FFTADJT_MSB */ +#define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100 +#define F367TER_SYR_START 0xf1000080 +#define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f + +/* SYR_TARGET_FFTADJT_LSB */ +#define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101 +#define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff + +/* SYR_TARGET_CHCADJT_MSB */ +#define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102 +#define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f + +/* SYR_TARGET_CHCADJT_LSB */ +#define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103 +#define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff + +/* SYR_FLAG */ +#define R367TER_SYR_FLAG 0xf104 +#define F367TER_TRIG_FLG1 0xf1040080 +#define F367TER_TRIG_FLG0 0xf1040040 +#define F367TER_FFT_FLG1 0xf1040008 +#define F367TER_FFT_FLG0 0xf1040004 +#define F367TER_CHC_FLG1 0xf1040002 +#define F367TER_CHC_FLG0 0xf1040001 + +/* CRL_TARGET1 */ +#define R367TER_CRL_TARGET1 0xf105 +#define F367TER_CRL_START 0xf1050080 +#define F367TER_CRL_TARGET_VHI 0xf105000f + +/* CRL_TARGET2 */ +#define R367TER_CRL_TARGET2 0xf106 +#define F367TER_CRL_TARGET_HI 0xf10600ff + +/* CRL_TARGET3 */ +#define R367TER_CRL_TARGET3 0xf107 +#define F367TER_CRL_TARGET_LO 0xf10700ff + +/* CRL_TARGET4 */ +#define R367TER_CRL_TARGET4 0xf108 +#define F367TER_CRL_TARGET_VLO 0xf10800ff + +/* CRL_FLAG */ +#define R367TER_CRL_FLAG 0xf109 +#define F367TER_CRL_FLAG1 0xf1090002 +#define F367TER_CRL_FLAG0 0xf1090001 + +/* TRL_TARGET1 */ +#define R367TER_TRL_TARGET1 0xf10a +#define F367TER_TRL_TARGET_HI 0xf10a00ff + +/* TRL_TARGET2 */ +#define R367TER_TRL_TARGET2 0xf10b +#define F367TER_TRL_TARGET_LO 0xf10b00ff + +/* TRL_CHC */ +#define R367TER_TRL_CHC 0xf10c +#define F367TER_TRL_START 0xf10c0080 +#define F367TER_CHC_START 0xf10c0040 +#define F367TER_TRL_FLAG1 0xf10c0002 +#define F367TER_TRL_FLAG0 0xf10c0001 + +/* CHC_SNR_TARG */ +#define R367TER_CHC_SNR_TARG 0xf10d +#define F367TER_CHC_SNR_TARGET 0xf10d00ff + +/* TOP_TRACK */ +#define R367TER_TOP_TRACK 0xf10e +#define F367TER_TOP_START 0xf10e0080 +#define F367TER_FIRST_FLAG 0xf10e0070 +#define F367TER_TOP_FLAG1 0xf10e0008 +#define F367TER_TOP_FLAG0 0xf10e0004 +#define F367TER_CHC_FLAG1 0xf10e0002 +#define F367TER_CHC_FLAG0 0xf10e0001 + +/* TRACKER_FREE1 */ +#define R367TER_TRACKER_FREE1 0xf10f +#define F367TER_TRACKER_FREE_1 0xf10f00ff + +/* ERROR_CRL1 */ +#define R367TER_ERROR_CRL1 0xf110 +#define F367TER_ERROR_CRL_VHI 0xf11000ff + +/* ERROR_CRL2 */ +#define R367TER_ERROR_CRL2 0xf111 +#define F367TER_ERROR_CRL_HI 0xf11100ff + +/* ERROR_CRL3 */ +#define R367TER_ERROR_CRL3 0xf112 +#define F367TER_ERROR_CRL_LOI 0xf11200ff + +/* ERROR_CRL4 */ +#define R367TER_ERROR_CRL4 0xf113 +#define F367TER_ERROR_CRL_VLO 0xf11300ff + +/* DEC_NCO1 */ +#define R367TER_DEC_NCO1 0xf114 +#define F367TER_DEC_NCO_VHI 0xf11400ff + +/* DEC_NCO2 */ +#define R367TER_DEC_NCO2 0xf115 +#define F367TER_DEC_NCO_HI 0xf11500ff + +/* DEC_NCO3 */ +#define R367TER_DEC_NCO3 0xf116 +#define F367TER_DEC_NCO_LO 0xf11600ff + +/* SNR */ +#define R367TER_SNR 0xf117 +#define F367TER_SNRATIO 0xf11700ff + +/* SYR_FFTADJ1 */ +#define R367TER_SYR_FFTADJ1 0xf118 +#define F367TER_SYR_FFTADJ_HI 0xf11800ff + +/* SYR_FFTADJ2 */ +#define R367TER_SYR_FFTADJ2 0xf119 +#define F367TER_SYR_FFTADJ_LO 0xf11900ff + +/* SYR_CHCADJ1 */ +#define R367TER_SYR_CHCADJ1 0xf11a +#define F367TER_SYR_CHCADJ_HI 0xf11a00ff + +/* SYR_CHCADJ2 */ +#define R367TER_SYR_CHCADJ2 0xf11b +#define F367TER_SYR_CHCADJ_LO 0xf11b00ff + +/* SYR_OFF */ +#define R367TER_SYR_OFF 0xf11c +#define F367TER_SYR_OFFSET 0xf11c00ff + +/* PPM_OFFSET1 */ +#define R367TER_PPM_OFFSET1 0xf11d +#define F367TER_PPM_OFFSET_HI 0xf11d00ff + +/* PPM_OFFSET2 */ +#define R367TER_PPM_OFFSET2 0xf11e +#define F367TER_PPM_OFFSET_LO 0xf11e00ff + +/* TRACKER_FREE2 */ +#define R367TER_TRACKER_FREE2 0xf11f +#define F367TER_TRACKER_FREE_2 0xf11f00ff + +/* DEBG_LT10 */ +#define R367TER_DEBG_LT10 0xf120 +#define F367TER_DEBUG_LT10 0xf12000ff + +/* DEBG_LT11 */ +#define R367TER_DEBG_LT11 0xf121 +#define F367TER_DEBUG_LT11 0xf12100ff + +/* DEBG_LT12 */ +#define R367TER_DEBG_LT12 0xf122 +#define F367TER_DEBUG_LT12 0xf12200ff + +/* DEBG_LT13 */ +#define R367TER_DEBG_LT13 0xf123 +#define F367TER_DEBUG_LT13 0xf12300ff + +/* DEBG_LT14 */ +#define R367TER_DEBG_LT14 0xf124 +#define F367TER_DEBUG_LT14 0xf12400ff + +/* DEBG_LT15 */ +#define R367TER_DEBG_LT15 0xf125 +#define F367TER_DEBUG_LT15 0xf12500ff + +/* DEBG_LT16 */ +#define R367TER_DEBG_LT16 0xf126 +#define F367TER_DEBUG_LT16 0xf12600ff + +/* DEBG_LT17 */ +#define R367TER_DEBG_LT17 0xf127 +#define F367TER_DEBUG_LT17 0xf12700ff + +/* DEBG_LT18 */ +#define R367TER_DEBG_LT18 0xf128 +#define F367TER_DEBUG_LT18 0xf12800ff + +/* DEBG_LT19 */ +#define R367TER_DEBG_LT19 0xf129 +#define F367TER_DEBUG_LT19 0xf12900ff + +/* DEBG_LT1a */ +#define R367TER_DEBG_LT1A 0xf12a +#define F367TER_DEBUG_LT1A 0xf12a00ff + +/* DEBG_LT1b */ +#define R367TER_DEBG_LT1B 0xf12b +#define F367TER_DEBUG_LT1B 0xf12b00ff + +/* DEBG_LT1c */ +#define R367TER_DEBG_LT1C 0xf12c +#define F367TER_DEBUG_LT1C 0xf12c00ff + +/* DEBG_LT1D */ +#define R367TER_DEBG_LT1D 0xf12d +#define F367TER_DEBUG_LT1D 0xf12d00ff + +/* DEBG_LT1E */ +#define R367TER_DEBG_LT1E 0xf12e +#define F367TER_DEBUG_LT1E 0xf12e00ff + +/* DEBG_LT1F */ +#define R367TER_DEBG_LT1F 0xf12f +#define F367TER_DEBUG_LT1F 0xf12f00ff + +/* RCCFGH */ +#define R367TER_RCCFGH 0xf200 +#define F367TER_TSRCFIFO_DVBCI 0xf2000080 +#define F367TER_TSRCFIFO_SERIAL 0xf2000040 +#define F367TER_TSRCFIFO_DISABLE 0xf2000020 +#define F367TER_TSFIFO_2TORC 0xf2000010 +#define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008 +#define F367TER_TSRCFIFO_ERRMODE 0xf2000006 +#define F367TER_RCCFGH_0 0xf2000001 + +/* RCCFGM */ +#define R367TER_RCCFGM 0xf201 +#define F367TER_TSRCFIFO_MANSPEED 0xf20100c0 +#define F367TER_TSRCFIFO_PERMDATA 0xf2010020 +#define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010 +#define F367TER_RCBYTE_OVERSAMPLING 0xf201000e +#define F367TER_TSRCFIFO_INVDATA 0xf2010001 + +/* RCCFGL */ +#define R367TER_RCCFGL 0xf202 +#define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0 +#define F367TER_RCCFGL_5 0xf2020020 +#define F367TER_TSRCFIFO_DUTY50 0xf2020010 +#define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008 +#define F367TER_TSRCFIFO_DISSERMUX 0xf2020004 +#define F367TER_RCCFGL_1 0xf2020002 +#define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001 + +/* RCINSDELH */ +#define R367TER_RCINSDELH 0xf203 +#define F367TER_TSRCDEL_SYNCBYTE 0xf2030080 +#define F367TER_TSRCDEL_XXHEADER 0xf2030040 +#define F367TER_TSRCDEL_BBHEADER 0xf2030020 +#define F367TER_TSRCDEL_DATAFIELD 0xf2030010 +#define F367TER_TSRCINSDEL_ISCR 0xf2030008 +#define F367TER_TSRCINSDEL_NPD 0xf2030004 +#define F367TER_TSRCINSDEL_RSPARITY 0xf2030002 +#define F367TER_TSRCINSDEL_CRC8 0xf2030001 + +/* RCINSDELM */ +#define R367TER_RCINSDELM 0xf204 +#define F367TER_TSRCINS_BBPADDING 0xf2040080 +#define F367TER_TSRCINS_BCHFEC 0xf2040040 +#define F367TER_TSRCINS_LDPCFEC 0xf2040020 +#define F367TER_TSRCINS_EMODCOD 0xf2040010 +#define F367TER_TSRCINS_TOKEN 0xf2040008 +#define F367TER_TSRCINS_XXXERR 0xf2040004 +#define F367TER_TSRCINS_MATYPE 0xf2040002 +#define F367TER_TSRCINS_UPL 0xf2040001 + +/* RCINSDELL */ +#define R367TER_RCINSDELL 0xf205 +#define F367TER_TSRCINS_DFL 0xf2050080 +#define F367TER_TSRCINS_SYNCD 0xf2050040 +#define F367TER_TSRCINS_BLOCLEN 0xf2050020 +#define F367TER_TSRCINS_SIGPCOUNT 0xf2050010 +#define F367TER_TSRCINS_FIFO 0xf2050008 +#define F367TER_TSRCINS_REALPACK 0xf2050004 +#define F367TER_TSRCINS_TSCONFIG 0xf2050002 +#define F367TER_TSRCINS_LATENCY 0xf2050001 + +/* RCSTATUS */ +#define R367TER_RCSTATUS 0xf206 +#define F367TER_TSRCFIFO_LINEOK 0xf2060080 +#define F367TER_TSRCFIFO_ERROR 0xf2060040 +#define F367TER_TSRCFIFO_DATA7 0xf2060020 +#define F367TER_RCSTATUS_4 0xf2060010 +#define F367TER_TSRCFIFO_DEMODSEL 0xf2060008 +#define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004 +#define F367TER_RCSTATUS_1 0xf2060002 +#define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001 + +/* RCSPEED */ +#define R367TER_RCSPEED 0xf207 +#define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff + +/* RCDEBUGM */ +#define R367TER_RCDEBUGM 0xf208 +#define F367TER_SD_UNSYNC 0xf2080080 +#define F367TER_ULFLOCK_DETECTM 0xf2080040 +#define F367TER_SUL_SELECTOS 0xf2080020 +#define F367TER_DILUL_NOSCRBLE 0xf2080010 +#define F367TER_NUL_SCRB 0xf2080008 +#define F367TER_UL_SCRB 0xf2080004 +#define F367TER_SCRAULBAD 0xf2080002 +#define F367TER_SCRAUL_UNSYNC 0xf2080001 + +/* RCDEBUGL */ +#define R367TER_RCDEBUGL 0xf209 +#define F367TER_RS_ERR 0xf2090080 +#define F367TER_LLFLOCK_DETECTM 0xf2090040 +#define F367TER_NOT_SUL_SELECTOS 0xf2090020 +#define F367TER_DILLL_NOSCRBLE 0xf2090010 +#define F367TER_NLL_SCRB 0xf2090008 +#define F367TER_LL_SCRB 0xf2090004 +#define F367TER_SCRALLBAD 0xf2090002 +#define F367TER_SCRALL_UNSYNC 0xf2090001 + +/* RCOBSCFG */ +#define R367TER_RCOBSCFG 0xf20a +#define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff + +/* RCOBSM */ +#define R367TER_RCOBSM 0xf20b +#define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff + +/* RCOBSL */ +#define R367TER_RCOBSL 0xf20c +#define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff + +/* RCFECSPY */ +#define R367TER_RCFECSPY 0xf210 +#define F367TER_SPYRC_ENABLE 0xf2100080 +#define F367TER_RCNO_SYNCBYTE 0xf2100040 +#define F367TER_RCSERIAL_MODE 0xf2100020 +#define F367TER_RCUNUSUAL_PACKET 0xf2100010 +#define F367TER_BERRCMETER_DATAMODE 0xf210000c +#define F367TER_BERRCMETER_LMODE 0xf2100002 +#define F367TER_BERRCMETER_RESET 0xf2100001 + +/* RCFSPYCFG */ +#define R367TER_RCFSPYCFG 0xf211 +#define F367TER_FECSPYRC_INPUT 0xf21100c0 +#define F367TER_RCRST_ON_ERROR 0xf2110020 +#define F367TER_RCONE_SHOT 0xf2110010 +#define F367TER_RCI2C_MODE 0xf211000c +#define F367TER_SPYRC_HSTERESIS 0xf2110003 + +/* RCFSPYDATA */ +#define R367TER_RCFSPYDATA 0xf212 +#define F367TER_SPYRC_STUFFING 0xf2120080 +#define F367TER_RCNOERR_PKTJITTER 0xf2120040 +#define F367TER_SPYRC_CNULLPKT 0xf2120020 +#define F367TER_SPYRC_OUTDATA_MODE 0xf212001f + +/* RCFSPYOUT */ +#define R367TER_RCFSPYOUT 0xf213 +#define F367TER_FSPYRC_DIRECT 0xf2130080 +#define F367TER_RCFSPYOUT_6 0xf2130040 +#define F367TER_SPYRC_OUTDATA_BUS 0xf2130038 +#define F367TER_RCSTUFF_MODE 0xf2130007 + +/* RCFSTATUS */ +#define R367TER_RCFSTATUS 0xf214 +#define F367TER_SPYRC_ENDSIM 0xf2140080 +#define F367TER_RCVALID_SIM 0xf2140040 +#define F367TER_RCFOUND_SIGNAL 0xf2140020 +#define F367TER_RCDSS_SYNCBYTE 0xf2140010 +#define F367TER_RCRESULT_STATE 0xf214000f + +/* RCFGOODPACK */ +#define R367TER_RCFGOODPACK 0xf215 +#define F367TER_RCGOOD_PACKET 0xf21500ff + +/* RCFPACKCNT */ +#define R367TER_RCFPACKCNT 0xf216 +#define F367TER_RCPACKET_COUNTER 0xf21600ff + +/* RCFSPYMISC */ +#define R367TER_RCFSPYMISC 0xf217 +#define F367TER_RCLABEL_COUNTER 0xf21700ff + +/* RCFBERCPT4 */ +#define R367TER_RCFBERCPT4 0xf218 +#define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff + +/* RCFBERCPT3 */ +#define R367TER_RCFBERCPT3 0xf219 +#define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff + +/* RCFBERCPT2 */ +#define R367TER_RCFBERCPT2 0xf21a +#define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff + +/* RCFBERCPT1 */ +#define R367TER_RCFBERCPT1 0xf21b +#define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff + +/* RCFBERCPT0 */ +#define R367TER_RCFBERCPT0 0xf21c +#define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff + +/* RCFBERERR2 */ +#define R367TER_RCFBERERR2 0xf21d +#define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff + +/* RCFBERERR1 */ +#define R367TER_RCFBERERR1 0xf21e +#define F367TER_FBERRCMETER_ERR 0xf21e00ff + +/* RCFBERERR0 */ +#define R367TER_RCFBERERR0 0xf21f +#define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff + +/* RCFSTATESM */ +#define R367TER_RCFSTATESM 0xf220 +#define F367TER_RCRSTATE_F 0xf2200080 +#define F367TER_RCRSTATE_E 0xf2200040 +#define F367TER_RCRSTATE_D 0xf2200020 +#define F367TER_RCRSTATE_C 0xf2200010 +#define F367TER_RCRSTATE_B 0xf2200008 +#define F367TER_RCRSTATE_A 0xf2200004 +#define F367TER_RCRSTATE_9 0xf2200002 +#define F367TER_RCRSTATE_8 0xf2200001 + +/* RCFSTATESL */ +#define R367TER_RCFSTATESL 0xf221 +#define F367TER_RCRSTATE_7 0xf2210080 +#define F367TER_RCRSTATE_6 0xf2210040 +#define F367TER_RCRSTATE_5 0xf2210020 +#define F367TER_RCRSTATE_4 0xf2210010 +#define F367TER_RCRSTATE_3 0xf2210008 +#define F367TER_RCRSTATE_2 0xf2210004 +#define F367TER_RCRSTATE_1 0xf2210002 +#define F367TER_RCRSTATE_0 0xf2210001 + +/* RCFSPYBER */ +#define R367TER_RCFSPYBER 0xf222 +#define F367TER_RCFSPYBER_7 0xf2220080 +#define F367TER_SPYRCOBS_XORREAD 0xf2220040 +#define F367TER_FSPYRCBER_OBSMODE 0xf2220020 +#define F367TER_FSPYRCBER_SYNCBYT 0xf2220010 +#define F367TER_FSPYRCBER_UNSYNC 0xf2220008 +#define F367TER_FSPYRCBER_CTIME 0xf2220007 + +/* RCFSPYDISTM */ +#define R367TER_RCFSPYDISTM 0xf223 +#define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff + +/* RCFSPYDISTL */ +#define R367TER_RCFSPYDISTL 0xf224 +#define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff + +/* RCFSPYOBS7 */ +#define R367TER_RCFSPYOBS7 0xf228 +#define F367TER_RCSPYOBS_SPYFAIL 0xf2280080 +#define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040 +#define F367TER_RCSPYOBS_ERROR 0xf2280020 +#define F367TER_RCSPYOBS_STROUT 0xf2280010 +#define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f + +/* RCFSPYOBS6 */ +#define R367TER_RCFSPYOBS6 0xf229 +#define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0 +#define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f + +/* RCFSPYOBS5 */ +#define R367TER_RCFSPYOBS5 0xf22a +#define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff + +/* RCFSPYOBS4 */ +#define R367TER_RCFSPYOBS4 0xf22b +#define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff + +/* RCFSPYOBS3 */ +#define R367TER_RCFSPYOBS3 0xf22c +#define F367TER_RCSPYOBS_DATA1 0xf22c00ff + +/* RCFSPYOBS2 */ +#define R367TER_RCFSPYOBS2 0xf22d +#define F367TER_RCSPYOBS_DATa0 0xf22d00ff + +/* RCFSPYOBS1 */ +#define R367TER_RCFSPYOBS1 0xf22e +#define F367TER_RCSPYOBS_DATAM1 0xf22e00ff + +/* RCFSPYOBS0 */ +#define R367TER_RCFSPYOBS0 0xf22f +#define F367TER_RCSPYOBS_DATAM2 0xf22f00ff + +/* TSGENERAL */ +#define R367TER_TSGENERAL 0xf230 +#define F367TER_TSGENERAL_7 0xf2300080 +#define F367TER_TSGENERAL_6 0xf2300040 +#define F367TER_TSFIFO_BCLK1aLL 0xf2300020 +#define F367TER_TSGENERAL_4 0xf2300010 +#define F367TER_MUXSTREAM_OUTMODE 0xf2300008 +#define F367TER_TSFIFO_PERMPARAL 0xf2300006 +#define F367TER_RST_REEDSOLO 0xf2300001 + +/* RC1SPEED */ +#define R367TER_RC1SPEED 0xf231 +#define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff + +/* TSGSTATUS */ +#define R367TER_TSGSTATUS 0xf232 +#define F367TER_TSGSTATUS_7 0xf2320080 +#define F367TER_TSGSTATUS_6 0xf2320040 +#define F367TER_RSMEM_FULL 0xf2320020 +#define F367TER_RS_MULTCALC 0xf2320010 +#define F367TER_RSIN_OVERTIME 0xf2320008 +#define F367TER_TSFIFO3_DEMODSEL 0xf2320004 +#define F367TER_TSFIFO2_DEMODSEL 0xf2320002 +#define F367TER_TSFIFO1_DEMODSEL 0xf2320001 + + +/* FECM */ +#define R367TER_FECM 0xf233 +#define F367TER_DSS_DVB 0xf2330080 +#define F367TER_DEMOD_BYPASS 0xf2330040 +#define F367TER_CMP_SLOWMODE 0xf2330020 +#define F367TER_DSS_SRCH 0xf2330010 +#define F367TER_FECM_3 0xf2330008 +#define F367TER_DIFF_MODEVIT 0xf2330004 +#define F367TER_SYNCVIT 0xf2330002 +#define F367TER_I2CSYM 0xf2330001 + +/* VTH12 */ +#define R367TER_VTH12 0xf234 +#define F367TER_VTH_12 0xf23400ff + +/* VTH23 */ +#define R367TER_VTH23 0xf235 +#define F367TER_VTH_23 0xf23500ff + +/* VTH34 */ +#define R367TER_VTH34 0xf236 +#define F367TER_VTH_34 0xf23600ff + +/* VTH56 */ +#define R367TER_VTH56 0xf237 +#define F367TER_VTH_56 0xf23700ff + +/* VTH67 */ +#define R367TER_VTH67 0xf238 +#define F367TER_VTH_67 0xf23800ff + +/* VTH78 */ +#define R367TER_VTH78 0xf239 +#define F367TER_VTH_78 0xf23900ff + +/* VITCURPUN */ +#define R367TER_VITCURPUN 0xf23a +#define F367TER_VIT_MAPPING 0xf23a00e0 +#define F367TER_VIT_CURPUN 0xf23a001f + +/* VERROR */ +#define R367TER_VERROR 0xf23b +#define F367TER_REGERR_VIT 0xf23b00ff + +/* PRVIT */ +#define R367TER_PRVIT 0xf23c +#define F367TER_PRVIT_7 0xf23c0080 +#define F367TER_DIS_VTHLOCK 0xf23c0040 +#define F367TER_E7_8VIT 0xf23c0020 +#define F367TER_E6_7VIT 0xf23c0010 +#define F367TER_E5_6VIT 0xf23c0008 +#define F367TER_E3_4VIT 0xf23c0004 +#define F367TER_E2_3VIT 0xf23c0002 +#define F367TER_E1_2VIT 0xf23c0001 + +/* VAVSRVIT */ +#define R367TER_VAVSRVIT 0xf23d +#define F367TER_AMVIT 0xf23d0080 +#define F367TER_FROZENVIT 0xf23d0040 +#define F367TER_SNVIT 0xf23d0030 +#define F367TER_TOVVIT 0xf23d000c +#define F367TER_HYPVIT 0xf23d0003 + +/* VSTATUSVIT */ +#define R367TER_VSTATUSVIT 0xf23e +#define F367TER_VITERBI_ON 0xf23e0080 +#define F367TER_END_LOOPVIT 0xf23e0040 +#define F367TER_VITERBI_DEPRF 0xf23e0020 +#define F367TER_PRFVIT 0xf23e0010 +#define F367TER_LOCKEDVIT 0xf23e0008 +#define F367TER_VITERBI_DELOCK 0xf23e0004 +#define F367TER_VIT_DEMODSEL 0xf23e0002 +#define F367TER_VITERBI_COMPOUT 0xf23e0001 + +/* VTHINUSE */ +#define R367TER_VTHINUSE 0xf23f +#define F367TER_VIT_INUSE 0xf23f00ff + +/* KDIV12 */ +#define R367TER_KDIV12 0xf240 +#define F367TER_KDIV12_MANUAL 0xf2400080 +#define F367TER_K_DIVIDER_12 0xf240007f + +/* KDIV23 */ +#define R367TER_KDIV23 0xf241 +#define F367TER_KDIV23_MANUAL 0xf2410080 +#define F367TER_K_DIVIDER_23 0xf241007f + +/* KDIV34 */ +#define R367TER_KDIV34 0xf242 +#define F367TER_KDIV34_MANUAL 0xf2420080 +#define F367TER_K_DIVIDER_34 0xf242007f + +/* KDIV56 */ +#define R367TER_KDIV56 0xf243 +#define F367TER_KDIV56_MANUAL 0xf2430080 +#define F367TER_K_DIVIDER_56 0xf243007f + +/* KDIV67 */ +#define R367TER_KDIV67 0xf244 +#define F367TER_KDIV67_MANUAL 0xf2440080 +#define F367TER_K_DIVIDER_67 0xf244007f + +/* KDIV78 */ +#define R367TER_KDIV78 0xf245 +#define F367TER_KDIV78_MANUAL 0xf2450080 +#define F367TER_K_DIVIDER_78 0xf245007f + +/* SIGPOWER */ +#define R367TER_SIGPOWER 0xf246 +#define F367TER_SIGPOWER_MANUAL 0xf2460080 +#define F367TER_SIG_POWER 0xf246007f + +/* DEMAPVIT */ +#define R367TER_DEMAPVIT 0xf247 +#define F367TER_DEMAPVIT_7 0xf2470080 +#define F367TER_K_DIVIDER_VIT 0xf247007f + +/* VITSCALE */ +#define R367TER_VITSCALE 0xf248 +#define F367TER_NVTH_NOSRANGE 0xf2480080 +#define F367TER_VERROR_MAXMODE 0xf2480040 +#define F367TER_KDIV_MODE 0xf2480030 +#define F367TER_NSLOWSN_LOCKED 0xf2480008 +#define F367TER_DELOCK_PRFLOSS 0xf2480004 +#define F367TER_DIS_RSFLOCK 0xf2480002 +#define F367TER_VITSCALE_0 0xf2480001 + +/* FFEC1PRG */ +#define R367TER_FFEC1PRG 0xf249 +#define F367TER_FDSS_DVB 0xf2490080 +#define F367TER_FDSS_SRCH 0xf2490040 +#define F367TER_FFECPROG_5 0xf2490020 +#define F367TER_FFECPROG_4 0xf2490010 +#define F367TER_FFECPROG_3 0xf2490008 +#define F367TER_FFECPROG_2 0xf2490004 +#define F367TER_FTS1_DISABLE 0xf2490002 +#define F367TER_FTS2_DISABLE 0xf2490001 + +/* FVITCURPUN */ +#define R367TER_FVITCURPUN 0xf24a +#define F367TER_FVIT_MAPPING 0xf24a00e0 +#define F367TER_FVIT_CURPUN 0xf24a001f + +/* FVERROR */ +#define R367TER_FVERROR 0xf24b +#define F367TER_FREGERR_VIT 0xf24b00ff + +/* FVSTATUSVIT */ +#define R367TER_FVSTATUSVIT 0xf24c +#define F367TER_FVITERBI_ON 0xf24c0080 +#define F367TER_F1END_LOOPVIT 0xf24c0040 +#define F367TER_FVITERBI_DEPRF 0xf24c0020 +#define F367TER_FPRFVIT 0xf24c0010 +#define F367TER_FLOCKEDVIT 0xf24c0008 +#define F367TER_FVITERBI_DELOCK 0xf24c0004 +#define F367TER_FVIT_DEMODSEL 0xf24c0002 +#define F367TER_FVITERBI_COMPOUT 0xf24c0001 + +/* DEBUG_LT1 */ +#define R367TER_DEBUG_LT1 0xf24d +#define F367TER_DBG_LT1 0xf24d00ff + +/* DEBUG_LT2 */ +#define R367TER_DEBUG_LT2 0xf24e +#define F367TER_DBG_LT2 0xf24e00ff + +/* DEBUG_LT3 */ +#define R367TER_DEBUG_LT3 0xf24f +#define F367TER_DBG_LT3 0xf24f00ff + +/* TSTSFMET */ +#define R367TER_TSTSFMET 0xf250 +#define F367TER_TSTSFEC_METRIQUES 0xf25000ff + +/* SELOUT */ +#define R367TER_SELOUT 0xf252 +#define F367TER_EN_SYNC 0xf2520080 +#define F367TER_EN_TBUSDEMAP 0xf2520040 +#define F367TER_SELOUT_5 0xf2520020 +#define F367TER_SELOUT_4 0xf2520010 +#define F367TER_TSTSYNCHRO_MODE 0xf2520002 + +/* TSYNC */ +#define R367TER_TSYNC 0xf253 +#define F367TER_CURPUN_INCMODE 0xf2530080 +#define F367TER_CERR_TSTMODE 0xf2530040 +#define F367TER_SHIFTSOF_MODE 0xf2530030 +#define F367TER_SLOWPHA_MODE 0xf2530008 +#define F367TER_PXX_BYPALL 0xf2530004 +#define F367TER_FROTA45_FIRST 0xf2530002 +#define F367TER_TST_BCHERROR 0xf2530001 + +/* TSTERR */ +#define R367TER_TSTERR 0xf254 +#define F367TER_TST_LONGPKT 0xf2540080 +#define F367TER_TST_ISSYION 0xf2540040 +#define F367TER_TST_NPDON 0xf2540020 +#define F367TER_TSTERR_4 0xf2540010 +#define F367TER_TRACEBACK_MODE 0xf2540008 +#define F367TER_TST_RSPARITY 0xf2540004 +#define F367TER_METRIQUE_MODE 0xf2540003 + +/* TSFSYNC */ +#define R367TER_TSFSYNC 0xf255 +#define F367TER_EN_SFECSYNC 0xf2550080 +#define F367TER_EN_SFECDEMAP 0xf2550040 +#define F367TER_SFCERR_TSTMODE 0xf2550020 +#define F367TER_SFECPXX_BYPALL 0xf2550010 +#define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f + +/* TSTSFERR */ +#define R367TER_TSTSFERR 0xf256 +#define F367TER_TSTSTERR_7 0xf2560080 +#define F367TER_TSTSTERR_6 0xf2560040 +#define F367TER_TSTSTERR_5 0xf2560020 +#define F367TER_TSTSTERR_4 0xf2560010 +#define F367TER_SFECTRACEBACK_MODE 0xf2560008 +#define F367TER_SFEC_NCONVPROG 0xf2560004 +#define F367TER_SFECMETRIQUE_MODE 0xf2560003 + +/* TSTTSSF1 */ +#define R367TER_TSTTSSF1 0xf258 +#define F367TER_TSTERSSF 0xf2580080 +#define F367TER_TSTTSSFEN 0xf2580040 +#define F367TER_SFEC_OUTMODE 0xf2580030 +#define F367TER_XLSF_NOFTHRESHOLD 0xf2580008 +#define F367TER_TSTTSSF_STACKSEL 0xf2580007 + +/* TSTTSSF2 */ +#define R367TER_TSTTSSF2 0xf259 +#define F367TER_DILSF_DBBHEADER 0xf2590080 +#define F367TER_TSTTSSF_DISBUG 0xf2590040 +#define F367TER_TSTTSSF_NOBADSTART 0xf2590020 +#define F367TER_TSTTSSF_SELECT 0xf259001f + +/* TSTTSSF3 */ +#define R367TER_TSTTSSF3 0xf25a +#define F367TER_TSTTSSF3_7 0xf25a0080 +#define F367TER_TSTTSSF3_6 0xf25a0040 +#define F367TER_TSTTSSF3_5 0xf25a0020 +#define F367TER_TSTTSSF3_4 0xf25a0010 +#define F367TER_TSTTSSF3_3 0xf25a0008 +#define F367TER_TSTTSSF3_2 0xf25a0004 +#define F367TER_TSTTSSF3_1 0xf25a0002 +#define F367TER_DISSF_CLKENABLE 0xf25a0001 + +/* TSTTS1 */ +#define R367TER_TSTTS1 0xf25c +#define F367TER_TSTERS 0xf25c0080 +#define F367TER_TSFIFO_DSSSYNCB 0xf25c0040 +#define F367TER_TSTTS_FSPYBEFRS 0xf25c0020 +#define F367TER_NFORCE_SYNCBYTE 0xf25c0010 +#define F367TER_XL_NOFTHRESHOLD 0xf25c0008 +#define F367TER_TSTTS_FRFORCEPKT 0xf25c0004 +#define F367TER_DESCR_NOTAUTO 0xf25c0002 +#define F367TER_TSTTSEN 0xf25c0001 + +/* TSTTS2 */ +#define R367TER_TSTTS2 0xf25d +#define F367TER_DIL_DBBHEADER 0xf25d0080 +#define F367TER_TSTTS_NOBADXXX 0xf25d0040 +#define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020 +#define F367TER_TSTTS_SELECT 0xf25d001f + +/* TSTTS3 */ +#define R367TER_TSTTS3 0xf25e +#define F367TER_TSTTS_NOPKTGAIN 0xf25e0080 +#define F367TER_TSTTS_NOPKTENE 0xf25e0040 +#define F367TER_TSTTS_ISOLATION 0xf25e0020 +#define F367TER_TSTTS_DISBUG 0xf25e0010 +#define F367TER_TSTTS_NOBADSTART 0xf25e0008 +#define F367TER_TSTTS_STACKSEL 0xf25e0007 + +/* TSTTS4 */ +#define R367TER_TSTTS4 0xf25f +#define F367TER_TSTTS4_7 0xf25f0080 +#define F367TER_TSTTS4_6 0xf25f0040 +#define F367TER_TSTTS4_5 0xf25f0020 +#define F367TER_TSTTS_DISDSTATE 0xf25f0010 +#define F367TER_TSTTS_FASTNOSYNC 0xf25f0008 +#define F367TER_EXT_FECSPYIN 0xf25f0004 +#define F367TER_TSTTS_NODPZERO 0xf25f0002 +#define F367TER_TSTTS_NODIV3 0xf25f0001 + +/* TSTTSRC */ +#define R367TER_TSTTSRC 0xf26c +#define F367TER_TSTTSRC_7 0xf26c0080 +#define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040 +#define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020 +#define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010 +#define F367TER_TSTTSRC_NODIV3 0xf26c0008 +#define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004 +#define F367TER_SAT25_SDDORIGINE 0xf26c0002 +#define F367TER_TSTTSRC_INACTIVE 0xf26c0001 + +/* TSTTSRS */ +#define R367TER_TSTTSRS 0xf26d +#define F367TER_TSTTSRS_7 0xf26d0080 +#define F367TER_TSTTSRS_6 0xf26d0040 +#define F367TER_TSTTSRS_5 0xf26d0020 +#define F367TER_TSTTSRS_4 0xf26d0010 +#define F367TER_TSTTSRS_3 0xf26d0008 +#define F367TER_TSTTSRS_2 0xf26d0004 +#define F367TER_TSTRS_DISRS2 0xf26d0002 +#define F367TER_TSTRS_DISRS1 0xf26d0001 + +/* TSSTATEM */ +#define R367TER_TSSTATEM 0xf270 +#define F367TER_TSDIL_ON 0xf2700080 +#define F367TER_TSSKIPRS_ON 0xf2700040 +#define F367TER_TSRS_ON 0xf2700020 +#define F367TER_TSDESCRAMB_ON 0xf2700010 +#define F367TER_TSFRAME_MODE 0xf2700008 +#define F367TER_TS_DISABLE 0xf2700004 +#define F367TER_TSACM_MODE 0xf2700002 +#define F367TER_TSOUT_NOSYNC 0xf2700001 + +/* TSSTATEL */ +#define R367TER_TSSTATEL 0xf271 +#define F367TER_TSNOSYNCBYTE 0xf2710080 +#define F367TER_TSPARITY_ON 0xf2710040 +#define F367TER_TSSYNCOUTRS_ON 0xf2710020 +#define F367TER_TSDVBS2_MODE 0xf2710010 +#define F367TER_TSISSYI_ON 0xf2710008 +#define F367TER_TSNPD_ON 0xf2710004 +#define F367TER_TSCRC8_ON 0xf2710002 +#define F367TER_TSDSS_PACKET 0xf2710001 + +/* TSCFGH */ +#define R367TER_TSCFGH 0xf272 +#define F367TER_TSFIFO_DVBCI 0xf2720080 +#define F367TER_TSFIFO_SERIAL 0xf2720040 +#define F367TER_TSFIFO_TEIUPDATE 0xf2720020 +#define F367TER_TSFIFO_DUTY50 0xf2720010 +#define F367TER_TSFIFO_HSGNLOUT 0xf2720008 +#define F367TER_TSFIFO_ERRMODE 0xf2720006 +#define F367TER_RST_HWARE 0xf2720001 + +/* TSCFGM */ +#define R367TER_TSCFGM 0xf273 +#define F367TER_TSFIFO_MANSPEED 0xf27300c0 +#define F367TER_TSFIFO_PERMDATA 0xf2730020 +#define F367TER_TSFIFO_NONEWSGNL 0xf2730010 +#define F367TER_TSFIFO_BITSPEED 0xf2730008 +#define F367TER_NPD_SPECDVBS2 0xf2730004 +#define F367TER_TSFIFO_STOPCKDIS 0xf2730002 +#define F367TER_TSFIFO_INVDATA 0xf2730001 + +/* TSCFGL */ +#define R367TER_TSCFGL 0xf274 +#define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0 +#define F367TER_BCHERROR_MODE 0xf2740030 +#define F367TER_TSFIFO_NSGNL2dATA 0xf2740008 +#define F367TER_TSFIFO_EMBINDVB 0xf2740004 +#define F367TER_TSFIFO_DPUNACT 0xf2740002 +#define F367TER_TSFIFO_NPDOFF 0xf2740001 + +/* TSSYNC */ +#define R367TER_TSSYNC 0xf275 +#define F367TER_TSFIFO_PERMUTE 0xf2750080 +#define F367TER_TSFIFO_FISCR3B 0xf2750060 +#define F367TER_TSFIFO_SYNCMODE 0xf2750018 +#define F367TER_TSFIFO_SYNCSEL 0xf2750007 + +/* TSINSDELH */ +#define R367TER_TSINSDELH 0xf276 +#define F367TER_TSDEL_SYNCBYTE 0xf2760080 +#define F367TER_TSDEL_XXHEADER 0xf2760040 +#define F367TER_TSDEL_BBHEADER 0xf2760020 +#define F367TER_TSDEL_DATAFIELD 0xf2760010 +#define F367TER_TSINSDEL_ISCR 0xf2760008 +#define F367TER_TSINSDEL_NPD 0xf2760004 +#define F367TER_TSINSDEL_RSPARITY 0xf2760002 +#define F367TER_TSINSDEL_CRC8 0xf2760001 + +/* TSINSDELM */ +#define R367TER_TSINSDELM 0xf277 +#define F367TER_TSINS_BBPADDING 0xf2770080 +#define F367TER_TSINS_BCHFEC 0xf2770040 +#define F367TER_TSINS_LDPCFEC 0xf2770020 +#define F367TER_TSINS_EMODCOD 0xf2770010 +#define F367TER_TSINS_TOKEN 0xf2770008 +#define F367TER_TSINS_XXXERR 0xf2770004 +#define F367TER_TSINS_MATYPE 0xf2770002 +#define F367TER_TSINS_UPL 0xf2770001 + +/* TSINSDELL */ +#define R367TER_TSINSDELL 0xf278 +#define F367TER_TSINS_DFL 0xf2780080 +#define F367TER_TSINS_SYNCD 0xf2780040 +#define F367TER_TSINS_BLOCLEN 0xf2780020 +#define F367TER_TSINS_SIGPCOUNT 0xf2780010 +#define F367TER_TSINS_FIFO 0xf2780008 +#define F367TER_TSINS_REALPACK 0xf2780004 +#define F367TER_TSINS_TSCONFIG 0xf2780002 +#define F367TER_TSINS_LATENCY 0xf2780001 + +/* TSDIVN */ +#define R367TER_TSDIVN 0xf279 +#define F367TER_TSFIFO_LOWSPEED 0xf2790080 +#define F367TER_BYTE_OVERSAMPLING 0xf2790070 +#define F367TER_TSMANUAL_PACKETNBR 0xf279000f + +/* TSDIVPM */ +#define R367TER_TSDIVPM 0xf27a +#define F367TER_TSMANUAL_P_HI 0xf27a00ff + +/* TSDIVPL */ +#define R367TER_TSDIVPL 0xf27b +#define F367TER_TSMANUAL_P_LO 0xf27b00ff + +/* TSDIVQM */ +#define R367TER_TSDIVQM 0xf27c +#define F367TER_TSMANUAL_Q_HI 0xf27c00ff + +/* TSDIVQL */ +#define R367TER_TSDIVQL 0xf27d +#define F367TER_TSMANUAL_Q_LO 0xf27d00ff + +/* TSDILSTKM */ +#define R367TER_TSDILSTKM 0xf27e +#define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff + +/* TSDILSTKL */ +#define R367TER_TSDILSTKL 0xf27f +#define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff + +/* TSSPEED */ +#define R367TER_TSSPEED 0xf280 +#define F367TER_TSFIFO_OUTSPEED 0xf28000ff + +/* TSSTATUS */ +#define R367TER_TSSTATUS 0xf281 +#define F367TER_TSFIFO_LINEOK 0xf2810080 +#define F367TER_TSFIFO_ERROR 0xf2810040 +#define F367TER_TSFIFO_DATA7 0xf2810020 +#define F367TER_TSFIFO_NOSYNC 0xf2810010 +#define F367TER_ISCR_INITIALIZED 0xf2810008 +#define F367TER_ISCR_UPDATED 0xf2810004 +#define F367TER_SOFFIFO_UNREGUL 0xf2810002 +#define F367TER_DIL_READY 0xf2810001 + +/* TSSTATUS2 */ +#define R367TER_TSSTATUS2 0xf282 +#define F367TER_TSFIFO_DEMODSEL 0xf2820080 +#define F367TER_TSFIFOSPEED_STORE 0xf2820040 +#define F367TER_DILXX_RESET 0xf2820020 +#define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010 +#define F367TER_TSFIFO_UNDERSPEED 0xf2820008 +#define F367TER_BITSPEED_EVENT 0xf2820004 +#define F367TER_UL_SCRAMBDETECT 0xf2820002 +#define F367TER_ULDTV67_FALSELOCK 0xf2820001 + +/* TSBITRATEM */ +#define R367TER_TSBITRATEM 0xf283 +#define F367TER_TSFIFO_BITRATE_HI 0xf28300ff + +/* TSBITRATEL */ +#define R367TER_TSBITRATEL 0xf284 +#define F367TER_TSFIFO_BITRATE_LO 0xf28400ff + +/* TSPACKLENM */ +#define R367TER_TSPACKLENM 0xf285 +#define F367TER_TSFIFO_PACKCPT 0xf28500e0 +#define F367TER_DIL_RPLEN_HI 0xf285001f + +/* TSPACKLENL */ +#define R367TER_TSPACKLENL 0xf286 +#define F367TER_DIL_RPLEN_LO 0xf28600ff + +/* TSBLOCLENM */ +#define R367TER_TSBLOCLENM 0xf287 +#define F367TER_TSFIFO_PFLEN_HI 0xf28700ff + +/* TSBLOCLENL */ +#define R367TER_TSBLOCLENL 0xf288 +#define F367TER_TSFIFO_PFLEN_LO 0xf28800ff + +/* TSDLYH */ +#define R367TER_TSDLYH 0xf289 +#define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080 +#define F367TER_SOFFIFO_SPEEDUP 0xf2890040 +#define F367TER_SOFFIFO_STOP 0xf2890020 +#define F367TER_SOFFIFO_REGULATED 0xf2890010 +#define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f + +/* TSDLYM */ +#define R367TER_TSDLYM 0xf28a +#define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff + +/* TSDLYL */ +#define R367TER_TSDLYL 0xf28b +#define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff + +/* TSNPDAV */ +#define R367TER_TSNPDAV 0xf28c +#define F367TER_TSNPD_AVERAGE 0xf28c00ff + +/* TSBUFSTATH */ +#define R367TER_TSBUFSTATH 0xf28d +#define F367TER_TSISCR_3BYTES 0xf28d0080 +#define F367TER_TSISCR_NEWDATA 0xf28d0040 +#define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f + +/* TSBUFSTATM */ +#define R367TER_TSBUFSTATM 0xf28e +#define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff + +/* TSBUFSTATL */ +#define R367TER_TSBUFSTATL 0xf28f +#define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff + +/* TSDEBUGM */ +#define R367TER_TSDEBUGM 0xf290 +#define F367TER_TSFIFO_ILLPACKET 0xf2900080 +#define F367TER_DIL_NOSYNC 0xf2900040 +#define F367TER_DIL_ISCR 0xf2900020 +#define F367TER_DILOUT_BSYNCB 0xf2900010 +#define F367TER_TSFIFO_EMPTYPKT 0xf2900008 +#define F367TER_TSFIFO_EMPTYRD 0xf2900004 +#define F367TER_SOFFIFO_STOPM 0xf2900002 +#define F367TER_SOFFIFO_SPEEDUPM 0xf2900001 + +/* TSDEBUGL */ +#define R367TER_TSDEBUGL 0xf291 +#define F367TER_TSFIFO_PACKLENFAIL 0xf2910080 +#define F367TER_TSFIFO_SYNCBFAIL 0xf2910040 +#define F367TER_TSFIFO_VITLIBRE 0xf2910020 +#define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010 +#define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008 +#define F367TER_TSFIFO_ERROR_EVNT 0xf2910004 +#define F367TER_TSFIFO_FULL 0xf2910002 +#define F367TER_TSFIFO_OVERFLOWM 0xf2910001 + +/* TSDLYSETH */ +#define R367TER_TSDLYSETH 0xf292 +#define F367TER_SOFFIFO_OFFSET 0xf29200e0 +#define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f + +/* TSDLYSETM */ +#define R367TER_TSDLYSETM 0xf293 +#define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff + +/* TSDLYSETL */ +#define R367TER_TSDLYSETL 0xf294 +#define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff + +/* TSOBSCFG */ +#define R367TER_TSOBSCFG 0xf295 +#define F367TER_TSFIFO_OBSCFG 0xf29500ff + +/* TSOBSM */ +#define R367TER_TSOBSM 0xf296 +#define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff + +/* TSOBSL */ +#define R367TER_TSOBSL 0xf297 +#define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff + +/* ERRCTRL1 */ +#define R367TER_ERRCTRL1 0xf298 +#define F367TER_ERR_SRC1 0xf29800f0 +#define F367TER_ERRCTRL1_3 0xf2980008 +#define F367TER_NUM_EVT1 0xf2980007 + +/* ERRCNT1H */ +#define R367TER_ERRCNT1H 0xf299 +#define F367TER_ERRCNT1_OLDVALUE 0xf2990080 +#define F367TER_ERR_CNT1 0xf299007f + +/* ERRCNT1M */ +#define R367TER_ERRCNT1M 0xf29a +#define F367TER_ERR_CNT1_HI 0xf29a00ff + +/* ERRCNT1L */ +#define R367TER_ERRCNT1L 0xf29b +#define F367TER_ERR_CNT1_LO 0xf29b00ff + +/* ERRCTRL2 */ +#define R367TER_ERRCTRL2 0xf29c +#define F367TER_ERR_SRC2 0xf29c00f0 +#define F367TER_ERRCTRL2_3 0xf29c0008 +#define F367TER_NUM_EVT2 0xf29c0007 + +/* ERRCNT2H */ +#define R367TER_ERRCNT2H 0xf29d +#define F367TER_ERRCNT2_OLDVALUE 0xf29d0080 +#define F367TER_ERR_CNT2_HI 0xf29d007f + +/* ERRCNT2M */ +#define R367TER_ERRCNT2M 0xf29e +#define F367TER_ERR_CNT2_MED 0xf29e00ff + +/* ERRCNT2L */ +#define R367TER_ERRCNT2L 0xf29f +#define F367TER_ERR_CNT2_LO 0xf29f00ff + +/* FECSPY */ +#define R367TER_FECSPY 0xf2a0 +#define F367TER_SPY_ENABLE 0xf2a00080 +#define F367TER_NO_SYNCBYTE 0xf2a00040 +#define F367TER_SERIAL_MODE 0xf2a00020 +#define F367TER_UNUSUAL_PACKET 0xf2a00010 +#define F367TER_BERMETER_DATAMODE 0xf2a0000c +#define F367TER_BERMETER_LMODE 0xf2a00002 +#define F367TER_BERMETER_RESET 0xf2a00001 + +/* FSPYCFG */ +#define R367TER_FSPYCFG 0xf2a1 +#define F367TER_FECSPY_INPUT 0xf2a100c0 +#define F367TER_RST_ON_ERROR 0xf2a10020 +#define F367TER_ONE_SHOT 0xf2a10010 +#define F367TER_I2C_MOD 0xf2a1000c +#define F367TER_SPY_HYSTERESIS 0xf2a10003 + +/* FSPYDATA */ +#define R367TER_FSPYDATA 0xf2a2 +#define F367TER_SPY_STUFFING 0xf2a20080 +#define F367TER_NOERROR_PKTJITTER 0xf2a20040 +#define F367TER_SPY_CNULLPKT 0xf2a20020 +#define F367TER_SPY_OUTDATA_MODE 0xf2a2001f + +/* FSPYOUT */ +#define R367TER_FSPYOUT 0xf2a3 +#define F367TER_FSPY_DIRECT 0xf2a30080 +#define F367TER_FSPYOUT_6 0xf2a30040 +#define F367TER_SPY_OUTDATA_BUS 0xf2a30038 +#define F367TER_STUFF_MODE 0xf2a30007 + +/* FSTATUS */ +#define R367TER_FSTATUS 0xf2a4 +#define F367TER_SPY_ENDSIM 0xf2a40080 +#define F367TER_VALID_SIM 0xf2a40040 +#define F367TER_FOUND_SIGNAL 0xf2a40020 +#define F367TER_DSS_SYNCBYTE 0xf2a40010 +#define F367TER_RESULT_STATE 0xf2a4000f + +/* FGOODPACK */ +#define R367TER_FGOODPACK 0xf2a5 +#define F367TER_FGOOD_PACKET 0xf2a500ff + +/* FPACKCNT */ +#define R367TER_FPACKCNT 0xf2a6 +#define F367TER_FPACKET_COUNTER 0xf2a600ff + +/* FSPYMISC */ +#define R367TER_FSPYMISC 0xf2a7 +#define F367TER_FLABEL_COUNTER 0xf2a700ff + +/* FBERCPT4 */ +#define R367TER_FBERCPT4 0xf2a8 +#define F367TER_FBERMETER_CPT5 0xf2a800ff + +/* FBERCPT3 */ +#define R367TER_FBERCPT3 0xf2a9 +#define F367TER_FBERMETER_CPT4 0xf2a900ff + +/* FBERCPT2 */ +#define R367TER_FBERCPT2 0xf2aa +#define F367TER_FBERMETER_CPT3 0xf2aa00ff + +/* FBERCPT1 */ +#define R367TER_FBERCPT1 0xf2ab +#define F367TER_FBERMETER_CPT2 0xf2ab00ff + +/* FBERCPT0 */ +#define R367TER_FBERCPT0 0xf2ac +#define F367TER_FBERMETER_CPT1 0xf2ac00ff + +/* FBERERR2 */ +#define R367TER_FBERERR2 0xf2ad +#define F367TER_FBERMETER_ERR_HI 0xf2ad00ff + +/* FBERERR1 */ +#define R367TER_FBERERR1 0xf2ae +#define F367TER_FBERMETER_ERR_MED 0xf2ae00ff + +/* FBERERR0 */ +#define R367TER_FBERERR0 0xf2af +#define F367TER_FBERMETER_ERR_LO 0xf2af00ff + +/* FSTATESM */ +#define R367TER_FSTATESM 0xf2b0 +#define F367TER_RSTATE_F 0xf2b00080 +#define F367TER_RSTATE_E 0xf2b00040 +#define F367TER_RSTATE_D 0xf2b00020 +#define F367TER_RSTATE_C 0xf2b00010 +#define F367TER_RSTATE_B 0xf2b00008 +#define F367TER_RSTATE_A 0xf2b00004 +#define F367TER_RSTATE_9 0xf2b00002 +#define F367TER_RSTATE_8 0xf2b00001 + +/* FSTATESL */ +#define R367TER_FSTATESL 0xf2b1 +#define F367TER_RSTATE_7 0xf2b10080 +#define F367TER_RSTATE_6 0xf2b10040 +#define F367TER_RSTATE_5 0xf2b10020 +#define F367TER_RSTATE_4 0xf2b10010 +#define F367TER_RSTATE_3 0xf2b10008 +#define F367TER_RSTATE_2 0xf2b10004 +#define F367TER_RSTATE_1 0xf2b10002 +#define F367TER_RSTATE_0 0xf2b10001 + +/* FSPYBER */ +#define R367TER_FSPYBER 0xf2b2 +#define F367TER_FSPYBER_7 0xf2b20080 +#define F367TER_FSPYOBS_XORREAD 0xf2b20040 +#define F367TER_FSPYBER_OBSMODE 0xf2b20020 +#define F367TER_FSPYBER_SYNCBYTE 0xf2b20010 +#define F367TER_FSPYBER_UNSYNC 0xf2b20008 +#define F367TER_FSPYBER_CTIME 0xf2b20007 + +/* FSPYDISTM */ +#define R367TER_FSPYDISTM 0xf2b3 +#define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff + +/* FSPYDISTL */ +#define R367TER_FSPYDISTL 0xf2b4 +#define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff + +/* FSPYOBS7 */ +#define R367TER_FSPYOBS7 0xf2b8 +#define F367TER_FSPYOBS_SPYFAIL 0xf2b80080 +#define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040 +#define F367TER_FSPYOBS_ERROR 0xf2b80020 +#define F367TER_FSPYOBS_STROUT 0xf2b80010 +#define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f + +/* FSPYOBS6 */ +#define R367TER_FSPYOBS6 0xf2b9 +#define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0 +#define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f + +/* FSPYOBS5 */ +#define R367TER_FSPYOBS5 0xf2ba +#define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff + +/* FSPYOBS4 */ +#define R367TER_FSPYOBS4 0xf2bb +#define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff + +/* FSPYOBS3 */ +#define R367TER_FSPYOBS3 0xf2bc +#define F367TER_FSPYOBS_DATA1 0xf2bc00ff + +/* FSPYOBS2 */ +#define R367TER_FSPYOBS2 0xf2bd +#define F367TER_FSPYOBS_DATa0 0xf2bd00ff + +/* FSPYOBS1 */ +#define R367TER_FSPYOBS1 0xf2be +#define F367TER_FSPYOBS_DATAM1 0xf2be00ff + +/* FSPYOBS0 */ +#define R367TER_FSPYOBS0 0xf2bf +#define F367TER_FSPYOBS_DATAM2 0xf2bf00ff + +/* SFDEMAP */ +#define R367TER_SFDEMAP 0xf2c0 +#define F367TER_SFDEMAP_7 0xf2c00080 +#define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f + +/* SFERROR */ +#define R367TER_SFERROR 0xf2c1 +#define F367TER_SFEC_REGERR_VIT 0xf2c100ff + +/* SFAVSR */ +#define R367TER_SFAVSR 0xf2c2 +#define F367TER_SFEC_SUMERRORS 0xf2c20080 +#define F367TER_SERROR_MAXMODE 0xf2c20040 +#define F367TER_SN_SFEC 0xf2c20030 +#define F367TER_KDIV_MODE_SFEC 0xf2c2000c +#define F367TER_SFAVSR_1 0xf2c20002 +#define F367TER_SFAVSR_0 0xf2c20001 + +/* SFECSTATUS */ +#define R367TER_SFECSTATUS 0xf2c3 +#define F367TER_SFEC_ON 0xf2c30080 +#define F367TER_SFSTATUS_6 0xf2c30040 +#define F367TER_SFSTATUS_5 0xf2c30020 +#define F367TER_SFSTATUS_4 0xf2c30010 +#define F367TER_LOCKEDSFEC 0xf2c30008 +#define F367TER_SFEC_DELOCK 0xf2c30004 +#define F367TER_SFEC_DEMODSEL1 0xf2c30002 +#define F367TER_SFEC_OVFON 0xf2c30001 + +/* SFKDIV12 */ +#define R367TER_SFKDIV12 0xf2c4 +#define F367TER_SFECKDIV12_MAN 0xf2c40080 +#define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f + +/* SFKDIV23 */ +#define R367TER_SFKDIV23 0xf2c5 +#define F367TER_SFECKDIV23_MAN 0xf2c50080 +#define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f + +/* SFKDIV34 */ +#define R367TER_SFKDIV34 0xf2c6 +#define F367TER_SFECKDIV34_MAN 0xf2c60080 +#define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f + +/* SFKDIV56 */ +#define R367TER_SFKDIV56 0xf2c7 +#define F367TER_SFECKDIV56_MAN 0xf2c70080 +#define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f + +/* SFKDIV67 */ +#define R367TER_SFKDIV67 0xf2c8 +#define F367TER_SFECKDIV67_MAN 0xf2c80080 +#define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f + +/* SFKDIV78 */ +#define R367TER_SFKDIV78 0xf2c9 +#define F367TER_SFECKDIV78_MAN 0xf2c90080 +#define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f + +/* SFDILSTKM */ +#define R367TER_SFDILSTKM 0xf2ca +#define F367TER_SFEC_PACKCPT 0xf2ca00e0 +#define F367TER_SFEC_DILSTK_HI 0xf2ca001f + +/* SFDILSTKL */ +#define R367TER_SFDILSTKL 0xf2cb +#define F367TER_SFEC_DILSTK_LO 0xf2cb00ff + +/* SFSTATUS */ +#define R367TER_SFSTATUS 0xf2cc +#define F367TER_SFEC_LINEOK 0xf2cc0080 +#define F367TER_SFEC_ERROR 0xf2cc0040 +#define F367TER_SFEC_DATA7 0xf2cc0020 +#define F367TER_SFEC_OVERFLOW 0xf2cc0010 +#define F367TER_SFEC_DEMODSEL2 0xf2cc0008 +#define F367TER_SFEC_NOSYNC 0xf2cc0004 +#define F367TER_SFEC_UNREGULA 0xf2cc0002 +#define F367TER_SFEC_READY 0xf2cc0001 + +/* SFDLYH */ +#define R367TER_SFDLYH 0xf2cd +#define F367TER_SFEC_TSTIMEVALID 0xf2cd0080 +#define F367TER_SFEC_SPEEDUP 0xf2cd0040 +#define F367TER_SFEC_STOP 0xf2cd0020 +#define F367TER_SFEC_REGULATED 0xf2cd0010 +#define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f + +/* SFDLYM */ +#define R367TER_SFDLYM 0xf2ce +#define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff + +/* SFDLYL */ +#define R367TER_SFDLYL 0xf2cf +#define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff + +/* SFDLYSETH */ +#define R367TER_SFDLYSETH 0xf2d0 +#define F367TER_SFEC_OFFSET 0xf2d000e0 +#define F367TER_SFECDLYSETH_4 0xf2d00010 +#define F367TER_RST_SFEC 0xf2d00008 +#define F367TER_SFECDLYSETH_2 0xf2d00004 +#define F367TER_SFEC_DISABLE 0xf2d00002 +#define F367TER_SFEC_UNREGUL 0xf2d00001 + +/* SFDLYSETM */ +#define R367TER_SFDLYSETM 0xf2d1 +#define F367TER_SFECDLYSETM_7 0xf2d10080 +#define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f + +/* SFDLYSETL */ +#define R367TER_SFDLYSETL 0xf2d2 +#define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff + +/* SFOBSCFG */ +#define R367TER_SFOBSCFG 0xf2d3 +#define F367TER_SFEC_OBSCFG 0xf2d300ff + +/* SFOBSM */ +#define R367TER_SFOBSM 0xf2d4 +#define F367TER_SFEC_OBSDATA_HI 0xf2d400ff + +/* SFOBSL */ +#define R367TER_SFOBSL 0xf2d5 +#define F367TER_SFEC_OBSDATA_LO 0xf2d500ff + +/* SFECINFO */ +#define R367TER_SFECINFO 0xf2d6 +#define F367TER_SFECINFO_7 0xf2d60080 +#define F367TER_SFEC_SYNCDLSB 0xf2d60070 +#define F367TER_SFCE_S1cPHASE 0xf2d6000f + +/* SFERRCTRL */ +#define R367TER_SFERRCTRL 0xf2d8 +#define F367TER_SFEC_ERR_SOURCE 0xf2d800f0 +#define F367TER_SFERRCTRL_3 0xf2d80008 +#define F367TER_SFEC_NUM_EVENT 0xf2d80007 + +/* SFERRCNTH */ +#define R367TER_SFERRCNTH 0xf2d9 +#define F367TER_SFERRC_OLDVALUE 0xf2d90080 +#define F367TER_SFEC_ERR_CNT 0xf2d9007f + +/* SFERRCNTM */ +#define R367TER_SFERRCNTM 0xf2da +#define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff + +/* SFERRCNTL */ +#define R367TER_SFERRCNTL 0xf2db +#define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff + +/* SYMBRATEM */ +#define R367TER_SYMBRATEM 0xf2e0 +#define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff + +/* SYMBRATEL */ +#define R367TER_SYMBRATEL 0xf2e1 +#define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff + +/* SYMBSTATUS */ +#define R367TER_SYMBSTATUS 0xf2e2 +#define F367TER_SYMBDLINE2_OFF 0xf2e20080 +#define F367TER_SDDL_REINIT1 0xf2e20040 +#define F367TER_SDD_REINIT1 0xf2e20020 +#define F367TER_TOKENID_ERROR 0xf2e20010 +#define F367TER_SYMBRATE_OVERFLOW 0xf2e20008 +#define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004 +#define F367TER_TOKENID_RSTEVENT 0xf2e20002 +#define F367TER_TOKENID_RESET1 0xf2e20001 + +/* SYMBCFG */ +#define R367TER_SYMBCFG 0xf2e3 +#define F367TER_SYMBCFG_7 0xf2e30080 +#define F367TER_SYMBCFG_6 0xf2e30040 +#define F367TER_SYMBCFG_5 0xf2e30020 +#define F367TER_SYMBCFG_4 0xf2e30010 +#define F367TER_SYMRATE_FSPEED 0xf2e3000c +#define F367TER_SYMRATE_SSPEED 0xf2e30003 + +/* SYMBFIFOM */ +#define R367TER_SYMBFIFOM 0xf2e4 +#define F367TER_SYMBFIFOM_7 0xf2e40080 +#define F367TER_SYMBFIFOM_6 0xf2e40040 +#define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f + +/* SYMBFIFOL */ +#define R367TER_SYMBFIFOL 0xf2e5 +#define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff + +/* SYMBOFFSM */ +#define R367TER_SYMBOFFSM 0xf2e6 +#define F367TER_TOKENID_RESET2 0xf2e60080 +#define F367TER_SDDL_REINIT2 0xf2e60040 +#define F367TER_SDD_REINIT2 0xf2e60020 +#define F367TER_SYMBOFFSM_4 0xf2e60010 +#define F367TER_SYMBOFFSM_3 0xf2e60008 +#define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007 + +/* SYMBOFFSL */ +#define R367TER_SYMBOFFSL 0xf2e7 +#define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff + +/* DEBUG_LT4 */ +#define R367TER_DEBUG_LT4 0xf400 +#define F367TER_F_DEBUG_LT4 0xf40000ff + +/* DEBUG_LT5 */ +#define R367TER_DEBUG_LT5 0xf401 +#define F367TER_F_DEBUG_LT5 0xf40100ff + +/* DEBUG_LT6 */ +#define R367TER_DEBUG_LT6 0xf402 +#define F367TER_F_DEBUG_LT6 0xf40200ff + +/* DEBUG_LT7 */ +#define R367TER_DEBUG_LT7 0xf403 +#define F367TER_F_DEBUG_LT7 0xf40300ff + +/* DEBUG_LT8 */ +#define R367TER_DEBUG_LT8 0xf404 +#define F367TER_F_DEBUG_LT8 0xf40400ff + +/* DEBUG_LT9 */ +#define R367TER_DEBUG_LT9 0xf405 +#define F367TER_F_DEBUG_LT9 0xf40500ff + +#define STV0367TER_NBREGS 445 + +/* ID */ +#define R367CAB_ID 0xf000 +#define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff + +/* I2CRPT */ +#define R367CAB_I2CRPT 0xf001 +#define F367CAB_I2CT_ON 0xf0010080 +#define F367CAB_ENARPT_LEVEL 0xf0010070 +#define F367CAB_SCLT_DELAY 0xf0010008 +#define F367CAB_SCLT_NOD 0xf0010004 +#define F367CAB_STOP_ENABLE 0xf0010002 +#define F367CAB_SDAT_NOD 0xf0010001 + +/* TOPCTRL */ +#define R367CAB_TOPCTRL 0xf002 +#define F367CAB_STDBY 0xf0020080 +#define F367CAB_STDBY_CORE 0xf0020020 +#define F367CAB_QAM_COFDM 0xf0020010 +#define F367CAB_TS_DIS 0xf0020008 +#define F367CAB_DIR_CLK_216 0xf0020004 + +/* IOCFG0 */ +#define R367CAB_IOCFG0 0xf003 +#define F367CAB_OP0_SD 0xf0030080 +#define F367CAB_OP0_VAL 0xf0030040 +#define F367CAB_OP0_OD 0xf0030020 +#define F367CAB_OP0_INV 0xf0030010 +#define F367CAB_OP0_DACVALUE_HI 0xf003000f + +/* DAc0R */ +#define R367CAB_DAC0R 0xf004 +#define F367CAB_OP0_DACVALUE_LO 0xf00400ff + +/* IOCFG1 */ +#define R367CAB_IOCFG1 0xf005 +#define F367CAB_IP0 0xf0050040 +#define F367CAB_OP1_OD 0xf0050020 +#define F367CAB_OP1_INV 0xf0050010 +#define F367CAB_OP1_DACVALUE_HI 0xf005000f + +/* DAC1R */ +#define R367CAB_DAC1R 0xf006 +#define F367CAB_OP1_DACVALUE_LO 0xf00600ff + +/* IOCFG2 */ +#define R367CAB_IOCFG2 0xf007 +#define F367CAB_OP2_LOCK_CONF 0xf00700e0 +#define F367CAB_OP2_OD 0xf0070010 +#define F367CAB_OP2_VAL 0xf0070008 +#define F367CAB_OP1_LOCK_CONF 0xf0070007 + +/* SDFR */ +#define R367CAB_SDFR 0xf008 +#define F367CAB_OP0_FREQ 0xf00800f0 +#define F367CAB_OP1_FREQ 0xf008000f + +/* AUX_CLK */ +#define R367CAB_AUX_CLK 0xf00a +#define F367CAB_AUXFEC_CTL 0xf00a00c0 +#define F367CAB_DIS_CKX4 0xf00a0020 +#define F367CAB_CKSEL 0xf00a0018 +#define F367CAB_CKDIV_PROG 0xf00a0006 +#define F367CAB_AUXCLK_ENA 0xf00a0001 + +/* FREESYS1 */ +#define R367CAB_FREESYS1 0xf00b +#define F367CAB_FREESYS_1 0xf00b00ff + +/* FREESYS2 */ +#define R367CAB_FREESYS2 0xf00c +#define F367CAB_FREESYS_2 0xf00c00ff + +/* FREESYS3 */ +#define R367CAB_FREESYS3 0xf00d +#define F367CAB_FREESYS_3 0xf00d00ff + +/* GPIO_CFG */ +#define R367CAB_GPIO_CFG 0xf00e +#define F367CAB_GPIO7_OD 0xf00e0080 +#define F367CAB_GPIO7_CFG 0xf00e0040 +#define F367CAB_GPIO6_OD 0xf00e0020 +#define F367CAB_GPIO6_CFG 0xf00e0010 +#define F367CAB_GPIO5_OD 0xf00e0008 +#define F367CAB_GPIO5_CFG 0xf00e0004 +#define F367CAB_GPIO4_OD 0xf00e0002 +#define F367CAB_GPIO4_CFG 0xf00e0001 + +/* GPIO_CMD */ +#define R367CAB_GPIO_CMD 0xf00f +#define F367CAB_GPIO7_VAL 0xf00f0008 +#define F367CAB_GPIO6_VAL 0xf00f0004 +#define F367CAB_GPIO5_VAL 0xf00f0002 +#define F367CAB_GPIO4_VAL 0xf00f0001 + +/* TSTRES */ +#define R367CAB_TSTRES 0xf0c0 +#define F367CAB_FRES_DISPLAY 0xf0c00080 +#define F367CAB_FRES_FIFO_AD 0xf0c00020 +#define F367CAB_FRESRS 0xf0c00010 +#define F367CAB_FRESACS 0xf0c00008 +#define F367CAB_FRESFEC 0xf0c00004 +#define F367CAB_FRES_PRIF 0xf0c00002 +#define F367CAB_FRESCORE 0xf0c00001 + +/* ANACTRL */ +#define R367CAB_ANACTRL 0xf0c1 +#define F367CAB_BYPASS_XTAL 0xf0c10040 +#define F367CAB_BYPASS_PLLXN 0xf0c1000c +#define F367CAB_DIS_PAD_OSC 0xf0c10002 +#define F367CAB_STDBY_PLLXN 0xf0c10001 + +/* TSTBUS */ +#define R367CAB_TSTBUS 0xf0c2 +#define F367CAB_TS_BYTE_CLK_INV 0xf0c20080 +#define F367CAB_CFG_IP 0xf0c20070 +#define F367CAB_CFG_TST 0xf0c2000f + +/* RF_AGC1 */ +#define R367CAB_RF_AGC1 0xf0d4 +#define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff + +/* RF_AGC2 */ +#define R367CAB_RF_AGC2 0xf0d5 +#define F367CAB_REF_ADGP 0xf0d50080 +#define F367CAB_STDBY_ADCGP 0xf0d50020 +#define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003 + +/* ANADIGCTRL */ +#define R367CAB_ANADIGCTRL 0xf0d7 +#define F367CAB_SEL_CLKDEM 0xf0d70020 +#define F367CAB_EN_BUFFER_Q 0xf0d70010 +#define F367CAB_EN_BUFFER_I 0xf0d70008 +#define F367CAB_ADC_RIS_EGDE 0xf0d70004 +#define F367CAB_SGN_ADC 0xf0d70002 +#define F367CAB_SEL_AD12_SYNC 0xf0d70001 + +/* PLLMDIV */ +#define R367CAB_PLLMDIV 0xf0d8 +#define F367CAB_PLL_MDIV 0xf0d800ff + +/* PLLNDIV */ +#define R367CAB_PLLNDIV 0xf0d9 +#define F367CAB_PLL_NDIV 0xf0d900ff + +/* PLLSETUP */ +#define R367CAB_PLLSETUP 0xf0da +#define F367CAB_PLL_PDIV 0xf0da0070 +#define F367CAB_PLL_KDIV 0xf0da000f + +/* DUAL_AD12 */ +#define R367CAB_DUAL_AD12 0xf0db +#define F367CAB_FS20M 0xf0db0020 +#define F367CAB_FS50M 0xf0db0010 +#define F367CAB_INMODe0 0xf0db0008 +#define F367CAB_POFFQ 0xf0db0004 +#define F367CAB_POFFI 0xf0db0002 +#define F367CAB_INMODE1 0xf0db0001 + +/* TSTBIST */ +#define R367CAB_TSTBIST 0xf0dc +#define F367CAB_TST_BYP_CLK 0xf0dc0080 +#define F367CAB_TST_GCLKENA_STD 0xf0dc0040 +#define F367CAB_TST_GCLKENA 0xf0dc0020 +#define F367CAB_TST_MEMBIST 0xf0dc001f + +/* CTRL_1 */ +#define R367CAB_CTRL_1 0xf402 +#define F367CAB_SOFT_RST 0xf4020080 +#define F367CAB_EQU_RST 0xf4020008 +#define F367CAB_CRL_RST 0xf4020004 +#define F367CAB_TRL_RST 0xf4020002 +#define F367CAB_AGC_RST 0xf4020001 + +/* CTRL_2 */ +#define R367CAB_CTRL_2 0xf403 +#define F367CAB_DEINT_RST 0xf4030008 +#define F367CAB_RS_RST 0xf4030004 + +/* IT_STATUS1 */ +#define R367CAB_IT_STATUS1 0xf408 +#define F367CAB_SWEEP_OUT 0xf4080080 +#define F367CAB_FSM_CRL 0xf4080040 +#define F367CAB_CRL_LOCK 0xf4080020 +#define F367CAB_MFSM 0xf4080010 +#define F367CAB_TRL_LOCK 0xf4080008 +#define F367CAB_TRL_AGC_LIMIT 0xf4080004 +#define F367CAB_ADJ_AGC_LOCK 0xf4080002 +#define F367CAB_AGC_QAM_LOCK 0xf4080001 + +/* IT_STATUS2 */ +#define R367CAB_IT_STATUS2 0xf409 +#define F367CAB_TSMF_CNT 0xf4090080 +#define F367CAB_TSMF_EOF 0xf4090040 +#define F367CAB_TSMF_RDY 0xf4090020 +#define F367CAB_FEC_NOCORR 0xf4090010 +#define F367CAB_SYNCSTATE 0xf4090008 +#define F367CAB_DEINT_LOCK 0xf4090004 +#define F367CAB_FADDING_FRZ 0xf4090002 +#define F367CAB_TAPMON_ALARM 0xf4090001 + +/* IT_EN1 */ +#define R367CAB_IT_EN1 0xf40a +#define F367CAB_SWEEP_OUTE 0xf40a0080 +#define F367CAB_FSM_CRLE 0xf40a0040 +#define F367CAB_CRL_LOCKE 0xf40a0020 +#define F367CAB_MFSME 0xf40a0010 +#define F367CAB_TRL_LOCKE 0xf40a0008 +#define F367CAB_TRL_AGC_LIMITE 0xf40a0004 +#define F367CAB_ADJ_AGC_LOCKE 0xf40a0002 +#define F367CAB_AGC_LOCKE 0xf40a0001 + +/* IT_EN2 */ +#define R367CAB_IT_EN2 0xf40b +#define F367CAB_TSMF_CNTE 0xf40b0080 +#define F367CAB_TSMF_EOFE 0xf40b0040 +#define F367CAB_TSMF_RDYE 0xf40b0020 +#define F367CAB_FEC_NOCORRE 0xf40b0010 +#define F367CAB_SYNCSTATEE 0xf40b0008 +#define F367CAB_DEINT_LOCKE 0xf40b0004 +#define F367CAB_FADDING_FRZE 0xf40b0002 +#define F367CAB_TAPMON_ALARME 0xf40b0001 + +/* CTRL_STATUS */ +#define R367CAB_CTRL_STATUS 0xf40c +#define F367CAB_QAMFEC_LOCK 0xf40c0004 +#define F367CAB_TSMF_LOCK 0xf40c0002 +#define F367CAB_TSMF_ERROR 0xf40c0001 + +/* TEST_CTL */ +#define R367CAB_TEST_CTL 0xf40f +#define F367CAB_TST_BLK_SEL 0xf40f0060 +#define F367CAB_TST_BUS_SEL 0xf40f001f + +/* AGC_CTL */ +#define R367CAB_AGC_CTL 0xf410 +#define F367CAB_AGC_LCK_TH 0xf41000f0 +#define F367CAB_AGC_ACCUMRSTSEL 0xf4100007 + +/* AGC_IF_CFG */ +#define R367CAB_AGC_IF_CFG 0xf411 +#define F367CAB_AGC_IF_BWSEL 0xf41100f0 +#define F367CAB_AGC_IF_FREEZE 0xf4110002 + +/* AGC_RF_CFG */ +#define R367CAB_AGC_RF_CFG 0xf412 +#define F367CAB_AGC_RF_BWSEL 0xf4120070 +#define F367CAB_AGC_RF_FREEZE 0xf4120002 + +/* AGC_PWM_CFG */ +#define R367CAB_AGC_PWM_CFG 0xf413 +#define F367CAB_AGC_RF_PWM_TST 0xf4130080 +#define F367CAB_AGC_RF_PWM_INV 0xf4130040 +#define F367CAB_AGC_IF_PWM_TST 0xf4130008 +#define F367CAB_AGC_IF_PWM_INV 0xf4130004 +#define F367CAB_AGC_PWM_CLKDIV 0xf4130003 + +/* AGC_PWR_REF_L */ +#define R367CAB_AGC_PWR_REF_L 0xf414 +#define F367CAB_AGC_PWRREF_LO 0xf41400ff + +/* AGC_PWR_REF_H */ +#define R367CAB_AGC_PWR_REF_H 0xf415 +#define F367CAB_AGC_PWRREF_HI 0xf4150003 + +/* AGC_RF_TH_L */ +#define R367CAB_AGC_RF_TH_L 0xf416 +#define F367CAB_AGC_RF_TH_LO 0xf41600ff + +/* AGC_RF_TH_H */ +#define R367CAB_AGC_RF_TH_H 0xf417 +#define F367CAB_AGC_RF_TH_HI 0xf417000f + +/* AGC_IF_LTH_L */ +#define R367CAB_AGC_IF_LTH_L 0xf418 +#define F367CAB_AGC_IF_THLO_LO 0xf41800ff + +/* AGC_IF_LTH_H */ +#define R367CAB_AGC_IF_LTH_H 0xf419 +#define F367CAB_AGC_IF_THLO_HI 0xf419000f + +/* AGC_IF_HTH_L */ +#define R367CAB_AGC_IF_HTH_L 0xf41a +#define F367CAB_AGC_IF_THHI_LO 0xf41a00ff + +/* AGC_IF_HTH_H */ +#define R367CAB_AGC_IF_HTH_H 0xf41b +#define F367CAB_AGC_IF_THHI_HI 0xf41b000f + +/* AGC_PWR_RD_L */ +#define R367CAB_AGC_PWR_RD_L 0xf41c +#define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff + +/* AGC_PWR_RD_M */ +#define R367CAB_AGC_PWR_RD_M 0xf41d +#define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff + +/* AGC_PWR_RD_H */ +#define R367CAB_AGC_PWR_RD_H 0xf41e +#define F367CAB_AGC_PWR_WORD_HI 0xf41e0003 + +/* AGC_PWM_IFCMD_L */ +#define R367CAB_AGC_PWM_IFCMD_L 0xf420 +#define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff + +/* AGC_PWM_IFCMD_H */ +#define R367CAB_AGC_PWM_IFCMD_H 0xf421 +#define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f + +/* AGC_PWM_RFCMD_L */ +#define R367CAB_AGC_PWM_RFCMD_L 0xf422 +#define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff + +/* AGC_PWM_RFCMD_H */ +#define R367CAB_AGC_PWM_RFCMD_H 0xf423 +#define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f + +/* IQDEM_CFG */ +#define R367CAB_IQDEM_CFG 0xf424 +#define F367CAB_IQDEM_CLK_SEL 0xf4240004 +#define F367CAB_IQDEM_INVIQ 0xf4240002 +#define F367CAB_IQDEM_A2dTYPE 0xf4240001 + +/* MIX_NCO_LL */ +#define R367CAB_MIX_NCO_LL 0xf425 +#define F367CAB_MIX_NCO_INC_LL 0xf42500ff + +/* MIX_NCO_HL */ +#define R367CAB_MIX_NCO_HL 0xf426 +#define F367CAB_MIX_NCO_INC_HL 0xf42600ff + +/* MIX_NCO_HH */ +#define R367CAB_MIX_NCO_HH 0xf427 +#define F367CAB_MIX_NCO_INVCNST 0xf4270080 +#define F367CAB_MIX_NCO_INC_HH 0xf427007f + +/* SRC_NCO_LL */ +#define R367CAB_SRC_NCO_LL 0xf428 +#define F367CAB_SRC_NCO_INC_LL 0xf42800ff + +/* SRC_NCO_LH */ +#define R367CAB_SRC_NCO_LH 0xf429 +#define F367CAB_SRC_NCO_INC_LH 0xf42900ff + +/* SRC_NCO_HL */ +#define R367CAB_SRC_NCO_HL 0xf42a +#define F367CAB_SRC_NCO_INC_HL 0xf42a00ff + +/* SRC_NCO_HH */ +#define R367CAB_SRC_NCO_HH 0xf42b +#define F367CAB_SRC_NCO_INC_HH 0xf42b007f + +/* IQDEM_GAIN_SRC_L */ +#define R367CAB_IQDEM_GAIN_SRC_L 0xf42c +#define F367CAB_GAIN_SRC_LO 0xf42c00ff + +/* IQDEM_GAIN_SRC_H */ +#define R367CAB_IQDEM_GAIN_SRC_H 0xf42d +#define F367CAB_GAIN_SRC_HI 0xf42d0003 + +/* IQDEM_DCRM_CFG_LL */ +#define R367CAB_IQDEM_DCRM_CFG_LL 0xf430 +#define F367CAB_DCRM0_DCIN_L 0xf43000ff + +/* IQDEM_DCRM_CFG_LH */ +#define R367CAB_IQDEM_DCRM_CFG_LH 0xf431 +#define F367CAB_DCRM1_I_DCIN_L 0xf43100fc +#define F367CAB_DCRM0_DCIN_H 0xf4310003 + +/* IQDEM_DCRM_CFG_HL */ +#define R367CAB_IQDEM_DCRM_CFG_HL 0xf432 +#define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0 +#define F367CAB_DCRM1_I_DCIN_H 0xf432000f + +/* IQDEM_DCRM_CFG_HH */ +#define R367CAB_IQDEM_DCRM_CFG_HH 0xf433 +#define F367CAB_DCRM1_FRZ 0xf4330080 +#define F367CAB_DCRM0_FRZ 0xf4330040 +#define F367CAB_DCRM1_Q_DCIN_H 0xf433003f + +/* IQDEM_ADJ_COEFf0 */ +#define R367CAB_IQDEM_ADJ_COEFF0 0xf434 +#define F367CAB_ADJIIR_COEFF10_L 0xf43400ff + +/* IQDEM_ADJ_COEFF1 */ +#define R367CAB_IQDEM_ADJ_COEFF1 0xf435 +#define F367CAB_ADJIIR_COEFF11_L 0xf43500fc +#define F367CAB_ADJIIR_COEFF10_H 0xf4350003 + +/* IQDEM_ADJ_COEFF2 */ +#define R367CAB_IQDEM_ADJ_COEFF2 0xf436 +#define F367CAB_ADJIIR_COEFF12_L 0xf43600f0 +#define F367CAB_ADJIIR_COEFF11_H 0xf436000f + +/* IQDEM_ADJ_COEFF3 */ +#define R367CAB_IQDEM_ADJ_COEFF3 0xf437 +#define F367CAB_ADJIIR_COEFF20_L 0xf43700c0 +#define F367CAB_ADJIIR_COEFF12_H 0xf437003f + +/* IQDEM_ADJ_COEFF4 */ +#define R367CAB_IQDEM_ADJ_COEFF4 0xf438 +#define F367CAB_ADJIIR_COEFF20_H 0xf43800ff + +/* IQDEM_ADJ_COEFF5 */ +#define R367CAB_IQDEM_ADJ_COEFF5 0xf439 +#define F367CAB_ADJIIR_COEFF21_L 0xf43900ff + +/* IQDEM_ADJ_COEFF6 */ +#define R367CAB_IQDEM_ADJ_COEFF6 0xf43a +#define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc +#define F367CAB_ADJIIR_COEFF21_H 0xf43a0003 + +/* IQDEM_ADJ_COEFF7 */ +#define R367CAB_IQDEM_ADJ_COEFF7 0xf43b +#define F367CAB_ADJIIR_COEFF22_H 0xf43b000f + +/* IQDEM_ADJ_EN */ +#define R367CAB_IQDEM_ADJ_EN 0xf43c +#define F367CAB_ALLPASSFILT_EN 0xf43c0008 +#define F367CAB_ADJ_AGC_EN 0xf43c0004 +#define F367CAB_ADJ_COEFF_FRZ 0xf43c0002 +#define F367CAB_ADJ_EN 0xf43c0001 + +/* IQDEM_ADJ_AGC_REF */ +#define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d +#define F367CAB_ADJ_AGC_REF 0xf43d00ff + +/* ALLPASSFILT1 */ +#define R367CAB_ALLPASSFILT1 0xf440 +#define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff + +/* ALLPASSFILT2 */ +#define R367CAB_ALLPASSFILT2 0xf441 +#define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff + +/* ALLPASSFILT3 */ +#define R367CAB_ALLPASSFILT3 0xf442 +#define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0 +#define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f + +/* ALLPASSFILT4 */ +#define R367CAB_ALLPASSFILT4 0xf443 +#define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff + +/* ALLPASSFILT5 */ +#define R367CAB_ALLPASSFILT5 0xf444 +#define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff + +/* ALLPASSFILT6 */ +#define R367CAB_ALLPASSFILT6 0xf445 +#define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0 +#define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f + +/* ALLPASSFILT7 */ +#define R367CAB_ALLPASSFILT7 0xf446 +#define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff + +/* ALLPASSFILT8 */ +#define R367CAB_ALLPASSFILT8 0xf447 +#define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff + +/* ALLPASSFILT9 */ +#define R367CAB_ALLPASSFILT9 0xf448 +#define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc +#define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003 + +/* ALLPASSFILT10 */ +#define R367CAB_ALLPASSFILT10 0xf449 +#define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff + +/* ALLPASSFILT11 */ +#define R367CAB_ALLPASSFILT11 0xf44a +#define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff + +/* TRL_AGC_CFG */ +#define R367CAB_TRL_AGC_CFG 0xf450 +#define F367CAB_TRL_AGC_FREEZE 0xf4500080 +#define F367CAB_TRL_AGC_REF 0xf450007f + +/* TRL_LPF_CFG */ +#define R367CAB_TRL_LPF_CFG 0xf454 +#define F367CAB_NYQPOINT_INV 0xf4540040 +#define F367CAB_TRL_SHIFT 0xf4540030 +#define F367CAB_NYQ_COEFF_SEL 0xf454000c +#define F367CAB_TRL_LPF_FREEZE 0xf4540002 +#define F367CAB_TRL_LPF_CRT 0xf4540001 + +/* TRL_LPF_ACQ_GAIN */ +#define R367CAB_TRL_LPF_ACQ_GAIN 0xf455 +#define F367CAB_TRL_GDIR_ACQ 0xf4550070 +#define F367CAB_TRL_GINT_ACQ 0xf4550007 + +/* TRL_LPF_TRK_GAIN */ +#define R367CAB_TRL_LPF_TRK_GAIN 0xf456 +#define F367CAB_TRL_GDIR_TRK 0xf4560070 +#define F367CAB_TRL_GINT_TRK 0xf4560007 + +/* TRL_LPF_OUT_GAIN */ +#define R367CAB_TRL_LPF_OUT_GAIN 0xf457 +#define F367CAB_TRL_GAIN_OUT 0xf4570007 + +/* TRL_LOCKDET_LTH */ +#define R367CAB_TRL_LOCKDET_LTH 0xf458 +#define F367CAB_TRL_LCK_THLO 0xf4580007 + +/* TRL_LOCKDET_HTH */ +#define R367CAB_TRL_LOCKDET_HTH 0xf459 +#define F367CAB_TRL_LCK_THHI 0xf45900ff + +/* TRL_LOCKDET_TRGVAL */ +#define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a +#define F367CAB_TRL_LCK_TRG 0xf45a00ff + +/* IQ_QAM */ +#define R367CAB_IQ_QAM 0xf45c +#define F367CAB_IQ_INPUT 0xf45c0008 +#define F367CAB_DETECT_MODE 0xf45c0007 + +/* FSM_STATE */ +#define R367CAB_FSM_STATE 0xf460 +#define F367CAB_CRL_DFE 0xf4600080 +#define F367CAB_DFE_START 0xf4600040 +#define F367CAB_CTRLG_START 0xf4600030 +#define F367CAB_FSM_FORCESTATE 0xf460000f + +/* FSM_CTL */ +#define R367CAB_FSM_CTL 0xf461 +#define F367CAB_FEC2_EN 0xf4610040 +#define F367CAB_SIT_EN 0xf4610020 +#define F367CAB_TRL_AHEAD 0xf4610010 +#define F367CAB_TRL2_EN 0xf4610008 +#define F367CAB_FSM_EQA1_EN 0xf4610004 +#define F367CAB_FSM_BKP_DIS 0xf4610002 +#define F367CAB_FSM_FORCE_EN 0xf4610001 + +/* FSM_STS */ +#define R367CAB_FSM_STS 0xf462 +#define F367CAB_FSM_STATUS 0xf462000f + +/* FSM_SNR0_HTH */ +#define R367CAB_FSM_SNR0_HTH 0xf463 +#define F367CAB_SNR0_HTH 0xf46300ff + +/* FSM_SNR1_HTH */ +#define R367CAB_FSM_SNR1_HTH 0xf464 +#define F367CAB_SNR1_HTH 0xf46400ff + +/* FSM_SNR2_HTH */ +#define R367CAB_FSM_SNR2_HTH 0xf465 +#define F367CAB_SNR2_HTH 0xf46500ff + +/* FSM_SNR0_LTH */ +#define R367CAB_FSM_SNR0_LTH 0xf466 +#define F367CAB_SNR0_LTH 0xf46600ff + +/* FSM_SNR1_LTH */ +#define R367CAB_FSM_SNR1_LTH 0xf467 +#define F367CAB_SNR1_LTH 0xf46700ff + +/* FSM_EQA1_HTH */ +#define R367CAB_FSM_EQA1_HTH 0xf468 +#define F367CAB_SNR3_HTH_LO 0xf46800f0 +#define F367CAB_EQA1_HTH 0xf468000f + +/* FSM_TEMPO */ +#define R367CAB_FSM_TEMPO 0xf469 +#define F367CAB_SIT 0xf46900c0 +#define F367CAB_WST 0xf4690038 +#define F367CAB_ELT 0xf4690006 +#define F367CAB_SNR3_HTH_HI 0xf4690001 + +/* FSM_CONFIG */ +#define R367CAB_FSM_CONFIG 0xf46a +#define F367CAB_FEC2_DFEOFF 0xf46a0004 +#define F367CAB_PRIT_STATE 0xf46a0002 +#define F367CAB_MODMAP_STATE 0xf46a0001 + +/* EQU_I_TESTTAP_L */ +#define R367CAB_EQU_I_TESTTAP_L 0xf474 +#define F367CAB_I_TEST_TAP_L 0xf47400ff + +/* EQU_I_TESTTAP_M */ +#define R367CAB_EQU_I_TESTTAP_M 0xf475 +#define F367CAB_I_TEST_TAP_M 0xf47500ff + +/* EQU_I_TESTTAP_H */ +#define R367CAB_EQU_I_TESTTAP_H 0xf476 +#define F367CAB_I_TEST_TAP_H 0xf476001f + +/* EQU_TESTAP_CFG */ +#define R367CAB_EQU_TESTAP_CFG 0xf477 +#define F367CAB_TEST_FFE_DFE_SEL 0xf4770040 +#define F367CAB_TEST_TAP_SELECT 0xf477003f + +/* EQU_Q_TESTTAP_L */ +#define R367CAB_EQU_Q_TESTTAP_L 0xf478 +#define F367CAB_Q_TEST_TAP_L 0xf47800ff + +/* EQU_Q_TESTTAP_M */ +#define R367CAB_EQU_Q_TESTTAP_M 0xf479 +#define F367CAB_Q_TEST_TAP_M 0xf47900ff + +/* EQU_Q_TESTTAP_H */ +#define R367CAB_EQU_Q_TESTTAP_H 0xf47a +#define F367CAB_Q_TEST_TAP_H 0xf47a001f + +/* EQU_TAP_CTRL */ +#define R367CAB_EQU_TAP_CTRL 0xf47b +#define F367CAB_MTAP_FRZ 0xf47b0010 +#define F367CAB_PRE_FREEZE 0xf47b0008 +#define F367CAB_DFE_TAPMON_EN 0xf47b0004 +#define F367CAB_FFE_TAPMON_EN 0xf47b0002 +#define F367CAB_MTAP_ONLY 0xf47b0001 + +/* EQU_CTR_CRL_CONTROL_L */ +#define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c +#define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff + +/* EQU_CTR_CRL_CONTROL_H */ +#define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d +#define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff + +/* EQU_CTR_HIPOW_L */ +#define R367CAB_EQU_CTR_HIPOW_L 0xf47e +#define F367CAB_CTR_HIPOW_L 0xf47e00ff + +/* EQU_CTR_HIPOW_H */ +#define R367CAB_EQU_CTR_HIPOW_H 0xf47f +#define F367CAB_CTR_HIPOW_H 0xf47f00ff + +/* EQU_I_EQU_LO */ +#define R367CAB_EQU_I_EQU_LO 0xf480 +#define F367CAB_EQU_I_EQU_L 0xf48000ff + +/* EQU_I_EQU_HI */ +#define R367CAB_EQU_I_EQU_HI 0xf481 +#define F367CAB_EQU_I_EQU_H 0xf4810003 + +/* EQU_Q_EQU_LO */ +#define R367CAB_EQU_Q_EQU_LO 0xf482 +#define F367CAB_EQU_Q_EQU_L 0xf48200ff + +/* EQU_Q_EQU_HI */ +#define R367CAB_EQU_Q_EQU_HI 0xf483 +#define F367CAB_EQU_Q_EQU_H 0xf4830003 + +/* EQU_MAPPER */ +#define R367CAB_EQU_MAPPER 0xf484 +#define F367CAB_QUAD_AUTO 0xf4840080 +#define F367CAB_QUAD_INV 0xf4840040 +#define F367CAB_QAM_MODE 0xf4840007 + +/* EQU_SWEEP_RATE */ +#define R367CAB_EQU_SWEEP_RATE 0xf485 +#define F367CAB_SNR_PER 0xf48500c0 +#define F367CAB_SWEEP_RATE 0xf485003f + +/* EQU_SNR_LO */ +#define R367CAB_EQU_SNR_LO 0xf486 +#define F367CAB_SNR_LO 0xf48600ff + +/* EQU_SNR_HI */ +#define R367CAB_EQU_SNR_HI 0xf487 +#define F367CAB_SNR_HI 0xf48700ff + +/* EQU_GAMMA_LO */ +#define R367CAB_EQU_GAMMA_LO 0xf488 +#define F367CAB_GAMMA_LO 0xf48800ff + +/* EQU_GAMMA_HI */ +#define R367CAB_EQU_GAMMA_HI 0xf489 +#define F367CAB_GAMMA_ME 0xf48900ff + +/* EQU_ERR_GAIN */ +#define R367CAB_EQU_ERR_GAIN 0xf48a +#define F367CAB_EQA1MU 0xf48a0070 +#define F367CAB_CRL2MU 0xf48a000e +#define F367CAB_GAMMA_HI 0xf48a0001 + +/* EQU_RADIUS */ +#define R367CAB_EQU_RADIUS 0xf48b +#define F367CAB_RADIUS 0xf48b00ff + +/* EQU_FFE_MAINTAP */ +#define R367CAB_EQU_FFE_MAINTAP 0xf48c +#define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff + +/* EQU_FFE_LEAKAGE */ +#define R367CAB_EQU_FFE_LEAKAGE 0xf48e +#define F367CAB_LEAK_PER 0xf48e00f0 +#define F367CAB_EQU_OUTSEL 0xf48e0002 +#define F367CAB_PNT2dFE 0xf48e0001 + +/* EQU_FFE_MAINTAP_POS */ +#define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f +#define F367CAB_FFE_LEAK_EN 0xf48f0080 +#define F367CAB_DFE_LEAK_EN 0xf48f0040 +#define F367CAB_FFE_MAINTAP_POS 0xf48f003f + +/* EQU_GAIN_WIDE */ +#define R367CAB_EQU_GAIN_WIDE 0xf490 +#define F367CAB_DFE_GAIN_WIDE 0xf49000f0 +#define F367CAB_FFE_GAIN_WIDE 0xf490000f + +/* EQU_GAIN_NARROW */ +#define R367CAB_EQU_GAIN_NARROW 0xf491 +#define F367CAB_DFE_GAIN_NARROW 0xf49100f0 +#define F367CAB_FFE_GAIN_NARROW 0xf491000f + +/* EQU_CTR_LPF_GAIN */ +#define R367CAB_EQU_CTR_LPF_GAIN 0xf492 +#define F367CAB_CTR_GTO 0xf4920080 +#define F367CAB_CTR_GDIR 0xf4920070 +#define F367CAB_SWEEP_EN 0xf4920008 +#define F367CAB_CTR_GINT 0xf4920007 + +/* EQU_CRL_LPF_GAIN */ +#define R367CAB_EQU_CRL_LPF_GAIN 0xf493 +#define F367CAB_CRL_GTO 0xf4930080 +#define F367CAB_CRL_GDIR 0xf4930070 +#define F367CAB_SWEEP_DIR 0xf4930008 +#define F367CAB_CRL_GINT 0xf4930007 + +/* EQU_GLOBAL_GAIN */ +#define R367CAB_EQU_GLOBAL_GAIN 0xf494 +#define F367CAB_CRL_GAIN 0xf49400f8 +#define F367CAB_CTR_INC_GAIN 0xf4940004 +#define F367CAB_CTR_FRAC 0xf4940003 + +/* EQU_CRL_LD_SEN */ +#define R367CAB_EQU_CRL_LD_SEN 0xf495 +#define F367CAB_CTR_BADPOINT_EN 0xf4950080 +#define F367CAB_CTR_GAIN 0xf4950070 +#define F367CAB_LIMANEN 0xf4950008 +#define F367CAB_CRL_LD_SEN 0xf4950007 + +/* EQU_CRL_LD_VAL */ +#define R367CAB_EQU_CRL_LD_VAL 0xf496 +#define F367CAB_CRL_BISTH_LIMIT 0xf4960080 +#define F367CAB_CARE_EN 0xf4960040 +#define F367CAB_CRL_LD_PER 0xf4960030 +#define F367CAB_CRL_LD_WST 0xf496000c +#define F367CAB_CRL_LD_TFS 0xf4960003 + +/* EQU_CRL_TFR */ +#define R367CAB_EQU_CRL_TFR 0xf497 +#define F367CAB_CRL_LD_TFR 0xf49700ff + +/* EQU_CRL_BISTH_LO */ +#define R367CAB_EQU_CRL_BISTH_LO 0xf498 +#define F367CAB_CRL_BISTH_LO 0xf49800ff + +/* EQU_CRL_BISTH_HI */ +#define R367CAB_EQU_CRL_BISTH_HI 0xf499 +#define F367CAB_CRL_BISTH_HI 0xf49900ff + +/* EQU_SWEEP_RANGE_LO */ +#define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a +#define F367CAB_SWEEP_RANGE_LO 0xf49a00ff + +/* EQU_SWEEP_RANGE_HI */ +#define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b +#define F367CAB_SWEEP_RANGE_HI 0xf49b00ff + +/* EQU_CRL_LIMITER */ +#define R367CAB_EQU_CRL_LIMITER 0xf49c +#define F367CAB_BISECTOR_EN 0xf49c0080 +#define F367CAB_PHEST128_EN 0xf49c0040 +#define F367CAB_CRL_LIM 0xf49c003f + +/* EQU_MODULUS_MAP */ +#define R367CAB_EQU_MODULUS_MAP 0xf49d +#define F367CAB_PNT_DEPTH 0xf49d00e0 +#define F367CAB_MODULUS_CMP 0xf49d001f + +/* EQU_PNT_GAIN */ +#define R367CAB_EQU_PNT_GAIN 0xf49e +#define F367CAB_PNT_EN 0xf49e0080 +#define F367CAB_MODULUSMAP_EN 0xf49e0040 +#define F367CAB_PNT_GAIN 0xf49e003f + +/* FEC_AC_CTR_0 */ +#define R367CAB_FEC_AC_CTR_0 0xf4a8 +#define F367CAB_BE_BYPASS 0xf4a80020 +#define F367CAB_REFRESH47 0xf4a80010 +#define F367CAB_CT_NBST 0xf4a80008 +#define F367CAB_TEI_ENA 0xf4a80004 +#define F367CAB_DS_ENA 0xf4a80002 +#define F367CAB_TSMF_EN 0xf4a80001 + +/* FEC_AC_CTR_1 */ +#define R367CAB_FEC_AC_CTR_1 0xf4a9 +#define F367CAB_DEINT_DEPTH 0xf4a900ff + +/* FEC_AC_CTR_2 */ +#define R367CAB_FEC_AC_CTR_2 0xf4aa +#define F367CAB_DEINT_M 0xf4aa00f8 +#define F367CAB_DIS_UNLOCK 0xf4aa0004 +#define F367CAB_DESCR_MODE 0xf4aa0003 + +/* FEC_AC_CTR_3 */ +#define R367CAB_FEC_AC_CTR_3 0xf4ab +#define F367CAB_DI_UNLOCK 0xf4ab0080 +#define F367CAB_DI_FREEZE 0xf4ab0040 +#define F367CAB_MISMATCH 0xf4ab0030 +#define F367CAB_ACQ_MODE 0xf4ab000c +#define F367CAB_TRK_MODE 0xf4ab0003 + +/* FEC_STATUS */ +#define R367CAB_FEC_STATUS 0xf4ac +#define F367CAB_DEINT_SMCNTR 0xf4ac00e0 +#define F367CAB_DEINT_SYNCSTATE 0xf4ac0018 +#define F367CAB_DEINT_SYNLOST 0xf4ac0004 +#define F367CAB_DESCR_SYNCSTATE 0xf4ac0002 + +/* RS_COUNTER_0 */ +#define R367CAB_RS_COUNTER_0 0xf4ae +#define F367CAB_BK_CT_L 0xf4ae00ff + +/* RS_COUNTER_1 */ +#define R367CAB_RS_COUNTER_1 0xf4af +#define F367CAB_BK_CT_H 0xf4af00ff + +/* RS_COUNTER_2 */ +#define R367CAB_RS_COUNTER_2 0xf4b0 +#define F367CAB_CORR_CT_L 0xf4b000ff + +/* RS_COUNTER_3 */ +#define R367CAB_RS_COUNTER_3 0xf4b1 +#define F367CAB_CORR_CT_H 0xf4b100ff + +/* RS_COUNTER_4 */ +#define R367CAB_RS_COUNTER_4 0xf4b2 +#define F367CAB_UNCORR_CT_L 0xf4b200ff + +/* RS_COUNTER_5 */ +#define R367CAB_RS_COUNTER_5 0xf4b3 +#define F367CAB_UNCORR_CT_H 0xf4b300ff + +/* BERT_0 */ +#define R367CAB_BERT_0 0xf4b4 +#define F367CAB_RS_NOCORR 0xf4b40004 +#define F367CAB_CT_HOLD 0xf4b40002 +#define F367CAB_CT_CLEAR 0xf4b40001 + +/* BERT_1 */ +#define R367CAB_BERT_1 0xf4b5 +#define F367CAB_BERT_ON 0xf4b50020 +#define F367CAB_BERT_ERR_SRC 0xf4b50010 +#define F367CAB_BERT_ERR_MODE 0xf4b50008 +#define F367CAB_BERT_NBYTE 0xf4b50007 + +/* BERT_2 */ +#define R367CAB_BERT_2 0xf4b6 +#define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff + +/* BERT_3 */ +#define R367CAB_BERT_3 0xf4b7 +#define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff + +/* OUTFORMAT_0 */ +#define R367CAB_OUTFORMAT_0 0xf4b8 +#define F367CAB_CLK_POLARITY 0xf4b80080 +#define F367CAB_FEC_TYPE 0xf4b80040 +#define F367CAB_SYNC_STRIP 0xf4b80008 +#define F367CAB_TS_SWAP 0xf4b80004 +#define F367CAB_OUTFORMAT 0xf4b80003 + +/* OUTFORMAT_1 */ +#define R367CAB_OUTFORMAT_1 0xf4b9 +#define F367CAB_CI_DIVRANGE 0xf4b900ff + +/* SMOOTHER_2 */ +#define R367CAB_SMOOTHER_2 0xf4be +#define F367CAB_FIFO_BYPASS 0xf4be0020 + +/* TSMF_CTRL_0 */ +#define R367CAB_TSMF_CTRL_0 0xf4c0 +#define F367CAB_TS_NUMBER 0xf4c0001e +#define F367CAB_SEL_MODE 0xf4c00001 + +/* TSMF_CTRL_1 */ +#define R367CAB_TSMF_CTRL_1 0xf4c1 +#define F367CAB_CHECK_ERROR_BIT 0xf4c10080 +#define F367CAB_CHCK_F_SYNC 0xf4c10040 +#define F367CAB_H_MODE 0xf4c10008 +#define F367CAB_D_V_MODE 0xf4c10004 +#define F367CAB_MODE 0xf4c10003 + +/* TSMF_CTRL_3 */ +#define R367CAB_TSMF_CTRL_3 0xf4c3 +#define F367CAB_SYNC_IN_COUNT 0xf4c300f0 +#define F367CAB_SYNC_OUT_COUNT 0xf4c3000f + +/* TS_ON_ID_0 */ +#define R367CAB_TS_ON_ID_0 0xf4c4 +#define F367CAB_TS_ID_L 0xf4c400ff + +/* TS_ON_ID_1 */ +#define R367CAB_TS_ON_ID_1 0xf4c5 +#define F367CAB_TS_ID_H 0xf4c500ff + +/* TS_ON_ID_2 */ +#define R367CAB_TS_ON_ID_2 0xf4c6 +#define F367CAB_ON_ID_L 0xf4c600ff + +/* TS_ON_ID_3 */ +#define R367CAB_TS_ON_ID_3 0xf4c7 +#define F367CAB_ON_ID_H 0xf4c700ff + +/* RE_STATUS_0 */ +#define R367CAB_RE_STATUS_0 0xf4c8 +#define F367CAB_RECEIVE_STATUS_L 0xf4c800ff + +/* RE_STATUS_1 */ +#define R367CAB_RE_STATUS_1 0xf4c9 +#define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff + +/* RE_STATUS_2 */ +#define R367CAB_RE_STATUS_2 0xf4ca +#define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff + +/* RE_STATUS_3 */ +#define R367CAB_RE_STATUS_3 0xf4cb +#define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f + +/* TS_STATUS_0 */ +#define R367CAB_TS_STATUS_0 0xf4cc +#define F367CAB_TS_STATUS_L 0xf4cc00ff + +/* TS_STATUS_1 */ +#define R367CAB_TS_STATUS_1 0xf4cd +#define F367CAB_TS_STATUS_H 0xf4cd007f + +/* TS_STATUS_2 */ +#define R367CAB_TS_STATUS_2 0xf4ce +#define F367CAB_ERROR 0xf4ce0080 +#define F367CAB_EMERGENCY 0xf4ce0040 +#define F367CAB_CRE_TS 0xf4ce0030 +#define F367CAB_VER 0xf4ce000e +#define F367CAB_M_LOCK 0xf4ce0001 + +/* TS_STATUS_3 */ +#define R367CAB_TS_STATUS_3 0xf4cf +#define F367CAB_UPDATE_READY 0xf4cf0080 +#define F367CAB_END_FRAME_HEADER 0xf4cf0040 +#define F367CAB_CONTCNT 0xf4cf0020 +#define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f + +/* T_O_ID_0 */ +#define R367CAB_T_O_ID_0 0xf4d0 +#define F367CAB_ON_ID_I_L 0xf4d000ff + +/* T_O_ID_1 */ +#define R367CAB_T_O_ID_1 0xf4d1 +#define F367CAB_ON_ID_I_H 0xf4d100ff + +/* T_O_ID_2 */ +#define R367CAB_T_O_ID_2 0xf4d2 +#define F367CAB_TS_ID_I_L 0xf4d200ff + +/* T_O_ID_3 */ +#define R367CAB_T_O_ID_3 0xf4d3 +#define F367CAB_TS_ID_I_H 0xf4d300ff + +#define STV0367CAB_NBREGS 187 + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,2331 @@ +/* + * stv0367dd: STV0367 DVB-C/T demodulator driver + * + * Copyright (C) 2011 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "stv0367dd.h" +#include "stv0367dd_regs.h" + +enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; +enum { QAM_MOD_QAM4 = 0, + QAM_MOD_QAM16, + QAM_MOD_QAM32, + QAM_MOD_QAM64, + QAM_MOD_QAM128, + QAM_MOD_QAM256, + QAM_MOD_QAM512, + QAM_MOD_QAM1024 +}; + +enum {QAM_SPECT_NORMAL, QAM_SPECT_INVERTED }; + +enum { + QAM_FEC_A = 1, /* J83 Annex A */ + QAM_FEC_B = (1<<1), /* J83 Annex B */ + QAM_FEC_C = (1<<2) /* J83 Annex C */ +}; + +enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; + +struct stv_state { +#ifdef USE_API3 + struct dvb_frontend c_frontend; + struct dvb_frontend t_frontend; +#else + struct dvb_frontend frontend; +#endif + fe_modulation_t modulation; + u32 symbol_rate; + u32 bandwidth; + struct device *dev; + + struct i2c_adapter *i2c; + u8 adr; + void *priv; + + struct mutex mutex; + struct mutex ctlock; + + u32 master_clock; + u32 adc_clock; + u8 ID; + u8 I2CRPT; + u32 omode; + u8 qam_inversion; + + s32 IF; + + s32 m_FECTimeOut; + s32 m_DemodTimeOut; + s32 m_SignalTimeOut; + s32 m_DemodLockTime; + s32 m_FFTTimeOut; + s32 m_TSTimeOut; + + bool m_bFirstTimeLock; + + u8 m_Save_QAM_AGC_CTL; + + enum EDemodState demod_state; + + u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k + u8 m_OFDM_Modulation; // + u8 m_OFDM_FEC; // + u8 m_OFDM_Guard; + + u32 ucblocks; + u32 ber; +}; + +struct init_table { + u16 adr; + u8 data; +}; + +struct init_table base_init[] = { + { R367_IOCFG0, 0x80 }, + { R367_DAC0R, 0x00 }, + { R367_IOCFG1, 0x00 }, + { R367_DAC1R, 0x00 }, + { R367_IOCFG2, 0x00 }, + { R367_SDFR, 0x00 }, + { R367_AUX_CLK, 0x00 }, + { R367_FREESYS1, 0x00 }, + { R367_FREESYS2, 0x00 }, + { R367_FREESYS3, 0x00 }, + { R367_GPIO_CFG, 0x55 }, + { R367_GPIO_CMD, 0x01 }, + { R367_TSTRES, 0x00 }, + { R367_ANACTRL, 0x00 }, + { R367_TSTBUS, 0x00 }, + { R367_RF_AGC2, 0x20 }, + { R367_ANADIGCTRL, 0x0b }, + { R367_PLLMDIV, 0x01 }, + { R367_PLLNDIV, 0x08 }, + { R367_PLLSETUP, 0x18 }, + { R367_DUAL_AD12, 0x04 }, + { R367_TSTBIST, 0x00 }, + { 0x0000, 0x00 } +}; + +struct init_table qam_init[] = { + { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 + { R367_QAM_CTRL_2, 0x03 }, + { R367_QAM_IT_STATUS1, 0x2b }, + { R367_QAM_IT_STATUS2, 0x08 }, + { R367_QAM_IT_EN1, 0x00 }, + { R367_QAM_IT_EN2, 0x00 }, + { R367_QAM_CTRL_STATUS, 0x04 }, + { R367_QAM_TEST_CTL, 0x00 }, + { R367_QAM_AGC_CTL, 0x73 }, + { R367_QAM_AGC_IF_CFG, 0x50 }, + { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze + { R367_QAM_AGC_PWM_CFG, 0x03 }, + { R367_QAM_AGC_PWR_REF_L, 0x5a }, + { R367_QAM_AGC_PWR_REF_H, 0x00 }, + { R367_QAM_AGC_RF_TH_L, 0xff }, + { R367_QAM_AGC_RF_TH_H, 0x07 }, + { R367_QAM_AGC_IF_LTH_L, 0x00 }, + { R367_QAM_AGC_IF_LTH_H, 0x08 }, + { R367_QAM_AGC_IF_HTH_L, 0xff }, + { R367_QAM_AGC_IF_HTH_H, 0x07 }, + { R367_QAM_AGC_PWR_RD_L, 0xa0 }, + { R367_QAM_AGC_PWR_RD_M, 0xe9 }, + { R367_QAM_AGC_PWR_RD_H, 0x03 }, + { R367_QAM_AGC_PWM_IFCMD_L, 0xe4 }, + { R367_QAM_AGC_PWM_IFCMD_H, 0x00 }, + { R367_QAM_AGC_PWM_RFCMD_L, 0xff }, + { R367_QAM_AGC_PWM_RFCMD_H, 0x07 }, + { R367_QAM_IQDEM_CFG, 0x01 }, + { R367_QAM_MIX_NCO_LL, 0x22 }, + { R367_QAM_MIX_NCO_HL, 0x96 }, + { R367_QAM_MIX_NCO_HH, 0x55 }, + { R367_QAM_SRC_NCO_LL, 0xff }, + { R367_QAM_SRC_NCO_LH, 0x0c }, + { R367_QAM_SRC_NCO_HL, 0xf5 }, + { R367_QAM_SRC_NCO_HH, 0x20 }, + { R367_QAM_IQDEM_GAIN_SRC_L, 0x06 }, + { R367_QAM_IQDEM_GAIN_SRC_H, 0x01 }, + { R367_QAM_IQDEM_DCRM_CFG_LL, 0xfe }, + { R367_QAM_IQDEM_DCRM_CFG_LH, 0xff }, + { R367_QAM_IQDEM_DCRM_CFG_HL, 0x0f }, + { R367_QAM_IQDEM_DCRM_CFG_HH, 0x00 }, + { R367_QAM_IQDEM_ADJ_COEFF0, 0x34 }, + { R367_QAM_IQDEM_ADJ_COEFF1, 0xae }, + { R367_QAM_IQDEM_ADJ_COEFF2, 0x46 }, + { R367_QAM_IQDEM_ADJ_COEFF3, 0x77 }, + { R367_QAM_IQDEM_ADJ_COEFF4, 0x96 }, + { R367_QAM_IQDEM_ADJ_COEFF5, 0x69 }, + { R367_QAM_IQDEM_ADJ_COEFF6, 0xc7 }, + { R367_QAM_IQDEM_ADJ_COEFF7, 0x01 }, + { R367_QAM_IQDEM_ADJ_EN, 0x04 }, + { R367_QAM_IQDEM_ADJ_AGC_REF, 0x94 }, + { R367_QAM_ALLPASSFILT1, 0xc9 }, + { R367_QAM_ALLPASSFILT2, 0x2d }, + { R367_QAM_ALLPASSFILT3, 0xa3 }, + { R367_QAM_ALLPASSFILT4, 0xfb }, + { R367_QAM_ALLPASSFILT5, 0xf6 }, + { R367_QAM_ALLPASSFILT6, 0x45 }, + { R367_QAM_ALLPASSFILT7, 0x6f }, + { R367_QAM_ALLPASSFILT8, 0x7e }, + { R367_QAM_ALLPASSFILT9, 0x05 }, + { R367_QAM_ALLPASSFILT10, 0x0a }, + { R367_QAM_ALLPASSFILT11, 0x51 }, + { R367_QAM_TRL_AGC_CFG, 0x20 }, + { R367_QAM_TRL_LPF_CFG, 0x28 }, + { R367_QAM_TRL_LPF_ACQ_GAIN, 0x44 }, + { R367_QAM_TRL_LPF_TRK_GAIN, 0x22 }, + { R367_QAM_TRL_LPF_OUT_GAIN, 0x03 }, + { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, + { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, + { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, + { R367_QAM_IQ_QAM, 0x01 }, + { R367_QAM_FSM_STATE, 0xa0 }, + { R367_QAM_FSM_CTL, 0x08 }, + { R367_QAM_FSM_STS, 0x0c }, + { R367_QAM_FSM_SNR0_HTH, 0x00 }, + { R367_QAM_FSM_SNR1_HTH, 0x00 }, + { R367_QAM_FSM_SNR2_HTH, 0x00 }, + { R367_QAM_FSM_SNR0_LTH, 0x00 }, + { R367_QAM_FSM_SNR1_LTH, 0x00 }, + { R367_QAM_FSM_EQA1_HTH, 0x00 }, + { R367_QAM_FSM_TEMPO, 0x32 }, + { R367_QAM_FSM_CONFIG, 0x03 }, + { R367_QAM_EQU_I_TESTTAP_L, 0x11 }, + { R367_QAM_EQU_I_TESTTAP_M, 0x00 }, + { R367_QAM_EQU_I_TESTTAP_H, 0x00 }, + { R367_QAM_EQU_TESTAP_CFG, 0x00 }, + { R367_QAM_EQU_Q_TESTTAP_L, 0xff }, + { R367_QAM_EQU_Q_TESTTAP_M, 0x00 }, + { R367_QAM_EQU_Q_TESTTAP_H, 0x00 }, + { R367_QAM_EQU_TAP_CTRL, 0x00 }, + { R367_QAM_EQU_CTR_CRL_CONTROL_L, 0x11 }, + { R367_QAM_EQU_CTR_CRL_CONTROL_H, 0x05 }, + { R367_QAM_EQU_CTR_HIPOW_L, 0x00 }, + { R367_QAM_EQU_CTR_HIPOW_H, 0x00 }, + { R367_QAM_EQU_I_EQU_LO, 0xef }, + { R367_QAM_EQU_I_EQU_HI, 0x00 }, + { R367_QAM_EQU_Q_EQU_LO, 0xee }, + { R367_QAM_EQU_Q_EQU_HI, 0x00 }, + { R367_QAM_EQU_MAPPER, 0xc5 }, + { R367_QAM_EQU_SWEEP_RATE, 0x80 }, + { R367_QAM_EQU_SNR_LO, 0x64 }, + { R367_QAM_EQU_SNR_HI, 0x03 }, + { R367_QAM_EQU_GAMMA_LO, 0x00 }, + { R367_QAM_EQU_GAMMA_HI, 0x00 }, + { R367_QAM_EQU_ERR_GAIN, 0x36 }, + { R367_QAM_EQU_RADIUS, 0xaa }, + { R367_QAM_EQU_FFE_MAINTAP, 0x00 }, + { R367_QAM_EQU_FFE_LEAKAGE, 0x63 }, + { R367_QAM_EQU_FFE_MAINTAP_POS, 0xdf }, + { R367_QAM_EQU_GAIN_WIDE, 0x88 }, + { R367_QAM_EQU_GAIN_NARROW, 0x41 }, + { R367_QAM_EQU_CTR_LPF_GAIN, 0xd1 }, + { R367_QAM_EQU_CRL_LPF_GAIN, 0xa7 }, + { R367_QAM_EQU_GLOBAL_GAIN, 0x06 }, + { R367_QAM_EQU_CRL_LD_SEN, 0x85 }, + { R367_QAM_EQU_CRL_LD_VAL, 0xe2 }, + { R367_QAM_EQU_CRL_TFR, 0x20 }, + { R367_QAM_EQU_CRL_BISTH_LO, 0x00 }, + { R367_QAM_EQU_CRL_BISTH_HI, 0x00 }, + { R367_QAM_EQU_SWEEP_RANGE_LO, 0x00 }, + { R367_QAM_EQU_SWEEP_RANGE_HI, 0x00 }, + { R367_QAM_EQU_CRL_LIMITER, 0x40 }, + { R367_QAM_EQU_MODULUS_MAP, 0x90 }, + { R367_QAM_EQU_PNT_GAIN, 0xa7 }, + { R367_QAM_FEC_AC_CTR_0, 0x16 }, + { R367_QAM_FEC_AC_CTR_1, 0x0b }, + { R367_QAM_FEC_AC_CTR_2, 0x88 }, + { R367_QAM_FEC_AC_CTR_3, 0x02 }, + { R367_QAM_FEC_STATUS, 0x12 }, + { R367_QAM_RS_COUNTER_0, 0x7d }, + { R367_QAM_RS_COUNTER_1, 0xd0 }, + { R367_QAM_RS_COUNTER_2, 0x19 }, + { R367_QAM_RS_COUNTER_3, 0x0b }, + { R367_QAM_RS_COUNTER_4, 0xa3 }, + { R367_QAM_RS_COUNTER_5, 0x00 }, + { R367_QAM_BERT_0, 0x01 }, + { R367_QAM_BERT_1, 0x25 }, + { R367_QAM_BERT_2, 0x41 }, + { R367_QAM_BERT_3, 0x39 }, + { R367_QAM_OUTFORMAT_0, 0xc2 }, + { R367_QAM_OUTFORMAT_1, 0x22 }, + { R367_QAM_SMOOTHER_2, 0x28 }, + { R367_QAM_TSMF_CTRL_0, 0x01 }, + { R367_QAM_TSMF_CTRL_1, 0xc6 }, + { R367_QAM_TSMF_CTRL_3, 0x43 }, + { R367_QAM_TS_ON_ID_0, 0x00 }, + { R367_QAM_TS_ON_ID_1, 0x00 }, + { R367_QAM_TS_ON_ID_2, 0x00 }, + { R367_QAM_TS_ON_ID_3, 0x00 }, + { R367_QAM_RE_STATUS_0, 0x00 }, + { R367_QAM_RE_STATUS_1, 0x00 }, + { R367_QAM_RE_STATUS_2, 0x00 }, + { R367_QAM_RE_STATUS_3, 0x00 }, + { R367_QAM_TS_STATUS_0, 0x00 }, + { R367_QAM_TS_STATUS_1, 0x00 }, + { R367_QAM_TS_STATUS_2, 0xa0 }, + { R367_QAM_TS_STATUS_3, 0x00 }, + { R367_QAM_T_O_ID_0, 0x00 }, + { R367_QAM_T_O_ID_1, 0x00 }, + { R367_QAM_T_O_ID_2, 0x00 }, + { R367_QAM_T_O_ID_3, 0x00 }, + { 0x0000, 0x00 } // EOT +}; + +struct init_table ofdm_init[] = { + //{R367_OFDM_ID ,0x60}, + //{R367_OFDM_I2CRPT ,0x22}, + //{R367_OFDM_TOPCTRL ,0x02}, + //{R367_OFDM_IOCFG0 ,0x40}, + //{R367_OFDM_DAC0R ,0x00}, + //{R367_OFDM_IOCFG1 ,0x00}, + //{R367_OFDM_DAC1R ,0x00}, + //{R367_OFDM_IOCFG2 ,0x62}, + //{R367_OFDM_SDFR ,0x00}, + //{R367_OFDM_STATUS ,0xf8}, + //{R367_OFDM_AUX_CLK ,0x0a}, + //{R367_OFDM_FREESYS1 ,0x00}, + //{R367_OFDM_FREESYS2 ,0x00}, + //{R367_OFDM_FREESYS3 ,0x00}, + //{R367_OFDM_GPIO_CFG ,0x55}, + //{R367_OFDM_GPIO_CMD ,0x00}, + {R367_OFDM_AGC2MAX ,0xff}, + {R367_OFDM_AGC2MIN ,0x00}, + {R367_OFDM_AGC1MAX ,0xff}, + {R367_OFDM_AGC1MIN ,0x00}, + {R367_OFDM_AGCR ,0xbc}, + {R367_OFDM_AGC2TH ,0x00}, + //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM + {R367_OFDM_AGCCTRL1 ,0x85}, + {R367_OFDM_AGCCTRL2 ,0x1f}, + {R367_OFDM_AGC1VAL1 ,0x00}, + {R367_OFDM_AGC1VAL2 ,0x00}, + {R367_OFDM_AGC2VAL1 ,0x6f}, + {R367_OFDM_AGC2VAL2 ,0x05}, + {R367_OFDM_AGC2PGA ,0x00}, + {R367_OFDM_OVF_RATE1 ,0x00}, + {R367_OFDM_OVF_RATE2 ,0x00}, + {R367_OFDM_GAIN_SRC1 ,0x2b}, + {R367_OFDM_GAIN_SRC2 ,0x04}, + {R367_OFDM_INC_DEROT1 ,0x55}, + {R367_OFDM_INC_DEROT2 ,0x55}, + {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, + {R367_OFDM_PPM_CPAMP_INV ,0x00}, + {R367_OFDM_FREESTFE_1 ,0x00}, + {R367_OFDM_FREESTFE_2 ,0x1c}, + {R367_OFDM_DCOFFSET ,0x00}, + {R367_OFDM_EN_PROCESS ,0x05}, + {R367_OFDM_SDI_SMOOTHER ,0x80}, + {R367_OFDM_FE_LOOP_OPEN ,0x1c}, + {R367_OFDM_FREQOFF1 ,0x00}, + {R367_OFDM_FREQOFF2 ,0x00}, + {R367_OFDM_FREQOFF3 ,0x00}, + {R367_OFDM_TIMOFF1 ,0x00}, + {R367_OFDM_TIMOFF2 ,0x00}, + {R367_OFDM_EPQ ,0x02}, + {R367_OFDM_EPQAUTO ,0x01}, + {R367_OFDM_SYR_UPDATE ,0xf5}, + {R367_OFDM_CHPFREE ,0x00}, + {R367_OFDM_PPM_STATE_MAC ,0x23}, + {R367_OFDM_INR_THRESHOLD ,0xff}, + {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, + {R367_OFDM_EPQ_CFG ,0x00}, + {R367_OFDM_EPQ_STATUS ,0x01}, + {R367_OFDM_AUTORELOCK ,0x81}, + {R367_OFDM_BER_THR_VMSB ,0x00}, + {R367_OFDM_BER_THR_MSB ,0x00}, + {R367_OFDM_BER_THR_LSB ,0x00}, + {R367_OFDM_CCD ,0x83}, + {R367_OFDM_SPECTR_CFG ,0x00}, + {R367_OFDM_CHC_DUMMY ,0x18}, + {R367_OFDM_INC_CTL ,0x88}, + {R367_OFDM_INCTHRES_COR1 ,0xb4}, + {R367_OFDM_INCTHRES_COR2 ,0x96}, + {R367_OFDM_INCTHRES_DET1 ,0x0e}, + {R367_OFDM_INCTHRES_DET2 ,0x11}, + {R367_OFDM_IIR_CELLNB ,0x8d}, + {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, + {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, + {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, + {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, + {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, + {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, + {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, + {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, + {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, + {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, + {R367_OFDM_FEPATH_CFG ,0x00}, + {R367_OFDM_PMC1_FUNC ,0x65}, + {R367_OFDM_PMC1_FOR ,0x00}, + {R367_OFDM_PMC2_FUNC ,0x00}, + {R367_OFDM_STATUS_ERR_DA ,0xe0}, + {R367_OFDM_DIG_AGC_R ,0xfe}, + {R367_OFDM_COMAGC_TARMSB ,0x0b}, + {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, + {R367_OFDM_COM_AGC_CFG ,0x3e}, + {R367_OFDM_COM_AGC_GAIN1 ,0x39}, + {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, + {R367_OFDM_LOCK_DET_MSB ,0x01}, + {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, + {R367_OFDM_AUT_GAIN_EN ,0xf4}, + {R367_OFDM_AUT_CFG ,0xf0}, + {R367_OFDM_LOCKN ,0x23}, + {R367_OFDM_INT_X_3 ,0x00}, + {R367_OFDM_INT_X_2 ,0x03}, + {R367_OFDM_INT_X_1 ,0x8d}, + {R367_OFDM_INT_X_0 ,0xa0}, + {R367_OFDM_MIN_ERRX_MSB ,0x00}, + {R367_OFDM_COR_CTL ,0x00}, + {R367_OFDM_COR_STAT ,0xf6}, + {R367_OFDM_COR_INTEN ,0x00}, + {R367_OFDM_COR_INTSTAT ,0x3f}, + {R367_OFDM_COR_MODEGUARD ,0x03}, + {R367_OFDM_AGC_CTL ,0x08}, + {R367_OFDM_AGC_MANUAL1 ,0x00}, + {R367_OFDM_AGC_MANUAL2 ,0x00}, + {R367_OFDM_AGC_TARG ,0x16}, + {R367_OFDM_AGC_GAIN1 ,0x53}, + {R367_OFDM_AGC_GAIN2 ,0x1d}, + {R367_OFDM_RESERVED_1 ,0x00}, + {R367_OFDM_RESERVED_2 ,0x00}, + {R367_OFDM_RESERVED_3 ,0x00}, + {R367_OFDM_CAS_CTL ,0x44}, + {R367_OFDM_CAS_FREQ ,0xb3}, + {R367_OFDM_CAS_DAGCGAIN ,0x12}, + {R367_OFDM_SYR_CTL ,0x04}, + {R367_OFDM_SYR_STAT ,0x10}, + {R367_OFDM_SYR_NCO1 ,0x00}, + {R367_OFDM_SYR_NCO2 ,0x00}, + {R367_OFDM_SYR_OFFSET1 ,0x00}, + {R367_OFDM_SYR_OFFSET2 ,0x00}, + {R367_OFDM_FFT_CTL ,0x00}, + {R367_OFDM_SCR_CTL ,0x70}, + {R367_OFDM_PPM_CTL1 ,0xf8}, + {R367_OFDM_TRL_CTL ,0xac}, + {R367_OFDM_TRL_NOMRATE1 ,0x1e}, + {R367_OFDM_TRL_NOMRATE2 ,0x58}, + {R367_OFDM_TRL_TIME1 ,0x1d}, + {R367_OFDM_TRL_TIME2 ,0xfc}, + {R367_OFDM_CRL_CTL ,0x24}, + {R367_OFDM_CRL_FREQ1 ,0xad}, + {R367_OFDM_CRL_FREQ2 ,0x9d}, + {R367_OFDM_CRL_FREQ3 ,0xff}, + {R367_OFDM_CHC_CTL ,0x01}, + {R367_OFDM_CHC_SNR ,0xf0}, + {R367_OFDM_BDI_CTL ,0x00}, + {R367_OFDM_DMP_CTL ,0x00}, + {R367_OFDM_TPS_RCVD1 ,0x30}, + {R367_OFDM_TPS_RCVD2 ,0x02}, + {R367_OFDM_TPS_RCVD3 ,0x01}, + {R367_OFDM_TPS_RCVD4 ,0x00}, + {R367_OFDM_TPS_ID_CELL1 ,0x00}, + {R367_OFDM_TPS_ID_CELL2 ,0x00}, + {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, + {R367_OFDM_TPS_SET2 ,0x02}, + {R367_OFDM_TPS_SET3 ,0x01}, + {R367_OFDM_TPS_CTL ,0x00}, + {R367_OFDM_CTL_FFTOSNUM ,0x34}, + {R367_OFDM_TESTSELECT ,0x09}, + {R367_OFDM_MSC_REV ,0x0a}, + {R367_OFDM_PIR_CTL ,0x00}, + {R367_OFDM_SNR_CARRIER1 ,0xa1}, + {R367_OFDM_SNR_CARRIER2 ,0x9a}, + {R367_OFDM_PPM_CPAMP ,0x2c}, + {R367_OFDM_TSM_AP0 ,0x00}, + {R367_OFDM_TSM_AP1 ,0x00}, + {R367_OFDM_TSM_AP2 ,0x00}, + {R367_OFDM_TSM_AP3 ,0x00}, + {R367_OFDM_TSM_AP4 ,0x00}, + {R367_OFDM_TSM_AP5 ,0x00}, + {R367_OFDM_TSM_AP6 ,0x00}, + {R367_OFDM_TSM_AP7 ,0x00}, + //{R367_OFDM_TSTRES ,0x00}, + //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ + //{R367_OFDM_TSTBUS ,0x00}, + //{R367_OFDM_TSTRATE ,0x00}, + {R367_OFDM_CONSTMODE ,0x01}, + {R367_OFDM_CONSTCARR1 ,0x00}, + {R367_OFDM_CONSTCARR2 ,0x00}, + {R367_OFDM_ICONSTEL ,0x0a}, + {R367_OFDM_QCONSTEL ,0x15}, + {R367_OFDM_TSTBISTRES0 ,0x00}, + {R367_OFDM_TSTBISTRES1 ,0x00}, + {R367_OFDM_TSTBISTRES2 ,0x28}, + {R367_OFDM_TSTBISTRES3 ,0x00}, + //{R367_OFDM_RF_AGC1 ,0xff}, + //{R367_OFDM_RF_AGC2 ,0x83}, + //{R367_OFDM_ANADIGCTRL ,0x19}, + //{R367_OFDM_PLLMDIV ,0x0c}, + //{R367_OFDM_PLLNDIV ,0x55}, + //{R367_OFDM_PLLSETUP ,0x18}, + //{R367_OFDM_DUAL_AD12 ,0x00}, + //{R367_OFDM_TSTBIST ,0x00}, + //{R367_OFDM_PAD_COMP_CTRL ,0x00}, + //{R367_OFDM_PAD_COMP_WR ,0x00}, + //{R367_OFDM_PAD_COMP_RD ,0xe0}, + {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, + {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, + {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, + {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, + {R367_OFDM_SYR_FLAG ,0x00}, + {R367_OFDM_CRL_TARGET1 ,0x00}, + {R367_OFDM_CRL_TARGET2 ,0x00}, + {R367_OFDM_CRL_TARGET3 ,0x00}, + {R367_OFDM_CRL_TARGET4 ,0x00}, + {R367_OFDM_CRL_FLAG ,0x00}, + {R367_OFDM_TRL_TARGET1 ,0x00}, + {R367_OFDM_TRL_TARGET2 ,0x00}, + {R367_OFDM_TRL_CHC ,0x00}, + {R367_OFDM_CHC_SNR_TARG ,0x00}, + {R367_OFDM_TOP_TRACK ,0x00}, + {R367_OFDM_TRACKER_FREE1 ,0x00}, + {R367_OFDM_ERROR_CRL1 ,0x00}, + {R367_OFDM_ERROR_CRL2 ,0x00}, + {R367_OFDM_ERROR_CRL3 ,0x00}, + {R367_OFDM_ERROR_CRL4 ,0x00}, + {R367_OFDM_DEC_NCO1 ,0x2c}, + {R367_OFDM_DEC_NCO2 ,0x0f}, + {R367_OFDM_DEC_NCO3 ,0x20}, + {R367_OFDM_SNR ,0xf1}, + {R367_OFDM_SYR_FFTADJ1 ,0x00}, + {R367_OFDM_SYR_FFTADJ2 ,0x00}, + {R367_OFDM_SYR_CHCADJ1 ,0x00}, + {R367_OFDM_SYR_CHCADJ2 ,0x00}, + {R367_OFDM_SYR_OFF ,0x00}, + {R367_OFDM_PPM_OFFSET1 ,0x00}, + {R367_OFDM_PPM_OFFSET2 ,0x03}, + {R367_OFDM_TRACKER_FREE2 ,0x00}, + {R367_OFDM_DEBG_LT10 ,0x00}, + {R367_OFDM_DEBG_LT11 ,0x00}, + {R367_OFDM_DEBG_LT12 ,0x00}, + {R367_OFDM_DEBG_LT13 ,0x00}, + {R367_OFDM_DEBG_LT14 ,0x00}, + {R367_OFDM_DEBG_LT15 ,0x00}, + {R367_OFDM_DEBG_LT16 ,0x00}, + {R367_OFDM_DEBG_LT17 ,0x00}, + {R367_OFDM_DEBG_LT18 ,0x00}, + {R367_OFDM_DEBG_LT19 ,0x00}, + {R367_OFDM_DEBG_LT1A ,0x00}, + {R367_OFDM_DEBG_LT1B ,0x00}, + {R367_OFDM_DEBG_LT1C ,0x00}, + {R367_OFDM_DEBG_LT1D ,0x00}, + {R367_OFDM_DEBG_LT1E ,0x00}, + {R367_OFDM_DEBG_LT1F ,0x00}, + {R367_OFDM_RCCFGH ,0x00}, + {R367_OFDM_RCCFGM ,0x00}, + {R367_OFDM_RCCFGL ,0x00}, + {R367_OFDM_RCINSDELH ,0x00}, + {R367_OFDM_RCINSDELM ,0x00}, + {R367_OFDM_RCINSDELL ,0x00}, + {R367_OFDM_RCSTATUS ,0x00}, + {R367_OFDM_RCSPEED ,0x6f}, + {R367_OFDM_RCDEBUGM ,0xe7}, + {R367_OFDM_RCDEBUGL ,0x9b}, + {R367_OFDM_RCOBSCFG ,0x00}, + {R367_OFDM_RCOBSM ,0x00}, + {R367_OFDM_RCOBSL ,0x00}, + {R367_OFDM_RCFECSPY ,0x00}, + {R367_OFDM_RCFSPYCFG ,0x00}, + {R367_OFDM_RCFSPYDATA ,0x00}, + {R367_OFDM_RCFSPYOUT ,0x00}, + {R367_OFDM_RCFSTATUS ,0x00}, + {R367_OFDM_RCFGOODPACK ,0x00}, + {R367_OFDM_RCFPACKCNT ,0x00}, + {R367_OFDM_RCFSPYMISC ,0x00}, + {R367_OFDM_RCFBERCPT4 ,0x00}, + {R367_OFDM_RCFBERCPT3 ,0x00}, + {R367_OFDM_RCFBERCPT2 ,0x00}, + {R367_OFDM_RCFBERCPT1 ,0x00}, + {R367_OFDM_RCFBERCPT0 ,0x00}, + {R367_OFDM_RCFBERERR2 ,0x00}, + {R367_OFDM_RCFBERERR1 ,0x00}, + {R367_OFDM_RCFBERERR0 ,0x00}, + {R367_OFDM_RCFSTATESM ,0x00}, + {R367_OFDM_RCFSTATESL ,0x00}, + {R367_OFDM_RCFSPYBER ,0x00}, + {R367_OFDM_RCFSPYDISTM ,0x00}, + {R367_OFDM_RCFSPYDISTL ,0x00}, + {R367_OFDM_RCFSPYOBS7 ,0x00}, + {R367_OFDM_RCFSPYOBS6 ,0x00}, + {R367_OFDM_RCFSPYOBS5 ,0x00}, + {R367_OFDM_RCFSPYOBS4 ,0x00}, + {R367_OFDM_RCFSPYOBS3 ,0x00}, + {R367_OFDM_RCFSPYOBS2 ,0x00}, + {R367_OFDM_RCFSPYOBS1 ,0x00}, + {R367_OFDM_RCFSPYOBS0 ,0x00}, + //{R367_OFDM_TSGENERAL ,0x00}, + //{R367_OFDM_RC1SPEED ,0x6f}, + //{R367_OFDM_TSGSTATUS ,0x18}, + {R367_OFDM_FECM ,0x01}, + {R367_OFDM_VTH12 ,0xff}, + {R367_OFDM_VTH23 ,0xa1}, + {R367_OFDM_VTH34 ,0x64}, + {R367_OFDM_VTH56 ,0x40}, + {R367_OFDM_VTH67 ,0x00}, + {R367_OFDM_VTH78 ,0x2c}, + {R367_OFDM_VITCURPUN ,0x12}, + {R367_OFDM_VERROR ,0x01}, + {R367_OFDM_PRVIT ,0x3f}, + {R367_OFDM_VAVSRVIT ,0x00}, + {R367_OFDM_VSTATUSVIT ,0xbd}, + {R367_OFDM_VTHINUSE ,0xa1}, + {R367_OFDM_KDIV12 ,0x20}, + {R367_OFDM_KDIV23 ,0x40}, + {R367_OFDM_KDIV34 ,0x20}, + {R367_OFDM_KDIV56 ,0x30}, + {R367_OFDM_KDIV67 ,0x00}, + {R367_OFDM_KDIV78 ,0x30}, + {R367_OFDM_SIGPOWER ,0x54}, + {R367_OFDM_DEMAPVIT ,0x40}, + {R367_OFDM_VITSCALE ,0x00}, + {R367_OFDM_FFEC1PRG ,0x00}, + {R367_OFDM_FVITCURPUN ,0x12}, + {R367_OFDM_FVERROR ,0x01}, + {R367_OFDM_FVSTATUSVIT ,0xbd}, + {R367_OFDM_DEBUG_LT1 ,0x00}, + {R367_OFDM_DEBUG_LT2 ,0x00}, + {R367_OFDM_DEBUG_LT3 ,0x00}, + {R367_OFDM_TSTSFMET ,0x00}, + {R367_OFDM_SELOUT ,0x00}, + {R367_OFDM_TSYNC ,0x00}, + {R367_OFDM_TSTERR ,0x00}, + {R367_OFDM_TSFSYNC ,0x00}, + {R367_OFDM_TSTSFERR ,0x00}, + {R367_OFDM_TSTTSSF1 ,0x01}, + {R367_OFDM_TSTTSSF2 ,0x1f}, + {R367_OFDM_TSTTSSF3 ,0x00}, + {R367_OFDM_TSTTS1 ,0x00}, + {R367_OFDM_TSTTS2 ,0x1f}, + {R367_OFDM_TSTTS3 ,0x01}, + {R367_OFDM_TSTTS4 ,0x00}, + {R367_OFDM_TSTTSRC ,0x00}, + {R367_OFDM_TSTTSRS ,0x00}, + {R367_OFDM_TSSTATEM ,0xb0}, + {R367_OFDM_TSSTATEL ,0x40}, + {R367_OFDM_TSCFGH ,0x80}, + {R367_OFDM_TSCFGM ,0x00}, + {R367_OFDM_TSCFGL ,0x20}, + {R367_OFDM_TSSYNC ,0x00}, + {R367_OFDM_TSINSDELH ,0x00}, + {R367_OFDM_TSINSDELM ,0x00}, + {R367_OFDM_TSINSDELL ,0x00}, + {R367_OFDM_TSDIVN ,0x03}, + {R367_OFDM_TSDIVPM ,0x00}, + {R367_OFDM_TSDIVPL ,0x00}, + {R367_OFDM_TSDIVQM ,0x00}, + {R367_OFDM_TSDIVQL ,0x00}, + {R367_OFDM_TSDILSTKM ,0x00}, + {R367_OFDM_TSDILSTKL ,0x00}, + {R367_OFDM_TSSPEED ,0x6f}, + {R367_OFDM_TSSTATUS ,0x81}, + {R367_OFDM_TSSTATUS2 ,0x6a}, + {R367_OFDM_TSBITRATEM ,0x0f}, + {R367_OFDM_TSBITRATEL ,0xc6}, + {R367_OFDM_TSPACKLENM ,0x00}, + {R367_OFDM_TSPACKLENL ,0xfc}, + {R367_OFDM_TSBLOCLENM ,0x0a}, + {R367_OFDM_TSBLOCLENL ,0x80}, + {R367_OFDM_TSDLYH ,0x90}, + {R367_OFDM_TSDLYM ,0x68}, + {R367_OFDM_TSDLYL ,0x01}, + {R367_OFDM_TSNPDAV ,0x00}, + {R367_OFDM_TSBUFSTATH ,0x00}, + {R367_OFDM_TSBUFSTATM ,0x00}, + {R367_OFDM_TSBUFSTATL ,0x00}, + {R367_OFDM_TSDEBUGM ,0xcf}, + {R367_OFDM_TSDEBUGL ,0x1e}, + {R367_OFDM_TSDLYSETH ,0x00}, + {R367_OFDM_TSDLYSETM ,0x68}, + {R367_OFDM_TSDLYSETL ,0x00}, + {R367_OFDM_TSOBSCFG ,0x00}, + {R367_OFDM_TSOBSM ,0x47}, + {R367_OFDM_TSOBSL ,0x1f}, + {R367_OFDM_ERRCTRL1 ,0x95}, + {R367_OFDM_ERRCNT1H ,0x80}, + {R367_OFDM_ERRCNT1M ,0x00}, + {R367_OFDM_ERRCNT1L ,0x00}, + {R367_OFDM_ERRCTRL2 ,0x95}, + {R367_OFDM_ERRCNT2H ,0x00}, + {R367_OFDM_ERRCNT2M ,0x00}, + {R367_OFDM_ERRCNT2L ,0x00}, + {R367_OFDM_FECSPY ,0x88}, + {R367_OFDM_FSPYCFG ,0x2c}, + {R367_OFDM_FSPYDATA ,0x3a}, + {R367_OFDM_FSPYOUT ,0x06}, + {R367_OFDM_FSTATUS ,0x61}, + {R367_OFDM_FGOODPACK ,0xff}, + {R367_OFDM_FPACKCNT ,0xff}, + {R367_OFDM_FSPYMISC ,0x66}, + {R367_OFDM_FBERCPT4 ,0x00}, + {R367_OFDM_FBERCPT3 ,0x00}, + {R367_OFDM_FBERCPT2 ,0x36}, + {R367_OFDM_FBERCPT1 ,0x36}, + {R367_OFDM_FBERCPT0 ,0x14}, + {R367_OFDM_FBERERR2 ,0x00}, + {R367_OFDM_FBERERR1 ,0x03}, + {R367_OFDM_FBERERR0 ,0x28}, + {R367_OFDM_FSTATESM ,0x00}, + {R367_OFDM_FSTATESL ,0x02}, + {R367_OFDM_FSPYBER ,0x00}, + {R367_OFDM_FSPYDISTM ,0x01}, + {R367_OFDM_FSPYDISTL ,0x9f}, + {R367_OFDM_FSPYOBS7 ,0xc9}, + {R367_OFDM_FSPYOBS6 ,0x99}, + {R367_OFDM_FSPYOBS5 ,0x08}, + {R367_OFDM_FSPYOBS4 ,0xec}, + {R367_OFDM_FSPYOBS3 ,0x01}, + {R367_OFDM_FSPYOBS2 ,0x0f}, + {R367_OFDM_FSPYOBS1 ,0xf5}, + {R367_OFDM_FSPYOBS0 ,0x08}, + {R367_OFDM_SFDEMAP ,0x40}, + {R367_OFDM_SFERROR ,0x00}, + {R367_OFDM_SFAVSR ,0x30}, + {R367_OFDM_SFECSTATUS ,0xcc}, + {R367_OFDM_SFKDIV12 ,0x20}, + {R367_OFDM_SFKDIV23 ,0x40}, + {R367_OFDM_SFKDIV34 ,0x20}, + {R367_OFDM_SFKDIV56 ,0x20}, + {R367_OFDM_SFKDIV67 ,0x00}, + {R367_OFDM_SFKDIV78 ,0x20}, + {R367_OFDM_SFDILSTKM ,0x00}, + {R367_OFDM_SFDILSTKL ,0x00}, + {R367_OFDM_SFSTATUS ,0xb5}, + {R367_OFDM_SFDLYH ,0x90}, + {R367_OFDM_SFDLYM ,0x60}, + {R367_OFDM_SFDLYL ,0x01}, + {R367_OFDM_SFDLYSETH ,0xc0}, + {R367_OFDM_SFDLYSETM ,0x60}, + {R367_OFDM_SFDLYSETL ,0x00}, + {R367_OFDM_SFOBSCFG ,0x00}, + {R367_OFDM_SFOBSM ,0x47}, + {R367_OFDM_SFOBSL ,0x05}, + {R367_OFDM_SFECINFO ,0x40}, + {R367_OFDM_SFERRCTRL ,0x74}, + {R367_OFDM_SFERRCNTH ,0x80}, + {R367_OFDM_SFERRCNTM ,0x00}, + {R367_OFDM_SFERRCNTL ,0x00}, + {R367_OFDM_SYMBRATEM ,0x2f}, + {R367_OFDM_SYMBRATEL ,0x50}, + {R367_OFDM_SYMBSTATUS ,0x7f}, + {R367_OFDM_SYMBCFG ,0x00}, + {R367_OFDM_SYMBFIFOM ,0xf4}, + {R367_OFDM_SYMBFIFOL ,0x0d}, + {R367_OFDM_SYMBOFFSM ,0xf0}, + {R367_OFDM_SYMBOFFSL ,0x2d}, + //{R367_OFDM_DEBUG_LT4 ,0x00}, + //{R367_OFDM_DEBUG_LT5 ,0x00}, + //{R367_OFDM_DEBUG_LT6 ,0x00}, + //{R367_OFDM_DEBUG_LT7 ,0x00}, + //{R367_OFDM_DEBUG_LT8 ,0x00}, + //{R367_OFDM_DEBUG_LT9 ,0x00}, + { 0x0000, 0x00 } // EOT +}; + +static inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; + + tmp64 = (u64)a * (u64)b; + do_div(tmp64, c); + + return (u32) tmp64; +} + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = + {.addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk("stv0367: i2c_write error\n"); + return -1; + } + return 0; +} + +#if 0 +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, + .buf = msg, .len = len}, + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { + printk("stv0367: i2c_read error\n"); + return -1; + } + return 0; +} +#endif + +static int writereg(struct stv_state *state, u16 reg, u8 dat) +{ + u8 mm[3] = { (reg >> 8), reg & 0xff, dat }; + + return i2c_write(state->i2c, state->adr, mm, 3); +} + +static int readreg(struct stv_state *state, u16 reg, u8 *val) +{ + u8 msg[2] = {reg >> 8, reg & 0xff}; + struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, + .buf = msg, .len = 2}, + {.addr = state->adr, .flags = I2C_M_RD, + .buf = val, .len = 1}}; + return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; +} + +static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) +{ + u8 msg[2] = {reg >> 8, reg & 0xff}; + struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, + .buf = msg, .len = 2}, + {.addr = state->adr, .flags = I2C_M_RD, + .buf = val, .len = count}}; + return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; +} + +static int write_init_table(struct stv_state *state, struct init_table *tab) +{ + while (1) { + if (!tab->adr) + break; + if (writereg(state, tab->adr, tab->data) < 0) + return -1; + tab++; + } + return 0; +} + +static int qam_set_modulation(struct stv_state *state) +{ + int stat = 0; + + switch(state->modulation) { + case QAM_16: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0x90); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); + writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); + break; + case QAM_32: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0xb0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); + writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); + break; + case QAM_64: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ + if(state->symbol_rate>4500000) + { + writereg(state, R367_QAM_FSM_STATE,0xb0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); + } + else if(state->symbol_rate>2500000) // 25000000 + { + writereg(state, R367_QAM_FSM_STATE,0xa0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); + } + else + { + writereg(state, R367_QAM_FSM_STATE,0xa0); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + } + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); + writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); + break; + case QAM_128: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0x90); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); + if(state->symbol_rate>4500000) // 45000000 + { + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + } + else if(state->symbol_rate>2500000) // 25000000 + { + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); + } + else + { + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); + } + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); + writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); + break; + case QAM_256: + writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); + writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ + writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ + writereg(state, R367_QAM_FSM_STATE,0xa0); + if(state->symbol_rate>4500000) // 45000000 + { + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + } + else if(state->symbol_rate>2500000) // 25000000 + { + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); + } + else + { + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); + } + writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); + writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); + writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); + writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); + break; + default: + stat = -EINVAL; + break; + } + return stat; +} + + +static int QAM_SetSymbolRate(struct stv_state *state) +{ + int status = 0; + u32 sr = state->symbol_rate; + u32 Corr = 0; + u32 Temp, Temp1, AdpClk; + + switch(state->modulation) { + default: + case QAM_16: Corr = 1032; break; + case QAM_32: Corr = 954; break; + case QAM_64: Corr = 983; break; + case QAM_128: Corr = 957; break; + case QAM_256: Corr = 948; break; + } + + // Transfer ration + Temp = (256*sr) / state->adc_clock; + writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); + + /* Symbol rate and SRC gain calculation */ + AdpClk = (state->master_clock) / 2000; /* TRL works at half the system clock */ + + Temp = state->symbol_rate; + Temp1 = sr; + + if(sr < 2097152) /* 2097152 = 2^21 */ + { + Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; + Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; + } + else if(sr < 4194304) /* 4194304 = 2**22 */ + { + Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; + Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; + } + else if(sr < 8388608) /* 8388608 = 2**23 */ + { + Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; + Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; + } + else + { + Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; + Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; + } + + ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ + //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! + //{ + // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); + //} + ///* AllPass filter is never used on this IC */ + //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! + + writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); + writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); + writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); + writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); + + writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); + writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); + return status; +} + + +static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) +{ + int status = 0; + u32 Sampled_IF; + + do { + //if (DerotFrequency < 1000000) + // DerotFrequency = state->adc_clock/4; /* ZIF operation */ + if (DerotFrequency > state->adc_clock) + DerotFrequency = DerotFrequency - state->adc_clock; // User Alias + + Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; + if(Sampled_IF > 8388607) + Sampled_IF = 8388607; + + writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); + writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); + writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); + } while(0); + + return status; +} + + + +static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) +{ + int status = 0; + u32 AGCTimeOut = 25; + u32 TRLTimeOut = 100000000 / state->symbol_rate; + u32 CRLSymbols = 0; + u32 EQLTimeOut = 100; + u32 SearchRange = state->symbol_rate / 25; + u32 CRLTimeOut; + u8 Temp; + + if( state->demod_state != QAMSet ) { + writereg(state, R367_DEBUG_LT4,0x00); + writereg(state, R367_DEBUG_LT5,0x01); + writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 + writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 + writereg(state, R367_DEBUG_LT8,0x00); + writereg(state, R367_DEBUG_LT9,0x00); + + // Tuner Setup + writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ + writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ + + // Clock setup + writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ + writereg(state, R367_TOPCTRL,0x10); // Set QAM + + writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV,232); + writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ + + msleep(50); + writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ + + state->master_clock = 58000000; + state->adc_clock = 58000000; + + state->demod_state = QAMSet; + } + + state->m_bFirstTimeLock = true; + state->m_DemodLockTime = -1; + + qam_set_modulation(state); + QAM_SetSymbolRate(state); + + // Will make problems on low symbol rates ( < 2500000 ) + + switch(state->modulation) { + default: + case QAM_16: CRLSymbols = 150000; break; + case QAM_32: CRLSymbols = 250000; break; + case QAM_64: CRLSymbols = 200000; break; + case QAM_128: CRLSymbols = 250000; break; + case QAM_256: CRLSymbols = 250000; break; + } + + CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); + CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; + if( CRLTimeOut < 50 ) CRLTimeOut = 50; + + state->m_FECTimeOut = 20; + state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; + state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; + + // QAM_AGC_ACCUMRSTSEL = 0; + readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); + writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); + + // QAM_MODULUSMAP_EN = 0 + readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); + writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); + + // QAM_SWEEP_EN = 0 + readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); + writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); + + QAM_SetDerotFrequency(state, IntermediateFrequency); + + // Release TRL + writereg(state, R367_QAM_CTRL_1,0x00); + + state->IF = IntermediateFrequency; + state->demod_state = QAMStarted; + + return status; +} + +static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) +{ + int status = 0; + u8 GAIN_SRC1; + u32 Derot; + u8 SYR_CTL; + u8 tmp1; + u8 tmp2; + + if ( state->demod_state != OFDMSet ) { + // QAM Disable + writereg(state, R367_DEBUG_LT4, 0x00); + writereg(state, R367_DEBUG_LT5, 0x00); + writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 + writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 + writereg(state, R367_DEBUG_LT8, 0x00); + writereg(state, R367_DEBUG_LT9, 0x00); + + // Tuner Setup + writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ + writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ + + // Clock setup + writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ + writereg(state, R367_TOPCTRL, 0x00); // Set OFDM + + writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV, 8); + writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ + + msleep(50); + writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ + + state->master_clock = 54000000; + state->adc_clock = 54000000; + + state->demod_state = OFDMSet; + } + + state->m_bFirstTimeLock = true; + state->m_DemodLockTime = -1; + + // Set inversion in GAIN_SRC1 (fixed from init) + // is in GAIN_SRC1, see below + + GAIN_SRC1 = 0xA0; + // Bandwidth + + // Fixed values for 54 MHz + switch(state->bandwidth) { + case 0: + case 8000000: + // Normrate = 44384; + writereg(state, R367_OFDM_TRL_CTL,0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); + writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); + // Gain SRC = 2774 + writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); + writereg(state, R367_OFDM_GAIN_SRC2,0xD6); + break; + case 7000000: + // Normrate = 38836; + writereg(state, R367_OFDM_TRL_CTL,0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); + writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); + // Gain SRC = 2427 + writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); + writereg(state, R367_OFDM_GAIN_SRC2,0x7B); + break; + case 6000000: + // Normrate = 33288; + writereg(state, R367_OFDM_TRL_CTL,0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); + writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); + // Gain SRC = 2080 + writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); + writereg(state, R367_OFDM_GAIN_SRC2,0x20); + break; + default: + return -EINVAL; + break; + } + + Derot = ((IntermediateFrequency / 1000) * 65536) / (state->master_clock / 1000); + + writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); + writereg(state, R367_OFDM_INC_DEROT2,(Derot)); + + readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); + SYR_CTL &= ~0x78; + writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 + + + writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 + SYR_CTL &= 0x01; + writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 + + msleep(5); + + writereg(state, R367_OFDM_COR_CTL,0x20); // Start core + + // -- Begin M.V. + // Reset FEC and Read Solomon + readreg(state, R367_OFDM_SFDLYSETH,&tmp1); + readreg(state, R367_TSGENERAL,&tmp2); + writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); + writereg(state, R367_TSGENERAL,tmp2 | 0x01); + // -- End M.V. + + state->m_SignalTimeOut = 200; + state->IF = IntermediateFrequency; + state->demod_state = OFDMStarted; + state->m_DemodTimeOut = 0; + state->m_FECTimeOut = 0; + state->m_TSTimeOut = 0; + + return status; +} + +#if 0 +static int Stop(struct stv_state *state) +{ + int status = 0; + + switch(state->demod_state) + { + case QAMStarted: + status = writereg(state, R367_QAM_CTRL_1,0x06); + state->demod_state = QAMSet; + break; + case OFDMStarted: + status = writereg(state, R367_OFDM_COR_CTL,0x00); + state->demod_state = OFDMSet; + break; + default: + break; + } + return status; +} +#endif + +static s32 Log10x100(u32 x) +{ + static u32 LookupTable[100] = { + 101157945, 103514217, 105925373, 108392691, 110917482, + 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 + 127350308, 130316678, 133352143, 136458314, 139636836, + 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 + 160324539, 164058977, 167880402, 171790839, 175792361, + 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 + 201836636, 206538016, 211348904, 216271852, 221309471, + 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 + 254097271, 260015956, 266072506, 272270131, 278612117, + 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 + 319889511, 327340695, 334965439, 342767787, 350751874, + 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 + 402717034, 412097519, 421696503, 431519077, 441570447, + 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 + 506990708, 518800039, 530884444, 543250331, 555904257, + 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 + 638263486, 653130553, 668343918, 683911647, 699841996, + 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 + 803526122, 822242650, 841395142, 860993752, 881048873, + 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 + }; + s32 y; + int i; + + if (x == 0) + return 0; + y = 800; + if (x >= 1000000000) { + x /= 10; + y += 100; + } + + while (x < 100000000) { + x *= 10; + y -= 100; + } + i = 0; + while (i < 100 && x > LookupTable[i]) + i += 1; + y += i; + return y; +} + +static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) +{ + u32 RegValAvg = 0; + u8 RegVal[2]; + int status = 0, i; + + *pSignalToNoise = 0; + for (i = 0; i < 10; i += 1 ) { + readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); + RegValAvg += RegVal[0] + 256 * RegVal[1]; + } + if (RegValAvg != 0) { + s32 Power = 1; + switch(state->modulation) { + case QAM_16: + Power = 20480; + break; + case QAM_32: + Power = 23040; + break; + case QAM_64: + Power = 21504; + break; + case QAM_128: + Power = 23616; + break; + case QAM_256: + Power = 21760; + break; + default: + break; + } + *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); + } else { + *pSignalToNoise = 380; + } + return status; +} + +static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) +{ + u8 CHC_SNR = 0; + + int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); + if (status >= 0) { + // Note: very unclear documentation on this. + // Datasheet states snr = CHC_SNR/4 dB -> way to high values! + // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values + // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 + // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best + *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; + } + //printk("SNR %d\n", *pSignalToNoise); + return status; +} + +#if 0 +static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) +{ + *pQuality = 100; + return 0; +}; + +static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) +{ + static s32 QE_SN[] = { + 51, // QPSK 1/2 + 69, // QPSK 2/3 + 79, // QPSK 3/4 + 89, // QPSK 5/6 + 97, // QPSK 7/8 + 108, // 16-QAM 1/2 + 131, // 16-QAM 2/3 + 146, // 16-QAM 3/4 + 156, // 16-QAM 5/6 + 160, // 16-QAM 7/8 + 165, // 64-QAM 1/2 + 187, // 64-QAM 2/3 + 202, // 64-QAM 3/4 + 216, // 64-QAM 5/6 + 225, // 64-QAM 7/8 + }; + u8 TPS_Received[2]; + int Constellation; + int CodeRate; + s32 SignalToNoiseRel, BERQuality; + + *pQuality = 0; + readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); + Constellation = TPS_Received[0] & 0x03; + CodeRate = TPS_Received[1] & 0x07; + + if( Constellation > 2 || CodeRate > 5 ) + return -1; + SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; + BERQuality = 100; + + if( SignalToNoiseRel < -70 ) + *pQuality = 0; + else if( SignalToNoiseRel < 30 ) { + *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; + } else + *pQuality = BERQuality; + return 0; +}; + +static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) +{ + s32 SignalToNoiseRel = 0; + s32 Quality = 0; + s32 BERQuality = 100; + + switch(state->modulation) { + case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; + case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig + case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; + case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; + case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; + } + + if( SignalToNoiseRel < -70 ) Quality = 0; + else if( SignalToNoiseRel < 30 ) + { + Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; + } + else + Quality = BERQuality; + + return Quality; +} + +static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) +{ + *pQuality = 0; + switch(state->demod_state) + { + case QAMStarted: + *pQuality = DVBCQuality(state, SignalToNoise); + break; + case OFDMStarted: + return DVBT_GetQuality(state, SignalToNoise, pQuality); + } + return 0; +}; +#endif + +static int attach_init(struct stv_state *state) +{ + int stat = 0; + + stat = readreg(state, R367_ID, &state->ID); + if ( stat < 0 || state->ID != 0x60 ) + return -ENODEV; + printk("stv0367 found\n"); + + writereg(state, R367_TOPCTRL, 0x10); + write_init_table(state, base_init); + write_init_table(state, qam_init); + + writereg(state, R367_TOPCTRL, 0x00); + write_init_table(state, ofdm_init); + + writereg(state, R367_OFDM_GAIN_SRC1, 0x2A); + writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); + writereg(state, R367_OFDM_INC_DEROT1, 0x55); + writereg(state, R367_OFDM_INC_DEROT2, 0x55); + writereg(state, R367_OFDM_TRL_CTL, 0x14); + writereg(state, R367_OFDM_TRL_NOMRATE1, 0xAE); + writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); + writereg(state, R367_OFDM_FEPATH_CFG, 0x0); + + // OFDM TS Setup + + writereg(state, R367_OFDM_TSCFGH, 0x70); + writereg(state, R367_OFDM_TSCFGM, 0xC0); + writereg(state, R367_OFDM_TSCFGL, 0x20); + writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz + //writereg(state, R367_TSTBUS, 0x80); // Invert CLK + + writereg(state, R367_OFDM_TSCFGH, 0x71); + writereg(state, R367_OFDM_TSCFGH, 0x70); + + writereg(state, R367_TOPCTRL, 0x10); + + // Also needed for QAM + writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup + + writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // + + // QAM TS setup, note exact format also depends on descrambler settings + writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial + // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // + + // Clock setup + writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ + + if( state->master_clock == 58000000 ) { + writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV,232); + } else { + writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ + writereg(state, R367_PLLNDIV,8); + } + writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ + + // Tuner setup + writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ + writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ + + writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ + writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ + writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ + writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ + + writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ + + writereg(state, R367_I2CRPT, state->I2CRPT); + state->demod_state = QAMSet; + return stat; +} + +#ifdef USE_API3 +static void c_release(struct dvb_frontend* fe) +#else +static void release(struct dvb_frontend* fe) +#endif +{ + struct stv_state *state=fe->demodulator_priv; + printk("%s\n", __FUNCTION__); + kfree(state); +} + +#ifdef USE_API3 +static int c_init (struct dvb_frontend *fe) +{ + struct stv_state *state=fe->demodulator_priv; + + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + state->omode = OM_DVBC; + return 0; +} + +static int c_sleep(struct dvb_frontend* fe) +{ + struct stv_state *state=fe->demodulator_priv; + + mutex_unlock(&state->ctlock); + return 0; +} +#endif + +static int gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct stv_state *state = fe->demodulator_priv; + u8 i2crpt = state->I2CRPT & ~0x80; + + if (enable) + i2crpt |= 0x80; + if (writereg(state, R367_I2CRPT, i2crpt) < 0) + return -1; + state->I2CRPT = i2crpt; + return 0; +} + +#if 0 +static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + return DVBFE_ALGO_SEARCH_AGAIN; +} +#endif + +#if 0 +int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); +int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); +#endif + +static int ofdm_lock(struct stv_state *state) +{ + int status = 0; + u8 OFDM_Status; + s32 DemodTimeOut = 10; + s32 FECTimeOut = 0; + s32 TSTimeOut = 0; + u8 CPAMPMin = 255; + u8 CPAMPValue; + u8 SYR_STAT; + u8 FFTMode; + u8 TSStatus; + + msleep(state->m_SignalTimeOut); + readreg(state, R367_OFDM_STATUS,&OFDM_Status); + + if (!(OFDM_Status & 0x40)) + return -1; + //printk("lock 1\n"); + + readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); + FFTMode = (SYR_STAT & 0x0C) >> 2; + + switch(FFTMode) + { + case 0: // 2K + DemodTimeOut = 10; + FECTimeOut = 150; + TSTimeOut = 125; + CPAMPMin = 20; + break; + case 1: // 8K + DemodTimeOut = 55; + FECTimeOut = 600; + TSTimeOut = 500; + CPAMPMin = 80; + break; + case 2: // 4K + DemodTimeOut = 40; + FECTimeOut = 300; + TSTimeOut = 250; + CPAMPMin = 30; + break; + } + state->m_OFDM_FFTMode = FFTMode; + readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); + msleep(DemodTimeOut); + { + // Release FEC and Read Solomon Reset + u8 tmp1; + u8 tmp2; + readreg(state, R367_OFDM_SFDLYSETH,&tmp1); + readreg(state, R367_TSGENERAL,&tmp2); + writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); + writereg(state, R367_TSGENERAL,tmp2 & ~0x01); + } + msleep(FECTimeOut); + if( (OFDM_Status & 0x98) != 0x98 ) + ;//return -1; + //printk("lock 2\n"); + + { + u8 Guard = (SYR_STAT & 0x03); + if(Guard < 2) + { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER + } else { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER + } + + // apply Sfec workaround if 8K 64QAM CR!=1/2 + if( FFTMode == 1) + { + u8 tmp[2]; + readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); + if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) + { + writereg(state, R367_OFDM_SFDLYSETH,0xc0); + writereg(state, R367_OFDM_SFDLYSETM,0x60); + writereg(state, R367_OFDM_SFDLYSETL,0x00); + } + else + { + writereg(state, R367_OFDM_SFDLYSETH,0x00); + } + } + } + msleep(TSTimeOut); + readreg(state, R367_OFDM_TSSTATUS,&TSStatus); + if( (TSStatus & 0x80) != 0x80 ) + return -1; + //printk("lock 3\n"); + return status; +} + + +#ifdef USE_API3 +static int set_parameters(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + int stat; + struct stv_state *state = fe->demodulator_priv; + u32 OF = 0; + u32 IF; + + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe, p); + + switch (state->omode) { + case OM_DVBC: + case OM_QAM_ITU_C: + state->modulation = p->u.qam.modulation; + state->symbol_rate = p->u.qam.symbol_rate; + break; + case OM_DVBT: + switch (p->u.ofdm.bandwidth) { + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + state->bandwidth = 8000000; + break; + case BANDWIDTH_7_MHZ: + state->bandwidth = 7000000; + break; + case BANDWIDTH_6_MHZ: + state->bandwidth = 6000000; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } +#else +static int set_parameters(struct dvb_frontend *fe) +{ + int stat; + struct stv_state *state = fe->demodulator_priv; + u32 OF = 0; + u32 IF; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: + state->omode = OM_DVBC; + /* symbol rate 0 might cause an oops */ + if (fe->dtv_property_cache.symbol_rate == 0) { + printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); + return -EINVAL; + } + break; + case SYS_DVBT: + state->omode = OM_DVBT; + break; + default: + return -EINVAL; + } + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe); + state->modulation = fe->dtv_property_cache.modulation; + state->symbol_rate = fe->dtv_property_cache.symbol_rate; + state->bandwidth = fe->dtv_property_cache.bandwidth_hz; +#endif + fe->ops.tuner_ops.get_if_frequency(fe, &IF); + //fe->ops.tuner_ops.get_frequency(fe, &IF); + + switch(state->omode) { + case OM_DVBT: + stat = OFDM_Start(state, OF, IF); + ofdm_lock(state); + break; + case OM_DVBC: + case OM_QAM_ITU_C: + stat = QAM_Start(state, OF, IF); + break; + default: + stat = -EINVAL; + } + //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); + return stat; +} + +#if 0 +static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct stv_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) +{ + int status = STATUS_SUCCESS; + u8 OFDM_Status; + s32 DemodTimeOut = 0; + s32 FECTimeOut = 0; + s32 TSTimeOut = 0; + u8 CPAMPMin = 255; + u8 CPAMPValue; + bool SYRLock; + u8 SYR_STAT; + u8 FFTMode; + u8 TSStatus; + + readreg(state, R367_OFDM_STATUS,&OFDM_Status); + + SYRLock = (OFDM_Status & 0x40) != 0; + + if( Time > m_SignalTimeOut && !SYRLock ) + { + *pLockStatus = NEVER_LOCK; + break; + } + + if( !SYRLock ) break; + + *pLockStatus = SIGNAL_PRESENT; + + // Check Mode + + readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); + FFTMode = (SYR_STAT & 0x0C) >> 2; + + switch(FFTMode) + { + case 0: // 2K + DemodTimeOut = 10; + FECTimeOut = 150; + TSTimeOut = 125; + CPAMPMin = 20; + break; + case 1: // 8K + DemodTimeOut = 55; + FECTimeOut = 600; + TSTimeOut = 500; + CPAMPMin = 80; + break; + case 2: // 4K + DemodTimeOut = 40; + FECTimeOut = 300; + TSTimeOut = 250; + CPAMPMin = 30; + break; + } + + m_OFDM_FFTMode = FFTMode; + + if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) + { + m_DemodTimeOut = Time + DemodTimeOut; + //break; + } + + readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); + + if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) + { + break; + } + + if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) + { + // initiate retry + *pLockStatus = NEVER_LOCK; + break; + } + + if( CPAMPValue < CPAMPMin ) break; + + *pLockStatus = DEMOD_LOCK; + + if( m_FECTimeOut == 0 && m_bFirstTimeLock ) + { + // Release FEC and Read Solomon Reset + u8 tmp1; + u8 tmp2; + readreg(state, R367_OFDM_SFDLYSETH,&tmp1); + readreg(state, R367_TSGENERAL,&tmp2); + writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); + writereg(state, R367_TSGENERAL,tmp2 & ~0x01); + + m_FECTimeOut = Time + FECTimeOut; + } + + // Wait for TSP_LOCK, LK, PRF + if( (OFDM_Status & 0x98) != 0x98 ) + { + if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; + break; + } + + if( m_bFirstTimeLock && m_TSTimeOut == 0) + { + u8 Guard = (SYR_STAT & 0x03); + if(Guard < 2) + { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER + } else { + u8 tmp; + readreg(state, R367_OFDM_SYR_CTL,&tmp); + writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN + readreg(state, R367_OFDM_SYR_UPDATE,&tmp); + writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER + } + + // apply Sfec workaround if 8K 64QAM CR!=1/2 + if( FFTMode == 1) + { + u8 tmp[2]; + readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); + if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) + { + writereg(state, R367_OFDM_SFDLYSETH,0xc0); + writereg(state, R367_OFDM_SFDLYSETM,0x60); + writereg(state, R367_OFDM_SFDLYSETL,0x00); + } + else + { + writereg(state, R367_OFDM_SFDLYSETH,0x00); + } + } + + m_TSTimeOut = Time + TSTimeOut; + } + readreg(state, R367_OFDM_TSSTATUS,&TSStatus); + if( (TSStatus & 0x80) != 0x80 ) + { + if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; + break; + } + *pLockStatus = MPEG_LOCK; + m_bFirstTimeLock = false; + return status; +} + +#endif + +static int read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct stv_state *state = fe->demodulator_priv; + *status=0; + + switch(state->demod_state) { + case QAMStarted: + { + u8 FEC_Lock; + u8 QAM_Lock; + + readreg(state, R367_QAM_FSM_STS, &QAM_Lock); + QAM_Lock &= 0x0F; + if (QAM_Lock >10) + *status|=0x07; + readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); + if (FEC_Lock&2) + *status|=0x1f; + if (state->m_bFirstTimeLock) { + state->m_bFirstTimeLock = false; + // QAM_AGC_ACCUMRSTSEL to Tracking; + writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); + } + break; + } + case OFDMStarted: + { + u8 OFDM_Status; + u8 TSStatus; + + readreg(state, R367_OFDM_TSSTATUS, &TSStatus); + + readreg(state, R367_OFDM_STATUS, &OFDM_Status); + if (OFDM_Status & 0x40) + *status |= FE_HAS_SIGNAL; + + if ((OFDM_Status & 0x98) == 0x98) + *status|=0x0f; + + if (TSStatus & 0x80) + *status |= 0x1f; + break; + } + default: + break; + } + return 0; +} + +static int read_ber_ter(struct dvb_frontend *fe, u32 *ber) +{ + struct stv_state *state = fe->demodulator_priv; + u32 err; + u8 cnth, cntm, cntl; + +#if 1 + readreg(state, R367_OFDM_SFERRCNTH, &cnth); + + if (cnth & 0x80) { + *ber = state->ber; + return 0; + } + + readreg(state, R367_OFDM_SFERRCNTM, &cntm); + readreg(state, R367_OFDM_SFERRCNTL, &cntl); + + err = ((cnth & 0x7f) << 16) | (cntm << 8) | cntl; + +#if 0 + { + u64 err64; + err64 = (u64) err; + err64 *= 1000000000ULL; + err64 >>= 21; + err = err64; + } +#endif +#else + readreg(state, R367_OFDM_ERRCNT1HM, &cnth); + +#endif + *ber = state->ber = err; + return 0; +} + +static int read_ber_cab(struct dvb_frontend *fe, u32 *ber) +{ + struct stv_state *state = fe->demodulator_priv; + u32 err; + u8 cntm, cntl, ctrl; + + readreg(state, R367_QAM_BERT_1, &ctrl); + if (!(ctrl & 0x20)) { + readreg(state, R367_QAM_BERT_2, &cntl); + readreg(state, R367_QAM_BERT_3, &cntm); + err = (cntm << 8) | cntl; + //printk("err %04x\n", err); + state->ber = err; + writereg(state, R367_QAM_BERT_1, 0x27); + } + *ber = (u32) state->ber; + return 0; +} + +static int read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct stv_state *state = fe->demodulator_priv; + + if (state->demod_state == QAMStarted) + return read_ber_cab(fe, ber); + if (state->demod_state == OFDMStarted) + return read_ber_ter(fe, ber); + *ber = 0; + return 0; +} + +static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + if (fe->ops.tuner_ops.get_rf_strength) + fe->ops.tuner_ops.get_rf_strength(fe, strength); + else + *strength = 0; + return 0; +} + +static int read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct stv_state *state = fe->demodulator_priv; + s32 snr2 = 0; + + switch(state->demod_state) { + case QAMStarted: + QAM_GetSignalToNoise(state, &snr2); + break; + case OFDMStarted: + OFDM_GetSignalToNoise(state, &snr2); + break; + default: + break; + } + *snr = snr2&0xffff; + return 0; +} + +static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct stv_state *state = fe->demodulator_priv; + u8 errl, errm, errh; + u8 val; + + switch(state->demod_state) { + case QAMStarted: + readreg(state, R367_QAM_RS_COUNTER_4, &errl); + readreg(state, R367_QAM_RS_COUNTER_5, &errm); + *ucblocks = (errm << 8) | errl; + break; + case OFDMStarted: + readreg(state, R367_OFDM_SFERRCNTH, &val); + if ((val & 0x80) == 0) { + readreg(state, R367_OFDM_ERRCNT1H, &errh); + readreg(state, R367_OFDM_ERRCNT1M, &errl); + readreg(state, R367_OFDM_ERRCNT1L, &errm); + state->ucblocks = (errh <<16) | (errm << 8) | errl; + } + *ucblocks = state->ucblocks; + break; + default: + *ucblocks = 0; + break; + } + return 0; +} + +static int c_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + sets->min_delay_ms=3000; + sets->max_drift=0; + sets->step_size=0; + return 0; +} + +#ifndef USE_API3 +static int get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + return c_get_tune_settings(fe, sets); + default: + /* DVB-T: Use info.frequency_stepsize. */ + return -EINVAL; + } +} +#endif + +#ifdef USE_API3 +static void t_release(struct dvb_frontend* fe) +{ + //struct stv_state *state=fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + //kfree(state); +} + +static int t_init (struct dvb_frontend *fe) +{ + struct stv_state *state=fe->demodulator_priv; + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + state->omode = OM_DVBT; + return 0; +} + +static int t_sleep(struct dvb_frontend* fe) +{ + struct stv_state *state=fe->demodulator_priv; + mutex_unlock(&state->ctlock); + return 0; +} +#endif + +#if 0 +static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct stv_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static enum dvbfe_algo algo(struct dvb_frontend *fe) +{ + return DVBFE_ALGO_CUSTOM; +} +#endif + +#ifdef USE_API3 +static struct dvb_frontend_ops c_ops = { + .info = { + .name = "STV0367 DVB-C", + .type = FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 47000000, + .frequency_max = 862000000, + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO + }, + .release = c_release, + .init = c_init, + .sleep = c_sleep, + .i2c_gate_ctrl = gate_ctrl, + + .get_tune_settings = c_get_tune_settings, + + .read_status = read_status, + .read_ber = read_ber, + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, + +#if 1 + .set_frontend = set_parameters, +#else + .get_frontend_algo = algo, + .search = search, +#endif +}; + +static struct dvb_frontend_ops t_ops = { + .info = { + .name = "STV0367 DVB-T", + .type = FE_OFDM, + .frequency_min = 47125000, + .frequency_max = 865000000, + .frequency_stepsize = 166667, + .frequency_tolerance = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | + FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | + FE_CAN_MUTE_TS + }, + .release = t_release, + .init = t_init, + .sleep = t_sleep, + .i2c_gate_ctrl = gate_ctrl, + + .set_frontend = set_parameters, + + .read_status = read_status, + .read_ber = read_ber, + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, +}; + +#else + +static struct dvb_frontend_ops common_ops = { + .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, + .info = { + .name = "STV0367 DVB-C DVB-T", + .frequency_stepsize = 166667, /* DVB-T only */ + .frequency_min = 47000000, /* DVB-T: 47125000 */ + .frequency_max = 865000000, /* DVB-C: 862000000 */ + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = /* DVB-C */ + FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | + FE_CAN_FEC_AUTO | + /* DVB-T */ + FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS + }, + .release = release, + .i2c_gate_ctrl = gate_ctrl, + + .get_tune_settings = get_tune_settings, + + .set_frontend = set_parameters, + + .read_status = read_status, + .read_ber = read_ber, + .read_signal_strength = read_signal_strength, + .read_snr = read_snr, + .read_ucblocks = read_ucblocks, +}; +#endif + + +static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) +{ + u32 ulENARPTLEVEL = 5; + u32 ulQAMInversion = 2; + state->omode = OM_NONE; + state->adr = cfg->adr; + + mutex_init(&state->mutex); + mutex_init(&state->ctlock); + +#ifdef USE_API3 + memcpy(&state->c_frontend.ops, &c_ops, sizeof(struct dvb_frontend_ops)); + memcpy(&state->t_frontend.ops, &t_ops, sizeof(struct dvb_frontend_ops)); + state->c_frontend.demodulator_priv = state; + state->t_frontend.demodulator_priv = state; +#else + memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); + state->frontend.demodulator_priv = state; +#endif + + state->master_clock = 58000000; + state->adc_clock = 58000000; + state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); + state->qam_inversion = ((ulQAMInversion & 3) << 6 ); + state->demod_state = Off; +} + + +struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, + struct dvb_frontend **fe_t) +{ + struct stv_state *state = NULL; + + state = kzalloc(sizeof(struct stv_state), GFP_KERNEL); + if (!state) + return NULL; + + state->i2c = i2c; + init_state(state, cfg); + + if (attach_init(state)<0) + goto error; +#ifdef USE_API3 + *fe_t = &state->t_frontend; + return &state->c_frontend; +#else + return &state->frontend; +#endif + +error: + printk("stv0367: not found\n"); + kfree(state); + return NULL; +} + + +MODULE_DESCRIPTION("STV0367DD driver"); +MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(stv0367_attach); + + + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,17 @@ +#ifndef _STV0367DD_H_ +#define _STV0367DD_H_ + +#include +#include + +struct stv0367_cfg { + u8 adr; + u32 xtal; + u32 ts_mode; +}; + + +extern struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, + struct stv0367_cfg *cfg, + struct dvb_frontend **fe_t); +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd_regs.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd_regs.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd_regs.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv0367dd_regs.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,3431 @@ +// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions +// Author Manfred Völkel, Februar 2011 +// (c) 2010 DigitalDevices GmbH Germany. All rights reserved + +// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ + +/* ======================================================================= + -- Registers Declaration + -- ------------------------- + -- Each register (R367_XXXXX) is defined by its address (2 bytes). + -- + -- Each field (F367_XXXXX)is defined as follow: + -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] + ======================================================================= */ + +/* ID */ +#define R367_ID 0xF000 +#define F367_IDENTIFICATIONREG 0xF00000FF + +/* I2CRPT */ +#define R367_I2CRPT 0xF001 +#define F367_I2CT_ON 0xF0010080 +#define F367_ENARPT_LEVEL 0xF0010070 +#define F367_SCLT_DELAY 0xF0010008 +#define F367_SCLT_NOD 0xF0010004 +#define F367_STOP_ENABLE 0xF0010002 +#define F367_SDAT_NOD 0xF0010001 + +/* TOPCTRL */ +#define R367_TOPCTRL 0xF002 +#define F367_STDBY 0xF0020080 +#define F367_STDBY_FEC 0xF0020040 +#define F367_STDBY_CORE 0xF0020020 +#define F367_QAM_COFDM 0xF0020010 +#define F367_TS_DIS 0xF0020008 +#define F367_DIR_CLK_216 0xF0020004 +#define F367_TUNER_BB 0xF0020002 +#define F367_DVBT_H 0xF0020001 + +/* IOCFG0 */ +#define R367_IOCFG0 0xF003 +#define F367_OP0_SD 0xF0030080 +#define F367_OP0_VAL 0xF0030040 +#define F367_OP0_OD 0xF0030020 +#define F367_OP0_INV 0xF0030010 +#define F367_OP0_DACVALUE_HI 0xF003000F + +/* DAC0R */ +#define R367_DAC0R 0xF004 +#define F367_OP0_DACVALUE_LO 0xF00400FF + +/* IOCFG1 */ +#define R367_IOCFG1 0xF005 +#define F367_IP0 0xF0050040 +#define F367_OP1_OD 0xF0050020 +#define F367_OP1_INV 0xF0050010 +#define F367_OP1_DACVALUE_HI 0xF005000F + +/* DAC1R */ +#define R367_DAC1R 0xF006 +#define F367_OP1_DACVALUE_LO 0xF00600FF + +/* IOCFG2 */ +#define R367_IOCFG2 0xF007 +#define F367_OP2_LOCK_CONF 0xF00700E0 +#define F367_OP2_OD 0xF0070010 +#define F367_OP2_VAL 0xF0070008 +#define F367_OP1_LOCK_CONF 0xF0070007 + +/* SDFR */ +#define R367_SDFR 0xF008 +#define F367_OP0_FREQ 0xF00800F0 +#define F367_OP1_FREQ 0xF008000F + +/* STATUS */ +#define R367_OFDM_STATUS 0xF009 +#define F367_TPS_LOCK 0xF0090080 +#define F367_SYR_LOCK 0xF0090040 +#define F367_AGC_LOCK 0xF0090020 +#define F367_PRF 0xF0090010 +#define F367_LK 0xF0090008 +#define F367_PR 0xF0090007 + +/* AUX_CLK */ +#define R367_AUX_CLK 0xF00A +#define F367_AUXFEC_CTL 0xF00A00C0 +#define F367_DIS_CKX4 0xF00A0020 +#define F367_CKSEL 0xF00A0018 +#define F367_CKDIV_PROG 0xF00A0006 +#define F367_AUXCLK_ENA 0xF00A0001 + +/* FREESYS1 */ +#define R367_FREESYS1 0xF00B +#define F367_FREE_SYS1 0xF00B00FF + +/* FREESYS2 */ +#define R367_FREESYS2 0xF00C +#define F367_FREE_SYS2 0xF00C00FF + +/* FREESYS3 */ +#define R367_FREESYS3 0xF00D +#define F367_FREE_SYS3 0xF00D00FF + +/* GPIO_CFG */ +#define R367_GPIO_CFG 0xF00E +#define F367_GPIO7_NOD 0xF00E0080 +#define F367_GPIO7_CFG 0xF00E0040 +#define F367_GPIO6_NOD 0xF00E0020 +#define F367_GPIO6_CFG 0xF00E0010 +#define F367_GPIO5_NOD 0xF00E0008 +#define F367_GPIO5_CFG 0xF00E0004 +#define F367_GPIO4_NOD 0xF00E0002 +#define F367_GPIO4_CFG 0xF00E0001 + +/* GPIO_CMD */ +#define R367_GPIO_CMD 0xF00F +#define F367_GPIO7_VAL 0xF00F0008 +#define F367_GPIO6_VAL 0xF00F0004 +#define F367_GPIO5_VAL 0xF00F0002 +#define F367_GPIO4_VAL 0xF00F0001 + +/* AGC2MAX */ +#define R367_OFDM_AGC2MAX 0xF010 +#define F367_OFDM_AGC2_MAX 0xF01000FF + +/* AGC2MIN */ +#define R367_OFDM_AGC2MIN 0xF011 +#define F367_OFDM_AGC2_MIN 0xF01100FF + +/* AGC1MAX */ +#define R367_OFDM_AGC1MAX 0xF012 +#define F367_OFDM_AGC1_MAX 0xF01200FF + +/* AGC1MIN */ +#define R367_OFDM_AGC1MIN 0xF013 +#define F367_OFDM_AGC1_MIN 0xF01300FF + +/* AGCR */ +#define R367_OFDM_AGCR 0xF014 +#define F367_OFDM_RATIO_A 0xF01400E0 +#define F367_OFDM_RATIO_B 0xF0140018 +#define F367_OFDM_RATIO_C 0xF0140007 + +/* AGC2TH */ +#define R367_OFDM_AGC2TH 0xF015 +#define F367_OFDM_AGC2_THRES 0xF01500FF + +/* AGC12C */ +#define R367_OFDM_AGC12C 0xF016 +#define F367_OFDM_AGC1_IV 0xF0160080 +#define F367_OFDM_AGC1_OD 0xF0160040 +#define F367_OFDM_AGC1_LOAD 0xF0160020 +#define F367_OFDM_AGC2_IV 0xF0160010 +#define F367_OFDM_AGC2_OD 0xF0160008 +#define F367_OFDM_AGC2_LOAD 0xF0160004 +#define F367_OFDM_AGC12_MODE 0xF0160003 + +/* AGCCTRL1 */ +#define R367_OFDM_AGCCTRL1 0xF017 +#define F367_OFDM_DAGC_ON 0xF0170080 +#define F367_OFDM_INVERT_AGC12 0xF0170040 +#define F367_OFDM_AGC1_MODE 0xF0170008 +#define F367_OFDM_AGC2_MODE 0xF0170007 + +/* AGCCTRL2 */ +#define R367_OFDM_AGCCTRL2 0xF018 +#define F367_OFDM_FRZ2_CTRL 0xF0180060 +#define F367_OFDM_FRZ1_CTRL 0xF0180018 +#define F367_OFDM_TIME_CST 0xF0180007 + +/* AGC1VAL1 */ +#define R367_OFDM_AGC1VAL1 0xF019 +#define F367_OFDM_AGC1_VAL_LO 0xF01900FF + +/* AGC1VAL2 */ +#define R367_OFDM_AGC1VAL2 0xF01A +#define F367_OFDM_AGC1_VAL_HI 0xF01A000F + +/* AGC2VAL1 */ +#define R367_OFDM_AGC2VAL1 0xF01B +#define F367_OFDM_AGC2_VAL_LO 0xF01B00FF + +/* AGC2VAL2 */ +#define R367_OFDM_AGC2VAL2 0xF01C +#define F367_OFDM_AGC2_VAL_HI 0xF01C000F + +/* AGC2PGA */ +#define R367_OFDM_AGC2PGA 0xF01D +#define F367_OFDM_AGC2_PGA 0xF01D00FF + +/* OVF_RATE1 */ +#define R367_OFDM_OVF_RATE1 0xF01E +#define F367_OFDM_OVF_RATE_HI 0xF01E000F + +/* OVF_RATE2 */ +#define R367_OFDM_OVF_RATE2 0xF01F +#define F367_OFDM_OVF_RATE_LO 0xF01F00FF + +/* GAIN_SRC1 */ +#define R367_OFDM_GAIN_SRC1 0xF020 +#define F367_OFDM_INV_SPECTR 0xF0200080 +#define F367_OFDM_IQ_INVERT 0xF0200040 +#define F367_OFDM_INR_BYPASS 0xF0200020 +#define F367_OFDM_STATUS_INV_SPECRUM 0xF0200010 +#define F367_OFDM_GAIN_SRC_HI 0xF020000F + +/* GAIN_SRC2 */ +#define R367_OFDM_GAIN_SRC2 0xF021 +#define F367_OFDM_GAIN_SRC_LO 0xF02100FF + +/* INC_DEROT1 */ +#define R367_OFDM_INC_DEROT1 0xF022 +#define F367_OFDM_INC_DEROT_HI 0xF02200FF + +/* INC_DEROT2 */ +#define R367_OFDM_INC_DEROT2 0xF023 +#define F367_OFDM_INC_DEROT_LO 0xF02300FF + +/* PPM_CPAMP_DIR */ +#define R367_OFDM_PPM_CPAMP_DIR 0xF024 +#define F367_OFDM_PPM_CPAMP_DIRECT 0xF02400FF + +/* PPM_CPAMP_INV */ +#define R367_OFDM_PPM_CPAMP_INV 0xF025 +#define F367_OFDM_PPM_CPAMP_INVER 0xF02500FF + +/* FREESTFE_1 */ +#define R367_OFDM_FREESTFE_1 0xF026 +#define F367_OFDM_SYMBOL_NUMBER_INC 0xF02600C0 +#define F367_OFDM_SEL_LSB 0xF0260004 +#define F367_OFDM_AVERAGE_ON 0xF0260002 +#define F367_OFDM_DC_ADJ 0xF0260001 + +/* FREESTFE_2 */ +#define R367_OFDM_FREESTFE_2 0xF027 +#define F367_OFDM_SEL_SRCOUT 0xF02700C0 +#define F367_OFDM_SEL_SYRTHR 0xF027001F + +/* DCOFFSET */ +#define R367_OFDM_DCOFFSET 0xF028 +#define F367_OFDM_SELECT_I_Q 0xF0280080 +#define F367_OFDM_DC_OFFSET 0xF028007F + +/* EN_PROCESS */ +#define R367_OFDM_EN_PROCESS 0xF029 +#define F367_OFDM_FREE 0xF02900F0 +#define F367_OFDM_ENAB_MANUAL 0xF0290001 + +/* SDI_SMOOTHER */ +#define R367_OFDM_SDI_SMOOTHER 0xF02A +#define F367_OFDM_DIS_SMOOTH 0xF02A0080 +#define F367_OFDM_SDI_INC_SMOOTHER 0xF02A007F + +/* FE_LOOP_OPEN */ +#define R367_OFDM_FE_LOOP_OPEN 0xF02B +#define F367_OFDM_TRL_LOOP_OP 0xF02B0002 +#define F367_OFDM_CRL_LOOP_OP 0xF02B0001 + +/* FREQOFF1 */ +#define R367_OFDM_FREQOFF1 0xF02C +#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_VHI 0xF02C00FF + +/* FREQOFF2 */ +#define R367_OFDM_FREQOFF2 0xF02D +#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_HI 0xF02D00FF + +/* FREQOFF3 */ +#define R367_OFDM_FREQOFF3 0xF02E +#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_LO 0xF02E00FF + +/* TIMOFF1 */ +#define R367_OFDM_TIMOFF1 0xF02F +#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_HI 0xF02F00FF + +/* TIMOFF2 */ +#define R367_OFDM_TIMOFF2 0xF030 +#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_LO 0xF03000FF + +/* EPQ */ +#define R367_OFDM_EPQ 0xF031 +#define F367_OFDM_EPQ1 0xF03100FF + +/* EPQAUTO */ +#define R367_OFDM_EPQAUTO 0xF032 +#define F367_OFDM_EPQ2 0xF03200FF + +/* SYR_UPDATE */ +#define R367_OFDM_SYR_UPDATE 0xF033 +#define F367_OFDM_SYR_PROTV 0xF0330080 +#define F367_OFDM_SYR_PROTV_GAIN 0xF0330060 +#define F367_OFDM_SYR_FILTER 0xF0330010 +#define F367_OFDM_SYR_TRACK_THRES 0xF033000C + +/* CHPFREE */ +#define R367_OFDM_CHPFREE 0xF034 +#define F367_OFDM_CHP_FREE 0xF03400FF + +/* PPM_STATE_MAC */ +#define R367_OFDM_PPM_STATE_MAC 0xF035 +#define F367_OFDM_PPM_STATE_MACHINE_DECODER 0xF035003F + +/* INR_THRESHOLD */ +#define R367_OFDM_INR_THRESHOLD 0xF036 +#define F367_OFDM_INR_THRESH 0xF03600FF + +/* EPQ_TPS_ID_CELL */ +#define R367_OFDM_EPQ_TPS_ID_CELL 0xF037 +#define F367_OFDM_ENABLE_LGTH_TO_CF 0xF0370080 +#define F367_OFDM_DIS_TPS_RSVD 0xF0370040 +#define F367_OFDM_DIS_BCH 0xF0370020 +#define F367_OFDM_DIS_ID_CEL 0xF0370010 +#define F367_OFDM_TPS_ADJUST_SYM 0xF037000F + +/* EPQ_CFG */ +#define R367_OFDM_EPQ_CFG 0xF038 +#define F367_OFDM_EPQ_RANGE 0xF0380002 +#define F367_OFDM_EPQ_SOFT 0xF0380001 + +/* EPQ_STATUS */ +#define R367_OFDM_EPQ_STATUS 0xF039 +#define F367_OFDM_SLOPE_INC 0xF03900FC +#define F367_OFDM_TPS_FIELD 0xF0390003 + +/* AUTORELOCK */ +#define R367_OFDM_AUTORELOCK 0xF03A +#define F367_OFDM_BYPASS_BER_TEMPO 0xF03A0080 +#define F367_OFDM_BER_TEMPO 0xF03A0070 +#define F367_OFDM_BYPASS_COFDM_TEMPO 0xF03A0008 +#define F367_OFDM_COFDM_TEMPO 0xF03A0007 + +/* BER_THR_VMSB */ +#define R367_OFDM_BER_THR_VMSB 0xF03B +#define F367_OFDM_BER_THRESHOLD_HI 0xF03B00FF + +/* BER_THR_MSB */ +#define R367_OFDM_BER_THR_MSB 0xF03C +#define F367_OFDM_BER_THRESHOLD_MID 0xF03C00FF + +/* BER_THR_LSB */ +#define R367_OFDM_BER_THR_LSB 0xF03D +#define F367_OFDM_BER_THRESHOLD_LO 0xF03D00FF + +/* CCD */ +#define R367_OFDM_CCD 0xF03E +#define F367_OFDM_CCD_DETECTED 0xF03E0080 +#define F367_OFDM_CCD_RESET 0xF03E0040 +#define F367_OFDM_CCD_THRESHOLD 0xF03E000F + +/* SPECTR_CFG */ +#define R367_OFDM_SPECTR_CFG 0xF03F +#define F367_OFDM_SPECT_CFG 0xF03F0003 + +/* CONSTMU_MSB */ +#define R367_OFDM_CONSTMU_MSB 0xF040 +#define F367_OFDM_CONSTMU_FREEZE 0xF0400080 +#define F367_OFDM_CONSTNU_FORCE_EN 0xF0400040 +#define F367_OFDM_CONST_MU_MSB 0xF040003F + +/* CONSTMU_LSB */ +#define R367_OFDM_CONSTMU_LSB 0xF041 +#define F367_OFDM_CONST_MU_LSB 0xF04100FF + +/* CONSTMU_MAX_MSB */ +#define R367_OFDM_CONSTMU_MAX_MSB 0xF042 +#define F367_OFDM_CONST_MU_MAX_MSB 0xF042003F + +/* CONSTMU_MAX_LSB */ +#define R367_OFDM_CONSTMU_MAX_LSB 0xF043 +#define F367_OFDM_CONST_MU_MAX_LSB 0xF04300FF + +/* ALPHANOISE */ +#define R367_OFDM_ALPHANOISE 0xF044 +#define F367_OFDM_USE_ALLFILTER 0xF0440080 +#define F367_OFDM_INTER_ON 0xF0440040 +#define F367_OFDM_ALPHA_NOISE 0xF044001F + +/* MAXGP_MSB */ +#define R367_OFDM_MAXGP_MSB 0xF045 +#define F367_OFDM_MUFILTER_LENGTH 0xF04500F0 +#define F367_OFDM_MAX_GP_MSB 0xF045000F + +/* MAXGP_LSB */ +#define R367_OFDM_MAXGP_LSB 0xF046 +#define F367_OFDM_MAX_GP_LSB 0xF04600FF + +/* ALPHAMSB */ +#define R367_OFDM_ALPHAMSB 0xF047 +#define F367_OFDM_CHC_DATARATE 0xF04700C0 +#define F367_OFDM_ALPHA_MSB 0xF047003F + +/* ALPHALSB */ +#define R367_OFDM_ALPHALSB 0xF048 +#define F367_OFDM_ALPHA_LSB 0xF04800FF + +/* PILOT_ACCU */ +#define R367_OFDM_PILOT_ACCU 0xF049 +#define F367_OFDM_USE_SCAT4ADDAPT 0xF0490080 +#define F367_OFDM_PILOT_ACC 0xF049001F + +/* PILOTMU_ACCU */ +#define R367_OFDM_PILOTMU_ACCU 0xF04A +#define F367_OFDM_DISCARD_BAD_SP 0xF04A0080 +#define F367_OFDM_DISCARD_BAD_CP 0xF04A0040 +#define F367_OFDM_PILOT_MU_ACCU 0xF04A001F + +/* FILT_CHANNEL_EST */ +#define R367_OFDM_FILT_CHANNEL_EST 0xF04B +#define F367_OFDM_USE_FILT_PILOT 0xF04B0080 +#define F367_OFDM_FILT_CHANNEL 0xF04B007F + +/* ALPHA_NOPISE_FREQ */ +#define R367_OFDM_ALPHA_NOPISE_FREQ 0xF04C +#define F367_OFDM_NOISE_FREQ_FILT 0xF04C0040 +#define F367_OFDM_ALPHA_NOISE_FREQ 0xF04C003F + +/* RATIO_PILOT */ +#define R367_OFDM_RATIO_PILOT 0xF04D +#define F367_OFDM_RATIO_MEAN_SP 0xF04D00F0 +#define F367_OFDM_RATIO_MEAN_CP 0xF04D000F + +/* CHC_CTL */ +#define R367_OFDM_CHC_CTL 0xF04E +#define F367_OFDM_TRACK_EN 0xF04E0080 +#define F367_OFDM_NOISE_NORM_EN 0xF04E0040 +#define F367_OFDM_FORCE_CHC_RESET 0xF04E0020 +#define F367_OFDM_SHORT_TIME 0xF04E0010 +#define F367_OFDM_FORCE_STATE_EN 0xF04E0008 +#define F367_OFDM_FORCE_STATE 0xF04E0007 + +/* EPQ_ADJUST */ +#define R367_OFDM_EPQ_ADJUST 0xF04F +#define F367_OFDM_ADJUST_SCAT_IND 0xF04F00C0 +#define F367_OFDM_ONE_SYMBOL 0xF04F0010 +#define F367_OFDM_EPQ_DECAY 0xF04F000E +#define F367_OFDM_HOLD_SLOPE 0xF04F0001 + +/* EPQ_THRES */ +#define R367_OFDM_EPQ_THRES 0xF050 +#define F367_OFDM_EPQ_THR 0xF05000FF + +/* OMEGA_CTL */ +#define R367_OFDM_OMEGA_CTL 0xF051 +#define F367_OFDM_OMEGA_RST 0xF0510080 +#define F367_OFDM_FREEZE_OMEGA 0xF0510040 +#define F367_OFDM_OMEGA_SEL 0xF051003F + +/* GP_CTL */ +#define R367_OFDM_GP_CTL 0xF052 +#define F367_OFDM_CHC_STATE 0xF05200E0 +#define F367_OFDM_FREEZE_GP 0xF0520010 +#define F367_OFDM_GP_SEL 0xF052000F + +/* MUMSB */ +#define R367_OFDM_MUMSB 0xF053 +#define F367_OFDM_MU_MSB 0xF053007F + +/* MULSB */ +#define R367_OFDM_MULSB 0xF054 +#define F367_OFDM_MU_LSB 0xF05400FF + +/* GPMSB */ +#define R367_OFDM_GPMSB 0xF055 +#define F367_OFDM_CSI_THRESHOLD 0xF05500E0 +#define F367_OFDM_GP_MSB 0xF055000F + +/* GPLSB */ +#define R367_OFDM_GPLSB 0xF056 +#define F367_OFDM_GP_LSB 0xF05600FF + +/* OMEGAMSB */ +#define R367_OFDM_OMEGAMSB 0xF057 +#define F367_OFDM_OMEGA_MSB 0xF057007F + +/* OMEGALSB */ +#define R367_OFDM_OMEGALSB 0xF058 +#define F367_OFDM_OMEGA_LSB 0xF05800FF + +/* SCAT_NB */ +#define R367_OFDM_SCAT_NB 0xF059 +#define F367_OFDM_CHC_TEST 0xF05900F8 +#define F367_OFDM_SCAT_NUMB 0xF0590003 + +/* CHC_DUMMY */ +#define R367_OFDM_CHC_DUMMY 0xF05A +#define F367_OFDM_CHC_DUM 0xF05A00FF + +/* INC_CTL */ +#define R367_OFDM_INC_CTL 0xF05B +#define F367_OFDM_INC_BYPASS 0xF05B0080 +#define F367_OFDM_INC_NDEPTH 0xF05B000C +#define F367_OFDM_INC_MADEPTH 0xF05B0003 + +/* INCTHRES_COR1 */ +#define R367_OFDM_INCTHRES_COR1 0xF05C +#define F367_OFDM_INC_THRES_COR1 0xF05C00FF + +/* INCTHRES_COR2 */ +#define R367_OFDM_INCTHRES_COR2 0xF05D +#define F367_OFDM_INC_THRES_COR2 0xF05D00FF + +/* INCTHRES_DET1 */ +#define R367_OFDM_INCTHRES_DET1 0xF05E +#define F367_OFDM_INC_THRES_DET1 0xF05E003F + +/* INCTHRES_DET2 */ +#define R367_OFDM_INCTHRES_DET2 0xF05F +#define F367_OFDM_INC_THRES_DET2 0xF05F003F + +/* IIR_CELLNB */ +#define R367_OFDM_IIR_CELLNB 0xF060 +#define F367_OFDM_NRST_IIR 0xF0600080 +#define F367_OFDM_IIR_CELL_NB 0xF0600007 + +/* IIRCX_COEFF1_MSB */ +#define R367_OFDM_IIRCX_COEFF1_MSB 0xF061 +#define F367_OFDM_IIR_CX_COEFF1_MSB 0xF06100FF + +/* IIRCX_COEFF1_LSB */ +#define R367_OFDM_IIRCX_COEFF1_LSB 0xF062 +#define F367_OFDM_IIR_CX_COEFF1_LSB 0xF06200FF + +/* IIRCX_COEFF2_MSB */ +#define R367_OFDM_IIRCX_COEFF2_MSB 0xF063 +#define F367_OFDM_IIR_CX_COEFF2_MSB 0xF06300FF + +/* IIRCX_COEFF2_LSB */ +#define R367_OFDM_IIRCX_COEFF2_LSB 0xF064 +#define F367_OFDM_IIR_CX_COEFF2_LSB 0xF06400FF + +/* IIRCX_COEFF3_MSB */ +#define R367_OFDM_IIRCX_COEFF3_MSB 0xF065 +#define F367_OFDM_IIR_CX_COEFF3_MSB 0xF06500FF + +/* IIRCX_COEFF3_LSB */ +#define R367_OFDM_IIRCX_COEFF3_LSB 0xF066 +#define F367_OFDM_IIR_CX_COEFF3_LSB 0xF06600FF + +/* IIRCX_COEFF4_MSB */ +#define R367_OFDM_IIRCX_COEFF4_MSB 0xF067 +#define F367_OFDM_IIR_CX_COEFF4_MSB 0xF06700FF + +/* IIRCX_COEFF4_LSB */ +#define R367_OFDM_IIRCX_COEFF4_LSB 0xF068 +#define F367_OFDM_IIR_CX_COEFF4_LSB 0xF06800FF + +/* IIRCX_COEFF5_MSB */ +#define R367_OFDM_IIRCX_COEFF5_MSB 0xF069 +#define F367_OFDM_IIR_CX_COEFF5_MSB 0xF06900FF + +/* IIRCX_COEFF5_LSB */ +#define R367_OFDM_IIRCX_COEFF5_LSB 0xF06A +#define F367_OFDM_IIR_CX_COEFF5_LSB 0xF06A00FF + +/* FEPATH_CFG */ +#define R367_OFDM_FEPATH_CFG 0xF06B +#define F367_OFDM_DEMUX_SWAP 0xF06B0004 +#define F367_OFDM_DIGAGC_SWAP 0xF06B0002 +#define F367_OFDM_LONGPATH_IF 0xF06B0001 + +/* PMC1_FUNC */ +#define R367_OFDM_PMC1_FUNC 0xF06C +#define F367_OFDM_SOFT_RSTN 0xF06C0080 +#define F367_OFDM_PMC1_AVERAGE_TIME 0xF06C0078 +#define F367_OFDM_PMC1_WAIT_TIME 0xF06C0006 +#define F367_OFDM_PMC1_2N_SEL 0xF06C0001 + +/* PMC1_FOR */ +#define R367_OFDM_PMC1_FOR 0xF06D +#define F367_OFDM_PMC1_FORCE 0xF06D0080 +#define F367_OFDM_PMC1_FORCE_VALUE 0xF06D007C + +/* PMC2_FUNC */ +#define R367_OFDM_PMC2_FUNC 0xF06E +#define F367_OFDM_PMC2_SOFT_STN 0xF06E0080 +#define F367_OFDM_PMC2_ACCU_TIME 0xF06E0070 +#define F367_OFDM_PMC2_CMDP_MN 0xF06E0008 +#define F367_OFDM_PMC2_SWAP 0xF06E0004 + +/* STATUS_ERR_DA */ +#define R367_OFDM_STATUS_ERR_DA 0xF06F +#define F367_OFDM_COM_USEGAINTRK 0xF06F0080 +#define F367_OFDM_COM_AGCLOCK 0xF06F0040 +#define F367_OFDM_AUT_AGCLOCK 0xF06F0020 +#define F367_OFDM_MIN_ERR_X_LSB 0xF06F000F + +/* DIG_AGC_R */ +#define R367_OFDM_DIG_AGC_R 0xF070 +#define F367_OFDM_COM_SOFT_RSTN 0xF0700080 +#define F367_OFDM_COM_AGC_ON 0xF0700040 +#define F367_OFDM_COM_EARLY 0xF0700020 +#define F367_OFDM_AUT_SOFT_RESETN 0xF0700010 +#define F367_OFDM_AUT_AGC_ON 0xF0700008 +#define F367_OFDM_AUT_EARLY 0xF0700004 +#define F367_OFDM_AUT_ROT_EN 0xF0700002 +#define F367_OFDM_LOCK_SOFT_RESETN 0xF0700001 + +/* COMAGC_TARMSB */ +#define R367_OFDM_COMAGC_TARMSB 0xF071 +#define F367_OFDM_COM_AGC_TARGET_MSB 0xF07100FF + +/* COM_AGC_TAR_ENMODE */ +#define R367_OFDM_COM_AGC_TAR_ENMODE 0xF072 +#define F367_OFDM_COM_AGC_TARGET_LSB 0xF07200F0 +#define F367_OFDM_COM_ENMODE 0xF072000F + +/* COM_AGC_CFG */ +#define R367_OFDM_COM_AGC_CFG 0xF073 +#define F367_OFDM_COM_N 0xF07300F8 +#define F367_OFDM_COM_STABMODE 0xF0730006 +#define F367_OFDM_ERR_SEL 0xF0730001 + +/* COM_AGC_GAIN1 */ +#define R367_OFDM_COM_AGC_GAIN1 0xF074 +#define F367_OFDM_COM_GAIN1ACK 0xF07400F0 +#define F367_OFDM_COM_GAIN1TRK 0xF074000F + +/* AUT_AGC_TARGETMSB */ +#define R367_OFDM_AUT_AGC_TARGETMSB 0xF075 +#define F367_OFDM_AUT_AGC_TARGET_MSB 0xF07500FF + +/* LOCK_DET_MSB */ +#define R367_OFDM_LOCK_DET_MSB 0xF076 +#define F367_OFDM_LOCK_DETECT_MSB 0xF07600FF + +/* AGCTAR_LOCK_LSBS */ +#define R367_OFDM_AGCTAR_LOCK_LSBS 0xF077 +#define F367_OFDM_AUT_AGC_TARGET_LSB 0xF07700F0 +#define F367_OFDM_LOCK_DETECT_LSB 0xF077000F + +/* AUT_GAIN_EN */ +#define R367_OFDM_AUT_GAIN_EN 0xF078 +#define F367_OFDM_AUT_ENMODE 0xF07800F0 +#define F367_OFDM_AUT_GAIN2 0xF078000F + +/* AUT_CFG */ +#define R367_OFDM_AUT_CFG 0xF079 +#define F367_OFDM_AUT_N 0xF07900F8 +#define F367_OFDM_INT_CHOICE 0xF0790006 +#define F367_OFDM_INT_LOAD 0xF0790001 + +/* LOCKN */ +#define R367_OFDM_LOCKN 0xF07A +#define F367_OFDM_LOCK_N 0xF07A00F8 +#define F367_OFDM_SEL_IQNTAR 0xF07A0004 +#define F367_OFDM_LOCK_DETECT_CHOICE 0xF07A0003 + +/* INT_X_3 */ +#define R367_OFDM_INT_X_3 0xF07B +#define F367_OFDM_INT_X3 0xF07B00FF + +/* INT_X_2 */ +#define R367_OFDM_INT_X_2 0xF07C +#define F367_OFDM_INT_X2 0xF07C00FF + +/* INT_X_1 */ +#define R367_OFDM_INT_X_1 0xF07D +#define F367_OFDM_INT_X1 0xF07D00FF + +/* INT_X_0 */ +#define R367_OFDM_INT_X_0 0xF07E +#define F367_OFDM_INT_X0 0xF07E00FF + +/* MIN_ERRX_MSB */ +#define R367_OFDM_MIN_ERRX_MSB 0xF07F +#define F367_OFDM_MIN_ERR_X_MSB 0xF07F00FF + +/* COR_CTL */ +#define R367_OFDM_COR_CTL 0xF080 +#define F367_OFDM_CORE_ACTIVE 0xF0800020 +#define F367_OFDM_HOLD 0xF0800010 +#define F367_OFDM_CORE_STATE_CTL 0xF080000F + +/* COR_STAT */ +#define R367_OFDM_COR_STAT 0xF081 +#define F367_OFDM_SCATT_LOCKED 0xF0810080 +#define F367_OFDM_TPS_LOCKED 0xF0810040 +#define F367_OFDM_SYR_LOCKED_COR 0xF0810020 +#define F367_OFDM_AGC_LOCKED_STAT 0xF0810010 +#define F367_OFDM_CORE_STATE_STAT 0xF081000F + +/* COR_INTEN */ +#define R367_OFDM_COR_INTEN 0xF082 +#define F367_OFDM_INTEN 0xF0820080 +#define F367_OFDM_INTEN_SYR 0xF0820020 +#define F367_OFDM_INTEN_FFT 0xF0820010 +#define F367_OFDM_INTEN_AGC 0xF0820008 +#define F367_OFDM_INTEN_TPS1 0xF0820004 +#define F367_OFDM_INTEN_TPS2 0xF0820002 +#define F367_OFDM_INTEN_TPS3 0xF0820001 + +/* COR_INTSTAT */ +#define R367_OFDM_COR_INTSTAT 0xF083 +#define F367_OFDM_INTSTAT_SYR 0xF0830020 +#define F367_OFDM_INTSTAT_FFT 0xF0830010 +#define F367_OFDM_INTSAT_AGC 0xF0830008 +#define F367_OFDM_INTSTAT_TPS1 0xF0830004 +#define F367_OFDM_INTSTAT_TPS2 0xF0830002 +#define F367_OFDM_INTSTAT_TPS3 0xF0830001 + +/* COR_MODEGUARD */ +#define R367_OFDM_COR_MODEGUARD 0xF084 +#define F367_OFDM_FORCE 0xF0840010 +#define F367_OFDM_MODE 0xF084000C +#define F367_OFDM_GUARD 0xF0840003 + +/* AGC_CTL */ +#define R367_OFDM_AGC_CTL 0xF085 +#define F367_OFDM_AGC_TIMING_FACTOR 0xF08500E0 +#define F367_OFDM_AGC_LAST 0xF0850010 +#define F367_OFDM_AGC_GAIN 0xF085000C +#define F367_OFDM_AGC_NEG 0xF0850002 +#define F367_OFDM_AGC_SET 0xF0850001 + +/* AGC_MANUAL1 */ +#define R367_OFDM_AGC_MANUAL1 0xF086 +#define F367_OFDM_AGC_VAL_LO 0xF08600FF + +/* AGC_MANUAL2 */ +#define R367_OFDM_AGC_MANUAL2 0xF087 +#define F367_OFDM_AGC_VAL_HI 0xF087000F + +/* AGC_TARG */ +#define R367_OFDM_AGC_TARG 0xF088 +#define F367_OFDM_AGC_TARGET 0xF08800FF + +/* AGC_GAIN1 */ +#define R367_OFDM_AGC_GAIN1 0xF089 +#define F367_OFDM_AGC_GAIN_LO 0xF08900FF + +/* AGC_GAIN2 */ +#define R367_OFDM_AGC_GAIN2 0xF08A +#define F367_OFDM_AGC_LOCKED_GAIN2 0xF08A0010 +#define F367_OFDM_AGC_GAIN_HI 0xF08A000F + +/* RESERVED_1 */ +#define R367_OFDM_RESERVED_1 0xF08B +#define F367_OFDM_RESERVED1 0xF08B00FF + +/* RESERVED_2 */ +#define R367_OFDM_RESERVED_2 0xF08C +#define F367_OFDM_RESERVED2 0xF08C00FF + +/* RESERVED_3 */ +#define R367_OFDM_RESERVED_3 0xF08D +#define F367_OFDM_RESERVED3 0xF08D00FF + +/* CAS_CTL */ +#define R367_OFDM_CAS_CTL 0xF08E +#define F367_OFDM_CCS_ENABLE 0xF08E0080 +#define F367_OFDM_ACS_DISABLE 0xF08E0040 +#define F367_OFDM_DAGC_DIS 0xF08E0020 +#define F367_OFDM_DAGC_GAIN 0xF08E0018 +#define F367_OFDM_CCSMU 0xF08E0007 + +/* CAS_FREQ */ +#define R367_OFDM_CAS_FREQ 0xF08F +#define F367_OFDM_CCS_FREQ 0xF08F00FF + +/* CAS_DAGCGAIN */ +#define R367_OFDM_CAS_DAGCGAIN 0xF090 +#define F367_OFDM_CAS_DAGC_GAIN 0xF09000FF + +/* SYR_CTL */ +#define R367_OFDM_SYR_CTL 0xF091 +#define F367_OFDM_SICTH_ENABLE 0xF0910080 +#define F367_OFDM_LONG_ECHO 0xF0910078 +#define F367_OFDM_AUTO_LE_EN 0xF0910004 +#define F367_OFDM_SYR_BYPASS 0xF0910002 +#define F367_OFDM_SYR_TR_DIS 0xF0910001 + +/* SYR_STAT */ +#define R367_OFDM_SYR_STAT 0xF092 +#define F367_OFDM_SYR_LOCKED_STAT 0xF0920010 +#define F367_OFDM_SYR_MODE 0xF092000C +#define F367_OFDM_SYR_GUARD 0xF0920003 + +/* SYR_NCO1 */ +#define R367_OFDM_SYR_NCO1 0xF093 +#define F367_OFDM_SYR_NCO_LO 0xF09300FF + +/* SYR_NCO2 */ +#define R367_OFDM_SYR_NCO2 0xF094 +#define F367_OFDM_SYR_NCO_HI 0xF094003F + +/* SYR_OFFSET1 */ +#define R367_OFDM_SYR_OFFSET1 0xF095 +#define F367_OFDM_SYR_OFFSET_LO 0xF09500FF + +/* SYR_OFFSET2 */ +#define R367_OFDM_SYR_OFFSET2 0xF096 +#define F367_OFDM_SYR_OFFSET_HI 0xF096003F + +/* FFT_CTL */ +#define R367_OFDM_FFT_CTL 0xF097 +#define F367_OFDM_SHIFT_FFT_TRIG 0xF0970018 +#define F367_OFDM_FFT_TRIGGER 0xF0970004 +#define F367_OFDM_FFT_MANUAL 0xF0970002 +#define F367_OFDM_IFFT_MODE 0xF0970001 + +/* SCR_CTL */ +#define R367_OFDM_SCR_CTL 0xF098 +#define F367_OFDM_SYRADJDECAY 0xF0980070 +#define F367_OFDM_SCR_CPEDIS 0xF0980002 +#define F367_OFDM_SCR_DIS 0xF0980001 + +/* PPM_CTL1 */ +#define R367_OFDM_PPM_CTL1 0xF099 +#define F367_OFDM_PPM_MAXFREQ 0xF0990030 +#define F367_OFDM_PPM_MAXTIM 0xF0990008 +#define F367_OFDM_PPM_INVSEL 0xF0990004 +#define F367_OFDM_PPM_SCATDIS 0xF0990002 +#define F367_OFDM_PPM_BYP 0xF0990001 + +/* TRL_CTL */ +#define R367_OFDM_TRL_CTL 0xF09A +#define F367_OFDM_TRL_NOMRATE_LSB 0xF09A0080 +#define F367_OFDM_TRL_GAIN_FACTOR 0xF09A0078 +#define F367_OFDM_TRL_LOOPGAIN 0xF09A0007 + +/* TRL_NOMRATE1 */ +#define R367_OFDM_TRL_NOMRATE1 0xF09B +#define F367_OFDM_TRL_NOMRATE_LO 0xF09B00FF + +/* TRL_NOMRATE2 */ +#define R367_OFDM_TRL_NOMRATE2 0xF09C +#define F367_OFDM_TRL_NOMRATE_HI 0xF09C00FF + +/* TRL_TIME1 */ +#define R367_OFDM_TRL_TIME1 0xF09D +#define F367_OFDM_TRL_TOFFSET_LO 0xF09D00FF + +/* TRL_TIME2 */ +#define R367_OFDM_TRL_TIME2 0xF09E +#define F367_OFDM_TRL_TOFFSET_HI 0xF09E00FF + +/* CRL_CTL */ +#define R367_OFDM_CRL_CTL 0xF09F +#define F367_OFDM_CRL_DIS 0xF09F0080 +#define F367_OFDM_CRL_GAIN_FACTOR 0xF09F0078 +#define F367_OFDM_CRL_LOOPGAIN 0xF09F0007 + +/* CRL_FREQ1 */ +#define R367_OFDM_CRL_FREQ1 0xF0A0 +#define F367_OFDM_CRL_FOFFSET_LO 0xF0A000FF + +/* CRL_FREQ2 */ +#define R367_OFDM_CRL_FREQ2 0xF0A1 +#define F367_OFDM_CRL_FOFFSET_HI 0xF0A100FF + +/* CRL_FREQ3 */ +#define R367_OFDM_CRL_FREQ3 0xF0A2 +#define F367_OFDM_CRL_FOFFSET_VHI 0xF0A200FF + +/* TPS_SFRAME_CTL */ +#define R367_OFDM_TPS_SFRAME_CTL 0xF0A3 +#define F367_OFDM_TPS_SFRAME_SYNC 0xF0A30001 + +/* CHC_SNR */ +#define R367_OFDM_CHC_SNR 0xF0A4 +#define F367_OFDM_CHCSNR 0xF0A400FF + +/* BDI_CTL */ +#define R367_OFDM_BDI_CTL 0xF0A5 +#define F367_OFDM_BDI_LPSEL 0xF0A50002 +#define F367_OFDM_BDI_SERIAL 0xF0A50001 + +/* DMP_CTL */ +#define R367_OFDM_DMP_CTL 0xF0A6 +#define F367_OFDM_DMP_SCALING_FACTOR 0xF0A6001E +#define F367_OFDM_DMP_SDDIS 0xF0A60001 + +/* TPS_RCVD1 */ +#define R367_OFDM_TPS_RCVD1 0xF0A7 +#define F367_OFDM_TPS_CHANGE 0xF0A70040 +#define F367_OFDM_BCH_OK 0xF0A70020 +#define F367_OFDM_TPS_SYNC 0xF0A70010 +#define F367_OFDM_TPS_FRAME 0xF0A70003 + +/* TPS_RCVD2 */ +#define R367_OFDM_TPS_RCVD2 0xF0A8 +#define F367_OFDM_TPS_HIERMODE 0xF0A80070 +#define F367_OFDM_TPS_CONST 0xF0A80003 + +/* TPS_RCVD3 */ +#define R367_OFDM_TPS_RCVD3 0xF0A9 +#define F367_OFDM_TPS_LPCODE 0xF0A90070 +#define F367_OFDM_TPS_HPCODE 0xF0A90007 + +/* TPS_RCVD4 */ +#define R367_OFDM_TPS_RCVD4 0xF0AA +#define F367_OFDM_TPS_GUARD 0xF0AA0030 +#define F367_OFDM_TPS_MODE 0xF0AA0003 + +/* TPS_ID_CELL1 */ +#define R367_OFDM_TPS_ID_CELL1 0xF0AB +#define F367_OFDM_TPS_ID_CELL_LO 0xF0AB00FF + +/* TPS_ID_CELL2 */ +#define R367_OFDM_TPS_ID_CELL2 0xF0AC +#define F367_OFDM_TPS_ID_CELL_HI 0xF0AC00FF + +/* TPS_RCVD5_SET1 */ +#define R367_OFDM_TPS_RCVD5_SET1 0xF0AD +#define F367_OFDM_TPS_NA 0xF0AD00FC +#define F367_OFDM_TPS_SETFRAME 0xF0AD0003 + +/* TPS_SET2 */ +#define R367_OFDM_TPS_SET2 0xF0AE +#define F367_OFDM_TPS_SETHIERMODE 0xF0AE0070 +#define F367_OFDM_TPS_SETCONST 0xF0AE0003 + +/* TPS_SET3 */ +#define R367_OFDM_TPS_SET3 0xF0AF +#define F367_OFDM_TPS_SETLPCODE 0xF0AF0070 +#define F367_OFDM_TPS_SETHPCODE 0xF0AF0007 + +/* TPS_CTL */ +#define R367_OFDM_TPS_CTL 0xF0B0 +#define F367_OFDM_TPS_IMM 0xF0B00004 +#define F367_OFDM_TPS_BCHDIS 0xF0B00002 +#define F367_OFDM_TPS_UPDDIS 0xF0B00001 + +/* CTL_FFTOSNUM */ +#define R367_OFDM_CTL_FFTOSNUM 0xF0B1 +#define F367_OFDM_SYMBOL_NUMBER 0xF0B1007F + +/* TESTSELECT */ +#define R367_OFDM_TESTSELECT 0xF0B2 +#define F367_OFDM_TEST_SELECT 0xF0B2001F + +/* MSC_REV */ +#define R367_OFDM_MSC_REV 0xF0B3 +#define F367_OFDM_REV_NUMBER 0xF0B300FF + +/* PIR_CTL */ +#define R367_OFDM_PIR_CTL 0xF0B4 +#define F367_OFDM_FREEZE 0xF0B40001 + +/* SNR_CARRIER1 */ +#define R367_OFDM_SNR_CARRIER1 0xF0B5 +#define F367_OFDM_SNR_CARRIER_LO 0xF0B500FF + +/* SNR_CARRIER2 */ +#define R367_OFDM_SNR_CARRIER2 0xF0B6 +#define F367_OFDM_MEAN 0xF0B600C0 +#define F367_OFDM_SNR_CARRIER_HI 0xF0B6001F + +/* PPM_CPAMP */ +#define R367_OFDM_PPM_CPAMP 0xF0B7 +#define F367_OFDM_PPM_CPC 0xF0B700FF + +/* TSM_AP0 */ +#define R367_OFDM_TSM_AP0 0xF0B8 +#define F367_OFDM_ADDRESS_BYTE_0 0xF0B800FF + +/* TSM_AP1 */ +#define R367_OFDM_TSM_AP1 0xF0B9 +#define F367_OFDM_ADDRESS_BYTE_1 0xF0B900FF + +/* TSM_AP2 */ +#define R367_OFDM_TSM_AP2 0xF0BA +#define F367_OFDM_DATA_BYTE_0 0xF0BA00FF + +/* TSM_AP3 */ +#define R367_OFDM_TSM_AP3 0xF0BB +#define F367_OFDM_DATA_BYTE_1 0xF0BB00FF + +/* TSM_AP4 */ +#define R367_OFDM_TSM_AP4 0xF0BC +#define F367_OFDM_DATA_BYTE_2 0xF0BC00FF + +/* TSM_AP5 */ +#define R367_OFDM_TSM_AP5 0xF0BD +#define F367_OFDM_DATA_BYTE_3 0xF0BD00FF + +/* TSM_AP6 */ +#define R367_OFDM_TSM_AP6 0xF0BE +#define F367_OFDM_TSM_AP_6 0xF0BE00FF + +/* TSM_AP7 */ +#define R367_OFDM_TSM_AP7 0xF0BF +#define F367_OFDM_MEM_SELECT_BYTE 0xF0BF00FF + +/* TSTRES */ +#define R367_TSTRES 0xF0C0 +#define F367_FRES_DISPLAY 0xF0C00080 +#define F367_FRES_FIFO_AD 0xF0C00020 +#define F367_FRESRS 0xF0C00010 +#define F367_FRESACS 0xF0C00008 +#define F367_FRESFEC 0xF0C00004 +#define F367_FRES_PRIF 0xF0C00002 +#define F367_FRESCORE 0xF0C00001 + +/* ANACTRL */ +#define R367_ANACTRL 0xF0C1 +#define F367_BYPASS_XTAL 0xF0C10040 +#define F367_BYPASS_PLLXN 0xF0C1000C +#define F367_DIS_PAD_OSC 0xF0C10002 +#define F367_STDBY_PLLXN 0xF0C10001 + +/* TSTBUS */ +#define R367_TSTBUS 0xF0C2 +#define F367_TS_BYTE_CLK_INV 0xF0C20080 +#define F367_CFG_IP 0xF0C20070 +#define F367_CFG_TST 0xF0C2000F + +/* TSTRATE */ +#define R367_TSTRATE 0xF0C6 +#define F367_FORCEPHA 0xF0C60080 +#define F367_FNEWPHA 0xF0C60010 +#define F367_FROT90 0xF0C60008 +#define F367_FR 0xF0C60007 + +/* CONSTMODE */ +#define R367_OFDM_CONSTMODE 0xF0CB +#define F367_OFDM_TST_PRIF 0xF0CB00E0 +#define F367_OFDM_CAR_TYPE 0xF0CB0018 +#define F367_OFDM_CONST_MODE 0xF0CB0003 + +/* CONSTCARR1 */ +#define R367_OFDM_CONSTCARR1 0xF0CC +#define F367_OFDM_CONST_CARR_LO 0xF0CC00FF + +/* CONSTCARR2 */ +#define R367_OFDM_CONSTCARR2 0xF0CD +#define F367_OFDM_CONST_CARR_HI 0xF0CD001F + +/* ICONSTEL */ +#define R367_OFDM_ICONSTEL 0xF0CE +#define F367_OFDM_PICONSTEL 0xF0CE00FF + +/* QCONSTEL */ +#define R367_OFDM_QCONSTEL 0xF0CF +#define F367_OFDM_PQCONSTEL 0xF0CF00FF + +/* TSTBISTRES0 */ +#define R367_OFDM_TSTBISTRES0 0xF0D0 +#define F367_OFDM_BEND_PPM 0xF0D00080 +#define F367_OFDM_BBAD_PPM 0xF0D00040 +#define F367_OFDM_BEND_FFTW 0xF0D00020 +#define F367_OFDM_BBAD_FFTW 0xF0D00010 +#define F367_OFDM_BEND_FFT_BUF 0xF0D00008 +#define F367_OFDM_BBAD_FFT_BUF 0xF0D00004 +#define F367_OFDM_BEND_SYR 0xF0D00002 +#define F367_OFDM_BBAD_SYR 0xF0D00001 + +/* TSTBISTRES1 */ +#define R367_OFDM_TSTBISTRES1 0xF0D1 +#define F367_OFDM_BEND_CHC_CP 0xF0D10080 +#define F367_OFDM_BBAD_CHC_CP 0xF0D10040 +#define F367_OFDM_BEND_CHCI 0xF0D10020 +#define F367_OFDM_BBAD_CHCI 0xF0D10010 +#define F367_OFDM_BEND_BDI 0xF0D10008 +#define F367_OFDM_BBAD_BDI 0xF0D10004 +#define F367_OFDM_BEND_SDI 0xF0D10002 +#define F367_OFDM_BBAD_SDI 0xF0D10001 + +/* TSTBISTRES2 */ +#define R367_OFDM_TSTBISTRES2 0xF0D2 +#define F367_OFDM_BEND_CHC_INC 0xF0D20080 +#define F367_OFDM_BBAD_CHC_INC 0xF0D20040 +#define F367_OFDM_BEND_CHC_SPP 0xF0D20020 +#define F367_OFDM_BBAD_CHC_SPP 0xF0D20010 +#define F367_OFDM_BEND_CHC_CPP 0xF0D20008 +#define F367_OFDM_BBAD_CHC_CPP 0xF0D20004 +#define F367_OFDM_BEND_CHC_SP 0xF0D20002 +#define F367_OFDM_BBAD_CHC_SP 0xF0D20001 + +/* TSTBISTRES3 */ +#define R367_OFDM_TSTBISTRES3 0xF0D3 +#define F367_OFDM_BEND_QAM 0xF0D30080 +#define F367_OFDM_BBAD_QAM 0xF0D30040 +#define F367_OFDM_BEND_SFEC_VIT 0xF0D30020 +#define F367_OFDM_BBAD_SFEC_VIT 0xF0D30010 +#define F367_OFDM_BEND_SFEC_DLINE 0xF0D30008 +#define F367_OFDM_BBAD_SFEC_DLINE 0xF0D30004 +#define F367_OFDM_BEND_SFEC_HW 0xF0D30002 +#define F367_OFDM_BBAD_SFEC_HW 0xF0D30001 + +/* RF_AGC1 */ +#define R367_RF_AGC1 0xF0D4 +#define F367_RF_AGC1_LEVEL_HI 0xF0D400FF + +/* RF_AGC2 */ +#define R367_RF_AGC2 0xF0D5 +#define F367_REF_ADGP 0xF0D50080 +#define F367_STDBY_ADCGP 0xF0D50020 +#define F367_CHANNEL_SEL 0xF0D5001C +#define F367_RF_AGC1_LEVEL_LO 0xF0D50003 + +/* ANADIGCTRL */ +#define R367_ANADIGCTRL 0xF0D7 +#define F367_SEL_CLKDEM 0xF0D70020 +#define F367_EN_BUFFER_Q 0xF0D70010 +#define F367_EN_BUFFER_I 0xF0D70008 +#define F367_ADC_RIS_EGDE 0xF0D70004 +#define F367_SGN_ADC 0xF0D70002 +#define F367_SEL_AD12_SYNC 0xF0D70001 + +/* PLLMDIV */ +#define R367_PLLMDIV 0xF0D8 +#define F367_PLL_MDIV 0xF0D800FF + +/* PLLNDIV */ +#define R367_PLLNDIV 0xF0D9 +#define F367_PLL_NDIV 0xF0D900FF + +/* PLLSETUP */ +#define R367_PLLSETUP 0xF0DA +#define F367_PLL_PDIV 0xF0DA0070 +#define F367_PLL_KDIV 0xF0DA000F + +/* DUAL_AD12 */ +#define R367_DUAL_AD12 0xF0DB +#define F367_FS20M 0xF0DB0020 +#define F367_FS50M 0xF0DB0010 +#define F367_INMODE0 0xF0DB0008 +#define F367_POFFQ 0xF0DB0004 +#define F367_POFFI 0xF0DB0002 +#define F367_INMODE1 0xF0DB0001 + +/* TSTBIST */ +#define R367_TSTBIST 0xF0DC +#define F367_TST_BYP_CLK 0xF0DC0080 +#define F367_TST_GCLKENA_STD 0xF0DC0040 +#define F367_TST_GCLKENA 0xF0DC0020 +#define F367_TST_MEMBIST 0xF0DC001F + +/* PAD_COMP_CTRL */ +#define R367_PAD_COMP_CTRL 0xF0DD +#define F367_COMPTQ 0xF0DD0010 +#define F367_COMPEN 0xF0DD0008 +#define F367_FREEZE2 0xF0DD0004 +#define F367_SLEEP_INHBT 0xF0DD0002 +#define F367_CHIP_SLEEP 0xF0DD0001 + +/* PAD_COMP_WR */ +#define R367_PAD_COMP_WR 0xF0DE +#define F367_WR_ASRC 0xF0DE007F + +/* PAD_COMP_RD */ +#define R367_PAD_COMP_RD 0xF0DF +#define F367_COMPOK 0xF0DF0080 +#define F367_RD_ASRC 0xF0DF007F + +/* SYR_TARGET_FFTADJT_MSB */ +#define R367_OFDM_SYR_TARGET_FFTADJT_MSB 0xF100 +#define F367_OFDM_SYR_START 0xF1000080 +#define F367_OFDM_SYR_TARGET_FFTADJ_HI 0xF100000F + +/* SYR_TARGET_FFTADJT_LSB */ +#define R367_OFDM_SYR_TARGET_FFTADJT_LSB 0xF101 +#define F367_OFDM_SYR_TARGET_FFTADJ_LO 0xF10100FF + +/* SYR_TARGET_CHCADJT_MSB */ +#define R367_OFDM_SYR_TARGET_CHCADJT_MSB 0xF102 +#define F367_OFDM_SYR_TARGET_CHCADJ_HI 0xF102000F + +/* SYR_TARGET_CHCADJT_LSB */ +#define R367_OFDM_SYR_TARGET_CHCADJT_LSB 0xF103 +#define F367_OFDM_SYR_TARGET_CHCADJ_LO 0xF10300FF + +/* SYR_FLAG */ +#define R367_OFDM_SYR_FLAG 0xF104 +#define F367_OFDM_TRIG_FLG1 0xF1040080 +#define F367_OFDM_TRIG_FLG0 0xF1040040 +#define F367_OFDM_FFT_FLG1 0xF1040008 +#define F367_OFDM_FFT_FLG0 0xF1040004 +#define F367_OFDM_CHC_FLG1 0xF1040002 +#define F367_OFDM_CHC_FLG0 0xF1040001 + +/* CRL_TARGET1 */ +#define R367_OFDM_CRL_TARGET1 0xF105 +#define F367_OFDM_CRL_START 0xF1050080 +#define F367_OFDM_CRL_TARGET_VHI 0xF105000F + +/* CRL_TARGET2 */ +#define R367_OFDM_CRL_TARGET2 0xF106 +#define F367_OFDM_CRL_TARGET_HI 0xF10600FF + +/* CRL_TARGET3 */ +#define R367_OFDM_CRL_TARGET3 0xF107 +#define F367_OFDM_CRL_TARGET_LO 0xF10700FF + +/* CRL_TARGET4 */ +#define R367_OFDM_CRL_TARGET4 0xF108 +#define F367_OFDM_CRL_TARGET_VLO 0xF10800FF + +/* CRL_FLAG */ +#define R367_OFDM_CRL_FLAG 0xF109 +#define F367_OFDM_CRL_FLAG1 0xF1090002 +#define F367_OFDM_CRL_FLAG0 0xF1090001 + +/* TRL_TARGET1 */ +#define R367_OFDM_TRL_TARGET1 0xF10A +#define F367_OFDM_TRL_TARGET_HI 0xF10A00FF + +/* TRL_TARGET2 */ +#define R367_OFDM_TRL_TARGET2 0xF10B +#define F367_OFDM_TRL_TARGET_LO 0xF10B00FF + +/* TRL_CHC */ +#define R367_OFDM_TRL_CHC 0xF10C +#define F367_OFDM_TRL_START 0xF10C0080 +#define F367_OFDM_CHC_START 0xF10C0040 +#define F367_OFDM_TRL_FLAG1 0xF10C0002 +#define F367_OFDM_TRL_FLAG0 0xF10C0001 + +/* CHC_SNR_TARG */ +#define R367_OFDM_CHC_SNR_TARG 0xF10D +#define F367_OFDM_CHC_SNR_TARGET 0xF10D00FF + +/* TOP_TRACK */ +#define R367_OFDM_TOP_TRACK 0xF10E +#define F367_OFDM_TOP_START 0xF10E0080 +#define F367_OFDM_FIRST_FLAG 0xF10E0070 +#define F367_OFDM_TOP_FLAG1 0xF10E0008 +#define F367_OFDM_TOP_FLAG0 0xF10E0004 +#define F367_OFDM_CHC_FLAG1 0xF10E0002 +#define F367_OFDM_CHC_FLAG0 0xF10E0001 + +/* TRACKER_FREE1 */ +#define R367_OFDM_TRACKER_FREE1 0xF10F +#define F367_OFDM_TRACKER_FREE_1 0xF10F00FF + +/* ERROR_CRL1 */ +#define R367_OFDM_ERROR_CRL1 0xF110 +#define F367_OFDM_ERROR_CRL_VHI 0xF11000FF + +/* ERROR_CRL2 */ +#define R367_OFDM_ERROR_CRL2 0xF111 +#define F367_OFDM_ERROR_CRL_HI 0xF11100FF + +/* ERROR_CRL3 */ +#define R367_OFDM_ERROR_CRL3 0xF112 +#define F367_OFDM_ERROR_CRL_LOI 0xF11200FF + +/* ERROR_CRL4 */ +#define R367_OFDM_ERROR_CRL4 0xF113 +#define F367_OFDM_ERROR_CRL_VLO 0xF11300FF + +/* DEC_NCO1 */ +#define R367_OFDM_DEC_NCO1 0xF114 +#define F367_OFDM_DEC_NCO_VHI 0xF11400FF + +/* DEC_NCO2 */ +#define R367_OFDM_DEC_NCO2 0xF115 +#define F367_OFDM_DEC_NCO_HI 0xF11500FF + +/* DEC_NCO3 */ +#define R367_OFDM_DEC_NCO3 0xF116 +#define F367_OFDM_DEC_NCO_LO 0xF11600FF + +/* SNR */ +#define R367_OFDM_SNR 0xF117 +#define F367_OFDM_SNRATIO 0xF11700FF + +/* SYR_FFTADJ1 */ +#define R367_OFDM_SYR_FFTADJ1 0xF118 +#define F367_OFDM_SYR_FFTADJ_HI 0xF11800FF + +/* SYR_FFTADJ2 */ +#define R367_OFDM_SYR_FFTADJ2 0xF119 +#define F367_OFDM_SYR_FFTADJ_LO 0xF11900FF + +/* SYR_CHCADJ1 */ +#define R367_OFDM_SYR_CHCADJ1 0xF11A +#define F367_OFDM_SYR_CHCADJ_HI 0xF11A00FF + +/* SYR_CHCADJ2 */ +#define R367_OFDM_SYR_CHCADJ2 0xF11B +#define F367_OFDM_SYR_CHCADJ_LO 0xF11B00FF + +/* SYR_OFF */ +#define R367_OFDM_SYR_OFF 0xF11C +#define F367_OFDM_SYR_OFFSET 0xF11C00FF + +/* PPM_OFFSET1 */ +#define R367_OFDM_PPM_OFFSET1 0xF11D +#define F367_OFDM_PPM_OFFSET_HI 0xF11D00FF + +/* PPM_OFFSET2 */ +#define R367_OFDM_PPM_OFFSET2 0xF11E +#define F367_OFDM_PPM_OFFSET_LO 0xF11E00FF + +/* TRACKER_FREE2 */ +#define R367_OFDM_TRACKER_FREE2 0xF11F +#define F367_OFDM_TRACKER_FREE_2 0xF11F00FF + +/* DEBG_LT10 */ +#define R367_OFDM_DEBG_LT10 0xF120 +#define F367_OFDM_DEBUG_LT10 0xF12000FF + +/* DEBG_LT11 */ +#define R367_OFDM_DEBG_LT11 0xF121 +#define F367_OFDM_DEBUG_LT11 0xF12100FF + +/* DEBG_LT12 */ +#define R367_OFDM_DEBG_LT12 0xF122 +#define F367_OFDM_DEBUG_LT12 0xF12200FF + +/* DEBG_LT13 */ +#define R367_OFDM_DEBG_LT13 0xF123 +#define F367_OFDM_DEBUG_LT13 0xF12300FF + +/* DEBG_LT14 */ +#define R367_OFDM_DEBG_LT14 0xF124 +#define F367_OFDM_DEBUG_LT14 0xF12400FF + +/* DEBG_LT15 */ +#define R367_OFDM_DEBG_LT15 0xF125 +#define F367_OFDM_DEBUG_LT15 0xF12500FF + +/* DEBG_LT16 */ +#define R367_OFDM_DEBG_LT16 0xF126 +#define F367_OFDM_DEBUG_LT16 0xF12600FF + +/* DEBG_LT17 */ +#define R367_OFDM_DEBG_LT17 0xF127 +#define F367_OFDM_DEBUG_LT17 0xF12700FF + +/* DEBG_LT18 */ +#define R367_OFDM_DEBG_LT18 0xF128 +#define F367_OFDM_DEBUG_LT18 0xF12800FF + +/* DEBG_LT19 */ +#define R367_OFDM_DEBG_LT19 0xF129 +#define F367_OFDM_DEBUG_LT19 0xF12900FF + +/* DEBG_LT1A */ +#define R367_OFDM_DEBG_LT1A 0xF12A +#define F367_OFDM_DEBUG_LT1A 0xF12A00FF + +/* DEBG_LT1B */ +#define R367_OFDM_DEBG_LT1B 0xF12B +#define F367_OFDM_DEBUG_LT1B 0xF12B00FF + +/* DEBG_LT1C */ +#define R367_OFDM_DEBG_LT1C 0xF12C +#define F367_OFDM_DEBUG_LT1C 0xF12C00FF + +/* DEBG_LT1D */ +#define R367_OFDM_DEBG_LT1D 0xF12D +#define F367_OFDM_DEBUG_LT1D 0xF12D00FF + +/* DEBG_LT1E */ +#define R367_OFDM_DEBG_LT1E 0xF12E +#define F367_OFDM_DEBUG_LT1E 0xF12E00FF + +/* DEBG_LT1F */ +#define R367_OFDM_DEBG_LT1F 0xF12F +#define F367_OFDM_DEBUG_LT1F 0xF12F00FF + +/* RCCFGH */ +#define R367_OFDM_RCCFGH 0xF200 +#define F367_OFDM_TSRCFIFO_DVBCI 0xF2000080 +#define F367_OFDM_TSRCFIFO_SERIAL 0xF2000040 +#define F367_OFDM_TSRCFIFO_DISABLE 0xF2000020 +#define F367_OFDM_TSFIFO_2TORC 0xF2000010 +#define F367_OFDM_TSRCFIFO_HSGNLOUT 0xF2000008 +#define F367_OFDM_TSRCFIFO_ERRMODE 0xF2000006 +#define F367_OFDM_RCCFGH_0 0xF2000001 + +/* RCCFGM */ +#define R367_OFDM_RCCFGM 0xF201 +#define F367_OFDM_TSRCFIFO_MANSPEED 0xF20100C0 +#define F367_OFDM_TSRCFIFO_PERMDATA 0xF2010020 +#define F367_OFDM_TSRCFIFO_NONEWSGNL 0xF2010010 +#define F367_OFDM_RCBYTE_OVERSAMPLING 0xF201000E +#define F367_OFDM_TSRCFIFO_INVDATA 0xF2010001 + +/* RCCFGL */ +#define R367_OFDM_RCCFGL 0xF202 +#define F367_OFDM_TSRCFIFO_BCLKDEL1CK 0xF20200C0 +#define F367_OFDM_RCCFGL_5 0xF2020020 +#define F367_OFDM_TSRCFIFO_DUTY50 0xF2020010 +#define F367_OFDM_TSRCFIFO_NSGNL2DATA 0xF2020008 +#define F367_OFDM_TSRCFIFO_DISSERMUX 0xF2020004 +#define F367_OFDM_RCCFGL_1 0xF2020002 +#define F367_OFDM_TSRCFIFO_STOPCKDIS 0xF2020001 + +/* RCINSDELH */ +#define R367_OFDM_RCINSDELH 0xF203 +#define F367_OFDM_TSRCDEL_SYNCBYTE 0xF2030080 +#define F367_OFDM_TSRCDEL_XXHEADER 0xF2030040 +#define F367_OFDM_TSRCDEL_BBHEADER 0xF2030020 +#define F367_OFDM_TSRCDEL_DATAFIELD 0xF2030010 +#define F367_OFDM_TSRCINSDEL_ISCR 0xF2030008 +#define F367_OFDM_TSRCINSDEL_NPD 0xF2030004 +#define F367_OFDM_TSRCINSDEL_RSPARITY 0xF2030002 +#define F367_OFDM_TSRCINSDEL_CRC8 0xF2030001 + +/* RCINSDELM */ +#define R367_OFDM_RCINSDELM 0xF204 +#define F367_OFDM_TSRCINS_BBPADDING 0xF2040080 +#define F367_OFDM_TSRCINS_BCHFEC 0xF2040040 +#define F367_OFDM_TSRCINS_LDPCFEC 0xF2040020 +#define F367_OFDM_TSRCINS_EMODCOD 0xF2040010 +#define F367_OFDM_TSRCINS_TOKEN 0xF2040008 +#define F367_OFDM_TSRCINS_XXXERR 0xF2040004 +#define F367_OFDM_TSRCINS_MATYPE 0xF2040002 +#define F367_OFDM_TSRCINS_UPL 0xF2040001 + +/* RCINSDELL */ +#define R367_OFDM_RCINSDELL 0xF205 +#define F367_OFDM_TSRCINS_DFL 0xF2050080 +#define F367_OFDM_TSRCINS_SYNCD 0xF2050040 +#define F367_OFDM_TSRCINS_BLOCLEN 0xF2050020 +#define F367_OFDM_TSRCINS_SIGPCOUNT 0xF2050010 +#define F367_OFDM_TSRCINS_FIFO 0xF2050008 +#define F367_OFDM_TSRCINS_REALPACK 0xF2050004 +#define F367_OFDM_TSRCINS_TSCONFIG 0xF2050002 +#define F367_OFDM_TSRCINS_LATENCY 0xF2050001 + +/* RCSTATUS */ +#define R367_OFDM_RCSTATUS 0xF206 +#define F367_OFDM_TSRCFIFO_LINEOK 0xF2060080 +#define F367_OFDM_TSRCFIFO_ERROR 0xF2060040 +#define F367_OFDM_TSRCFIFO_DATA7 0xF2060020 +#define F367_OFDM_RCSTATUS_4 0xF2060010 +#define F367_OFDM_TSRCFIFO_DEMODSEL 0xF2060008 +#define F367_OFDM_TSRC1FIFOSPEED_STORE 0xF2060004 +#define F367_OFDM_RCSTATUS_1 0xF2060002 +#define F367_OFDM_TSRCSERIAL_IMPOSSIBLE 0xF2060001 + +/* RCSPEED */ +#define R367_OFDM_RCSPEED 0xF207 +#define F367_OFDM_TSRCFIFO_OUTSPEED 0xF20700FF + +/* RCDEBUGM */ +#define R367_OFDM_RCDEBUGM 0xF208 +#define F367_OFDM_SD_UNSYNC 0xF2080080 +#define F367_OFDM_ULFLOCK_DETECTM 0xF2080040 +#define F367_OFDM_SUL_SELECTOS 0xF2080020 +#define F367_OFDM_DILUL_NOSCRBLE 0xF2080010 +#define F367_OFDM_NUL_SCRB 0xF2080008 +#define F367_OFDM_UL_SCRB 0xF2080004 +#define F367_OFDM_SCRAULBAD 0xF2080002 +#define F367_OFDM_SCRAUL_UNSYNC 0xF2080001 + +/* RCDEBUGL */ +#define R367_OFDM_RCDEBUGL 0xF209 +#define F367_OFDM_RS_ERR 0xF2090080 +#define F367_OFDM_LLFLOCK_DETECTM 0xF2090040 +#define F367_OFDM_NOT_SUL_SELECTOS 0xF2090020 +#define F367_OFDM_DILLL_NOSCRBLE 0xF2090010 +#define F367_OFDM_NLL_SCRB 0xF2090008 +#define F367_OFDM_LL_SCRB 0xF2090004 +#define F367_OFDM_SCRALLBAD 0xF2090002 +#define F367_OFDM_SCRALL_UNSYNC 0xF2090001 + +/* RCOBSCFG */ +#define R367_OFDM_RCOBSCFG 0xF20A +#define F367_OFDM_TSRCFIFO_OBSCFG 0xF20A00FF + +/* RCOBSM */ +#define R367_OFDM_RCOBSM 0xF20B +#define F367_OFDM_TSRCFIFO_OBSDATA_HI 0xF20B00FF + +/* RCOBSL */ +#define R367_OFDM_RCOBSL 0xF20C +#define F367_OFDM_TSRCFIFO_OBSDATA_LO 0xF20C00FF + +/* RCFECSPY */ +#define R367_OFDM_RCFECSPY 0xF210 +#define F367_OFDM_SPYRC_ENABLE 0xF2100080 +#define F367_OFDM_RCNO_SYNCBYTE 0xF2100040 +#define F367_OFDM_RCSERIAL_MODE 0xF2100020 +#define F367_OFDM_RCUNUSUAL_PACKET 0xF2100010 +#define F367_OFDM_BERRCMETER_DATAMODE 0xF210000C +#define F367_OFDM_BERRCMETER_LMODE 0xF2100002 +#define F367_OFDM_BERRCMETER_RESET 0xF2100001 + +/* RCFSPYCFG */ +#define R367_OFDM_RCFSPYCFG 0xF211 +#define F367_OFDM_FECSPYRC_INPUT 0xF21100C0 +#define F367_OFDM_RCRST_ON_ERROR 0xF2110020 +#define F367_OFDM_RCONE_SHOT 0xF2110010 +#define F367_OFDM_RCI2C_MODE 0xF211000C +#define F367_OFDM_SPYRC_HSTERESIS 0xF2110003 + +/* RCFSPYDATA */ +#define R367_OFDM_RCFSPYDATA 0xF212 +#define F367_OFDM_SPYRC_STUFFING 0xF2120080 +#define F367_OFDM_RCNOERR_PKTJITTER 0xF2120040 +#define F367_OFDM_SPYRC_CNULLPKT 0xF2120020 +#define F367_OFDM_SPYRC_OUTDATA_MODE 0xF212001F + +/* RCFSPYOUT */ +#define R367_OFDM_RCFSPYOUT 0xF213 +#define F367_OFDM_FSPYRC_DIRECT 0xF2130080 +#define F367_OFDM_RCFSPYOUT_6 0xF2130040 +#define F367_OFDM_SPYRC_OUTDATA_BUS 0xF2130038 +#define F367_OFDM_RCSTUFF_MODE 0xF2130007 + +/* RCFSTATUS */ +#define R367_OFDM_RCFSTATUS 0xF214 +#define F367_OFDM_SPYRC_ENDSIM 0xF2140080 +#define F367_OFDM_RCVALID_SIM 0xF2140040 +#define F367_OFDM_RCFOUND_SIGNAL 0xF2140020 +#define F367_OFDM_RCDSS_SYNCBYTE 0xF2140010 +#define F367_OFDM_RCRESULT_STATE 0xF214000F + +/* RCFGOODPACK */ +#define R367_OFDM_RCFGOODPACK 0xF215 +#define F367_OFDM_RCGOOD_PACKET 0xF21500FF + +/* RCFPACKCNT */ +#define R367_OFDM_RCFPACKCNT 0xF216 +#define F367_OFDM_RCPACKET_COUNTER 0xF21600FF + +/* RCFSPYMISC */ +#define R367_OFDM_RCFSPYMISC 0xF217 +#define F367_OFDM_RCLABEL_COUNTER 0xF21700FF + +/* RCFBERCPT4 */ +#define R367_OFDM_RCFBERCPT4 0xF218 +#define F367_OFDM_FBERRCMETER_CPT_MMMMSB 0xF21800FF + +/* RCFBERCPT3 */ +#define R367_OFDM_RCFBERCPT3 0xF219 +#define F367_OFDM_FBERRCMETER_CPT_MMMSB 0xF21900FF + +/* RCFBERCPT2 */ +#define R367_OFDM_RCFBERCPT2 0xF21A +#define F367_OFDM_FBERRCMETER_CPT_MMSB 0xF21A00FF + +/* RCFBERCPT1 */ +#define R367_OFDM_RCFBERCPT1 0xF21B +#define F367_OFDM_FBERRCMETER_CPT_MSB 0xF21B00FF + +/* RCFBERCPT0 */ +#define R367_OFDM_RCFBERCPT0 0xF21C +#define F367_OFDM_FBERRCMETER_CPT_LSB 0xF21C00FF + +/* RCFBERERR2 */ +#define R367_OFDM_RCFBERERR2 0xF21D +#define F367_OFDM_FBERRCMETER_ERR_HI 0xF21D00FF + +/* RCFBERERR1 */ +#define R367_OFDM_RCFBERERR1 0xF21E +#define F367_OFDM_FBERRCMETER_ERR 0xF21E00FF + +/* RCFBERERR0 */ +#define R367_OFDM_RCFBERERR0 0xF21F +#define F367_OFDM_FBERRCMETER_ERR_LO 0xF21F00FF + +/* RCFSTATESM */ +#define R367_OFDM_RCFSTATESM 0xF220 +#define F367_OFDM_RCRSTATE_F 0xF2200080 +#define F367_OFDM_RCRSTATE_E 0xF2200040 +#define F367_OFDM_RCRSTATE_D 0xF2200020 +#define F367_OFDM_RCRSTATE_C 0xF2200010 +#define F367_OFDM_RCRSTATE_B 0xF2200008 +#define F367_OFDM_RCRSTATE_A 0xF2200004 +#define F367_OFDM_RCRSTATE_9 0xF2200002 +#define F367_OFDM_RCRSTATE_8 0xF2200001 + +/* RCFSTATESL */ +#define R367_OFDM_RCFSTATESL 0xF221 +#define F367_OFDM_RCRSTATE_7 0xF2210080 +#define F367_OFDM_RCRSTATE_6 0xF2210040 +#define F367_OFDM_RCRSTATE_5 0xF2210020 +#define F367_OFDM_RCRSTATE_4 0xF2210010 +#define F367_OFDM_RCRSTATE_3 0xF2210008 +#define F367_OFDM_RCRSTATE_2 0xF2210004 +#define F367_OFDM_RCRSTATE_1 0xF2210002 +#define F367_OFDM_RCRSTATE_0 0xF2210001 + +/* RCFSPYBER */ +#define R367_OFDM_RCFSPYBER 0xF222 +#define F367_OFDM_RCFSPYBER_7 0xF2220080 +#define F367_OFDM_SPYRCOBS_XORREAD 0xF2220040 +#define F367_OFDM_FSPYRCBER_OBSMODE 0xF2220020 +#define F367_OFDM_FSPYRCBER_SYNCBYT 0xF2220010 +#define F367_OFDM_FSPYRCBER_UNSYNC 0xF2220008 +#define F367_OFDM_FSPYRCBER_CTIME 0xF2220007 + +/* RCFSPYDISTM */ +#define R367_OFDM_RCFSPYDISTM 0xF223 +#define F367_OFDM_RCPKTTIME_DISTANCE_HI 0xF22300FF + +/* RCFSPYDISTL */ +#define R367_OFDM_RCFSPYDISTL 0xF224 +#define F367_OFDM_RCPKTTIME_DISTANCE_LO 0xF22400FF + +/* RCFSPYOBS7 */ +#define R367_OFDM_RCFSPYOBS7 0xF228 +#define F367_OFDM_RCSPYOBS_SPYFAIL 0xF2280080 +#define F367_OFDM_RCSPYOBS_SPYFAIL1 0xF2280040 +#define F367_OFDM_RCSPYOBS_ERROR 0xF2280020 +#define F367_OFDM_RCSPYOBS_STROUT 0xF2280010 +#define F367_OFDM_RCSPYOBS_RESULTSTATE1 0xF228000F + +/* RCFSPYOBS6 */ +#define R367_OFDM_RCFSPYOBS6 0xF229 +#define F367_OFDM_RCSPYOBS_RESULTSTATE0 0xF22900F0 +#define F367_OFDM_RCSPYOBS_RESULTSTATEM1 0xF229000F + +/* RCFSPYOBS5 */ +#define R367_OFDM_RCFSPYOBS5 0xF22A +#define F367_OFDM_RCSPYOBS_BYTEOFPACKET1 0xF22A00FF + +/* RCFSPYOBS4 */ +#define R367_OFDM_RCFSPYOBS4 0xF22B +#define F367_OFDM_RCSPYOBS_BYTEVALUE1 0xF22B00FF + +/* RCFSPYOBS3 */ +#define R367_OFDM_RCFSPYOBS3 0xF22C +#define F367_OFDM_RCSPYOBS_DATA1 0xF22C00FF + +/* RCFSPYOBS2 */ +#define R367_OFDM_RCFSPYOBS2 0xF22D +#define F367_OFDM_RCSPYOBS_DATA0 0xF22D00FF + +/* RCFSPYOBS1 */ +#define R367_OFDM_RCFSPYOBS1 0xF22E +#define F367_OFDM_RCSPYOBS_DATAM1 0xF22E00FF + +/* RCFSPYOBS0 */ +#define R367_OFDM_RCFSPYOBS0 0xF22F +#define F367_OFDM_RCSPYOBS_DATAM2 0xF22F00FF + +/* TSGENERAL */ +#define R367_TSGENERAL 0xF230 +#define F367_TSGENERAL_7 0xF2300080 +#define F367_TSGENERAL_6 0xF2300040 +#define F367_TSFIFO_BCLK1ALL 0xF2300020 +#define F367_TSGENERAL_4 0xF2300010 +#define F367_MUXSTREAM_OUTMODE 0xF2300008 +#define F367_TSFIFO_PERMPARAL 0xF2300006 +#define F367_RST_REEDSOLO 0xF2300001 + +/* RC1SPEED */ +#define R367_RC1SPEED 0xF231 +#define F367_TSRCFIFO1_OUTSPEED 0xF23100FF + +/* TSGSTATUS */ +#define R367_TSGSTATUS 0xF232 +#define F367_TSGSTATUS_7 0xF2320080 +#define F367_TSGSTATUS_6 0xF2320040 +#define F367_RSMEM_FULL 0xF2320020 +#define F367_RS_MULTCALC 0xF2320010 +#define F367_RSIN_OVERTIME 0xF2320008 +#define F367_TSFIFO3_DEMODSEL 0xF2320004 +#define F367_TSFIFO2_DEMODSEL 0xF2320002 +#define F367_TSFIFO1_DEMODSEL 0xF2320001 + + +/* FECM */ +#define R367_OFDM_FECM 0xF233 +#define F367_OFDM_DSS_DVB 0xF2330080 +#define F367_OFDM_DEMOD_BYPASS 0xF2330040 +#define F367_OFDM_CMP_SLOWMODE 0xF2330020 +#define F367_OFDM_DSS_SRCH 0xF2330010 +#define F367_OFDM_FECM_3 0xF2330008 +#define F367_OFDM_DIFF_MODEVIT 0xF2330004 +#define F367_OFDM_SYNCVIT 0xF2330002 +#define F367_OFDM_I2CSYM 0xF2330001 + +/* VTH12 */ +#define R367_OFDM_VTH12 0xF234 +#define F367_OFDM_VTH_12 0xF23400FF + +/* VTH23 */ +#define R367_OFDM_VTH23 0xF235 +#define F367_OFDM_VTH_23 0xF23500FF + +/* VTH34 */ +#define R367_OFDM_VTH34 0xF236 +#define F367_OFDM_VTH_34 0xF23600FF + +/* VTH56 */ +#define R367_OFDM_VTH56 0xF237 +#define F367_OFDM_VTH_56 0xF23700FF + +/* VTH67 */ +#define R367_OFDM_VTH67 0xF238 +#define F367_OFDM_VTH_67 0xF23800FF + +/* VTH78 */ +#define R367_OFDM_VTH78 0xF239 +#define F367_OFDM_VTH_78 0xF23900FF + +/* VITCURPUN */ +#define R367_OFDM_VITCURPUN 0xF23A +#define F367_OFDM_VIT_MAPPING 0xF23A00E0 +#define F367_OFDM_VIT_CURPUN 0xF23A001F + +/* VERROR */ +#define R367_OFDM_VERROR 0xF23B +#define F367_OFDM_REGERR_VIT 0xF23B00FF + +/* PRVIT */ +#define R367_OFDM_PRVIT 0xF23C +#define F367_OFDM_PRVIT_7 0xF23C0080 +#define F367_OFDM_DIS_VTHLOCK 0xF23C0040 +#define F367_OFDM_E7_8VIT 0xF23C0020 +#define F367_OFDM_E6_7VIT 0xF23C0010 +#define F367_OFDM_E5_6VIT 0xF23C0008 +#define F367_OFDM_E3_4VIT 0xF23C0004 +#define F367_OFDM_E2_3VIT 0xF23C0002 +#define F367_OFDM_E1_2VIT 0xF23C0001 + +/* VAVSRVIT */ +#define R367_OFDM_VAVSRVIT 0xF23D +#define F367_OFDM_AMVIT 0xF23D0080 +#define F367_OFDM_FROZENVIT 0xF23D0040 +#define F367_OFDM_SNVIT 0xF23D0030 +#define F367_OFDM_TOVVIT 0xF23D000C +#define F367_OFDM_HYPVIT 0xF23D0003 + +/* VSTATUSVIT */ +#define R367_OFDM_VSTATUSVIT 0xF23E +#define F367_OFDM_VITERBI_ON 0xF23E0080 +#define F367_OFDM_END_LOOPVIT 0xF23E0040 +#define F367_OFDM_VITERBI_DEPRF 0xF23E0020 +#define F367_OFDM_PRFVIT 0xF23E0010 +#define F367_OFDM_LOCKEDVIT 0xF23E0008 +#define F367_OFDM_VITERBI_DELOCK 0xF23E0004 +#define F367_OFDM_VIT_DEMODSEL 0xF23E0002 +#define F367_OFDM_VITERBI_COMPOUT 0xF23E0001 + +/* VTHINUSE */ +#define R367_OFDM_VTHINUSE 0xF23F +#define F367_OFDM_VIT_INUSE 0xF23F00FF + +/* KDIV12 */ +#define R367_OFDM_KDIV12 0xF240 +#define F367_OFDM_KDIV12_MANUAL 0xF2400080 +#define F367_OFDM_K_DIVIDER_12 0xF240007F + +/* KDIV23 */ +#define R367_OFDM_KDIV23 0xF241 +#define F367_OFDM_KDIV23_MANUAL 0xF2410080 +#define F367_OFDM_K_DIVIDER_23 0xF241007F + +/* KDIV34 */ +#define R367_OFDM_KDIV34 0xF242 +#define F367_OFDM_KDIV34_MANUAL 0xF2420080 +#define F367_OFDM_K_DIVIDER_34 0xF242007F + +/* KDIV56 */ +#define R367_OFDM_KDIV56 0xF243 +#define F367_OFDM_KDIV56_MANUAL 0xF2430080 +#define F367_OFDM_K_DIVIDER_56 0xF243007F + +/* KDIV67 */ +#define R367_OFDM_KDIV67 0xF244 +#define F367_OFDM_KDIV67_MANUAL 0xF2440080 +#define F367_OFDM_K_DIVIDER_67 0xF244007F + +/* KDIV78 */ +#define R367_OFDM_KDIV78 0xF245 +#define F367_OFDM_KDIV78_MANUAL 0xF2450080 +#define F367_OFDM_K_DIVIDER_78 0xF245007F + +/* SIGPOWER */ +#define R367_OFDM_SIGPOWER 0xF246 +#define F367_OFDM_SIGPOWER_MANUAL 0xF2460080 +#define F367_OFDM_SIG_POWER 0xF246007F + +/* DEMAPVIT */ +#define R367_OFDM_DEMAPVIT 0xF247 +#define F367_OFDM_DEMAPVIT_7 0xF2470080 +#define F367_OFDM_K_DIVIDER_VIT 0xF247007F + +/* VITSCALE */ +#define R367_OFDM_VITSCALE 0xF248 +#define F367_OFDM_NVTH_NOSRANGE 0xF2480080 +#define F367_OFDM_VERROR_MAXMODE 0xF2480040 +#define F367_OFDM_KDIV_MODE 0xF2480030 +#define F367_OFDM_NSLOWSN_LOCKED 0xF2480008 +#define F367_OFDM_DELOCK_PRFLOSS 0xF2480004 +#define F367_OFDM_DIS_RSFLOCK 0xF2480002 +#define F367_OFDM_VITSCALE_0 0xF2480001 + +/* FFEC1PRG */ +#define R367_OFDM_FFEC1PRG 0xF249 +#define F367_OFDM_FDSS_DVB 0xF2490080 +#define F367_OFDM_FDSS_SRCH 0xF2490040 +#define F367_OFDM_FFECPROG_5 0xF2490020 +#define F367_OFDM_FFECPROG_4 0xF2490010 +#define F367_OFDM_FFECPROG_3 0xF2490008 +#define F367_OFDM_FFECPROG_2 0xF2490004 +#define F367_OFDM_FTS1_DISABLE 0xF2490002 +#define F367_OFDM_FTS2_DISABLE 0xF2490001 + +/* FVITCURPUN */ +#define R367_OFDM_FVITCURPUN 0xF24A +#define F367_OFDM_FVIT_MAPPING 0xF24A00E0 +#define F367_OFDM_FVIT_CURPUN 0xF24A001F + +/* FVERROR */ +#define R367_OFDM_FVERROR 0xF24B +#define F367_OFDM_FREGERR_VIT 0xF24B00FF + +/* FVSTATUSVIT */ +#define R367_OFDM_FVSTATUSVIT 0xF24C +#define F367_OFDM_FVITERBI_ON 0xF24C0080 +#define F367_OFDM_F1END_LOOPVIT 0xF24C0040 +#define F367_OFDM_FVITERBI_DEPRF 0xF24C0020 +#define F367_OFDM_FPRFVIT 0xF24C0010 +#define F367_OFDM_FLOCKEDVIT 0xF24C0008 +#define F367_OFDM_FVITERBI_DELOCK 0xF24C0004 +#define F367_OFDM_FVIT_DEMODSEL 0xF24C0002 +#define F367_OFDM_FVITERBI_COMPOUT 0xF24C0001 + +/* DEBUG_LT1 */ +#define R367_OFDM_DEBUG_LT1 0xF24D +#define F367_OFDM_DBG_LT1 0xF24D00FF + +/* DEBUG_LT2 */ +#define R367_OFDM_DEBUG_LT2 0xF24E +#define F367_OFDM_DBG_LT2 0xF24E00FF + +/* DEBUG_LT3 */ +#define R367_OFDM_DEBUG_LT3 0xF24F +#define F367_OFDM_DBG_LT3 0xF24F00FF + + /* TSTSFMET */ +#define R367_OFDM_TSTSFMET 0xF250 +#define F367_OFDM_TSTSFEC_METRIQUES 0xF25000FF + + /* SELOUT */ +#define R367_OFDM_SELOUT 0xF252 +#define F367_OFDM_EN_SYNC 0xF2520080 +#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 +#define F367_OFDM_SELOUT_5 0xF2520020 +#define F367_OFDM_SELOUT_4 0xF2520010 +#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 + + /* TSYNC */ +#define R367_OFDM_TSYNC 0xF253 +#define F367_OFDM_CURPUN_INCMODE 0xF2530080 +#define F367_OFDM_CERR_TSTMODE 0xF2530040 +#define F367_OFDM_SHIFTSOF_MODE 0xF2530030 +#define F367_OFDM_SLOWPHA_MODE 0xF2530008 +#define F367_OFDM_PXX_BYPALL 0xF2530004 +#define F367_OFDM_FROTA45_FIRST 0xF2530002 +#define F367_OFDM_TST_BCHERROR 0xF2530001 + + /* TSTERR */ +#define R367_OFDM_TSTERR 0xF254 +#define F367_OFDM_TST_LONGPKT 0xF2540080 +#define F367_OFDM_TST_ISSYION 0xF2540040 +#define F367_OFDM_TST_NPDON 0xF2540020 +#define F367_OFDM_TSTERR_4 0xF2540010 +#define F367_OFDM_TRACEBACK_MODE 0xF2540008 +#define F367_OFDM_TST_RSPARITY 0xF2540004 +#define F367_OFDM_METRIQUE_MODE 0xF2540003 + + /* TSFSYNC */ +#define R367_OFDM_TSFSYNC 0xF255 +#define F367_OFDM_EN_SFECSYNC 0xF2550080 +#define F367_OFDM_EN_SFECDEMAP 0xF2550040 +#define F367_OFDM_SFCERR_TSTMODE 0xF2550020 +#define F367_OFDM_SFECPXX_BYPALL 0xF2550010 +#define F367_OFDM_SFECTSTSYNCHRO_MODE 0xF255000F + + /* TSTSFERR */ +#define R367_OFDM_TSTSFERR 0xF256 +#define F367_OFDM_TSTSTERR_7 0xF2560080 +#define F367_OFDM_TSTSTERR_6 0xF2560040 +#define F367_OFDM_TSTSTERR_5 0xF2560020 +#define F367_OFDM_TSTSTERR_4 0xF2560010 +#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 +#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 +#define F367_OFDM_SFECMETRIQUE_MODE 0xF2560003 + + /* TSTTSSF1 */ +#define R367_OFDM_TSTTSSF1 0xF258 +#define F367_OFDM_TSTERSSF 0xF2580080 +#define F367_OFDM_TSTTSSFEN 0xF2580040 +#define F367_OFDM_SFEC_OUTMODE 0xF2580030 +#define F367_OFDM_XLSF_NOFTHRESHOLD 0xF2580008 +#define F367_OFDM_TSTTSSF_STACKSEL 0xF2580007 + + /* TSTTSSF2 */ +#define R367_OFDM_TSTTSSF2 0xF259 +#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 +#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 +#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 +#define F367_OFDM_TSTTSSF_SELECT 0xF259001F + + /* TSTTSSF3 */ +#define R367_OFDM_TSTTSSF3 0xF25A +#define F367_OFDM_TSTTSSF3_7 0xF25A0080 +#define F367_OFDM_TSTTSSF3_6 0xF25A0040 +#define F367_OFDM_TSTTSSF3_5 0xF25A0020 +#define F367_OFDM_TSTTSSF3_4 0xF25A0010 +#define F367_OFDM_TSTTSSF3_3 0xF25A0008 +#define F367_OFDM_TSTTSSF3_2 0xF25A0004 +#define F367_OFDM_TSTTSSF3_1 0xF25A0002 +#define F367_OFDM_DISSF_CLKENABLE 0xF25A0001 + + /* TSTTS1 */ +#define R367_OFDM_TSTTS1 0xF25C +#define F367_OFDM_TSTERS 0xF25C0080 +#define F367_OFDM_TSFIFO_DSSSYNCB 0xF25C0040 +#define F367_OFDM_TSTTS_FSPYBEFRS 0xF25C0020 +#define F367_OFDM_NFORCE_SYNCBYTE 0xF25C0010 +#define F367_OFDM_XL_NOFTHRESHOLD 0xF25C0008 +#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 +#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 +#define F367_OFDM_TSTTSEN 0xF25C0001 + + /* TSTTS2 */ +#define R367_OFDM_TSTTS2 0xF25D +#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 +#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 +#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 +#define F367_OFDM_TSTTS_SELECT 0xF25D001F + + /* TSTTS3 */ +#define R367_OFDM_TSTTS3 0xF25E +#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 +#define F367_OFDM_TSTTS_NOPKTENE 0xF25E0040 +#define F367_OFDM_TSTTS_ISOLATION 0xF25E0020 +#define F367_OFDM_TSTTS_DISBUG 0xF25E0010 +#define F367_OFDM_TSTTS_NOBADSTART 0xF25E0008 +#define F367_OFDM_TSTTS_STACKSEL 0xF25E0007 + + /* TSTTS4 */ +#define R367_OFDM_TSTTS4 0xF25F +#define F367_OFDM_TSTTS4_7 0xF25F0080 +#define F367_OFDM_TSTTS4_6 0xF25F0040 +#define F367_OFDM_TSTTS4_5 0xF25F0020 +#define F367_OFDM_TSTTS_DISDSTATE 0xF25F0010 +#define F367_OFDM_TSTTS_FASTNOSYNC 0xF25F0008 +#define F367_OFDM_EXT_FECSPYIN 0xF25F0004 +#define F367_OFDM_TSTTS_NODPZERO 0xF25F0002 +#define F367_OFDM_TSTTS_NODIV3 0xF25F0001 + + /* TSTTSRC */ +#define R367_OFDM_TSTTSRC 0xF26C +#define F367_OFDM_TSTTSRC_7 0xF26C0080 +#define F367_OFDM_TSRCFIFO_DSSSYNCB 0xF26C0040 +#define F367_OFDM_TSRCFIFO_DPUNACTIVE 0xF26C0020 +#define F367_OFDM_TSRCFIFO_DELSPEEDUP 0xF26C0010 +#define F367_OFDM_TSTTSRC_NODIV3 0xF26C0008 +#define F367_OFDM_TSTTSRC_FRFORCEPKT 0xF26C0004 +#define F367_OFDM_SAT25_SDDORIGINE 0xF26C0002 +#define F367_OFDM_TSTTSRC_INACTIVE 0xF26C0001 + + /* TSTTSRS */ +#define R367_OFDM_TSTTSRS 0xF26D +#define F367_OFDM_TSTTSRS_7 0xF26D0080 +#define F367_OFDM_TSTTSRS_6 0xF26D0040 +#define F367_OFDM_TSTTSRS_5 0xF26D0020 +#define F367_OFDM_TSTTSRS_4 0xF26D0010 +#define F367_OFDM_TSTTSRS_3 0xF26D0008 +#define F367_OFDM_TSTTSRS_2 0xF26D0004 +#define F367_OFDM_TSTRS_DISRS2 0xF26D0002 +#define F367_OFDM_TSTRS_DISRS1 0xF26D0001 + +/* TSSTATEM */ +#define R367_OFDM_TSSTATEM 0xF270 +#define F367_OFDM_TSDIL_ON 0xF2700080 +#define F367_OFDM_TSSKIPRS_ON 0xF2700040 +#define F367_OFDM_TSRS_ON 0xF2700020 +#define F367_OFDM_TSDESCRAMB_ON 0xF2700010 +#define F367_OFDM_TSFRAME_MODE 0xF2700008 +#define F367_OFDM_TS_DISABLE 0xF2700004 +#define F367_OFDM_TSACM_MODE 0xF2700002 +#define F367_OFDM_TSOUT_NOSYNC 0xF2700001 + +/* TSSTATEL */ +#define R367_OFDM_TSSTATEL 0xF271 +#define F367_OFDM_TSNOSYNCBYTE 0xF2710080 +#define F367_OFDM_TSPARITY_ON 0xF2710040 +#define F367_OFDM_TSSYNCOUTRS_ON 0xF2710020 +#define F367_OFDM_TSDVBS2_MODE 0xF2710010 +#define F367_OFDM_TSISSYI_ON 0xF2710008 +#define F367_OFDM_TSNPD_ON 0xF2710004 +#define F367_OFDM_TSCRC8_ON 0xF2710002 +#define F367_OFDM_TSDSS_PACKET 0xF2710001 + +/* TSCFGH */ +#define R367_OFDM_TSCFGH 0xF272 +#define F367_OFDM_TSFIFO_DVBCI 0xF2720080 +#define F367_OFDM_TSFIFO_SERIAL 0xF2720040 +#define F367_OFDM_TSFIFO_TEIUPDATE 0xF2720020 +#define F367_OFDM_TSFIFO_DUTY50 0xF2720010 +#define F367_OFDM_TSFIFO_HSGNLOUT 0xF2720008 +#define F367_OFDM_TSFIFO_ERRMODE 0xF2720006 +#define F367_OFDM_RST_HWARE 0xF2720001 + +/* TSCFGM */ +#define R367_OFDM_TSCFGM 0xF273 +#define F367_OFDM_TSFIFO_MANSPEED 0xF27300C0 +#define F367_OFDM_TSFIFO_PERMDATA 0xF2730020 +#define F367_OFDM_TSFIFO_NONEWSGNL 0xF2730010 +#define F367_OFDM_TSFIFO_BITSPEED 0xF2730008 +#define F367_OFDM_NPD_SPECDVBS2 0xF2730004 +#define F367_OFDM_TSFIFO_STOPCKDIS 0xF2730002 +#define F367_OFDM_TSFIFO_INVDATA 0xF2730001 + +/* TSCFGL */ +#define R367_OFDM_TSCFGL 0xF274 +#define F367_OFDM_TSFIFO_BCLKDEL1CK 0xF27400C0 +#define F367_OFDM_BCHERROR_MODE 0xF2740030 +#define F367_OFDM_TSFIFO_NSGNL2DATA 0xF2740008 +#define F367_OFDM_TSFIFO_EMBINDVB 0xF2740004 +#define F367_OFDM_TSFIFO_DPUNACT 0xF2740002 +#define F367_OFDM_TSFIFO_NPDOFF 0xF2740001 + +/* TSSYNC */ +#define R367_OFDM_TSSYNC 0xF275 +#define F367_OFDM_TSFIFO_PERMUTE 0xF2750080 +#define F367_OFDM_TSFIFO_FISCR3B 0xF2750060 +#define F367_OFDM_TSFIFO_SYNCMODE 0xF2750018 +#define F367_OFDM_TSFIFO_SYNCSEL 0xF2750007 + +/* TSINSDELH */ +#define R367_OFDM_TSINSDELH 0xF276 +#define F367_OFDM_TSDEL_SYNCBYTE 0xF2760080 +#define F367_OFDM_TSDEL_XXHEADER 0xF2760040 +#define F367_OFDM_TSDEL_BBHEADER 0xF2760020 +#define F367_OFDM_TSDEL_DATAFIELD 0xF2760010 +#define F367_OFDM_TSINSDEL_ISCR 0xF2760008 +#define F367_OFDM_TSINSDEL_NPD 0xF2760004 +#define F367_OFDM_TSINSDEL_RSPARITY 0xF2760002 +#define F367_OFDM_TSINSDEL_CRC8 0xF2760001 + +/* TSINSDELM */ +#define R367_OFDM_TSINSDELM 0xF277 +#define F367_OFDM_TSINS_BBPADDING 0xF2770080 +#define F367_OFDM_TSINS_BCHFEC 0xF2770040 +#define F367_OFDM_TSINS_LDPCFEC 0xF2770020 +#define F367_OFDM_TSINS_EMODCOD 0xF2770010 +#define F367_OFDM_TSINS_TOKEN 0xF2770008 +#define F367_OFDM_TSINS_XXXERR 0xF2770004 +#define F367_OFDM_TSINS_MATYPE 0xF2770002 +#define F367_OFDM_TSINS_UPL 0xF2770001 + +/* TSINSDELL */ +#define R367_OFDM_TSINSDELL 0xF278 +#define F367_OFDM_TSINS_DFL 0xF2780080 +#define F367_OFDM_TSINS_SYNCD 0xF2780040 +#define F367_OFDM_TSINS_BLOCLEN 0xF2780020 +#define F367_OFDM_TSINS_SIGPCOUNT 0xF2780010 +#define F367_OFDM_TSINS_FIFO 0xF2780008 +#define F367_OFDM_TSINS_REALPACK 0xF2780004 +#define F367_OFDM_TSINS_TSCONFIG 0xF2780002 +#define F367_OFDM_TSINS_LATENCY 0xF2780001 + +/* TSDIVN */ +#define R367_OFDM_TSDIVN 0xF279 +#define F367_OFDM_TSFIFO_LOWSPEED 0xF2790080 +#define F367_OFDM_BYTE_OVERSAMPLING 0xF2790070 +#define F367_OFDM_TSMANUAL_PACKETNBR 0xF279000F + +/* TSDIVPM */ +#define R367_OFDM_TSDIVPM 0xF27A +#define F367_OFDM_TSMANUAL_P_HI 0xF27A00FF + +/* TSDIVPL */ +#define R367_OFDM_TSDIVPL 0xF27B +#define F367_OFDM_TSMANUAL_P_LO 0xF27B00FF + +/* TSDIVQM */ +#define R367_OFDM_TSDIVQM 0xF27C +#define F367_OFDM_TSMANUAL_Q_HI 0xF27C00FF + +/* TSDIVQL */ +#define R367_OFDM_TSDIVQL 0xF27D +#define F367_OFDM_TSMANUAL_Q_LO 0xF27D00FF + +/* TSDILSTKM */ +#define R367_OFDM_TSDILSTKM 0xF27E +#define F367_OFDM_TSFIFO_DILSTK_HI 0xF27E00FF + +/* TSDILSTKL */ +#define R367_OFDM_TSDILSTKL 0xF27F +#define F367_OFDM_TSFIFO_DILSTK_LO 0xF27F00FF + +/* TSSPEED */ +#define R367_OFDM_TSSPEED 0xF280 +#define F367_OFDM_TSFIFO_OUTSPEED 0xF28000FF + +/* TSSTATUS */ +#define R367_OFDM_TSSTATUS 0xF281 +#define F367_OFDM_TSFIFO_LINEOK 0xF2810080 +#define F367_OFDM_TSFIFO_ERROR 0xF2810040 +#define F367_OFDM_TSFIFO_DATA7 0xF2810020 +#define F367_OFDM_TSFIFO_NOSYNC 0xF2810010 +#define F367_OFDM_ISCR_INITIALIZED 0xF2810008 +#define F367_OFDM_ISCR_UPDATED 0xF2810004 +#define F367_OFDM_SOFFIFO_UNREGUL 0xF2810002 +#define F367_OFDM_DIL_READY 0xF2810001 + +/* TSSTATUS2 */ +#define R367_OFDM_TSSTATUS2 0xF282 +#define F367_OFDM_TSFIFO_DEMODSEL 0xF2820080 +#define F367_OFDM_TSFIFOSPEED_STORE 0xF2820040 +#define F367_OFDM_DILXX_RESET 0xF2820020 +#define F367_OFDM_TSSERIAL_IMPOSSIBLE 0xF2820010 +#define F367_OFDM_TSFIFO_UNDERSPEED 0xF2820008 +#define F367_OFDM_BITSPEED_EVENT 0xF2820004 +#define F367_OFDM_UL_SCRAMBDETECT 0xF2820002 +#define F367_OFDM_ULDTV67_FALSELOCK 0xF2820001 + +/* TSBITRATEM */ +#define R367_OFDM_TSBITRATEM 0xF283 +#define F367_OFDM_TSFIFO_BITRATE_HI 0xF28300FF + +/* TSBITRATEL */ +#define R367_OFDM_TSBITRATEL 0xF284 +#define F367_OFDM_TSFIFO_BITRATE_LO 0xF28400FF + +/* TSPACKLENM */ +#define R367_OFDM_TSPACKLENM 0xF285 +#define F367_OFDM_TSFIFO_PACKCPT 0xF28500E0 +#define F367_OFDM_DIL_RPLEN_HI 0xF285001F + +/* TSPACKLENL */ +#define R367_OFDM_TSPACKLENL 0xF286 +#define F367_OFDM_DIL_RPLEN_LO 0xF28600FF + +/* TSBLOCLENM */ +#define R367_OFDM_TSBLOCLENM 0xF287 +#define F367_OFDM_TSFIFO_PFLEN_HI 0xF28700FF + +/* TSBLOCLENL */ +#define R367_OFDM_TSBLOCLENL 0xF288 +#define F367_OFDM_TSFIFO_PFLEN_LO 0xF28800FF + +/* TSDLYH */ +#define R367_OFDM_TSDLYH 0xF289 +#define F367_OFDM_SOFFIFO_TSTIMEVALID 0xF2890080 +#define F367_OFDM_SOFFIFO_SPEEDUP 0xF2890040 +#define F367_OFDM_SOFFIFO_STOP 0xF2890020 +#define F367_OFDM_SOFFIFO_REGULATED 0xF2890010 +#define F367_OFDM_SOFFIFO_REALSBOFF_HI 0xF289000F + +/* TSDLYM */ +#define R367_OFDM_TSDLYM 0xF28A +#define F367_OFDM_SOFFIFO_REALSBOFF_MED 0xF28A00FF + +/* TSDLYL */ +#define R367_OFDM_TSDLYL 0xF28B +#define F367_OFDM_SOFFIFO_REALSBOFF_LO 0xF28B00FF + +/* TSNPDAV */ +#define R367_OFDM_TSNPDAV 0xF28C +#define F367_OFDM_TSNPD_AVERAGE 0xF28C00FF + +/* TSBUFSTATH */ +#define R367_OFDM_TSBUFSTATH 0xF28D +#define F367_OFDM_TSISCR_3BYTES 0xF28D0080 +#define F367_OFDM_TSISCR_NEWDATA 0xF28D0040 +#define F367_OFDM_TSISCR_BUFSTAT_HI 0xF28D003F + +/* TSBUFSTATM */ +#define R367_OFDM_TSBUFSTATM 0xF28E +#define F367_OFDM_TSISCR_BUFSTAT_MED 0xF28E00FF + +/* TSBUFSTATL */ +#define R367_OFDM_TSBUFSTATL 0xF28F +#define F367_OFDM_TSISCR_BUFSTAT_LO 0xF28F00FF + +/* TSDEBUGM */ +#define R367_OFDM_TSDEBUGM 0xF290 +#define F367_OFDM_TSFIFO_ILLPACKET 0xF2900080 +#define F367_OFDM_DIL_NOSYNC 0xF2900040 +#define F367_OFDM_DIL_ISCR 0xF2900020 +#define F367_OFDM_DILOUT_BSYNCB 0xF2900010 +#define F367_OFDM_TSFIFO_EMPTYPKT 0xF2900008 +#define F367_OFDM_TSFIFO_EMPTYRD 0xF2900004 +#define F367_OFDM_SOFFIFO_STOPM 0xF2900002 +#define F367_OFDM_SOFFIFO_SPEEDUPM 0xF2900001 + +/* TSDEBUGL */ +#define R367_OFDM_TSDEBUGL 0xF291 +#define F367_OFDM_TSFIFO_PACKLENFAIL 0xF2910080 +#define F367_OFDM_TSFIFO_SYNCBFAIL 0xF2910040 +#define F367_OFDM_TSFIFO_VITLIBRE 0xF2910020 +#define F367_OFDM_TSFIFO_BOOSTSPEEDM 0xF2910010 +#define F367_OFDM_TSFIFO_UNDERSPEEDM 0xF2910008 +#define F367_OFDM_TSFIFO_ERROR_EVNT 0xF2910004 +#define F367_OFDM_TSFIFO_FULL 0xF2910002 +#define F367_OFDM_TSFIFO_OVERFLOWM 0xF2910001 + +/* TSDLYSETH */ +#define R367_OFDM_TSDLYSETH 0xF292 +#define F367_OFDM_SOFFIFO_OFFSET 0xF29200E0 +#define F367_OFDM_SOFFIFO_SYMBOFFSET_HI 0xF292001F + +/* TSDLYSETM */ +#define R367_OFDM_TSDLYSETM 0xF293 +#define F367_OFDM_SOFFIFO_SYMBOFFSET_MED 0xF29300FF + +/* TSDLYSETL */ +#define R367_OFDM_TSDLYSETL 0xF294 +#define F367_OFDM_SOFFIFO_SYMBOFFSET_LO 0xF29400FF + +/* TSOBSCFG */ +#define R367_OFDM_TSOBSCFG 0xF295 +#define F367_OFDM_TSFIFO_OBSCFG 0xF29500FF + +/* TSOBSM */ +#define R367_OFDM_TSOBSM 0xF296 +#define F367_OFDM_TSFIFO_OBSDATA_HI 0xF29600FF + +/* TSOBSL */ +#define R367_OFDM_TSOBSL 0xF297 +#define F367_OFDM_TSFIFO_OBSDATA_LO 0xF29700FF + +/* ERRCTRL1 */ +#define R367_OFDM_ERRCTRL1 0xF298 +#define F367_OFDM_ERR_SRC1 0xF29800F0 +#define F367_OFDM_ERRCTRL1_3 0xF2980008 +#define F367_OFDM_NUM_EVT1 0xF2980007 + +/* ERRCNT1H */ +#define R367_OFDM_ERRCNT1H 0xF299 +#define F367_OFDM_ERRCNT1_OLDVALUE 0xF2990080 +#define F367_OFDM_ERR_CNT1 0xF299007F + +/* ERRCNT1M */ +#define R367_OFDM_ERRCNT1M 0xF29A +#define F367_OFDM_ERR_CNT1_HI 0xF29A00FF + +/* ERRCNT1L */ +#define R367_OFDM_ERRCNT1L 0xF29B +#define F367_OFDM_ERR_CNT1_LO 0xF29B00FF + +/* ERRCTRL2 */ +#define R367_OFDM_ERRCTRL2 0xF29C +#define F367_OFDM_ERR_SRC2 0xF29C00F0 +#define F367_OFDM_ERRCTRL2_3 0xF29C0008 +#define F367_OFDM_NUM_EVT2 0xF29C0007 + +/* ERRCNT2H */ +#define R367_OFDM_ERRCNT2H 0xF29D +#define F367_OFDM_ERRCNT2_OLDVALUE 0xF29D0080 +#define F367_OFDM_ERR_CNT2_HI 0xF29D007F + +/* ERRCNT2M */ +#define R367_OFDM_ERRCNT2M 0xF29E +#define F367_OFDM_ERR_CNT2_MED 0xF29E00FF + +/* ERRCNT2L */ +#define R367_OFDM_ERRCNT2L 0xF29F +#define F367_OFDM_ERR_CNT2_LO 0xF29F00FF + +/* FECSPY */ +#define R367_OFDM_FECSPY 0xF2A0 +#define F367_OFDM_SPY_ENABLE 0xF2A00080 +#define F367_OFDM_NO_SYNCBYTE 0xF2A00040 +#define F367_OFDM_SERIAL_MODE 0xF2A00020 +#define F367_OFDM_UNUSUAL_PACKET 0xF2A00010 +#define F367_OFDM_BERMETER_DATAMODE 0xF2A0000C +#define F367_OFDM_BERMETER_LMODE 0xF2A00002 +#define F367_OFDM_BERMETER_RESET 0xF2A00001 + +/* FSPYCFG */ +#define R367_OFDM_FSPYCFG 0xF2A1 +#define F367_OFDM_FECSPY_INPUT 0xF2A100C0 +#define F367_OFDM_RST_ON_ERROR 0xF2A10020 +#define F367_OFDM_ONE_SHOT 0xF2A10010 +#define F367_OFDM_I2C_MOD 0xF2A1000C +#define F367_OFDM_SPY_HYSTERESIS 0xF2A10003 + +/* FSPYDATA */ +#define R367_OFDM_FSPYDATA 0xF2A2 +#define F367_OFDM_SPY_STUFFING 0xF2A20080 +#define F367_OFDM_NOERROR_PKTJITTER 0xF2A20040 +#define F367_OFDM_SPY_CNULLPKT 0xF2A20020 +#define F367_OFDM_SPY_OUTDATA_MODE 0xF2A2001F + +/* FSPYOUT */ +#define R367_OFDM_FSPYOUT 0xF2A3 +#define F367_OFDM_FSPY_DIRECT 0xF2A30080 +#define F367_OFDM_FSPYOUT_6 0xF2A30040 +#define F367_OFDM_SPY_OUTDATA_BUS 0xF2A30038 +#define F367_OFDM_STUFF_MODE 0xF2A30007 + +/* FSTATUS */ +#define R367_OFDM_FSTATUS 0xF2A4 +#define F367_OFDM_SPY_ENDSIM 0xF2A40080 +#define F367_OFDM_VALID_SIM 0xF2A40040 +#define F367_OFDM_FOUND_SIGNAL 0xF2A40020 +#define F367_OFDM_DSS_SYNCBYTE 0xF2A40010 +#define F367_OFDM_RESULT_STATE 0xF2A4000F + +/* FGOODPACK */ +#define R367_OFDM_FGOODPACK 0xF2A5 +#define F367_OFDM_FGOOD_PACKET 0xF2A500FF + +/* FPACKCNT */ +#define R367_OFDM_FPACKCNT 0xF2A6 +#define F367_OFDM_FPACKET_COUNTER 0xF2A600FF + +/* FSPYMISC */ +#define R367_OFDM_FSPYMISC 0xF2A7 +#define F367_OFDM_FLABEL_COUNTER 0xF2A700FF + +/* FBERCPT4 */ +#define R367_OFDM_FBERCPT4 0xF2A8 +#define F367_OFDM_FBERMETER_CPT5 0xF2A800FF + +/* FBERCPT3 */ +#define R367_OFDM_FBERCPT3 0xF2A9 +#define F367_OFDM_FBERMETER_CPT4 0xF2A900FF + +/* FBERCPT2 */ +#define R367_OFDM_FBERCPT2 0xF2AA +#define F367_OFDM_FBERMETER_CPT3 0xF2AA00FF + +/* FBERCPT1 */ +#define R367_OFDM_FBERCPT1 0xF2AB +#define F367_OFDM_FBERMETER_CPT2 0xF2AB00FF + +/* FBERCPT0 */ +#define R367_OFDM_FBERCPT0 0xF2AC +#define F367_OFDM_FBERMETER_CPT1 0xF2AC00FF + +/* FBERERR2 */ +#define R367_OFDM_FBERERR2 0xF2AD +#define F367_OFDM_FBERMETER_ERR_HI 0xF2AD00FF + +/* FBERERR1 */ +#define R367_OFDM_FBERERR1 0xF2AE +#define F367_OFDM_FBERMETER_ERR_MED 0xF2AE00FF + +/* FBERERR0 */ +#define R367_OFDM_FBERERR0 0xF2AF +#define F367_OFDM_FBERMETER_ERR_LO 0xF2AF00FF + +/* FSTATESM */ +#define R367_OFDM_FSTATESM 0xF2B0 +#define F367_OFDM_RSTATE_F 0xF2B00080 +#define F367_OFDM_RSTATE_E 0xF2B00040 +#define F367_OFDM_RSTATE_D 0xF2B00020 +#define F367_OFDM_RSTATE_C 0xF2B00010 +#define F367_OFDM_RSTATE_B 0xF2B00008 +#define F367_OFDM_RSTATE_A 0xF2B00004 +#define F367_OFDM_RSTATE_9 0xF2B00002 +#define F367_OFDM_RSTATE_8 0xF2B00001 + +/* FSTATESL */ +#define R367_OFDM_FSTATESL 0xF2B1 +#define F367_OFDM_RSTATE_7 0xF2B10080 +#define F367_OFDM_RSTATE_6 0xF2B10040 +#define F367_OFDM_RSTATE_5 0xF2B10020 +#define F367_OFDM_RSTATE_4 0xF2B10010 +#define F367_OFDM_RSTATE_3 0xF2B10008 +#define F367_OFDM_RSTATE_2 0xF2B10004 +#define F367_OFDM_RSTATE_1 0xF2B10002 +#define F367_OFDM_RSTATE_0 0xF2B10001 + +/* FSPYBER */ +#define R367_OFDM_FSPYBER 0xF2B2 +#define F367_OFDM_FSPYBER_7 0xF2B20080 +#define F367_OFDM_FSPYOBS_XORREAD 0xF2B20040 +#define F367_OFDM_FSPYBER_OBSMODE 0xF2B20020 +#define F367_OFDM_FSPYBER_SYNCBYTE 0xF2B20010 +#define F367_OFDM_FSPYBER_UNSYNC 0xF2B20008 +#define F367_OFDM_FSPYBER_CTIME 0xF2B20007 + +/* FSPYDISTM */ +#define R367_OFDM_FSPYDISTM 0xF2B3 +#define F367_OFDM_PKTTIME_DISTANCE_HI 0xF2B300FF + +/* FSPYDISTL */ +#define R367_OFDM_FSPYDISTL 0xF2B4 +#define F367_OFDM_PKTTIME_DISTANCE_LO 0xF2B400FF + +/* FSPYOBS7 */ +#define R367_OFDM_FSPYOBS7 0xF2B8 +#define F367_OFDM_FSPYOBS_SPYFAIL 0xF2B80080 +#define F367_OFDM_FSPYOBS_SPYFAIL1 0xF2B80040 +#define F367_OFDM_FSPYOBS_ERROR 0xF2B80020 +#define F367_OFDM_FSPYOBS_STROUT 0xF2B80010 +#define F367_OFDM_FSPYOBS_RESULTSTATE1 0xF2B8000F + +/* FSPYOBS6 */ +#define R367_OFDM_FSPYOBS6 0xF2B9 +#define F367_OFDM_FSPYOBS_RESULTSTATE0 0xF2B900F0 +#define F367_OFDM_FSPYOBS_RESULTSTATEM1 0xF2B9000F + +/* FSPYOBS5 */ +#define R367_OFDM_FSPYOBS5 0xF2BA +#define F367_OFDM_FSPYOBS_BYTEOFPACKET1 0xF2BA00FF + +/* FSPYOBS4 */ +#define R367_OFDM_FSPYOBS4 0xF2BB +#define F367_OFDM_FSPYOBS_BYTEVALUE1 0xF2BB00FF + +/* FSPYOBS3 */ +#define R367_OFDM_FSPYOBS3 0xF2BC +#define F367_OFDM_FSPYOBS_DATA1 0xF2BC00FF + +/* FSPYOBS2 */ +#define R367_OFDM_FSPYOBS2 0xF2BD +#define F367_OFDM_FSPYOBS_DATA0 0xF2BD00FF + +/* FSPYOBS1 */ +#define R367_OFDM_FSPYOBS1 0xF2BE +#define F367_OFDM_FSPYOBS_DATAM1 0xF2BE00FF + +/* FSPYOBS0 */ +#define R367_OFDM_FSPYOBS0 0xF2BF +#define F367_OFDM_FSPYOBS_DATAM2 0xF2BF00FF + +/* SFDEMAP */ +#define R367_OFDM_SFDEMAP 0xF2C0 +#define F367_OFDM_SFDEMAP_7 0xF2C00080 +#define F367_OFDM_SFEC_K_DIVIDER_VIT 0xF2C0007F + +/* SFERROR */ +#define R367_OFDM_SFERROR 0xF2C1 +#define F367_OFDM_SFEC_REGERR_VIT 0xF2C100FF + +/* SFAVSR */ +#define R367_OFDM_SFAVSR 0xF2C2 +#define F367_OFDM_SFEC_SUMERRORS 0xF2C20080 +#define F367_OFDM_SERROR_MAXMODE 0xF2C20040 +#define F367_OFDM_SN_SFEC 0xF2C20030 +#define F367_OFDM_KDIV_MODE_SFEC 0xF2C2000C +#define F367_OFDM_SFAVSR_1 0xF2C20002 +#define F367_OFDM_SFAVSR_0 0xF2C20001 + +/* SFECSTATUS */ +#define R367_OFDM_SFECSTATUS 0xF2C3 +#define F367_OFDM_SFEC_ON 0xF2C30080 +#define F367_OFDM_SFSTATUS_6 0xF2C30040 +#define F367_OFDM_SFSTATUS_5 0xF2C30020 +#define F367_OFDM_SFSTATUS_4 0xF2C30010 +#define F367_OFDM_LOCKEDSFEC 0xF2C30008 +#define F367_OFDM_SFEC_DELOCK 0xF2C30004 +#define F367_OFDM_SFEC_DEMODSEL1 0xF2C30002 +#define F367_OFDM_SFEC_OVFON 0xF2C30001 + +/* SFKDIV12 */ +#define R367_OFDM_SFKDIV12 0xF2C4 +#define F367_OFDM_SFECKDIV12_MAN 0xF2C40080 +#define F367_OFDM_SFEC_K_DIVIDER_12 0xF2C4007F + +/* SFKDIV23 */ +#define R367_OFDM_SFKDIV23 0xF2C5 +#define F367_OFDM_SFECKDIV23_MAN 0xF2C50080 +#define F367_OFDM_SFEC_K_DIVIDER_23 0xF2C5007F + +/* SFKDIV34 */ +#define R367_OFDM_SFKDIV34 0xF2C6 +#define F367_OFDM_SFECKDIV34_MAN 0xF2C60080 +#define F367_OFDM_SFEC_K_DIVIDER_34 0xF2C6007F + +/* SFKDIV56 */ +#define R367_OFDM_SFKDIV56 0xF2C7 +#define F367_OFDM_SFECKDIV56_MAN 0xF2C70080 +#define F367_OFDM_SFEC_K_DIVIDER_56 0xF2C7007F + +/* SFKDIV67 */ +#define R367_OFDM_SFKDIV67 0xF2C8 +#define F367_OFDM_SFECKDIV67_MAN 0xF2C80080 +#define F367_OFDM_SFEC_K_DIVIDER_67 0xF2C8007F + +/* SFKDIV78 */ +#define R367_OFDM_SFKDIV78 0xF2C9 +#define F367_OFDM_SFECKDIV78_MAN 0xF2C90080 +#define F367_OFDM_SFEC_K_DIVIDER_78 0xF2C9007F + +/* SFDILSTKM */ +#define R367_OFDM_SFDILSTKM 0xF2CA +#define F367_OFDM_SFEC_PACKCPT 0xF2CA00E0 +#define F367_OFDM_SFEC_DILSTK_HI 0xF2CA001F + +/* SFDILSTKL */ +#define R367_OFDM_SFDILSTKL 0xF2CB +#define F367_OFDM_SFEC_DILSTK_LO 0xF2CB00FF + +/* SFSTATUS */ +#define R367_OFDM_SFSTATUS 0xF2CC +#define F367_OFDM_SFEC_LINEOK 0xF2CC0080 +#define F367_OFDM_SFEC_ERROR 0xF2CC0040 +#define F367_OFDM_SFEC_DATA7 0xF2CC0020 +#define F367_OFDM_SFEC_OVERFLOW 0xF2CC0010 +#define F367_OFDM_SFEC_DEMODSEL2 0xF2CC0008 +#define F367_OFDM_SFEC_NOSYNC 0xF2CC0004 +#define F367_OFDM_SFEC_UNREGULA 0xF2CC0002 +#define F367_OFDM_SFEC_READY 0xF2CC0001 + +/* SFDLYH */ +#define R367_OFDM_SFDLYH 0xF2CD +#define F367_OFDM_SFEC_TSTIMEVALID 0xF2CD0080 +#define F367_OFDM_SFEC_SPEEDUP 0xF2CD0040 +#define F367_OFDM_SFEC_STOP 0xF2CD0020 +#define F367_OFDM_SFEC_REGULATED 0xF2CD0010 +#define F367_OFDM_SFEC_REALSYMBOFFSET 0xF2CD000F + +/* SFDLYM */ +#define R367_OFDM_SFDLYM 0xF2CE +#define F367_OFDM_SFEC_REALSYMBOFFSET_HI 0xF2CE00FF + +/* SFDLYL */ +#define R367_OFDM_SFDLYL 0xF2CF +#define F367_OFDM_SFEC_REALSYMBOFFSET_LO 0xF2CF00FF + +/* SFDLYSETH */ +#define R367_OFDM_SFDLYSETH 0xF2D0 +#define F367_OFDM_SFEC_OFFSET 0xF2D000E0 +#define F367_OFDM_SFECDLYSETH_4 0xF2D00010 +#define F367_OFDM_RST_SFEC 0xF2D00008 +#define F367_OFDM_SFECDLYSETH_2 0xF2D00004 +#define F367_OFDM_SFEC_DISABLE 0xF2D00002 +#define F367_OFDM_SFEC_UNREGUL 0xF2D00001 + +/* SFDLYSETM */ +#define R367_OFDM_SFDLYSETM 0xF2D1 +#define F367_OFDM_SFECDLYSETM_7 0xF2D10080 +#define F367_OFDM_SFEC_SYMBOFFSET_HI 0xF2D1007F + +/* SFDLYSETL */ +#define R367_OFDM_SFDLYSETL 0xF2D2 +#define F367_OFDM_SFEC_SYMBOFFSET_LO 0xF2D200FF + +/* SFOBSCFG */ +#define R367_OFDM_SFOBSCFG 0xF2D3 +#define F367_OFDM_SFEC_OBSCFG 0xF2D300FF + +/* SFOBSM */ +#define R367_OFDM_SFOBSM 0xF2D4 +#define F367_OFDM_SFEC_OBSDATA_HI 0xF2D400FF + +/* SFOBSL */ +#define R367_OFDM_SFOBSL 0xF2D5 +#define F367_OFDM_SFEC_OBSDATA_LO 0xF2D500FF + +/* SFECINFO */ +#define R367_OFDM_SFECINFO 0xF2D6 +#define F367_OFDM_SFECINFO_7 0xF2D60080 +#define F367_OFDM_SFEC_SYNCDLSB 0xF2D60070 +#define F367_OFDM_SFCE_S1CPHASE 0xF2D6000F + +/* SFERRCTRL */ +#define R367_OFDM_SFERRCTRL 0xF2D8 +#define F367_OFDM_SFEC_ERR_SOURCE 0xF2D800F0 +#define F367_OFDM_SFERRCTRL_3 0xF2D80008 +#define F367_OFDM_SFEC_NUM_EVENT 0xF2D80007 + +/* SFERRCNTH */ +#define R367_OFDM_SFERRCNTH 0xF2D9 +#define F367_OFDM_SFERRC_OLDVALUE 0xF2D90080 +#define F367_OFDM_SFEC_ERR_CNT 0xF2D9007F + +/* SFERRCNTM */ +#define R367_OFDM_SFERRCNTM 0xF2DA +#define F367_OFDM_SFEC_ERR_CNT_HI 0xF2DA00FF + +/* SFERRCNTL */ +#define R367_OFDM_SFERRCNTL 0xF2DB +#define F367_OFDM_SFEC_ERR_CNT_LO 0xF2DB00FF + +/* SYMBRATEM */ +#define R367_OFDM_SYMBRATEM 0xF2E0 +#define F367_OFDM_DEFGEN_SYMBRATE_HI 0xF2E000FF + +/* SYMBRATEL */ +#define R367_OFDM_SYMBRATEL 0xF2E1 +#define F367_OFDM_DEFGEN_SYMBRATE_LO 0xF2E100FF + +/* SYMBSTATUS */ +#define R367_OFDM_SYMBSTATUS 0xF2E2 +#define F367_OFDM_SYMBDLINE2_OFF 0xF2E20080 +#define F367_OFDM_SDDL_REINIT1 0xF2E20040 +#define F367_OFDM_SDD_REINIT1 0xF2E20020 +#define F367_OFDM_TOKENID_ERROR 0xF2E20010 +#define F367_OFDM_SYMBRATE_OVERFLOW 0xF2E20008 +#define F367_OFDM_SYMBRATE_UNDERFLOW 0xF2E20004 +#define F367_OFDM_TOKENID_RSTEVENT 0xF2E20002 +#define F367_OFDM_TOKENID_RESET1 0xF2E20001 + +/* SYMBCFG */ +#define R367_OFDM_SYMBCFG 0xF2E3 +#define F367_OFDM_SYMBCFG_7 0xF2E30080 +#define F367_OFDM_SYMBCFG_6 0xF2E30040 +#define F367_OFDM_SYMBCFG_5 0xF2E30020 +#define F367_OFDM_SYMBCFG_4 0xF2E30010 +#define F367_OFDM_SYMRATE_FSPEED 0xF2E3000C +#define F367_OFDM_SYMRATE_SSPEED 0xF2E30003 + +/* SYMBFIFOM */ +#define R367_OFDM_SYMBFIFOM 0xF2E4 +#define F367_OFDM_SYMBFIFOM_7 0xF2E40080 +#define F367_OFDM_SYMBFIFOM_6 0xF2E40040 +#define F367_OFDM_DEFGEN_SYMFIFO_HI 0xF2E4003F + +/* SYMBFIFOL */ +#define R367_OFDM_SYMBFIFOL 0xF2E5 +#define F367_OFDM_DEFGEN_SYMFIFO_LO 0xF2E500FF + +/* SYMBOFFSM */ +#define R367_OFDM_SYMBOFFSM 0xF2E6 +#define F367_OFDM_TOKENID_RESET2 0xF2E60080 +#define F367_OFDM_SDDL_REINIT2 0xF2E60040 +#define F367_OFDM_SDD_REINIT2 0xF2E60020 +#define F367_OFDM_SYMBOFFSM_4 0xF2E60010 +#define F367_OFDM_SYMBOFFSM_3 0xF2E60008 +#define F367_OFDM_DEFGEN_SYMBOFFSET_HI 0xF2E60007 + +/* SYMBOFFSL */ +#define R367_OFDM_SYMBOFFSL 0xF2E7 +#define F367_OFDM_DEFGEN_SYMBOFFSET_LO 0xF2E700FF + +/* DEBUG_LT4 */ +#define R367_DEBUG_LT4 0xF400 +#define F367_F_DEBUG_LT4 0xF40000FF + +/* DEBUG_LT5 */ +#define R367_DEBUG_LT5 0xF401 +#define F367_F_DEBUG_LT5 0xF40100FF + +/* DEBUG_LT6 */ +#define R367_DEBUG_LT6 0xF402 +#define F367_F_DEBUG_LT6 0xF40200FF + +/* DEBUG_LT7 */ +#define R367_DEBUG_LT7 0xF403 +#define F367_F_DEBUG_LT7 0xF40300FF + +/* DEBUG_LT8 */ +#define R367_DEBUG_LT8 0xF404 +#define F367_F_DEBUG_LT8 0xF40400FF + +/* DEBUG_LT9 */ +#define R367_DEBUG_LT9 0xF405 +#define F367_F_DEBUG_LT9 0xF40500FF + +/* CTRL_1 */ +#define R367_QAM_CTRL_1 0xF402 +#define F367_QAM_SOFT_RST 0xF4020080 +#define F367_QAM_EQU_RST 0xF4020008 +#define F367_QAM_CRL_RST 0xF4020004 +#define F367_QAM_TRL_RST 0xF4020002 +#define F367_QAM_AGC_RST 0xF4020001 + +/* CTRL_2 */ +#define R367_QAM_CTRL_2 0xF403 +#define F367_QAM_DEINT_RST 0xF4030008 +#define F367_QAM_RS_RST 0xF4030004 + +/* IT_STATUS1 */ +#define R367_QAM_IT_STATUS1 0xF408 +#define F367_QAM_SWEEP_OUT 0xF4080080 +#define F367_QAM_FSM_CRL 0xF4080040 +#define F367_QAM_CRL_LOCK 0xF4080020 +#define F367_QAM_MFSM 0xF4080010 +#define F367_QAM_TRL_LOCK 0xF4080008 +#define F367_QAM_TRL_AGC_LIMIT 0xF4080004 +#define F367_QAM_ADJ_AGC_LOCK 0xF4080002 +#define F367_QAM_AGC_QAM_LOCK 0xF4080001 + +/* IT_STATUS2 */ +#define R367_QAM_IT_STATUS2 0xF409 +#define F367_QAM_TSMF_CNT 0xF4090080 +#define F367_QAM_TSMF_EOF 0xF4090040 +#define F367_QAM_TSMF_RDY 0xF4090020 +#define F367_QAM_FEC_NOCORR 0xF4090010 +#define F367_QAM_SYNCSTATE 0xF4090008 +#define F367_QAM_DEINT_LOCK 0xF4090004 +#define F367_QAM_FADDING_FRZ 0xF4090002 +#define F367_QAM_TAPMON_ALARM 0xF4090001 + +/* IT_EN1 */ +#define R367_QAM_IT_EN1 0xF40A +#define F367_QAM_SWEEP_OUTE 0xF40A0080 +#define F367_QAM_FSM_CRLE 0xF40A0040 +#define F367_QAM_CRL_LOCKE 0xF40A0020 +#define F367_QAM_MFSME 0xF40A0010 +#define F367_QAM_TRL_LOCKE 0xF40A0008 +#define F367_QAM_TRL_AGC_LIMITE 0xF40A0004 +#define F367_QAM_ADJ_AGC_LOCKE 0xF40A0002 +#define F367_QAM_AGC_LOCKE 0xF40A0001 + +/* IT_EN2 */ +#define R367_QAM_IT_EN2 0xF40B +#define F367_QAM_TSMF_CNTE 0xF40B0080 +#define F367_QAM_TSMF_EOFE 0xF40B0040 +#define F367_QAM_TSMF_RDYE 0xF40B0020 +#define F367_QAM_FEC_NOCORRE 0xF40B0010 +#define F367_QAM_SYNCSTATEE 0xF40B0008 +#define F367_QAM_DEINT_LOCKE 0xF40B0004 +#define F367_QAM_FADDING_FRZE 0xF40B0002 +#define F367_QAM_TAPMON_ALARME 0xF40B0001 + +/* CTRL_STATUS */ +#define R367_QAM_CTRL_STATUS 0xF40C +#define F367_QAM_QAMFEC_LOCK 0xF40C0004 +#define F367_QAM_TSMF_LOCK 0xF40C0002 +#define F367_QAM_TSMF_ERROR 0xF40C0001 + +/* TEST_CTL */ +#define R367_QAM_TEST_CTL 0xF40F +#define F367_QAM_TST_BLK_SEL 0xF40F0060 +#define F367_QAM_TST_BUS_SEL 0xF40F001F + +/* AGC_CTL */ +#define R367_QAM_AGC_CTL 0xF410 +#define F367_QAM_AGC_LCK_TH 0xF41000F0 +#define F367_QAM_AGC_ACCUMRSTSEL 0xF4100007 + +/* AGC_IF_CFG */ +#define R367_QAM_AGC_IF_CFG 0xF411 +#define F367_QAM_AGC_IF_BWSEL 0xF41100F0 +#define F367_QAM_AGC_IF_FREEZE 0xF4110002 + +/* AGC_RF_CFG */ +#define R367_QAM_AGC_RF_CFG 0xF412 +#define F367_QAM_AGC_RF_BWSEL 0xF4120070 +#define F367_QAM_AGC_RF_FREEZE 0xF4120002 + +/* AGC_PWM_CFG */ +#define R367_QAM_AGC_PWM_CFG 0xF413 +#define F367_QAM_AGC_RF_PWM_TST 0xF4130080 +#define F367_QAM_AGC_RF_PWM_INV 0xF4130040 +#define F367_QAM_AGC_IF_PWM_TST 0xF4130008 +#define F367_QAM_AGC_IF_PWM_INV 0xF4130004 +#define F367_QAM_AGC_PWM_CLKDIV 0xF4130003 + +/* AGC_PWR_REF_L */ +#define R367_QAM_AGC_PWR_REF_L 0xF414 +#define F367_QAM_AGC_PWRREF_LO 0xF41400FF + +/* AGC_PWR_REF_H */ +#define R367_QAM_AGC_PWR_REF_H 0xF415 +#define F367_QAM_AGC_PWRREF_HI 0xF4150003 + +/* AGC_RF_TH_L */ +#define R367_QAM_AGC_RF_TH_L 0xF416 +#define F367_QAM_AGC_RF_TH_LO 0xF41600FF + +/* AGC_RF_TH_H */ +#define R367_QAM_AGC_RF_TH_H 0xF417 +#define F367_QAM_AGC_RF_TH_HI 0xF417000F + +/* AGC_IF_LTH_L */ +#define R367_QAM_AGC_IF_LTH_L 0xF418 +#define F367_QAM_AGC_IF_THLO_LO 0xF41800FF + +/* AGC_IF_LTH_H */ +#define R367_QAM_AGC_IF_LTH_H 0xF419 +#define F367_QAM_AGC_IF_THLO_HI 0xF419000F + +/* AGC_IF_HTH_L */ +#define R367_QAM_AGC_IF_HTH_L 0xF41A +#define F367_QAM_AGC_IF_THHI_LO 0xF41A00FF + +/* AGC_IF_HTH_H */ +#define R367_QAM_AGC_IF_HTH_H 0xF41B +#define F367_QAM_AGC_IF_THHI_HI 0xF41B000F + +/* AGC_PWR_RD_L */ +#define R367_QAM_AGC_PWR_RD_L 0xF41C +#define F367_QAM_AGC_PWR_WORD_LO 0xF41C00FF + +/* AGC_PWR_RD_M */ +#define R367_QAM_AGC_PWR_RD_M 0xF41D +#define F367_QAM_AGC_PWR_WORD_ME 0xF41D00FF + +/* AGC_PWR_RD_H */ +#define R367_QAM_AGC_PWR_RD_H 0xF41E +#define F367_QAM_AGC_PWR_WORD_HI 0xF41E0003 + +/* AGC_PWM_IFCMD_L */ +#define R367_QAM_AGC_PWM_IFCMD_L 0xF420 +#define F367_QAM_AGC_IF_PWMCMD_LO 0xF42000FF + +/* AGC_PWM_IFCMD_H */ +#define R367_QAM_AGC_PWM_IFCMD_H 0xF421 +#define F367_QAM_AGC_IF_PWMCMD_HI 0xF421000F + +/* AGC_PWM_RFCMD_L */ +#define R367_QAM_AGC_PWM_RFCMD_L 0xF422 +#define F367_QAM_AGC_RF_PWMCMD_LO 0xF42200FF + +/* AGC_PWM_RFCMD_H */ +#define R367_QAM_AGC_PWM_RFCMD_H 0xF423 +#define F367_QAM_AGC_RF_PWMCMD_HI 0xF423000F + +/* IQDEM_CFG */ +#define R367_QAM_IQDEM_CFG 0xF424 +#define F367_QAM_IQDEM_CLK_SEL 0xF4240004 +#define F367_QAM_IQDEM_INVIQ 0xF4240002 +#define F367_QAM_IQDEM_A2DTYPE 0xF4240001 + +/* MIX_NCO_LL */ +#define R367_QAM_MIX_NCO_LL 0xF425 +#define F367_QAM_MIX_NCO_INC_LL 0xF42500FF + +/* MIX_NCO_HL */ +#define R367_QAM_MIX_NCO_HL 0xF426 +#define F367_QAM_MIX_NCO_INC_HL 0xF42600FF + +/* MIX_NCO_HH */ +#define R367_QAM_MIX_NCO_HH 0xF427 +#define F367_QAM_MIX_NCO_INVCNST 0xF4270080 +#define F367_QAM_MIX_NCO_INC_HH 0xF427007F + +/* SRC_NCO_LL */ +#define R367_QAM_SRC_NCO_LL 0xF428 +#define F367_QAM_SRC_NCO_INC_LL 0xF42800FF + +/* SRC_NCO_LH */ +#define R367_QAM_SRC_NCO_LH 0xF429 +#define F367_QAM_SRC_NCO_INC_LH 0xF42900FF + +/* SRC_NCO_HL */ +#define R367_QAM_SRC_NCO_HL 0xF42A +#define F367_QAM_SRC_NCO_INC_HL 0xF42A00FF + +/* SRC_NCO_HH */ +#define R367_QAM_SRC_NCO_HH 0xF42B +#define F367_QAM_SRC_NCO_INC_HH 0xF42B007F + +/* IQDEM_GAIN_SRC_L */ +#define R367_QAM_IQDEM_GAIN_SRC_L 0xF42C +#define F367_QAM_GAIN_SRC_LO 0xF42C00FF + +/* IQDEM_GAIN_SRC_H */ +#define R367_QAM_IQDEM_GAIN_SRC_H 0xF42D +#define F367_QAM_GAIN_SRC_HI 0xF42D0003 + +/* IQDEM_DCRM_CFG_LL */ +#define R367_QAM_IQDEM_DCRM_CFG_LL 0xF430 +#define F367_QAM_DCRM0_DCIN_L 0xF43000FF + +/* IQDEM_DCRM_CFG_LH */ +#define R367_QAM_IQDEM_DCRM_CFG_LH 0xF431 +#define F367_QAM_DCRM1_I_DCIN_L 0xF43100FC +#define F367_QAM_DCRM0_DCIN_H 0xF4310003 + +/* IQDEM_DCRM_CFG_HL */ +#define R367_QAM_IQDEM_DCRM_CFG_HL 0xF432 +#define F367_QAM_DCRM1_Q_DCIN_L 0xF43200F0 +#define F367_QAM_DCRM1_I_DCIN_H 0xF432000F + +/* IQDEM_DCRM_CFG_HH */ +#define R367_QAM_IQDEM_DCRM_CFG_HH 0xF433 +#define F367_QAM_DCRM1_FRZ 0xF4330080 +#define F367_QAM_DCRM0_FRZ 0xF4330040 +#define F367_QAM_DCRM1_Q_DCIN_H 0xF433003F + +/* IQDEM_ADJ_COEFF0 */ +#define R367_QAM_IQDEM_ADJ_COEFF0 0xF434 +#define F367_QAM_ADJIIR_COEFF10_L 0xF43400FF + +/* IQDEM_ADJ_COEFF1 */ +#define R367_QAM_IQDEM_ADJ_COEFF1 0xF435 +#define F367_QAM_ADJIIR_COEFF11_L 0xF43500FC +#define F367_QAM_ADJIIR_COEFF10_H 0xF4350003 + +/* IQDEM_ADJ_COEFF2 */ +#define R367_QAM_IQDEM_ADJ_COEFF2 0xF436 +#define F367_QAM_ADJIIR_COEFF12_L 0xF43600F0 +#define F367_QAM_ADJIIR_COEFF11_H 0xF436000F + +/* IQDEM_ADJ_COEFF3 */ +#define R367_QAM_IQDEM_ADJ_COEFF3 0xF437 +#define F367_QAM_ADJIIR_COEFF20_L 0xF43700C0 +#define F367_QAM_ADJIIR_COEFF12_H 0xF437003F + +/* IQDEM_ADJ_COEFF4 */ +#define R367_QAM_IQDEM_ADJ_COEFF4 0xF438 +#define F367_QAM_ADJIIR_COEFF20_H 0xF43800FF + +/* IQDEM_ADJ_COEFF5 */ +#define R367_QAM_IQDEM_ADJ_COEFF5 0xF439 +#define F367_QAM_ADJIIR_COEFF21_L 0xF43900FF + +/* IQDEM_ADJ_COEFF6 */ +#define R367_QAM_IQDEM_ADJ_COEFF6 0xF43A +#define F367_QAM_ADJIIR_COEFF22_L 0xF43A00FC +#define F367_QAM_ADJIIR_COEFF21_H 0xF43A0003 + +/* IQDEM_ADJ_COEFF7 */ +#define R367_QAM_IQDEM_ADJ_COEFF7 0xF43B +#define F367_QAM_ADJIIR_COEFF22_H 0xF43B000F + +/* IQDEM_ADJ_EN */ +#define R367_QAM_IQDEM_ADJ_EN 0xF43C +#define F367_QAM_ALLPASSFILT_EN 0xF43C0008 +#define F367_QAM_ADJ_AGC_EN 0xF43C0004 +#define F367_QAM_ADJ_COEFF_FRZ 0xF43C0002 +#define F367_QAM_ADJ_EN 0xF43C0001 + +/* IQDEM_ADJ_AGC_REF */ +#define R367_QAM_IQDEM_ADJ_AGC_REF 0xF43D +#define F367_QAM_ADJ_AGC_REF 0xF43D00FF + +/* ALLPASSFILT1 */ +#define R367_QAM_ALLPASSFILT1 0xF440 +#define F367_QAM_ALLPASSFILT_COEFF1_LO 0xF44000FF + +/* ALLPASSFILT2 */ +#define R367_QAM_ALLPASSFILT2 0xF441 +#define F367_QAM_ALLPASSFILT_COEFF1_ME 0xF44100FF + +/* ALLPASSFILT3 */ +#define R367_QAM_ALLPASSFILT3 0xF442 +#define F367_QAM_ALLPASSFILT_COEFF2_LO 0xF44200C0 +#define F367_QAM_ALLPASSFILT_COEFF1_HI 0xF442003F + +/* ALLPASSFILT4 */ +#define R367_QAM_ALLPASSFILT4 0xF443 +#define F367_QAM_ALLPASSFILT_COEFF2_MEL 0xF44300FF + +/* ALLPASSFILT5 */ +#define R367_QAM_ALLPASSFILT5 0xF444 +#define F367_QAM_ALLPASSFILT_COEFF2_MEH 0xF44400FF + +/* ALLPASSFILT6 */ +#define R367_QAM_ALLPASSFILT6 0xF445 +#define F367_QAM_ALLPASSFILT_COEFF3_LO 0xF44500F0 +#define F367_QAM_ALLPASSFILT_COEFF2_HI 0xF445000F + +/* ALLPASSFILT7 */ +#define R367_QAM_ALLPASSFILT7 0xF446 +#define F367_QAM_ALLPASSFILT_COEFF3_MEL 0xF44600FF + +/* ALLPASSFILT8 */ +#define R367_QAM_ALLPASSFILT8 0xF447 +#define F367_QAM_ALLPASSFILT_COEFF3_MEH 0xF44700FF + +/* ALLPASSFILT9 */ +#define R367_QAM_ALLPASSFILT9 0xF448 +#define F367_QAM_ALLPASSFILT_COEFF4_LO 0xF44800FC +#define F367_QAM_ALLPASSFILT_COEFF3_HI 0xF4480003 + +/* ALLPASSFILT10 */ +#define R367_QAM_ALLPASSFILT10 0xF449 +#define F367_QAM_ALLPASSFILT_COEFF4_ME 0xF44900FF + +/* ALLPASSFILT11 */ +#define R367_QAM_ALLPASSFILT11 0xF44A +#define F367_QAM_ALLPASSFILT_COEFF4_HI 0xF44A00FF + +/* TRL_AGC_CFG */ +#define R367_QAM_TRL_AGC_CFG 0xF450 +#define F367_QAM_TRL_AGC_FREEZE 0xF4500080 +#define F367_QAM_TRL_AGC_REF 0xF450007F + +/* TRL_LPF_CFG */ +#define R367_QAM_TRL_LPF_CFG 0xF454 +#define F367_QAM_NYQPOINT_INV 0xF4540040 +#define F367_QAM_TRL_SHIFT 0xF4540030 +#define F367_QAM_NYQ_COEFF_SEL 0xF454000C +#define F367_QAM_TRL_LPF_FREEZE 0xF4540002 +#define F367_QAM_TRL_LPF_CRT 0xF4540001 + +/* TRL_LPF_ACQ_GAIN */ +#define R367_QAM_TRL_LPF_ACQ_GAIN 0xF455 +#define F367_QAM_TRL_GDIR_ACQ 0xF4550070 +#define F367_QAM_TRL_GINT_ACQ 0xF4550007 + +/* TRL_LPF_TRK_GAIN */ +#define R367_QAM_TRL_LPF_TRK_GAIN 0xF456 +#define F367_QAM_TRL_GDIR_TRK 0xF4560070 +#define F367_QAM_TRL_GINT_TRK 0xF4560007 + +/* TRL_LPF_OUT_GAIN */ +#define R367_QAM_TRL_LPF_OUT_GAIN 0xF457 +#define F367_QAM_TRL_GAIN_OUT 0xF4570007 + +/* TRL_LOCKDET_LTH */ +#define R367_QAM_TRL_LOCKDET_LTH 0xF458 +#define F367_QAM_TRL_LCK_THLO 0xF4580007 + +/* TRL_LOCKDET_HTH */ +#define R367_QAM_TRL_LOCKDET_HTH 0xF459 +#define F367_QAM_TRL_LCK_THHI 0xF45900FF + +/* TRL_LOCKDET_TRGVAL */ +#define R367_QAM_TRL_LOCKDET_TRGVAL 0xF45A +#define F367_QAM_TRL_LCK_TRG 0xF45A00FF + +/* IQ_QAM */ +#define R367_QAM_IQ_QAM 0xF45C +#define F367_QAM_IQ_INPUT 0xF45C0008 +#define F367_QAM_DETECT_MODE 0xF45C0007 + +/* FSM_STATE */ +#define R367_QAM_FSM_STATE 0xF460 +#define F367_QAM_CRL_DFE 0xF4600080 +#define F367_QAM_DFE_START 0xF4600040 +#define F367_QAM_CTRLG_START 0xF4600030 +#define F367_QAM_FSM_FORCESTATE 0xF460000F + +/* FSM_CTL */ +#define R367_QAM_FSM_CTL 0xF461 +#define F367_QAM_FEC2_EN 0xF4610040 +#define F367_QAM_SIT_EN 0xF4610020 +#define F367_QAM_TRL_AHEAD 0xF4610010 +#define F367_QAM_TRL2_EN 0xF4610008 +#define F367_QAM_FSM_EQA1_EN 0xF4610004 +#define F367_QAM_FSM_BKP_DIS 0xF4610002 +#define F367_QAM_FSM_FORCE_EN 0xF4610001 + +/* FSM_STS */ +#define R367_QAM_FSM_STS 0xF462 +#define F367_QAM_FSM_STATUS 0xF462000F + +/* FSM_SNR0_HTH */ +#define R367_QAM_FSM_SNR0_HTH 0xF463 +#define F367_QAM_SNR0_HTH 0xF46300FF + +/* FSM_SNR1_HTH */ +#define R367_QAM_FSM_SNR1_HTH 0xF464 +#define F367_QAM_SNR1_HTH 0xF46400FF + +/* FSM_SNR2_HTH */ +#define R367_QAM_FSM_SNR2_HTH 0xF465 +#define F367_QAM_SNR2_HTH 0xF46500FF + +/* FSM_SNR0_LTH */ +#define R367_QAM_FSM_SNR0_LTH 0xF466 +#define F367_QAM_SNR0_LTH 0xF46600FF + +/* FSM_SNR1_LTH */ +#define R367_QAM_FSM_SNR1_LTH 0xF467 +#define F367_QAM_SNR1_LTH 0xF46700FF + +/* FSM_EQA1_HTH */ +#define R367_QAM_FSM_EQA1_HTH 0xF468 +#define F367_QAM_SNR3_HTH_LO 0xF46800F0 +#define F367_QAM_EQA1_HTH 0xF468000F + +/* FSM_TEMPO */ +#define R367_QAM_FSM_TEMPO 0xF469 +#define F367_QAM_SIT 0xF46900C0 +#define F367_QAM_WST 0xF4690038 +#define F367_QAM_ELT 0xF4690006 +#define F367_QAM_SNR3_HTH_HI 0xF4690001 + +/* FSM_CONFIG */ +#define R367_QAM_FSM_CONFIG 0xF46A +#define F367_QAM_FEC2_DFEOFF 0xF46A0004 +#define F367_QAM_PRIT_STATE 0xF46A0002 +#define F367_QAM_MODMAP_STATE 0xF46A0001 + +/* EQU_I_TESTTAP_L */ +#define R367_QAM_EQU_I_TESTTAP_L 0xF474 +#define F367_QAM_I_TEST_TAP_L 0xF47400FF + +/* EQU_I_TESTTAP_M */ +#define R367_QAM_EQU_I_TESTTAP_M 0xF475 +#define F367_QAM_I_TEST_TAP_M 0xF47500FF + +/* EQU_I_TESTTAP_H */ +#define R367_QAM_EQU_I_TESTTAP_H 0xF476 +#define F367_QAM_I_TEST_TAP_H 0xF476001F + +/* EQU_TESTAP_CFG */ +#define R367_QAM_EQU_TESTAP_CFG 0xF477 +#define F367_QAM_TEST_FFE_DFE_SEL 0xF4770040 +#define F367_QAM_TEST_TAP_SELECT 0xF477003F + +/* EQU_Q_TESTTAP_L */ +#define R367_QAM_EQU_Q_TESTTAP_L 0xF478 +#define F367_QAM_Q_TEST_TAP_L 0xF47800FF + +/* EQU_Q_TESTTAP_M */ +#define R367_QAM_EQU_Q_TESTTAP_M 0xF479 +#define F367_QAM_Q_TEST_TAP_M 0xF47900FF + +/* EQU_Q_TESTTAP_H */ +#define R367_QAM_EQU_Q_TESTTAP_H 0xF47A +#define F367_QAM_Q_TEST_TAP_H 0xF47A001F + +/* EQU_TAP_CTRL */ +#define R367_QAM_EQU_TAP_CTRL 0xF47B +#define F367_QAM_MTAP_FRZ 0xF47B0010 +#define F367_QAM_PRE_FREEZE 0xF47B0008 +#define F367_QAM_DFE_TAPMON_EN 0xF47B0004 +#define F367_QAM_FFE_TAPMON_EN 0xF47B0002 +#define F367_QAM_MTAP_ONLY 0xF47B0001 + +/* EQU_CTR_CRL_CONTROL_L */ +#define R367_QAM_EQU_CTR_CRL_CONTROL_L 0xF47C +#define F367_QAM_EQU_CTR_CRL_CONTROL_LO 0xF47C00FF + +/* EQU_CTR_CRL_CONTROL_H */ +#define R367_QAM_EQU_CTR_CRL_CONTROL_H 0xF47D +#define F367_QAM_EQU_CTR_CRL_CONTROL_HI 0xF47D00FF + +/* EQU_CTR_HIPOW_L */ +#define R367_QAM_EQU_CTR_HIPOW_L 0xF47E +#define F367_QAM_CTR_HIPOW_L 0xF47E00FF + +/* EQU_CTR_HIPOW_H */ +#define R367_QAM_EQU_CTR_HIPOW_H 0xF47F +#define F367_QAM_CTR_HIPOW_H 0xF47F00FF + +/* EQU_I_EQU_LO */ +#define R367_QAM_EQU_I_EQU_LO 0xF480 +#define F367_QAM_EQU_I_EQU_L 0xF48000FF + +/* EQU_I_EQU_HI */ +#define R367_QAM_EQU_I_EQU_HI 0xF481 +#define F367_QAM_EQU_I_EQU_H 0xF4810003 + +/* EQU_Q_EQU_LO */ +#define R367_QAM_EQU_Q_EQU_LO 0xF482 +#define F367_QAM_EQU_Q_EQU_L 0xF48200FF + +/* EQU_Q_EQU_HI */ +#define R367_QAM_EQU_Q_EQU_HI 0xF483 +#define F367_QAM_EQU_Q_EQU_H 0xF4830003 + +/* EQU_MAPPER */ +#define R367_QAM_EQU_MAPPER 0xF484 +#define F367_QAM_QUAD_AUTO 0xF4840080 +#define F367_QAM_QUAD_INV 0xF4840040 +#define F367_QAM_QAM_MODE 0xF4840007 + +/* EQU_SWEEP_RATE */ +#define R367_QAM_EQU_SWEEP_RATE 0xF485 +#define F367_QAM_SNR_PER 0xF48500C0 +#define F367_QAM_SWEEP_RATE 0xF485003F + +/* EQU_SNR_LO */ +#define R367_QAM_EQU_SNR_LO 0xF486 +#define F367_QAM_SNR_LO 0xF48600FF + +/* EQU_SNR_HI */ +#define R367_QAM_EQU_SNR_HI 0xF487 +#define F367_QAM_SNR_HI 0xF48700FF + +/* EQU_GAMMA_LO */ +#define R367_QAM_EQU_GAMMA_LO 0xF488 +#define F367_QAM_GAMMA_LO 0xF48800FF + +/* EQU_GAMMA_HI */ +#define R367_QAM_EQU_GAMMA_HI 0xF489 +#define F367_QAM_GAMMA_ME 0xF48900FF + +/* EQU_ERR_GAIN */ +#define R367_QAM_EQU_ERR_GAIN 0xF48A +#define F367_QAM_EQA1MU 0xF48A0070 +#define F367_QAM_CRL2MU 0xF48A000E +#define F367_QAM_GAMMA_HI 0xF48A0001 + +/* EQU_RADIUS */ +#define R367_QAM_EQU_RADIUS 0xF48B +#define F367_QAM_RADIUS 0xF48B00FF + +/* EQU_FFE_MAINTAP */ +#define R367_QAM_EQU_FFE_MAINTAP 0xF48C +#define F367_QAM_FFE_MAINTAP_INIT 0xF48C00FF + +/* EQU_FFE_LEAKAGE */ +#define R367_QAM_EQU_FFE_LEAKAGE 0xF48E +#define F367_QAM_LEAK_PER 0xF48E00F0 +#define F367_QAM_EQU_OUTSEL 0xF48E0002 +#define F367_QAM_PNT2DFE 0xF48E0001 + +/* EQU_FFE_MAINTAP_POS */ +#define R367_QAM_EQU_FFE_MAINTAP_POS 0xF48F +#define F367_QAM_FFE_LEAK_EN 0xF48F0080 +#define F367_QAM_DFE_LEAK_EN 0xF48F0040 +#define F367_QAM_FFE_MAINTAP_POS 0xF48F003F + +/* EQU_GAIN_WIDE */ +#define R367_QAM_EQU_GAIN_WIDE 0xF490 +#define F367_QAM_DFE_GAIN_WIDE 0xF49000F0 +#define F367_QAM_FFE_GAIN_WIDE 0xF490000F + +/* EQU_GAIN_NARROW */ +#define R367_QAM_EQU_GAIN_NARROW 0xF491 +#define F367_QAM_DFE_GAIN_NARROW 0xF49100F0 +#define F367_QAM_FFE_GAIN_NARROW 0xF491000F + +/* EQU_CTR_LPF_GAIN */ +#define R367_QAM_EQU_CTR_LPF_GAIN 0xF492 +#define F367_QAM_CTR_GTO 0xF4920080 +#define F367_QAM_CTR_GDIR 0xF4920070 +#define F367_QAM_SWEEP_EN 0xF4920008 +#define F367_QAM_CTR_GINT 0xF4920007 + +/* EQU_CRL_LPF_GAIN */ +#define R367_QAM_EQU_CRL_LPF_GAIN 0xF493 +#define F367_QAM_CRL_GTO 0xF4930080 +#define F367_QAM_CRL_GDIR 0xF4930070 +#define F367_QAM_SWEEP_DIR 0xF4930008 +#define F367_QAM_CRL_GINT 0xF4930007 + +/* EQU_GLOBAL_GAIN */ +#define R367_QAM_EQU_GLOBAL_GAIN 0xF494 +#define F367_QAM_CRL_GAIN 0xF49400F8 +#define F367_QAM_CTR_INC_GAIN 0xF4940004 +#define F367_QAM_CTR_FRAC 0xF4940003 + +/* EQU_CRL_LD_SEN */ +#define R367_QAM_EQU_CRL_LD_SEN 0xF495 +#define F367_QAM_CTR_BADPOINT_EN 0xF4950080 +#define F367_QAM_CTR_GAIN 0xF4950070 +#define F367_QAM_LIMANEN 0xF4950008 +#define F367_QAM_CRL_LD_SEN 0xF4950007 + +/* EQU_CRL_LD_VAL */ +#define R367_QAM_EQU_CRL_LD_VAL 0xF496 +#define F367_QAM_CRL_BISTH_LIMIT 0xF4960080 +#define F367_QAM_CARE_EN 0xF4960040 +#define F367_QAM_CRL_LD_PER 0xF4960030 +#define F367_QAM_CRL_LD_WST 0xF496000C +#define F367_QAM_CRL_LD_TFS 0xF4960003 + +/* EQU_CRL_TFR */ +#define R367_QAM_EQU_CRL_TFR 0xF497 +#define F367_QAM_CRL_LD_TFR 0xF49700FF + +/* EQU_CRL_BISTH_LO */ +#define R367_QAM_EQU_CRL_BISTH_LO 0xF498 +#define F367_QAM_CRL_BISTH_LO 0xF49800FF + +/* EQU_CRL_BISTH_HI */ +#define R367_QAM_EQU_CRL_BISTH_HI 0xF499 +#define F367_QAM_CRL_BISTH_HI 0xF49900FF + +/* EQU_SWEEP_RANGE_LO */ +#define R367_QAM_EQU_SWEEP_RANGE_LO 0xF49A +#define F367_QAM_SWEEP_RANGE_LO 0xF49A00FF + +/* EQU_SWEEP_RANGE_HI */ +#define R367_QAM_EQU_SWEEP_RANGE_HI 0xF49B +#define F367_QAM_SWEEP_RANGE_HI 0xF49B00FF + +/* EQU_CRL_LIMITER */ +#define R367_QAM_EQU_CRL_LIMITER 0xF49C +#define F367_QAM_BISECTOR_EN 0xF49C0080 +#define F367_QAM_PHEST128_EN 0xF49C0040 +#define F367_QAM_CRL_LIM 0xF49C003F + +/* EQU_MODULUS_MAP */ +#define R367_QAM_EQU_MODULUS_MAP 0xF49D +#define F367_QAM_PNT_DEPTH 0xF49D00E0 +#define F367_QAM_MODULUS_CMP 0xF49D001F + +/* EQU_PNT_GAIN */ +#define R367_QAM_EQU_PNT_GAIN 0xF49E +#define F367_QAM_PNT_EN 0xF49E0080 +#define F367_QAM_MODULUSMAP_EN 0xF49E0040 +#define F367_QAM_PNT_GAIN 0xF49E003F + +/* FEC_AC_CTR_0 */ +#define R367_QAM_FEC_AC_CTR_0 0xF4A8 +#define F367_QAM_BE_BYPASS 0xF4A80020 +#define F367_QAM_REFRESH47 0xF4A80010 +#define F367_QAM_CT_NBST 0xF4A80008 +#define F367_QAM_TEI_ENA 0xF4A80004 +#define F367_QAM_DS_ENA 0xF4A80002 +#define F367_QAM_TSMF_EN 0xF4A80001 + +/* FEC_AC_CTR_1 */ +#define R367_QAM_FEC_AC_CTR_1 0xF4A9 +#define F367_QAM_DEINT_DEPTH 0xF4A900FF + +/* FEC_AC_CTR_2 */ +#define R367_QAM_FEC_AC_CTR_2 0xF4AA +#define F367_QAM_DEINT_M 0xF4AA00F8 +#define F367_QAM_DIS_UNLOCK 0xF4AA0004 +#define F367_QAM_DESCR_MODE 0xF4AA0003 + +/* FEC_AC_CTR_3 */ +#define R367_QAM_FEC_AC_CTR_3 0xF4AB +#define F367_QAM_DI_UNLOCK 0xF4AB0080 +#define F367_QAM_DI_FREEZE 0xF4AB0040 +#define F367_QAM_MISMATCH 0xF4AB0030 +#define F367_QAM_ACQ_MODE 0xF4AB000C +#define F367_QAM_TRK_MODE 0xF4AB0003 + +/* FEC_STATUS */ +#define R367_QAM_FEC_STATUS 0xF4AC +#define F367_QAM_DEINT_SMCNTR 0xF4AC00E0 +#define F367_QAM_DEINT_SYNCSTATE 0xF4AC0018 +#define F367_QAM_DEINT_SYNLOST 0xF4AC0004 +#define F367_QAM_DESCR_SYNCSTATE 0xF4AC0002 + +/* RS_COUNTER_0 */ +#define R367_QAM_RS_COUNTER_0 0xF4AE +#define F367_QAM_BK_CT_L 0xF4AE00FF + +/* RS_COUNTER_1 */ +#define R367_QAM_RS_COUNTER_1 0xF4AF +#define F367_QAM_BK_CT_H 0xF4AF00FF + +/* RS_COUNTER_2 */ +#define R367_QAM_RS_COUNTER_2 0xF4B0 +#define F367_QAM_CORR_CT_L 0xF4B000FF + +/* RS_COUNTER_3 */ +#define R367_QAM_RS_COUNTER_3 0xF4B1 +#define F367_QAM_CORR_CT_H 0xF4B100FF + +/* RS_COUNTER_4 */ +#define R367_QAM_RS_COUNTER_4 0xF4B2 +#define F367_QAM_UNCORR_CT_L 0xF4B200FF + +/* RS_COUNTER_5 */ +#define R367_QAM_RS_COUNTER_5 0xF4B3 +#define F367_QAM_UNCORR_CT_H 0xF4B300FF + +/* BERT_0 */ +#define R367_QAM_BERT_0 0xF4B4 +#define F367_QAM_RS_NOCORR 0xF4B40004 +#define F367_QAM_CT_HOLD 0xF4B40002 +#define F367_QAM_CT_CLEAR 0xF4B40001 + +/* BERT_1 */ +#define R367_QAM_BERT_1 0xF4B5 +#define F367_QAM_BERT_ON 0xF4B50020 +#define F367_QAM_BERT_ERR_SRC 0xF4B50010 +#define F367_QAM_BERT_ERR_MODE 0xF4B50008 +#define F367_QAM_BERT_NBYTE 0xF4B50007 + +/* BERT_2 */ +#define R367_QAM_BERT_2 0xF4B6 +#define F367_QAM_BERT_ERRCOUNT_L 0xF4B600FF + +/* BERT_3 */ +#define R367_QAM_BERT_3 0xF4B7 +#define F367_QAM_BERT_ERRCOUNT_H 0xF4B700FF + +/* OUTFORMAT_0 */ +#define R367_QAM_OUTFORMAT_0 0xF4B8 +#define F367_QAM_CLK_POLARITY 0xF4B80080 +#define F367_QAM_FEC_TYPE 0xF4B80040 +#define F367_QAM_SYNC_STRIP 0xF4B80008 +#define F367_QAM_TS_SWAP 0xF4B80004 +#define F367_QAM_OUTFORMAT 0xF4B80003 + +/* OUTFORMAT_1 */ +#define R367_QAM_OUTFORMAT_1 0xF4B9 +#define F367_QAM_CI_DIVRANGE 0xF4B900FF + +/* SMOOTHER_2 */ +#define R367_QAM_SMOOTHER_2 0xF4BE +#define F367_QAM_FIFO_BYPASS 0xF4BE0020 + +/* TSMF_CTRL_0 */ +#define R367_QAM_TSMF_CTRL_0 0xF4C0 +#define F367_QAM_TS_NUMBER 0xF4C0001E +#define F367_QAM_SEL_MODE 0xF4C00001 + +/* TSMF_CTRL_1 */ +#define R367_QAM_TSMF_CTRL_1 0xF4C1 +#define F367_QAM_CHECK_ERROR_BIT 0xF4C10080 +#define F367_QAM_CHCK_F_SYNC 0xF4C10040 +#define F367_QAM_H_MODE 0xF4C10008 +#define F367_QAM_D_V_MODE 0xF4C10004 +#define F367_QAM_MODE 0xF4C10003 + +/* TSMF_CTRL_3 */ +#define R367_QAM_TSMF_CTRL_3 0xF4C3 +#define F367_QAM_SYNC_IN_COUNT 0xF4C300F0 +#define F367_QAM_SYNC_OUT_COUNT 0xF4C3000F + +/* TS_ON_ID_0 */ +#define R367_QAM_TS_ON_ID_0 0xF4C4 +#define F367_QAM_TS_ID_L 0xF4C400FF + +/* TS_ON_ID_1 */ +#define R367_QAM_TS_ON_ID_1 0xF4C5 +#define F367_QAM_TS_ID_H 0xF4C500FF + +/* TS_ON_ID_2 */ +#define R367_QAM_TS_ON_ID_2 0xF4C6 +#define F367_QAM_ON_ID_L 0xF4C600FF + +/* TS_ON_ID_3 */ +#define R367_QAM_TS_ON_ID_3 0xF4C7 +#define F367_QAM_ON_ID_H 0xF4C700FF + +/* RE_STATUS_0 */ +#define R367_QAM_RE_STATUS_0 0xF4C8 +#define F367_QAM_RECEIVE_STATUS_L 0xF4C800FF + +/* RE_STATUS_1 */ +#define R367_QAM_RE_STATUS_1 0xF4C9 +#define F367_QAM_RECEIVE_STATUS_LH 0xF4C900FF + +/* RE_STATUS_2 */ +#define R367_QAM_RE_STATUS_2 0xF4CA +#define F367_QAM_RECEIVE_STATUS_HL 0xF4CA00FF + +/* RE_STATUS_3 */ +#define R367_QAM_RE_STATUS_3 0xF4CB +#define F367_QAM_RECEIVE_STATUS_HH 0xF4CB003F + +/* TS_STATUS_0 */ +#define R367_QAM_TS_STATUS_0 0xF4CC +#define F367_QAM_TS_STATUS_L 0xF4CC00FF + +/* TS_STATUS_1 */ +#define R367_QAM_TS_STATUS_1 0xF4CD +#define F367_QAM_TS_STATUS_H 0xF4CD007F + +/* TS_STATUS_2 */ +#define R367_QAM_TS_STATUS_2 0xF4CE +#define F367_QAM_ERROR 0xF4CE0080 +#define F367_QAM_EMERGENCY 0xF4CE0040 +#define F367_QAM_CRE_TS 0xF4CE0030 +#define F367_QAM_VER 0xF4CE000E +#define F367_QAM_M_LOCK 0xF4CE0001 + +/* TS_STATUS_3 */ +#define R367_QAM_TS_STATUS_3 0xF4CF +#define F367_QAM_UPDATE_READY 0xF4CF0080 +#define F367_QAM_END_FRAME_HEADER 0xF4CF0040 +#define F367_QAM_CONTCNT 0xF4CF0020 +#define F367_QAM_TS_IDENTIFIER_SEL 0xF4CF000F + +/* T_O_ID_0 */ +#define R367_QAM_T_O_ID_0 0xF4D0 +#define F367_QAM_ON_ID_I_L 0xF4D000FF + +/* T_O_ID_1 */ +#define R367_QAM_T_O_ID_1 0xF4D1 +#define F367_QAM_ON_ID_I_H 0xF4D100FF + +/* T_O_ID_2 */ +#define R367_QAM_T_O_ID_2 0xF4D2 +#define F367_QAM_TS_ID_I_L 0xF4D200FF + +/* T_O_ID_3 */ +#define R367_QAM_T_O_ID_3 0xF4D3 +#define F367_QAM_TS_ID_I_H 0xF4D300FF + diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,4922 @@ +/* + STV0900/0903 Multistandard Broadcast Frontend driver + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "dvb_frontend.h" + +#include "stv6110x.h" /* for demodulator internal modes */ + +#include "stv090x_reg.h" +#include "stv090x.h" +#include "stv090x_priv.h" + + #define ERRCTRL1_DVBS1 0x76 +#define ERRCTRL1_DVBS2 0x67 + +static unsigned int verbose; +module_param(verbose, int, 0644); + +/* internal params node */ +struct stv090x_dev { + /* pointer for internal params, one for each pair of demods */ + struct stv090x_internal *internal; + struct stv090x_dev *next_dev; +}; + +/* first internal params */ +static struct stv090x_dev *stv090x_first_dev; + +/* find chip by i2c adapter and i2c address */ +static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap, + u8 i2c_addr) +{ + struct stv090x_dev *temp_dev = stv090x_first_dev; + + /* + Search of the last stv0900 chip or + find it by i2c adapter and i2c address */ + while ((temp_dev != NULL) && + ((temp_dev->internal->i2c_adap != i2c_adap) || + (temp_dev->internal->i2c_addr != i2c_addr))) { + + temp_dev = temp_dev->next_dev; + } + + return temp_dev; +} + +/* deallocating chip */ +static void remove_dev(struct stv090x_internal *internal) +{ + struct stv090x_dev *prev_dev = stv090x_first_dev; + struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, + internal->i2c_addr); + + if (del_dev != NULL) { + if (del_dev == stv090x_first_dev) { + stv090x_first_dev = del_dev->next_dev; + } else { + while (prev_dev->next_dev != del_dev) + prev_dev = prev_dev->next_dev; + + prev_dev->next_dev = del_dev->next_dev; + } + + kfree(del_dev); + } +} + +/* allocating new chip */ +static struct stv090x_dev *append_internal(struct stv090x_internal *internal) +{ + struct stv090x_dev *new_dev; + struct stv090x_dev *temp_dev; + + new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL); + if (new_dev != NULL) { + new_dev->internal = internal; + new_dev->next_dev = NULL; + + /* append to list */ + if (stv090x_first_dev == NULL) { + stv090x_first_dev = new_dev; + } else { + temp_dev = stv090x_first_dev; + while (temp_dev->next_dev != NULL) + temp_dev = temp_dev->next_dev; + + temp_dev->next_dev = new_dev; + } + } + + return new_dev; +} + + +/* DVBS1 and DSS C/N Lookup table */ +static const struct stv090x_tab stv090x_s1cn_tab[] = { + { 0, 8917 }, /* 0.0dB */ + { 5, 8801 }, /* 0.5dB */ + { 10, 8667 }, /* 1.0dB */ + { 15, 8522 }, /* 1.5dB */ + { 20, 8355 }, /* 2.0dB */ + { 25, 8175 }, /* 2.5dB */ + { 30, 7979 }, /* 3.0dB */ + { 35, 7763 }, /* 3.5dB */ + { 40, 7530 }, /* 4.0dB */ + { 45, 7282 }, /* 4.5dB */ + { 50, 7026 }, /* 5.0dB */ + { 55, 6781 }, /* 5.5dB */ + { 60, 6514 }, /* 6.0dB */ + { 65, 6241 }, /* 6.5dB */ + { 70, 5965 }, /* 7.0dB */ + { 75, 5690 }, /* 7.5dB */ + { 80, 5424 }, /* 8.0dB */ + { 85, 5161 }, /* 8.5dB */ + { 90, 4902 }, /* 9.0dB */ + { 95, 4654 }, /* 9.5dB */ + { 100, 4417 }, /* 10.0dB */ + { 105, 4186 }, /* 10.5dB */ + { 110, 3968 }, /* 11.0dB */ + { 115, 3757 }, /* 11.5dB */ + { 120, 3558 }, /* 12.0dB */ + { 125, 3366 }, /* 12.5dB */ + { 130, 3185 }, /* 13.0dB */ + { 135, 3012 }, /* 13.5dB */ + { 140, 2850 }, /* 14.0dB */ + { 145, 2698 }, /* 14.5dB */ + { 150, 2550 }, /* 15.0dB */ + { 160, 2283 }, /* 16.0dB */ + { 170, 2042 }, /* 17.0dB */ + { 180, 1827 }, /* 18.0dB */ + { 190, 1636 }, /* 19.0dB */ + { 200, 1466 }, /* 20.0dB */ + { 210, 1315 }, /* 21.0dB */ + { 220, 1181 }, /* 22.0dB */ + { 230, 1064 }, /* 23.0dB */ + { 240, 960 }, /* 24.0dB */ + { 250, 869 }, /* 25.0dB */ + { 260, 792 }, /* 26.0dB */ + { 270, 724 }, /* 27.0dB */ + { 280, 665 }, /* 28.0dB */ + { 290, 616 }, /* 29.0dB */ + { 300, 573 }, /* 30.0dB */ + { 310, 537 }, /* 31.0dB */ + { 320, 507 }, /* 32.0dB */ + { 330, 483 }, /* 33.0dB */ + { 400, 398 }, /* 40.0dB */ + { 450, 381 }, /* 45.0dB */ + { 500, 377 } /* 50.0dB */ +}; + +/* DVBS2 C/N Lookup table */ +static const struct stv090x_tab stv090x_s2cn_tab[] = { + { -30, 13348 }, /* -3.0dB */ + { -20, 12640 }, /* -2d.0B */ + { -10, 11883 }, /* -1.0dB */ + { 0, 11101 }, /* -0.0dB */ + { 5, 10718 }, /* 0.5dB */ + { 10, 10339 }, /* 1.0dB */ + { 15, 9947 }, /* 1.5dB */ + { 20, 9552 }, /* 2.0dB */ + { 25, 9183 }, /* 2.5dB */ + { 30, 8799 }, /* 3.0dB */ + { 35, 8422 }, /* 3.5dB */ + { 40, 8062 }, /* 4.0dB */ + { 45, 7707 }, /* 4.5dB */ + { 50, 7353 }, /* 5.0dB */ + { 55, 7025 }, /* 5.5dB */ + { 60, 6684 }, /* 6.0dB */ + { 65, 6331 }, /* 6.5dB */ + { 70, 6036 }, /* 7.0dB */ + { 75, 5727 }, /* 7.5dB */ + { 80, 5437 }, /* 8.0dB */ + { 85, 5164 }, /* 8.5dB */ + { 90, 4902 }, /* 9.0dB */ + { 95, 4653 }, /* 9.5dB */ + { 100, 4408 }, /* 10.0dB */ + { 105, 4187 }, /* 10.5dB */ + { 110, 3961 }, /* 11.0dB */ + { 115, 3751 }, /* 11.5dB */ + { 120, 3558 }, /* 12.0dB */ + { 125, 3368 }, /* 12.5dB */ + { 130, 3191 }, /* 13.0dB */ + { 135, 3017 }, /* 13.5dB */ + { 140, 2862 }, /* 14.0dB */ + { 145, 2710 }, /* 14.5dB */ + { 150, 2565 }, /* 15.0dB */ + { 160, 2300 }, /* 16.0dB */ + { 170, 2058 }, /* 17.0dB */ + { 180, 1849 }, /* 18.0dB */ + { 190, 1663 }, /* 19.0dB */ + { 200, 1495 }, /* 20.0dB */ + { 210, 1349 }, /* 21.0dB */ + { 220, 1222 }, /* 22.0dB */ + { 230, 1110 }, /* 23.0dB */ + { 240, 1011 }, /* 24.0dB */ + { 250, 925 }, /* 25.0dB */ + { 260, 853 }, /* 26.0dB */ + { 270, 789 }, /* 27.0dB */ + { 280, 734 }, /* 28.0dB */ + { 290, 690 }, /* 29.0dB */ + { 300, 650 }, /* 30.0dB */ + { 310, 619 }, /* 31.0dB */ + { 320, 593 }, /* 32.0dB */ + { 330, 571 }, /* 33.0dB */ + { 400, 498 }, /* 40.0dB */ + { 450, 484 }, /* 45.0dB */ + { 500, 481 } /* 50.0dB */ +}; + +/* RF level C/N lookup table */ +static const struct stv090x_tab stv090x_rf_tab[] = { + { -5, 0xcaa1 }, /* -5dBm */ + { -10, 0xc229 }, /* -10dBm */ + { -15, 0xbb08 }, /* -15dBm */ + { -20, 0xb4bc }, /* -20dBm */ + { -25, 0xad5a }, /* -25dBm */ + { -30, 0xa298 }, /* -30dBm */ + { -35, 0x98a8 }, /* -35dBm */ + { -40, 0x8389 }, /* -40dBm */ + { -45, 0x59be }, /* -45dBm */ + { -50, 0x3a14 }, /* -50dBm */ + { -55, 0x2d11 }, /* -55dBm */ + { -60, 0x210d }, /* -60dBm */ + { -65, 0xa14f }, /* -65dBm */ + { -70, 0x07aa } /* -70dBm */ +}; + + +static struct stv090x_reg stv0900_initval[] = { + + { STV090x_OUTCFG, 0x00 }, + { STV090x_MODECFG, 0xff }, + { STV090x_AGCRF1CFG, 0x11 }, + { STV090x_AGCRF2CFG, 0x13 }, + { STV090x_TSGENERAL1X, 0x14 }, + { STV090x_TSTTNR2, 0x21 }, + { STV090x_TSTTNR4, 0x21 }, + { STV090x_P2_DISTXCTL, 0x22 }, + { STV090x_P2_F22TX, 0xc0 }, + { STV090x_P2_F22RX, 0xc0 }, + { STV090x_P2_DISRXCTL, 0x00 }, + { STV090x_P2_DMDCFGMD, 0xF9 }, + { STV090x_P2_DEMOD, 0x08 }, + { STV090x_P2_DMDCFG3, 0xc4 }, + { STV090x_P2_CARFREQ, 0xed }, + { STV090x_P2_LDT, 0xd0 }, + { STV090x_P2_LDT2, 0xb8 }, + { STV090x_P2_TMGCFG, 0xd2 }, + { STV090x_P2_TMGTHRISE, 0x20 }, + { STV090x_P1_TMGCFG, 0xd2 }, + + { STV090x_P2_TMGTHFALL, 0x00 }, + { STV090x_P2_FECSPY, 0x88 }, + { STV090x_P2_FSPYDATA, 0x3a }, + { STV090x_P2_FBERCPT4, 0x00 }, + { STV090x_P2_FSPYBER, 0x10 }, + { STV090x_P2_ERRCTRL1, 0x35 }, + { STV090x_P2_ERRCTRL2, 0xc1 }, + { STV090x_P2_CFRICFG, 0xf8 }, + { STV090x_P2_NOSCFG, 0x1c }, + { STV090x_P2_DMDTOM, 0x20 }, + { STV090x_P2_CORRELMANT, 0x70 }, + { STV090x_P2_CORRELABS, 0x88 }, + { STV090x_P2_AGC2O, 0x5b }, + { STV090x_P2_AGC2REF, 0x38 }, + { STV090x_P2_CARCFG, 0xe4 }, + { STV090x_P2_ACLC, 0x1A }, + { STV090x_P2_BCLC, 0x09 }, + { STV090x_P2_CARHDR, 0x08 }, + { STV090x_P2_KREFTMG, 0xc1 }, + { STV090x_P2_SFRUPRATIO, 0xf0 }, + { STV090x_P2_SFRLOWRATIO, 0x70 }, + { STV090x_P2_SFRSTEP, 0x58 }, + { STV090x_P2_TMGCFG2, 0x01 }, + { STV090x_P2_CAR2CFG, 0x26 }, + { STV090x_P2_BCLC2S2Q, 0x86 }, + { STV090x_P2_BCLC2S28, 0x86 }, + { STV090x_P2_SMAPCOEF7, 0x77 }, + { STV090x_P2_SMAPCOEF6, 0x85 }, + { STV090x_P2_SMAPCOEF5, 0x77 }, + { STV090x_P2_TSCFGL, 0x20 }, + { STV090x_P2_DMDCFG2, 0x3b }, + { STV090x_P2_MODCODLST0, 0xff }, + { STV090x_P2_MODCODLST1, 0xff }, + { STV090x_P2_MODCODLST2, 0xff }, + { STV090x_P2_MODCODLST3, 0xff }, + { STV090x_P2_MODCODLST4, 0xff }, + { STV090x_P2_MODCODLST5, 0xff }, + { STV090x_P2_MODCODLST6, 0xff }, + { STV090x_P2_MODCODLST7, 0xcc }, + { STV090x_P2_MODCODLST8, 0xcc }, + { STV090x_P2_MODCODLST9, 0xcc }, + { STV090x_P2_MODCODLSTA, 0xcc }, + { STV090x_P2_MODCODLSTB, 0xcc }, + { STV090x_P2_MODCODLSTC, 0xcc }, + { STV090x_P2_MODCODLSTD, 0xcc }, + { STV090x_P2_MODCODLSTE, 0xcc }, + { STV090x_P2_MODCODLSTF, 0xcf }, + { STV090x_P1_DISTXCTL, 0x22 }, + { STV090x_P1_F22TX, 0xc0 }, + { STV090x_P1_F22RX, 0xc0 }, + { STV090x_P1_DISRXCTL, 0x00 }, + { STV090x_P1_DMDCFGMD, 0xf9 }, + { STV090x_P1_DEMOD, 0x08 }, + { STV090x_P1_DMDCFG3, 0xc4 }, + { STV090x_P1_DMDTOM, 0x20 }, + { STV090x_P1_CARFREQ, 0xed }, + { STV090x_P1_LDT, 0xd0 }, + { STV090x_P1_LDT2, 0xb8 }, + { STV090x_P1_TMGCFG, 0xd2 }, + { STV090x_P1_TMGTHRISE, 0x20 }, + { STV090x_P1_TMGTHFALL, 0x00 }, + { STV090x_P1_SFRUPRATIO, 0xf0 }, + { STV090x_P1_SFRLOWRATIO, 0x70 }, + { STV090x_P1_TSCFGL, 0x20 }, + { STV090x_P1_FECSPY, 0x88 }, + { STV090x_P1_FSPYDATA, 0x3a }, + { STV090x_P1_FBERCPT4, 0x00 }, + { STV090x_P1_FSPYBER, 0x10 }, + { STV090x_P1_ERRCTRL1, 0x35 }, + { STV090x_P1_ERRCTRL2, 0xc1 }, + { STV090x_P1_CFRICFG, 0xf8 }, + { STV090x_P1_NOSCFG, 0x1c }, + { STV090x_P1_CORRELMANT, 0x70 }, + { STV090x_P1_CORRELABS, 0x88 }, + { STV090x_P1_AGC2O, 0x5b }, + { STV090x_P1_AGC2REF, 0x38 }, + { STV090x_P1_CARCFG, 0xe4 }, + { STV090x_P1_ACLC, 0x1A }, + { STV090x_P1_BCLC, 0x09 }, + { STV090x_P1_CARHDR, 0x08 }, + { STV090x_P1_KREFTMG, 0xc1 }, + { STV090x_P1_SFRSTEP, 0x58 }, + { STV090x_P1_TMGCFG2, 0x01 }, + { STV090x_P1_CAR2CFG, 0x26 }, + { STV090x_P1_BCLC2S2Q, 0x86 }, + { STV090x_P1_BCLC2S28, 0x86 }, + { STV090x_P1_SMAPCOEF7, 0x77 }, + { STV090x_P1_SMAPCOEF6, 0x85 }, + { STV090x_P1_SMAPCOEF5, 0x77 }, + { STV090x_P1_DMDCFG2, 0x3b }, + { STV090x_P1_MODCODLST0, 0xff }, + { STV090x_P1_MODCODLST1, 0xff }, + { STV090x_P1_MODCODLST2, 0xff }, + { STV090x_P1_MODCODLST3, 0xff }, + { STV090x_P1_MODCODLST4, 0xff }, + { STV090x_P1_MODCODLST5, 0xff }, + { STV090x_P1_MODCODLST6, 0xff }, + { STV090x_P1_MODCODLST7, 0xcc }, + { STV090x_P1_MODCODLST8, 0xcc }, + { STV090x_P1_MODCODLST9, 0xcc }, + { STV090x_P1_MODCODLSTA, 0xcc }, + { STV090x_P1_MODCODLSTB, 0xcc }, + { STV090x_P1_MODCODLSTC, 0xcc }, + { STV090x_P1_MODCODLSTD, 0xcc }, + { STV090x_P1_MODCODLSTE, 0xcc }, + { STV090x_P1_MODCODLSTF, 0xcf }, + { STV090x_GENCFG, 0x1d }, + { STV090x_NBITER_NF4, 0x37 }, + { STV090x_NBITER_NF5, 0x29 }, + { STV090x_NBITER_NF6, 0x37 }, + { STV090x_NBITER_NF7, 0x33 }, + { STV090x_NBITER_NF8, 0x31 }, + { STV090x_NBITER_NF9, 0x2f }, + { STV090x_NBITER_NF10, 0x39 }, + { STV090x_NBITER_NF11, 0x3a }, + { STV090x_NBITER_NF12, 0x29 }, + { STV090x_NBITER_NF13, 0x37 }, + { STV090x_NBITER_NF14, 0x33 }, + { STV090x_NBITER_NF15, 0x2f }, + { STV090x_NBITER_NF16, 0x39 }, + { STV090x_NBITER_NF17, 0x3a }, + { STV090x_NBITERNOERR, 0x04 }, + { STV090x_GAINLLR_NF4, 0x0C }, + { STV090x_GAINLLR_NF5, 0x0F }, + { STV090x_GAINLLR_NF6, 0x11 }, + { STV090x_GAINLLR_NF7, 0x14 }, + { STV090x_GAINLLR_NF8, 0x17 }, + { STV090x_GAINLLR_NF9, 0x19 }, + { STV090x_GAINLLR_NF10, 0x20 }, + { STV090x_GAINLLR_NF11, 0x21 }, + { STV090x_GAINLLR_NF12, 0x0D }, + { STV090x_GAINLLR_NF13, 0x0F }, + { STV090x_GAINLLR_NF14, 0x13 }, + { STV090x_GAINLLR_NF15, 0x1A }, + { STV090x_GAINLLR_NF16, 0x1F }, + { STV090x_GAINLLR_NF17, 0x21 }, + { STV090x_RCCFGH, 0x20 }, + { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ + { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ + { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ + { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */ +}; + +static struct stv090x_reg stv0903_initval[] = { + { STV090x_OUTCFG, 0x00 }, + { STV090x_AGCRF1CFG, 0x11 }, + { STV090x_STOPCLK1, 0x48 }, + { STV090x_STOPCLK2, 0x14 }, + { STV090x_TSTTNR1, 0x27 }, + { STV090x_TSTTNR2, 0x21 }, + { STV090x_P1_DISTXCTL, 0x22 }, + { STV090x_P1_F22TX, 0xc0 }, + { STV090x_P1_F22RX, 0xc0 }, + { STV090x_P1_DISRXCTL, 0x00 }, + { STV090x_P1_DMDCFGMD, 0xF9 }, + { STV090x_P1_DEMOD, 0x08 }, + { STV090x_P1_DMDCFG3, 0xc4 }, + { STV090x_P1_CARFREQ, 0xed }, + { STV090x_P1_TNRCFG2, 0x82 }, + { STV090x_P1_LDT, 0xd0 }, + { STV090x_P1_LDT2, 0xb8 }, + { STV090x_P1_TMGCFG, 0xd2 }, + { STV090x_P1_TMGTHRISE, 0x20 }, + { STV090x_P1_TMGTHFALL, 0x00 }, + { STV090x_P1_SFRUPRATIO, 0xf0 }, + { STV090x_P1_SFRLOWRATIO, 0x70 }, + { STV090x_P1_TSCFGL, 0x20 }, + { STV090x_P1_FECSPY, 0x88 }, + { STV090x_P1_FSPYDATA, 0x3a }, + { STV090x_P1_FBERCPT4, 0x00 }, + { STV090x_P1_FSPYBER, 0x10 }, + { STV090x_P1_ERRCTRL1, 0x35 }, + { STV090x_P1_ERRCTRL2, 0xc1 }, + { STV090x_P1_CFRICFG, 0xf8 }, + { STV090x_P1_NOSCFG, 0x1c }, + { STV090x_P1_DMDTOM, 0x20 }, + { STV090x_P1_CORRELMANT, 0x70 }, + { STV090x_P1_CORRELABS, 0x88 }, + { STV090x_P1_AGC2O, 0x5b }, + { STV090x_P1_AGC2REF, 0x38 }, + { STV090x_P1_CARCFG, 0xe4 }, + { STV090x_P1_ACLC, 0x1A }, + { STV090x_P1_BCLC, 0x09 }, + { STV090x_P1_CARHDR, 0x08 }, + { STV090x_P1_KREFTMG, 0xc1 }, + { STV090x_P1_SFRSTEP, 0x58 }, + { STV090x_P1_TMGCFG2, 0x01 }, + { STV090x_P1_CAR2CFG, 0x26 }, + { STV090x_P1_BCLC2S2Q, 0x86 }, + { STV090x_P1_BCLC2S28, 0x86 }, + { STV090x_P1_SMAPCOEF7, 0x77 }, + { STV090x_P1_SMAPCOEF6, 0x85 }, + { STV090x_P1_SMAPCOEF5, 0x77 }, + { STV090x_P1_DMDCFG2, 0x3b }, + { STV090x_P1_MODCODLST0, 0xff }, + { STV090x_P1_MODCODLST1, 0xff }, + { STV090x_P1_MODCODLST2, 0xff }, + { STV090x_P1_MODCODLST3, 0xff }, + { STV090x_P1_MODCODLST4, 0xff }, + { STV090x_P1_MODCODLST5, 0xff }, + { STV090x_P1_MODCODLST6, 0xff }, + { STV090x_P1_MODCODLST7, 0xcc }, + { STV090x_P1_MODCODLST8, 0xcc }, + { STV090x_P1_MODCODLST9, 0xcc }, + { STV090x_P1_MODCODLSTA, 0xcc }, + { STV090x_P1_MODCODLSTB, 0xcc }, + { STV090x_P1_MODCODLSTC, 0xcc }, + { STV090x_P1_MODCODLSTD, 0xcc }, + { STV090x_P1_MODCODLSTE, 0xcc }, + { STV090x_P1_MODCODLSTF, 0xcf }, + { STV090x_GENCFG, 0x1c }, + { STV090x_NBITER_NF4, 0x37 }, + { STV090x_NBITER_NF5, 0x29 }, + { STV090x_NBITER_NF6, 0x37 }, + { STV090x_NBITER_NF7, 0x33 }, + { STV090x_NBITER_NF8, 0x31 }, + { STV090x_NBITER_NF9, 0x2f }, + { STV090x_NBITER_NF10, 0x39 }, + { STV090x_NBITER_NF11, 0x3a }, + { STV090x_NBITER_NF12, 0x29 }, + { STV090x_NBITER_NF13, 0x37 }, + { STV090x_NBITER_NF14, 0x33 }, + { STV090x_NBITER_NF15, 0x2f }, + { STV090x_NBITER_NF16, 0x39 }, + { STV090x_NBITER_NF17, 0x3a }, + { STV090x_NBITERNOERR, 0x04 }, + { STV090x_GAINLLR_NF4, 0x0C }, + { STV090x_GAINLLR_NF5, 0x0F }, + { STV090x_GAINLLR_NF6, 0x11 }, + { STV090x_GAINLLR_NF7, 0x14 }, + { STV090x_GAINLLR_NF8, 0x17 }, + { STV090x_GAINLLR_NF9, 0x19 }, + { STV090x_GAINLLR_NF10, 0x20 }, + { STV090x_GAINLLR_NF11, 0x21 }, + { STV090x_GAINLLR_NF12, 0x0D }, + { STV090x_GAINLLR_NF13, 0x0F }, + { STV090x_GAINLLR_NF14, 0x13 }, + { STV090x_GAINLLR_NF15, 0x1A }, + { STV090x_GAINLLR_NF16, 0x1F }, + { STV090x_GAINLLR_NF17, 0x21 }, + { STV090x_RCCFGH, 0x20 }, + { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ + { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ +}; + +static struct stv090x_reg stv0900_cut20_val[] = { + + { STV090x_P2_DMDCFG3, 0xe8 }, + { STV090x_P2_DMDCFG4, 0x10 }, + { STV090x_P2_CARFREQ, 0x38 }, + { STV090x_P2_CARHDR, 0x20 }, + { STV090x_P2_KREFTMG, 0x5a }, + { STV090x_P2_SMAPCOEF7, 0x06 }, + { STV090x_P2_SMAPCOEF6, 0x00 }, + { STV090x_P2_SMAPCOEF5, 0x04 }, + { STV090x_P2_NOSCFG, 0x0c }, + { STV090x_P1_DMDCFG3, 0xe8 }, + { STV090x_P1_DMDCFG4, 0x10 }, + { STV090x_P1_CARFREQ, 0x38 }, + { STV090x_P1_CARHDR, 0x20 }, + { STV090x_P1_KREFTMG, 0x5a }, + { STV090x_P1_SMAPCOEF7, 0x06 }, + { STV090x_P1_SMAPCOEF6, 0x00 }, + { STV090x_P1_SMAPCOEF5, 0x04 }, + { STV090x_P1_NOSCFG, 0x0c }, + { STV090x_GAINLLR_NF4, 0x21 }, + { STV090x_GAINLLR_NF5, 0x21 }, + { STV090x_GAINLLR_NF6, 0x20 }, + { STV090x_GAINLLR_NF7, 0x1F }, + { STV090x_GAINLLR_NF8, 0x1E }, + { STV090x_GAINLLR_NF9, 0x1E }, + { STV090x_GAINLLR_NF10, 0x1D }, + { STV090x_GAINLLR_NF11, 0x1B }, + { STV090x_GAINLLR_NF12, 0x20 }, + { STV090x_GAINLLR_NF13, 0x20 }, + { STV090x_GAINLLR_NF14, 0x20 }, + { STV090x_GAINLLR_NF15, 0x20 }, + { STV090x_GAINLLR_NF16, 0x20 }, + { STV090x_GAINLLR_NF17, 0x21 }, +}; + +static struct stv090x_reg stv0903_cut20_val[] = { + { STV090x_P1_DMDCFG3, 0xe8 }, + { STV090x_P1_DMDCFG4, 0x10 }, + { STV090x_P1_CARFREQ, 0x38 }, + { STV090x_P1_CARHDR, 0x20 }, + { STV090x_P1_KREFTMG, 0x5a }, + { STV090x_P1_SMAPCOEF7, 0x06 }, + { STV090x_P1_SMAPCOEF6, 0x00 }, + { STV090x_P1_SMAPCOEF5, 0x04 }, + { STV090x_P1_NOSCFG, 0x0c }, + { STV090x_GAINLLR_NF4, 0x21 }, + { STV090x_GAINLLR_NF5, 0x21 }, + { STV090x_GAINLLR_NF6, 0x20 }, + { STV090x_GAINLLR_NF7, 0x1F }, + { STV090x_GAINLLR_NF8, 0x1E }, + { STV090x_GAINLLR_NF9, 0x1E }, + { STV090x_GAINLLR_NF10, 0x1D }, + { STV090x_GAINLLR_NF11, 0x1B }, + { STV090x_GAINLLR_NF12, 0x20 }, + { STV090x_GAINLLR_NF13, 0x20 }, + { STV090x_GAINLLR_NF14, 0x20 }, + { STV090x_GAINLLR_NF15, 0x20 }, + { STV090x_GAINLLR_NF16, 0x20 }, + { STV090x_GAINLLR_NF17, 0x21 } +}; + +/* Cut 2.0 Long Frame Tracking CR loop */ +static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = { + /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e }, + { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e }, + { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d }, + { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, + { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, + { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, + { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, + { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, + { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d }, + { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d }, + { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d }, + { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, + { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, + { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } +}; + +/* Cut 3.0 Long Frame Tracking CR loop */ +static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = { + /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b }, + { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, + { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, + { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, + { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, + { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, + { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, + { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, + { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 }, + { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a }, + { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a }, + { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b }, + { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b }, + { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b } +}; + +/* Cut 2.0 Long Frame Tracking CR Loop */ +static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = { + /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c }, + { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c }, + { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, + { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, + { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, + { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, + { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, + { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, + { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, + { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, + { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c } +}; + +/* Cut 3.0 Long Frame Tracking CR Loop */ +static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = { + /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a }, + { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a }, + { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, + { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, + { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, + { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, + { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, + { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, + { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, + { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, + { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } +}; + +static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = { + /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e }, + { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e }, + { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e } +}; + +static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = { + /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b }, + { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b }, + { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b } +}; + +/* Cut 2.0 Short Frame Tracking CR Loop */ +static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { + /* MODCOD 2M 5M 10M 20M 30M */ + { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d }, + { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c }, + { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }, + { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d } +}; + +/* Cut 3.0 Short Frame Tracking CR Loop */ +static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { + /* MODCOD 2M 5M 10M 20M 30M */ + { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, + { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, + { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, + { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A } +}; + +static inline s32 comp2(s32 __x, s32 __width) +{ + if (__width == 32) + return __x; + else + return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x; +} + +static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) +{ + const struct stv090x_config *config = state->config; + int ret; + + u8 b0[] = { reg >> 8, reg & 0xff }; + u8 buf; + + struct i2c_msg msg[] = { + { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, + { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } + }; + + ret = i2c_transfer(state->i2c, msg, 2); + if (ret != 2) { + if (ret != -ERESTARTSYS) + dprintk(FE_ERROR, 1, + "Read error, Reg=[0x%02x], Status=%d", + reg, ret); + + return ret < 0 ? ret : -EREMOTEIO; + } + if (unlikely(*state->verbose >= FE_DEBUGREG)) + dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x", + reg, buf); + + return (unsigned int) buf; +} + +static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) +{ + const struct stv090x_config *config = state->config; + int ret; + u8 buf[2 + count]; + struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + memcpy(&buf[2], data, count); + + if (unlikely(*state->verbose >= FE_DEBUGREG)) { + int i; + + printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); + for (i = 0; i < count; i++) + printk(" %02x", data[i]); + printk("\n"); + } + + ret = i2c_transfer(state->i2c, &i2c_msg, 1); + if (ret != 1) { + if (ret != -ERESTARTSYS) + dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", + reg, data[0], count, ret); + return ret < 0 ? ret : -EREMOTEIO; + } + + return 0; +} + +static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) +{ + return stv090x_write_regs(state, reg, &data, 1); +} + +static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) +{ + u32 reg; + + /* + * NOTE! A lock is used as a FSM to control the state in which + * access is serialized between two tuners on the same demod. + * This has nothing to do with a lock to protect a critical section + * which may in some other cases be confused with protecting I/O + * access to the demodulator gate. + * In case of any error, the lock is unlocked and exit within the + * relevant operations themselves. + */ + if (enable) { + if (state->config->tuner_i2c_lock) + state->config->tuner_i2c_lock(&state->frontend, 1); + else + mutex_lock(&state->internal->tuner_lock); + } + + reg = STV090x_READ_DEMOD(state, I2CRPT); + if (enable) { + dprintk(FE_DEBUG, 1, "Enable Gate"); + STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); + reg = 0xc8; + if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) + goto err; + + } else { + dprintk(FE_DEBUG, 1, "Disable Gate"); + STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); + reg = 0x4a; + if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) + goto err; + } + + if (!enable) { + if (state->config->tuner_i2c_lock) + state->config->tuner_i2c_lock(&state->frontend, 0); + else + mutex_unlock(&state->internal->tuner_lock); + } + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + if (state->config->tuner_i2c_lock) + state->config->tuner_i2c_lock(&state->frontend, 0); + else + mutex_unlock(&state->internal->tuner_lock); + return -1; +} + +static void stv090x_get_lock_tmg(struct stv090x_state *state) +{ + switch (state->algo) { + case STV090x_BLIND_SEARCH: + dprintk(FE_DEBUG, 1, "Blind Search"); + if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ + state->DemodTimeout = 1500; + state->FecTimeout = 400; + } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ + state->DemodTimeout = 1000; + state->FecTimeout = 300; + } else { /*SR >20Msps*/ + state->DemodTimeout = 700; + state->FecTimeout = 100; + } + break; + + case STV090x_COLD_SEARCH: + case STV090x_WARM_SEARCH: + default: + dprintk(FE_DEBUG, 1, "Normal Search"); + if (state->srate <= 1000000) { /*SR <=1Msps*/ + state->DemodTimeout = 4500; + state->FecTimeout = 1700; + } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ + state->DemodTimeout = 2500; + state->FecTimeout = 1100; + } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ + state->DemodTimeout = 1000; + state->FecTimeout = 550; + } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ + state->DemodTimeout = 700; + state->FecTimeout = 250; + } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ + state->DemodTimeout = 400; + state->FecTimeout = 130; + } else { /*SR >20Msps*/ + state->DemodTimeout = 300; + state->FecTimeout = 100; + } + break; + } + + if (state->algo == STV090x_WARM_SEARCH) + state->DemodTimeout /= 2; +} + +static int stv090x_set_srate(struct stv090x_state *state, u32 srate) +{ + u32 sym; + + if (srate > 60000000) { + sym = (srate << 4); /* SR * 2^16 / master_clk */ + sym /= (state->internal->mclk >> 12); + } else if (srate > 6000000) { + sym = (srate << 6); + sym /= (state->internal->mclk >> 10); + } else { + sym = (srate << 9); + sym /= (state->internal->mclk >> 7); + } + + if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ + goto err; + if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ + goto err; + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) +{ + u32 sym; + + srate = 105 * (srate / 100); + if (srate > 60000000) { + sym = (srate << 4); /* SR * 2^16 / master_clk */ + sym /= (state->internal->mclk >> 12); + } else if (srate > 6000000) { + sym = (srate << 6); + sym /= (state->internal->mclk >> 10); + } else { + sym = (srate << 9); + sym /= (state->internal->mclk >> 7); + } + + if (sym < 0x7fff) { + if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ + goto err; + if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ + goto err; + } else { + if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ + goto err; + if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ + goto err; + } + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) +{ + u32 sym; + + srate = 95 * (srate / 100); + if (srate > 60000000) { + sym = (srate << 4); /* SR * 2^16 / master_clk */ + sym /= (state->internal->mclk >> 12); + } else if (srate > 6000000) { + sym = (srate << 6); + sym /= (state->internal->mclk >> 10); + } else { + sym = (srate << 9); + sym /= (state->internal->mclk >> 7); + } + + if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ + goto err; + if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ + goto err; + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff) +{ + u32 ro; + + switch (rolloff) { + case STV090x_RO_20: + ro = 20; + break; + case STV090x_RO_25: + ro = 25; + break; + case STV090x_RO_35: + default: + ro = 35; + break; + } + + return srate + (srate * ro) / 100; +} + +static int stv090x_set_vit_thacq(struct stv090x_state *state) +{ + if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) + goto err; + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_set_vit_thtracq(struct stv090x_state *state) +{ + if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) + goto err; + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_set_viterbi(struct stv090x_state *state) +{ + switch (state->search_mode) { + case STV090x_SEARCH_AUTO: + if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ + goto err; + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ + goto err; + break; + case STV090x_SEARCH_DVBS1: + if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ + goto err; + switch (state->fec) { + case STV090x_PR12: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) + goto err; + break; + + case STV090x_PR23: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) + goto err; + break; + + case STV090x_PR34: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) + goto err; + break; + + case STV090x_PR56: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) + goto err; + break; + + case STV090x_PR78: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) + goto err; + break; + + default: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ + goto err; + break; + } + break; + case STV090x_SEARCH_DSS: + if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) + goto err; + switch (state->fec) { + case STV090x_PR12: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) + goto err; + break; + + case STV090x_PR23: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) + goto err; + break; + + case STV090x_PR67: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) + goto err; + break; + + default: + if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ + goto err; + break; + } + break; + default: + break; + } + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_stop_modcod(struct stv090x_state *state) +{ + if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) + goto err; + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_activate_modcod(struct stv090x_state *state) +{ + if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) + goto err; + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_activate_modcod_single(struct stv090x_state *state) +{ + + if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) + goto err; + + return 0; + +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) +{ + u32 reg; + + switch (state->demod) { + case STV090x_DEMODULATOR_0: + mutex_lock(&state->internal->demod_lock); + reg = stv090x_read_reg(state, STV090x_STOPCLK2); + STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); + if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) + goto err; + mutex_unlock(&state->internal->demod_lock); + break; + + case STV090x_DEMODULATOR_1: + mutex_lock(&state->internal->demod_lock); + reg = stv090x_read_reg(state, STV090x_STOPCLK2); + STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); + if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) + goto err; + mutex_unlock(&state->internal->demod_lock); + break; + + default: + dprintk(FE_ERROR, 1, "Wrong demodulator!"); + break; + } + return 0; +err: + mutex_unlock(&state->internal->demod_lock); + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_dvbs_track_crl(struct stv090x_state *state) +{ + if (state->internal->dev_ver >= 0x30) { + /* Set ACLC BCLC optimised value vs SR */ + if (state->srate >= 15000000) { + if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) + goto err; + } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { + if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) + goto err; + } else if (state->srate < 7000000) { + if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) + goto err; + } + + } else { + /* Cut 2.0 */ + if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) + goto err; + } + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_delivery_search(struct stv090x_state *state) +{ + u32 reg; + + switch (state->search_mode) { + case STV090x_SEARCH_DVBS1: + case STV090x_SEARCH_DSS: + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + + /* Activate Viterbi decoder in legacy search, + * do not use FRESVIT1, might impact VITERBI2 + */ + if (stv090x_vitclk_ctl(state, 0) < 0) + goto err; + + if (stv090x_dvbs_track_crl(state) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ + goto err; + + if (stv090x_set_vit_thacq(state) < 0) + goto err; + if (stv090x_set_viterbi(state) < 0) + goto err; + break; + + case STV090x_SEARCH_DVBS2: + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + + if (stv090x_vitclk_ctl(state, 1) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ + goto err; + if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) + goto err; + + if (state->internal->dev_ver <= 0x20) { + /* enable S2 carrier loop */ + if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) + goto err; + } else { + /* > Cut 3: Stop carrier 3 */ + if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) + goto err; + } + + if (state->demod_mode != STV090x_SINGLE) { + /* Cut 2: enable link during search */ + if (stv090x_activate_modcod(state) < 0) + goto err; + } else { + /* Single demodulator + * Authorize SHORT and LONG frames, + * QPSK, 8PSK, 16APSK and 32APSK + */ + if (stv090x_activate_modcod_single(state) < 0) + goto err; + } + + if (stv090x_set_vit_thtracq(state) < 0) + goto err; + break; + + case STV090x_SEARCH_AUTO: + default: + /* enable DVB-S2 and DVB-S2 in Auto MODE */ + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + + if (stv090x_vitclk_ctl(state, 0) < 0) + goto err; + + if (stv090x_dvbs_track_crl(state) < 0) + goto err; + + if (state->internal->dev_ver <= 0x20) { + /* enable S2 carrier loop */ + if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) + goto err; + } else { + /* > Cut 3: Stop carrier 3 */ + if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) + goto err; + } + + if (state->demod_mode != STV090x_SINGLE) { + /* Cut 2: enable link during search */ + if (stv090x_activate_modcod(state) < 0) + goto err; + } else { + /* Single demodulator + * Authorize SHORT and LONG frames, + * QPSK, 8PSK, 16APSK and 32APSK + */ + if (stv090x_activate_modcod_single(state) < 0) + goto err; + } + + if (stv090x_set_vit_thacq(state) < 0) + goto err; + + if (stv090x_set_viterbi(state) < 0) + goto err; + break; + } + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_start_search(struct stv090x_state *state) +{ + u32 reg, freq_abs; + s16 freq; + + /* Reset demodulator */ + reg = STV090x_READ_DEMOD(state, DMDISTATE); + STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); + if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) + goto err; + + if (state->internal->dev_ver <= 0x20) { + if (state->srate <= 5000000) { + if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) + goto err; + + /*enlarge the timing bandwidth for Low SR*/ + if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) + goto err; + } else { + /* If the symbol rate is >5 Msps + Set The carrier search up and low to auto mode */ + if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) + goto err; + /*reduce the timing bandwidth for high SR*/ + if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) + goto err; + } + } else { + /* >= Cut 3 */ + if (state->srate <= 5000000) { + /* enlarge the timing bandwidth for Low SR */ + STV090x_WRITE_DEMOD(state, RTCS2, 0x68); + } else { + /* reduce timing bandwidth for high SR */ + STV090x_WRITE_DEMOD(state, RTCS2, 0x44); + } + + /* Set CFR min and max to manual mode */ + STV090x_WRITE_DEMOD(state, CARCFG, 0x46); + + if (state->algo == STV090x_WARM_SEARCH) { + /* WARM Start + * CFR min = -1MHz, + * CFR max = +1MHz + */ + freq_abs = 1000 << 16; + freq_abs /= (state->internal->mclk / 1000); + freq = (s16) freq_abs; + } else { + /* COLD Start + * CFR min =- (SearchRange / 2 + 600KHz) + * CFR max = +(SearchRange / 2 + 600KHz) + * (600KHz for the tuner step size) + */ + freq_abs = (state->search_range / 2000) + 600; + freq_abs = freq_abs << 16; + freq_abs /= (state->internal->mclk / 1000); + freq = (s16) freq_abs; + } + + if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) + goto err; + + freq *= -1; + + if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) + goto err; + + } + + if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) + goto err; + + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) + goto err; + + if ((state->search_mode == STV090x_SEARCH_DVBS1) || + (state->search_mode == STV090x_SEARCH_DSS) || + (state->search_mode == STV090x_SEARCH_AUTO)) { + + if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) + goto err; + } + } + + if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) + goto err; + + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); + STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + reg = STV090x_READ_DEMOD(state, DMDCFG2); + STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); + if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) + goto err; + + if (state->internal->dev_ver >= 0x20) { + /*Frequency offset detector setting*/ + if (state->srate < 2000000) { + if (state->internal->dev_ver <= 0x20) { + /* Cut 2 */ + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) + goto err; + } else { + /* Cut 3 */ + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) + goto err; + } + if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) + goto err; + } else if (state->srate < 10000000) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) + goto err; + } else { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) + goto err; + } + } else { + if (state->srate < 10000000) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) + goto err; + } else { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) + goto err; + } + } + + switch (state->algo) { + case STV090x_WARM_SEARCH: + /* The symbol rate and the exact + * carrier Frequency are known + */ + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) + goto err; + break; + + case STV090x_COLD_SEARCH: + /* The symbol rate is known */ + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) + goto err; + break; + + default: + break; + } + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_get_agc2_min_level(struct stv090x_state *state) +{ + u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; + s32 i, j, steps, dir; + + if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) + goto err; + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); + STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ + goto err; + if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ + goto err; + if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ + goto err; + if (stv090x_set_srate(state, 1000000) < 0) + goto err; + + steps = state->search_range / 1000000; + if (steps <= 0) + steps = 1; + + dir = 1; + freq_step = (1000000 * 256) / (state->internal->mclk / 256); + freq_init = 0; + + for (i = 0; i < steps; i++) { + if (dir > 0) + freq_init = freq_init + (freq_step * i); + else + freq_init = freq_init - (freq_step * i); + + dir *= -1; + + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ + goto err; + msleep(10); + + agc2 = 0; + for (j = 0; j < 10; j++) { + agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | + STV090x_READ_DEMOD(state, AGC2I0); + } + agc2 /= 10; + if (agc2 < agc2_min) + agc2_min = agc2; + } + + return agc2_min; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) +{ + u8 r3, r2, r1, r0; + s32 srate, int_1, int_2, tmp_1, tmp_2; + + r3 = STV090x_READ_DEMOD(state, SFR3); + r2 = STV090x_READ_DEMOD(state, SFR2); + r1 = STV090x_READ_DEMOD(state, SFR1); + r0 = STV090x_READ_DEMOD(state, SFR0); + + srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0); + + int_1 = clk >> 16; + int_2 = srate >> 16; + + tmp_1 = clk % 0x10000; + tmp_2 = srate % 0x10000; + + srate = (int_1 * int_2) + + ((int_1 * tmp_2) >> 16) + + ((int_2 * tmp_1) >> 16); + + return srate; +} + +static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) +{ + struct dvb_frontend *fe = &state->frontend; + + int tmg_lock = 0, i; + s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; + u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; + u32 agc2th; + + if (state->internal->dev_ver >= 0x30) + agc2th = 0x2e00; + else + agc2th = 0x1f00; + + reg = STV090x_READ_DEMOD(state, DMDISTATE); + STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ + if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) + goto err; + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); + STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) + goto err; + + if (state->internal->dev_ver >= 0x30) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) + goto err; + + } else if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) + goto err; + } + + if (state->srate <= 2000000) + car_step = 1000; + else if (state->srate <= 5000000) + car_step = 2000; + else if (state->srate <= 12000000) + car_step = 3000; + else + car_step = 5000; + + steps = -1 + ((state->search_range / 1000) / car_step); + steps /= 2; + steps = (2 * steps) + 1; + if (steps < 0) + steps = 1; + else if (steps > 10) { + steps = 11; + car_step = (state->search_range / 1000) / 10; + } + cur_step = 0; + dir = 1; + freq = state->frequency; + + while ((!tmg_lock) && (cur_step < steps)) { + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) + goto err; + /* trigger acquisition */ + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) + goto err; + msleep(50); + for (i = 0; i < 10; i++) { + reg = STV090x_READ_DEMOD(state, DSTATUS); + if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) + tmg_cpt++; + agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | + STV090x_READ_DEMOD(state, AGC2I0); + } + agc2 /= 10; + srate_coarse = stv090x_get_srate(state, state->internal->mclk); + cur_step++; + dir *= -1; + if ((tmg_cpt >= 5) && (agc2 < agc2th) && + (srate_coarse < 50000000) && (srate_coarse > 850000)) + tmg_lock = 1; + else if (cur_step < steps) { + if (dir > 0) + freq += cur_step * car_step; + else + freq -= cur_step * car_step; + + /* Setup tuner */ + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_set_frequency) { + if (state->config->tuner_set_frequency(fe, freq) < 0) + goto err_gateoff; + } + + if (state->config->tuner_set_bandwidth) { + if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + msleep(50); + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_get_status) { + if (state->config->tuner_get_status(fe, ®) < 0) + goto err_gateoff; + } + + if (reg) + dprintk(FE_DEBUG, 1, "Tuner phase locked"); + else + dprintk(FE_DEBUG, 1, "Tuner unlocked"); + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + } + } + if (!tmg_lock) + srate_coarse = 0; + else + srate_coarse = stv090x_get_srate(state, state->internal->mclk); + + return srate_coarse; + +err_gateoff: + stv090x_i2c_gate_ctrl(state, 0); +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static u32 stv090x_srate_srch_fine(struct stv090x_state *state) +{ + u32 srate_coarse, freq_coarse, sym, reg; + + srate_coarse = stv090x_get_srate(state, state->internal->mclk); + freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; + freq_coarse |= STV090x_READ_DEMOD(state, CFR1); + sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ + + if (sym < state->srate) + srate_coarse = 0; + else { + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ + goto err; + if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) + goto err; + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) + goto err; + + if (state->internal->dev_ver >= 0x30) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) + goto err; + } else if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) + goto err; + } + + if (srate_coarse > 3000000) { + sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ + sym = (sym / 1000) * 65536; + sym /= (state->internal->mclk / 1000); + if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) + goto err; + sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */ + sym = (sym / 1000) * 65536; + sym /= (state->internal->mclk / 1000); + if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) + goto err; + sym = (srate_coarse / 1000) * 65536; + sym /= (state->internal->mclk / 1000); + if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) + goto err; + } else { + sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ + sym = (sym / 100) * 65536; + sym /= (state->internal->mclk / 100); + if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) + goto err; + sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */ + sym = (sym / 100) * 65536; + sym /= (state->internal->mclk / 100); + if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) + goto err; + sym = (srate_coarse / 100) * 65536; + sym /= (state->internal->mclk / 100); + if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) + goto err; + } + if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ + goto err; + } + + return srate_coarse; + +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) +{ + s32 timer = 0, lock = 0; + u32 reg; + u8 stat; + + while ((timer < timeout) && (!lock)) { + reg = STV090x_READ_DEMOD(state, DMDSTATE); + stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); + + switch (stat) { + case 0: /* searching */ + case 1: /* first PLH detected */ + default: + dprintk(FE_DEBUG, 1, "Demodulator searching .."); + lock = 0; + break; + case 2: /* DVB-S2 mode */ + case 3: /* DVB-S1/legacy mode */ + reg = STV090x_READ_DEMOD(state, DSTATUS); + lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); + break; + } + + if (!lock) + msleep(10); + else + dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK"); + + timer += 10; + } + return lock; +} + +static int stv090x_blind_search(struct stv090x_state *state) +{ + u32 agc2, reg, srate_coarse; + s32 cpt_fail, agc2_ovflw, i; + u8 k_ref, k_max, k_min; + int coarse_fail = 0; + int lock; + + k_max = 110; + k_min = 10; + + agc2 = stv090x_get_agc2_min_level(state); + + if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { + lock = 0; + } else { + + if (state->internal->dev_ver <= 0x20) { + if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) + goto err; + } else { + /* > Cut 3 */ + if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) + goto err; + } + + if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) + goto err; + + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ + goto err; + } + + k_ref = k_max; + do { + if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) + goto err; + if (stv090x_srate_srch_coarse(state) != 0) { + srate_coarse = stv090x_srate_srch_fine(state); + if (srate_coarse != 0) { + stv090x_get_lock_tmg(state); + lock = stv090x_get_dmdlock(state, + state->DemodTimeout); + } else { + lock = 0; + } + } else { + cpt_fail = 0; + agc2_ovflw = 0; + for (i = 0; i < 10; i++) { + agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | + STV090x_READ_DEMOD(state, AGC2I0); + if (agc2 >= 0xff00) + agc2_ovflw++; + reg = STV090x_READ_DEMOD(state, DSTATUS2); + if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && + (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) + + cpt_fail++; + } + if ((cpt_fail > 7) || (agc2_ovflw > 7)) + coarse_fail = 1; + + lock = 0; + } + k_ref -= 20; + } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); + } + + return lock; + +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_chk_tmg(struct stv090x_state *state) +{ + u32 reg; + s32 tmg_cpt = 0, i; + u8 freq, tmg_thh, tmg_thl; + int tmg_lock = 0; + + freq = STV090x_READ_DEMOD(state, CARFREQ); + tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); + tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); + if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) + goto err; + + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ + goto err; + msleep(10); + + for (i = 0; i < 10; i++) { + reg = STV090x_READ_DEMOD(state, DSTATUS); + if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) + tmg_cpt++; + msleep(1); + } + if (tmg_cpt >= 3) + tmg_lock = 1; + + if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ + goto err; + if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ + goto err; + + if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) + goto err; + + return tmg_lock; + +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) +{ + struct dvb_frontend *fe = &state->frontend; + + u32 reg; + s32 car_step, steps, cur_step, dir, freq, timeout_lock; + int lock = 0; + + if (state->srate >= 10000000) + timeout_lock = timeout_dmd / 3; + else + timeout_lock = timeout_dmd / 2; + + lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ + if (!lock) { + if (state->srate >= 10000000) { + if (stv090x_chk_tmg(state)) { + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) + goto err; + lock = stv090x_get_dmdlock(state, timeout_dmd); + } else { + lock = 0; + } + } else { + if (state->srate <= 4000000) + car_step = 1000; + else if (state->srate <= 7000000) + car_step = 2000; + else if (state->srate <= 10000000) + car_step = 3000; + else + car_step = 5000; + + steps = (state->search_range / 1000) / car_step; + steps /= 2; + steps = 2 * (steps + 1); + if (steps < 0) + steps = 2; + else if (steps > 12) + steps = 12; + + cur_step = 1; + dir = 1; + + if (!lock) { + freq = state->frequency; + state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; + while ((cur_step <= steps) && (!lock)) { + if (dir > 0) + freq += cur_step * car_step; + else + freq -= cur_step * car_step; + + /* Setup tuner */ + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_set_frequency) { + if (state->config->tuner_set_frequency(fe, freq) < 0) + goto err_gateoff; + } + + if (state->config->tuner_set_bandwidth) { + if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + msleep(50); + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_get_status) { + if (state->config->tuner_get_status(fe, ®) < 0) + goto err_gateoff; + } + + if (reg) + dprintk(FE_DEBUG, 1, "Tuner phase locked"); + else + dprintk(FE_DEBUG, 1, "Tuner unlocked"); + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); + if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) + goto err; + lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); + + dir *= -1; + cur_step++; + } + } + } + } + + return lock; + +err_gateoff: + stv090x_i2c_gate_ctrl(state, 0); +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) +{ + s32 timeout, inc, steps_max, srate, car_max; + + srate = state->srate; + car_max = state->search_range / 1000; + car_max += car_max / 10; + car_max = 65536 * (car_max / 2); + car_max /= (state->internal->mclk / 1000); + + if (car_max > 0x4000) + car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */ + + inc = srate; + inc /= state->internal->mclk / 1000; + inc *= 256; + inc *= 256; + inc /= 1000; + + switch (state->search_mode) { + case STV090x_SEARCH_DVBS1: + case STV090x_SEARCH_DSS: + inc *= 3; /* freq step = 3% of srate */ + timeout = 20; + break; + + case STV090x_SEARCH_DVBS2: + inc *= 4; + timeout = 25; + break; + + case STV090x_SEARCH_AUTO: + default: + inc *= 3; + timeout = 25; + break; + } + inc /= 100; + if ((inc > car_max) || (inc < 0)) + inc = car_max / 2; /* increment <= 1/8 Mclk */ + + timeout *= 27500; /* 27.5 Msps reference */ + if (srate > 0) + timeout /= (srate / 1000); + + if ((timeout > 100) || (timeout < 0)) + timeout = 100; + + steps_max = (car_max / inc) + 1; /* min steps = 3 */ + if ((steps_max > 100) || (steps_max < 0)) { + steps_max = 100; /* max steps <= 100 */ + inc = car_max / steps_max; + } + *freq_inc = inc; + *timeout_sw = timeout; + *steps = steps_max; + + return 0; +} + +static int stv090x_chk_signal(struct stv090x_state *state) +{ + s32 offst_car, agc2, car_max; + int no_signal; + + offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; + offst_car |= STV090x_READ_DEMOD(state, CFR1); + offst_car = comp2(offst_car, 16); + + agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; + agc2 |= STV090x_READ_DEMOD(state, AGC2I0); + car_max = state->search_range / 1000; + + car_max += (car_max / 10); /* 10% margin */ + car_max = (65536 * car_max / 2); + car_max /= state->internal->mclk / 1000; + + if (car_max > 0x4000) + car_max = 0x4000; + + if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) { + no_signal = 1; + dprintk(FE_DEBUG, 1, "No Signal"); + } else { + no_signal = 0; + dprintk(FE_DEBUG, 1, "Found Signal"); + } + + return no_signal; +} + +static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) +{ + int no_signal, lock = 0; + s32 cpt_step = 0, offst_freq, car_max; + u32 reg; + + car_max = state->search_range / 1000; + car_max += (car_max / 10); + car_max = (65536 * car_max / 2); + car_max /= (state->internal->mclk / 1000); + if (car_max > 0x4000) + car_max = 0x4000; + + if (zigzag) + offst_freq = 0; + else + offst_freq = -car_max + inc; + + do { + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) + goto err; + + reg = STV090x_READ_DEMOD(state, PDELCTRL1); + STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ + if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) + goto err; + + if (zigzag) { + if (offst_freq >= 0) + offst_freq = -offst_freq - 2 * inc; + else + offst_freq = -offst_freq; + } else { + offst_freq += 2 * inc; + } + + cpt_step++; + + lock = stv090x_get_dmdlock(state, timeout); + no_signal = stv090x_chk_signal(state); + + } while ((!lock) && + (!no_signal) && + ((offst_freq - inc) < car_max) && + ((offst_freq + inc) > -car_max) && + (cpt_step < steps_max)); + + reg = STV090x_READ_DEMOD(state, PDELCTRL1); + STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) + goto err; + + return lock; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_sw_algo(struct stv090x_state *state) +{ + int no_signal, zigzag, lock = 0; + u32 reg; + + s32 dvbs2_fly_wheel; + s32 inc, timeout_step, trials, steps_max; + + /* get params */ + stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); + + switch (state->search_mode) { + case STV090x_SEARCH_DVBS1: + case STV090x_SEARCH_DSS: + /* accelerate the frequency detector */ + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) + goto err; + } + + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) + goto err; + zigzag = 0; + break; + + case STV090x_SEARCH_DVBS2: + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) + goto err; + } + + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) + goto err; + zigzag = 1; + break; + + case STV090x_SEARCH_AUTO: + default: + /* accelerate the frequency detector */ + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) + goto err; + } + + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) + goto err; + zigzag = 0; + break; + } + + trials = 0; + do { + lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); + no_signal = stv090x_chk_signal(state); + trials++; + + /*run the SW search 2 times maximum*/ + if (lock || no_signal || (trials == 2)) { + /*Check if the demod is not losing lock in DVBS2*/ + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) + goto err; + } + + reg = STV090x_READ_DEMOD(state, DMDSTATE); + if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { + /*Check if the demod is not losing lock in DVBS2*/ + msleep(timeout_step); + reg = STV090x_READ_DEMOD(state, DMDFLYW); + dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); + if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */ + msleep(timeout_step); + reg = STV090x_READ_DEMOD(state, DMDFLYW); + dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); + } + if (dvbs2_fly_wheel < 0xd) { + /*FALSE lock, The demod is losing lock */ + lock = 0; + if (trials < 2) { + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) + goto err; + } + + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) + goto err; + } + } + } + } + } while ((!lock) && (trials < 2) && (!no_signal)); + + return lock; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) +{ + u32 reg; + enum stv090x_delsys delsys; + + reg = STV090x_READ_DEMOD(state, DMDSTATE); + if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) + delsys = STV090x_DVBS2; + else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { + reg = STV090x_READ_DEMOD(state, FECM); + if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) + delsys = STV090x_DSS; + else + delsys = STV090x_DVBS1; + } else { + delsys = STV090x_ERROR; + } + + return delsys; +} + +/* in Hz */ +static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) +{ + s32 derot, int_1, int_2, tmp_1, tmp_2; + + derot = STV090x_READ_DEMOD(state, CFR2) << 16; + derot |= STV090x_READ_DEMOD(state, CFR1) << 8; + derot |= STV090x_READ_DEMOD(state, CFR0); + + derot = comp2(derot, 24); + int_1 = mclk >> 12; + int_2 = derot >> 12; + + /* carrier_frequency = MasterClock * Reg / 2^24 */ + tmp_1 = mclk % 0x1000; + tmp_2 = derot % 0x1000; + + derot = (int_1 * int_2) + + ((int_1 * tmp_2) >> 12) + + ((int_2 * tmp_1) >> 12); + + return derot; +} + +static int stv090x_get_viterbi(struct stv090x_state *state) +{ + u32 reg, rate; + + reg = STV090x_READ_DEMOD(state, VITCURPUN); + rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); + + switch (rate) { + case 13: + state->fec = STV090x_PR12; + break; + + case 18: + state->fec = STV090x_PR23; + break; + + case 21: + state->fec = STV090x_PR34; + break; + + case 24: + state->fec = STV090x_PR56; + break; + + case 25: + state->fec = STV090x_PR67; + break; + + case 26: + state->fec = STV090x_PR78; + break; + + default: + state->fec = STV090x_PRERR; + break; + } + + return 0; +} + +static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) +{ + struct dvb_frontend *fe = &state->frontend; + + u8 tmg; + u32 reg; + s32 i = 0, offst_freq; + + msleep(5); + + if (state->algo == STV090x_BLIND_SEARCH) { + tmg = STV090x_READ_DEMOD(state, TMGREG2); + STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); + while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) { + tmg = STV090x_READ_DEMOD(state, TMGREG2); + msleep(5); + i += 5; + } + } + state->delsys = stv090x_get_std(state); + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_get_frequency) { + if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; + state->frequency += offst_freq; + + if (stv090x_get_viterbi(state) < 0) + goto err; + + reg = STV090x_READ_DEMOD(state, DMDMODCOD); + state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); + state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; + state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; + reg = STV090x_READ_DEMOD(state, TMGOBS); + state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); + reg = STV090x_READ_DEMOD(state, FECM); + state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); + + if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_get_frequency) { + if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) + return STV090x_RANGEOK; + else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) + return STV090x_RANGEOK; + else + return STV090x_OUTOFRANGE; /* Out of Range */ + } else { + if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) + return STV090x_RANGEOK; + else + return STV090x_OUTOFRANGE; + } + + return STV090x_OUTOFRANGE; + +err_gateoff: + stv090x_i2c_gate_ctrl(state, 0); +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) +{ + s32 offst_tmg; + + offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; + offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; + offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); + + offst_tmg = comp2(offst_tmg, 24); /* 2's complement */ + if (!offst_tmg) + offst_tmg = 1; + + offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg); + offst_tmg /= 320; + + return offst_tmg; +} + +static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) +{ + u8 aclc = 0x29; + s32 i; + struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low; + + if (state->internal->dev_ver == 0x20) { + car_loop = stv090x_s2_crl_cut20; + car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20; + car_loop_apsk_low = stv090x_s2_apsk_crl_cut20; + } else { + /* >= Cut 3 */ + car_loop = stv090x_s2_crl_cut30; + car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30; + car_loop_apsk_low = stv090x_s2_apsk_crl_cut30; + } + + if (modcod < STV090x_QPSK_12) { + i = 0; + while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod)) + i++; + + if (i >= 3) + i = 2; + + } else { + i = 0; + while ((i < 14) && (modcod != car_loop[i].modcod)) + i++; + + if (i >= 14) { + i = 0; + while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod)) + i++; + + if (i >= 11) + i = 10; + } + } + + if (modcod <= STV090x_QPSK_25) { + if (pilots) { + if (state->srate <= 3000000) + aclc = car_loop_qpsk_low[i].crl_pilots_on_2; + else if (state->srate <= 7000000) + aclc = car_loop_qpsk_low[i].crl_pilots_on_5; + else if (state->srate <= 15000000) + aclc = car_loop_qpsk_low[i].crl_pilots_on_10; + else if (state->srate <= 25000000) + aclc = car_loop_qpsk_low[i].crl_pilots_on_20; + else + aclc = car_loop_qpsk_low[i].crl_pilots_on_30; + } else { + if (state->srate <= 3000000) + aclc = car_loop_qpsk_low[i].crl_pilots_off_2; + else if (state->srate <= 7000000) + aclc = car_loop_qpsk_low[i].crl_pilots_off_5; + else if (state->srate <= 15000000) + aclc = car_loop_qpsk_low[i].crl_pilots_off_10; + else if (state->srate <= 25000000) + aclc = car_loop_qpsk_low[i].crl_pilots_off_20; + else + aclc = car_loop_qpsk_low[i].crl_pilots_off_30; + } + + } else if (modcod <= STV090x_8PSK_910) { + if (pilots) { + if (state->srate <= 3000000) + aclc = car_loop[i].crl_pilots_on_2; + else if (state->srate <= 7000000) + aclc = car_loop[i].crl_pilots_on_5; + else if (state->srate <= 15000000) + aclc = car_loop[i].crl_pilots_on_10; + else if (state->srate <= 25000000) + aclc = car_loop[i].crl_pilots_on_20; + else + aclc = car_loop[i].crl_pilots_on_30; + } else { + if (state->srate <= 3000000) + aclc = car_loop[i].crl_pilots_off_2; + else if (state->srate <= 7000000) + aclc = car_loop[i].crl_pilots_off_5; + else if (state->srate <= 15000000) + aclc = car_loop[i].crl_pilots_off_10; + else if (state->srate <= 25000000) + aclc = car_loop[i].crl_pilots_off_20; + else + aclc = car_loop[i].crl_pilots_off_30; + } + } else { /* 16APSK and 32APSK */ + if (state->srate <= 3000000) + aclc = car_loop_apsk_low[i].crl_pilots_on_2; + else if (state->srate <= 7000000) + aclc = car_loop_apsk_low[i].crl_pilots_on_5; + else if (state->srate <= 15000000) + aclc = car_loop_apsk_low[i].crl_pilots_on_10; + else if (state->srate <= 25000000) + aclc = car_loop_apsk_low[i].crl_pilots_on_20; + else + aclc = car_loop_apsk_low[i].crl_pilots_on_30; + } + + return aclc; +} + +static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) +{ + struct stv090x_short_frame_crloop *short_crl = NULL; + s32 index = 0; + u8 aclc = 0x0b; + + switch (state->modulation) { + case STV090x_QPSK: + default: + index = 0; + break; + case STV090x_8PSK: + index = 1; + break; + case STV090x_16APSK: + index = 2; + break; + case STV090x_32APSK: + index = 3; + break; + } + + if (state->internal->dev_ver >= 0x30) { + /* Cut 3.0 and up */ + short_crl = stv090x_s2_short_crl_cut30; + } else { + /* Cut 2.0 and up: we don't support cuts older than 2.0 */ + short_crl = stv090x_s2_short_crl_cut20; + } + + if (state->srate <= 3000000) + aclc = short_crl[index].crl_2; + else if (state->srate <= 7000000) + aclc = short_crl[index].crl_5; + else if (state->srate <= 15000000) + aclc = short_crl[index].crl_10; + else if (state->srate <= 25000000) + aclc = short_crl[index].crl_20; + else + aclc = short_crl[index].crl_30; + + return aclc; +} + +static int stv090x_optimize_track(struct stv090x_state *state) +{ + struct dvb_frontend *fe = &state->frontend; + + enum stv090x_rolloff rolloff; + enum stv090x_modcod modcod; + + s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0; + u32 reg; + + srate = stv090x_get_srate(state, state->internal->mclk); + srate += stv090x_get_tmgoffst(state, srate); + + switch (state->delsys) { + case STV090x_DVBS1: + case STV090x_DSS: + if (state->search_mode == STV090x_SEARCH_AUTO) { + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + } + reg = STV090x_READ_DEMOD(state, DEMOD); + STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); + STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); + if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) + goto err; + + if (state->internal->dev_ver >= 0x30) { + if (stv090x_get_viterbi(state) < 0) + goto err; + + if (state->fec == STV090x_PR12) { + if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) + goto err; + } else { + if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) + goto err; + } + } + + if (STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS1) < 0) + goto err; + break; + + case STV090x_DVBS2: + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + if (state->internal->dev_ver >= 0x30) { + if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) + goto err; + } + if (state->frame_len == STV090x_LONG_FRAME) { + reg = STV090x_READ_DEMOD(state, DMDMODCOD); + modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); + pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; + aclc = stv090x_optimize_carloop(state, modcod, pilots); + if (modcod <= STV090x_QPSK_910) { + STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); + } else if (modcod <= STV090x_8PSK_910) { + if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) + goto err; + } + if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { + if (modcod <= STV090x_16APSK_910) { + if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) + goto err; + } else { + if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) + goto err; + } + } + } else { + /*Carrier loop setting for short frame*/ + aclc = stv090x_optimize_carloop_short(state); + if (state->modulation == STV090x_QPSK) { + if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) + goto err; + } else if (state->modulation == STV090x_8PSK) { + if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) + goto err; + } else if (state->modulation == STV090x_16APSK) { + if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) + goto err; + } else if (state->modulation == STV090x_32APSK) { + if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) + goto err; + } + } + + STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS2); /* PER */ + break; + + case STV090x_ERROR: + default: + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); + STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + break; + } + + f_1 = STV090x_READ_DEMOD(state, CFR2); + f_0 = STV090x_READ_DEMOD(state, CFR1); + reg = STV090x_READ_DEMOD(state, TMGOBS); + rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); + + if (state->algo == STV090x_BLIND_SEARCH) { + STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); + reg = STV090x_READ_DEMOD(state, DMDCFGMD); + STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); + STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); + if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) + goto err; + + if (stv090x_set_srate(state, srate) < 0) + goto err; + blind_tune = 1; + + if (stv090x_dvbs_track_crl(state) < 0) + goto err; + } + + if (state->internal->dev_ver >= 0x20) { + if ((state->search_mode == STV090x_SEARCH_DVBS1) || + (state->search_mode == STV090x_SEARCH_DSS) || + (state->search_mode == STV090x_SEARCH_AUTO)) { + + if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) + goto err; + } + } + + if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) + goto err; + + /* AUTO tracking MODE */ + if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) + goto err; + /* AUTO tracking MODE */ + if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) + goto err; + + if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || + (state->srate < 10000000)) { + /* update initial carrier freq with the found freq offset */ + if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) + goto err; + state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; + + if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { + + if (state->algo != STV090x_WARM_SEARCH) { + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_set_bandwidth) { + if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + } + } + if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) + msleep(50); /* blind search: wait 50ms for SR stabilization */ + else + msleep(5); + + stv090x_get_lock_tmg(state); + + if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) + goto err; + + i = 0; + + while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { + + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) + goto err; + i++; + } + } + + } + + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) + goto err; + } + + if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) + stv090x_set_vit_thtracq(state); + + return 0; + +err_gateoff: + stv090x_i2c_gate_ctrl(state, 0); +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) +{ + s32 timer = 0, lock = 0, stat; + u32 reg; + + while ((timer < timeout) && (!lock)) { + reg = STV090x_READ_DEMOD(state, DMDSTATE); + stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); + + switch (stat) { + case 0: /* searching */ + case 1: /* first PLH detected */ + default: + lock = 0; + break; + + case 2: /* DVB-S2 mode */ + reg = STV090x_READ_DEMOD(state, PDELSTATUS1); + lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); + break; + + case 3: /* DVB-S1/legacy mode */ + reg = STV090x_READ_DEMOD(state, VSTATUSVIT); + lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); + break; + } + if (!lock) { + msleep(10); + timer += 10; + } + } + return lock; +} + +static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) +{ + u32 reg; + s32 timer = 0; + int lock; + + lock = stv090x_get_dmdlock(state, timeout_dmd); + if (lock) + lock = stv090x_get_feclock(state, timeout_fec); + + if (lock) { + lock = 0; + + while ((timer < timeout_fec) && (!lock)) { + reg = STV090x_READ_DEMOD(state, TSSTATUS); + lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); + msleep(1); + timer++; + } + } + + return lock; +} + +static int stv090x_set_s2rolloff(struct stv090x_state *state) +{ + u32 reg; + + if (state->internal->dev_ver <= 0x20) { + /* rolloff to auto mode if DVBS2 */ + reg = STV090x_READ_DEMOD(state, DEMOD); + STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); + if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) + goto err; + } else { + /* DVB-S2 rolloff to auto mode if DVBS2 */ + reg = STV090x_READ_DEMOD(state, DEMOD); + STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); + if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) + goto err; + } + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + + +static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) +{ + struct dvb_frontend *fe = &state->frontend; + enum stv090x_signal_state signal_state = STV090x_NOCARRIER; + u32 reg; + s32 agc1_power, power_iq = 0, i; + int lock = 0, low_sr = 0; + + reg = STV090x_READ_DEMOD(state, TSCFGH); + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ + if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ + goto err; + + if (state->internal->dev_ver >= 0x20) { + if (state->srate > 5000000) { + if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) + goto err; + } else { + if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) + goto err; + } + } + + stv090x_get_lock_tmg(state); + + if (state->algo == STV090x_BLIND_SEARCH) { + state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ + if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ + goto err; + if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) + goto err; + if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */ + goto err; + } else { + /* known srate */ + if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) + goto err; + + if (state->srate < 2000000) { + /* SR < 2MSPS */ + if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) + goto err; + } else { + /* SR >= 2Msps */ + if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) + goto err; + } + + if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) + goto err; + + if (state->internal->dev_ver >= 0x20) { + if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) + goto err; + if (state->algo == STV090x_COLD_SEARCH) + state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; + else if (state->algo == STV090x_WARM_SEARCH) + state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; + } + + /* if cold start or warm (Symbolrate is known) + * use a Narrow symbol rate scan range + */ + if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ + goto err; + + if (stv090x_set_srate(state, state->srate) < 0) + goto err; + + if (stv090x_set_max_srate(state, state->internal->mclk, + state->srate) < 0) + goto err; + if (stv090x_set_min_srate(state, state->internal->mclk, + state->srate) < 0) + goto err; + + if (state->srate >= 10000000) + low_sr = 0; + else + low_sr = 1; + } + + /* Setup tuner */ + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_set_bbgain) { + reg = state->config->tuner_bbgain; + if (reg == 0) + reg = 10; /* default: 10dB */ + if (state->config->tuner_set_bbgain(fe, reg) < 0) + goto err_gateoff; + } + + if (state->config->tuner_set_frequency) { + if (state->config->tuner_set_frequency(fe, state->frequency) < 0) + goto err_gateoff; + } + + if (state->config->tuner_set_bandwidth) { + if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + msleep(50); + + if (state->config->tuner_get_status) { + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + if (state->config->tuner_get_status(fe, ®) < 0) + goto err_gateoff; + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + if (reg) + dprintk(FE_DEBUG, 1, "Tuner phase locked"); + else { + dprintk(FE_DEBUG, 1, "Tuner unlocked"); + return STV090x_NOCARRIER; + } + } + + msleep(10); + agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), + STV090x_READ_DEMOD(state, AGCIQIN0)); + + if (agc1_power == 0) { + /* If AGC1 integrator value is 0 + * then read POWERI, POWERQ + */ + for (i = 0; i < 5; i++) { + power_iq += (STV090x_READ_DEMOD(state, POWERI) + + STV090x_READ_DEMOD(state, POWERQ)) >> 1; + } + power_iq /= 5; + } + + if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { + dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); + lock = 0; + signal_state = STV090x_NOAGC1; + } else { + reg = STV090x_READ_DEMOD(state, DEMOD); + STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); + + if (state->internal->dev_ver <= 0x20) { + /* rolloff to auto mode if DVBS2 */ + STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); + } else { + /* DVB-S2 rolloff to auto mode if DVBS2 */ + STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); + } + if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) + goto err; + + if (stv090x_delivery_search(state) < 0) + goto err; + + if (state->algo != STV090x_BLIND_SEARCH) { + if (stv090x_start_search(state) < 0) + goto err; + } + } + + if (signal_state == STV090x_NOAGC1) + return signal_state; + + if (state->algo == STV090x_BLIND_SEARCH) + lock = stv090x_blind_search(state); + + else if (state->algo == STV090x_COLD_SEARCH) + lock = stv090x_get_coldlock(state, state->DemodTimeout); + + else if (state->algo == STV090x_WARM_SEARCH) + lock = stv090x_get_dmdlock(state, state->DemodTimeout); + + if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { + if (!low_sr) { + if (stv090x_chk_tmg(state)) + lock = stv090x_sw_algo(state); + } + } + + if (lock) + signal_state = stv090x_get_sig_params(state); + + if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */ + stv090x_optimize_track(state); + + if (state->internal->dev_ver >= 0x20) { + /* >= Cut 2.0 :release TS reset after + * demod lock and optimized Tracking + */ + reg = STV090x_READ_DEMOD(state, TSCFGH); + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ + if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) + goto err; + + msleep(3); + + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ + if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) + goto err; + + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ + if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) + goto err; + } + + lock = stv090x_get_lock(state, state->FecTimeout, + state->FecTimeout); + if (lock) { + if (state->delsys == STV090x_DVBS2) { + stv090x_set_s2rolloff(state); + + reg = STV090x_READ_DEMOD(state, PDELCTRL2); + STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); + if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) + goto err; + /* Reset DVBS2 packet delinator error counter */ + reg = STV090x_READ_DEMOD(state, PDELCTRL2); + STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); + if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS2) < 0) /* PER */ + goto err; + } else { + if (STV090x_WRITE_DEMOD(state, ERRCTRL1, ERRCTRL1_DVBS1) < 0) + goto err; + } + /* Reset the Total packet counter */ + if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) + goto err; + /* Reset the packet Error counter2 */ + if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) + goto err; + } else { + signal_state = STV090x_NODATA; + stv090x_chk_signal(state); + } + } + return signal_state; + +err_gateoff: + stv090x_i2c_gate_ctrl(state, 0); +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +#ifndef USE_API3 +static enum dvbfe_search stv090x_search(struct dvb_frontend *fe) +#else +static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +#endif +{ + struct stv090x_state *state = fe->demodulator_priv; + struct dtv_frontend_properties *props = &fe->dtv_property_cache; + +#ifndef USE_API3 + if (props->frequency == 0) +#else + return DVBFE_ALGO_SEARCH_INVALID; +#endif + + state->delsys = props->delivery_system; +#ifndef USE_API3 + state->frequency = props->frequency; + state->srate = props->symbol_rate; +#else + state->frequency = p->frequency; + state->srate = p->u.qpsk.symbol_rate; +#endif + state->search_mode = STV090x_SEARCH_AUTO; + state->algo = STV090x_COLD_SEARCH; + state->fec = STV090x_PRERR; + if (state->srate > 10000000) { + dprintk(FE_DEBUG, 1, "Search range: 10 MHz"); + state->search_range = 10000000; + } else { + dprintk(FE_DEBUG, 1, "Search range: 5 MHz"); + state->search_range = 5000000; + } + + if (stv090x_algo(state) == STV090x_RANGEOK) { + dprintk(FE_DEBUG, 1, "Search success!"); + return DVBFE_ALGO_SEARCH_SUCCESS; + } else { + dprintk(FE_DEBUG, 1, "Search failed!"); + return DVBFE_ALGO_SEARCH_FAILED; + } + + return DVBFE_ALGO_SEARCH_ERROR; +} + +static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg, dstatus; + u8 search_state; + + *status = 0; + + dstatus = STV090x_READ_DEMOD(state, DSTATUS); + if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD)) + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; + + reg = STV090x_READ_DEMOD(state, DMDSTATE); + search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); + + switch (search_state) { + case 0: /* searching */ + case 1: /* first PLH detected */ + default: + dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)"); + break; + + case 2: /* DVB-S2 mode */ + dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); + if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { + reg = STV090x_READ_DEMOD(state, PDELSTATUS1); + if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { + *status |= FE_HAS_VITERBI; + reg = STV090x_READ_DEMOD(state, TSSTATUS); + if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) + *status |= FE_HAS_SYNC | FE_HAS_LOCK; + } + } + break; + + case 3: /* DVB-S1/legacy mode */ + dprintk(FE_DEBUG, 1, "Delivery system: DVB-S"); + if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) { + reg = STV090x_READ_DEMOD(state, VSTATUSVIT); + if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { + *status |= FE_HAS_VITERBI; + reg = STV090x_READ_DEMOD(state, TSSTATUS); + if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) + *status |= FE_HAS_SYNC | FE_HAS_LOCK; + } + } + break; + } + + return 0; +} + +static int stv090x_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct stv090x_state *state = fe->demodulator_priv; + + u32 reg, h, m, l; + enum fe_status status; + + stv090x_read_status(fe, &status); + if (!(status & FE_HAS_LOCK)) { + *ber = 1 << 23; /* Max BER */ + } else { + /* Counter 1 */ + reg = STV090x_READ_DEMOD(state, ERRCNT12); + h = STV090x_GETFIELD_Px(reg, ERR_CNT12_FIELD); + + reg = STV090x_READ_DEMOD(state, ERRCNT11); + m = STV090x_GETFIELD_Px(reg, ERR_CNT11_FIELD); + + reg = STV090x_READ_DEMOD(state, ERRCNT10); + l = STV090x_GETFIELD_Px(reg, ERR_CNT10_FIELD); + + *ber = ((h << 16) | (m << 8) | l); + } + return 0; +} + +#if 0 +static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) +{ + struct stv090x_state *state = fe->demodulator_priv; + + s32 count_4, count_3, count_2, count_1, count_0, count; + u32 reg, h, m, l; + enum fe_status status; + + stv090x_read_status(fe, &status); + if (!(status & FE_HAS_LOCK)) { + *per = 1 << 23; /* Max PER */ + } else { + /* Counter 2 */ + reg = STV090x_READ_DEMOD(state, ERRCNT22); + h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); + + reg = STV090x_READ_DEMOD(state, ERRCNT21); + m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); + + reg = STV090x_READ_DEMOD(state, ERRCNT20); + l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); + + *per = ((h << 16) | (m << 8) | l); + + count_4 = STV090x_READ_DEMOD(state, FBERCPT4); + count_3 = STV090x_READ_DEMOD(state, FBERCPT3); + count_2 = STV090x_READ_DEMOD(state, FBERCPT2); + count_1 = STV090x_READ_DEMOD(state, FBERCPT1); + count_0 = STV090x_READ_DEMOD(state, FBERCPT0); + + if ((!count_4) && (!count_3)) { + count = (count_2 & 0xff) << 16; + count |= (count_1 & 0xff) << 8; + count |= count_0 & 0xff; + } else { + count = 1 << 24; + } + if (count == 0) + *per = 1; + } + if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) + goto err; + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} +#endif + +static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) +{ + int res = 0; + int min = 0, med; + + if ((val >= tab[min].read && val < tab[max].read) || + (val >= tab[max].read && val < tab[min].read)) { + while ((max - min) > 1) { + med = (max + min) / 2; + if ((val >= tab[min].read && val < tab[med].read) || + (val >= tab[med].read && val < tab[min].read)) + max = med; + else + min = med; + } + res = ((val - tab[min].read) * + (tab[max].real - tab[min].real) / + (tab[max].read - tab[min].read)) + + tab[min].real; + } else { + if (tab[min].read < tab[max].read) { + if (val < tab[min].read) + res = tab[min].real; + else if (val >= tab[max].read) + res = tab[max].real; + } else { + if (val >= tab[min].read) + res = tab[min].real; + else if (val < tab[max].read) + res = tab[max].real; + } + } + + return res; +} + +static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg; + s32 agc_0, agc_1, agc; + s32 str; + + reg = STV090x_READ_DEMOD(state, AGCIQIN1); + agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); + reg = STV090x_READ_DEMOD(state, AGCIQIN0); + agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); + agc = MAKEWORD16(agc_1, agc_0); + + str = stv090x_table_lookup(stv090x_rf_tab, + ARRAY_SIZE(stv090x_rf_tab) - 1, agc); + if (agc > stv090x_rf_tab[0].read) + str = 0; + else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) + str = -100; +#ifdef DBVALS + *strength = str; +#else + *strength = (str + 100) * 0xFFFF / 100; +#endif + return 0; +} + +static int stv090x_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct stv090x_state *state = fe->demodulator_priv; + u8 err0, err1; + + *ucblocks = 0; + switch (state->delsys) { + case STV090x_DVBS2: + err0 = STV090x_READ_DEMOD(state, UPCRCKO0); + err1 = STV090x_READ_DEMOD(state, UPCRCKO1); + *ucblocks = (err1 << 8) | err0; + default: + break; + } + return 0; +} + +static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg_0, reg_1, reg, i; + s32 val_0, val_1, val = 0; + u8 lock_f; +#ifndef DBVALS + s32 div; + u32 last; +#endif + + switch (state->delsys) { + case STV090x_DVBS2: + reg = STV090x_READ_DEMOD(state, DSTATUS); + lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); + if (lock_f) { + msleep(5); + for (i = 0; i < 16; i++) { + reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); + val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); + reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); + val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD); + val += MAKEWORD16(val_1, val_0); + msleep(1); + } + val /= 16; +#ifdef DBVALS + *cnr = stv090x_table_lookup(stv090x_s2cn_tab, + ARRAY_SIZE(stv090x_s2cn_tab) - 1, val); +#else + last = ARRAY_SIZE(stv090x_s2cn_tab) - 1; + div = stv090x_s2cn_tab[0].read - + stv090x_s2cn_tab[last].read; + *cnr = 0xFFFF - ((val * 0xFFFF) / div); +#endif + } else +#ifdef DBVALS + *cnr = -30; +#else + *cnr = 0; +#endif + break; + + case STV090x_DVBS1: + case STV090x_DSS: + reg = STV090x_READ_DEMOD(state, DSTATUS); + lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); + if (lock_f) { + msleep(5); + for (i = 0; i < 16; i++) { + reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); + val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); + reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); + val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD); + val += MAKEWORD16(val_1, val_0); + msleep(1); + } + val /= 16; +#ifdef DBVALS + *cnr = stv090x_table_lookup(stv090x_s1cn_tab, + ARRAY_SIZE(stv090x_s1cn_tab) - 1, val); +#else + last = ARRAY_SIZE(stv090x_s1cn_tab) - 1; + div = stv090x_s1cn_tab[0].read - + stv090x_s1cn_tab[last].read; + *cnr = 0xFFFF - ((val * 0xFFFF) / div); +#endif + } else + *cnr = 0; + break; + default: + break; + } + + return 0; +} + +static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg; + + reg = STV090x_READ_DEMOD(state, DISTXCTL); + switch (tone) { + case SEC_TONE_ON: + STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); + STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + break; + + case SEC_TONE_OFF: + STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); + STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + break; + default: + return -EINVAL; + } + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + + +static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe) +{ + return DVBFE_ALGO_CUSTOM; +} + +static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg, idle = 0, fifo_full = 1; + int i; + + reg = STV090x_READ_DEMOD(state, DISTXCTL); + + STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, + (state->config->diseqc_envelope_mode) ? 4 : 2); + STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + + STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + + for (i = 0; i < cmd->msg_len; i++) { + + while (fifo_full) { + reg = STV090x_READ_DEMOD(state, DISTXSTATUS); + fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); + } + + if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) + goto err; + } + reg = STV090x_READ_DEMOD(state, DISTXCTL); + STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + + i = 0; + + while ((!idle) && (i < 10)) { + reg = STV090x_READ_DEMOD(state, DISTXSTATUS); + idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); + msleep(10); + i++; + } + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg, idle = 0, fifo_full = 1; + u8 mode, value; + int i; + + reg = STV090x_READ_DEMOD(state, DISTXCTL); + + if (burst == SEC_MINI_A) { + mode = (state->config->diseqc_envelope_mode) ? 5 : 3; + value = 0x00; + } else { + mode = (state->config->diseqc_envelope_mode) ? 4 : 2; + value = 0xFF; + } + + STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); + STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + + STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + + while (fifo_full) { + reg = STV090x_READ_DEMOD(state, DISTXSTATUS); + fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); + } + + if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) + goto err; + + reg = STV090x_READ_DEMOD(state, DISTXCTL); + STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); + if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) + goto err; + + i = 0; + + while ((!idle) && (i < 10)) { + reg = STV090x_READ_DEMOD(state, DISTXSTATUS); + idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); + msleep(10); + i++; + } + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg = 0, i = 0, rx_end = 0; + + while ((rx_end != 1) && (i < 10)) { + msleep(10); + i++; + reg = STV090x_READ_DEMOD(state, DISRX_ST0); + rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); + } + + if (rx_end) { + reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); + for (i = 0; i < reply->msg_len; i++) + reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); + } + + return 0; +} + +static int stv090x_sleep(struct dvb_frontend *fe) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg; + u8 full_standby = 0; + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (state->config->tuner_sleep) { + if (state->config->tuner_sleep(fe) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep", + state->device == STV0900 ? "STV0900" : "STV0903", + state->demod); + + mutex_lock(&state->internal->demod_lock); + + switch (state->demod) { + case STV090x_DEMODULATOR_0: + /* power off ADC 1 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR1); + STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); + if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) + goto err; + /* power off DiSEqC 1 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR2); + STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); + if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) + goto err; + + /* check whether path 2 is already sleeping, that is when + ADC2 is off */ + reg = stv090x_read_reg(state, STV090x_TSTTNR3); + if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0) + full_standby = 1; + + /* stop clocks */ + reg = stv090x_read_reg(state, STV090x_STOPCLK1); + /* packet delineator 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1); + /* ADC 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1); + /* FEC clock is shared between the two paths, only stop it + when full standby is possible */ + if (full_standby) + STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); + if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) + goto err; + reg = stv090x_read_reg(state, STV090x_STOPCLK2); + /* sampling 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); + /* viterbi 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1); + /* TS clock is shared between the two paths, only stop it + when full standby is possible */ + if (full_standby) + STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); + if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) + goto err; + break; + + case STV090x_DEMODULATOR_1: + /* power off ADC 2 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR3); + STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); + if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) + goto err; + /* power off DiSEqC 2 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR4); + STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); + if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) + goto err; + + /* check whether path 1 is already sleeping, that is when + ADC1 is off */ + reg = stv090x_read_reg(state, STV090x_TSTTNR1); + if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0) + full_standby = 1; + + /* stop clocks */ + reg = stv090x_read_reg(state, STV090x_STOPCLK1); + /* packet delineator 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1); + /* ADC 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1); + /* FEC clock is shared between the two paths, only stop it + when full standby is possible */ + if (full_standby) + STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); + if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) + goto err; + reg = stv090x_read_reg(state, STV090x_STOPCLK2); + /* sampling 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); + /* viterbi 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1); + /* TS clock is shared between the two paths, only stop it + when full standby is possible */ + if (full_standby) + STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); + if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) + goto err; + break; + + default: + dprintk(FE_ERROR, 1, "Wrong demodulator!"); + break; + } + + if (full_standby) { + /* general power off */ + reg = stv090x_read_reg(state, STV090x_SYNTCTRL); + STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) + goto err; + } + + mutex_unlock(&state->internal->demod_lock); + return 0; + +err_gateoff: + stv090x_i2c_gate_ctrl(state, 0); +err: + mutex_unlock(&state->internal->demod_lock); + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_wakeup(struct dvb_frontend *fe) +{ + struct stv090x_state *state = fe->demodulator_priv; + u32 reg; + + dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby", + state->device == STV0900 ? "STV0900" : "STV0903", + state->demod); + + mutex_lock(&state->internal->demod_lock); + + /* general power on */ + reg = stv090x_read_reg(state, STV090x_SYNTCTRL); + STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) + goto err; + + switch (state->demod) { + case STV090x_DEMODULATOR_0: + /* power on ADC 1 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR1); + STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); + if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) + goto err; + /* power on DiSEqC 1 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR2); + STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1); + if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) + goto err; + + /* activate clocks */ + reg = stv090x_read_reg(state, STV090x_STOPCLK1); + /* packet delineator 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0); + /* ADC 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0); + /* FEC clock */ + STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); + if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) + goto err; + reg = stv090x_read_reg(state, STV090x_STOPCLK2); + /* sampling 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0); + /* viterbi 1 clock */ + STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0); + /* TS clock */ + STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); + if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) + goto err; + break; + + case STV090x_DEMODULATOR_1: + /* power on ADC 2 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR3); + STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1); + if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) + goto err; + /* power on DiSEqC 2 */ + reg = stv090x_read_reg(state, STV090x_TSTTNR4); + STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1); + if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) + goto err; + + /* activate clocks */ + reg = stv090x_read_reg(state, STV090x_STOPCLK1); + /* packet delineator 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0); + /* ADC 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0); + /* FEC clock */ + STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); + if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) + goto err; + reg = stv090x_read_reg(state, STV090x_STOPCLK2); + /* sampling 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0); + /* viterbi 2 clock */ + STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0); + /* TS clock */ + STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); + if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) + goto err; + break; + + default: + dprintk(FE_ERROR, 1, "Wrong demodulator!"); + break; + } + + mutex_unlock(&state->internal->demod_lock); + return 0; +err: + mutex_unlock(&state->internal->demod_lock); + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static void stv090x_release(struct dvb_frontend *fe) +{ + struct stv090x_state *state = fe->demodulator_priv; + + state->internal->num_used--; + if (state->internal->num_used <= 0) { + + dprintk(FE_ERROR, 1, "Actually removing"); + + remove_dev(state->internal); + kfree(state->internal); + } + + kfree(state); +} + +static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) +{ + u32 reg = 0; + + reg = stv090x_read_reg(state, STV090x_GENCFG); + + switch (ldpc_mode) { + case STV090x_DUAL: + default: + if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { + /* set LDPC to dual mode */ + if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) + goto err; + + state->demod_mode = STV090x_DUAL; + + reg = stv090x_read_reg(state, STV090x_TSTRES0); + STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); + if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) + goto err; + STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); + if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) + goto err; + + if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) + goto err; + } + break; + + case STV090x_SINGLE: + if (stv090x_stop_modcod(state) < 0) + goto err; + if (stv090x_activate_modcod_single(state) < 0) + goto err; + + if (state->demod == STV090x_DEMODULATOR_1) { + if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ + goto err; + } else { + if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ + goto err; + } + + reg = stv090x_read_reg(state, STV090x_TSTRES0); + STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); + if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) + goto err; + STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); + if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) + goto err; + + reg = STV090x_READ_DEMOD(state, PDELCTRL1); + STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); + if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); + if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) + goto err; + break; + } + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +/* return (Hz), clk in Hz*/ +static u32 stv090x_get_mclk(struct stv090x_state *state) +{ + const struct stv090x_config *config = state->config; + u32 div, reg; + u8 ratio; + + div = stv090x_read_reg(state, STV090x_NCOARSE); + reg = stv090x_read_reg(state, STV090x_SYNTCTRL); + ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; + + return (div + 1) * config->xtal / ratio; /* kHz */ +} + +static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) +{ + const struct stv090x_config *config = state->config; + u32 reg, div, clk_sel; + + reg = stv090x_read_reg(state, STV090x_SYNTCTRL); + clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); + + div = ((clk_sel * mclk) / config->xtal) - 1; + + reg = stv090x_read_reg(state, STV090x_NCOARSE); + STV090x_SETFIELD(reg, M_DIV_FIELD, div); + if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) + goto err; + + state->internal->mclk = stv090x_get_mclk(state); + + /*Set the DiseqC frequency to 22KHz */ + div = state->internal->mclk / 704000; + if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) + goto err; + if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) + goto err; + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_set_tspath(struct stv090x_state *state) +{ + u32 reg; + + if (state->internal->dev_ver >= 0x20) { + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + switch (state->config->ts2_mode) { + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); + break; + + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ + goto err; + reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); + STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); + if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) + goto err; + reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); + STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); + if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) + goto err; + break; + } + break; + + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + switch (state->config->ts2_mode) { + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) + goto err; + break; + + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) + goto err; + break; + } + break; + } + } else { + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + switch (state->config->ts2_mode) { + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); + break; + + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); + reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); + STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); + if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) + goto err; + reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); + STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); + if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) + goto err; + break; + } + break; + + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + switch (state->config->ts2_mode) { + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + default: + stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); + break; + + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); + break; + } + break; + } + } + + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_DVBCI: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_SERIAL_PUNCTURED: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_SERIAL_CONTINUOUS: + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + break; + + default: + break; + } + + switch (state->config->ts2_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_DVBCI: + reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_SERIAL_PUNCTURED: + reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) + goto err; + break; + + case STV090x_TSMODE_SERIAL_CONTINUOUS: + reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); + STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); + STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); + STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) + goto err; + break; + + default: + break; + } + + if (state->config->ts1_clk > 0) { + u32 speed; + + switch (state->config->ts1_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + default: + speed = state->internal->mclk / + (state->config->ts1_clk / 4); + if (speed < 0x08) + speed = 0x08; + if (speed > 0xFF) + speed = 0xFF; + break; + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + speed = state->internal->mclk / + (state->config->ts1_clk / 32); + if (speed < 0x20) + speed = 0x20; + if (speed > 0xFF) + speed = 0xFF; + break; + } + reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); + STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); + if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) + goto err; + } + + if (state->config->ts2_clk > 0) { + u32 speed; + + switch (state->config->ts2_mode) { + case STV090x_TSMODE_PARALLEL_PUNCTURED: + case STV090x_TSMODE_DVBCI: + default: + speed = state->internal->mclk / + (state->config->ts2_clk / 4); + if (speed < 0x08) + speed = 0x08; + if (speed > 0xFF) + speed = 0xFF; + break; + case STV090x_TSMODE_SERIAL_PUNCTURED: + case STV090x_TSMODE_SERIAL_CONTINUOUS: + speed = state->internal->mclk / + (state->config->ts2_clk / 32); + if (speed < 0x20) + speed = 0x20; + if (speed > 0xFF) + speed = 0xFF; + break; + } + reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); + STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); + if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) + goto err; + } + + + printk("TSCFGH resets\n"); + + reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) + goto err; + + reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); + if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) + goto err; + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_init(struct dvb_frontend *fe) +{ + struct stv090x_state *state = fe->demodulator_priv; + const struct stv090x_config *config = state->config; + u32 reg; + + if (state->internal->mclk == 0) { + /* call tuner init to configure the tuner's clock output + divider directly before setting up the master clock of + the stv090x. */ + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (config->tuner_init) { + if (config->tuner_init(fe) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + + stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ + msleep(5); + if (stv090x_write_reg(state, STV090x_SYNTCTRL, + 0x20 | config->clk_mode) < 0) + goto err; + stv090x_get_mclk(state); + } + + if (stv090x_wakeup(fe) < 0) { + dprintk(FE_ERROR, 1, "Error waking device"); + goto err; + } + + if (stv090x_ldpc_mode(state, state->demod_mode) < 0) + goto err; + + reg = STV090x_READ_DEMOD(state, TNRCFG2); + STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); + if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) + goto err; + reg = STV090x_READ_DEMOD(state, DEMOD); + STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); + if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) + goto err; + + if (stv090x_i2c_gate_ctrl(state, 1) < 0) + goto err; + + if (config->tuner_set_mode) { + if (config->tuner_set_mode(fe, TUNER_WAKE) < 0) + goto err_gateoff; + } + + if (config->tuner_init) { + if (config->tuner_init(fe) < 0) + goto err_gateoff; + } + + if (stv090x_i2c_gate_ctrl(state, 0) < 0) + goto err; + +#if 0 + if (stv090x_set_tspath(state) < 0) + goto err; +#endif + return 0; + +err_gateoff: + stv090x_i2c_gate_ctrl(state, 0); +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +static int stv090x_setup(struct dvb_frontend *fe) +{ + struct stv090x_state *state = fe->demodulator_priv; + const struct stv090x_config *config = state->config; + const struct stv090x_reg *stv090x_initval = NULL; + const struct stv090x_reg *stv090x_cut20_val = NULL; + unsigned long t1_size = 0, t2_size = 0; + u32 reg = 0; + + int i; + + if (state->device == STV0900) { + dprintk(FE_DEBUG, 1, "Initializing STV0900"); + stv090x_initval = stv0900_initval; + t1_size = ARRAY_SIZE(stv0900_initval); + stv090x_cut20_val = stv0900_cut20_val; + t2_size = ARRAY_SIZE(stv0900_cut20_val); + } else if (state->device == STV0903) { + dprintk(FE_DEBUG, 1, "Initializing STV0903"); + stv090x_initval = stv0903_initval; + t1_size = ARRAY_SIZE(stv0903_initval); + stv090x_cut20_val = stv0903_cut20_val; + t2_size = ARRAY_SIZE(stv0903_cut20_val); + } + + /* STV090x init */ + + /* Stop Demod */ + if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) + goto err; + + msleep(5); + + /* Set No Tuner Mode */ + if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) + goto err; + + /* I2C repeater OFF */ + STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); + if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) + goto err; + + if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ + goto err; + msleep(5); + if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ + goto err; + if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ + goto err; + msleep(5); + + /* write initval */ + dprintk(FE_DEBUG, 1, "Setting up initial values"); + for (i = 0; i < t1_size; i++) { + if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) + goto err; + } + + state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); + if (state->internal->dev_ver >= 0x20) { + if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) + goto err; + + /* write cut20_val*/ + dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values"); + for (i = 0; i < t2_size; i++) { + if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) + goto err; + } + + } else if (state->internal->dev_ver < 0x20) { + dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!", + state->internal->dev_ver); + + goto err; + } else if (state->internal->dev_ver > 0x30) { + /* we shouldn't bail out from here */ + dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!", + state->internal->dev_ver); + } + + /* ADC1 range */ + reg = stv090x_read_reg(state, STV090x_TSTTNR1); + STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, + (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1); + if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) + goto err; + + /* ADC2 range */ + reg = stv090x_read_reg(state, STV090x_TSTTNR3); + STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, + (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1); + if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) + goto err; + + if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) + goto err; + if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) + goto err; + + if (stv090x_set_tspath(state) < 0) + goto err; + + return 0; +err: + dprintk(FE_ERROR, 1, "I/O error"); + return -1; +} + +int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value, + u8 xor_value) +{ + struct stv090x_state *state = fe->demodulator_priv; + u8 reg = 0; + + STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir); + STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value); + STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value); + + return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); +} +EXPORT_SYMBOL(stv090x_set_gpio); + +static struct dvb_frontend_ops stv090x_ops = { +#ifndef USE_API3 + .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, +#endif + .info = { + .name = "STV090x Multistandard", +#ifdef USE_API3 + .type = FE_QPSK, +#endif + .frequency_min = 950000, + .frequency_max = 2150000, + .frequency_stepsize = 0, + .frequency_tolerance = 0, + .symbol_rate_min = 1000000, + .symbol_rate_max = 45000000, + .caps = FE_CAN_INVERSION_AUTO | + FE_CAN_FEC_AUTO | + FE_CAN_QPSK | + FE_CAN_2G_MODULATION + }, + + .release = stv090x_release, + .init = stv090x_init, + + .sleep = stv090x_sleep, + .get_frontend_algo = stv090x_frontend_algo, + + .diseqc_send_master_cmd = stv090x_send_diseqc_msg, + .diseqc_send_burst = stv090x_send_diseqc_burst, + .diseqc_recv_slave_reply = stv090x_recv_slave_reply, + .set_tone = stv090x_set_tone, + + .search = stv090x_search, + .read_status = stv090x_read_status, + .read_ber = stv090x_read_ber, + .read_signal_strength = stv090x_read_signal_strength, + .read_snr = stv090x_read_cnr, + .read_ucblocks = stv090x_read_ucblocks, +}; + + +struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, + struct i2c_adapter *i2c, + enum stv090x_demodulator demod) +{ + struct stv090x_state *state = NULL; + struct stv090x_dev *temp_int; + + state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL); + if (state == NULL) + goto error; + + state->verbose = &verbose; + state->config = config; + state->i2c = i2c; + state->frontend.ops = stv090x_ops; + state->frontend.demodulator_priv = state; + state->demod = demod; + state->demod_mode = config->demod_mode; /* Single or Dual mode */ + state->device = config->device; + state->rolloff = STV090x_RO_35; /* default */ + + temp_int = find_dev(state->i2c, + state->config->address); + + if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) { + state->internal = temp_int->internal; + state->internal->num_used++; + dprintk(FE_INFO, 1, "Found Internal Structure!"); + } else { + state->internal = kmalloc(sizeof(struct stv090x_internal), + GFP_KERNEL); + if (!state->internal) + goto error; + temp_int = append_internal(state->internal); + if (!temp_int) { + kfree(state->internal); + goto error; + } + state->internal->num_used = 1; + state->internal->mclk = 0; + state->internal->dev_ver = 0; + state->internal->i2c_adap = state->i2c; + state->internal->i2c_addr = state->config->address; + dprintk(FE_INFO, 1, "Create New Internal Structure!"); + + mutex_init(&state->internal->demod_lock); + mutex_init(&state->internal->tuner_lock); + + if (stv090x_setup(&state->frontend) < 0) { + dprintk(FE_ERROR, 1, "Error setting up device"); + goto err_remove; + } + } + + /* workaround for stuck DiSEqC output */ + if (config->diseqc_envelope_mode) + stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); + + dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", + state->device == STV0900 ? "STV0900" : "STV0903", + demod, + state->internal->dev_ver); + + return &state->frontend; + +err_remove: + remove_dev(state->internal); + kfree(state->internal); +error: + kfree(state); + return NULL; +} +EXPORT_SYMBOL(stv090x_attach); +MODULE_PARM_DESC(verbose, "Set Verbosity level"); +MODULE_AUTHOR("Manu Abraham"); +MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend"); +MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,134 @@ +/* + STV0900/0903 Multistandard Broadcast Frontend driver + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __STV090x_H +#define __STV090x_H + +enum stv090x_demodulator { + STV090x_DEMODULATOR_0 = 1, + STV090x_DEMODULATOR_1 +}; + +enum stv090x_device { + STV0903 = 0, + STV0900, +}; + +enum stv090x_mode { + STV090x_DUAL = 0, + STV090x_SINGLE +}; + +enum stv090x_tsmode { + STV090x_TSMODE_SERIAL_PUNCTURED = 1, + STV090x_TSMODE_SERIAL_CONTINUOUS, + STV090x_TSMODE_PARALLEL_PUNCTURED, + STV090x_TSMODE_DVBCI +}; + +enum stv090x_clkmode { + STV090x_CLK_INT = 0, /* Clk i/p = CLKI */ + STV090x_CLK_EXT = 2 /* Clk i/p = XTALI */ +}; + +enum stv090x_i2crpt { + STV090x_RPTLEVEL_256 = 0, + STV090x_RPTLEVEL_128 = 1, + STV090x_RPTLEVEL_64 = 2, + STV090x_RPTLEVEL_32 = 3, + STV090x_RPTLEVEL_16 = 4, + STV090x_RPTLEVEL_8 = 5, + STV090x_RPTLEVEL_4 = 6, + STV090x_RPTLEVEL_2 = 7, +}; + +enum stv090x_adc_range { + STV090x_ADC_2Vpp = 0, + STV090x_ADC_1Vpp = 1 +}; + +struct stv090x_config { + enum stv090x_device device; + enum stv090x_mode demod_mode; + enum stv090x_clkmode clk_mode; + + u32 xtal; /* default: 8000000 */ + u8 address; /* default: 0x68 */ + + u8 ts1_mode; + u8 ts2_mode; + u32 ts1_clk; + u32 ts2_clk; + + u8 ts1_tei : 1; + u8 ts2_tei : 1; + + enum stv090x_i2crpt repeater_level; + + u8 tuner_bbgain; /* default: 10db */ + enum stv090x_adc_range adc1_range; /* default: 2Vpp */ + enum stv090x_adc_range adc2_range; /* default: 2Vpp */ + + bool diseqc_envelope_mode; + + int (*tuner_init) (struct dvb_frontend *fe); + int (*tuner_sleep) (struct dvb_frontend *fe); + int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode); + int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency); + int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency); + int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth); + int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth); + int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain); + int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain); + int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk); + int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status); + void (*tuner_i2c_lock) (struct dvb_frontend *fe, int lock); +}; + +#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE)) + +extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, + struct i2c_adapter *i2c, + enum stv090x_demodulator demod); + +/* dir = 0 -> output, dir = 1 -> input/open-drain */ +extern int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, + u8 dir, u8 value, u8 xor_value); + +#else + +static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, + struct i2c_adapter *i2c, + enum stv090x_demodulator demod) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} + +static inline int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, + u8 opd, u8 value, u8 xor_value) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return -ENODEV; +} +#endif /* CONFIG_DVB_STV090x */ + +#endif /* __STV090x_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_priv.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_priv.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,279 @@ +/* + STV0900/0903 Multistandard Broadcast Frontend driver + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __STV090x_PRIV_H +#define __STV090x_PRIV_H + +#include "dvb_frontend.h" + +#define FE_ERROR 0 +#define FE_NOTICE 1 +#define FE_INFO 2 +#define FE_DEBUG 3 +#define FE_DEBUGREG 4 + +#define dprintk(__y, __z, format, arg...) do { \ + if (__z) { \ + if ((verbose > FE_ERROR) && (verbose > __y)) \ + printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \ + else if ((verbose > FE_NOTICE) && (verbose > __y)) \ + printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \ + else if ((verbose > FE_INFO) && (verbose > __y)) \ + printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \ + else if ((verbose > FE_DEBUG) && (verbose > __y)) \ + printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \ + } else { \ + if (verbose > __y) \ + printk(format, ##arg); \ + } \ +} while (0) + +#define STV090x_READ_DEMOD(__state, __reg) (( \ + (__state)->demod == STV090x_DEMODULATOR_1) ? \ + stv090x_read_reg(__state, STV090x_P2_##__reg) : \ + stv090x_read_reg(__state, STV090x_P1_##__reg)) + +#define STV090x_WRITE_DEMOD(__state, __reg, __data) (( \ + (__state)->demod == STV090x_DEMODULATOR_1) ? \ + stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\ + stv090x_write_reg(__state, STV090x_P1_##__reg, __data)) + +#define STV090x_ADDR_OFFST(__state, __x) (( \ + (__state->demod) == STV090x_DEMODULATOR_1) ? \ + STV090x_P1_##__x : \ + STV090x_P2_##__x) + + +#define STV090x_SETFIELD(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_##bitf) - 1) <<\ + STV090x_OFFST_##bitf))) | \ + (val << STV090x_OFFST_##bitf)) + +#define STV090x_GETFIELD(val, bitf) ((val >> STV090x_OFFST_##bitf) & ((1 << STV090x_WIDTH_##bitf) - 1)) + + +#define STV090x_SETFIELD_Px(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_Px_##bitf) - 1) <<\ + STV090x_OFFST_Px_##bitf))) | \ + (val << STV090x_OFFST_Px_##bitf)) + +#define STV090x_GETFIELD_Px(val, bitf) ((val >> STV090x_OFFST_Px_##bitf) & ((1 << STV090x_WIDTH_Px_##bitf) - 1)) + +#define MAKEWORD16(__a, __b) (((__a) << 8) | (__b)) + +#define MSB(__x) ((__x >> 8) & 0xff) +#define LSB(__x) (__x & 0xff) + + +#define STV090x_IQPOWER_THRESHOLD 30 +#define STV090x_SEARCH_AGC2_TH_CUT20 700 +#define STV090x_SEARCH_AGC2_TH_CUT30 1400 + +#define STV090x_SEARCH_AGC2_TH(__ver) \ + ((__ver <= 0x20) ? \ + STV090x_SEARCH_AGC2_TH_CUT20 : \ + STV090x_SEARCH_AGC2_TH_CUT30) + +enum stv090x_signal_state { + STV090x_NOAGC1, + STV090x_NOCARRIER, + STV090x_NODATA, + STV090x_DATAOK, + STV090x_RANGEOK, + STV090x_OUTOFRANGE +}; + +enum stv090x_fec { + STV090x_PR12 = 0, + STV090x_PR23, + STV090x_PR34, + STV090x_PR45, + STV090x_PR56, + STV090x_PR67, + STV090x_PR78, + STV090x_PR89, + STV090x_PR910, + STV090x_PRERR +}; + +enum stv090x_modulation { + STV090x_QPSK, + STV090x_8PSK, + STV090x_16APSK, + STV090x_32APSK, + STV090x_UNKNOWN +}; + +enum stv090x_frame { + STV090x_LONG_FRAME, + STV090x_SHORT_FRAME +}; + +enum stv090x_pilot { + STV090x_PILOTS_OFF, + STV090x_PILOTS_ON +}; + +enum stv090x_rolloff { + STV090x_RO_35, + STV090x_RO_25, + STV090x_RO_20 +}; + +enum stv090x_inversion { + STV090x_IQ_AUTO, + STV090x_IQ_NORMAL, + STV090x_IQ_SWAP +}; + +enum stv090x_modcod { + STV090x_DUMMY_PLF = 0, + STV090x_QPSK_14, + STV090x_QPSK_13, + STV090x_QPSK_25, + STV090x_QPSK_12, + STV090x_QPSK_35, + STV090x_QPSK_23, + STV090x_QPSK_34, + STV090x_QPSK_45, + STV090x_QPSK_56, + STV090x_QPSK_89, + STV090x_QPSK_910, + STV090x_8PSK_35, + STV090x_8PSK_23, + STV090x_8PSK_34, + STV090x_8PSK_56, + STV090x_8PSK_89, + STV090x_8PSK_910, + STV090x_16APSK_23, + STV090x_16APSK_34, + STV090x_16APSK_45, + STV090x_16APSK_56, + STV090x_16APSK_89, + STV090x_16APSK_910, + STV090x_32APSK_34, + STV090x_32APSK_45, + STV090x_32APSK_56, + STV090x_32APSK_89, + STV090x_32APSK_910, + STV090x_MODCODE_UNKNOWN +}; + +enum stv090x_search { + STV090x_SEARCH_DSS = 0, + STV090x_SEARCH_DVBS1, + STV090x_SEARCH_DVBS2, + STV090x_SEARCH_AUTO +}; + +enum stv090x_algo { + STV090x_BLIND_SEARCH, + STV090x_COLD_SEARCH, + STV090x_WARM_SEARCH +}; + +enum stv090x_delsys { + STV090x_ERROR = 0, + STV090x_DVBS1 = 1, + STV090x_DVBS2, + STV090x_DSS +}; + +struct stv090x_long_frame_crloop { + enum stv090x_modcod modcod; + + u8 crl_pilots_on_2; + u8 crl_pilots_off_2; + u8 crl_pilots_on_5; + u8 crl_pilots_off_5; + u8 crl_pilots_on_10; + u8 crl_pilots_off_10; + u8 crl_pilots_on_20; + u8 crl_pilots_off_20; + u8 crl_pilots_on_30; + u8 crl_pilots_off_30; +}; + +struct stv090x_short_frame_crloop { + enum stv090x_modulation modulation; + + u8 crl_2; /* SR < 3M */ + u8 crl_5; /* 3 < SR <= 7M */ + u8 crl_10; /* 7 < SR <= 15M */ + u8 crl_20; /* 10 < SR <= 25M */ + u8 crl_30; /* 10 < SR <= 45M */ +}; + +struct stv090x_reg { + u16 addr; + u8 data; +}; + +struct stv090x_tab { + s32 real; + s32 read; +}; + +struct stv090x_internal { + struct i2c_adapter *i2c_adap; + u8 i2c_addr; + + struct mutex demod_lock; /* Lock access to shared register */ + struct mutex tuner_lock; /* Lock access to tuners */ + s32 mclk; /* Masterclock Divider factor */ + u32 dev_ver; + + int num_used; +}; + +struct stv090x_state { + enum stv090x_device device; + enum stv090x_demodulator demod; + enum stv090x_mode demod_mode; + struct stv090x_internal *internal; + + struct i2c_adapter *i2c; + const struct stv090x_config *config; + struct dvb_frontend frontend; + + u32 *verbose; /* Cached module verbosity */ + + enum stv090x_delsys delsys; + enum stv090x_fec fec; + enum stv090x_modulation modulation; + enum stv090x_modcod modcod; + enum stv090x_search search_mode; + enum stv090x_frame frame_len; + enum stv090x_pilot pilots; + enum stv090x_rolloff rolloff; + enum stv090x_inversion inversion; + enum stv090x_algo algo; + + u32 frequency; + u32 srate; + + s32 tuner_bw; + + s32 search_range; + + s32 DemodTimeout; + s32 FecTimeout; +}; + +#endif /* __STV090x_PRIV_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_reg.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_reg.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_reg.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv090x_reg.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,2371 @@ +/* + STV0900/0903 Multistandard Broadcast Frontend driver + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __STV090x_REG_H +#define __STV090x_REG_H + +#define STV090x_MID 0xf100 +#define STV090x_OFFST_MCHIP_IDENT_FIELD 4 +#define STV090x_WIDTH_MCHIP_IDENT_FIELD 4 +#define STV090x_OFFST_MRELEASE_FIELD 0 +#define STV090x_WIDTH_MRELEASE_FIELD 4 + +#define STV090x_DACR1 0xf113 +#define STV090x_OFFST_DACR1_MODE_FIELD 5 +#define STV090x_WIDTH_DACR1_MODE_FIELD 3 +#define STV090x_OFFST_DACR1_VALUE_FIELD 0 +#define STV090x_WIDTH_DACR1_VALUE_FIELD 4 + +#define STV090x_DACR2 0xf114 +#define STV090x_OFFST_DACR2_VALUE_FIELD 0 +#define STV090x_WIDTH_DACR2_VALUE_FIELD 8 + +#define STV090x_OUTCFG 0xf11c +#define STV090x_OFFST_OUTSERRS1_HZ_FIELD 6 +#define STV090x_WIDTH_OUTSERRS1_HZ_FIELD 1 +#define STV090x_OFFST_OUTSERRS2_HZ_FIELD 5 +#define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1 +#define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4 +#define STV090x_WIDTH_OUTSERRS3_HZ_FIELD 1 +#define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3 +#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1 + +#define STV090x_MODECFG 0xf11d + +#define STV090x_IRQSTATUS3 0xf120 +#define STV090x_OFFST_SPLL_LOCK_FIELD 5 +#define STV090x_WIDTH_SPLL_LOCK_FIELD 1 +#define STV090x_OFFST_SSTREAM_LCK_3_FIELD 4 +#define STV090x_WIDTH_SSTREAM_LCK_3_FIELD 1 +#define STV090x_OFFST_SSTREAM_LCK_2_FIELD 3 +#define STV090x_WIDTH_SSTREAM_LCK_2_FIELD 1 +#define STV090x_OFFST_SSTREAM_LCK_1_FIELD 2 +#define STV090x_WIDTH_SSTREAM_LCK_1_FIELD 1 +#define STV090x_OFFST_SDVBS1_PRF_2_FIELD 1 +#define STV090x_WIDTH_SDVBS1_PRF_2_FIELD 1 +#define STV090x_OFFST_SDVBS1_PRF_1_FIELD 0 +#define STV090x_WIDTH_SDVBS1_PRF_1_FIELD 1 + +#define STV090x_IRQSTATUS2 0xf121 +#define STV090x_OFFST_SSPY_ENDSIM_3_FIELD 7 +#define STV090x_WIDTH_SSPY_ENDSIM_3_FIELD 1 +#define STV090x_OFFST_SSPY_ENDSIM_2_FIELD 6 +#define STV090x_WIDTH_SSPY_ENDSIM_2_FIELD 1 +#define STV090x_OFFST_SSPY_ENDSIM_1_FIELD 5 +#define STV090x_WIDTH_SSPY_ENDSIM_1_FIELD 1 +#define STV090x_OFFST_SPKTDEL_ERROR_2_FIELD 4 +#define STV090x_WIDTH_SPKTDEL_ERROR_2_FIELD 1 +#define STV090x_OFFST_SPKTDEL_LOCKB_2_FIELD 3 +#define STV090x_WIDTH_SPKTDEL_LOCKB_2_FIELD 1 +#define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD 2 +#define STV090x_WIDTH_SPKTDEL_LOCK_2_FIELD 1 +#define STV090x_OFFST_SPKTDEL_ERROR_1_FIELD 1 +#define STV090x_WIDTH_SPKTDEL_ERROR_1_FIELD 1 +#define STV090x_OFFST_SPKTDEL_LOCKB_1_FIELD 0 +#define STV090x_WIDTH_SPKTDEL_LOCKB_1_FIELD 1 + +#define STV090x_IRQSTATUS1 0xf122 +#define STV090x_OFFST_SPKTDEL_LOCK_1_FIELD 7 +#define STV090x_WIDTH_SPKTDEL_LOCK_1_FIELD 1 +#define STV090x_OFFST_SDEMOD_LOCKB_2_FIELD 2 +#define STV090x_WIDTH_SDEMOD_LOCKB_2_FIELD 1 +#define STV090x_OFFST_SDEMOD_LOCK_2_FIELD 1 +#define STV090x_WIDTH_SDEMOD_LOCK_2_FIELD 1 +#define STV090x_OFFST_SDEMOD_IRQ_2_FIELD 0 +#define STV090x_WIDTH_SDEMOD_IRQ_2_FIELD 1 + +#define STV090x_IRQSTATUS0 0xf123 +#define STV090x_OFFST_SDEMOD_LOCKB_1_FIELD 7 +#define STV090x_WIDTH_SDEMOD_LOCKB_1_FIELD 1 +#define STV090x_OFFST_SDEMOD_LOCK_1_FIELD 6 +#define STV090x_WIDTH_SDEMOD_LOCK_1_FIELD 1 +#define STV090x_OFFST_SDEMOD_IRQ_1_FIELD 5 +#define STV090x_WIDTH_SDEMOD_IRQ_1_FIELD 1 +#define STV090x_OFFST_SBCH_ERRFLAG_FIELD 4 +#define STV090x_WIDTH_SBCH_ERRFLAG_FIELD 1 +#define STV090x_OFFST_SDISEQC2RX_IRQ_FIELD 3 +#define STV090x_WIDTH_SDISEQC2RX_IRQ_FIELD 1 +#define STV090x_OFFST_SDISEQC2TX_IRQ_FIELD 2 +#define STV090x_WIDTH_SDISEQC2TX_IRQ_FIELD 1 +#define STV090x_OFFST_SDISEQC1RX_IRQ_FIELD 1 +#define STV090x_WIDTH_SDISEQC1RX_IRQ_FIELD 1 +#define STV090x_OFFST_SDISEQC1TX_IRQ_FIELD 0 +#define STV090x_WIDTH_SDISEQC1TX_IRQ_FIELD 1 + +#define STV090x_IRQMASK3 0xf124 +#define STV090x_OFFST_MPLL_LOCK_FIELD 5 +#define STV090x_WIDTH_MPLL_LOCK_FIELD 1 +#define STV090x_OFFST_MSTREAM_LCK_3_FIELD 4 +#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD 1 +#define STV090x_OFFST_MSTREAM_LCK_2_FIELD 3 +#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD 1 +#define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2 +#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD 1 +#define STV090x_OFFST_MDVBS1_PRF_2_FIELD 1 +#define STV090x_WIDTH_MDVBS1_PRF_2_FIELD 1 +#define STV090x_OFFST_MDVBS1_PRF_1_FIELD 0 +#define STV090x_WIDTH_MDVBS1_PRF_1_FIELD 1 + +#define STV090x_IRQMASK2 0xf125 +#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD 7 +#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD 1 +#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD 6 +#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD 1 +#define STV090x_OFFST_MSPY_ENDSIM_1_FIELD 5 +#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD 1 +#define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD 4 +#define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD 1 +#define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD 3 +#define STV090x_WIDTH_MPKTDEL_LOCKB_2_FIELD 1 +#define STV090x_OFFST_MPKTDEL_LOCK_2_FIELD 2 +#define STV090x_WIDTH_MPKTDEL_LOCK_2_FIELD 1 +#define STV090x_OFFST_MPKTDEL_ERROR_1_FIELD 1 +#define STV090x_WIDTH_MPKTDEL_ERROR_1_FIELD 1 +#define STV090x_OFFST_MPKTDEL_LOCKB_1_FIELD 0 +#define STV090x_WIDTH_MPKTDEL_LOCKB_1_FIELD 1 + +#define STV090x_IRQMASK1 0xf126 +#define STV090x_OFFST_MPKTDEL_LOCK_1_FIELD 7 +#define STV090x_WIDTH_MPKTDEL_LOCK_1_FIELD 1 +#define STV090x_OFFST_MEXTPINB2_FIELD 6 +#define STV090x_WIDTH_MEXTPINB2_FIELD 1 +#define STV090x_OFFST_MEXTPIN2_FIELD 5 +#define STV090x_WIDTH_MEXTPIN2_FIELD 1 +#define STV090x_OFFST_MEXTPINB1_FIELD 4 +#define STV090x_WIDTH_MEXTPINB1_FIELD 1 +#define STV090x_OFFST_MEXTPIN1_FIELD 3 +#define STV090x_WIDTH_MEXTPIN1_FIELD 1 +#define STV090x_OFFST_MDEMOD_LOCKB_2_FIELD 2 +#define STV090x_WIDTH_MDEMOD_LOCKB_2_FIELD 1 +#define STV090x_OFFST_MDEMOD_LOCK_2_FIELD 1 +#define STV090x_WIDTH_MDEMOD_LOCK_2_FIELD 1 +#define STV090x_OFFST_MDEMOD_IRQ_2_FIELD 0 +#define STV090x_WIDTH_MDEMOD_IRQ_2_FIELD 1 + +#define STV090x_IRQMASK0 0xf127 +#define STV090x_OFFST_MDEMOD_LOCKB_1_FIELD 7 +#define STV090x_WIDTH_MDEMOD_LOCKB_1_FIELD 1 +#define STV090x_OFFST_MDEMOD_LOCK_1_FIELD 6 +#define STV090x_WIDTH_MDEMOD_LOCK_1_FIELD 1 +#define STV090x_OFFST_MDEMOD_IRQ_1_FIELD 5 +#define STV090x_WIDTH_MDEMOD_IRQ_1_FIELD 1 +#define STV090x_OFFST_MBCH_ERRFLAG_FIELD 4 +#define STV090x_WIDTH_MBCH_ERRFLAG_FIELD 1 +#define STV090x_OFFST_MDISEQC2RX_IRQ_FIELD 3 +#define STV090x_WIDTH_MDISEQC2RX_IRQ_FIELD 1 +#define STV090x_OFFST_MDISEQC2TX_IRQ_FIELD 2 +#define STV090x_WIDTH_MDISEQC2TX_IRQ_FIELD 1 +#define STV090x_OFFST_MDISEQC1RX_IRQ_FIELD 1 +#define STV090x_WIDTH_MDISEQC1RX_IRQ_FIELD 1 +#define STV090x_OFFST_MDISEQC1TX_IRQ_FIELD 0 +#define STV090x_WIDTH_MDISEQC1TX_IRQ_FIELD 1 + +#define STV090x_I2CCFG 0xf129 +#define STV090x_OFFST_12C_FASTMODE_FIELD 3 +#define STV090x_WIDTH_12C_FASTMODE_FIELD 1 +#define STV090x_OFFST_12CADDR_INC_FIELD 0 +#define STV090x_WIDTH_12CADDR_INC_FIELD 2 + +#define STV090x_Px_I2CRPT(__x) (0xf12a + (__x - 1) * 0x1) +#define STV090x_P1_I2CRPT STV090x_Px_I2CRPT(1) +#define STV090x_P2_I2CRPT STV090x_Px_I2CRPT(2) +#define STV090x_OFFST_Px_I2CT_ON_FIELD 7 +#define STV090x_WIDTH_Px_I2CT_ON_FIELD 1 +#define STV090x_OFFST_Px_ENARPT_LEVEL_FIELD 4 +#define STV090x_WIDTH_Px_ENARPT_LEVEL_FIELD 3 +#define STV090x_OFFST_Px_SCLT_DELAY_FIELD 3 +#define STV090x_WIDTH_Px_SCLT_DELAY_FIELD 1 +#define STV090x_OFFST_Px_STOP_ENABLE_FIELD 2 +#define STV090x_WIDTH_Px_STOP_ENABLE_FIELD 1 +#define STV090x_OFFST_Px_STOP_SDAT2SDA_FIELD 1 +#define STV090x_WIDTH_Px_STOP_SDAT2SDA_FIELD 1 + +#define STV090x_CLKI2CFG 0xf140 +#define STV090x_OFFST_CLKI2_OPD_FIELD 7 +#define STV090x_WIDTH_CLKI2_OPD_FIELD 1 +#define STV090x_OFFST_CLKI2_CONFIG_FIELD 1 +#define STV090x_WIDTH_CLKI2_CONFIG_FIELD 6 +#define STV090x_OFFST_CLKI2_XOR_FIELD 0 +#define STV090x_WIDTH_CLKI2_XOR_FIELD 1 + +#define STV090x_GPIOxCFG(__x) (0xf141 + (__x - 1)) +#define STV090x_GPIO1CFG STV090x_GPIOxCFG(1) +#define STV090x_GPIO2CFG STV090x_GPIOxCFG(2) +#define STV090x_GPIO3CFG STV090x_GPIOxCFG(3) +#define STV090x_GPIO4CFG STV090x_GPIOxCFG(4) +#define STV090x_GPIO5CFG STV090x_GPIOxCFG(5) +#define STV090x_GPIO6CFG STV090x_GPIOxCFG(6) +#define STV090x_GPIO7CFG STV090x_GPIOxCFG(7) +#define STV090x_GPIO8CFG STV090x_GPIOxCFG(8) +#define STV090x_GPIO9CFG STV090x_GPIOxCFG(9) +#define STV090x_GPIO10CFG STV090x_GPIOxCFG(10) +#define STV090x_GPIO11CFG STV090x_GPIOxCFG(11) +#define STV090x_GPIO12CFG STV090x_GPIOxCFG(12) +#define STV090x_GPIO13CFG STV090x_GPIOxCFG(13) +#define STV090x_OFFST_GPIOx_OPD_FIELD 7 +#define STV090x_WIDTH_GPIOx_OPD_FIELD 1 +#define STV090x_OFFST_GPIOx_CONFIG_FIELD 1 +#define STV090x_WIDTH_GPIOx_CONFIG_FIELD 6 +#define STV090x_OFFST_GPIOx_XOR_FIELD 0 +#define STV090x_WIDTH_GPIOx_XOR_FIELD 1 + +#define STV090x_CSxCFG(__x) (0xf14e + __x * 0x1) +#define STV090x_CS0CFG STV090x_CSxCFG(0) +#define STV090x_CS1CFG STV090x_CSxCFG(1) +#define STV090x_OFFST_CSX_OPD_FIELD 7 +#define STV090x_WIDTH_CSX_OPD_FIELD 1 +#define STV090x_OFFST_CSX_CONFIG_FIELD 1 +#define STV090x_WIDTH_CSX_CONFIG_FIELD 6 +#define STV090x_OFFST_CSX_XOR_FIELD 0 +#define STV090x_WIDTH_CSX_XOR_FIELD 1 + + +#define STV090x_STDBYCFG 0xf150 +#define STV090x_OFFST_STDBY_OPD_FIELD 7 +#define STV090x_WIDTH_STDBY_OPD_FIELD 1 +#define STV090x_OFFST_STDBY_CONFIG_FIELD 1 +#define STV090x_WIDTH_STDBY_CONFIG_FIELD 6 +#define STV090x_OFFST_STDBY_XOR_FIELD 0 +#define STV090x_WIDTH_STDBY_XOR_FIELD 1 + +#define STV090x_DIRCLKCFG 0xf151 +#define STV090x_OFFST_DIRCLK_OPD_FIELD 7 +#define STV090x_WIDTH_DIRCLK_OPD_FIELD 1 +#define STV090x_OFFST_DIRCLK_CONFIG_FIELD 1 +#define STV090x_WIDTH_DIRCLK_CONFIG_FIELD 6 +#define STV090x_OFFST_DIRCLK_XOR_FIELD 0 +#define STV090x_WIDTH_DIRCLK_XOR_FIELD 1 + + +#define STV090x_AGCRFxCFG(__x) (0xf152 + (__x - 1) * 0x4) +#define STV090x_AGCRF1CFG STV090x_AGCRFxCFG(1) +#define STV090x_AGCRF2CFG STV090x_AGCRFxCFG(2) +#define STV090x_OFFST_AGCRFx_OPD_FIELD 7 +#define STV090x_WIDTH_AGCRFx_OPD_FIELD 1 +#define STV090x_OFFST_AGCRFx_CONFIG_FIELD 1 +#define STV090x_WIDTH_AGCRFx_CONFIG_FIELD 6 +#define STV090x_OFFST_AGCRFx_XOR_FIELD 0 +#define STV090x_WIDTH_AGCRFx_XOR_FIELD 1 + +#define STV090x_SDATxCFG(__x) (0xf153 + (__x - 1) * 0x4) +#define STV090x_SDAT1CFG STV090x_SDATxCFG(1) +#define STV090x_SDAT2CFG STV090x_SDATxCFG(2) +#define STV090x_OFFST_SDATx_OPD_FIELD 7 +#define STV090x_WIDTH_SDATx_OPD_FIELD 1 +#define STV090x_OFFST_SDATx_CONFIG_FIELD 1 +#define STV090x_WIDTH_SDATx_CONFIG_FIELD 6 +#define STV090x_OFFST_SDATx_XOR_FIELD 0 +#define STV090x_WIDTH_SDATx_XOR_FIELD 1 + +#define STV090x_SCLTxCFG(__x) (0xf154 + (__x - 1) * 0x4) +#define STV090x_SCLT1CFG STV090x_SCLTxCFG(1) +#define STV090x_SCLT2CFG STV090x_SCLTxCFG(2) +#define STV090x_OFFST_SCLTx_OPD_FIELD 7 +#define STV090x_WIDTH_SCLTx_OPD_FIELD 1 +#define STV090x_OFFST_SCLTx_CONFIG_FIELD 1 +#define STV090x_WIDTH_SCLTx_CONFIG_FIELD 6 +#define STV090x_OFFST_SCLTx_XOR_FIELD 0 +#define STV090x_WIDTH_SCLTx_XOR_FIELD 1 + +#define STV090x_DISEQCOxCFG(__x) (0xf155 + (__x - 1) * 0x4) +#define STV090x_DISEQCO1CFG STV090x_DISEQCOxCFG(1) +#define STV090x_DISEQCO2CFG STV090x_DISEQCOxCFG(2) +#define STV090x_OFFST_DISEQCOx_OPD_FIELD 7 +#define STV090x_WIDTH_DISEQCOx_OPD_FIELD 1 +#define STV090x_OFFST_DISEQCOx_CONFIG_FIELD 1 +#define STV090x_WIDTH_DISEQCOx_CONFIG_FIELD 6 +#define STV090x_OFFST_DISEQCOx_XOR_FIELD 0 +#define STV090x_WIDTH_DISEQCOx_XOR_FIELD 1 + +#define STV090x_CLKOUT27CFG 0xf15a +#define STV090x_OFFST_CLKOUT27_OPD_FIELD 7 +#define STV090x_WIDTH_CLKOUT27_OPD_FIELD 1 +#define STV090x_OFFST_CLKOUT27_CONFIG_FIELD 1 +#define STV090x_WIDTH_CLKOUT27_CONFIG_FIELD 6 +#define STV090x_OFFST_CLKOUT27_XOR_FIELD 0 +#define STV090x_WIDTH_CLKOUT27_XOR_FIELD 1 + +#define STV090x_ERRORxCFG(__x) (0xf15b + (__x - 1) * 0x5) +#define STV090x_ERROR1CFG STV090x_ERRORxCFG(1) +#define STV090x_ERROR2CFG STV090x_ERRORxCFG(2) +#define STV090x_ERROR3CFG STV090x_ERRORxCFG(3) +#define STV090x_OFFST_ERRORx_OPD_FIELD 7 +#define STV090x_WIDTH_ERRORx_OPD_FIELD 1 +#define STV090x_OFFST_ERRORx_CONFIG_FIELD 1 +#define STV090x_WIDTH_ERRORx_CONFIG_FIELD 6 +#define STV090x_OFFST_ERRORx_XOR_FIELD 0 +#define STV090x_WIDTH_ERRORx_XOR_FIELD 1 + +#define STV090x_DPNxCFG(__x) (0xf15c + (__x - 1) * 0x5) +#define STV090x_DPN1CFG STV090x_DPNxCFG(1) +#define STV090x_DPN2CFG STV090x_DPNxCFG(2) +#define STV090x_DPN3CFG STV090x_DPNxCFG(3) +#define STV090x_OFFST_DPNx_OPD_FIELD 7 +#define STV090x_WIDTH_DPNx_OPD_FIELD 1 +#define STV090x_OFFST_DPNx_CONFIG_FIELD 1 +#define STV090x_WIDTH_DPNx_CONFIG_FIELD 6 +#define STV090x_OFFST_DPNx_XOR_FIELD 0 +#define STV090x_WIDTH_DPNx_XOR_FIELD 1 + +#define STV090x_STROUTxCFG(__x) (0xf15d + (__x - 1) * 0x5) +#define STV090x_STROUT1CFG STV090x_STROUTxCFG(1) +#define STV090x_STROUT2CFG STV090x_STROUTxCFG(2) +#define STV090x_STROUT3CFG STV090x_STROUTxCFG(3) +#define STV090x_OFFST_STROUTx_OPD_FIELD 7 +#define STV090x_WIDTH_STROUTx_OPD_FIELD 1 +#define STV090x_OFFST_STROUTx_CONFIG_FIELD 1 +#define STV090x_WIDTH_STROUTx_CONFIG_FIELD 6 +#define STV090x_OFFST_STROUTx_XOR_FIELD 0 +#define STV090x_WIDTH_STROUTx_XOR_FIELD 1 + +#define STV090x_CLKOUTxCFG(__x) (0xf15e + (__x - 1) * 0x5) +#define STV090x_CLKOUT1CFG STV090x_CLKOUTxCFG(1) +#define STV090x_CLKOUT2CFG STV090x_CLKOUTxCFG(2) +#define STV090x_CLKOUT3CFG STV090x_CLKOUTxCFG(3) +#define STV090x_OFFST_CLKOUTx_OPD_FIELD 7 +#define STV090x_WIDTH_CLKOUTx_OPD_FIELD 1 +#define STV090x_OFFST_CLKOUTx_CONFIG_FIELD 1 +#define STV090x_WIDTH_CLKOUTx_CONFIG_FIELD 6 +#define STV090x_OFFST_CLKOUTx_XOR_FIELD 0 +#define STV090x_WIDTH_CLKOUTx_XOR_FIELD 1 + +#define STV090x_DATAxCFG(__x) (0xf15f + (__x - 71) * 0x5) +#define STV090x_DATA71CFG STV090x_DATAxCFG(71) +#define STV090x_DATA72CFG STV090x_DATAxCFG(72) +#define STV090x_DATA73CFG STV090x_DATAxCFG(73) +#define STV090x_OFFST_DATAx_OPD_FIELD 7 +#define STV090x_WIDTH_DATAx_OPD_FIELD 1 +#define STV090x_OFFST_DATAx_CONFIG_FIELD 1 +#define STV090x_WIDTH_DATAx_CONFIG_FIELD 6 +#define STV090x_OFFST_DATAx_XOR_FIELD 0 +#define STV090x_WIDTH_DATAx_XOR_FIELD 1 + +#define STV090x_NCOARSE 0xf1b3 +#define STV090x_OFFST_M_DIV_FIELD 0 +#define STV090x_WIDTH_M_DIV_FIELD 8 + +#define STV090x_SYNTCTRL 0xf1b6 +#define STV090x_OFFST_STANDBY_FIELD 7 +#define STV090x_WIDTH_STANDBY_FIELD 1 +#define STV090x_OFFST_BYPASSPLLCORE_FIELD 6 +#define STV090x_WIDTH_BYPASSPLLCORE_FIELD 1 +#define STV090x_OFFST_SELX1RATIO_FIELD 5 +#define STV090x_WIDTH_SELX1RATIO_FIELD 1 +#define STV090x_OFFST_STOP_PLL_FIELD 3 +#define STV090x_WIDTH_STOP_PLL_FIELD 1 +#define STV090x_OFFST_BYPASSPLLFSK_FIELD 2 +#define STV090x_WIDTH_BYPASSPLLFSK_FIELD 1 +#define STV090x_OFFST_SELOSCI_FIELD 1 +#define STV090x_WIDTH_SELOSCI_FIELD 1 +#define STV090x_OFFST_BYPASSPLLADC_FIELD 0 +#define STV090x_WIDTH_BYPASSPLLADC_FIELD 1 + +#define STV090x_FILTCTRL 0xf1b7 +#define STV090x_OFFST_INV_CLK135_FIELD 7 +#define STV090x_WIDTH_INV_CLK135_FIELD 1 +#define STV090x_OFFST_SEL_FSKCKDIV_FIELD 2 +#define STV090x_WIDTH_SEL_FSKCKDIV_FIELD 1 +#define STV090x_OFFST_INV_CLKFSK_FIELD 1 +#define STV090x_WIDTH_INV_CLKFSK_FIELD 1 +#define STV090x_OFFST_BYPASS_APPLI_FIELD 0 +#define STV090x_WIDTH_BYPASS_APPLI_FIELD 1 + +#define STV090x_PLLSTAT 0xf1b8 +#define STV090x_OFFST_PLLLOCK_FIELD 0 +#define STV090x_WIDTH_PLLLOCK_FIELD 1 + +#define STV090x_STOPCLK1 0xf1c2 +#define STV090x_OFFST_STOP_CLKPKDT2_FIELD 6 +#define STV090x_WIDTH_STOP_CLKPKDT2_FIELD 1 +#define STV090x_OFFST_STOP_CLKPKDT1_FIELD 5 +#define STV090x_WIDTH_STOP_CLKPKDT1_FIELD 1 +#define STV090x_OFFST_STOP_CLKFEC_FIELD 4 +#define STV090x_WIDTH_STOP_CLKFEC_FIELD 1 +#define STV090x_OFFST_STOP_CLKADCI2_FIELD 3 +#define STV090x_WIDTH_STOP_CLKADCI2_FIELD 1 +#define STV090x_OFFST_INV_CLKADCI2_FIELD 2 +#define STV090x_WIDTH_INV_CLKADCI2_FIELD 1 +#define STV090x_OFFST_STOP_CLKADCI1_FIELD 1 +#define STV090x_WIDTH_STOP_CLKADCI1_FIELD 1 +#define STV090x_OFFST_INV_CLKADCI1_FIELD 0 +#define STV090x_WIDTH_INV_CLKADCI1_FIELD 1 + +#define STV090x_STOPCLK2 0xf1c3 +#define STV090x_OFFST_STOP_CLKSAMP2_FIELD 4 +#define STV090x_WIDTH_STOP_CLKSAMP2_FIELD 1 +#define STV090x_OFFST_STOP_CLKSAMP1_FIELD 3 +#define STV090x_WIDTH_STOP_CLKSAMP1_FIELD 1 +#define STV090x_OFFST_STOP_CLKVIT2_FIELD 2 +#define STV090x_WIDTH_STOP_CLKVIT2_FIELD 1 +#define STV090x_OFFST_STOP_CLKVIT1_FIELD 1 +#define STV090x_WIDTH_STOP_CLKVIT1_FIELD 1 +#define STV090x_OFFST_STOP_CLKTS_FIELD 0 +#define STV090x_WIDTH_STOP_CLKTS_FIELD 1 + +#define STV090x_TSTTNR0 0xf1df +#define STV090x_OFFST_SEL_FSK_FIELD 7 +#define STV090x_WIDTH_SEL_FSK_FIELD 1 +#define STV090x_OFFST_FSK_PON_FIELD 2 +#define STV090x_WIDTH_FSK_PON_FIELD 1 + +#define STV090x_TSTTNR1 0xf1e0 +#define STV090x_OFFST_ADC1_PON_FIELD 1 +#define STV090x_WIDTH_ADC1_PON_FIELD 1 +#define STV090x_OFFST_ADC1_INMODE_FIELD 0 +#define STV090x_WIDTH_ADC1_INMODE_FIELD 1 + +#define STV090x_TSTTNR2 0xf1e1 +#define STV090x_OFFST_DISEQC1_PON_FIELD 5 +#define STV090x_WIDTH_DISEQC1_PON_FIELD 1 + +#define STV090x_TSTTNR3 0xf1e2 +#define STV090x_OFFST_ADC2_PON_FIELD 1 +#define STV090x_WIDTH_ADC2_PON_FIELD 1 +#define STV090x_OFFST_ADC2_INMODE_FIELD 0 +#define STV090x_WIDTH_ADC2_INMODE_FIELD 1 + +#define STV090x_TSTTNR4 0xf1e3 +#define STV090x_OFFST_DISEQC2_PON_FIELD 5 +#define STV090x_WIDTH_DISEQC2_PON_FIELD 1 + +#define STV090x_FSKTFC2 0xf170 +#define STV090x_OFFST_FSKT_KMOD_FIELD 2 +#define STV090x_WIDTH_FSKT_KMOD_FIELD 6 +#define STV090x_OFFST_FSKT_CAR_FIELD 0 +#define STV090x_WIDTH_FSKT_CAR_FIELD 2 + +#define STV090x_FSKTFC1 0xf171 +#define STV090x_OFFST_FSKTC1_CAR_FIELD 0 +#define STV090x_WIDTH_FSKTC1_CAR_FIELD 8 + +#define STV090x_FSKTFC0 0xf172 +#define STV090x_OFFST_FSKTC0_CAR_FIELD 0 +#define STV090x_WIDTH_FSKTC0_CAR_FIELD 8 + +#define STV090x_FSKTDELTAF1 0xf173 +#define STV090x_OFFST_FSKTF1_DELTAF_FIELD 0 +#define STV090x_WIDTH_FSKTF1_DELTAF_FIELD 4 + +#define STV090x_FSKTDELTAF0 0xf174 +#define STV090x_OFFST_FSKTF0_DELTAF_FIELD 0 +#define STV090x_WIDTH_FSKTF0_DELTAF_FIELD 8 + +#define STV090x_FSKTCTRL 0xf175 +#define STV090x_OFFST_FSKT_EN_SGN_FIELD 6 +#define STV090x_WIDTH_FSKT_EN_SGN_FIELD 1 +#define STV090x_OFFST_FSKT_MOD_SGN_FIELD 5 +#define STV090x_WIDTH_FSKT_MOD_SGN_FIELD 1 +#define STV090x_OFFST_FSKT_MOD_EN_FIELD 2 +#define STV090x_WIDTH_FSKT_MOD_EN_FIELD 3 +#define STV090x_OFFST_FSKT_DACMODE_FIELD 0 +#define STV090x_WIDTH_FSKT_DACMODE_FIELD 2 + +#define STV090x_FSKRFC2 0xf176 +#define STV090x_OFFST_FSKRC2_DETSGN_FIELD 6 +#define STV090x_WIDTH_FSKRC2_DETSGN_FIELD 1 +#define STV090x_OFFST_FSKRC2_OUTSGN_FIELD 5 +#define STV090x_WIDTH_FSKRC2_OUTSGN_FIELD 1 +#define STV090x_OFFST_FSKRC2_KAGC_FIELD 2 +#define STV090x_WIDTH_FSKRC2_KAGC_FIELD 3 +#define STV090x_OFFST_FSKRC2_CAR_FIELD 0 +#define STV090x_WIDTH_FSKRC2_CAR_FIELD 2 + +#define STV090x_FSKRFC1 0xf177 +#define STV090x_OFFST_FSKRC1_CAR_FIELD 0 +#define STV090x_WIDTH_FSKRC1_CAR_FIELD 8 + +#define STV090x_FSKRFC0 0xf178 +#define STV090x_OFFST_FSKRC0_CAR_FIELD 0 +#define STV090x_WIDTH_FSKRC0_CAR_FIELD 8 + +#define STV090x_FSKRK1 0xf179 +#define STV090x_OFFST_FSKR_K1_EXP_FIELD 5 +#define STV090x_WIDTH_FSKR_K1_EXP_FIELD 3 +#define STV090x_OFFST_FSKR_K1_MANT_FIELD 0 +#define STV090x_WIDTH_FSKR_K1_MANT_FIELD 5 + +#define STV090x_FSKRK2 0xf17a +#define STV090x_OFFST_FSKR_K2_EXP_FIELD 5 +#define STV090x_WIDTH_FSKR_K2_EXP_FIELD 3 +#define STV090x_OFFST_FSKR_K2_MANT_FIELD 0 +#define STV090x_WIDTH_FSKR_K2_MANT_FIELD 5 + +#define STV090x_FSKRAGCR 0xf17b +#define STV090x_OFFST_FSKR_OUTCTL_FIELD 6 +#define STV090x_WIDTH_FSKR_OUTCTL_FIELD 2 +#define STV090x_OFFST_FSKR_AGC_REF_FIELD 0 +#define STV090x_WIDTH_FSKR_AGC_REF_FIELD 6 + +#define STV090x_FSKRAGC 0xf17c +#define STV090x_OFFST_FSKR_AGC_ACCU_FIELD 0 +#define STV090x_WIDTH_FSKR_AGC_ACCU_FIELD 8 + +#define STV090x_FSKRALPHA 0xf17d +#define STV090x_OFFST_FSKR_ALPHA_EXP_FIELD 2 +#define STV090x_WIDTH_FSKR_ALPHA_EXP_FIELD 3 +#define STV090x_OFFST_FSKR_ALPHA_M_FIELD 0 +#define STV090x_WIDTH_FSKR_ALPHA_M_FIELD 2 + +#define STV090x_FSKRPLTH1 0xf17e +#define STV090x_OFFST_FSKR_BETA_FIELD 4 +#define STV090x_WIDTH_FSKR_BETA_FIELD 4 +#define STV090x_OFFST_FSKR_PLL_TRESH1_FIELD 0 +#define STV090x_WIDTH_FSKR_PLL_TRESH1_FIELD 4 + +#define STV090x_FSKRPLTH0 0xf17f +#define STV090x_OFFST_FSKR_PLL_TRESH0_FIELD 0 +#define STV090x_WIDTH_FSKR_PLL_TRESH0_FIELD 8 + +#define STV090x_FSKRDF1 0xf180 +#define STV090x_OFFST_FSKR_DELTAF1_FIELD 0 +#define STV090x_WIDTH_FSKR_DELTAF1_FIELD 5 + +#define STV090x_FSKRDF0 0xf181 +#define STV090x_OFFST_FSKR_DELTAF0_FIELD 0 +#define STV090x_WIDTH_FSKR_DELTAF0_FIELD 8 + +#define STV090x_FSKRSTEPP 0xf182 +#define STV090x_OFFST_FSKR_STEP_PLUS_FIELD 0 +#define STV090x_WIDTH_FSKR_STEP_PLUS_FIELD 8 + +#define STV090x_FSKRSTEPM 0xf183 +#define STV090x_OFFST_FSKR_STEP_MINUS_FIELD 0 +#define STV090x_WIDTH_FSKR_STEP_MINUS_FIELD 8 + +#define STV090x_FSKRDET1 0xf184 +#define STV090x_OFFST_FSKR_CARDET1_ACCU_FIELD 0 +#define STV090x_WIDTH_FSKR_CARDET1_ACCU_FIELD 4 + +#define STV090x_FSKRDET0 0xf185 +#define STV090x_OFFST_FSKR_CARDET0_ACCU_FIELD 0 +#define STV090x_WIDTH_FSKR_CARDET0_ACCU_FIELD 8 + +#define STV090x_FSKRDTH1 0xf186 +#define STV090x_OFFST_FSKR_CARLOSS_THRESH1_FIELD 4 +#define STV090x_WIDTH_FSKR_CARLOSS_THRESH1_FIELD 4 +#define STV090x_OFFST_FSKR_CARDET_THRESH1_FIELD 0 +#define STV090x_WIDTH_FSKR_CARDET_THRESH1_FIELD 4 + +#define STV090x_FSKRDTH0 0xf187 +#define STV090x_OFFST_FSKR_CARDET_THRESH0_FIELD 0 +#define STV090x_WIDTH_FSKR_CARDET_THRESH0_FIELD 8 + +#define STV090x_FSKRLOSS 0xf188 +#define STV090x_OFFST_FSKR_CARLOSS_THRESH_FIELD 0 +#define STV090x_WIDTH_FSKR_CARLOSS_THRESH_FIELD 8 + +#define STV090x_Px_DISTXCTL(__x) (0xF1A0 - (__x - 1) * 0x10) +#define STV090x_P1_DISTXCTL STV090x_Px_DISTXCTL(1) +#define STV090x_P2_DISTXCTL STV090x_Px_DISTXCTL(2) +#define STV090x_OFFST_Px_TIM_OFF_FIELD 7 +#define STV090x_WIDTH_Px_TIM_OFF_FIELD 1 +#define STV090x_OFFST_Px_DISEQC_RESET_FIELD 6 +#define STV090x_WIDTH_Px_DISEQC_RESET_FIELD 1 +#define STV090x_OFFST_Px_TIM_CMD_FIELD 4 +#define STV090x_WIDTH_Px_TIM_CMD_FIELD 2 +#define STV090x_OFFST_Px_DIS_PRECHARGE_FIELD 3 +#define STV090x_WIDTH_Px_DIS_PRECHARGE_FIELD 1 +#define STV090x_OFFST_Px_DISTX_MODE_FIELD 0 +#define STV090x_WIDTH_Px_DISTX_MODE_FIELD 3 + +#define STV090x_Px_DISRXCTL(__x) (0xf1a1 - (__x - 1) * 0x10) +#define STV090x_P1_DISRXCTL STV090x_Px_DISRXCTL(1) +#define STV090x_P2_DISRXCTL STV090x_Px_DISRXCTL(2) +#define STV090x_OFFST_Px_RECEIVER_ON_FIELD 7 +#define STV090x_WIDTH_Px_RECEIVER_ON_FIELD 1 +#define STV090x_OFFST_Px_IGNO_SHORT22K_FIELD 6 +#define STV090x_WIDTH_Px_IGNO_SHORT22K_FIELD 1 +#define STV090x_OFFST_Px_ONECHIP_TRX_FIELD 5 +#define STV090x_WIDTH_Px_ONECHIP_TRX_FIELD 1 +#define STV090x_OFFST_Px_EXT_ENVELOP_FIELD 4 +#define STV090x_WIDTH_Px_EXT_ENVELOP_FIELD 1 +#define STV090x_OFFST_Px_PIN_SELECT_FIELD 2 +#define STV090x_WIDTH_Px_PIN_SELECT_FIELD 2 +#define STV090x_OFFST_Px_IRQ_RXEND_FIELD 1 +#define STV090x_WIDTH_Px_IRQ_RXEND_FIELD 1 +#define STV090x_OFFST_Px_IRQ_4NBYTES_FIELD 0 +#define STV090x_WIDTH_Px_IRQ_4NBYTES_FIELD 1 + +#define STV090x_Px_DISRX_ST0(__x) (0xf1a4 - (__x - 1) * 0x10) +#define STV090x_P1_DISRX_ST0 STV090x_Px_DISRX_ST0(1) +#define STV090x_P2_DISRX_ST0 STV090x_Px_DISRX_ST0(2) +#define STV090x_OFFST_Px_RX_END_FIELD 7 +#define STV090x_WIDTH_Px_RX_END_FIELD 1 +#define STV090x_OFFST_Px_RX_ACTIVE_FIELD 6 +#define STV090x_WIDTH_Px_RX_ACTIVE_FIELD 1 +#define STV090x_OFFST_Px_SHORT_22KHZ_FIELD 5 +#define STV090x_WIDTH_Px_SHORT_22KHZ_FIELD 1 +#define STV090x_OFFST_Px_CONT_TONE_FIELD 4 +#define STV090x_WIDTH_Px_CONT_TONE_FIELD 1 +#define STV090x_OFFST_Px_FIFO_4BREADY_FIELD 3 +#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD 1 +#define STV090x_OFFST_Px_FIFO_EMPTY_FIELD 2 +#define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD 1 +#define STV090x_OFFST_Px_ABORT_DISRX_FIELD 0 +#define STV090x_WIDTH_Px_ABORT_DISRX_FIELD 1 + +#define STV090x_Px_DISRX_ST1(__x) (0xf1a5 - (__x - 1) * 0x10) +#define STV090x_P1_DISRX_ST1 STV090x_Px_DISRX_ST1(1) +#define STV090x_P2_DISRX_ST1 STV090x_Px_DISRX_ST1(2) +#define STV090x_OFFST_Px_RX_FAIL_FIELD 7 +#define STV090x_WIDTH_Px_RX_FAIL_FIELD 1 +#define STV090x_OFFST_Px_FIFO_PARITYFAIL_FIELD 6 +#define STV090x_WIDTH_Px_FIFO_PARITYFAIL_FIELD 1 +#define STV090x_OFFST_Px_RX_NONBYTE_FIELD 5 +#define STV090x_WIDTH_Px_RX_NONBYTE_FIELD 1 +#define STV090x_OFFST_Px_FIFO_OVERFLOW_FIELD 4 +#define STV090x_WIDTH_Px_FIFO_OVERFLOW_FIELD 1 +#define STV090x_OFFST_Px_FIFO_BYTENBR_FIELD 0 +#define STV090x_WIDTH_Px_FIFO_BYTENBR_FIELD 4 + +#define STV090x_Px_DISRXDATA(__x) (0xf1a6 - (__x - 1) * 0x10) +#define STV090x_P1_DISRXDATA STV090x_Px_DISRXDATA(1) +#define STV090x_P2_DISRXDATA STV090x_Px_DISRXDATA(2) +#define STV090x_OFFST_Px_DISRX_DATA_FIELD 0 +#define STV090x_WIDTH_Px_DISRX_DATA_FIELD 8 + +#define STV090x_Px_DISTXDATA(__x) (0xf1a7 - (__x - 1) * 0x10) +#define STV090x_P1_DISTXDATA STV090x_Px_DISTXDATA(1) +#define STV090x_P2_DISTXDATA STV090x_Px_DISTXDATA(2) +#define STV090x_OFFST_Px_DISEQC_FIFO_FIELD 0 +#define STV090x_WIDTH_Px_DISEQC_FIFO_FIELD 8 + +#define STV090x_Px_DISTXSTATUS(__x) (0xf1a8 - (__x - 1) * 0x10) +#define STV090x_P1_DISTXSTATUS STV090x_Px_DISTXSTATUS(1) +#define STV090x_P2_DISTXSTATUS STV090x_Px_DISTXSTATUS(2) +#define STV090x_OFFST_Px_TX_FAIL_FIELD 7 +#define STV090x_WIDTH_Px_TX_FAIL_FIELD 1 +#define STV090x_OFFST_Px_FIFO_FULL_FIELD 6 +#define STV090x_WIDTH_Px_FIFO_FULL_FIELD 1 +#define STV090x_OFFST_Px_TX_IDLE_FIELD 5 +#define STV090x_WIDTH_Px_TX_IDLE_FIELD 1 +#define STV090x_OFFST_Px_GAP_BURST_FIELD 4 +#define STV090x_WIDTH_Px_GAP_BURST_FIELD 1 +#define STV090x_OFFST_Px_TXFIFO_BYTES_FIELD 0 +#define STV090x_WIDTH_Px_TXFIFO_BYTES_FIELD 4 + +#define STV090x_Px_F22TX(__x) (0xf1a9 - (__x - 1) * 0x10) +#define STV090x_P1_F22TX STV090x_Px_F22TX(1) +#define STV090x_P2_F22TX STV090x_Px_F22TX(2) +#define STV090x_OFFST_Px_F22_REG_FIELD 0 +#define STV090x_WIDTH_Px_F22_REG_FIELD 8 + +#define STV090x_Px_F22RX(__x) (0xf1aa - (__x - 1) * 0x10) +#define STV090x_P1_F22RX STV090x_Px_F22RX(1) +#define STV090x_P2_F22RX STV090x_Px_F22RX(2) +#define STV090x_OFFST_Px_F22RX_REG_FIELD 0 +#define STV090x_WIDTH_Px_F22RX_REG_FIELD 8 + +#define STV090x_Px_ACRPRESC(__x) (0xf1ac - (__x - 1) * 0x10) +#define STV090x_P1_ACRPRESC STV090x_Px_ACRPRESC(1) +#define STV090x_P2_ACRPRESC STV090x_Px_ACRPRESC(2) +#define STV090x_OFFST_Px_ACR_PRESC_FIELD 0 +#define STV090x_WIDTH_Px_ACR_PRESC_FIELD 3 + +#define STV090x_Px_ACRDIV(__x) (0xf1ad - (__x - 1) * 0x10) +#define STV090x_P1_ACRDIV STV090x_Px_ACRDIV(1) +#define STV090x_P2_ACRDIV STV090x_Px_ACRDIV(2) +#define STV090x_OFFST_Px_ACR_DIV_FIELD 0 +#define STV090x_WIDTH_Px_ACR_DIV_FIELD 8 + +#define STV090x_Px_IQCONST(__x) (0xF400 - (__x - 1) * 0x200) +#define STV090x_P1_IQCONST STV090x_Px_IQCONST(1) +#define STV090x_P2_IQCONST STV090x_Px_IQCONST(2) +#define STV090x_OFFST_Px_CONSTEL_SELECT_FIELD 5 +#define STV090x_WIDTH_Px_CONSTEL_SELECT_FIELD 2 + +#define STV090x_Px_NOSCFG(__x) (0xF401 - (__x - 1) * 0x200) +#define STV090x_P1_NOSCFG STV090x_Px_NOSCFG(1) +#define STV090x_P2_NOSCFG STV090x_Px_NOSCFG(2) +#define STV090x_OFFST_Px_NOSPLH_BETA_FIELD 3 +#define STV090x_WIDTH_Px_NOSPLH_BETA_FIELD 2 +#define STV090x_OFFST_Px_NOSDATA_BETA_FIELD 0 +#define STV090x_WIDTH_Px_NOSDATA_BETA_FIELD 3 + +#define STV090x_Px_ISYMB(__x) (0xF402 - (__x - 1) * 0x200) +#define STV090x_P1_ISYMB STV090x_Px_ISYMB(1) +#define STV090x_P2_ISYMB STV090x_Px_ISYMB(2) +#define STV090x_OFFST_Px_I_SYMBOL_FIELD 0 +#define STV090x_WIDTH_Px_I_SYMBOL_FIELD 8 + +#define STV090x_Px_QSYMB(__x) (0xF403 - (__x - 1) * 0x200) +#define STV090x_P1_QSYMB STV090x_Px_QSYMB(1) +#define STV090x_P2_QSYMB STV090x_Px_QSYMB(2) +#define STV090x_OFFST_Px_Q_SYMBOL_FIELD 0 +#define STV090x_WIDTH_Px_Q_SYMBOL_FIELD 8 + +#define STV090x_Px_AGC1CFG(__x) (0xF404 - (__x - 1) * 0x200) +#define STV090x_P1_AGC1CFG STV090x_Px_AGC1CFG(1) +#define STV090x_P2_AGC1CFG STV090x_Px_AGC1CFG(2) +#define STV090x_OFFST_Px_DC_FROZEN_FIELD 7 +#define STV090x_WIDTH_Px_DC_FROZEN_FIELD 1 +#define STV090x_OFFST_Px_DC_CORRECT_FIELD 6 +#define STV090x_WIDTH_Px_DC_CORRECT_FIELD 1 +#define STV090x_OFFST_Px_AMM_FROZEN_FIELD 5 +#define STV090x_WIDTH_Px_AMM_FROZEN_FIELD 1 +#define STV090x_OFFST_Px_AMM_CORRECT_FIELD 4 +#define STV090x_WIDTH_Px_AMM_CORRECT_FIELD 1 +#define STV090x_OFFST_Px_QUAD_FROZEN_FIELD 3 +#define STV090x_WIDTH_Px_QUAD_FROZEN_FIELD 1 +#define STV090x_OFFST_Px_QUAD_CORRECT_FIELD 2 +#define STV090x_WIDTH_Px_QUAD_CORRECT_FIELD 1 + +#define STV090x_Px_AGC1CN(__x) (0xF406 - (__x - 1) * 0x200) +#define STV090x_P1_AGC1CN STV090x_Px_AGC1CN(1) +#define STV090x_P2_AGC1CN STV090x_Px_AGC1CN(2) +#define STV090x_WIDTH_Px_AGC1_LOCKED_FIELD 7 +#define STV090x_OFFST_Px_AGC1_LOCKED_FIELD 1 +#define STV090x_OFFST_Px_AGC1_MINPOWER_FIELD 4 +#define STV090x_WIDTH_Px_AGC1_MINPOWER_FIELD 1 +#define STV090x_OFFST_Px_AGCOUT_FAST_FIELD 3 +#define STV090x_WIDTH_Px_AGCOUT_FAST_FIELD 1 +#define STV090x_OFFST_Px_AGCIQ_BETA_FIELD 0 +#define STV090x_WIDTH_Px_AGCIQ_BETA_FIELD 3 + +#define STV090x_Px_AGC1REF(__x) (0xF407 - (__x - 1) * 0x200) +#define STV090x_P1_AGC1REF STV090x_Px_AGC1REF(1) +#define STV090x_P2_AGC1REF STV090x_Px_AGC1REF(2) +#define STV090x_OFFST_Px_AGCIQ_REF_FIELD 0 +#define STV090x_WIDTH_Px_AGCIQ_REF_FIELD 8 + +#define STV090x_Px_IDCCOMP(__x) (0xF408 - (__x - 1) * 0x200) +#define STV090x_P1_IDCCOMP STV090x_Px_IDCCOMP(1) +#define STV090x_P2_IDCCOMP STV090x_Px_IDCCOMP(2) +#define STV090x_OFFST_Px_IAVERAGE_ADJ_FIELD 0 +#define STV090x_WIDTH_Px_IAVERAGE_ADJ_FIELD 8 + +#define STV090x_Px_QDCCOMP(__x) (0xF409 - (__x - 1) * 0x200) +#define STV090x_P1_QDCCOMP STV090x_Px_QDCCOMP(1) +#define STV090x_P2_QDCCOMP STV090x_Px_QDCCOMP(2) +#define STV090x_OFFST_Px_QAVERAGE_ADJ_FIELD 0 +#define STV090x_WIDTH_Px_QAVERAGE_ADJ_FIELD 8 + +#define STV090x_Px_POWERI(__x) (0xF40A - (__x - 1) * 0x200) +#define STV090x_P1_POWERI STV090x_Px_POWERI(1) +#define STV090x_P2_POWERI STV090x_Px_POWERI(2) +#define STV090x_OFFST_Px_POWER_I_FIELD 0 +#define STV090x_WIDTH_Px_POWER_I_FIELD 8 + +#define STV090x_Px_POWERQ(__x) (0xF40B - (__x - 1) * 0x200) +#define STV090x_P1_POWERQ STV090x_Px_POWERQ(1) +#define STV090x_P2_POWERQ STV090x_Px_POWERQ(2) +#define STV090x_OFFST_Px_POWER_Q_FIELD 0 +#define STV090x_WIDTH_Px_POWER_Q_FIELD 8 + +#define STV090x_Px_AGC1AMM(__x) (0xF40C - (__x - 1) * 0x200) +#define STV090x_P1_AGC1AMM STV090x_Px_AGC1AMM(1) +#define STV090x_P2_AGC1AMM STV090x_Px_AGC1AMM(2) +#define STV090x_OFFST_Px_AMM_VALUE_FIELD 0 +#define STV090x_WIDTH_Px_AMM_VALUE_FIELD 8 + +#define STV090x_Px_AGC1QUAD(__x) (0xF40D - (__x - 1) * 0x200) +#define STV090x_P1_AGC1QUAD STV090x_Px_AGC1QUAD(1) +#define STV090x_P2_AGC1QUAD STV090x_Px_AGC1QUAD(2) +#define STV090x_OFFST_Px_QUAD_VALUE_FIELD 0 +#define STV090x_WIDTH_Px_QUAD_VALUE_FIELD 8 + +#define STV090x_Px_AGCIQINy(__x, __y) (0xF40F - (__x-1) * 0x200 - __y * 0x1) +#define STV090x_P1_AGCIQIN0 STV090x_Px_AGCIQINy(1, 0) +#define STV090x_P1_AGCIQIN1 STV090x_Px_AGCIQINy(1, 1) +#define STV090x_P2_AGCIQIN0 STV090x_Px_AGCIQINy(2, 0) +#define STV090x_P2_AGCIQIN1 STV090x_Px_AGCIQINy(2, 1) +#define STV090x_OFFST_Px_AGCIQ_VALUE_FIELD 0 +#define STV090x_WIDTH_Px_AGCIQ_VALUE_FIELD 8 + +#define STV090x_Px_DEMOD(__x) (0xF410 - (__x - 1) * 0x200) +#define STV090x_P1_DEMOD STV090x_Px_DEMOD(1) +#define STV090x_P2_DEMOD STV090x_Px_DEMOD(2) +#define STV090x_OFFST_Px_MANUAL_S2ROLLOFF_FIELD 7 +#define STV090x_WIDTH_Px_MANUAL_S2ROLLOFF_FIELD 1 +#define STV090x_OFFST_Px_DEMOD_STOP_FIELD 6 +#define STV090x_WIDTH_Px_DEMOD_STOP_FIELD 1 +#define STV090x_OFFST_Px_SPECINV_CONTROL_FIELD 4 +#define STV090x_WIDTH_Px_SPECINV_CONTROL_FIELD 2 +#define STV090x_OFFST_Px_FORCE_ENASAMP_FIELD 3 +#define STV090x_WIDTH_Px_FORCE_ENASAMP_FIELD 1 +#define STV090x_OFFST_Px_MANUAL_SXROLLOFF_FIELD 2 +#define STV090x_WIDTH_Px_MANUAL_SXROLLOFF_FIELD 1 +#define STV090x_OFFST_Px_ROLLOFF_CONTROL_FIELD 0 +#define STV090x_WIDTH_Px_ROLLOFF_CONTROL_FIELD 2 + +#define STV090x_Px_DMDMODCOD(__x) (0xF411 - (__x - 1) * 0x200) +#define STV090x_P1_DMDMODCOD STV090x_Px_DMDMODCOD(1) +#define STV090x_P2_DMDMODCOD STV090x_Px_DMDMODCOD(2) +#define STV090x_OFFST_Px_MANUAL_MODCOD_FIELD 7 +#define STV090x_WIDTH_Px_MANUAL_MODCOD_FIELD 1 +#define STV090x_OFFST_Px_DEMOD_MODCOD_FIELD 2 +#define STV090x_WIDTH_Px_DEMOD_MODCOD_FIELD 5 +#define STV090x_OFFST_Px_DEMOD_TYPE_FIELD 0 +#define STV090x_WIDTH_Px_DEMOD_TYPE_FIELD 2 + +#define STV090x_Px_DSTATUS(__x) (0xF412 - (__x - 1) * 0x200) +#define STV090x_P1_DSTATUS STV090x_Px_DSTATUS(1) +#define STV090x_P2_DSTATUS STV090x_Px_DSTATUS(2) +#define STV090x_OFFST_Px_CAR_LOCK_FIELD 7 +#define STV090x_WIDTH_Px_CAR_LOCK_FIELD 1 +#define STV090x_OFFST_Px_TMGLOCK_QUALITY_FIELD 5 +#define STV090x_WIDTH_Px_TMGLOCK_QUALITY_FIELD 2 +#define STV090x_OFFST_Px_LOCK_DEFINITIF_FIELD 3 +#define STV090x_WIDTH_Px_LOCK_DEFINITIF_FIELD 1 + +#define STV090x_Px_DSTATUS2(__x) (0xF413 - (__x - 1) * 0x200) +#define STV090x_P1_DSTATUS2 STV090x_Px_DSTATUS2(1) +#define STV090x_P2_DSTATUS2 STV090x_Px_DSTATUS2(2) +#define STV090x_OFFST_Px_DEMOD_DELOCK_FIELD 7 +#define STV090x_WIDTH_Px_DEMOD_DELOCK_FIELD 1 +#define STV090x_OFFST_Px_AGC1_NOSIGNALACK_FIELD 3 +#define STV090x_WIDTH_Px_AGC1_NOSIGNALACK_FIELD 1 +#define STV090x_OFFST_Px_AGC2_OVERFLOW_FIELD 2 +#define STV090x_WIDTH_Px_AGC2_OVERFLOW_FIELD 1 +#define STV090x_OFFST_Px_CFR_OVERFLOW_FIELD 1 +#define STV090x_WIDTH_Px_CFR_OVERFLOW_FIELD 1 +#define STV090x_OFFST_Px_GAMMA_OVERUNDER_FIELD 0 +#define STV090x_WIDTH_Px_GAMMA_OVERUNDER_FIELD 1 + +#define STV090x_Px_DMDCFGMD(__x) (0xF414 - (__x - 1) * 0x200) +#define STV090x_P1_DMDCFGMD STV090x_Px_DMDCFGMD(1) +#define STV090x_P2_DMDCFGMD STV090x_Px_DMDCFGMD(2) +#define STV090x_OFFST_Px_DVBS2_ENABLE_FIELD 7 +#define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD 1 +#define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD 6 +#define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD 1 +#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD 4 +#define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD 1 +#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD 3 +#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD 1 +#define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD 2 +#define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD 1 +#define STV090x_OFFST_Px_TUN_RNG_FIELD 0 +#define STV090x_WIDTH_Px_TUN_RNG_FIELD 2 + +#define STV090x_Px_DMDCFG2(__x) (0xF415 - (__x - 1) * 0x200) +#define STV090x_P1_DMDCFG2 STV090x_Px_DMDCFG2(1) +#define STV090x_P2_DMDCFG2 STV090x_Px_DMDCFG2(2) +#define STV090x_OFFST_Px_S1S2_SEQUENTIAL_FIELD 6 +#define STV090x_WIDTH_Px_S1S2_SEQUENTIAL_FIELD 1 + +#define STV090x_Px_DMDISTATE(__x) (0xF416 - (__x - 1) * 0x200) +#define STV090x_P1_DMDISTATE STV090x_Px_DMDISTATE(1) +#define STV090x_P2_DMDISTATE STV090x_Px_DMDISTATE(2) +#define STV090x_OFFST_Px_I2C_DEMOD_MODE_FIELD 0 +#define STV090x_WIDTH_Px_I2C_DEMOD_MODE_FIELD 5 + +#define STV090x_Px_DMDTOM(__x) (0xF417 - (__x - 1) * 0x200) /* check */ +#define STV090x_P1_DMDTOM STV090x_Px_DMDTOM(1) +#define STV090x_P2_DMDTOM STV090x_Px_DMDTOM(2) + +#define STV090x_Px_DMDSTATE(__x) (0xF41B - (__x - 1) * 0x200) +#define STV090x_P1_DMDSTATE STV090x_Px_DMDSTATE(1) +#define STV090x_P2_DMDSTATE STV090x_Px_DMDSTATE(2) +#define STV090x_OFFST_Px_HEADER_MODE_FIELD 5 +#define STV090x_WIDTH_Px_HEADER_MODE_FIELD 2 + +#define STV090x_Px_DMDFLYW(__x) (0xF41C - (__x - 1) * 0x200) +#define STV090x_P1_DMDFLYW STV090x_Px_DMDFLYW(1) +#define STV090x_P2_DMDFLYW STV090x_Px_DMDFLYW(2) +#define STV090x_OFFST_Px_I2C_IRQVAL_FIELD 4 +#define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD 4 +#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD 0 +#define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD 4 + +#define STV090x_Px_DSTATUS3(__x) (0xF41D - (__x - 1) * 0x200) +#define STV090x_P1_DSTATUS3 STV090x_Px_DSTATUS3(1) +#define STV090x_P2_DSTATUS3 STV090x_Px_DSTATUS3(2) +#define STV090x_OFFST_Px_DEMOD_CFGMODE_FIELD 5 +#define STV090x_WIDTH_Px_DEMOD_CFGMODE_FIELD 2 + +#define STV090x_Px_DMDCFG3(__x) (0xF41E - (__x - 1) * 0x200) +#define STV090x_P1_DMDCFG3 STV090x_Px_DMDCFG3(1) +#define STV090x_P2_DMDCFG3 STV090x_Px_DMDCFG3(2) +#define STV090x_OFFST_Px_NOSTOP_FIFOFULL_FIELD 3 +#define STV090x_WIDTH_Px_NOSTOP_FIFOFULL_FIELD 1 + +#define STV090x_Px_DMDCFG4(__x) (0xf41f - (__x - 1) * 0x200) +#define STV090x_P1_DMDCFG4 STV090x_Px_DMDCFG4(1) +#define STV090x_P2_DMDCFG4 STV090x_Px_DMDCFG4(2) + +#define STV090x_Px_CORRELMANT(__x) (0xF420 - (__x - 1) * 0x200) +#define STV090x_P1_CORRELMANT STV090x_Px_CORRELMANT(1) +#define STV090x_P2_CORRELMANT STV090x_Px_CORRELMANT(2) +#define STV090x_OFFST_Px_CORREL_MANT_FIELD 0 +#define STV090x_WIDTH_Px_CORREL_MANT_FIELD 8 + +#define STV090x_Px_CORRELABS(__x) (0xF421 - (__x - 1) * 0x200) +#define STV090x_P1_CORRELABS STV090x_Px_CORRELABS(1) +#define STV090x_P2_CORRELABS STV090x_Px_CORRELABS(2) +#define STV090x_OFFST_Px_CORREL_ABS_FIELD 0 +#define STV090x_WIDTH_Px_CORREL_ABS_FIELD 8 + +#define STV090x_Px_CORRELEXP(__x) (0xF422 - (__x - 1) * 0x200) +#define STV090x_P1_CORRELEXP STV090x_Px_CORRELEXP(1) +#define STV090x_P2_CORRELEXP STV090x_Px_CORRELEXP(2) +#define STV090x_OFFST_Px_CORREL_ABSEXP_FIELD 4 +#define STV090x_WIDTH_Px_CORREL_ABSEXP_FIELD 4 +#define STV090x_OFFST_Px_CORREL_EXP_FIELD 0 +#define STV090x_WIDTH_Px_CORREL_EXP_FIELD 4 + +#define STV090x_Px_PLHMODCOD(__x) (0xF424 - (__x - 1) * 0x200) +#define STV090x_P1_PLHMODCOD STV090x_Px_PLHMODCOD(1) +#define STV090x_P2_PLHMODCOD STV090x_Px_PLHMODCOD(2) +#define STV090x_OFFST_Px_SPECINV_DEMOD_FIELD 7 +#define STV090x_WIDTH_Px_SPECINV_DEMOD_FIELD 1 +#define STV090x_OFFST_Px_PLH_MODCOD_FIELD 2 +#define STV090x_WIDTH_Px_PLH_MODCOD_FIELD 5 +#define STV090x_OFFST_Px_PLH_TYPE_FIELD 0 +#define STV090x_WIDTH_Px_PLH_TYPE_FIELD 2 + +#define STV090x_Px_AGCK32(__x) (0xf42b - (__x - 1) * 0x200) +#define STV090x_P1_AGCK32 STV090x_Px_AGCK32(1) +#define STV090x_P2_AGCK32 STV090x_Px_AGCK32(2) + +#define STV090x_Px_AGC2O(__x) (0xF42C - (__x - 1) * 0x200) +#define STV090x_P1_AGC2O STV090x_Px_AGC2O(1) +#define STV090x_P2_AGC2O STV090x_Px_AGC2O(2) + +#define STV090x_Px_AGC2REF(__x) (0xF42D - (__x - 1) * 0x200) +#define STV090x_P1_AGC2REF STV090x_Px_AGC2REF(1) +#define STV090x_P2_AGC2REF STV090x_Px_AGC2REF(2) +#define STV090x_OFFST_Px_AGC2_REF_FIELD 0 +#define STV090x_WIDTH_Px_AGC2_REF_FIELD 8 + +#define STV090x_Px_AGC1ADJ(__x) (0xF42E - (__x - 1) * 0x200) +#define STV090x_P1_AGC1ADJ STV090x_Px_AGC1ADJ(1) +#define STV090x_P2_AGC1ADJ STV090x_Px_AGC1ADJ(2) +#define STV090x_OFFST_Px_AGC1_ADJUSTED_FIELD 0 +#define STV090x_WIDTH_Px_AGC1_ADJUSTED_FIELD 7 + +#define STV090x_Px_AGC2Iy(__x, __y) (0xF437 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_AGC2I0 STV090x_Px_AGC2Iy(1, 0) +#define STV090x_P1_AGC2I1 STV090x_Px_AGC2Iy(1, 1) +#define STV090x_P2_AGC2I0 STV090x_Px_AGC2Iy(2, 0) +#define STV090x_P2_AGC2I1 STV090x_Px_AGC2Iy(2, 1) +#define STV090x_OFFST_Px_AGC2_INTEGRATOR_FIELD 0 +#define STV090x_WIDTH_Px_AGC2_INTEGRATOR_FIELD 8 + +#define STV090x_Px_CARCFG(__x) (0xF438 - (__x - 1) * 0x200) +#define STV090x_P1_CARCFG STV090x_Px_CARCFG(1) +#define STV090x_P2_CARCFG STV090x_Px_CARCFG(2) +#define STV090x_OFFST_Px_EN_CAR2CENTER_FIELD 5 +#define STV090x_WIDTH_Px_EN_CAR2CENTER_FIELD 1 +#define STV090x_OFFST_Px_ROTATON_FIELD 2 +#define STV090x_WIDTH_Px_ROTATON_FIELD 1 +#define STV090x_OFFST_Px_PH_DET_ALGO_FIELD 0 +#define STV090x_WIDTH_Px_PH_DET_ALGO_FIELD 2 + +#define STV090x_Px_ACLC(__x) (0xF439 - (__x - 1) * 0x200) +#define STV090x_P1_ACLC STV090x_Px_ACLC(1) +#define STV090x_P2_ACLC STV090x_Px_ACLC(2) +#define STV090x_OFFST_Px_CAR_ALPHA_MANT_FIELD 4 +#define STV090x_WIDTH_Px_CAR_ALPHA_MANT_FIELD 2 +#define STV090x_OFFST_Px_CAR_ALPHA_EXP_FIELD 0 +#define STV090x_WIDTH_Px_CAR_ALPHA_EXP_FIELD 4 + +#define STV090x_Px_BCLC(__x) (0xF43A - (__x - 1) * 0x200) +#define STV090x_P1_BCLC STV090x_Px_BCLC(1) +#define STV090x_P2_BCLC STV090x_Px_BCLC(2) +#define STV090x_OFFST_Px_CAR_BETA_MANT_FIELD 4 +#define STV090x_WIDTH_Px_CAR_BETA_MANT_FIELD 2 +#define STV090x_OFFST_Px_CAR_BETA_EXP_FIELD 0 +#define STV090x_WIDTH_Px_CAR_BETA_EXP_FIELD 4 + +#define STV090x_Px_CARFREQ(__x) (0xF43D - (__x - 1) * 0x200) +#define STV090x_P1_CARFREQ STV090x_Px_CARFREQ(1) +#define STV090x_P2_CARFREQ STV090x_Px_CARFREQ(2) +#define STV090x_OFFST_Px_KC_COARSE_EXP_FIELD 4 +#define STV090x_WIDTH_Px_KC_COARSE_EXP_FIELD 4 +#define STV090x_OFFST_Px_BETA_FREQ_FIELD 0 +#define STV090x_WIDTH_Px_BETA_FREQ_FIELD 4 + +#define STV090x_Px_CARHDR(__x) (0xF43E - (__x - 1) * 0x200) +#define STV090x_P1_CARHDR STV090x_Px_CARHDR(1) +#define STV090x_P2_CARHDR STV090x_Px_CARHDR(2) +#define STV090x_OFFST_Px_FREQ_HDR_FIELD 0 +#define STV090x_WIDTH_Px_FREQ_HDR_FIELD 8 + +#define STV090x_Px_LDT(__x) (0xF43F - (__x - 1) * 0x200) +#define STV090x_P1_LDT STV090x_Px_LDT(1) +#define STV090x_P2_LDT STV090x_Px_LDT(2) +#define STV090x_OFFST_Px_CARLOCK_THRES_FIELD 0 +#define STV090x_WIDTH_Px_CARLOCK_THRES_FIELD 8 + +#define STV090x_Px_LDT2(__x) (0xF440 - (__x - 1) * 0x200) +#define STV090x_P1_LDT2 STV090x_Px_LDT2(1) +#define STV090x_P2_LDT2 STV090x_Px_LDT2(2) +#define STV090x_OFFST_Px_CARLOCK_THRES2_FIELD 0 +#define STV090x_WIDTH_Px_CARLOCK_THRES2_FIELD 8 + +#define STV090x_Px_CFRICFG(__x) (0xF441 - (__x - 1) * 0x200) +#define STV090x_P1_CFRICFG STV090x_Px_CFRICFG(1) +#define STV090x_P2_CFRICFG STV090x_Px_CFRICFG(2) +#define STV090x_OFFST_Px_NEG_CFRSTEP_FIELD 0 +#define STV090x_WIDTH_Px_NEG_CFRSTEP_FIELD 1 + +#define STV090x_Pn_CFRUPy(__x, __y) (0xF443 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_CFRUP0 STV090x_Pn_CFRUPy(1, 0) +#define STV090x_P1_CFRUP1 STV090x_Pn_CFRUPy(1, 1) +#define STV090x_P2_CFRUP0 STV090x_Pn_CFRUPy(2, 0) +#define STV090x_P2_CFRUP1 STV090x_Pn_CFRUPy(2, 1) +#define STV090x_OFFST_Px_CFR_UP_FIELD 0 +#define STV090x_WIDTH_Px_CFR_UP_FIELD 8 + +#define STV090x_Pn_CFRLOWy(__x, __y) (0xF447 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_CFRLOW0 STV090x_Pn_CFRLOWy(1, 0) +#define STV090x_P1_CFRLOW1 STV090x_Pn_CFRLOWy(1, 1) +#define STV090x_P2_CFRLOW0 STV090x_Pn_CFRLOWy(2, 0) +#define STV090x_P2_CFRLOW1 STV090x_Pn_CFRLOWy(2, 1) +#define STV090x_OFFST_Px_CFR_LOW_FIELD 0 +#define STV090x_WIDTH_Px_CFR_LOW_FIELD 8 + +#define STV090x_Pn_CFRINITy(__x, __y) (0xF449 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_CFRINIT0 STV090x_Pn_CFRINITy(1, 0) +#define STV090x_P1_CFRINIT1 STV090x_Pn_CFRINITy(1, 1) +#define STV090x_P2_CFRINIT0 STV090x_Pn_CFRINITy(2, 0) +#define STV090x_P2_CFRINIT1 STV090x_Pn_CFRINITy(2, 1) +#define STV090x_OFFST_Px_CFR_INIT_FIELD 0 +#define STV090x_WIDTH_Px_CFR_INIT_FIELD 8 + +#define STV090x_Px_CFRINC1(__x) (0xF44A - (__x - 1) * 0x200) +#define STV090x_P1_CFRINC1 STV090x_Px_CFRINC1(1) +#define STV090x_P2_CFRINC1 STV090x_Px_CFRINC1(2) +#define STV090x_OFFST_Px_CFR_INC1_FIELD 0 +#define STV090x_WIDTH_Px_CFR_INC1_FIELD 7 /* check */ + +#define STV090x_Px_CFRINC0(__x) (0xF44B - (__x - 1) * 0x200) +#define STV090x_P1_CFRINC0 STV090x_Px_CFRINC0(1) +#define STV090x_P2_CFRINC0 STV090x_Px_CFRINC0(2) +#define STV090x_OFFST_Px_CFR_INC0_FIELD 4 /* check */ +#define STV090x_WIDTH_Px_CFR_INC0_FIELD 4 + +#define STV090x_Pn_CFRy(__x, __y) (0xF44E - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_CFR0 STV090x_Pn_CFRy(1, 0) +#define STV090x_P1_CFR1 STV090x_Pn_CFRy(1, 1) +#define STV090x_P1_CFR2 STV090x_Pn_CFRy(1, 2) +#define STV090x_P2_CFR0 STV090x_Pn_CFRy(2, 0) +#define STV090x_P2_CFR1 STV090x_Pn_CFRy(2, 1) +#define STV090x_P2_CFR2 STV090x_Pn_CFRy(2, 2) +#define STV090x_OFFST_Px_CAR_FREQ_FIELD 0 +#define STV090x_WIDTH_Px_CAR_FREQ_FIELD 8 + +#define STV090x_Px_LDI(__x) (0xF44F - (__x - 1) * 0x200) +#define STV090x_P1_LDI STV090x_Px_LDI(1) +#define STV090x_P2_LDI STV090x_Px_LDI(2) +#define STV090x_OFFST_Px_LOCK_DET_INTEGR_FIELD 0 +#define STV090x_WIDTH_Px_LOCK_DET_INTEGR_FIELD 8 + +#define STV090x_Px_TMGCFG(__x) (0xF450 - (__x - 1) * 0x200) +#define STV090x_P1_TMGCFG STV090x_Px_TMGCFG(1) +#define STV090x_P2_TMGCFG STV090x_Px_TMGCFG(2) +#define STV090x_OFFST_Px_TMGLOCK_BETA_FIELD 6 +#define STV090x_WIDTH_Px_TMGLOCK_BETA_FIELD 2 +#define STV090x_OFFST_Px_DO_TIMING_FIELD 4 +#define STV090x_WIDTH_Px_DO_TIMING_FIELD 1 +#define STV090x_OFFST_Px_TMG_MINFREQ_FIELD 0 +#define STV090x_WIDTH_Px_TMG_MINFREQ_FIELD 2 + +#define STV090x_Px_RTC(__x) (0xF451 - (__x - 1) * 0x200) +#define STV090x_P1_RTC STV090x_Px_RTC(1) +#define STV090x_P2_RTC STV090x_Px_RTC(2) +#define STV090x_OFFST_Px_TMGALPHA_EXP_FIELD 4 +#define STV090x_WIDTH_Px_TMGALPHA_EXP_FIELD 4 +#define STV090x_OFFST_Px_TMGBETA_EXP_FIELD 0 +#define STV090x_WIDTH_Px_TMGBETA_EXP_FIELD 4 + +#define STV090x_Px_RTCS2(__x) (0xF452 - (__x - 1) * 0x200) +#define STV090x_P1_RTCS2 STV090x_Px_RTCS2(1) +#define STV090x_P2_RTCS2 STV090x_Px_RTCS2(2) +#define STV090x_OFFST_Px_TMGALPHAS2_EXP_FIELD 4 +#define STV090x_WIDTH_Px_TMGALPHAS2_EXP_FIELD 4 +#define STV090x_OFFST_Px_TMGBETAS2_EXP_FIELD 0 +#define STV090x_WIDTH_Px_TMGBETAS2_EXP_FIELD 4 + +#define STV090x_Px_TMGTHRISE(__x) (0xF453 - (__x - 1) * 0x200) +#define STV090x_P1_TMGTHRISE STV090x_Px_TMGTHRISE(1) +#define STV090x_P2_TMGTHRISE STV090x_Px_TMGTHRISE(2) +#define STV090x_OFFST_Px_TMGLOCK_THRISE_FIELD 0 +#define STV090x_WIDTH_Px_TMGLOCK_THRISE_FIELD 8 + +#define STV090x_Px_TMGTHFALL(__x) (0xF454 - (__x - 1) * 0x200) +#define STV090x_P1_TMGTHFALL STV090x_Px_TMGTHFALL(1) +#define STV090x_P2_TMGTHFALL STV090x_Px_TMGTHFALL(2) +#define STV090x_OFFST_Px_TMGLOCK_THFALL_FIELD 0 +#define STV090x_WIDTH_Px_TMGLOCK_THFALL_FIELD 8 + +#define STV090x_Px_SFRUPRATIO(__x) (0xF455 - (__x - 1) * 0x200) +#define STV090x_P1_SFRUPRATIO STV090x_Px_SFRUPRATIO(1) +#define STV090x_P2_SFRUPRATIO STV090x_Px_SFRUPRATIO(2) +#define STV090x_OFFST_Px_SFR_UPRATIO_FIELD 0 +#define STV090x_WIDTH_Px_SFR_UPRATIO_FIELD 8 + +#define STV090x_Px_SFRLOWRATIO(__x) (0xF456 - (__x - 1) * 0x200) +#define STV090x_P1_SFRLOWRATIO STV090x_Px_SFRLOWRATIO(1) +#define STV090x_P2_SFRLOWRATIO STV090x_Px_SFRLOWRATIO(2) +#define STV090x_OFFST_Px_SFR_LOWRATIO_FIELD 0 +#define STV090x_WIDTH_Px_SFR_LOWRATIO_FIELD 8 + +#define STV090x_Px_KREFTMG(__x) (0xF458 - (__x - 1) * 0x200) +#define STV090x_P1_KREFTMG STV090x_Px_KREFTMG(1) +#define STV090x_P2_KREFTMG STV090x_Px_KREFTMG(2) +#define STV090x_OFFST_Px_KREF_TMG_FIELD 0 +#define STV090x_WIDTH_Px_KREF_TMG_FIELD 8 + +#define STV090x_Px_SFRSTEP(__x) (0xF459 - (__x - 1) * 0x200) +#define STV090x_P1_SFRSTEP STV090x_Px_SFRSTEP(1) +#define STV090x_P2_SFRSTEP STV090x_Px_SFRSTEP(2) +#define STV090x_OFFST_Px_SFR_SCANSTEP_FIELD 4 +#define STV090x_WIDTH_Px_SFR_SCANSTEP_FIELD 4 +#define STV090x_OFFST_Px_SFR_CENTERSTEP_FIELD 0 +#define STV090x_WIDTH_Px_SFR_CENTERSTEP_FIELD 4 + +#define STV090x_Px_TMGCFG2(__x) (0xF45A - (__x - 1) * 0x200) +#define STV090x_P1_TMGCFG2 STV090x_Px_TMGCFG2(1) +#define STV090x_P2_TMGCFG2 STV090x_Px_TMGCFG2(2) +#define STV090x_OFFST_Px_SFRRATIO_FINE_FIELD 0 +#define STV090x_WIDTH_Px_SFRRATIO_FINE_FIELD 1 + +#define STV090x_Px_SFRINIT1(__x) (0xF45E - (__x - 1) * 0x200) +#define STV090x_P1_SFRINIT1 STV090x_Px_SFRINIT1(1) +#define STV090x_P2_SFRINIT1 STV090x_Px_SFRINIT1(2) +#define STV090x_OFFST_Px_SFR_INIT1_FIELD 0 +#define STV090x_WIDTH_Px_SFR_INIT1_FIELD 7 + +#define STV090x_Px_SFRINIT0(__x) (0xF45F - (__x - 1) * 0x200) +#define STV090x_P1_SFRINIT0 STV090x_Px_SFRINIT0(1) +#define STV090x_P2_SFRINIT0 STV090x_Px_SFRINIT0(2) +#define STV090x_OFFST_Px_SFR_INIT0_FIELD 0 +#define STV090x_WIDTH_Px_SFR_INIT0_FIELD 8 + +#define STV090x_Px_SFRUP1(__x) (0xF460 - (__x - 1) * 0x200) +#define STV090x_P1_SFRUP1 STV090x_Px_SFRUP1(1) +#define STV090x_P2_SFRUP1 STV090x_Px_SFRUP1(2) +#define STV090x_OFFST_Px_SYMB_FREQ_UP1_FIELD 0 +#define STV090x_WIDTH_Px_SYMB_FREQ_UP1_FIELD 7 + +#define STV090x_Px_SFRUP0(__x) (0xF461 - (__x - 1) * 0x200) +#define STV090x_P1_SFRUP0 STV090x_Px_SFRUP0(1) +#define STV090x_P2_SFRUP0 STV090x_Px_SFRUP0(2) +#define STV090x_OFFST_Px_SYMB_FREQ_UP0_FIELD 0 +#define STV090x_WIDTH_Px_SYMB_FREQ_UP0_FIELD 8 + +#define STV090x_Px_SFRLOW1(__x) (0xF462 - (__x - 1) * 0x200) +#define STV090x_P1_SFRLOW1 STV090x_Px_SFRLOW1(1) +#define STV090x_P2_SFRLOW1 STV090x_Px_SFRLOW1(2) +#define STV090x_OFFST_Px_SYMB_FREQ_LOW1_FIELD 0 +#define STV090x_WIDTH_Px_SYMB_FREQ_LOW1_FIELD 7 + +#define STV090x_Px_SFRLOW0(__x) (0xF463 - (__x - 1) * 0x200) +#define STV090x_P1_SFRLOW0 STV090x_Px_SFRLOW0(1) +#define STV090x_P2_SFRLOW0 STV090x_Px_SFRLOW0(2) +#define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD 0 +#define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD 8 + +#define STV090x_Px_SFRy(__x, __y) (0xF467 - (__x-1) * 0x200 - __y) +#define STV090x_P1_SFR0 STV090x_Px_SFRy(1, 0) +#define STV090x_P1_SFR1 STV090x_Px_SFRy(1, 1) +#define STV090x_P1_SFR2 STV090x_Px_SFRy(1, 2) +#define STV090x_P1_SFR3 STV090x_Px_SFRy(1, 3) +#define STV090x_P2_SFR0 STV090x_Px_SFRy(2, 0) +#define STV090x_P2_SFR1 STV090x_Px_SFRy(2, 1) +#define STV090x_P2_SFR2 STV090x_Px_SFRy(2, 2) +#define STV090x_P2_SFR3 STV090x_Px_SFRy(2, 3) +#define STV090x_OFFST_Px_SYMB_FREQ_FIELD 0 +#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD 8 + +#define STV090x_Px_TMGREG2(__x) (0xF468 - (__x - 1) * 0x200) +#define STV090x_P1_TMGREG2 STV090x_Px_TMGREG2(1) +#define STV090x_P2_TMGREG2 STV090x_Px_TMGREG2(2) +#define STV090x_OFFST_Px_TMGREG_FIELD 0 +#define STV090x_WIDTH_Px_TMGREG_FIELD 8 + +#define STV090x_Px_TMGREG1(__x) (0xF469 - (__x - 1) * 0x200) +#define STV090x_P1_TMGREG1 STV090x_Px_TMGREG1(1) +#define STV090x_P2_TMGREG1 STV090x_Px_TMGREG1(2) +#define STV090x_OFFST_Px_TMGREG_FIELD 0 +#define STV090x_WIDTH_Px_TMGREG_FIELD 8 + +#define STV090x_Px_TMGREG0(__x) (0xF46A - (__x - 1) * 0x200) +#define STV090x_P1_TMGREG0 STV090x_Px_TMGREG0(1) +#define STV090x_P2_TMGREG0 STV090x_Px_TMGREG0(2) +#define STV090x_OFFST_Px_TMGREG_FIELD 0 +#define STV090x_WIDTH_Px_TMGREG_FIELD 8 + +#define STV090x_Px_TMGLOCKy(__x, __y) (0xF46C - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_TMGLOCK0 STV090x_Px_TMGLOCKy(1, 0) +#define STV090x_P1_TMGLOCK1 STV090x_Px_TMGLOCKy(1, 1) +#define STV090x_P2_TMGLOCK0 STV090x_Px_TMGLOCKy(2, 0) +#define STV090x_P2_TMGLOCK1 STV090x_Px_TMGLOCKy(2, 1) +#define STV090x_OFFST_Px_TMGLOCK_LEVEL_FIELD 0 +#define STV090x_WIDTH_Px_TMGLOCK_LEVEL_FIELD 8 + +#define STV090x_Px_TMGOBS(__x) (0xF46D - (__x - 1) * 0x200) +#define STV090x_P1_TMGOBS STV090x_Px_TMGOBS(1) +#define STV090x_P2_TMGOBS STV090x_Px_TMGOBS(2) +#define STV090x_OFFST_Px_ROLLOFF_STATUS_FIELD 6 +#define STV090x_WIDTH_Px_ROLLOFF_STATUS_FIELD 2 + +#define STV090x_Px_EQUALCFG(__x) (0xF46F - (__x - 1) * 0x200) +#define STV090x_P1_EQUALCFG STV090x_Px_EQUALCFG(1) +#define STV090x_P2_EQUALCFG STV090x_Px_EQUALCFG(2) +#define STV090x_OFFST_Px_EQUAL_ON_FIELD 6 +#define STV090x_WIDTH_Px_EQUAL_ON_FIELD 1 +#define STV090x_OFFST_Px_MU_EQUALDFE_FIELD 0 +#define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD 3 + +#define STV090x_Px_EQUAIy(__x, __y) (0xf470 - (__x-1) * 0x200 + 2 * (__y-1)) +#define STV090x_P1_EQUAI1 STV090x_Px_EQUAIy(1, 1) +#define STV090x_P1_EQUAI2 STV090x_Px_EQUAIy(1, 2) +#define STV090x_P1_EQUAI3 STV090x_Px_EQUAIy(1, 3) +#define STV090x_P1_EQUAI4 STV090x_Px_EQUAIy(1, 4) +#define STV090x_P1_EQUAI5 STV090x_Px_EQUAIy(1, 5) +#define STV090x_P1_EQUAI6 STV090x_Px_EQUAIy(1, 6) +#define STV090x_P1_EQUAI7 STV090x_Px_EQUAIy(1, 7) +#define STV090x_P1_EQUAI8 STV090x_Px_EQUAIy(1, 8) + +#define STV090x_P2_EQUAI1 STV090x_Px_EQUAIy(2, 1) +#define STV090x_P2_EQUAI2 STV090x_Px_EQUAIy(2, 2) +#define STV090x_P2_EQUAI3 STV090x_Px_EQUAIy(2, 3) +#define STV090x_P2_EQUAI4 STV090x_Px_EQUAIy(2, 4) +#define STV090x_P2_EQUAI5 STV090x_Px_EQUAIy(2, 5) +#define STV090x_P2_EQUAI6 STV090x_Px_EQUAIy(2, 6) +#define STV090x_P2_EQUAI7 STV090x_Px_EQUAIy(2, 7) +#define STV090x_P2_EQUAI8 STV090x_Px_EQUAIy(2, 8) +#define STV090x_OFFST_Px_EQUA_ACCIy_FIELD 0 +#define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD 8 + +#define STV090x_Px_EQUAQy(__x, __y) (0xf471 - (__x-1) * 0x200 + 2 * (__y-1)) +#define STV090x_P1_EQUAQ1 STV090x_Px_EQUAQy(1, 1) +#define STV090x_P1_EQUAQ2 STV090x_Px_EQUAQy(1, 2) +#define STV090x_P1_EQUAQ3 STV090x_Px_EQUAQy(1, 3) +#define STV090x_P1_EQUAQ4 STV090x_Px_EQUAQy(1, 4) +#define STV090x_P1_EQUAQ5 STV090x_Px_EQUAQy(1, 5) +#define STV090x_P1_EQUAQ6 STV090x_Px_EQUAQy(1, 6) +#define STV090x_P1_EQUAQ7 STV090x_Px_EQUAQy(1, 7) +#define STV090x_P1_EQUAQ8 STV090x_Px_EQUAQy(1, 8) + +#define STV090x_P2_EQUAQ1 STV090x_Px_EQUAQy(2, 1) +#define STV090x_P2_EQUAQ2 STV090x_Px_EQUAQy(2, 2) +#define STV090x_P2_EQUAQ3 STV090x_Px_EQUAQy(2, 3) +#define STV090x_P2_EQUAQ4 STV090x_Px_EQUAQy(2, 4) +#define STV090x_P2_EQUAQ5 STV090x_Px_EQUAQy(2, 5) +#define STV090x_P2_EQUAQ6 STV090x_Px_EQUAQy(2, 6) +#define STV090x_P2_EQUAQ7 STV090x_Px_EQUAQy(2, 7) +#define STV090x_P2_EQUAQ8 STV090x_Px_EQUAQy(2, 8) +#define STV090x_OFFST_Px_EQUA_ACCQy_FIELD 0 +#define STV090x_WIDTH_Px_EQUA_ACCQy_FIELD 8 + +#define STV090x_Px_NNOSDATATy(__x, __y) (0xf481 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NNOSDATAT0 STV090x_Px_NNOSDATATy(1, 0) +#define STV090x_P1_NNOSDATAT1 STV090x_Px_NNOSDATATy(1, 1) +#define STV090x_P2_NNOSDATAT0 STV090x_Px_NNOSDATATy(2, 0) +#define STV090x_P2_NNOSDATAT1 STV090x_Px_NNOSDATATy(2, 1) +#define STV090x_OFFST_Px_NOSDATAT_NORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSDATAT_NORMED_FIELD 8 + +#define STV090x_Px_NNOSDATAy(__x, __y) (0xf483 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NNOSDATA0 STV090x_Px_NNOSDATAy(1, 0) +#define STV090x_P1_NNOSDATA1 STV090x_Px_NNOSDATAy(1, 1) +#define STV090x_P2_NNOSDATA0 STV090x_Px_NNOSDATAy(2, 0) +#define STV090x_P2_NNOSDATA1 STV090x_Px_NNOSDATAy(2, 1) +#define STV090x_OFFST_Px_NOSDATA_NORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSDATA_NORMED_FIELD 8 + +#define STV090x_Px_NNOSPLHTy(__x, __y) (0xf485 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NNOSPLHT0 STV090x_Px_NNOSPLHTy(1, 0) +#define STV090x_P1_NNOSPLHT1 STV090x_Px_NNOSPLHTy(1, 1) +#define STV090x_P2_NNOSPLHT0 STV090x_Px_NNOSPLHTy(2, 0) +#define STV090x_P2_NNOSPLHT1 STV090x_Px_NNOSPLHTy(2, 1) +#define STV090x_OFFST_Px_NOSPLHT_NORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSPLHT_NORMED_FIELD 8 + +#define STV090x_Px_NNOSPLHy(__x, __y) (0xf487 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NNOSPLH0 STV090x_Px_NNOSPLHy(1, 0) +#define STV090x_P1_NNOSPLH1 STV090x_Px_NNOSPLHy(1, 1) +#define STV090x_P2_NNOSPLH0 STV090x_Px_NNOSPLHy(2, 0) +#define STV090x_P2_NNOSPLH1 STV090x_Px_NNOSPLHy(2, 1) +#define STV090x_OFFST_Px_NOSPLH_NORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSPLH_NORMED_FIELD 8 + +#define STV090x_Px_NOSDATATy(__x, __y) (0xf489 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NOSDATAT0 STV090x_Px_NOSDATATy(1, 0) +#define STV090x_P1_NOSDATAT1 STV090x_Px_NOSDATATy(1, 1) +#define STV090x_P2_NOSDATAT0 STV090x_Px_NOSDATATy(2, 0) +#define STV090x_P2_NOSDATAT1 STV090x_Px_NOSDATATy(2, 1) +#define STV090x_OFFST_Px_NOSDATAT_UNNORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSDATAT_UNNORMED_FIELD 8 + +#define STV090x_Px_NOSDATAy(__x, __y) (0xf48b - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NOSDATA0 STV090x_Px_NOSDATAy(1, 0) +#define STV090x_P1_NOSDATA1 STV090x_Px_NOSDATAy(1, 1) +#define STV090x_P2_NOSDATA0 STV090x_Px_NOSDATAy(2, 0) +#define STV090x_P2_NOSDATA1 STV090x_Px_NOSDATAy(2, 1) +#define STV090x_OFFST_Px_NOSDATA_UNNORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSDATA_UNNORMED_FIELD 8 + +#define STV090x_Px_NOSPLHTy(__x, __y) (0xf48d - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NOSPLHT0 STV090x_Px_NOSPLHTy(1, 0) +#define STV090x_P1_NOSPLHT1 STV090x_Px_NOSPLHTy(1, 1) +#define STV090x_P2_NOSPLHT0 STV090x_Px_NOSPLHTy(2, 0) +#define STV090x_P2_NOSPLHT1 STV090x_Px_NOSPLHTy(2, 1) +#define STV090x_OFFST_Px_NOSPLHT_UNNORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSPLHT_UNNORMED_FIELD 8 + +#define STV090x_Px_NOSPLHy(__x, __y) (0xf48f - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_NOSPLH0 STV090x_Px_NOSPLHy(1, 0) +#define STV090x_P1_NOSPLH1 STV090x_Px_NOSPLHy(1, 1) +#define STV090x_P2_NOSPLH0 STV090x_Px_NOSPLHy(2, 0) +#define STV090x_P2_NOSPLH1 STV090x_Px_NOSPLHy(2, 1) +#define STV090x_OFFST_Px_NOSPLH_UNNORMED_FIELD 0 +#define STV090x_WIDTH_Px_NOSPLH_UNNORMED_FIELD 8 + +#define STV090x_Px_CAR2CFG(__x) (0xf490 - (__x - 1) * 0x200) +#define STV090x_P1_CAR2CFG STV090x_Px_CAR2CFG(1) +#define STV090x_P2_CAR2CFG STV090x_Px_CAR2CFG(2) +#define STV090x_OFFST_Px_PN4_SELECT_FIELD 6 +#define STV090x_WIDTH_Px_PN4_SELECT_FIELD 1 +#define STV090x_OFFST_Px_CFR2_STOPDVBS1_FIELD 5 +#define STV090x_WIDTH_Px_CFR2_STOPDVBS1_FIELD 1 +#define STV090x_OFFST_Px_ROTA2ON_FIELD 2 +#define STV090x_WIDTH_Px_ROTA2ON_FIELD 1 +#define STV090x_OFFST_Px_PH_DET_ALGO2_FIELD 0 +#define STV090x_WIDTH_Px_PH_DET_ALGO2_FIELD 2 + +#define STV090x_Px_ACLC2(__x) (0xf491 - (__x - 1) * 0x200) +#define STV090x_P1_ACLC2 STV090x_Px_ACLC2(1) +#define STV090x_P2_ACLC2 STV090x_Px_ACLC2(2) +#define STV090x_OFFST_Px_CAR2_ALPHA_MANT_FIELD 4 +#define STV090x_WIDTH_Px_CAR2_ALPHA_MANT_FIELD 2 +#define STV090x_OFFST_Px_CAR2_ALPHA_EXP_FIELD 0 +#define STV090x_WIDTH_Px_CAR2_ALPHA_EXP_FIELD 4 + +#define STV090x_Px_BCLC2(__x) (0xf492 - (__x - 1) * 0x200) +#define STV090x_P1_BCLC2 STV090x_Px_BCLC2(1) +#define STV090x_P2_BCLC2 STV090x_Px_BCLC2(2) +#define STV090x_OFFST_Px_CAR2_BETA_MANT_FIELD 4 +#define STV090x_WIDTH_Px_CAR2_BETA_MANT_FIELD 2 +#define STV090x_OFFST_Px_CAR2_BETA_EXP_FIELD 0 +#define STV090x_WIDTH_Px_CAR2_BETA_EXP_FIELD 4 + +#define STV090x_Px_ACLC2S2Q(__x) (0xf497 - (__x - 1) * 0x200) +#define STV090x_P1_ACLC2S2Q STV090x_Px_ACLC2S2Q(1) +#define STV090x_P2_ACLC2S2Q STV090x_Px_ACLC2S2Q(2) +#define STV090x_OFFST_Px_ENAB_SPSKSYMB_FIELD 7 +#define STV090x_WIDTH_Px_ENAB_SPSKSYMB_FIELD 1 +#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_E_FIELD 4 + +#define STV090x_Px_ACLC2S28(__x) (0xf498 - (__x - 1) * 0x200) +#define STV090x_P1_ACLC2S28 STV090x_Px_ACLC2S28(1) +#define STV090x_P2_ACLC2S28 STV090x_Px_ACLC2S28(2) +#define STV090x_OFFST_Px_CAR2S2_8_ALPH_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_8_ALPH_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_E_FIELD 4 + +#define STV090x_Px_ACLC2S216A(__x) (0xf499 - (__x - 1) * 0x200) +#define STV090x_P1_ACLC2S216A STV090x_Px_ACLC2S216A(1) +#define STV090x_P2_ACLC2S216A STV090x_Px_ACLC2S216A(2) +#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD 4 + +#define STV090x_Px_ACLC2S232A(__x) (0xf49A - (__x - 1) * 0x200) +#define STV090x_P1_ACLC2S232A STV090x_Px_ACLC2S232A(1) +#define STV090x_P2_ACLC2S232A STV090x_Px_ACLC2S232A(2) +#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_E_FIELD 4 + +#define STV090x_Px_BCLC2S2Q(__x) (0xf49c - (__x - 1) * 0x200) +#define STV090x_P1_BCLC2S2Q STV090x_Px_BCLC2S2Q(1) +#define STV090x_P2_BCLC2S2Q STV090x_Px_BCLC2S2Q(2) +#define STV090x_OFFST_Px_CAR2S2_Q_BETA_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_Q_BETA_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_E_FIELD 4 + +#define STV090x_Px_BCLC2S28(__x) (0xf49d - (__x - 1) * 0x200) +#define STV090x_P1_BCLC2S28 STV090x_Px_BCLC2S28(1) +#define STV090x_P2_BCLC2S28 STV090x_Px_BCLC2S28(2) +#define STV090x_OFFST_Px_CAR2S2_8_BETA_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_8_BETA_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD 4 + +#define STV090x_Px_BCLC2S216A(__x) (0xf49e - (__x - 1) * 0x200) +#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1) +#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(2) +#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD 4 + +#define STV090x_Px_BCLC2S232A(__x) (0xf49f - (__x - 1) * 0x200) +#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1) +#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(2) +#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4 +#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_M_FIELD 2 +#define STV090x_OFFST_Px_CAR2S2_32A_BETA_E_FIELD 0 +#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_E_FIELD 4 + +#define STV090x_Px_PLROOT2(__x) (0xf4ac - (__x - 1) * 0x200) +#define STV090x_P1_PLROOT2 STV090x_Px_PLROOT2(1) +#define STV090x_P2_PLROOT2 STV090x_Px_PLROOT2(2) +#define STV090x_OFFST_Px_PLSCRAMB_MODE_FIELD 2 +#define STV090x_WIDTH_Px_PLSCRAMB_MODE_FIELD 2 +#define STV090x_OFFST_Px_PLSCRAMB_ROOT_FIELD 0 +#define STV090x_WIDTH_Px_PLSCRAMB_ROOT_FIELD 2 + +#define STV090x_Px_PLROOT1(__x) (0xf4ad - (__x - 1) * 0x200) +#define STV090x_P1_PLROOT1 STV090x_Px_PLROOT1(1) +#define STV090x_P2_PLROOT1 STV090x_Px_PLROOT1(2) +#define STV090x_OFFST_Px_PLSCRAMB_ROOT1_FIELD 0 +#define STV090x_WIDTH_Px_PLSCRAMB_ROOT1_FIELD 8 + +#define STV090x_Px_PLROOT0(__x) (0xf4ae - (__x - 1) * 0x200) +#define STV090x_P1_PLROOT0 STV090x_Px_PLROOT0(1) +#define STV090x_P2_PLROOT0 STV090x_Px_PLROOT0(2) +#define STV090x_OFFST_Px_PLSCRAMB_ROOT0_FIELD 0 +#define STV090x_WIDTH_Px_PLSCRAMB_ROOT0_FIELD 8 + +#define STV090x_Px_MODCODLST0(__x) (0xf4b0 - (__x - 1) * 0x200) /* check */ +#define STV090x_P1_MODCODLST0 STV090x_Px_MODCODLST0(1) +#define STV090x_P2_MODCODLST0 STV090x_Px_MODCODLST0(2) + +#define STV090x_Px_MODCODLST1(__x) (0xf4b1 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST1 STV090x_Px_MODCODLST1(1) +#define STV090x_P2_MODCODLST1 STV090x_Px_MODCODLST1(2) +#define STV090x_OFFST_Px_DIS_MODCOD29_FIELD 4 +#define STV090x_WIDTH_Px_DIS_MODCOD29_FIELD 4 +#define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD 0 +#define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD 4 + +#define STV090x_Px_MODCODLST2(__x) (0xf4b2 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST2 STV090x_Px_MODCODLST2(1) +#define STV090x_P2_MODCODLST2 STV090x_Px_MODCODLST2(2) +#define STV090x_OFFST_Px_DIS_32PSK_8_9_FIELD 4 +#define STV090x_WIDTH_Px_DIS_32PSK_8_9_FIELD 4 +#define STV090x_OFFST_Px_DIS_32PSK_5_6_FIELD 0 +#define STV090x_WIDTH_Px_DIS_32PSK_5_6_FIELD 4 + +#define STV090x_Px_MODCODLST3(__x) (0xf4b3 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST3 STV090x_Px_MODCODLST3(1) +#define STV090x_P2_MODCODLST3 STV090x_Px_MODCODLST3(2) +#define STV090x_OFFST_Px_DIS_32PSK_4_5_FIELD 4 +#define STV090x_WIDTH_Px_DIS_32PSK_4_5_FIELD 4 +#define STV090x_OFFST_Px_DIS_32PSK_3_4_FIELD 0 +#define STV090x_WIDTH_Px_DIS_32PSK_3_4_FIELD 4 + +#define STV090x_Px_MODCODLST4(__x) (0xf4b4 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST4 STV090x_Px_MODCODLST4(1) +#define STV090x_P2_MODCODLST4 STV090x_Px_MODCODLST4(2) +#define STV090x_OFFST_Px_DIS_16PSK_9_10_FIELD 4 +#define STV090x_WIDTH_Px_DIS_16PSK_9_10_FIELD 4 +#define STV090x_OFFST_Px_DIS_16PSK_8_9_FIELD 0 +#define STV090x_WIDTH_Px_DIS_16PSK_8_9_FIELD 4 + +#define STV090x_Px_MODCODLST5(__x) (0xf4b5 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST5 STV090x_Px_MODCODLST5(1) +#define STV090x_P2_MODCODLST5 STV090x_Px_MODCODLST5(2) +#define STV090x_OFFST_Px_DIS_16PSK_5_6_FIELD 4 +#define STV090x_WIDTH_Px_DIS_16PSK_5_6_FIELD 4 +#define STV090x_OFFST_Px_DIS_16PSK_4_5_FIELD 0 +#define STV090x_WIDTH_Px_DIS_16PSK_4_5_FIELD 4 + +#define STV090x_Px_MODCODLST6(__x) (0xf4b6 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST6 STV090x_Px_MODCODLST6(1) +#define STV090x_P2_MODCODLST6 STV090x_Px_MODCODLST6(2) +#define STV090x_OFFST_Px_DIS_16PSK_3_4_FIELD 4 +#define STV090x_WIDTH_Px_DIS_16PSK_3_4_FIELD 4 +#define STV090x_OFFST_Px_DIS_16PSK_2_3_FIELD 0 +#define STV090x_WIDTH_Px_DIS_16PSK_2_3_FIELD 4 + +#define STV090x_Px_MODCODLST7(__x) (0xf4b7 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST7 STV090x_Px_MODCODLST7(1) +#define STV090x_P2_MODCODLST7 STV090x_Px_MODCODLST7(2) +#define STV090x_OFFST_Px_DIS_8P_9_10_FIELD 4 +#define STV090x_WIDTH_Px_DIS_8P_9_10_FIELD 4 +#define STV090x_OFFST_Px_DIS_8P_8_9_FIELD 0 +#define STV090x_WIDTH_Px_DIS_8P_8_9_FIELD 4 + +#define STV090x_Px_MODCODLST8(__x) (0xf4b8 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST8 STV090x_Px_MODCODLST8(1) +#define STV090x_P2_MODCODLST8 STV090x_Px_MODCODLST8(2) +#define STV090x_OFFST_Px_DIS_8P_5_6_FIELD 4 +#define STV090x_WIDTH_Px_DIS_8P_5_6_FIELD 4 +#define STV090x_OFFST_Px_DIS_8P_3_4_FIELD 0 +#define STV090x_WIDTH_Px_DIS_8P_3_4_FIELD 4 + +#define STV090x_Px_MODCODLST9(__x) (0xf4b9 - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLST9 STV090x_Px_MODCODLST9(1) +#define STV090x_P2_MODCODLST9 STV090x_Px_MODCODLST9(2) +#define STV090x_OFFST_Px_DIS_8P_2_3_FIELD 4 +#define STV090x_WIDTH_Px_DIS_8P_2_3_FIELD 4 +#define STV090x_OFFST_Px_DIS_8P_3_5_FIELD 0 +#define STV090x_WIDTH_Px_DIS_8P_3_5_FIELD 4 + +#define STV090x_Px_MODCODLSTA(__x) (0xf4ba - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLSTA STV090x_Px_MODCODLSTA(1) +#define STV090x_P2_MODCODLSTA STV090x_Px_MODCODLSTA(2) +#define STV090x_OFFST_Px_DIS_QP_9_10_FIELD 4 +#define STV090x_WIDTH_Px_DIS_QP_9_10_FIELD 4 +#define STV090x_OFFST_Px_DIS_QP_8_9_FIELD 0 +#define STV090x_WIDTH_Px_DIS_QP_8_9_FIELD 4 + +#define STV090x_Px_MODCODLSTB(__x) (0xf4bb - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLSTB STV090x_Px_MODCODLSTB(1) +#define STV090x_P2_MODCODLSTB STV090x_Px_MODCODLSTB(2) +#define STV090x_OFFST_Px_DIS_QP_5_6_FIELD 4 +#define STV090x_WIDTH_Px_DIS_QP_5_6_FIELD 4 +#define STV090x_OFFST_Px_DIS_QP_4_5_FIELD 0 +#define STV090x_WIDTH_Px_DIS_QP_4_5_FIELD 4 + +#define STV090x_Px_MODCODLSTC(__x) (0xf4bc - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLSTC STV090x_Px_MODCODLSTC(1) +#define STV090x_P2_MODCODLSTC STV090x_Px_MODCODLSTC(2) +#define STV090x_OFFST_Px_DIS_QP_3_4_FIELD 4 +#define STV090x_WIDTH_Px_DIS_QP_3_4_FIELD 4 +#define STV090x_OFFST_Px_DIS_QP_2_3_FIELD 0 +#define STV090x_WIDTH_Px_DIS_QP_2_3_FIELD 4 + +#define STV090x_Px_MODCODLSTD(__x) (0xf4bd - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLSTD STV090x_Px_MODCODLSTD(1) +#define STV090x_P2_MODCODLSTD STV090x_Px_MODCODLSTD(2) +#define STV090x_OFFST_Px_DIS_QP_3_5_FIELD 4 +#define STV090x_WIDTH_Px_DIS_QP_3_5_FIELD 4 +#define STV090x_OFFST_Px_DIS_QP_1_2_FIELD 0 +#define STV090x_WIDTH_Px_DIS_QP_1_2_FIELD 4 + +#define STV090x_Px_MODCODLSTE(__x) (0xf4be - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLSTE STV090x_Px_MODCODLSTE(1) +#define STV090x_P2_MODCODLSTE STV090x_Px_MODCODLSTE(2) +#define STV090x_OFFST_Px_DIS_QP_2_5_FIELD 4 +#define STV090x_WIDTH_Px_DIS_QP_2_5_FIELD 4 +#define STV090x_OFFST_Px_DIS_QP_1_3_FIELD 0 +#define STV090x_WIDTH_Px_DIS_QP_1_3_FIELD 4 + +#define STV090x_Px_MODCODLSTF(__x) (0xf4bf - (__x - 1) * 0x200) +#define STV090x_P1_MODCODLSTF STV090x_Px_MODCODLSTF(1) +#define STV090x_P2_MODCODLSTF STV090x_Px_MODCODLSTF(2) +#define STV090x_OFFST_Px_DIS_QP_1_4_FIELD 4 +#define STV090x_WIDTH_Px_DIS_QP_1_4_FIELD 4 + +#define STV090x_Px_GAUSSR0(__x) (0xf4c0 - (__x - 1) * 0x200) +#define STV090x_P1_GAUSSR0 STV090x_Px_GAUSSR0(1) +#define STV090x_P2_GAUSSR0 STV090x_Px_GAUSSR0(2) +#define STV090x_OFFST_Px_EN_CCIMODE_FIELD 7 +#define STV090x_WIDTH_Px_EN_CCIMODE_FIELD 1 +#define STV090x_OFFST_Px_R0_GAUSSIEN_FIELD 0 +#define STV090x_WIDTH_Px_R0_GAUSSIEN_FIELD 7 + +#define STV090x_Px_CCIR0(__x) (0xf4c1 - (__x - 1) * 0x200) +#define STV090x_P1_CCIR0 STV090x_Px_CCIR0(1) +#define STV090x_P2_CCIR0 STV090x_Px_CCIR0(2) +#define STV090x_OFFST_Px_CCIDETECT_PLH_FIELD 7 +#define STV090x_WIDTH_Px_CCIDETECT_PLH_FIELD 1 +#define STV090x_OFFST_Px_R0_CCI_FIELD 0 +#define STV090x_WIDTH_Px_R0_CCI_FIELD 7 + +#define STV090x_Px_CCIQUANT(__x) (0xf4c2 - (__x - 1) * 0x200) +#define STV090x_P1_CCIQUANT STV090x_Px_CCIQUANT(1) +#define STV090x_P2_CCIQUANT STV090x_Px_CCIQUANT(2) +#define STV090x_OFFST_Px_CCI_BETA_FIELD 5 +#define STV090x_WIDTH_Px_CCI_BETA_FIELD 3 +#define STV090x_OFFST_Px_CCI_QUANT_FIELD 0 +#define STV090x_WIDTH_Px_CCI_QUANT_FIELD 5 + +#define STV090x_Px_CCITHRESH(__x) (0xf4c3 - (__x - 1) * 0x200) +#define STV090x_P1_CCITHRESH STV090x_Px_CCITHRESH(1) +#define STV090x_P2_CCITHRESH STV090x_Px_CCITHRESH(2) +#define STV090x_OFFST_Px_CCI_THRESHOLD_FIELD 0 +#define STV090x_WIDTH_Px_CCI_THRESHOLD_FIELD 8 + +#define STV090x_Px_CCIACC(__x) (0xf4c4 - (__x - 1) * 0x200) +#define STV090x_P1_CCIACC STV090x_Px_CCIACC(1) +#define STV090x_P2_CCIACC STV090x_Px_CCIACC(2) +#define STV090x_OFFST_Px_CCI_VALUE_FIELD 0 +#define STV090x_WIDTH_Px_CCI_VALUE_FIELD 8 + +#define STV090x_Px_DMDRESCFG(__x) (0xF4C6 - (__x - 1) * 0x200) +#define STV090x_P1_DMDRESCFG STV090x_Px_DMDRESCFG(1) +#define STV090x_P2_DMDRESCFG STV090x_Px_DMDRESCFG(2) +#define STV090x_OFFST_Px_DMDRES_RESET_FIELD 7 +#define STV090x_WIDTH_Px_DMDRES_RESET_FIELD 1 + +#define STV090x_Px_DMDRESADR(__x) (0xF4C7 - (__x - 1) * 0x200) +#define STV090x_P1_DMDRESADR STV090x_Px_DMDRESADR(1) +#define STV090x_P2_DMDRESADR STV090x_Px_DMDRESADR(2) +#define STV090x_OFFST_Px_DMDRES_RESNBR_FIELD 0 +#define STV090x_WIDTH_Px_DMDRES_RESNBR_FIELD 4 + +#define STV090x_Px_DMDRESDATAy(__x, __y) (0xF4C8 - (__x - 1) * 0x200 + (7 - __y)) +#define STV090x_P1_DMDRESDATA0 STV090x_Px_DMDRESDATAy(1, 0) +#define STV090x_P1_DMDRESDATA1 STV090x_Px_DMDRESDATAy(1, 1) +#define STV090x_P1_DMDRESDATA2 STV090x_Px_DMDRESDATAy(1, 2) +#define STV090x_P1_DMDRESDATA3 STV090x_Px_DMDRESDATAy(1, 3) +#define STV090x_P1_DMDRESDATA4 STV090x_Px_DMDRESDATAy(1, 4) +#define STV090x_P1_DMDRESDATA5 STV090x_Px_DMDRESDATAy(1, 5) +#define STV090x_P1_DMDRESDATA6 STV090x_Px_DMDRESDATAy(1, 6) +#define STV090x_P1_DMDRESDATA7 STV090x_Px_DMDRESDATAy(1, 7) +#define STV090x_P2_DMDRESDATA0 STV090x_Px_DMDRESDATAy(2, 0) +#define STV090x_P2_DMDRESDATA1 STV090x_Px_DMDRESDATAy(2, 1) +#define STV090x_P2_DMDRESDATA2 STV090x_Px_DMDRESDATAy(2, 2) +#define STV090x_P2_DMDRESDATA3 STV090x_Px_DMDRESDATAy(2, 3) +#define STV090x_P2_DMDRESDATA4 STV090x_Px_DMDRESDATAy(2, 4) +#define STV090x_P2_DMDRESDATA5 STV090x_Px_DMDRESDATAy(2, 5) +#define STV090x_P2_DMDRESDATA6 STV090x_Px_DMDRESDATAy(2, 6) +#define STV090x_P2_DMDRESDATA7 STV090x_Px_DMDRESDATAy(2, 7) +#define STV090x_OFFST_Px_DMDRES_DATA_FIELD 0 +#define STV090x_WIDTH_Px_DMDRES_DATA_FIELD 8 + +#define STV090x_Px_FFEIy(__x, __y) (0xf4d0 - (__x - 1) * 0x200 + 0x2 * (__y - 1)) +#define STV090x_P1_FFEI1 STV090x_Px_FFEIy(1, 1) +#define STV090x_P1_FFEI2 STV090x_Px_FFEIy(1, 2) +#define STV090x_P1_FFEI3 STV090x_Px_FFEIy(1, 3) +#define STV090x_P1_FFEI4 STV090x_Px_FFEIy(1, 4) +#define STV090x_P2_FFEI1 STV090x_Px_FFEIy(2, 1) +#define STV090x_P2_FFEI2 STV090x_Px_FFEIy(2, 2) +#define STV090x_P2_FFEI3 STV090x_Px_FFEIy(2, 3) +#define STV090x_P2_FFEI4 STV090x_Px_FFEIy(2, 4) +#define STV090x_OFFST_Px_FFE_ACCIy_FIELD 0 +#define STV090x_WIDTH_Px_FFE_ACCIy_FIELD 8 + +#define STV090x_Px_FFEQy(__x, __y) (0xf4d1 - (__x - 1) * 0x200 + 0x2 * (__y - 1)) +#define STV090x_P1_FFEQ1 STV090x_Px_FFEQy(1, 1) +#define STV090x_P1_FFEQ2 STV090x_Px_FFEQy(1, 2) +#define STV090x_P1_FFEQ3 STV090x_Px_FFEQy(1, 3) +#define STV090x_P1_FFEQ4 STV090x_Px_FFEQy(1, 4) +#define STV090x_P2_FFEQ1 STV090x_Px_FFEQy(2, 1) +#define STV090x_P2_FFEQ2 STV090x_Px_FFEQy(2, 2) +#define STV090x_P2_FFEQ3 STV090x_Px_FFEQy(2, 3) +#define STV090x_P2_FFEQ4 STV090x_Px_FFEQy(2, 4) +#define STV090x_OFFST_Px_FFE_ACCQy_FIELD 0 +#define STV090x_WIDTH_Px_FFE_ACCQy_FIELD 8 + +#define STV090x_Px_FFECFG(__x) (0xf4d8 - (__x - 1) * 0x200) +#define STV090x_P1_FFECFG STV090x_Px_FFECFG(1) +#define STV090x_P2_FFECFG STV090x_Px_FFECFG(2) +#define STV090x_OFFST_Px_EQUALFFE_ON_FIELD 6 +#define STV090x_WIDTH_Px_EQUALFFE_ON_FIELD 1 + +#define STV090x_Px_SMAPCOEF7(__x) (0xf500 - (__x - 1) * 0x200) +#define STV090x_P1_SMAPCOEF7 STV090x_Px_SMAPCOEF7(1) +#define STV090x_P2_SMAPCOEF7 STV090x_Px_SMAPCOEF7(2) +#define STV090x_OFFST_Px_DIS_QSCALE_FIELD 7 +#define STV090x_WIDTH_Px_DIS_QSCALE_FIELD 1 +#define STV090x_OFFST_Px_SMAPCOEF_Q_LLR12_FIELD 0 +#define STV090x_WIDTH_Px_SMAPCOEF_Q_LLR12_FIELD 7 + +#define STV090x_Px_SMAPCOEF6(__x) (0xf501 - (__x - 1) * 0x200) +#define STV090x_P1_SMAPCOEF6 STV090x_Px_SMAPCOEF6(1) +#define STV090x_P2_SMAPCOEF6 STV090x_Px_SMAPCOEF6(2) +#define STV090x_OFFST_Px_ADJ_8PSKLLR1_FIELD 2 +#define STV090x_WIDTH_Px_ADJ_8PSKLLR1_FIELD 1 +#define STV090x_OFFST_Px_OLD_8PSKLLR1_FIELD 1 +#define STV090x_WIDTH_Px_OLD_8PSKLLR1_FIELD 1 +#define STV090x_OFFST_Px_DIS_AB8PSK_FIELD 0 +#define STV090x_WIDTH_Px_DIS_AB8PSK_FIELD 1 + +#define STV090x_Px_SMAPCOEF5(__x) (0xf502 - (__x - 1) * 0x200) +#define STV090x_P1_SMAPCOEF5 STV090x_Px_SMAPCOEF5(1) +#define STV090x_P2_SMAPCOEF5 STV090x_Px_SMAPCOEF5(2) +#define STV090x_OFFST_Px_DIS_8SCALE_FIELD 7 +#define STV090x_WIDTH_Px_DIS_8SCALE_FIELD 1 +#define STV090x_OFFST_Px_SMAPCOEF_8P_LLR23_FIELD 0 +#define STV090x_WIDTH_Px_SMAPCOEF_8P_LLR23_FIELD 7 + +#define STV090x_Px_DMDPLHSTAT(__x) (0xF520 - (__x - 1) * 0x200) +#define STV090x_P1_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(1) +#define STV090x_P2_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(2) +#define STV090x_OFFST_Px_PLH_STATISTIC_FIELD 0 +#define STV090x_WIDTH_Px_PLH_STATISTIC_FIELD 8 + +#define STV090x_Px_LOCKTIMEy(__x, __y) (0xF525 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_LOCKTIME0 STV090x_Px_LOCKTIMEy(1, 0) +#define STV090x_P1_LOCKTIME1 STV090x_Px_LOCKTIMEy(1, 1) +#define STV090x_P1_LOCKTIME2 STV090x_Px_LOCKTIMEy(1, 2) +#define STV090x_P1_LOCKTIME3 STV090x_Px_LOCKTIMEy(1, 3) +#define STV090x_P2_LOCKTIME0 STV090x_Px_LOCKTIMEy(2, 0) +#define STV090x_P2_LOCKTIME1 STV090x_Px_LOCKTIMEy(2, 1) +#define STV090x_P2_LOCKTIME2 STV090x_Px_LOCKTIMEy(2, 2) +#define STV090x_P2_LOCKTIME3 STV090x_Px_LOCKTIMEy(2, 3) +#define STV090x_OFFST_Px_DEMOD_LOCKTIME_FIELD 0 +#define STV090x_WIDTH_Px_DEMOD_LOCKTIME_FIELD 8 + +#define STV090x_Px_TNRCFG(__x) (0xf4e0 - (__x - 1) * 0x200) /* check */ +#define STV090x_P1_TNRCFG STV090x_Px_TNRCFG(1) +#define STV090x_P2_TNRCFG STV090x_Px_TNRCFG(2) + +#define STV090x_Px_TNRCFG2(__x) (0xf4e1 - (__x - 1) * 0x200) +#define STV090x_P1_TNRCFG2 STV090x_Px_TNRCFG2(1) +#define STV090x_P2_TNRCFG2 STV090x_Px_TNRCFG2(2) +#define STV090x_OFFST_Px_TUN_IQSWAP_FIELD 7 +#define STV090x_WIDTH_Px_TUN_IQSWAP_FIELD 1 + +#define STV090x_Px_VITSCALE(__x) (0xf532 - (__x - 1) * 0x200) +#define STV090x_P1_VITSCALE STV090x_Px_VITSCALE(1) +#define STV090x_P2_VITSCALE STV090x_Px_VITSCALE(2) +#define STV090x_OFFST_Px_NVTH_NOSRANGE_FIELD 7 +#define STV090x_WIDTH_Px_NVTH_NOSRANGE_FIELD 1 +#define STV090x_OFFST_Px_VERROR_MAXMODE_FIELD 6 +#define STV090x_WIDTH_Px_VERROR_MAXMODE_FIELD 1 +#define STV090x_OFFST_Px_NSLOWSN_LOCKED_FIELD 3 +#define STV090x_WIDTH_Px_NSLOWSN_LOCKED_FIELD 1 +#define STV090x_OFFST_Px_DIS_RSFLOCK_FIELD 1 +#define STV090x_WIDTH_Px_DIS_RSFLOCK_FIELD 1 + +#define STV090x_Px_FECM(__x) (0xf533 - (__x - 1) * 0x200) +#define STV090x_P1_FECM STV090x_Px_FECM(1) +#define STV090x_P2_FECM STV090x_Px_FECM(2) +#define STV090x_OFFST_Px_DSS_DVB_FIELD 7 +#define STV090x_WIDTH_Px_DSS_DVB_FIELD 1 +#define STV090x_OFFST_Px_DSS_SRCH_FIELD 4 +#define STV090x_WIDTH_Px_DSS_SRCH_FIELD 1 +#define STV090x_OFFST_Px_SYNCVIT_FIELD 1 +#define STV090x_WIDTH_Px_SYNCVIT_FIELD 1 +#define STV090x_OFFST_Px_IQINV_FIELD 0 +#define STV090x_WIDTH_Px_IQINV_FIELD 1 + +#define STV090x_Px_VTH12(__x) (0xf534 - (__x - 1) * 0x200) +#define STV090x_P1_VTH12 STV090x_Px_VTH12(1) +#define STV090x_P2_VTH12 STV090x_Px_VTH12(2) +#define STV090x_OFFST_Px_VTH12_FIELD 0 +#define STV090x_WIDTH_Px_VTH12_FIELD 8 + +#define STV090x_Px_VTH23(__x) (0xf535 - (__x - 1) * 0x200) +#define STV090x_P1_VTH23 STV090x_Px_VTH23(1) +#define STV090x_P2_VTH23 STV090x_Px_VTH23(2) +#define STV090x_OFFST_Px_VTH23_FIELD 0 +#define STV090x_WIDTH_Px_VTH23_FIELD 8 + +#define STV090x_Px_VTH34(__x) (0xf536 - (__x - 1) * 0x200) +#define STV090x_P1_VTH34 STV090x_Px_VTH34(1) +#define STV090x_P2_VTH34 STV090x_Px_VTH34(2) +#define STV090x_OFFST_Px_VTH34_FIELD 0 +#define STV090x_WIDTH_Px_VTH34_FIELD 8 + +#define STV090x_Px_VTH56(__x) (0xf537 - (__x - 1) * 0x200) +#define STV090x_P1_VTH56 STV090x_Px_VTH56(1) +#define STV090x_P2_VTH56 STV090x_Px_VTH56(2) +#define STV090x_OFFST_Px_VTH56_FIELD 0 +#define STV090x_WIDTH_Px_VTH56_FIELD 8 + +#define STV090x_Px_VTH67(__x) (0xf538 - (__x - 1) * 0x200) +#define STV090x_P1_VTH67 STV090x_Px_VTH67(1) +#define STV090x_P2_VTH67 STV090x_Px_VTH67(2) +#define STV090x_OFFST_Px_VTH67_FIELD 0 +#define STV090x_WIDTH_Px_VTH67_FIELD 8 + +#define STV090x_Px_VTH78(__x) (0xf539 - (__x - 1) * 0x200) +#define STV090x_P1_VTH78 STV090x_Px_VTH78(1) +#define STV090x_P2_VTH78 STV090x_Px_VTH78(2) +#define STV090x_OFFST_Px_VTH78_FIELD 0 +#define STV090x_WIDTH_Px_VTH78_FIELD 8 + +#define STV090x_Px_VITCURPUN(__x) (0xf53a - (__x - 1) * 0x200) +#define STV090x_P1_VITCURPUN STV090x_Px_VITCURPUN(1) +#define STV090x_P2_VITCURPUN STV090x_Px_VITCURPUN(2) +#define STV090x_OFFST_Px_VIT_CURPUN_FIELD 0 +#define STV090x_WIDTH_Px_VIT_CURPUN_FIELD 5 + +#define STV090x_Px_VERROR(__x) (0xf53b - (__x - 1) * 0x200) +#define STV090x_P1_VERROR STV090x_Px_VERROR(1) +#define STV090x_P2_VERROR STV090x_Px_VERROR(2) +#define STV090x_OFFST_Px_REGERR_VIT_FIELD 0 +#define STV090x_WIDTH_Px_REGERR_VIT_FIELD 8 + +#define STV090x_Px_PRVIT(__x) (0xf53c - (__x - 1) * 0x200) +#define STV090x_P1_PRVIT STV090x_Px_PRVIT(1) +#define STV090x_P2_PRVIT STV090x_Px_PRVIT(2) +#define STV090x_OFFST_Px_DIS_VTHLOCK_FIELD 6 +#define STV090x_WIDTH_Px_DIS_VTHLOCK_FIELD 1 +#define STV090x_OFFST_Px_E7_8VIT_FIELD 5 +#define STV090x_WIDTH_Px_E7_8VIT_FIELD 1 +#define STV090x_OFFST_Px_E6_7VIT_FIELD 4 +#define STV090x_WIDTH_Px_E6_7VIT_FIELD 1 +#define STV090x_OFFST_Px_E5_6VIT_FIELD 3 +#define STV090x_WIDTH_Px_E5_6VIT_FIELD 1 +#define STV090x_OFFST_Px_E3_4VIT_FIELD 2 +#define STV090x_WIDTH_Px_E3_4VIT_FIELD 1 +#define STV090x_OFFST_Px_E2_3VIT_FIELD 1 +#define STV090x_WIDTH_Px_E2_3VIT_FIELD 1 +#define STV090x_OFFST_Px_E1_2VIT_FIELD 0 +#define STV090x_WIDTH_Px_E1_2VIT_FIELD 1 + +#define STV090x_Px_VAVSRVIT(__x) (0xf53d - (__x - 1) * 0x200) +#define STV090x_P1_VAVSRVIT STV090x_Px_VAVSRVIT(1) +#define STV090x_P2_VAVSRVIT STV090x_Px_VAVSRVIT(2) +#define STV090x_OFFST_Px_SNVIT_FIELD 4 +#define STV090x_WIDTH_Px_SNVIT_FIELD 2 +#define STV090x_OFFST_Px_TOVVIT_FIELD 2 +#define STV090x_WIDTH_Px_TOVVIT_FIELD 2 +#define STV090x_OFFST_Px_HYPVIT_FIELD 0 +#define STV090x_WIDTH_Px_HYPVIT_FIELD 2 + +#define STV090x_Px_VSTATUSVIT(__x) (0xf53e - (__x - 1) * 0x200) +#define STV090x_P1_VSTATUSVIT STV090x_Px_VSTATUSVIT(1) +#define STV090x_P2_VSTATUSVIT STV090x_Px_VSTATUSVIT(2) +#define STV090x_OFFST_Px_PRFVIT_FIELD 4 +#define STV090x_WIDTH_Px_PRFVIT_FIELD 1 +#define STV090x_OFFST_Px_LOCKEDVIT_FIELD 3 +#define STV090x_WIDTH_Px_LOCKEDVIT_FIELD 1 + +#define STV090x_Px_VTHINUSE(__x) (0xf53f - (__x - 1) * 0x200) +#define STV090x_P1_VTHINUSE STV090x_Px_VTHINUSE(1) +#define STV090x_P2_VTHINUSE STV090x_Px_VTHINUSE(2) +#define STV090x_OFFST_Px_VIT_INUSE_FIELD 0 +#define STV090x_WIDTH_Px_VIT_INUSE_FIELD 8 + +#define STV090x_Px_KDIV12(__x) (0xf540 - (__x - 1) * 0x200) +#define STV090x_P1_KDIV12 STV090x_Px_KDIV12(1) +#define STV090x_P2_KDIV12 STV090x_Px_KDIV12(2) +#define STV090x_OFFST_Px_K_DIVIDER_12_FIELD 0 +#define STV090x_WIDTH_Px_K_DIVIDER_12_FIELD 7 + +#define STV090x_Px_KDIV23(__x) (0xf541 - (__x - 1) * 0x200) +#define STV090x_P1_KDIV23 STV090x_Px_KDIV23(1) +#define STV090x_P2_KDIV23 STV090x_Px_KDIV23(2) +#define STV090x_OFFST_Px_K_DIVIDER_23_FIELD 0 +#define STV090x_WIDTH_Px_K_DIVIDER_23_FIELD 7 + +#define STV090x_Px_KDIV34(__x) (0xf542 - (__x - 1) * 0x200) +#define STV090x_P1_KDIV34 STV090x_Px_KDIV34(1) +#define STV090x_P2_KDIV34 STV090x_Px_KDIV34(2) +#define STV090x_OFFST_Px_K_DIVIDER_34_FIELD 0 +#define STV090x_WIDTH_Px_K_DIVIDER_34_FIELD 7 + +#define STV090x_Px_KDIV56(__x) (0xf543 - (__x - 1) * 0x200) +#define STV090x_P1_KDIV56 STV090x_Px_KDIV56(1) +#define STV090x_P2_KDIV56 STV090x_Px_KDIV56(2) +#define STV090x_OFFST_Px_K_DIVIDER_56_FIELD 0 +#define STV090x_WIDTH_Px_K_DIVIDER_56_FIELD 7 + +#define STV090x_Px_KDIV67(__x) (0xf544 - (__x - 1) * 0x200) +#define STV090x_P1_KDIV67 STV090x_Px_KDIV67(1) +#define STV090x_P2_KDIV67 STV090x_Px_KDIV67(2) +#define STV090x_OFFST_Px_K_DIVIDER_67_FIELD 0 +#define STV090x_WIDTH_Px_K_DIVIDER_67_FIELD 7 + +#define STV090x_Px_KDIV78(__x) (0xf545 - (__x - 1) * 0x200) +#define STV090x_P1_KDIV78 STV090x_Px_KDIV78(1) +#define STV090x_P2_KDIV78 STV090x_Px_KDIV78(2) +#define STV090x_OFFST_Px_K_DIVIDER_78_FIELD 0 +#define STV090x_WIDTH_Px_K_DIVIDER_78_FIELD 7 + +#define STV090x_Px_PDELCTRL1(__x) (0xf550 - (__x - 1) * 0x200) +#define STV090x_P1_PDELCTRL1 STV090x_Px_PDELCTRL1(1) +#define STV090x_P2_PDELCTRL1 STV090x_Px_PDELCTRL1(2) +#define STV090x_OFFST_Px_INV_MISMASK_FIELD 7 +#define STV090x_WIDTH_Px_INV_MISMASK_FIELD 1 +#define STV090x_OFFST_Px_FILTER_EN_FIELD 5 +#define STV090x_WIDTH_Px_FILTER_EN_FIELD 1 +#define STV090x_OFFST_Px_EN_MIS00_FIELD 1 +#define STV090x_WIDTH_Px_EN_MIS00_FIELD 1 +#define STV090x_OFFST_Px_ALGOSWRST_FIELD 0 +#define STV090x_WIDTH_Px_ALGOSWRST_FIELD 1 + +#define STV090x_Px_PDELCTRL2(__x) (0xf551 - (__x - 1) * 0x200) +#define STV090x_P1_PDELCTRL2 STV090x_Px_PDELCTRL2(1) +#define STV090x_P2_PDELCTRL2 STV090x_Px_PDELCTRL2(2) +#define STV090x_OFFST_Px_FORCE_CONTINUOUS 7 +#define STV090x_WIDTH_Px_FORCE_CONTINUOUS 1 +#define STV090x_OFFST_Px_RESET_UPKO_COUNT 6 +#define STV090x_WIDTH_Px_RESET_UPKO_COUNT 1 +#define STV090x_OFFST_Px_USER_PKTDELIN_NB 5 +#define STV090x_WIDTH_Px_USER_PKTDELIN_NB 1 +#define STV090x_OFFST_Px_FORCE_LOCKED 4 +#define STV090x_WIDTH_Px_FORCE_LOCKED 1 +#define STV090x_OFFST_Px_DATA_UNBBSCRAM 3 +#define STV090x_WIDTH_Px_DATA_UNBBSCRAM 1 +#define STV090x_OFFST_Px_FORCE_LONGPACKET 2 +#define STV090x_WIDTH_Px_FORCE_LONGPACKET 1 +#define STV090x_OFFST_Px_FRAME_MODE_FIELD 1 +#define STV090x_WIDTH_Px_FRAME_MODE_FIELD 1 + +#define STV090x_Px_HYSTTHRESH(__x) (0xf554 - (__x - 1) * 0x200) +#define STV090x_P1_HYSTTHRESH STV090x_Px_HYSTTHRESH(1) +#define STV090x_P2_HYSTTHRESH STV090x_Px_HYSTTHRESH(2) +#define STV090x_OFFST_Px_UNLCK_THRESH_FIELD 4 +#define STV090x_WIDTH_Px_UNLCK_THRESH_FIELD 4 +#define STV090x_OFFST_Px_DELIN_LCK_THRESH_FIELD 0 +#define STV090x_WIDTH_Px_DELIN_LCK_THRESH_FIELD 4 + +#define STV090x_Px_ISIENTRY(__x) (0xf55e - (__x - 1) * 0x200) +#define STV090x_P1_ISIENTRY STV090x_Px_ISIENTRY(1) +#define STV090x_P2_ISIENTRY STV090x_Px_ISIENTRY(2) +#define STV090x_OFFST_Px_ISI_ENTRY_FIELD 0 +#define STV090x_WIDTH_Px_ISI_ENTRY_FIELD 8 + +#define STV090x_Px_ISIBITENA(__x) (0xf55f - (__x - 1) * 0x200) +#define STV090x_P1_ISIBITENA STV090x_Px_ISIBITENA(1) +#define STV090x_P2_ISIBITENA STV090x_Px_ISIBITENA(2) +#define STV090x_OFFST_Px_ISI_BIT_EN_FIELD 0 +#define STV090x_WIDTH_Px_ISI_BIT_EN_FIELD 8 + +#define STV090x_Px_MATSTRy(__x, __y) (0xf561 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_MATSTR0 STV090x_Px_MATSTRy(1, 0) +#define STV090x_P1_MATSTR1 STV090x_Px_MATSTRy(1, 1) +#define STV090x_P2_MATSTR0 STV090x_Px_MATSTRy(2, 0) +#define STV090x_P2_MATSTR1 STV090x_Px_MATSTRy(2, 1) +#define STV090x_OFFST_Px_MATYPE_CURRENT_FIELD 0 +#define STV090x_WIDTH_Px_MATYPE_CURRENT_FIELD 8 + +#define STV090x_Px_UPLSTRy(__x, __y) (0xf563 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_UPLSTR0 STV090x_Px_UPLSTRy(1, 0) +#define STV090x_P1_UPLSTR1 STV090x_Px_UPLSTRy(1, 1) +#define STV090x_P2_UPLSTR0 STV090x_Px_UPLSTRy(2, 0) +#define STV090x_P2_UPLSTR1 STV090x_Px_UPLSTRy(2, 1) +#define STV090x_OFFST_Px_UPL_CURRENT_FIELD 0 +#define STV090x_WIDTH_Px_UPL_CURRENT_FIELD 8 + +#define STV090x_Px_DFLSTRy(__x, __y) (0xf565 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_DFLSTR0 STV090x_Px_DFLSTRy(1, 0) +#define STV090x_P1_DFLSTR1 STV090x_Px_DFLSTRy(1, 1) +#define STV090x_P2_DFLSTR0 STV090x_Px_DFLSTRy(2, 0) +#define STV090x_P2_DFLSTR1 STV090x_Px_DFLSTRy(2, 1) +#define STV090x_OFFST_Px_DFL_CURRENT_FIELD 0 +#define STV090x_WIDTH_Px_DFL_CURRENT_FIELD 8 + +#define STV090x_Px_SYNCSTR(__x) (0xf566 - (__x - 1) * 0x200) +#define STV090x_P1_SYNCSTR STV090x_Px_SYNCSTR(1) +#define STV090x_P2_SYNCSTR STV090x_Px_SYNCSTR(2) +#define STV090x_OFFST_Px_SYNC_CURRENT_FIELD 0 +#define STV090x_WIDTH_Px_SYNC_CURRENT_FIELD 8 + +#define STV090x_Px_SYNCDSTRy(__x, __y) (0xf568 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_SYNCDSTR0 STV090x_Px_SYNCDSTRy(1, 0) +#define STV090x_P1_SYNCDSTR1 STV090x_Px_SYNCDSTRy(1, 1) +#define STV090x_P2_SYNCDSTR0 STV090x_Px_SYNCDSTRy(2, 0) +#define STV090x_P2_SYNCDSTR1 STV090x_Px_SYNCDSTRy(2, 1) +#define STV090x_OFFST_Px_SYNCD_CURRENT_FIELD 0 +#define STV090x_WIDTH_Px_SYNCD_CURRENT_FIELD 8 + +#define STV090x_Px_PDELSTATUS1(__x) (0xf569 - (__x - 1) * 0x200) +#define STV090x_P1_PDELSTATUS1 STV090x_Px_PDELSTATUS1(1) +#define STV090x_P2_PDELSTATUS1 STV090x_Px_PDELSTATUS1(2) +#define STV090x_OFFST_Px_PKTDELIN_LOCK_FIELD 1 +#define STV090x_WIDTH_Px_PKTDELIN_LOCK_FIELD 1 +#define STV090x_OFFST_Px_FIRST_LOCK_FIELD 0 +#define STV090x_WIDTH_Px_FIRST_LOCK_FIELD 1 + +#define STV090x_Px_PDELSTATUS2(__x) (0xf56a - (__x - 1) * 0x200) +#define STV090x_P1_PDELSTATUS2 STV090x_Px_PDELSTATUS2(1) +#define STV090x_P2_PDELSTATUS2 STV090x_Px_PDELSTATUS2(2) +#define STV090x_OFFST_Px_FRAME_MODCOD_FIELD 2 +#define STV090x_WIDTH_Px_FRAME_MODCOD_FIELD 5 +#define STV090x_OFFST_Px_FRAME_TYPE_FIELD 0 +#define STV090x_WIDTH_Px_FRAME_TYPE_FIELD 2 + +#define STV090x_Px_BBFCRCKO1(__x) (0xf56b - (__x - 1) * 0x200) +#define STV090x_P1_BBFCRCKO1 STV090x_Px_BBFCRCKO1(1) +#define STV090x_P2_BBFCRCKO1 STV090x_Px_BBFCRCKO1(2) +#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD 0 +#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD 8 + +#define STV090x_Px_BBFCRCKO0(__x) (0xf56c - (__x - 1) * 0x200) +#define STV090x_P1_BBFCRCKO0 STV090x_Px_BBFCRCKO0(1) +#define STV090x_P2_BBFCRCKO0 STV090x_Px_BBFCRCKO0(2) +#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD 0 +#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD 8 + +#define STV090x_Px_UPCRCKO1(__x) (0xf56d - (__x - 1) * 0x200) +#define STV090x_P1_UPCRCKO1 STV090x_Px_UPCRCKO1(1) +#define STV090x_P2_UPCRCKO1 STV090x_Px_UPCRCKO1(2) +#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD 0 +#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD 8 + +#define STV090x_Px_UPCRCKO0(__x) (0xf56e - (__x - 1) * 0x200) +#define STV090x_P1_UPCRCKO0 STV090x_Px_UPCRCKO0(1) +#define STV090x_P2_UPCRCKO0 STV090x_Px_UPCRCKO0(2) +#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD 0 +#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD 8 + +#define STV090x_NBITER_NFx(__x) (0xFA03 + (__x - 4) * 0x1) +#define STV090x_NBITER_NF4 STV090x_NBITER_NFx(4) +#define STV090x_NBITER_NF5 STV090x_NBITER_NFx(5) +#define STV090x_NBITER_NF6 STV090x_NBITER_NFx(6) +#define STV090x_NBITER_NF7 STV090x_NBITER_NFx(7) +#define STV090x_NBITER_NF8 STV090x_NBITER_NFx(8) +#define STV090x_NBITER_NF9 STV090x_NBITER_NFx(9) +#define STV090x_NBITER_NF10 STV090x_NBITER_NFx(10) +#define STV090x_NBITER_NF11 STV090x_NBITER_NFx(11) +#define STV090x_NBITER_NF12 STV090x_NBITER_NFx(12) +#define STV090x_NBITER_NF13 STV090x_NBITER_NFx(13) +#define STV090x_NBITER_NF14 STV090x_NBITER_NFx(14) +#define STV090x_NBITER_NF15 STV090x_NBITER_NFx(15) +#define STV090x_NBITER_NF16 STV090x_NBITER_NFx(16) +#define STV090x_NBITER_NF17 STV090x_NBITER_NFx(17) + +#define STV090x_NBITERNOERR 0xFA3F +#define STV090x_OFFST_NBITER_STOP_CRIT_FIELD 0 +#define STV090x_WIDTH_NBITER_STOP_CRIT_FIELD 4 + +#define STV090x_GAINLLR_NFx(__x) (0xFA43 + (__x - 4) * 0x1) +#define STV090x_GAINLLR_NF4 STV090x_GAINLLR_NFx(4) +#define STV090x_OFFST_GAINLLR_NF_QP_1_2_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_1_2_FIELD 7 + +#define STV090x_GAINLLR_NF5 STV090x_GAINLLR_NFx(5) +#define STV090x_OFFST_GAINLLR_NF_QP_3_5_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_3_5_FIELD 7 + +#define STV090x_GAINLLR_NF6 STV090x_GAINLLR_NFx(6) +#define STV090x_OFFST_GAINLLR_NF_QP_2_3_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_2_3_FIELD 7 + +#define STV090x_GAINLLR_NF7 STV090x_GAINLLR_NFx(7) +#define STV090x_OFFST_GAINLLR_NF_QP_3_4_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_3_4_FIELD 7 + +#define STV090x_GAINLLR_NF8 STV090x_GAINLLR_NFx(8) +#define STV090x_OFFST_GAINLLR_NF_QP_4_5_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_4_5_FIELD 7 + +#define STV090x_GAINLLR_NF9 STV090x_GAINLLR_NFx(9) +#define STV090x_OFFST_GAINLLR_NF_QP_5_6_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_5_6_FIELD 7 + +#define STV090x_GAINLLR_NF10 STV090x_GAINLLR_NFx(10) +#define STV090x_OFFST_GAINLLR_NF_QP_8_9_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_8_9_FIELD 7 + +#define STV090x_GAINLLR_NF11 STV090x_GAINLLR_NFx(11) +#define STV090x_OFFST_GAINLLR_NF_QP_9_10_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_QP_9_10_FIELD 7 + +#define STV090x_GAINLLR_NF12 STV090x_GAINLLR_NFx(12) +#define STV090x_OFFST_GAINLLR_NF_8P_3_5_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_8P_3_5_FIELD 7 + +#define STV090x_GAINLLR_NF13 STV090x_GAINLLR_NFx(13) +#define STV090x_OFFST_GAINLLR_NF_8P_2_3_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_8P_2_3_FIELD 7 + +#define STV090x_GAINLLR_NF14 STV090x_GAINLLR_NFx(14) +#define STV090x_OFFST_GAINLLR_NF_8P_3_4_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_8P_3_4_FIELD 7 + +#define STV090x_GAINLLR_NF15 STV090x_GAINLLR_NFx(15) +#define STV090x_OFFST_GAINLLR_NF_8P_5_6_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_8P_5_6_FIELD 7 + +#define STV090x_GAINLLR_NF16 STV090x_GAINLLR_NFx(16) +#define STV090x_OFFST_GAINLLR_NF_8P_8_9_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_8P_8_9_FIELD 7 + +#define STV090x_GAINLLR_NF17 STV090x_GAINLLR_NFx(17) +#define STV090x_OFFST_GAINLLR_NF_8P_9_10_FIELD 0 +#define STV090x_WIDTH_GAINLLR_NF_8P_9_10_FIELD 7 + +#define STV090x_GENCFG 0xFA86 +#define STV090x_OFFST_BROADCAST_FIELD 4 +#define STV090x_WIDTH_BROADCAST_FIELD 1 +#define STV090x_OFFST_PRIORITY_FIELD 1 +#define STV090x_WIDTH_PRIORITY_FIELD 1 +#define STV090x_OFFST_DDEMOD_FIELD 0 +#define STV090x_WIDTH_DDEMOD_FIELD 1 + +#define STV090x_LDPCERRx(__x) (0xFA97 - (__x * 0x1)) +#define STV090x_LDPCERR0 STV090x_LDPCERRx(0) +#define STV090x_LDPCERR1 STV090x_LDPCERRx(1) +#define STV090x_OFFST_Px_LDPC_ERRORS_COUNTER_FIELD 0 +#define STV090x_WIDTH_Px_LDPC_ERRORS_COUNTER_FIELD 8 + +#define STV090x_BCHERR 0xFA98 +#define STV090x_OFFST_Px_ERRORFLAG_FIELD 4 +#define STV090x_WIDTH_Px_ERRORFLAG_FIELD 1 +#define STV090x_OFFST_Px_BCH_ERRORS_COUNTER_FIELD 0 +#define STV090x_WIDTH_Px_BCH_ERRORS_COUNTER_FIELD 4 + +#define STV090x_Px_TSSTATEM(__x) (0xF570 - (__x - 1) * 0x200) +#define STV090x_P1_TSSTATEM STV090x_Px_TSSTATEM(1) +#define STV090x_P2_TSSTATEM STV090x_Px_TSSTATEM(2) +#define STV090x_OFFST_Px_TSDIL_ON_FIELD 7 +#define STV090x_WIDTH_Px_TSDIL_ON_FIELD 1 +#define STV090x_OFFST_Px_TSRS_ON_FIELD 5 +#define STV090x_WIDTH_Px_TSRS_ON_FIELD 1 + +#define STV090x_Px_TSCFGH(__x) (0xF572 - (__x - 1) * 0x200) +#define STV090x_P1_TSCFGH STV090x_Px_TSCFGH(1) +#define STV090x_P2_TSCFGH STV090x_Px_TSCFGH(2) +#define STV090x_OFFST_Px_TSFIFO_DVBCI_FIELD 7 +#define STV090x_WIDTH_Px_TSFIFO_DVBCI_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_SERIAL_FIELD 6 +#define STV090x_WIDTH_Px_TSFIFO_SERIAL_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_TEIUPDATE_FIELD 5 +#define STV090x_WIDTH_Px_TSFIFO_TEIUPDATE_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_DUTY50_FIELD 4 +#define STV090x_WIDTH_Px_TSFIFO_DUTY50_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_HSGNLOUT_FIELD 3 +#define STV090x_WIDTH_Px_TSFIFO_HSGNLOUT_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_ERRORMODE_FIELD 1 +#define STV090x_WIDTH_Px_TSFIFO_ERRORMODE_FIELD 2 +#define STV090x_OFFST_Px_RST_HWARE_FIELD 0 +#define STV090x_WIDTH_Px_RST_HWARE_FIELD 1 + +#define STV090x_Px_TSCFGM(__x) (0xF573 - (__x - 1) * 0x200) +#define STV090x_P1_TSCFGM STV090x_Px_TSCFGM(1) +#define STV090x_P2_TSCFGM STV090x_Px_TSCFGM(2) +#define STV090x_OFFST_Px_TSFIFO_MANSPEED_FIELD 6 +#define STV090x_WIDTH_Px_TSFIFO_MANSPEED_FIELD 2 +#define STV090x_OFFST_Px_TSFIFO_PERMDATA_FIELD 5 +#define STV090x_WIDTH_Px_TSFIFO_PERMDATA_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_INVDATA_FIELD 0 +#define STV090x_WIDTH_Px_TSFIFO_INVDATA_FIELD 1 + +#define STV090x_Px_TSCFGL(__x) (0xF574 - (__x - 1) * 0x200) +#define STV090x_P1_TSCFGL STV090x_Px_TSCFGL(1) +#define STV090x_P2_TSCFGL STV090x_Px_TSCFGL(2) +#define STV090x_OFFST_Px_TSFIFO_BCLKDEL1CK_FIELD 6 +#define STV090x_WIDTH_Px_TSFIFO_BCLKDEL1CK_FIELD 2 +#define STV090x_OFFST_Px_BCHERROR_MODE_FIELD 4 +#define STV090x_WIDTH_Px_BCHERROR_MODE_FIELD 2 +#define STV090x_OFFST_Px_TSFIFO_NSGNL2DATA_FIELD 3 +#define STV090x_WIDTH_Px_TSFIFO_NSGNL2DATA_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_EMBINDVB_FIELD 2 +#define STV090x_WIDTH_Px_TSFIFO_EMBINDVB_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_DPUNACT_FIELD 1 +#define STV090x_WIDTH_Px_TSFIFO_DPUNACT_FIELD 1 + +#define STV090x_Px_TSINSDELH(__x) (0xF576 - (__x - 1) * 0x200) +#define STV090x_P1_TSINSDELH STV090x_Px_TSINSDELH(1) +#define STV090x_P2_TSINSDELH STV090x_Px_TSINSDELH(2) +#define STV090x_OFFST_Px_TSDEL_SYNCBYTE_FIELD 7 +#define STV090x_WIDTH_Px_TSDEL_SYNCBYTE_FIELD 1 +#define STV090x_OFFST_Px_TSDEL_XXHEADER_FIELD 6 +#define STV090x_WIDTH_Px_TSDEL_XXHEADER_FIELD 1 + +#define STV090x_Px_TSSPEED(__x) (0xF580 - (__x - 1) * 0x200) +#define STV090x_P1_TSSPEED STV090x_Px_TSSPEED(1) +#define STV090x_P2_TSSPEED STV090x_Px_TSSPEED(2) +#define STV090x_OFFST_Px_TSFIFO_OUTSPEED_FIELD 0 +#define STV090x_WIDTH_Px_TSFIFO_OUTSPEED_FIELD 8 + +#define STV090x_Px_TSSTATUS(__x) (0xF581 - (__x - 1) * 0x200) +#define STV090x_P1_TSSTATUS STV090x_Px_TSSTATUS(1) +#define STV090x_P2_TSSTATUS STV090x_Px_TSSTATUS(2) +#define STV090x_OFFST_Px_TSFIFO_LINEOK_FIELD 7 +#define STV090x_WIDTH_Px_TSFIFO_LINEOK_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_ERROR_FIELD 6 +#define STV090x_WIDTH_Px_TSFIFO_ERROR_FIELD 1 + +#define STV090x_Px_TSSTATUS2(__x) (0xF582 - (__x - 1) * 0x200) +#define STV090x_P1_TSSTATUS2 STV090x_Px_TSSTATUS2(1) +#define STV090x_P2_TSSTATUS2 STV090x_Px_TSSTATUS2(2) +#define STV090x_OFFST_Px_TSFIFO_DEMODSEL_FIELD 7 +#define STV090x_WIDTH_Px_TSFIFO_DEMODSEL_FIELD 1 +#define STV090x_OFFST_Px_TSFIFOSPEED_STORE_FIELD 6 +#define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD 1 +#define STV090x_OFFST_Px_DILXX_RESET_FIELD 5 +#define STV090x_WIDTH_Px_DILXX_RESET_FIELD 1 +#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD 4 +#define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD 1 +#define STV090x_OFFST_Px_SCRAMBDETECT_FIELD 1 +#define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD 1 + +#define STV090x_Px_TSBITRATEy(__x, __y) (0xF584 - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_TSBITRATE0 STV090x_Px_TSBITRATEy(1, 0) +#define STV090x_P1_TSBITRATE1 STV090x_Px_TSBITRATEy(1, 1) +#define STV090x_P2_TSBITRATE0 STV090x_Px_TSBITRATEy(2, 0) +#define STV090x_P2_TSBITRATE1 STV090x_Px_TSBITRATEy(2, 1) +#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD 0 +#define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD 8 + +#define STV090x_Px_ERRCTRL1(__x) (0xF598 - (__x - 1) * 0x200) +#define STV090x_P1_ERRCTRL1 STV090x_Px_ERRCTRL1(1) +#define STV090x_P2_ERRCTRL1 STV090x_Px_ERRCTRL1(2) +#define STV090x_OFFST_Px_ERR_SOURCE_FIELD 4 +#define STV090x_WIDTH_Px_ERR_SOURCE_FIELD 4 +#define STV090x_OFFST_Px_NUM_EVENT_FIELD 0 +#define STV090x_WIDTH_Px_NUM_EVENT_FIELD 3 + +#define STV090x_Px_ERRCNT12(__x) (0xF599 - (__x - 1) * 0x200) +#define STV090x_P1_ERRCNT12 STV090x_Px_ERRCNT12(1) +#define STV090x_P2_ERRCNT12 STV090x_Px_ERRCNT12(2) +#define STV090x_OFFST_Px_ERRCNT1_OLDVALUE_FIELD 7 +#define STV090x_WIDTH_Px_ERRCNT1_OLDVALUE_FIELD 1 +#define STV090x_OFFST_Px_ERR_CNT12_FIELD 0 +#define STV090x_WIDTH_Px_ERR_CNT12_FIELD 7 + +#define STV090x_Px_ERRCNT11(__x) (0xF59A - (__x - 1) * 0x200) +#define STV090x_P1_ERRCNT11 STV090x_Px_ERRCNT11(1) +#define STV090x_P2_ERRCNT11 STV090x_Px_ERRCNT11(2) +#define STV090x_OFFST_Px_ERR_CNT11_FIELD 0 +#define STV090x_WIDTH_Px_ERR_CNT11_FIELD 8 + +#define STV090x_Px_ERRCNT10(__x) (0xF59B - (__x - 1) * 0x200) +#define STV090x_P1_ERRCNT10 STV090x_Px_ERRCNT10(1) +#define STV090x_P2_ERRCNT10 STV090x_Px_ERRCNT10(2) +#define STV090x_OFFST_Px_ERR_CNT10_FIELD 0 +#define STV090x_WIDTH_Px_ERR_CNT10_FIELD 8 + +#define STV090x_Px_ERRCTRL2(__x) (0xF59C - (__x - 1) * 0x200) +#define STV090x_P1_ERRCTRL2 STV090x_Px_ERRCTRL2(1) +#define STV090x_P2_ERRCTRL2 STV090x_Px_ERRCTRL2(2) +#define STV090x_OFFST_Px_ERR_SOURCE2_FIELD 4 +#define STV090x_WIDTH_Px_ERR_SOURCE2_FIELD 4 +#define STV090x_OFFST_Px_NUM_EVENT2_FIELD 0 +#define STV090x_WIDTH_Px_NUM_EVENT2_FIELD 3 + +#define STV090x_Px_ERRCNT22(__x) (0xF59D - (__x - 1) * 0x200) +#define STV090x_P1_ERRCNT22 STV090x_Px_ERRCNT22(1) +#define STV090x_P2_ERRCNT22 STV090x_Px_ERRCNT22(2) +#define STV090x_OFFST_Px_ERRCNT2_OLDVALUE_FIELD 7 +#define STV090x_WIDTH_Px_ERRCNT2_OLDVALUE_FIELD 1 +#define STV090x_OFFST_Px_ERR_CNT2_FIELD 0 +#define STV090x_WIDTH_Px_ERR_CNT2_FIELD 7 + +#define STV090x_Px_ERRCNT21(__x) (0xF59E - (__x - 1) * 0x200) +#define STV090x_P1_ERRCNT21 STV090x_Px_ERRCNT21(1) +#define STV090x_P2_ERRCNT21 STV090x_Px_ERRCNT21(2) +#define STV090x_OFFST_Px_ERR_CNT21_FIELD 0 +#define STV090x_WIDTH_Px_ERR_CNT21_FIELD 8 + +#define STV090x_Px_ERRCNT20(__x) (0xF59F - (__x - 1) * 0x200) +#define STV090x_P1_ERRCNT20 STV090x_Px_ERRCNT20(1) +#define STV090x_P2_ERRCNT20 STV090x_Px_ERRCNT20(2) +#define STV090x_OFFST_Px_ERR_CNT20_FIELD 0 +#define STV090x_WIDTH_Px_ERR_CNT20_FIELD 8 + +#define STV090x_Px_FECSPY(__x) (0xF5A0 - (__x - 1) * 0x200) +#define STV090x_P1_FECSPY STV090x_Px_FECSPY(1) +#define STV090x_P2_FECSPY STV090x_Px_FECSPY(2) +#define STV090x_OFFST_Px_SPY_ENABLE_FIELD 7 +#define STV090x_WIDTH_Px_SPY_ENABLE_FIELD 1 +#define STV090x_OFFST_Px_BERMETER_DATAMAODE_FIELD 2 +#define STV090x_WIDTH_Px_BERMETER_DATAMAODE_FIELD 2 + +#define STV090x_Px_FSPYCFG(__x) (0xF5A1 - (__x - 1) * 0x200) +#define STV090x_P1_FSPYCFG STV090x_Px_FSPYCFG(1) +#define STV090x_P2_FSPYCFG STV090x_Px_FSPYCFG(2) +#define STV090x_OFFST_Px_RST_ON_ERROR_FIELD 5 +#define STV090x_WIDTH_Px_RST_ON_ERROR_FIELD 1 +#define STV090x_OFFST_Px_ONE_SHOT_FIELD 4 +#define STV090x_WIDTH_Px_ONE_SHOT_FIELD 1 +#define STV090x_OFFST_Px_I2C_MODE_FIELD 2 +#define STV090x_WIDTH_Px_I2C_MODE_FIELD 2 + +#define STV090x_Px_FSPYDATA(__x) (0xF5A2 - (__x - 1) * 0x200) +#define STV090x_P1_FSPYDATA STV090x_Px_FSPYDATA(1) +#define STV090x_P2_FSPYDATA STV090x_Px_FSPYDATA(2) +#define STV090x_OFFST_Px_SPY_STUFFING_FIELD 7 +#define STV090x_WIDTH_Px_SPY_STUFFING_FIELD 1 +#define STV090x_OFFST_Px_SPY_CNULLPKT_FIELD 5 +#define STV090x_WIDTH_Px_SPY_CNULLPKT_FIELD 1 +#define STV090x_OFFST_Px_SPY_OUTDATA_MODE_FIELD 0 +#define STV090x_WIDTH_Px_SPY_OUTDATA_MODE_FIELD 5 + +#define STV090x_Px_FSPYOUT(__x) (0xF5A3 - (__x - 1) * 0x200) +#define STV090x_P1_FSPYOUT STV090x_Px_FSPYOUT(1) +#define STV090x_P2_FSPYOUT STV090x_Px_FSPYOUT(2) +#define STV090x_OFFST_Px_FSPY_DIRECT_FIELD 7 +#define STV090x_WIDTH_Px_FSPY_DIRECT_FIELD 1 +#define STV090x_OFFST_Px_STUFF_MODE_FIELD 0 +#define STV090x_WIDTH_Px_STUFF_MODE_FIELD 3 + +#define STV090x_Px_FSTATUS(__x) (0xF5A4 - (__x - 1) * 0x200) +#define STV090x_P1_FSTATUS STV090x_Px_FSTATUS(1) +#define STV090x_P2_FSTATUS STV090x_Px_FSTATUS(2) +#define STV090x_OFFST_Px_SPY_ENDSIM_FIELD 7 +#define STV090x_WIDTH_Px_SPY_ENDSIM_FIELD 1 +#define STV090x_OFFST_Px_VALID_SIM_FIELD 6 +#define STV090x_WIDTH_Px_VALID_SIM_FIELD 1 +#define STV090x_OFFST_Px_FOUND_SIGNAL_FIELD 5 +#define STV090x_WIDTH_Px_FOUND_SIGNAL_FIELD 1 +#define STV090x_OFFST_Px_DSS_SYNCBYTE_FIELD 4 +#define STV090x_WIDTH_Px_DSS_SYNCBYTE_FIELD 1 +#define STV090x_OFFST_Px_RESULT_STATE_FIELD 0 +#define STV090x_WIDTH_Px_RESULT_STATE_FIELD 4 + +#define STV090x_Px_FBERCPT4(__x) (0xF5A8 - (__x - 1) * 0x200) +#define STV090x_P1_FBERCPT4 STV090x_Px_FBERCPT4(1) +#define STV090x_P2_FBERCPT4 STV090x_Px_FBERCPT4(2) +#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 +#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 + +#define STV090x_Px_FBERCPT3(__x) (0xF5A9 - (__x - 1) * 0x200) +#define STV090x_P1_FBERCPT3 STV090x_Px_FBERCPT3(1) +#define STV090x_P2_FBERCPT3 STV090x_Px_FBERCPT3(2) +#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 +#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 + +#define STV090x_Px_FBERCPT2(__x) (0xF5AA - (__x - 1) * 0x200) +#define STV090x_P1_FBERCPT2 STV090x_Px_FBERCPT2(1) +#define STV090x_P2_FBERCPT2 STV090x_Px_FBERCPT2(2) +#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 +#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 + +#define STV090x_Px_FBERCPT1(__x) (0xF5AB - (__x - 1) * 0x200) +#define STV090x_P1_FBERCPT1 STV090x_Px_FBERCPT1(1) +#define STV090x_P2_FBERCPT1 STV090x_Px_FBERCPT1(2) +#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 +#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 + +#define STV090x_Px_FBERCPT0(__x) (0xF5AC - (__x - 1) * 0x200) +#define STV090x_P1_FBERCPT0 STV090x_Px_FBERCPT0(1) +#define STV090x_P2_FBERCPT0 STV090x_Px_FBERCPT0(2) +#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0 +#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8 + +#define STV090x_Px_FBERERRy(__x, __y) (0xF5AF - (__x - 1) * 0x200 - __y * 0x1) +#define STV090x_P1_FBERERR0 STV090x_Px_FBERERRy(1, 0) +#define STV090x_P1_FBERERR1 STV090x_Px_FBERERRy(1, 1) +#define STV090x_P1_FBERERR2 STV090x_Px_FBERERRy(1, 2) +#define STV090x_P2_FBERERR0 STV090x_Px_FBERERRy(2, 0) +#define STV090x_P2_FBERERR1 STV090x_Px_FBERERRy(2, 1) +#define STV090x_P2_FBERERR2 STV090x_Px_FBERERRy(2, 2) +#define STV090x_OFFST_Px_FBERMETER_CPT_ERR_FIELD 0 +#define STV090x_WIDTH_Px_FBERMETER_CPT_ERR_FIELD 8 + +#define STV090x_Px_FSPYBER(__x) (0xF5B2 - (__x - 1) * 0x200) +#define STV090x_P1_FSPYBER STV090x_Px_FSPYBER(1) +#define STV090x_P2_FSPYBER STV090x_Px_FSPYBER(2) +#define STV090x_OFFST_Px_FSPYBER_SYNCBYTE_FIELD 4 +#define STV090x_WIDTH_Px_FSPYBER_SYNCBYTE_FIELD 1 +#define STV090x_OFFST_Px_FSPYBER_UNSYNC_FIELD 3 +#define STV090x_WIDTH_Px_FSPYBER_UNSYNC_FIELD 1 +#define STV090x_OFFST_Px_FSPYBER_CTIME_FIELD 0 +#define STV090x_WIDTH_Px_FSPYBER_CTIME_FIELD 3 + +#define STV090x_RCCFGH 0xf600 + +#define STV090x_TSGENERAL 0xF630 +#define STV090x_OFFST_Px_MUXSTREAM_OUT_FIELD 3 +#define STV090x_WIDTH_Px_MUXSTREAM_OUT_FIELD 1 +#define STV090x_OFFST_Px_TSFIFO_PERMPARAL_FIELD 1 +#define STV090x_WIDTH_Px_TSFIFO_PERMPARAL_FIELD 2 + +#define STV090x_TSGENERAL1X 0xf670 +#define STV090x_CFGEXT 0xfa80 + +#define STV090x_TSTRES0 0xFF11 +#define STV090x_OFFST_FRESFEC_FIELD 7 +#define STV090x_WIDTH_FRESFEC_FIELD 1 + +#define STV090x_Px_TSTDISRX(__x) (0xFF67 - (__x - 1) * 0x2) +#define STV090x_P1_TSTDISRX STV090x_Px_TSTDISRX(1) +#define STV090x_P2_TSTDISRX STV090x_Px_TSTDISRX(2) +#define STV090x_OFFST_Px_TSTDISRX_SELECT_FIELD 3 +#define STV090x_WIDTH_Px_TSTDISRX_SELECT_FIELD 1 + +#endif /* __STV090x_REG_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,405 @@ +/* + STV6110(A) Silicon tuner driver + + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" + +#include "stv6110x_reg.h" +#include "stv6110x.h" +#include "stv6110x_priv.h" + +static unsigned int verbose; +module_param(verbose, int, 0644); +MODULE_PARM_DESC(verbose, "Set Verbosity level"); + +static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data) +{ + int ret; + const struct stv6110x_config *config = stv6110x->config; + u8 b0[] = { reg }; + u8 b1[] = { 0 }; + struct i2c_msg msg[] = { + { .addr = config->addr, .flags = 0, .buf = b0, .len = 1 }, + { .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } + }; + + ret = i2c_transfer(stv6110x->i2c, msg, 2); + if (ret != 2) { + dprintk(FE_ERROR, 1, "I/O Error"); + return -EREMOTEIO; + } + *data = b1[0]; + + return 0; +} + +static int stv6110x_write_regs(struct stv6110x_state *stv6110x, int start, u8 data[], int len) +{ + int ret; + const struct stv6110x_config *config = stv6110x->config; + u8 buf[len + 1]; + struct i2c_msg msg = { + .addr = config->addr, + .flags = 0, + .buf = buf, + .len = len + 1 + }; + + if (start + len > 8) + return -EINVAL; + + buf[0] = start; + memcpy(&buf[1], data, len); + + ret = i2c_transfer(stv6110x->i2c, &msg, 1); + if (ret != 1) { + dprintk(FE_ERROR, 1, "I/O Error"); + return -EREMOTEIO; + } + + return 0; +} + +static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data) +{ + return stv6110x_write_regs(stv6110x, reg, &data, 1); +} + +static int stv6110x_init(struct dvb_frontend *fe) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + int ret; + + ret = stv6110x_write_regs(stv6110x, 0, stv6110x->regs, + ARRAY_SIZE(stv6110x->regs)); + if (ret < 0) { + dprintk(FE_ERROR, 1, "Initialization failed"); + return -1; + } + + return 0; +} + +static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + u32 rDiv, divider; + s32 pVal, pCalc, rDivOpt = 0, pCalcOpt = 1000; + u8 i; + + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16)); + + if (frequency <= 1023000) { + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0); + pVal = 40; + } else if (frequency <= 1300000) { + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1); + pVal = 40; + } else if (frequency <= 2046000) { + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0); + pVal = 20; + } else { + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1); + pVal = 20; + } + + for (rDiv = 0; rDiv <= 3; rDiv++) { + pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv); + + if ((abs((s32)(pCalc - pVal))) < (abs((s32)(pCalcOpt - pVal)))) + rDivOpt = rDiv; + + pCalcOpt = (REFCLOCK_kHz / 100) / R_DIV(rDivOpt); + } + + divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz; + divider = (divider + 5) / 10; + + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider)); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider)); + + /* VCO Auto calibration */ + STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1); + + stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]); + stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x->regs[STV6110x_TNG1]); + stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x->regs[STV6110x_TNG0]); + stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]); + + for (i = 0; i < TRIALS; i++) { + stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]); + if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x->regs[STV6110x_STAT1])) + break; + msleep(1); + } + + return 0; +} + +static int stv6110x_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + + stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x->regs[STV6110x_TNG1]); + stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x->regs[STV6110x_TNG0]); + + *frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x->regs[STV6110x_TNG1]), + STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x->regs[STV6110x_TNG0]))) * REFCLOCK_kHz; + + *frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x->regs[STV6110x_TNG1]) + + STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x->regs[STV6110x_TNG1]))); + + *frequency >>= 2; + + return 0; +} + +static int stv6110x_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + u32 halfbw; + u8 i; + + halfbw = bandwidth >> 1; + + if (halfbw > 36000000) + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */ + else if (halfbw < 5000000) + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */ + else + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */ + + + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */ + STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */ + + stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]); + stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]); + + for (i = 0; i < TRIALS; i++) { + stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]); + if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x->regs[STV6110x_STAT1])) + break; + msleep(1); + } + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */ + stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]); + + return 0; +} + +static int stv6110x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + + stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x->regs[STV6110x_CTRL3]); + *bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x->regs[STV6110x_CTRL3]) + 5) * 2000000; + + return 0; +} + +static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + + /* setup divider */ + switch (refclock) { + default: + case 1: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0); + break; + case 2: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1); + break; + case 4: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2); + break; + case 8: + case 0: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3); + break; + } + stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]); + + return 0; +} + +static int stv6110x_get_bbgain(struct dvb_frontend *fe, u32 *gain) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + + stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x->regs[STV6110x_CTRL2]); + *gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x->regs[STV6110x_CTRL2]); + + return 0; +} + +static int stv6110x_set_bbgain(struct dvb_frontend *fe, u32 gain) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2); + stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]); + + return 0; +} + +static int stv6110x_set_mode(struct dvb_frontend *fe, enum tuner_mode mode) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + int ret; + + switch (mode) { + case TUNER_SLEEP: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 0); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 0); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 0); + break; + + case TUNER_WAKE: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 1); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 1); + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 1); + break; + } + + ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]); + if (ret < 0) { + dprintk(FE_ERROR, 1, "I/O Error"); + return -EIO; + } + + return 0; +} + +static int stv6110x_sleep(struct dvb_frontend *fe) +{ + if (fe->tuner_priv) + return stv6110x_set_mode(fe, TUNER_SLEEP); + + return 0; +} + +static int stv6110x_get_status(struct dvb_frontend *fe, u32 *status) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + + stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]); + + if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x->regs[STV6110x_STAT1])) + *status = TUNER_PHASELOCKED; + else + *status = 0; + + return 0; +} + + +static int stv6110x_release(struct dvb_frontend *fe) +{ + struct stv6110x_state *stv6110x = fe->tuner_priv; + + fe->tuner_priv = NULL; + kfree(stv6110x); + + return 0; +} + +static struct dvb_tuner_ops stv6110x_ops = { + .info = { + .name = "STV6110(A) Silicon Tuner", + .frequency_min = 950000, + .frequency_max = 2150000, + .frequency_step = 0, + }, + .release = stv6110x_release +}; + +static struct stv6110x_devctl stv6110x_ctl = { + .tuner_init = stv6110x_init, + .tuner_sleep = stv6110x_sleep, + .tuner_set_mode = stv6110x_set_mode, + .tuner_set_frequency = stv6110x_set_frequency, + .tuner_get_frequency = stv6110x_get_frequency, + .tuner_set_bandwidth = stv6110x_set_bandwidth, + .tuner_get_bandwidth = stv6110x_get_bandwidth, + .tuner_set_bbgain = stv6110x_set_bbgain, + .tuner_get_bbgain = stv6110x_get_bbgain, + .tuner_set_refclk = stv6110x_set_refclock, + .tuner_get_status = stv6110x_get_status, +}; + +struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, + const struct stv6110x_config *config, + struct i2c_adapter *i2c) +{ + struct stv6110x_state *stv6110x; + u8 default_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e}; + + stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL); + if (!stv6110x) + return NULL; + + stv6110x->i2c = i2c; + stv6110x->config = config; + stv6110x->devctl = &stv6110x_ctl; + memcpy(stv6110x->regs, default_regs, 8); + + /* setup divider */ + switch (stv6110x->config->clk_div) { + default: + case 1: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0); + break; + case 2: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1); + break; + case 4: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2); + break; + case 8: + case 0: + STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3); + break; + } + + fe->tuner_priv = stv6110x; + fe->ops.tuner_ops = stv6110x_ops; + + printk(KERN_INFO "%s: Attaching STV6110x\n", __func__); + return stv6110x->devctl; +} +EXPORT_SYMBOL(stv6110x_attach); + +MODULE_AUTHOR("Manu Abraham"); +MODULE_DESCRIPTION("STV6110x Silicon tuner"); +MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,73 @@ +/* + STV6110(A) Silicon tuner driver + + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __STV6110x_H +#define __STV6110x_H + +struct stv6110x_config { + u8 addr; + u32 refclk; + u8 clk_div; /* divisor value for the output clock */ +}; + +enum tuner_mode { + TUNER_SLEEP = 1, + TUNER_WAKE, +}; + +enum tuner_status { + TUNER_PHASELOCKED = 1, +}; + +struct stv6110x_devctl { + int (*tuner_init) (struct dvb_frontend *fe); + int (*tuner_sleep) (struct dvb_frontend *fe); + int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode); + int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency); + int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency); + int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth); + int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth); + int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain); + int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain); + int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk); + int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status); +}; + + +#if defined(CONFIG_DVB_STV6110x) || (defined(CONFIG_DVB_STV6110x_MODULE) && defined(MODULE)) + +extern struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, + const struct stv6110x_config *config, + struct i2c_adapter *i2c); + +#else +static inline struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, + const struct stv6110x_config *config, + struct i2c_adapter *i2c) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} + +#endif /* CONFIG_DVB_STV6110x */ + +#endif /* __STV6110x_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_priv.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_priv.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,76 @@ +/* + STV6110(A) Silicon tuner driver + + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __STV6110x_PRIV_H +#define __STV6110x_PRIV_H + +#define FE_ERROR 0 +#define FE_NOTICE 1 +#define FE_INFO 2 +#define FE_DEBUG 3 +#define FE_DEBUGREG 4 + +#define dprintk(__y, __z, format, arg...) do { \ + if (__z) { \ + if ((verbose > FE_ERROR) && (verbose > __y)) \ + printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \ + else if ((verbose > FE_NOTICE) && (verbose > __y)) \ + printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \ + else if ((verbose > FE_INFO) && (verbose > __y)) \ + printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \ + else if ((verbose > FE_DEBUG) && (verbose > __y)) \ + printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \ + } else { \ + if (verbose > __y) \ + printk(format, ##arg); \ + } \ +} while (0) + + +#define STV6110x_SETFIELD(mask, bitf, val) \ + (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \ + STV6110x_OFFST_##bitf))) | \ + (val << STV6110x_OFFST_##bitf)) + +#define STV6110x_GETFIELD(bitf, val) \ + ((val >> STV6110x_OFFST_##bitf) & \ + ((1 << STV6110x_WIDTH_##bitf) - 1)) + +#define MAKEWORD16(a, b) (((a) << 8) | (b)) + +#define LSB(x) ((x & 0xff)) +#define MSB(y) ((y >> 8) & 0xff) + +#define TRIALS 10 +#define R_DIV(__div) (1 << (__div + 1)) +#define REFCLOCK_kHz (stv6110x->config->refclk / 1000) +#define REFCLOCK_MHz (stv6110x->config->refclk / 1000000) + +struct stv6110x_state { + struct i2c_adapter *i2c; + const struct stv6110x_config *config; + u8 regs[8]; + + struct stv6110x_devctl *devctl; +}; + +#endif /* __STV6110x_PRIV_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_reg.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_reg.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_reg.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/stv6110x_reg.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,82 @@ +/* + STV6110(A) Silicon tuner driver + + Copyright (C) Manu Abraham + + Copyright (C) ST Microelectronics + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __STV6110x_REG_H +#define __STV6110x_REG_H + +#define STV6110x_CTRL1 0x00 +#define STV6110x_OFFST_CTRL1_K 3 +#define STV6110x_WIDTH_CTRL1_K 5 +#define STV6110x_OFFST_CTRL1_LPT 2 +#define STV6110x_WIDTH_CTRL1_LPT 1 +#define STV6110x_OFFST_CTRL1_RX 1 +#define STV6110x_WIDTH_CTRL1_RX 1 +#define STV6110x_OFFST_CTRL1_SYN 0 +#define STV6110x_WIDTH_CTRL1_SYN 1 + +#define STV6110x_CTRL2 0x01 +#define STV6110x_OFFST_CTRL2_CO_DIV 6 +#define STV6110x_WIDTH_CTRL2_CO_DIV 2 +#define STV6110x_OFFST_CTRL2_RSVD 5 +#define STV6110x_WIDTH_CTRL2_RSVD 1 +#define STV6110x_OFFST_CTRL2_REFOUT_SEL 4 +#define STV6110x_WIDTH_CTRL2_REFOUT_SEL 1 +#define STV6110x_OFFST_CTRL2_BBGAIN 0 +#define STV6110x_WIDTH_CTRL2_BBGAIN 4 + +#define STV6110x_TNG0 0x02 +#define STV6110x_OFFST_TNG0_N_DIV_7_0 0 +#define STV6110x_WIDTH_TNG0_N_DIV_7_0 8 + +#define STV6110x_TNG1 0x03 +#define STV6110x_OFFST_TNG1_R_DIV 6 +#define STV6110x_WIDTH_TNG1_R_DIV 2 +#define STV6110x_OFFST_TNG1_PRESC32_ON 5 +#define STV6110x_WIDTH_TNG1_PRESC32_ON 1 +#define STV6110x_OFFST_TNG1_DIV4SEL 4 +#define STV6110x_WIDTH_TNG1_DIV4SEL 1 +#define STV6110x_OFFST_TNG1_N_DIV_11_8 0 +#define STV6110x_WIDTH_TNG1_N_DIV_11_8 4 + + +#define STV6110x_CTRL3 0x04 +#define STV6110x_OFFST_CTRL3_DCLOOP_OFF 7 +#define STV6110x_WIDTH_CTRL3_DCLOOP_OFF 1 +#define STV6110x_OFFST_CTRL3_RCCLK_OFF 6 +#define STV6110x_WIDTH_CTRL3_RCCLK_OFF 1 +#define STV6110x_OFFST_CTRL3_ICP 5 +#define STV6110x_WIDTH_CTRL3_ICP 1 +#define STV6110x_OFFST_CTRL3_CF 0 +#define STV6110x_WIDTH_CTRL3_CF 5 + +#define STV6110x_STAT1 0x05 +#define STV6110x_OFFST_STAT1_CALVCO_STRT 2 +#define STV6110x_WIDTH_STAT1_CALVCO_STRT 1 +#define STV6110x_OFFST_STAT1_CALRC_STRT 1 +#define STV6110x_WIDTH_STAT1_CALRC_STRT 1 +#define STV6110x_OFFST_STAT1_LOCK 0 +#define STV6110x_WIDTH_STAT1_LOCK 1 + +#define STV6110x_STAT2 0x06 +#define STV6110x_STAT3 0x07 + +#endif /* __STV6110x_REG_H */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,43 @@ +/* + * NXP TDA18212HN silicon tuner driver + * + * Copyright (C) 2011 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef TDA18212_H +#define TDA18212_H + +#include "dvb_frontend.h" + +struct tda18212_config { + u8 i2c_address; +}; + +#if defined(CONFIG_DVB_TDA18212) || \ + (defined(CONFIG_DVB_TDA18212_MODULE) && defined(MODULE)) +extern struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, struct tda18212_config *cfg); +#else +static inline struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, struct tda18212_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212_priv.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212_priv.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212_priv.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212_priv.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,45 @@ +/* + * NXP TDA18212HN silicon tuner driver + * + * Copyright (C) 2011 Antti Palosaari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef TDA18212_PRIV_H +#define TDA18212_PRIV_H + +#include "tda18212.h" + +#define LOG_PREFIX "tda18212" + +#undef dbg +#define dbg(f, arg...) \ + if (debug) \ + printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) +#undef err +#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) +#undef info +#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) +#undef warn +#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) + +struct tda18212_priv { + struct tda18212_config *cfg; + struct i2c_adapter *i2c; + u32 IF; +}; + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,937 @@ +/* + * tda18212: Driver for the TDA18212 tuner + * + * Copyright (C) 2011 Digital Devices GmbH + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" + +#ifndef CHK_ERROR + #define CHK_ERROR(s) if ((status = s) < 0) break +#endif + +#define MASTER_PSM_AGC1 0 +#define MASTER_AGC1_6_15dB 1 + +#define SLAVE_PSM_AGC1 1 +#define SLAVE_AGC1_6_15dB 0 + +// 0 = 2 Vpp ... 2 = 1 Vpp, 7 = 0.5 Vpp +#define IF_LEVEL_DVBC 2 +#define IF_LEVEL_DVBT 2 + +enum { + ID_1 = 0x00, + ID_2 = 0x01, + ID_3 = 0x02, + THERMO_1, + THERMO_2, + POWER_STATE_1, + POWER_STATE_2, + INPUT_POWER_LEVEL, + IRQ_STATUS, + IRQ_ENABLE, + IRQ_CLEAR, + IRQ_SET, + AGC1_1, + AGC2_1, + AGCK_1, + RF_AGC_1, + IR_MIXER_1 = 0x10, + AGC5_1, + IF_AGC, + IF_1, + REFERENCE, + IF_FREQUENCY_1, + RF_FREQUENCY_1, + RF_FREQUENCY_2, + RF_FREQUENCY_3, + MSM_1, + MSM_2, + PSM_1, + DCC_1, + FLO_MAX, + IR_CAL_1, + IR_CAL_2, + IR_CAL_3 = 0x20, + IR_CAL_4, + VSYNC_MGT, + IR_MIXER_2, + AGC1_2, + AGC5_2, + RF_CAL_1, + RF_CAL_2, + RF_CAL_3, + RF_CAL_4, + RF_CAL_5, + RF_CAL_6, + RF_FILTER_1, + RF_FILTER_2, + RF_FILTER_3, + RF_BAND_PASS_FILTER, + CP_CURRENT = 0x30, + AGC_DET_OUT = 0x31, + RF_AGC_GAIN_1 = 0x32, + RF_AGC_GAIN_2 = 0x33, + IF_AGC_GAIN = 0x34, + POWER_1 = 0x35, + POWER_2 = 0x36, + MISC_1, + RFCAL_LOG_1, + RFCAL_LOG_2, + RFCAL_LOG_3, + RFCAL_LOG_4, + RFCAL_LOG_5, + RFCAL_LOG_6, + RFCAL_LOG_7, + RFCAL_LOG_8, + RFCAL_LOG_9 = 0x40, + RFCAL_LOG_10 = 0x41, + RFCAL_LOG_11 = 0x42, + RFCAL_LOG_12 = 0x43, + REG_MAX, +}; + +enum HF_Standard { + HF_None=0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, + HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, + HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, + HF_DVBC_8MHZ, HF_DVBC +}; + +struct SStandardParams { + s32 m_IFFrequency; + u32 m_BandWidth; + u8 m_IF_1; // FF IF_HP_fc:2 IF_Notch:1 LP_FC_Offset:2 LP_FC:3 + u8 m_IR_MIXER_2; // 03 :6 HI_Pass:1 DC_Notch:1 + u8 m_AGC1_1; // 0F :4 AGC1_Top:4 + u8 m_AGC2_1; // 0F :4 AGC2_Top:4 + u8 m_RF_AGC_1_Low; // EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 + u8 m_RF_AGC_1_High;// EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 + u8 m_IR_MIXER_1; // 0F :4 IR_mixer_Top:4 + u8 m_AGC5_1; // 1F :3 AGC5_Ana AGC5_Top:4 + u8 m_AGCK_1; // 0F :4 AGCK_Step:2 AGCK_Mode:2 + u8 m_PSM_1; // 20 :2 PSM_StoB:1 :5 + bool m_AGC1_Freeze; + bool m_LTO_STO_immune; +}; + +#if 0 +static struct SStandardParams m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = +{ + { 3250000, 6000000, 0x20, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_6MHZ + { 3500000, 7000000, 0x31, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_7MHZ + { 4000000, 8000000, 0x22, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_8MHZ + { 0, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, // HF_DVBT (Unused) + { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, // HF_ATSC + { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_6MHZ +// { 5000000, 7000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) +// { 5000000, 8000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ + { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) + { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ +}; +#else +static struct SStandardParams m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = +{ + { 4000000, 6000000, 0x41, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_6MHZ + { 4500000, 7000000, 0x42, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_7MHZ + { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_8MHZ + // ------------------------------ + { 0, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, // HF_DVBT (Unused) + { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, // HF_ATSC + { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_6MHZ +// { 5000000, 7000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) +// { 5000000, 8000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ + { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) + { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ +}; +#endif +struct tda_state { + struct i2c_adapter *i2c; + u8 adr; + + enum HF_Standard m_Standard; + u32 m_Frequency; + u32 IF; + + bool m_isMaster; + bool m_bPowerMeasurement; + bool m_bLTEnable; + bool m_bEnableFreeze; + + u16 m_ID; + + s32 m_SettlingTime; + + u8 m_IFLevelDVBC; + u8 m_IFLevelDVBT; + u8 m_Regs[REG_MAX]; + u8 m_LastPowerLevel; +}; + +static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) +{ + struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, + .buf = data, .len = len}}; + return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +} + +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, + .buf = msg, .len = len}, + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { + printk("tda18212dd: i2c_read error\n"); + return -1; + } + return 0; +} + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = {.addr = adr, .flags = 0, + .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk("tda18212: i2c_write error\n"); + return -1; + } + return 0; +} + +static int write_regs(struct tda_state *state, + u8 SubAddr, u8 *Regs, u16 nRegs) +{ + u8 data[nRegs+1]; + + data[0] = SubAddr; + memcpy(data + 1, Regs, nRegs); + return i2c_write(state->i2c, state->adr, data, nRegs+1); +} + +static int write_reg(struct tda_state *state, u8 SubAddr,u8 Reg) +{ + u8 msg[2] = {SubAddr, Reg}; + + return i2c_write(state->i2c, state->adr, msg, 2); +} + +static int Read(struct tda_state *state, u8 * Regs) +{ + return i2c_readn(state->i2c, state->adr, Regs, REG_MAX); +} + +static int update_regs(struct tda_state *state, u8 RegFrom,u8 RegTo) +{ + return write_regs(state, RegFrom, + &state->m_Regs[RegFrom], RegTo-RegFrom+1); +} + +static int update_reg(struct tda_state *state, u8 Reg) +{ + return write_reg(state, Reg,state->m_Regs[Reg]); +} + + +static int read_regs(struct tda_state *state, + u8 SubAddr, u8 *Regs, u16 nRegs) +{ + return i2c_read(state->i2c, state->adr, + &SubAddr, 1, Regs, nRegs); +} + +static int read_reg(struct tda_state *state, + u8 SubAddr, u8 *Reg) +{ + return i2c_read(state->i2c, state->adr, + &SubAddr, 1, Reg, 1); +} + +static int read_reg1(struct tda_state *state, u8 Reg) +{ + return read_reg(state, Reg, &state->m_Regs[Reg]); +} + +static void init_state(struct tda_state *state) +{ + u32 ulIFLevelDVBC = IF_LEVEL_DVBC; + u32 ulIFLevelDVBT = IF_LEVEL_DVBT; + u32 ulPowerMeasurement = 1; + u32 ulLTEnable = 1; + u32 ulEnableFreeze = 0; + + state->m_Frequency = 0; + state->m_isMaster = true; + state->m_ID = 0; + state->m_LastPowerLevel = 0xFF; + state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07); + state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07); + state->m_bPowerMeasurement = (ulPowerMeasurement != 0); + state->m_bLTEnable = (ulLTEnable != 0); + state->m_bEnableFreeze = (ulEnableFreeze != 0); +} + +static int StartCalibration(struct tda_state *state) +{ + int status = 0; + do { + state->m_Regs[POWER_2] &= ~0x02; // RSSI CK = 31.25 kHz + CHK_ERROR(update_reg(state, POWER_2)); + + state->m_Regs[AGC1_2] = (state->m_Regs[AGC1_2] & ~0x60) | 0x40; // AGC1 Do Step = 2 + CHK_ERROR(update_reg(state, AGC1_2)); // AGC + + state->m_Regs[RF_FILTER_3] = (state->m_Regs[RF_FILTER_3] & ~0xC0) | 0x40; // AGC2 Do Step = 1 + CHK_ERROR(update_reg(state, RF_FILTER_3)); + + state->m_Regs[AGCK_1] |= 0xC0; // AGCs Assym Up Step = 3 // Datasheet sets all bits to 1! + CHK_ERROR(update_reg(state, AGCK_1)); + + state->m_Regs[AGC5_1] = (state->m_Regs[AGC5_1] & ~0x60) | 0x40; // AGCs Assym Do Step = 2 + CHK_ERROR(update_reg(state, AGC5_1)); + + state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ + CHK_ERROR(update_reg(state, IRQ_CLEAR)); + + state->m_Regs[MSM_1] = 0x3B; // Set Calibration + state->m_Regs[MSM_2] = 0x01; // Start MSM + CHK_ERROR(update_regs(state, MSM_1,MSM_2)); + state->m_Regs[MSM_2] = 0x00; + + } while(0); + return status; +} + +static int FinishCalibration(struct tda_state *state) +{ + int status = 0; + u8 RFCal_Log[12]; + + do { + u8 IRQ = 0; + int Timeout = 150; // 1.5 s + while(true) { + CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); + if ((IRQ & 0x80) != 0 ) + break; + Timeout -= 1; + if (Timeout == 0) { + status = -1; + break; + } + msleep(10); + } + CHK_ERROR(status); + + state->m_Regs[FLO_MAX] = 0x0A; + CHK_ERROR(update_reg(state, FLO_MAX)); + + state->m_Regs[AGC1_1] &= ~0xC0; + if( state->m_bLTEnable ) state->m_Regs[AGC1_1] |= 0x80; // LTEnable + + state->m_Regs[AGC1_1] |= (state->m_isMaster ? MASTER_AGC1_6_15dB : SLAVE_AGC1_6_15dB ) << 6; + CHK_ERROR(update_reg(state, AGC1_1)); + + state->m_Regs[PSM_1] &= ~0xC0; + state->m_Regs[PSM_1] |= (state->m_isMaster ? MASTER_PSM_AGC1 : SLAVE_PSM_AGC1 ) << 6; + CHK_ERROR(update_reg(state, PSM_1)); + + state->m_Regs[REFERENCE] |= 0x03; // XTOUT = 3 + CHK_ERROR(update_reg(state, REFERENCE)); + + CHK_ERROR(read_regs(state, RFCAL_LOG_1,RFCal_Log,sizeof(RFCal_Log))); + } while(0); + return status; +} + +static int PowerOn(struct tda_state *state) +{ + state->m_Regs[POWER_STATE_2] &= ~0x0F; + update_reg(state, POWER_STATE_2); + state->m_Regs[REFERENCE] |= 0x40; // Digital clock source = Sigma Delta + update_reg(state, REFERENCE); + return 0; +} + +static int Standby(struct tda_state *state) +{ + int status = 0; + + do { + state->m_Regs[REFERENCE] &= ~0x40; // Digital clock source = Quarz + CHK_ERROR(update_reg(state, REFERENCE)); + + state->m_Regs[POWER_STATE_2] &= ~0x0F; + state->m_Regs[POWER_STATE_2] |= state->m_isMaster ? 0x08 : 0x0E; + CHK_ERROR(update_reg(state, POWER_STATE_2)); + } while(0); + return status; +} + +static int attach_init(struct tda_state *state) +{ + int stat = 0; + u8 Id[2]; + u8 PowerState = 0x00; + + state->m_Standard = HF_None; + + /* first read after cold reset sometimes fails on some cards, + try twice */ + stat = read_regs(state, ID_1, Id, sizeof(Id)); + stat = read_regs(state, ID_1, Id, sizeof(Id)); + if (stat < 0) + return -1; + + state->m_ID = ((Id[0] & 0x7F) << 8) | Id[1]; + state->m_isMaster = ((Id[0] & 0x80) != 0); + if( !state->m_isMaster ) + state->m_bLTEnable = false; + + printk("tda18212dd: ChipID %04x\n", state->m_ID); + + if( state->m_ID != 18212 ) + return -1; + + stat = read_reg(state, POWER_STATE_1 ,&PowerState); + if (stat < 0) + return stat; + + printk("tda18212dd: PowerState %02x\n", PowerState); + + if (state->m_isMaster) { + if( PowerState & 0x02 ) { + // msleep for XTAL Calibration (on a PC this should be long done) + u8 IRQStatus = 0; + int Timeout = 10; + + while(Timeout > 0) { + read_reg(state, IRQ_STATUS, &IRQStatus); + if (IRQStatus & 0x20) + break; + Timeout -= 1; + msleep(10); + } + if( (IRQStatus & 0x20) == 0 ) { + stat = -ETIMEDOUT; + } + } + } else { + write_reg(state, FLO_MAX, 0x00); + write_reg(state, CP_CURRENT,0x68); + } + Read(state, state->m_Regs); + + PowerOn(state); + StartCalibration(state); + FinishCalibration(state); + Standby(state); + return stat; +} + +static int PowerMeasurement(struct tda_state *state, u8 *pPowerLevel) +{ + int status = 0; + + do { + u8 IRQ = 0; + int Timeout = 70; // 700 ms + + state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ + CHK_ERROR(update_reg(state, IRQ_CLEAR)); + + state->m_Regs[MSM_1] = 0x80; // power measurement + state->m_Regs[MSM_2] = 0x01; // Start MSM + CHK_ERROR(update_regs(state, MSM_1,MSM_2)); + state->m_Regs[MSM_2] = 0x00; + + while(true) { + CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); + if( (IRQ & 0x80) != 0 ) + break; + Timeout -= 1; + if( Timeout == 0 ) + { + status = -1; + break; + } + msleep(10); + } + CHK_ERROR(status); + + CHK_ERROR(read_reg1(state, INPUT_POWER_LEVEL)); + *pPowerLevel = state->m_Regs[INPUT_POWER_LEVEL] & 0x7F; + + + if( *pPowerLevel > 110 ) *pPowerLevel = 110; + } while(0); + /* printk("PL %d\n", *pPowerLevel); */ + return status; +} + +static int SetFrequency(struct tda_state *state, u32 Frequency, enum HF_Standard Standard) +{ + int status = 0; + struct SStandardParams *StandardParams; + u32 f = Frequency / 1000; + u8 IRQ = 0; + int Timeout = 25; // 250 ms + u32 fRatio = Frequency / 16000000; + u32 fDelta = Frequency - fRatio * 16000000; + + if( Standard < HF_DVBT_6MHZ || Standard > HF_DVBC_8MHZ ) + return -EINVAL; + StandardParams = &m_StandardTable[Standard - HF_DVBT_6MHZ]; + + if( StandardParams->m_IFFrequency == 0 ) + return -EINVAL; + state->m_Standard = HF_None; + state->m_Frequency = 0; + + do { + // IF Level + state->m_Regs[IF_AGC] = (Standard >= HF_DVBC_6MHZ) ? state->m_IFLevelDVBC : state->m_IFLevelDVBT; + CHK_ERROR(update_reg(state, IF_AGC)); + + // --------------------------------------------------------------------------------- + // Standard setup + + state->m_Regs[IF_1] = StandardParams->m_IF_1; + CHK_ERROR(update_reg(state, IF_1)); + + state->m_Regs[IR_MIXER_2] = (state->m_Regs[IR_MIXER_2] & ~0x03) | StandardParams->m_IR_MIXER_2; + CHK_ERROR(update_reg(state, IR_MIXER_2)); + + state->m_Regs[AGC1_1] = (state->m_Regs[AGC1_1] & ~0x0F) | StandardParams->m_AGC1_1; + CHK_ERROR(update_reg(state, AGC1_1)); + + state->m_Regs[AGC2_1] = (state->m_Regs[AGC2_1] & ~0x0F) | StandardParams->m_AGC2_1; + CHK_ERROR(update_reg(state, AGC2_1)); + + state->m_Regs[RF_AGC_1] &= ~0xEF; + if( Frequency < 291000000 ) + state->m_Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_Low; + else + state->m_Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_High; + CHK_ERROR(update_reg(state, RF_AGC_1)); + + state->m_Regs[IR_MIXER_1] = (state->m_Regs[IR_MIXER_1] & ~0x0F) | StandardParams->m_IR_MIXER_1; + CHK_ERROR(update_reg(state, IR_MIXER_1)); + + state->m_Regs[AGC5_1] = (state->m_Regs[AGC5_1] & ~0x1F) | StandardParams->m_AGC5_1; + CHK_ERROR(update_reg(state, AGC5_1)); + + state->m_Regs[AGCK_1] = (state->m_Regs[AGCK_1] & ~0x0F) | StandardParams->m_AGCK_1; + CHK_ERROR(update_reg(state, AGCK_1)); + + state->m_Regs[PSM_1] = (state->m_Regs[PSM_1] & ~0x20) | StandardParams->m_PSM_1; + CHK_ERROR(update_reg(state, PSM_1)); + + state->m_Regs[IF_FREQUENCY_1] = ( StandardParams->m_IFFrequency / 50000 ); + CHK_ERROR(update_reg(state, IF_FREQUENCY_1)); + + if( state->m_isMaster && StandardParams->m_LTO_STO_immune ) + { + u8 tmp; + u8 RF_Filter_Gain; + + CHK_ERROR(read_reg(state, RF_AGC_GAIN_1,&tmp)); + RF_Filter_Gain = (tmp & 0x30) >> 4; + + state->m_Regs[RF_FILTER_1] = (state->m_Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); + CHK_ERROR(update_reg(state, RF_FILTER_1)); + + state->m_Regs[RF_FILTER_1] |= 0x10; // Force + CHK_ERROR(update_reg(state, RF_FILTER_1)); + + while( RF_Filter_Gain != 0 ) + { + RF_Filter_Gain -= 1; + state->m_Regs[RF_FILTER_1] = (state->m_Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); + CHK_ERROR(update_reg(state, RF_FILTER_1)); + msleep(10); + } + CHK_ERROR(status); + + state->m_Regs[RF_AGC_1] |= 0x08; + CHK_ERROR(update_reg(state, RF_AGC_1)); + } + + // --------------------------------------------------------------------------------- + + state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ + CHK_ERROR(update_reg(state, IRQ_CLEAR)); + + CHK_ERROR(PowerOn(state)); + + state->m_Regs[RF_FREQUENCY_1] = ((f >> 16) & 0xFF); + state->m_Regs[RF_FREQUENCY_2] = ((f >> 8) & 0xFF); + state->m_Regs[RF_FREQUENCY_3] = ((f ) & 0xFF); + CHK_ERROR(update_regs(state, RF_FREQUENCY_1,RF_FREQUENCY_3)); + + state->m_Regs[MSM_1] = 0x41; // Tune + state->m_Regs[MSM_2] = 0x01; // Start MSM + CHK_ERROR(update_regs(state, MSM_1, MSM_2)); + state->m_Regs[MSM_2] = 0x00; + + while(true) + { + CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); + if( (IRQ & 0x80) != 0 ) break; + Timeout -= 1; + if (Timeout == 0) { + status = -1; + break; + } + msleep(10); + } + CHK_ERROR(status); + + // --------------------------------------------------------------------------------- + + if( state->m_isMaster && StandardParams->m_LTO_STO_immune ) + { + state->m_Regs[RF_AGC_1] &= ~0x08; + CHK_ERROR(update_reg(state, RF_AGC_1)); + + msleep(50); + + state->m_Regs[RF_FILTER_1] &= ~0x10; // remove force + CHK_ERROR(update_reg(state, RF_FILTER_1)); + } + + // --------------------------------------------------------------------------------- + // Spur reduction + + if( Frequency < 72000000 ) + { + state->m_Regs[REFERENCE] |= 0x40; // Set digital clock + } + else if( Frequency < 104000000 ) + { + state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock + } + else if( Frequency < 120000000 ) + { + state->m_Regs[REFERENCE] |= 0x40; // Set digital clock + } + else + { + if( fDelta <= 8000000 ) + { + if( fRatio & 1 ) state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock + else state->m_Regs[REFERENCE] |= 0x40; // Set digital clock + } + else + { + if( fRatio & 1 ) state->m_Regs[REFERENCE] |= 0x40; // Set digital clock + else state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock + } + + } + CHK_ERROR(update_reg(state, REFERENCE)); + + if( StandardParams->m_AGC1_Freeze && state->m_bEnableFreeze ) + { + u8 tmp; + int AGC1GainMin = 0; + int nSteps = 10; + int Step = 0; + + CHK_ERROR(read_reg(state, AGC1_2,&tmp)); + + if( (tmp & 0x80) == 0 ) + { + state->m_Regs[AGC1_2] |= 0x80; // Loop off + CHK_ERROR(update_reg(state, AGC1_2)); + state->m_Regs[AGC1_2] |= 0x10 ; // Force gain + CHK_ERROR(update_reg(state, AGC1_2)); + } + // Adapt + if( state->m_Regs[AGC1_1] & 0x40 ) // AGC1_6_15dB set + { + AGC1GainMin = 6; + nSteps = 4; + } + while( Step < nSteps ) + { + int Down = 0; + int Up = 0, i; + u8 AGC1_Gain; + + Step = Step + 1; + + for (i = 0; i < 40; i += 1) { + CHK_ERROR(read_reg(state, AGC_DET_OUT, &tmp)); + Up += (tmp & 0x02) ? 1 : -4; + Down += (tmp & 0x01) ? 14 : -1; + msleep(1); + } + CHK_ERROR(status); + AGC1_Gain = (state->m_Regs[AGC1_2] & 0x0F); + if( Up >= 15 && AGC1_Gain != 9 ) + { + state->m_Regs[AGC1_2] = ( state->m_Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain + 1); + CHK_ERROR(update_reg(state, AGC1_2)); + } + else if ( Down >= 10 && AGC1_Gain != AGC1GainMin ) + { + state->m_Regs[AGC1_2] = ( state->m_Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain - 1); + CHK_ERROR(update_reg(state, AGC1_2)); + } + else + { + Step = nSteps; + } + } + } + else + { + state->m_Regs[AGC1_2] &= ~0x10 ; // unforce gain + CHK_ERROR(update_reg(state, AGC1_2)); + state->m_Regs[AGC1_2] &= ~0x80; // Loop on + CHK_ERROR(update_reg(state, AGC1_2)); + } + + state->m_Standard = Standard; + state->m_Frequency = Frequency; + + if( state->m_bPowerMeasurement ) + PowerMeasurement(state, &state->m_LastPowerLevel); + } while(0); + + return status; +} + +static int sleep(struct dvb_frontend* fe) +{ + struct tda_state *state = fe->tuner_priv; + + Standby(state); + return 0; +} + +static int init(struct dvb_frontend* fe) +{ + //struct tda_state *state = fe->tuner_priv; + return 0; +} + +static int release(struct dvb_frontend* fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +#ifndef USE_API3 +static int set_params(struct dvb_frontend *fe) +{ + struct tda_state *state = fe->tuner_priv; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + int status = 0; + int Standard; + u32 bw; + + bw = (p->bandwidth_hz + 999999) / 1000000; + state->m_Frequency = p->frequency; + if (p->delivery_system == SYS_DVBT || + p->delivery_system == SYS_DVBT2 || + p->delivery_system == SYS_ISDBT || + p->delivery_system == SYS_DVBC2) { + switch (bw) { + case 6: + Standard = HF_DVBT_6MHZ; + break; + case 7: + Standard = HF_DVBT_7MHZ; + break; + default: + case 8: + Standard = HF_DVBT_8MHZ; + break; + } + } else if (p->delivery_system == SYS_DVBC_ANNEX_A) { + switch (bw) { + case 6: + Standard = HF_DVBC_6MHZ; + break; + case 7: + Standard = HF_DVBC_7MHZ; + break; + default: + case 8: + Standard = HF_DVBC_8MHZ; + break; + } + } else + return -EINVAL; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + SetFrequency(state, state->m_Frequency, Standard); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return status; +} +#else +static int set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct tda_state *state = fe->tuner_priv; + int status = 0; + int Standard; + + state->m_Frequency = params->frequency; + + if (fe->ops.info.type == FE_OFDM) + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + Standard = HF_DVBT_6MHZ; + break; + case BANDWIDTH_7_MHZ: + Standard = HF_DVBT_7MHZ; + break; + default: + case BANDWIDTH_8_MHZ: + Standard = HF_DVBT_8MHZ; + break; + } + else if (fe->ops.info.type == FE_QAM) { + Standard = HF_DVBC_8MHZ; + } else + return -EINVAL; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + SetFrequency(state, state->m_Frequency, Standard); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return status; +} +#endif + +static int get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tda_state *state = fe->tuner_priv; + + *frequency = state->IF; + return 0; +} + +static int get_rf_strength(struct dvb_frontend *fe, u16 *st) +{ + struct tda_state *state = fe->tuner_priv; + + *st = state->m_LastPowerLevel; + return 0; +} + +static int get_if(struct dvb_frontend *fe, u32 *frequency) +{ + struct tda_state *state = fe->tuner_priv; + + state->IF = 0; + if (state->m_Standard < HF_DVBT_6MHZ || + state->m_Standard > HF_DVBC_8MHZ) + return 0; + state->IF = m_StandardTable[state->m_Standard - HF_DVBT_6MHZ].m_IFFrequency; + *frequency = state->IF; + return 0; +} + +static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + //struct tda_state *state = fe->tuner_priv; + //*bandwidth = priv->bandwidth; + return 0; +} + + +static struct dvb_tuner_ops tuner_ops = { + .info = { + .name = "NXP TDA18212", + .frequency_min = 47125000, + .frequency_max = 865000000, + .frequency_step = 62500 + }, + .init = init, + .sleep = sleep, + .set_params = set_params, + .release = release, + .get_frequency = get_frequency, + .get_if_frequency = get_if, + .get_bandwidth = get_bandwidth, + .get_rf_strength = get_rf_strength, +}; + +struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 adr) +{ + struct tda_state *state; + int stat; + + state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); + if (!state) + return NULL; + state->adr = adr; + state->i2c = i2c; + memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); + init_state(state); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + stat = attach_init(state); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + if (stat < 0) { + kfree(state); + return 0; + } + fe->tuner_priv = state; + return fe; +} + +EXPORT_SYMBOL_GPL(tda18212dd_attach); +MODULE_DESCRIPTION("TDA18212 driver"); +MODULE_AUTHOR("DD"); +MODULE_LICENSE("GPL"); + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18212dd.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,5 @@ +#ifndef _TDA18212DD_H_ +#define _TDA18212DD_H_ +struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 adr); +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.c dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.c --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.c 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.c 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,1301 @@ +/* + * tda18271c2dd: Driver for the TDA18271C2 tuner + * + * Copyright (C) 2010 Digital Devices GmbH + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" + +struct SStandardParam { + s32 m_IFFrequency; + u32 m_BandWidth; + u8 m_EP3_4_0; + u8 m_EB22; +}; + +struct SMap { + u32 m_Frequency; + u8 m_Param; +}; + +struct SMapI { + u32 m_Frequency; + s32 m_Param; +}; + +struct SMap2 { + u32 m_Frequency; + u8 m_Param1; + u8 m_Param2; +}; + +struct SRFBandMap { + u32 m_RF_max; + u32 m_RF1_Default; + u32 m_RF2_Default; + u32 m_RF3_Default; +}; + +enum ERegister { + ID = 0, + TM, + PL, + EP1, EP2, EP3, EP4, EP5, + CPD, CD1, CD2, CD3, + MPD, MD1, MD2, MD3, + EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10, + EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20, + EB21, EB22, EB23, + NUM_REGS +}; + +struct tda_state { + struct i2c_adapter *i2c; + u8 adr; + + u32 m_Frequency; + u32 IF; + + u8 m_IFLevelAnalog; + u8 m_IFLevelDigital; + u8 m_IFLevelDVBC; + u8 m_IFLevelDVBT; + + u8 m_EP4; + u8 m_EP3_Standby; + + bool m_bMaster; + + s32 m_SettlingTime; + + u8 m_Regs[NUM_REGS]; + + /* Tracking filter settings for band 0..6 */ + u32 m_RF1[7]; + s32 m_RF_A1[7]; + s32 m_RF_B1[7]; + u32 m_RF2[7]; + s32 m_RF_A2[7]; + s32 m_RF_B2[7]; + u32 m_RF3[7]; + + u8 m_TMValue_RFCal; /* Calibration temperatur */ + + bool m_bFMInput; /* true to use Pin 8 for FM Radio */ + +}; + +static int PowerScan(struct tda_state *state, + u8 RFBand, u32 RF_in, + u32 *pRF_Out, bool *pbcal); + +static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) +{ + struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, + .buf = data, .len = len} }; + return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +} + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = {.addr = adr, .flags = 0, + .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr); + return -1; + } + return 0; +} + +static int WriteRegs(struct tda_state *state, + u8 SubAddr, u8 *Regs, u16 nRegs) +{ + u8 data[nRegs+1]; + + data[0] = SubAddr; + memcpy(data + 1, Regs, nRegs); + return i2c_write(state->i2c, state->adr, data, nRegs+1); +} + +static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) +{ + u8 msg[2] = {SubAddr, Reg}; + + return i2c_write(state->i2c, state->adr, msg, 2); +} + +static int Read(struct tda_state *state, u8 * Regs) +{ + return i2c_readn(state->i2c, state->adr, Regs, 16); +} + +static int ReadExtented(struct tda_state *state, u8 * Regs) +{ + return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS); +} + +static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo) +{ + return WriteRegs(state, RegFrom, + &state->m_Regs[RegFrom], RegTo-RegFrom+1); +} +static int UpdateReg(struct tda_state *state, u8 Reg) +{ + return WriteReg(state, Reg, state->m_Regs[Reg]); +} + +#include "tda18271c2dd_maps.h" + +static void reset(struct tda_state *state) +{ + u32 ulIFLevelAnalog = 0; + u32 ulIFLevelDigital = 2; + u32 ulIFLevelDVBC = 7; + u32 ulIFLevelDVBT = 6; + u32 ulXTOut = 0; + u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */ + u32 ulSlave = 0; + u32 ulFMInput = 0; + u32 ulSettlingTime = 100; + + state->m_Frequency = 0; + state->m_SettlingTime = 100; + state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2; + state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2; + state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2; + state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2; + + state->m_EP4 = 0x20; + if (ulXTOut != 0) + state->m_EP4 |= 0x40; + + state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F; + state->m_bMaster = (ulSlave == 0); + + state->m_SettlingTime = ulSettlingTime; + + state->m_bFMInput = (ulFMInput == 2); +} + +static bool SearchMap1(struct SMap Map[], + u32 Frequency, u8 *pParam) +{ + int i = 0; + + while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency)) + i += 1; + if (Map[i].m_Frequency == 0) + return false; + *pParam = Map[i].m_Param; + return true; +} + +static bool SearchMap2(struct SMapI Map[], + u32 Frequency, s32 *pParam) +{ + int i = 0; + + while ((Map[i].m_Frequency != 0) && + (Frequency > Map[i].m_Frequency)) + i += 1; + if (Map[i].m_Frequency == 0) + return false; + *pParam = Map[i].m_Param; + return true; +} + +static bool SearchMap3(struct SMap2 Map[], u32 Frequency, + u8 *pParam1, u8 *pParam2) +{ + int i = 0; + + while ((Map[i].m_Frequency != 0) && + (Frequency > Map[i].m_Frequency)) + i += 1; + if (Map[i].m_Frequency == 0) + return false; + *pParam1 = Map[i].m_Param1; + *pParam2 = Map[i].m_Param2; + return true; +} + +static bool SearchMap4(struct SRFBandMap Map[], + u32 Frequency, u8 *pRFBand) +{ + int i = 0; + + while (i < 7 && (Frequency > Map[i].m_RF_max)) + i += 1; + if (i == 7) + return false; + *pRFBand = i; + return true; +} + +static int ThermometerRead(struct tda_state *state, u8 *pTM_Value) +{ + int status = 0; + + do { + u8 Regs[16]; + state->m_Regs[TM] |= 0x10; + status = UpdateReg(state, TM); + if (status < 0) + break; + status = Read(state, Regs); + if (status < 0) + break; + if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) || + ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) { + state->m_Regs[TM] ^= 0x20; + status = UpdateReg(state, TM); + if (status < 0) + break; + msleep(10); + status = Read(state, Regs); + if (status < 0) + break; + } + *pTM_Value = (Regs[TM] & 0x20) + ? m_Thermometer_Map_2[Regs[TM] & 0x0F] + : m_Thermometer_Map_1[Regs[TM] & 0x0F] ; + state->m_Regs[TM] &= ~0x10; /* Thermometer off */ + status = UpdateReg(state, TM); + if (status < 0) + break; + state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */ + status = UpdateReg(state, EP4); + if (status < 0) + break; + } while (0); + + return status; +} + +static int StandBy(struct tda_state *state) +{ + int status = 0; + do { + state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */ + status = UpdateReg(state, EB12); + if (status < 0) + break; + state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */ + status = UpdateReg(state, EB18); + if (status < 0) + break; + state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */ + state->m_Regs[EP3] = state->m_EP3_Standby; + status = UpdateReg(state, EP3); + if (status < 0) + break; + state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */ + status = UpdateRegs(state, EB21, EB23); + if (status < 0) + break; + } while (0); + return status; +} + +static int CalcMainPLL(struct tda_state *state, u32 freq) +{ + + u8 PostDiv; + u8 Div; + u64 OscFreq; + u32 MainDiv; + + if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) + return -EINVAL; + + OscFreq = (u64) freq * (u64) Div; + OscFreq *= (u64) 16384; + do_div(OscFreq, (u64)16000000); + MainDiv = OscFreq; + + state->m_Regs[MPD] = PostDiv & 0x77; + state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F); + state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF); + state->m_Regs[MD3] = (MainDiv & 0xFF); + + return UpdateRegs(state, MPD, MD3); +} + +static int CalcCalPLL(struct tda_state *state, u32 freq) +{ + u8 PostDiv; + u8 Div; + u64 OscFreq; + u32 CalDiv; + + if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div)) + return -EINVAL; + + OscFreq = (u64)freq * (u64)Div; + /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */ + OscFreq *= (u64)16384; + do_div(OscFreq, (u64)16000000); + CalDiv = OscFreq; + + state->m_Regs[CPD] = PostDiv; + state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF); + state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF); + state->m_Regs[CD3] = (CalDiv & 0xFF); + + return UpdateRegs(state, CPD, CD3); +} + +static int CalibrateRF(struct tda_state *state, + u8 RFBand, u32 freq, s32 *pCprog) +{ + int status = 0; + u8 Regs[NUM_REGS]; + do { + u8 BP_Filter = 0; + u8 GainTaper = 0; + u8 RFC_K = 0; + u8 RFC_M = 0; + + state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */ + status = UpdateReg(state, EP4); + if (status < 0) + break; + state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */ + status = UpdateReg(state, EB18); + if (status < 0) + break; + + /* Switching off LT (as datasheet says) causes calibration on C1 to fail */ + /* (Readout of Cprog is allways 255) */ + if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */ + state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */ + + if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) && + SearchMap1(m_GainTaper_Map, freq, &GainTaper) && + SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M))) + return -EINVAL; + + state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter; + state->m_Regs[EP2] = (RFBand << 5) | GainTaper; + + state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2); + + status = UpdateRegs(state, EP1, EP3); + if (status < 0) + break; + status = UpdateReg(state, EB13); + if (status < 0) + break; + + state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */ + status = UpdateReg(state, EB4); + if (status < 0) + break; + + state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */ + status = UpdateReg(state, EB7); + if (status < 0) + break; + + state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */ + status = UpdateReg(state, EB14); + if (status < 0) + break; + + state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */ + status = UpdateReg(state, EB20); + if (status < 0) + break; + + state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */ + status = UpdateRegs(state, EP4, EP5); + if (status < 0) + break; + + status = CalcCalPLL(state, freq); + if (status < 0) + break; + status = CalcMainPLL(state, freq + 1000000); + if (status < 0) + break; + + msleep(5); + status = UpdateReg(state, EP2); + if (status < 0) + break; + status = UpdateReg(state, EP1); + if (status < 0) + break; + status = UpdateReg(state, EP2); + if (status < 0) + break; + status = UpdateReg(state, EP1); + if (status < 0) + break; + + state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */ + status = UpdateReg(state, EB4); + if (status < 0) + break; + + state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */ + status = UpdateReg(state, EB7); + if (status < 0) + break; + msleep(10); + + state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */ + status = UpdateReg(state, EB20); + if (status < 0) + break; + msleep(60); + + state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */ + state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */ + state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */ + status = UpdateReg(state, EB18); + if (status < 0) + break; + status = UpdateRegs(state, EP3, EP4); + if (status < 0) + break; + status = UpdateReg(state, EP1); + if (status < 0) + break; + + status = ReadExtented(state, Regs); + if (status < 0) + break; + + *pCprog = Regs[EB14]; + + } while (0); + return status; +} + +static int RFTrackingFiltersInit(struct tda_state *state, + u8 RFBand) +{ + int status = 0; + + u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default; + u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default; + u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default; + bool bcal = false; + + s32 Cprog_cal1 = 0; + s32 Cprog_table1 = 0; + s32 Cprog_cal2 = 0; + s32 Cprog_table2 = 0; + s32 Cprog_cal3 = 0; + s32 Cprog_table3 = 0; + + state->m_RF_A1[RFBand] = 0; + state->m_RF_B1[RFBand] = 0; + state->m_RF_A2[RFBand] = 0; + state->m_RF_B2[RFBand] = 0; + + do { + status = PowerScan(state, RFBand, RF1, &RF1, &bcal); + if (status < 0) + break; + if (bcal) { + status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1); + if (status < 0) + break; + } + SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1); + if (!bcal) + Cprog_cal1 = Cprog_table1; + state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1; + /* state->m_RF_A1[RF_Band] = ???? */ + + if (RF2 == 0) + break; + + status = PowerScan(state, RFBand, RF2, &RF2, &bcal); + if (status < 0) + break; + if (bcal) { + status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2); + if (status < 0) + break; + } + SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2); + if (!bcal) + Cprog_cal2 = Cprog_table2; + + state->m_RF_A1[RFBand] = + (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) / + ((s32)(RF2) - (s32)(RF1)); + + if (RF3 == 0) + break; + + status = PowerScan(state, RFBand, RF3, &RF3, &bcal); + if (status < 0) + break; + if (bcal) { + status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3); + if (status < 0) + break; + } + SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3); + if (!bcal) + Cprog_cal3 = Cprog_table3; + state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2)); + state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2; + + } while (0); + + state->m_RF1[RFBand] = RF1; + state->m_RF2[RFBand] = RF2; + state->m_RF3[RFBand] = RF3; + +#if 0 + printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__, + RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2, + state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3); +#endif + + return status; +} + +static int PowerScan(struct tda_state *state, + u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal) +{ + int status = 0; + do { + u8 Gain_Taper = 0; + s32 RFC_Cprog = 0; + u8 CID_Target = 0; + u8 CountLimit = 0; + u32 freq_MainPLL; + u8 Regs[NUM_REGS]; + u8 CID_Gain; + s32 Count = 0; + int sign = 1; + bool wait = false; + + if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) && + SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) && + SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) { + + printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__); + return -EINVAL; + } + + state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper; + state->m_Regs[EB14] = (RFC_Cprog); + status = UpdateReg(state, EP2); + if (status < 0) + break; + status = UpdateReg(state, EB14); + if (status < 0) + break; + + freq_MainPLL = RF_in + 1000000; + status = CalcMainPLL(state, freq_MainPLL); + if (status < 0) + break; + msleep(5); + state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */ + status = UpdateReg(state, EP4); + if (status < 0) + break; + status = UpdateReg(state, EP2); /* Launch power measurement */ + if (status < 0) + break; + status = ReadExtented(state, Regs); + if (status < 0) + break; + CID_Gain = Regs[EB10] & 0x3F; + state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */ + + *pRF_Out = RF_in; + + while (CID_Gain < CID_Target) { + freq_MainPLL = RF_in + sign * Count + 1000000; + status = CalcMainPLL(state, freq_MainPLL); + if (status < 0) + break; + msleep(wait ? 5 : 1); + wait = false; + status = UpdateReg(state, EP2); /* Launch power measurement */ + if (status < 0) + break; + status = ReadExtented(state, Regs); + if (status < 0) + break; + CID_Gain = Regs[EB10] & 0x3F; + Count += 200000; + + if (Count < CountLimit * 100000) + continue; + if (sign < 0) + break; + + sign = -sign; + Count = 200000; + wait = true; + } + status = status; + if (status < 0) + break; + if (CID_Gain >= CID_Target) { + *pbcal = true; + *pRF_Out = freq_MainPLL - 1000000; + } else + *pbcal = false; + } while (0); + + return status; +} + +static int PowerScanInit(struct tda_state *state) +{ + int status = 0; + do { + state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12; + state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */ + status = UpdateRegs(state, EP3, EP4); + if (status < 0) + break; + state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */ + status = UpdateReg(state, EB18); + if (status < 0) + break; + state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */ + state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ + status = UpdateRegs(state, EB21, EB23); + if (status < 0) + break; + } while (0); + return status; +} + +static int CalcRFFilterCurve(struct tda_state *state) +{ + int status = 0; + do { + msleep(200); /* Temperature stabilisation */ + status = PowerScanInit(state); + if (status < 0) + break; + status = RFTrackingFiltersInit(state, 0); + if (status < 0) + break; + status = RFTrackingFiltersInit(state, 1); + if (status < 0) + break; + status = RFTrackingFiltersInit(state, 2); + if (status < 0) + break; + status = RFTrackingFiltersInit(state, 3); + if (status < 0) + break; + status = RFTrackingFiltersInit(state, 4); + if (status < 0) + break; + status = RFTrackingFiltersInit(state, 5); + if (status < 0) + break; + status = RFTrackingFiltersInit(state, 6); + if (status < 0) + break; + status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */ + if (status < 0) + break; + } while (0); + + return status; +} + +static int FixedContentsI2CUpdate(struct tda_state *state) +{ + static u8 InitRegs[] = { + 0x08, 0x80, 0xC6, + 0xDF, 0x16, 0x60, 0x80, + 0x80, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xFC, 0x01, 0x84, 0x41, + 0x01, 0x84, 0x40, 0x07, + 0x00, 0x00, 0x96, 0x3F, + 0xC1, 0x00, 0x8F, 0x00, + 0x00, 0x8C, 0x00, 0x20, + 0xB3, 0x48, 0xB0, + }; + int status = 0; + memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1); + do { + status = UpdateRegs(state, TM, EB23); + if (status < 0) + break; + + /* AGC1 gain setup */ + state->m_Regs[EB17] = 0x00; + status = UpdateReg(state, EB17); + if (status < 0) + break; + state->m_Regs[EB17] = 0x03; + status = UpdateReg(state, EB17); + if (status < 0) + break; + state->m_Regs[EB17] = 0x43; + status = UpdateReg(state, EB17); + if (status < 0) + break; + state->m_Regs[EB17] = 0x4C; + status = UpdateReg(state, EB17); + if (status < 0) + break; + + /* IRC Cal Low band */ + state->m_Regs[EP3] = 0x1F; + state->m_Regs[EP4] = 0x66; + state->m_Regs[EP5] = 0x81; + state->m_Regs[CPD] = 0xCC; + state->m_Regs[CD1] = 0x6C; + state->m_Regs[CD2] = 0x00; + state->m_Regs[CD3] = 0x00; + state->m_Regs[MPD] = 0xC5; + state->m_Regs[MD1] = 0x77; + state->m_Regs[MD2] = 0x08; + state->m_Regs[MD3] = 0x00; + status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */ + if (status < 0) + break; + +#if 0 + state->m_Regs[EB4] = 0x61; /* missing in sw */ + status = UpdateReg(state, EB4); + if (status < 0) + break; + msleep(1); + state->m_Regs[EB4] = 0x41; + status = UpdateReg(state, EB4); + if (status < 0) + break; +#endif + + msleep(5); + status = UpdateReg(state, EP1); + if (status < 0) + break; + msleep(5); + + state->m_Regs[EP5] = 0x85; + state->m_Regs[CPD] = 0xCB; + state->m_Regs[CD1] = 0x66; + state->m_Regs[CD2] = 0x70; + status = UpdateRegs(state, EP3, CD3); + if (status < 0) + break; + msleep(5); + status = UpdateReg(state, EP2); + if (status < 0) + break; + msleep(30); + + /* IRC Cal mid band */ + state->m_Regs[EP5] = 0x82; + state->m_Regs[CPD] = 0xA8; + state->m_Regs[CD2] = 0x00; + state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */ + state->m_Regs[MD1] = 0x73; + state->m_Regs[MD2] = 0x1A; + status = UpdateRegs(state, EP3, MD3); + if (status < 0) + break; + + msleep(5); + status = UpdateReg(state, EP1); + if (status < 0) + break; + msleep(5); + + state->m_Regs[EP5] = 0x86; + state->m_Regs[CPD] = 0xA8; + state->m_Regs[CD1] = 0x66; + state->m_Regs[CD2] = 0xA0; + status = UpdateRegs(state, EP3, CD3); + if (status < 0) + break; + msleep(5); + status = UpdateReg(state, EP2); + if (status < 0) + break; + msleep(30); + + /* IRC Cal high band */ + state->m_Regs[EP5] = 0x83; + state->m_Regs[CPD] = 0x98; + state->m_Regs[CD1] = 0x65; + state->m_Regs[CD2] = 0x00; + state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */ + state->m_Regs[MD1] = 0x71; + state->m_Regs[MD2] = 0xCD; + status = UpdateRegs(state, EP3, MD3); + if (status < 0) + break; + msleep(5); + status = UpdateReg(state, EP1); + if (status < 0) + break; + msleep(5); + state->m_Regs[EP5] = 0x87; + state->m_Regs[CD1] = 0x65; + state->m_Regs[CD2] = 0x50; + status = UpdateRegs(state, EP3, CD3); + if (status < 0) + break; + msleep(5); + status = UpdateReg(state, EP2); + if (status < 0) + break; + msleep(30); + + /* Back to normal */ + state->m_Regs[EP4] = 0x64; + status = UpdateReg(state, EP4); + if (status < 0) + break; + status = UpdateReg(state, EP1); + if (status < 0) + break; + + } while (0); + return status; +} + +static int InitCal(struct tda_state *state) +{ + int status = 0; + + do { + status = FixedContentsI2CUpdate(state); + if (status < 0) + break; + status = CalcRFFilterCurve(state); + if (status < 0) + break; + status = StandBy(state); + if (status < 0) + break; + /* m_bInitDone = true; */ + } while (0); + return status; +}; + +static int RFTrackingFiltersCorrection(struct tda_state *state, + u32 Frequency) +{ + int status = 0; + s32 Cprog_table; + u8 RFBand; + u8 dCoverdT; + + if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) || + !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) || + !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT)) + + return -EINVAL; + + do { + u8 TMValue_Current; + u32 RF1 = state->m_RF1[RFBand]; + u32 RF2 = state->m_RF1[RFBand]; + u32 RF3 = state->m_RF1[RFBand]; + s32 RF_A1 = state->m_RF_A1[RFBand]; + s32 RF_B1 = state->m_RF_B1[RFBand]; + s32 RF_A2 = state->m_RF_A2[RFBand]; + s32 RF_B2 = state->m_RF_B2[RFBand]; + s32 Capprox = 0; + int TComp; + + state->m_Regs[EP3] &= ~0xE0; /* Power up */ + status = UpdateReg(state, EP3); + if (status < 0) + break; + + status = ThermometerRead(state, &TMValue_Current); + if (status < 0) + break; + + if (RF3 == 0 || Frequency < RF2) + Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table; + else + Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table; + + TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000; + + Capprox += TComp; + + if (Capprox < 0) + Capprox = 0; + else if (Capprox > 255) + Capprox = 255; + + + /* TODO Temperature compensation. There is defenitely a scale factor */ + /* missing in the datasheet, so leave it out for now. */ + state->m_Regs[EB14] = Capprox; + + status = UpdateReg(state, EB14); + if (status < 0) + break; + + } while (0); + return status; +} + +static int ChannelConfiguration(struct tda_state *state, + u32 Frequency, int Standard) +{ + + s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency; + int status = 0; + + u8 BP_Filter = 0; + u8 RF_Band = 0; + u8 GainTaper = 0; + u8 IR_Meas = 0; + + state->IF = IntermediateFrequency; + /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ + /* get values from tables */ + + if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) && + SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) && + SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) && + SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) { + + printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__); + return -EINVAL; + } + + do { + state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0; + state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */ + + /* m_EP4 default for XToutOn, CAL_Mode (0) */ + state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog); + /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */ + if (Standard <= HF_AnalogMax) + state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog; + else if (Standard <= HF_ATSC) + state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT; + else if (Standard <= HF_DVBC) + state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC; + else + state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; + + if ((Standard == HF_FM_Radio) && state->m_bFMInput) + state->m_Regs[EP4] |= 80; + + state->m_Regs[MPD] &= ~0x80; + if (Standard > HF_AnalogMax) + state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */ + + state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22; + + /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */ + if (Standard == HF_FM_Radio) + state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ + else + state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */ + + status = UpdateRegs(state, EB22, EB23); + if (status < 0) + break; + + state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */ + state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas; + state->m_Regs[EP2] = (RF_Band << 5) | GainTaper; + + state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) | + (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */ + /* AGC1_always_master = 0 */ + /* AGC_firstn = 0 */ + status = UpdateReg(state, EB1); + if (status < 0) + break; + + if (state->m_bMaster) { + status = CalcMainPLL(state, Frequency + IntermediateFrequency); + if (status < 0) + break; + status = UpdateRegs(state, TM, EP5); + if (status < 0) + break; + state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */ + status = UpdateReg(state, EB4); + if (status < 0) + break; + msleep(1); + state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ + status = UpdateReg(state, EB4); + if (status < 0) + break; + } else { + u8 PostDiv = 0; + u8 Div; + status = CalcCalPLL(state, Frequency + IntermediateFrequency); + if (status < 0) + break; + + SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div); + state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77); + status = UpdateReg(state, MPD); + if (status < 0) + break; + status = UpdateRegs(state, TM, EP5); + if (status < 0) + break; + + state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */ + status = UpdateReg(state, EB7); + if (status < 0) + break; + msleep(1); + state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */ + status = UpdateReg(state, EB7); + if (status < 0) + break; + } + msleep(20); + if (Standard != HF_FM_Radio) + state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */ + status = UpdateReg(state, EP3); + if (status < 0) + break; + + } while (0); + return status; +} + +static int sleep(struct dvb_frontend *fe) +{ + struct tda_state *state = fe->tuner_priv; + + StandBy(state); + return 0; +} + +static int init(struct dvb_frontend *fe) +{ + return 0; +} + +static int release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +/* + * As defined on EN 300 429 Annex A and on ITU-T J.83 annex A, the DVB-C + * roll-off factor is 0.15. + * According with the specs, the amount of the needed bandwith is given by: + * Bw = Symbol_rate * (1 + 0.15) + * As such, the maximum symbol rate supported by 6 MHz is + * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds + *NOTE: For ITU-T J.83 Annex C, the roll-off factor is 0.13. So: + * max_symbol_rate = 6 MHz / 1.13 = 5309735 Baud + * That means that an adjustment is needed for Japan, + * but, as currently DRX-K is hardcoded to Annex A, let's stick + * with 0.15 roll-off factor. + */ +#define MAX_SYMBOL_RATE_6MHz 5217391 + +#ifndef USE_API3 +static int set_params(struct dvb_frontend *fe) +#else +static int set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +#endif +{ + struct tda_state *state = fe->tuner_priv; + int status = 0; + int Standard; +#ifndef USE_API3 + u32 bw = fe->dtv_property_cache.bandwidth_hz; + u32 delsys = fe->dtv_property_cache.delivery_system; + + state->m_Frequency = fe->dtv_property_cache.frequency; + + switch (delsys) { + case SYS_DVBT: + case SYS_DVBT2: + switch (bw) { + case 6000000: + Standard = HF_DVBT_6MHZ; + break; + case 7000000: + Standard = HF_DVBT_7MHZ; + break; + case 8000000: + Standard = HF_DVBT_8MHZ; + break; + default: + return -EINVAL; + } + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + if (bw <= 6000000) + Standard = HF_DVBC_6MHZ; + else if (bw <= 7000000) + Standard = HF_DVBC_7MHZ; + else + Standard = HF_DVBC_8MHZ; + break; + default: + return -EINVAL; + } + do { + status = RFTrackingFiltersCorrection(state, state->m_Frequency); + if (status < 0) + break; + status = ChannelConfiguration(state, state->m_Frequency, + Standard); + if (status < 0) + break; + + msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ + } while (0); +#else + state->m_Frequency = params->frequency; + + if (fe->ops.info.type == FE_OFDM) + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + Standard = HF_DVBT_6MHZ; + break; + case BANDWIDTH_7_MHZ: + Standard = HF_DVBT_7MHZ; + break; + default: + case BANDWIDTH_8_MHZ: + Standard = HF_DVBT_8MHZ; + break; + } + else if (fe->ops.info.type == FE_QAM) { + if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) + Standard = HF_DVBC_6MHZ; + else + Standard = HF_DVBC_8MHZ; + } else + return -EINVAL; + do { + status = RFTrackingFiltersCorrection(state, params->frequency); + if (status < 0) + break; + status = ChannelConfiguration(state, params->frequency, Standard); + if (status < 0) + break; + + msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ + } while (0); +#endif + return status; +} + +#if 0 +static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc) +{ + if (IFAgc < 500) { + /* Scale this from 0 to 50000 */ + *pSignalStrength = IFAgc * 100; + } else { + /* Scale range 500-1500 to 50000-80000 */ + *pSignalStrength = 50000 + (IFAgc - 500) * 30; + } + + return 0; +} +#endif + +static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tda_state *state = fe->tuner_priv; + + *frequency = state->IF; + return 0; +} + +static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + /* struct tda_state *state = fe->tuner_priv; */ + /* *bandwidth = priv->bandwidth; */ + return 0; +} + + +static struct dvb_tuner_ops tuner_ops = { + .info = { + .name = "NXP TDA18271C2D", + .frequency_min = 47125000, + .frequency_max = 865000000, + .frequency_step = 62500 + }, + .init = init, + .sleep = sleep, + .set_params = set_params, + .release = release, + .get_if_frequency = get_if_frequency, + .get_bandwidth = get_bandwidth, +}; + +struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 adr) +{ + struct tda_state *state; + + state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); + if (!state) + return NULL; + + fe->tuner_priv = state; + state->adr = adr; + state->i2c = i2c; + memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); + reset(state); + InitCal(state); + + return fe; +} +EXPORT_SYMBOL_GPL(tda18271c2dd_attach); + +MODULE_DESCRIPTION("TDA18271C2 driver"); +MODULE_AUTHOR("DD"); +MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,16 @@ +#ifndef _TDA18271C2DD_H_ +#define _TDA18271C2DD_H_ +#if defined(CONFIG_DVB_TDA18271C2DD) || (defined(CONFIG_DVB_TDA18271C2DD_MODULE) \ + && defined(MODULE)) +struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 adr); +#else +static inline struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, u8 adr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd_maps.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd_maps.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd_maps.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/frontends/tda18271c2dd_maps.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,814 @@ +enum HF_S { + HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, + HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, + HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, + HF_DVBC_8MHZ, HF_DVBC +}; + +struct SStandardParam m_StandardTable[] = { + { 0, 0, 0x00, 0x00 }, /* HF_None */ + { 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */ + { 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */ + { 7100000, 8000000, 0x1E, 0x2C }, /* HF_G, */ + { 7250000, 8000000, 0x1E, 0x2C }, /* HF_I, */ + { 6900000, 8000000, 0x1E, 0x2C }, /* HF_L, */ + { 1250000, 8000000, 0x1E, 0x2C }, /* HF_L1, */ + { 5400000, 6000000, 0x1C, 0x2C }, /* HF_MN, */ + { 1250000, 500000, 0x18, 0x2C }, /* HF_FM_Radio, */ + { 0, 0, 0x00, 0x00 }, /* HF_AnalogMax (Unused) */ + { 3300000, 6000000, 0x1C, 0x58 }, /* HF_DVBT_6MHZ */ + { 3500000, 7000000, 0x1C, 0x37 }, /* HF_DVBT_7MHZ */ + { 4000000, 8000000, 0x1D, 0x37 }, /* HF_DVBT_8MHZ */ + { 0, 0, 0x00, 0x00 }, /* HF_DVBT (Unused) */ + { 5000000, 6000000, 0x1C, 0x37 }, /* HF_ATSC (center = 3.25 MHz) */ + { 4000000, 6000000, 0x1D, 0x58 }, /* HF_DVBC_6MHZ (Chicago) */ + { 4500000, 7000000, 0x1E, 0x37 }, /* HF_DVBC_7MHZ (not documented by NXP) */ + { 5000000, 8000000, 0x1F, 0x37 }, /* HF_DVBC_8MHZ */ + { 0, 0, 0x00, 0x00 }, /* HF_DVBC (Unused) */ +}; + +struct SMap m_BP_Filter_Map[] = { + { 62000000, 0x00 }, + { 84000000, 0x01 }, + { 100000000, 0x02 }, + { 140000000, 0x03 }, + { 170000000, 0x04 }, + { 180000000, 0x05 }, + { 865000000, 0x06 }, + { 0, 0x00 }, /* Table End */ +}; + +static struct SMapI m_RF_Cal_Map[] = { + { 41000000, 0x0F }, + { 43000000, 0x1C }, + { 45000000, 0x2F }, + { 46000000, 0x39 }, + { 47000000, 0x40 }, + { 47900000, 0x50 }, + { 49100000, 0x16 }, + { 50000000, 0x18 }, + { 51000000, 0x20 }, + { 53000000, 0x28 }, + { 55000000, 0x2B }, + { 56000000, 0x32 }, + { 57000000, 0x35 }, + { 58000000, 0x3E }, + { 59000000, 0x43 }, + { 60000000, 0x4E }, + { 61100000, 0x55 }, + { 63000000, 0x0F }, + { 64000000, 0x11 }, + { 65000000, 0x12 }, + { 66000000, 0x15 }, + { 67000000, 0x16 }, + { 68000000, 0x17 }, + { 70000000, 0x19 }, + { 71000000, 0x1C }, + { 72000000, 0x1D }, + { 73000000, 0x1F }, + { 74000000, 0x20 }, + { 75000000, 0x21 }, + { 76000000, 0x24 }, + { 77000000, 0x25 }, + { 78000000, 0x27 }, + { 80000000, 0x28 }, + { 81000000, 0x29 }, + { 82000000, 0x2D }, + { 83000000, 0x2E }, + { 84000000, 0x2F }, + { 85000000, 0x31 }, + { 86000000, 0x33 }, + { 87000000, 0x34 }, + { 88000000, 0x35 }, + { 89000000, 0x37 }, + { 90000000, 0x38 }, + { 91000000, 0x39 }, + { 93000000, 0x3C }, + { 94000000, 0x3E }, + { 95000000, 0x3F }, + { 96000000, 0x40 }, + { 97000000, 0x42 }, + { 99000000, 0x45 }, + { 100000000, 0x46 }, + { 102000000, 0x48 }, + { 103000000, 0x4A }, + { 105000000, 0x4D }, + { 106000000, 0x4E }, + { 107000000, 0x50 }, + { 108000000, 0x51 }, + { 110000000, 0x54 }, + { 111000000, 0x56 }, + { 112000000, 0x57 }, + { 113000000, 0x58 }, + { 114000000, 0x59 }, + { 115000000, 0x5C }, + { 116000000, 0x5D }, + { 117000000, 0x5F }, + { 119000000, 0x60 }, + { 120000000, 0x64 }, + { 121000000, 0x65 }, + { 122000000, 0x66 }, + { 123000000, 0x68 }, + { 124000000, 0x69 }, + { 125000000, 0x6C }, + { 126000000, 0x6D }, + { 127000000, 0x6E }, + { 128000000, 0x70 }, + { 129000000, 0x71 }, + { 130000000, 0x75 }, + { 131000000, 0x77 }, + { 132000000, 0x78 }, + { 133000000, 0x7B }, + { 134000000, 0x7E }, + { 135000000, 0x81 }, + { 136000000, 0x82 }, + { 137000000, 0x87 }, + { 138000000, 0x88 }, + { 139000000, 0x8D }, + { 140000000, 0x8E }, + { 141000000, 0x91 }, + { 142000000, 0x95 }, + { 143000000, 0x9A }, + { 144000000, 0x9D }, + { 145000000, 0xA1 }, + { 146000000, 0xA2 }, + { 147000000, 0xA4 }, + { 148000000, 0xA9 }, + { 149000000, 0xAE }, + { 150000000, 0xB0 }, + { 151000000, 0xB1 }, + { 152000000, 0xB7 }, + { 152600000, 0xBD }, + { 154000000, 0x20 }, + { 155000000, 0x22 }, + { 156000000, 0x24 }, + { 157000000, 0x25 }, + { 158000000, 0x27 }, + { 159000000, 0x29 }, + { 160000000, 0x2C }, + { 161000000, 0x2D }, + { 163000000, 0x2E }, + { 164000000, 0x2F }, + { 164700000, 0x30 }, + { 166000000, 0x11 }, + { 167000000, 0x12 }, + { 168000000, 0x13 }, + { 169000000, 0x14 }, + { 170000000, 0x15 }, + { 172000000, 0x16 }, + { 173000000, 0x17 }, + { 174000000, 0x18 }, + { 175000000, 0x1A }, + { 176000000, 0x1B }, + { 178000000, 0x1D }, + { 179000000, 0x1E }, + { 180000000, 0x1F }, + { 181000000, 0x20 }, + { 182000000, 0x21 }, + { 183000000, 0x22 }, + { 184000000, 0x24 }, + { 185000000, 0x25 }, + { 186000000, 0x26 }, + { 187000000, 0x27 }, + { 188000000, 0x29 }, + { 189000000, 0x2A }, + { 190000000, 0x2C }, + { 191000000, 0x2D }, + { 192000000, 0x2E }, + { 193000000, 0x2F }, + { 194000000, 0x30 }, + { 195000000, 0x33 }, + { 196000000, 0x35 }, + { 198000000, 0x36 }, + { 200000000, 0x38 }, + { 201000000, 0x3C }, + { 202000000, 0x3D }, + { 203500000, 0x3E }, + { 206000000, 0x0E }, + { 208000000, 0x0F }, + { 212000000, 0x10 }, + { 216000000, 0x11 }, + { 217000000, 0x12 }, + { 218000000, 0x13 }, + { 220000000, 0x14 }, + { 222000000, 0x15 }, + { 225000000, 0x16 }, + { 228000000, 0x17 }, + { 231000000, 0x18 }, + { 234000000, 0x19 }, + { 235000000, 0x1A }, + { 236000000, 0x1B }, + { 237000000, 0x1C }, + { 240000000, 0x1D }, + { 242000000, 0x1E }, + { 244000000, 0x1F }, + { 247000000, 0x20 }, + { 249000000, 0x21 }, + { 252000000, 0x22 }, + { 253000000, 0x23 }, + { 254000000, 0x24 }, + { 256000000, 0x25 }, + { 259000000, 0x26 }, + { 262000000, 0x27 }, + { 264000000, 0x28 }, + { 267000000, 0x29 }, + { 269000000, 0x2A }, + { 271000000, 0x2B }, + { 273000000, 0x2C }, + { 275000000, 0x2D }, + { 277000000, 0x2E }, + { 279000000, 0x2F }, + { 282000000, 0x30 }, + { 284000000, 0x31 }, + { 286000000, 0x32 }, + { 287000000, 0x33 }, + { 290000000, 0x34 }, + { 293000000, 0x35 }, + { 295000000, 0x36 }, + { 297000000, 0x37 }, + { 300000000, 0x38 }, + { 303000000, 0x39 }, + { 305000000, 0x3A }, + { 306000000, 0x3B }, + { 307000000, 0x3C }, + { 310000000, 0x3D }, + { 312000000, 0x3E }, + { 315000000, 0x3F }, + { 318000000, 0x40 }, + { 320000000, 0x41 }, + { 323000000, 0x42 }, + { 324000000, 0x43 }, + { 325000000, 0x44 }, + { 327000000, 0x45 }, + { 331000000, 0x46 }, + { 334000000, 0x47 }, + { 337000000, 0x48 }, + { 339000000, 0x49 }, + { 340000000, 0x4A }, + { 341000000, 0x4B }, + { 343000000, 0x4C }, + { 345000000, 0x4D }, + { 349000000, 0x4E }, + { 352000000, 0x4F }, + { 353000000, 0x50 }, + { 355000000, 0x51 }, + { 357000000, 0x52 }, + { 359000000, 0x53 }, + { 361000000, 0x54 }, + { 362000000, 0x55 }, + { 364000000, 0x56 }, + { 368000000, 0x57 }, + { 370000000, 0x58 }, + { 372000000, 0x59 }, + { 375000000, 0x5A }, + { 376000000, 0x5B }, + { 377000000, 0x5C }, + { 379000000, 0x5D }, + { 382000000, 0x5E }, + { 384000000, 0x5F }, + { 385000000, 0x60 }, + { 386000000, 0x61 }, + { 388000000, 0x62 }, + { 390000000, 0x63 }, + { 393000000, 0x64 }, + { 394000000, 0x65 }, + { 396000000, 0x66 }, + { 397000000, 0x67 }, + { 398000000, 0x68 }, + { 400000000, 0x69 }, + { 402000000, 0x6A }, + { 403000000, 0x6B }, + { 407000000, 0x6C }, + { 408000000, 0x6D }, + { 409000000, 0x6E }, + { 410000000, 0x6F }, + { 411000000, 0x70 }, + { 412000000, 0x71 }, + { 413000000, 0x72 }, + { 414000000, 0x73 }, + { 417000000, 0x74 }, + { 418000000, 0x75 }, + { 420000000, 0x76 }, + { 422000000, 0x77 }, + { 423000000, 0x78 }, + { 424000000, 0x79 }, + { 427000000, 0x7A }, + { 428000000, 0x7B }, + { 429000000, 0x7D }, + { 432000000, 0x7F }, + { 434000000, 0x80 }, + { 435000000, 0x81 }, + { 436000000, 0x83 }, + { 437000000, 0x84 }, + { 438000000, 0x85 }, + { 439000000, 0x86 }, + { 440000000, 0x87 }, + { 441000000, 0x88 }, + { 442000000, 0x89 }, + { 445000000, 0x8A }, + { 446000000, 0x8B }, + { 447000000, 0x8C }, + { 448000000, 0x8E }, + { 449000000, 0x8F }, + { 450000000, 0x90 }, + { 452000000, 0x91 }, + { 453000000, 0x93 }, + { 454000000, 0x94 }, + { 456000000, 0x96 }, + { 457800000, 0x98 }, + { 461000000, 0x11 }, + { 468000000, 0x12 }, + { 472000000, 0x13 }, + { 473000000, 0x14 }, + { 474000000, 0x15 }, + { 481000000, 0x16 }, + { 486000000, 0x17 }, + { 491000000, 0x18 }, + { 498000000, 0x19 }, + { 499000000, 0x1A }, + { 501000000, 0x1B }, + { 506000000, 0x1C }, + { 511000000, 0x1D }, + { 516000000, 0x1E }, + { 520000000, 0x1F }, + { 521000000, 0x20 }, + { 525000000, 0x21 }, + { 529000000, 0x22 }, + { 533000000, 0x23 }, + { 539000000, 0x24 }, + { 541000000, 0x25 }, + { 547000000, 0x26 }, + { 549000000, 0x27 }, + { 551000000, 0x28 }, + { 556000000, 0x29 }, + { 561000000, 0x2A }, + { 563000000, 0x2B }, + { 565000000, 0x2C }, + { 569000000, 0x2D }, + { 571000000, 0x2E }, + { 577000000, 0x2F }, + { 580000000, 0x30 }, + { 582000000, 0x31 }, + { 584000000, 0x32 }, + { 588000000, 0x33 }, + { 591000000, 0x34 }, + { 596000000, 0x35 }, + { 598000000, 0x36 }, + { 603000000, 0x37 }, + { 604000000, 0x38 }, + { 606000000, 0x39 }, + { 612000000, 0x3A }, + { 615000000, 0x3B }, + { 617000000, 0x3C }, + { 621000000, 0x3D }, + { 622000000, 0x3E }, + { 625000000, 0x3F }, + { 632000000, 0x40 }, + { 633000000, 0x41 }, + { 634000000, 0x42 }, + { 642000000, 0x43 }, + { 643000000, 0x44 }, + { 647000000, 0x45 }, + { 650000000, 0x46 }, + { 652000000, 0x47 }, + { 657000000, 0x48 }, + { 661000000, 0x49 }, + { 662000000, 0x4A }, + { 665000000, 0x4B }, + { 667000000, 0x4C }, + { 670000000, 0x4D }, + { 673000000, 0x4E }, + { 676000000, 0x4F }, + { 677000000, 0x50 }, + { 681000000, 0x51 }, + { 683000000, 0x52 }, + { 686000000, 0x53 }, + { 688000000, 0x54 }, + { 689000000, 0x55 }, + { 691000000, 0x56 }, + { 695000000, 0x57 }, + { 698000000, 0x58 }, + { 703000000, 0x59 }, + { 704000000, 0x5A }, + { 705000000, 0x5B }, + { 707000000, 0x5C }, + { 710000000, 0x5D }, + { 712000000, 0x5E }, + { 717000000, 0x5F }, + { 718000000, 0x60 }, + { 721000000, 0x61 }, + { 722000000, 0x62 }, + { 723000000, 0x63 }, + { 725000000, 0x64 }, + { 727000000, 0x65 }, + { 730000000, 0x66 }, + { 732000000, 0x67 }, + { 735000000, 0x68 }, + { 740000000, 0x69 }, + { 741000000, 0x6A }, + { 742000000, 0x6B }, + { 743000000, 0x6C }, + { 745000000, 0x6D }, + { 747000000, 0x6E }, + { 748000000, 0x6F }, + { 750000000, 0x70 }, + { 752000000, 0x71 }, + { 754000000, 0x72 }, + { 757000000, 0x73 }, + { 758000000, 0x74 }, + { 760000000, 0x75 }, + { 763000000, 0x76 }, + { 764000000, 0x77 }, + { 766000000, 0x78 }, + { 767000000, 0x79 }, + { 768000000, 0x7A }, + { 773000000, 0x7B }, + { 774000000, 0x7C }, + { 776000000, 0x7D }, + { 777000000, 0x7E }, + { 778000000, 0x7F }, + { 779000000, 0x80 }, + { 781000000, 0x81 }, + { 783000000, 0x82 }, + { 784000000, 0x83 }, + { 785000000, 0x84 }, + { 786000000, 0x85 }, + { 793000000, 0x86 }, + { 794000000, 0x87 }, + { 795000000, 0x88 }, + { 797000000, 0x89 }, + { 799000000, 0x8A }, + { 801000000, 0x8B }, + { 802000000, 0x8C }, + { 803000000, 0x8D }, + { 804000000, 0x8E }, + { 810000000, 0x90 }, + { 811000000, 0x91 }, + { 812000000, 0x92 }, + { 814000000, 0x93 }, + { 816000000, 0x94 }, + { 817000000, 0x96 }, + { 818000000, 0x97 }, + { 820000000, 0x98 }, + { 821000000, 0x99 }, + { 822000000, 0x9A }, + { 828000000, 0x9B }, + { 829000000, 0x9D }, + { 830000000, 0x9F }, + { 831000000, 0xA0 }, + { 833000000, 0xA1 }, + { 835000000, 0xA2 }, + { 836000000, 0xA3 }, + { 837000000, 0xA4 }, + { 838000000, 0xA6 }, + { 840000000, 0xA8 }, + { 842000000, 0xA9 }, + { 845000000, 0xAA }, + { 846000000, 0xAB }, + { 847000000, 0xAD }, + { 848000000, 0xAE }, + { 852000000, 0xAF }, + { 853000000, 0xB0 }, + { 858000000, 0xB1 }, + { 860000000, 0xB2 }, + { 861000000, 0xB3 }, + { 862000000, 0xB4 }, + { 863000000, 0xB6 }, + { 864000000, 0xB8 }, + { 865000000, 0xB9 }, + { 0, 0x00 }, /* Table End */ +}; + + +static struct SMap2 m_KM_Map[] = { + { 47900000, 3, 2 }, + { 61100000, 3, 1 }, + { 350000000, 3, 0 }, + { 720000000, 2, 1 }, + { 865000000, 3, 3 }, + { 0, 0x00 }, /* Table End */ +}; + +static struct SMap2 m_Main_PLL_Map[] = { + { 33125000, 0x57, 0xF0 }, + { 35500000, 0x56, 0xE0 }, + { 38188000, 0x55, 0xD0 }, + { 41375000, 0x54, 0xC0 }, + { 45125000, 0x53, 0xB0 }, + { 49688000, 0x52, 0xA0 }, + { 55188000, 0x51, 0x90 }, + { 62125000, 0x50, 0x80 }, + { 66250000, 0x47, 0x78 }, + { 71000000, 0x46, 0x70 }, + { 76375000, 0x45, 0x68 }, + { 82750000, 0x44, 0x60 }, + { 90250000, 0x43, 0x58 }, + { 99375000, 0x42, 0x50 }, + { 110375000, 0x41, 0x48 }, + { 124250000, 0x40, 0x40 }, + { 132500000, 0x37, 0x3C }, + { 142000000, 0x36, 0x38 }, + { 152750000, 0x35, 0x34 }, + { 165500000, 0x34, 0x30 }, + { 180500000, 0x33, 0x2C }, + { 198750000, 0x32, 0x28 }, + { 220750000, 0x31, 0x24 }, + { 248500000, 0x30, 0x20 }, + { 265000000, 0x27, 0x1E }, + { 284000000, 0x26, 0x1C }, + { 305500000, 0x25, 0x1A }, + { 331000000, 0x24, 0x18 }, + { 361000000, 0x23, 0x16 }, + { 397500000, 0x22, 0x14 }, + { 441500000, 0x21, 0x12 }, + { 497000000, 0x20, 0x10 }, + { 530000000, 0x17, 0x0F }, + { 568000000, 0x16, 0x0E }, + { 611000000, 0x15, 0x0D }, + { 662000000, 0x14, 0x0C }, + { 722000000, 0x13, 0x0B }, + { 795000000, 0x12, 0x0A }, + { 883000000, 0x11, 0x09 }, + { 994000000, 0x10, 0x08 }, + { 0, 0x00, 0x00 }, /* Table End */ +}; + +static struct SMap2 m_Cal_PLL_Map[] = { + { 33813000, 0xDD, 0xD0 }, + { 36625000, 0xDC, 0xC0 }, + { 39938000, 0xDB, 0xB0 }, + { 43938000, 0xDA, 0xA0 }, + { 48813000, 0xD9, 0x90 }, + { 54938000, 0xD8, 0x80 }, + { 62813000, 0xD3, 0x70 }, + { 67625000, 0xCD, 0x68 }, + { 73250000, 0xCC, 0x60 }, + { 79875000, 0xCB, 0x58 }, + { 87875000, 0xCA, 0x50 }, + { 97625000, 0xC9, 0x48 }, + { 109875000, 0xC8, 0x40 }, + { 125625000, 0xC3, 0x38 }, + { 135250000, 0xBD, 0x34 }, + { 146500000, 0xBC, 0x30 }, + { 159750000, 0xBB, 0x2C }, + { 175750000, 0xBA, 0x28 }, + { 195250000, 0xB9, 0x24 }, + { 219750000, 0xB8, 0x20 }, + { 251250000, 0xB3, 0x1C }, + { 270500000, 0xAD, 0x1A }, + { 293000000, 0xAC, 0x18 }, + { 319500000, 0xAB, 0x16 }, + { 351500000, 0xAA, 0x14 }, + { 390500000, 0xA9, 0x12 }, + { 439500000, 0xA8, 0x10 }, + { 502500000, 0xA3, 0x0E }, + { 541000000, 0x9D, 0x0D }, + { 586000000, 0x9C, 0x0C }, + { 639000000, 0x9B, 0x0B }, + { 703000000, 0x9A, 0x0A }, + { 781000000, 0x99, 0x09 }, + { 879000000, 0x98, 0x08 }, + { 0, 0x00, 0x00 }, /* Table End */ +}; + +static struct SMap m_GainTaper_Map[] = { + { 45400000, 0x1F }, + { 45800000, 0x1E }, + { 46200000, 0x1D }, + { 46700000, 0x1C }, + { 47100000, 0x1B }, + { 47500000, 0x1A }, + { 47900000, 0x19 }, + { 49600000, 0x17 }, + { 51200000, 0x16 }, + { 52900000, 0x15 }, + { 54500000, 0x14 }, + { 56200000, 0x13 }, + { 57800000, 0x12 }, + { 59500000, 0x11 }, + { 61100000, 0x10 }, + { 67600000, 0x0D }, + { 74200000, 0x0C }, + { 80700000, 0x0B }, + { 87200000, 0x0A }, + { 93800000, 0x09 }, + { 100300000, 0x08 }, + { 106900000, 0x07 }, + { 113400000, 0x06 }, + { 119900000, 0x05 }, + { 126500000, 0x04 }, + { 133000000, 0x03 }, + { 139500000, 0x02 }, + { 146100000, 0x01 }, + { 152600000, 0x00 }, + { 154300000, 0x1F }, + { 156100000, 0x1E }, + { 157800000, 0x1D }, + { 159500000, 0x1C }, + { 161200000, 0x1B }, + { 163000000, 0x1A }, + { 164700000, 0x19 }, + { 170200000, 0x17 }, + { 175800000, 0x16 }, + { 181300000, 0x15 }, + { 186900000, 0x14 }, + { 192400000, 0x13 }, + { 198000000, 0x12 }, + { 203500000, 0x11 }, + { 216200000, 0x14 }, + { 228900000, 0x13 }, + { 241600000, 0x12 }, + { 254400000, 0x11 }, + { 267100000, 0x10 }, + { 279800000, 0x0F }, + { 292500000, 0x0E }, + { 305200000, 0x0D }, + { 317900000, 0x0C }, + { 330700000, 0x0B }, + { 343400000, 0x0A }, + { 356100000, 0x09 }, + { 368800000, 0x08 }, + { 381500000, 0x07 }, + { 394200000, 0x06 }, + { 406900000, 0x05 }, + { 419700000, 0x04 }, + { 432400000, 0x03 }, + { 445100000, 0x02 }, + { 457800000, 0x01 }, + { 476300000, 0x19 }, + { 494800000, 0x18 }, + { 513300000, 0x17 }, + { 531800000, 0x16 }, + { 550300000, 0x15 }, + { 568900000, 0x14 }, + { 587400000, 0x13 }, + { 605900000, 0x12 }, + { 624400000, 0x11 }, + { 642900000, 0x10 }, + { 661400000, 0x0F }, + { 679900000, 0x0E }, + { 698400000, 0x0D }, + { 716900000, 0x0C }, + { 735400000, 0x0B }, + { 753900000, 0x0A }, + { 772500000, 0x09 }, + { 791000000, 0x08 }, + { 809500000, 0x07 }, + { 828000000, 0x06 }, + { 846500000, 0x05 }, + { 865000000, 0x04 }, + { 0, 0x00 }, /* Table End */ +}; + +static struct SMap m_RF_Cal_DC_Over_DT_Map[] = { + { 47900000, 0x00 }, + { 55000000, 0x00 }, + { 61100000, 0x0A }, + { 64000000, 0x0A }, + { 82000000, 0x14 }, + { 84000000, 0x19 }, + { 119000000, 0x1C }, + { 124000000, 0x20 }, + { 129000000, 0x2A }, + { 134000000, 0x32 }, + { 139000000, 0x39 }, + { 144000000, 0x3E }, + { 149000000, 0x3F }, + { 152600000, 0x40 }, + { 154000000, 0x40 }, + { 164700000, 0x41 }, + { 203500000, 0x32 }, + { 353000000, 0x19 }, + { 356000000, 0x1A }, + { 359000000, 0x1B }, + { 363000000, 0x1C }, + { 366000000, 0x1D }, + { 369000000, 0x1E }, + { 373000000, 0x1F }, + { 376000000, 0x20 }, + { 379000000, 0x21 }, + { 383000000, 0x22 }, + { 386000000, 0x23 }, + { 389000000, 0x24 }, + { 393000000, 0x25 }, + { 396000000, 0x26 }, + { 399000000, 0x27 }, + { 402000000, 0x28 }, + { 404000000, 0x29 }, + { 407000000, 0x2A }, + { 409000000, 0x2B }, + { 412000000, 0x2C }, + { 414000000, 0x2D }, + { 417000000, 0x2E }, + { 419000000, 0x2F }, + { 422000000, 0x30 }, + { 424000000, 0x31 }, + { 427000000, 0x32 }, + { 429000000, 0x33 }, + { 432000000, 0x34 }, + { 434000000, 0x35 }, + { 437000000, 0x36 }, + { 439000000, 0x37 }, + { 442000000, 0x38 }, + { 444000000, 0x39 }, + { 447000000, 0x3A }, + { 449000000, 0x3B }, + { 457800000, 0x3C }, + { 465000000, 0x0F }, + { 477000000, 0x12 }, + { 483000000, 0x14 }, + { 502000000, 0x19 }, + { 508000000, 0x1B }, + { 519000000, 0x1C }, + { 522000000, 0x1D }, + { 524000000, 0x1E }, + { 534000000, 0x1F }, + { 549000000, 0x20 }, + { 554000000, 0x22 }, + { 584000000, 0x24 }, + { 589000000, 0x26 }, + { 658000000, 0x27 }, + { 664000000, 0x2C }, + { 669000000, 0x2D }, + { 699000000, 0x2E }, + { 704000000, 0x30 }, + { 709000000, 0x31 }, + { 714000000, 0x32 }, + { 724000000, 0x33 }, + { 729000000, 0x36 }, + { 739000000, 0x38 }, + { 744000000, 0x39 }, + { 749000000, 0x3B }, + { 754000000, 0x3C }, + { 759000000, 0x3D }, + { 764000000, 0x3E }, + { 769000000, 0x3F }, + { 774000000, 0x40 }, + { 779000000, 0x41 }, + { 784000000, 0x43 }, + { 789000000, 0x46 }, + { 794000000, 0x48 }, + { 799000000, 0x4B }, + { 804000000, 0x4F }, + { 809000000, 0x54 }, + { 814000000, 0x59 }, + { 819000000, 0x5D }, + { 824000000, 0x61 }, + { 829000000, 0x68 }, + { 834000000, 0x6E }, + { 839000000, 0x75 }, + { 844000000, 0x7E }, + { 849000000, 0x82 }, + { 854000000, 0x84 }, + { 859000000, 0x8F }, + { 865000000, 0x9A }, + { 0, 0x00 }, /* Table End */ +}; + + +static struct SMap m_IR_Meas_Map[] = { + { 200000000, 0x05 }, + { 400000000, 0x06 }, + { 865000000, 0x07 }, + { 0, 0x00 }, /* Table End */ +}; + +static struct SMap2 m_CID_Target_Map[] = { + { 46000000, 0x04, 18 }, + { 52200000, 0x0A, 15 }, + { 70100000, 0x01, 40 }, + { 136800000, 0x18, 40 }, + { 156700000, 0x18, 40 }, + { 186250000, 0x0A, 40 }, + { 230000000, 0x0A, 40 }, + { 345000000, 0x18, 40 }, + { 426000000, 0x0E, 40 }, + { 489500000, 0x1E, 40 }, + { 697500000, 0x32, 40 }, + { 842000000, 0x3A, 40 }, + { 0, 0x00, 0 }, /* Table End */ +}; + +static struct SRFBandMap m_RF_Band_Map[7] = { + { 47900000, 46000000, 0, 0}, + { 61100000, 52200000, 0, 0}, + { 152600000, 70100000, 136800000, 0}, + { 164700000, 156700000, 0, 0}, + { 203500000, 186250000, 0, 0}, + { 457800000, 230000000, 345000000, 426000000}, + { 865000000, 489500000, 697500000, 842000000}, +}; + +u8 m_Thermometer_Map_1[16] = { + 60, 62, 66, 64, + 74, 72, 68, 70, + 90, 88, 84, 86, + 76, 78, 82, 80, +}; + +u8 m_Thermometer_Map_2[16] = { + 92, 94, 98, 96, + 106, 104, 100, 102, + 122, 120, 116, 118, + 108, 110, 114, 112, +}; diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/Kbuild dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/Kbuild --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/Kbuild 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/Kbuild 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,8 @@ +header-y += audio.h +header-y += ca.h +header-y += dmx.h +header-y += frontend.h +header-y += net.h +header-y += osd.h +header-y += version.h +header-y += video.h diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/audio.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/audio.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/audio.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/audio.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,135 @@ +/* + * audio.h + * + * Copyright (C) 2000 Ralph Metzler + * & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Lesser Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVBAUDIO_H_ +#define _DVBAUDIO_H_ + +#include + +typedef enum { + AUDIO_SOURCE_DEMUX, /* Select the demux as the main source */ + AUDIO_SOURCE_MEMORY /* Select internal memory as the main source */ +} audio_stream_source_t; + + +typedef enum { + AUDIO_STOPPED, /* Device is stopped */ + AUDIO_PLAYING, /* Device is currently playing */ + AUDIO_PAUSED /* Device is paused */ +} audio_play_state_t; + + +typedef enum { + AUDIO_STEREO, + AUDIO_MONO_LEFT, + AUDIO_MONO_RIGHT, + AUDIO_MONO, + AUDIO_STEREO_SWAPPED +} audio_channel_select_t; + + +typedef struct audio_mixer { + unsigned int volume_left; + unsigned int volume_right; + // what else do we need? bass, pass-through, ... +} audio_mixer_t; + + +typedef struct audio_status { + int AV_sync_state; /* sync audio and video? */ + int mute_state; /* audio is muted */ + audio_play_state_t play_state; /* current playback state */ + audio_stream_source_t stream_source; /* current stream source */ + audio_channel_select_t channel_select; /* currently selected channel */ + int bypass_mode; /* pass on audio data to */ + audio_mixer_t mixer_state; /* current mixer state */ +} audio_status_t; /* separate decoder hardware */ + + +typedef +struct audio_karaoke { /* if Vocal1 or Vocal2 are non-zero, they get mixed */ + int vocal1; /* into left and right t at 70% each */ + int vocal2; /* if both, Vocal1 and Vocal2 are non-zero, Vocal1 gets*/ + int melody; /* mixed into the left channel and */ + /* Vocal2 into the right channel at 100% each. */ + /* if Melody is non-zero, the melody channel gets mixed*/ +} audio_karaoke_t; /* into left and right */ + + +typedef __u16 audio_attributes_t; +/* bits: descr. */ +/* 15-13 audio coding mode (0=ac3, 2=mpeg1, 3=mpeg2ext, 4=LPCM, 6=DTS, */ +/* 12 multichannel extension */ +/* 11-10 audio type (0=not spec, 1=language included) */ +/* 9- 8 audio application mode (0=not spec, 1=karaoke, 2=surround) */ +/* 7- 6 Quantization / DRC (mpeg audio: 1=DRC exists)(lpcm: 0=16bit, */ +/* 5- 4 Sample frequency fs (0=48kHz, 1=96kHz) */ +/* 2- 0 number of audio channels (n+1 channels) */ + + +/* for GET_CAPABILITIES and SET_FORMAT, the latter should only set one bit */ +#define AUDIO_CAP_DTS 1 +#define AUDIO_CAP_LPCM 2 +#define AUDIO_CAP_MP1 4 +#define AUDIO_CAP_MP2 8 +#define AUDIO_CAP_MP3 16 +#define AUDIO_CAP_AAC 32 +#define AUDIO_CAP_OGG 64 +#define AUDIO_CAP_SDDS 128 +#define AUDIO_CAP_AC3 256 + +#define AUDIO_STOP _IO('o', 1) +#define AUDIO_PLAY _IO('o', 2) +#define AUDIO_PAUSE _IO('o', 3) +#define AUDIO_CONTINUE _IO('o', 4) +#define AUDIO_SELECT_SOURCE _IO('o', 5) +#define AUDIO_SET_MUTE _IO('o', 6) +#define AUDIO_SET_AV_SYNC _IO('o', 7) +#define AUDIO_SET_BYPASS_MODE _IO('o', 8) +#define AUDIO_CHANNEL_SELECT _IO('o', 9) +#define AUDIO_GET_STATUS _IOR('o', 10, audio_status_t) + +#define AUDIO_GET_CAPABILITIES _IOR('o', 11, unsigned int) +#define AUDIO_CLEAR_BUFFER _IO('o', 12) +#define AUDIO_SET_ID _IO('o', 13) +#define AUDIO_SET_MIXER _IOW('o', 14, audio_mixer_t) +#define AUDIO_SET_STREAMTYPE _IO('o', 15) +#define AUDIO_SET_EXT_ID _IO('o', 16) +#define AUDIO_SET_ATTRIBUTES _IOW('o', 17, audio_attributes_t) +#define AUDIO_SET_KARAOKE _IOW('o', 18, audio_karaoke_t) + +/** + * AUDIO_GET_PTS + * + * Read the 33 bit presentation time stamp as defined + * in ITU T-REC-H.222.0 / ISO/IEC 13818-1. + * + * The PTS should belong to the currently played + * frame if possible, but may also be a value close to it + * like the PTS of the last decoded frame or the last PTS + * extracted by the PES parser. + */ +#define AUDIO_GET_PTS _IOR('o', 19, __u64) +#define AUDIO_BILINGUAL_CHANNEL_SELECT _IO('o', 20) + +#endif /* _DVBAUDIO_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ca.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ca.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ca.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ca.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,90 @@ +/* + * ca.h + * + * Copyright (C) 2000 Ralph Metzler + * & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Lesser Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVBCA_H_ +#define _DVBCA_H_ + +/* slot interface types and info */ + +typedef struct ca_slot_info { + int num; /* slot number */ + + int type; /* CA interface this slot supports */ +#define CA_CI 1 /* CI high level interface */ +#define CA_CI_LINK 2 /* CI link layer level interface */ +#define CA_CI_PHYS 4 /* CI physical layer level interface */ +#define CA_DESCR 8 /* built-in descrambler */ +#define CA_SC 128 /* simple smart card interface */ + + unsigned int flags; +#define CA_CI_MODULE_PRESENT 1 /* module (or card) inserted */ +#define CA_CI_MODULE_READY 2 +} ca_slot_info_t; + + +/* descrambler types and info */ + +typedef struct ca_descr_info { + unsigned int num; /* number of available descramblers (keys) */ + unsigned int type; /* type of supported scrambling system */ +#define CA_ECD 1 +#define CA_NDS 2 +#define CA_DSS 4 +} ca_descr_info_t; + +typedef struct ca_caps { + unsigned int slot_num; /* total number of CA card and module slots */ + unsigned int slot_type; /* OR of all supported types */ + unsigned int descr_num; /* total number of descrambler slots (keys) */ + unsigned int descr_type; /* OR of all supported types */ +} ca_caps_t; + +/* a message to/from a CI-CAM */ +typedef struct ca_msg { + unsigned int index; + unsigned int type; + unsigned int length; + unsigned char msg[256]; +} ca_msg_t; + +typedef struct ca_descr { + unsigned int index; + unsigned int parity; /* 0 == even, 1 == odd */ + unsigned char cw[8]; +} ca_descr_t; + +typedef struct ca_pid { + unsigned int pid; + int index; /* -1 == disable*/ +} ca_pid_t; + +#define CA_RESET _IO('o', 128) +#define CA_GET_CAP _IOR('o', 129, ca_caps_t) +#define CA_GET_SLOT_INFO _IOR('o', 130, ca_slot_info_t) +#define CA_GET_DESCR_INFO _IOR('o', 131, ca_descr_info_t) +#define CA_GET_MSG _IOR('o', 132, ca_msg_t) +#define CA_SEND_MSG _IOW('o', 133, ca_msg_t) +#define CA_SET_DESCR _IOW('o', 134, ca_descr_t) +#define CA_SET_PID _IOW('o', 135, ca_pid_t) + +#endif diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/dmx.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/dmx.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/dmx.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/dmx.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,155 @@ +/* + * dmx.h + * + * Copyright (C) 2000 Marcus Metzler + * & Ralph Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _UAPI_DVBDMX_H_ +#define _UAPI_DVBDMX_H_ + +#include +#ifndef __KERNEL__ +#include +#endif + + +#define DMX_FILTER_SIZE 16 + +typedef enum +{ + DMX_OUT_DECODER, /* Streaming directly to decoder. */ + DMX_OUT_TAP, /* Output going to a memory buffer */ + /* (to be retrieved via the read command).*/ + DMX_OUT_TS_TAP, /* Output multiplexed into a new TS */ + /* (to be retrieved by reading from the */ + /* logical DVR device). */ + DMX_OUT_TSDEMUX_TAP /* Like TS_TAP but retrieved from the DMX device */ +} dmx_output_t; + + +typedef enum +{ + DMX_IN_FRONTEND, /* Input from a front-end device. */ + DMX_IN_DVR /* Input from the logical DVR device. */ +} dmx_input_t; + + +typedef enum dmx_ts_pes +{ + DMX_PES_AUDIO0, + DMX_PES_VIDEO0, + DMX_PES_TELETEXT0, + DMX_PES_SUBTITLE0, + DMX_PES_PCR0, + + DMX_PES_AUDIO1, + DMX_PES_VIDEO1, + DMX_PES_TELETEXT1, + DMX_PES_SUBTITLE1, + DMX_PES_PCR1, + + DMX_PES_AUDIO2, + DMX_PES_VIDEO2, + DMX_PES_TELETEXT2, + DMX_PES_SUBTITLE2, + DMX_PES_PCR2, + + DMX_PES_AUDIO3, + DMX_PES_VIDEO3, + DMX_PES_TELETEXT3, + DMX_PES_SUBTITLE3, + DMX_PES_PCR3, + + DMX_PES_OTHER +} dmx_pes_type_t; + +#define DMX_PES_AUDIO DMX_PES_AUDIO0 +#define DMX_PES_VIDEO DMX_PES_VIDEO0 +#define DMX_PES_TELETEXT DMX_PES_TELETEXT0 +#define DMX_PES_SUBTITLE DMX_PES_SUBTITLE0 +#define DMX_PES_PCR DMX_PES_PCR0 + + +typedef struct dmx_filter +{ + __u8 filter[DMX_FILTER_SIZE]; + __u8 mask[DMX_FILTER_SIZE]; + __u8 mode[DMX_FILTER_SIZE]; +} dmx_filter_t; + + +struct dmx_sct_filter_params +{ + __u16 pid; + dmx_filter_t filter; + __u32 timeout; + __u32 flags; +#define DMX_CHECK_CRC 1 +#define DMX_ONESHOT 2 +#define DMX_IMMEDIATE_START 4 +#define DMX_KERNEL_CLIENT 0x8000 +}; + + +struct dmx_pes_filter_params +{ + __u16 pid; + dmx_input_t input; + dmx_output_t output; + dmx_pes_type_t pes_type; + __u32 flags; +}; + +typedef struct dmx_caps { + __u32 caps; + int num_decoders; +} dmx_caps_t; + +typedef enum { + DMX_SOURCE_FRONT0 = 0, + DMX_SOURCE_FRONT1, + DMX_SOURCE_FRONT2, + DMX_SOURCE_FRONT3, + DMX_SOURCE_DVR0 = 16, + DMX_SOURCE_DVR1, + DMX_SOURCE_DVR2, + DMX_SOURCE_DVR3 +} dmx_source_t; + +struct dmx_stc { + unsigned int num; /* input : which STC? 0..N */ + unsigned int base; /* output: divisor for stc to get 90 kHz clock */ + __u64 stc; /* output: stc in 'base'*90 kHz units */ +}; + + +#define DMX_START _IO('o', 41) +#define DMX_STOP _IO('o', 42) +#define DMX_SET_FILTER _IOW('o', 43, struct dmx_sct_filter_params) +#define DMX_SET_PES_FILTER _IOW('o', 44, struct dmx_pes_filter_params) +#define DMX_SET_BUFFER_SIZE _IO('o', 45) +#define DMX_GET_PES_PIDS _IOR('o', 47, __u16[5]) +#define DMX_GET_CAPS _IOR('o', 48, dmx_caps_t) +#define DMX_SET_SOURCE _IOW('o', 49, dmx_source_t) +#define DMX_GET_STC _IOWR('o', 50, struct dmx_stc) +#define DMX_ADD_PID _IOW('o', 51, __u16) +#define DMX_REMOVE_PID _IOW('o', 52, __u16) + +#endif /* _UAPI_DVBDMX_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/frontend.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/frontend.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/frontend.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/frontend.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,594 @@ +/* + * frontend.h + * + * Copyright (C) 2000 Marcus Metzler + * Ralph Metzler + * Holger Waechtler + * Andre Draszik + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVBFRONTEND_H_ +#define _DVBFRONTEND_H_ + +#include + +typedef enum fe_type { + FE_QPSK, + FE_QAM, + FE_OFDM, + FE_ATSC +} fe_type_t; + + +typedef enum fe_caps { + FE_IS_STUPID = 0, + FE_CAN_INVERSION_AUTO = 0x1, + FE_CAN_FEC_1_2 = 0x2, + FE_CAN_FEC_2_3 = 0x4, + FE_CAN_FEC_3_4 = 0x8, + FE_CAN_FEC_4_5 = 0x10, + FE_CAN_FEC_5_6 = 0x20, + FE_CAN_FEC_6_7 = 0x40, + FE_CAN_FEC_7_8 = 0x80, + FE_CAN_FEC_8_9 = 0x100, + FE_CAN_FEC_AUTO = 0x200, + FE_CAN_QPSK = 0x400, + FE_CAN_QAM_16 = 0x800, + FE_CAN_QAM_32 = 0x1000, + FE_CAN_QAM_64 = 0x2000, + FE_CAN_QAM_128 = 0x4000, + FE_CAN_QAM_256 = 0x8000, + FE_CAN_QAM_AUTO = 0x10000, + FE_CAN_TRANSMISSION_MODE_AUTO = 0x20000, + FE_CAN_BANDWIDTH_AUTO = 0x40000, + FE_CAN_GUARD_INTERVAL_AUTO = 0x80000, + FE_CAN_HIERARCHY_AUTO = 0x100000, + FE_CAN_8VSB = 0x200000, + FE_CAN_16VSB = 0x400000, + FE_HAS_EXTENDED_CAPS = 0x800000, /* We need more bitspace for newer APIs, indicate this. */ + FE_CAN_MULTISTREAM = 0x4000000, /* frontend supports multistream filtering */ + FE_CAN_TURBO_FEC = 0x8000000, /* frontend supports "turbo fec modulation" */ + FE_CAN_2G_MODULATION = 0x10000000, /* frontend supports "2nd generation modulation" (DVB-S2) */ + FE_NEEDS_BENDING = 0x20000000, /* not supported anymore, don't use (frontend requires frequency bending) */ + FE_CAN_RECOVER = 0x40000000, /* frontend can recover from a cable unplug automatically */ + FE_CAN_MUTE_TS = 0x80000000 /* frontend can stop spurious TS data output */ +} fe_caps_t; + + +struct dvb_frontend_info { + char name[128]; + fe_type_t type; /* DEPRECATED. Use DTV_ENUM_DELSYS instead */ + __u32 frequency_min; + __u32 frequency_max; + __u32 frequency_stepsize; + __u32 frequency_tolerance; + __u32 symbol_rate_min; + __u32 symbol_rate_max; + __u32 symbol_rate_tolerance; /* ppm */ + __u32 notifier_delay; /* DEPRECATED */ + fe_caps_t caps; +}; + + +/** + * Check out the DiSEqC bus spec available on http://www.eutelsat.org/ for + * the meaning of this struct... + */ +struct dvb_diseqc_master_cmd { + __u8 msg [6]; /* { framing, address, command, data [3] } */ + __u8 msg_len; /* valid values are 3...6 */ +}; + + +struct dvb_diseqc_slave_reply { + __u8 msg [4]; /* { framing, data [3] } */ + __u8 msg_len; /* valid values are 0...4, 0 means no msg */ + int timeout; /* return from ioctl after timeout ms with */ +}; /* errorcode when no message was received */ + + +typedef enum fe_sec_voltage { + SEC_VOLTAGE_13, + SEC_VOLTAGE_18, + SEC_VOLTAGE_OFF +} fe_sec_voltage_t; + + +typedef enum fe_sec_tone_mode { + SEC_TONE_ON, + SEC_TONE_OFF +} fe_sec_tone_mode_t; + + +typedef enum fe_sec_mini_cmd { + SEC_MINI_A, + SEC_MINI_B +} fe_sec_mini_cmd_t; + + +/** + * enum fe_status - enumerates the possible frontend status + * @FE_HAS_SIGNAL: found something above the noise level + * @FE_HAS_CARRIER: found a DVB signal + * @FE_HAS_VITERBI: FEC is stable + * @FE_HAS_SYNC: found sync bytes + * @FE_HAS_LOCK: everything's working + * @FE_TIMEDOUT: no lock within the last ~2 seconds + * @FE_REINIT: frontend was reinitialized, application is recommended + * to reset DiSEqC, tone and parameters + */ + +typedef enum fe_status { + FE_HAS_SIGNAL = 0x01, + FE_HAS_CARRIER = 0x02, + FE_HAS_VITERBI = 0x04, + FE_HAS_SYNC = 0x08, + FE_HAS_LOCK = 0x10, + FE_TIMEDOUT = 0x20, + FE_REINIT = 0x40, +} fe_status_t; + +typedef enum fe_spectral_inversion { + INVERSION_OFF, + INVERSION_ON, + INVERSION_AUTO +} fe_spectral_inversion_t; + + +typedef enum fe_code_rate { + FEC_NONE = 0, + FEC_1_2, + FEC_2_3, + FEC_3_4, + FEC_4_5, + FEC_5_6, + FEC_6_7, + FEC_7_8, + FEC_8_9, + FEC_AUTO, + FEC_3_5, + FEC_9_10, + FEC_2_5, +} fe_code_rate_t; + + +typedef enum fe_modulation { + QPSK, + QAM_16, + QAM_32, + QAM_64, + QAM_128, + QAM_256, + QAM_AUTO, + VSB_8, + VSB_16, + PSK_8, + APSK_16, + APSK_32, + DQPSK, + QAM_4_NR, +} fe_modulation_t; + +typedef enum fe_transmit_mode { + TRANSMISSION_MODE_2K, + TRANSMISSION_MODE_8K, + TRANSMISSION_MODE_AUTO, + TRANSMISSION_MODE_4K, + TRANSMISSION_MODE_1K, + TRANSMISSION_MODE_16K, + TRANSMISSION_MODE_32K, + TRANSMISSION_MODE_C1, + TRANSMISSION_MODE_C3780, +} fe_transmit_mode_t; + +#if defined(__DVB_CORE__) || !defined (__KERNEL__) +typedef enum fe_bandwidth { + BANDWIDTH_8_MHZ, + BANDWIDTH_7_MHZ, + BANDWIDTH_6_MHZ, + BANDWIDTH_AUTO, + BANDWIDTH_5_MHZ, + BANDWIDTH_10_MHZ, + BANDWIDTH_1_712_MHZ, +} fe_bandwidth_t; +#endif + +typedef enum fe_guard_interval { + GUARD_INTERVAL_1_32, + GUARD_INTERVAL_1_16, + GUARD_INTERVAL_1_8, + GUARD_INTERVAL_1_4, + GUARD_INTERVAL_AUTO, + GUARD_INTERVAL_1_128, + GUARD_INTERVAL_19_128, + GUARD_INTERVAL_19_256, + GUARD_INTERVAL_PN420, + GUARD_INTERVAL_PN595, + GUARD_INTERVAL_PN945, +} fe_guard_interval_t; + + +typedef enum fe_hierarchy { + HIERARCHY_NONE, + HIERARCHY_1, + HIERARCHY_2, + HIERARCHY_4, + HIERARCHY_AUTO +} fe_hierarchy_t; + +enum fe_interleaving { + INTERLEAVING_NONE, + INTERLEAVING_AUTO, + INTERLEAVING_240, + INTERLEAVING_720, +}; + +#if defined(__DVB_CORE__) || !defined (__KERNEL__) +struct dvb_qpsk_parameters { + __u32 symbol_rate; /* symbol rate in Symbols per second */ + fe_code_rate_t fec_inner; /* forward error correction (see above) */ +}; + +struct dvb_qam_parameters { + __u32 symbol_rate; /* symbol rate in Symbols per second */ + fe_code_rate_t fec_inner; /* forward error correction (see above) */ + fe_modulation_t modulation; /* modulation type (see above) */ +}; + +struct dvb_vsb_parameters { + fe_modulation_t modulation; /* modulation type (see above) */ +}; + +struct dvb_ofdm_parameters { + fe_bandwidth_t bandwidth; + fe_code_rate_t code_rate_HP; /* high priority stream code rate */ + fe_code_rate_t code_rate_LP; /* low priority stream code rate */ + fe_modulation_t constellation; /* modulation type (see above) */ + fe_transmit_mode_t transmission_mode; + fe_guard_interval_t guard_interval; + fe_hierarchy_t hierarchy_information; +}; + + +struct dvb_frontend_parameters { + __u32 frequency; /* (absolute) frequency in Hz for QAM/OFDM/ATSC */ + /* intermediate frequency in kHz for QPSK */ + fe_spectral_inversion_t inversion; + union { + struct dvb_qpsk_parameters qpsk; + struct dvb_qam_parameters qam; + struct dvb_ofdm_parameters ofdm; + struct dvb_vsb_parameters vsb; + } u; +}; + +struct dvb_frontend_event { + fe_status_t status; + struct dvb_frontend_parameters parameters; +}; +#endif + +/* S2API Commands */ +#define DTV_UNDEFINED 0 +#define DTV_TUNE 1 +#define DTV_CLEAR 2 +#define DTV_FREQUENCY 3 +#define DTV_MODULATION 4 +#define DTV_BANDWIDTH_HZ 5 +#define DTV_INVERSION 6 +#define DTV_DISEQC_MASTER 7 +#define DTV_SYMBOL_RATE 8 +#define DTV_INNER_FEC 9 +#define DTV_VOLTAGE 10 +#define DTV_TONE 11 +#define DTV_PILOT 12 +#define DTV_ROLLOFF 13 +#define DTV_DISEQC_SLAVE_REPLY 14 + +/* Basic enumeration set for querying unlimited capabilities */ +#define DTV_FE_CAPABILITY_COUNT 15 +#define DTV_FE_CAPABILITY 16 +#define DTV_DELIVERY_SYSTEM 17 + +/* ISDB-T and ISDB-Tsb */ +#define DTV_ISDBT_PARTIAL_RECEPTION 18 +#define DTV_ISDBT_SOUND_BROADCASTING 19 + +#define DTV_ISDBT_SB_SUBCHANNEL_ID 20 +#define DTV_ISDBT_SB_SEGMENT_IDX 21 +#define DTV_ISDBT_SB_SEGMENT_COUNT 22 + +#define DTV_ISDBT_LAYERA_FEC 23 +#define DTV_ISDBT_LAYERA_MODULATION 24 +#define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25 +#define DTV_ISDBT_LAYERA_TIME_INTERLEAVING 26 + +#define DTV_ISDBT_LAYERB_FEC 27 +#define DTV_ISDBT_LAYERB_MODULATION 28 +#define DTV_ISDBT_LAYERB_SEGMENT_COUNT 29 +#define DTV_ISDBT_LAYERB_TIME_INTERLEAVING 30 + +#define DTV_ISDBT_LAYERC_FEC 31 +#define DTV_ISDBT_LAYERC_MODULATION 32 +#define DTV_ISDBT_LAYERC_SEGMENT_COUNT 33 +#define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34 + +#define DTV_API_VERSION 35 + +#define DTV_CODE_RATE_HP 36 +#define DTV_CODE_RATE_LP 37 +#define DTV_GUARD_INTERVAL 38 +#define DTV_TRANSMISSION_MODE 39 +#define DTV_HIERARCHY 40 + +#define DTV_ISDBT_LAYER_ENABLED 41 + +#define DTV_STREAM_ID 42 +#define DTV_ISDBS_TS_ID_LEGACY DTV_STREAM_ID +#define DTV_DVBT2_PLP_ID_LEGACY 43 + +#define DTV_ENUM_DELSYS 44 + +/* ATSC-MH */ +#define DTV_ATSCMH_FIC_VER 45 +#define DTV_ATSCMH_PARADE_ID 46 +#define DTV_ATSCMH_NOG 47 +#define DTV_ATSCMH_TNOG 48 +#define DTV_ATSCMH_SGN 49 +#define DTV_ATSCMH_PRC 50 +#define DTV_ATSCMH_RS_FRAME_MODE 51 +#define DTV_ATSCMH_RS_FRAME_ENSEMBLE 52 +#define DTV_ATSCMH_RS_CODE_MODE_PRI 53 +#define DTV_ATSCMH_RS_CODE_MODE_SEC 54 +#define DTV_ATSCMH_SCCC_BLOCK_MODE 55 +#define DTV_ATSCMH_SCCC_CODE_MODE_A 56 +#define DTV_ATSCMH_SCCC_CODE_MODE_B 57 +#define DTV_ATSCMH_SCCC_CODE_MODE_C 58 +#define DTV_ATSCMH_SCCC_CODE_MODE_D 59 + +#define DTV_INTERLEAVING 60 +#define DTV_LNA 61 + +/* Quality parameters */ +#define DTV_STAT_SIGNAL_STRENGTH 62 +#define DTV_STAT_CNR 63 +#define DTV_STAT_PRE_ERROR_BIT_COUNT 64 +#define DTV_STAT_PRE_TOTAL_BIT_COUNT 65 +#define DTV_STAT_POST_ERROR_BIT_COUNT 66 +#define DTV_STAT_POST_TOTAL_BIT_COUNT 67 +#define DTV_STAT_ERROR_BLOCK_COUNT 68 +#define DTV_STAT_TOTAL_BLOCK_COUNT 69 + +#define DTV_MAX_COMMAND DTV_STAT_TOTAL_BLOCK_COUNT + +typedef enum fe_pilot { + PILOT_ON, + PILOT_OFF, + PILOT_AUTO, +} fe_pilot_t; + +typedef enum fe_rolloff { + ROLLOFF_35, /* Implied value in DVB-S, default for DVB-S2 */ + ROLLOFF_20, + ROLLOFF_25, + ROLLOFF_AUTO, +} fe_rolloff_t; + +typedef enum fe_delivery_system { + SYS_UNDEFINED, + SYS_DVBC_ANNEX_A, + SYS_DVBC_ANNEX_B, + SYS_DVBT, + SYS_DSS, + SYS_DVBS, + SYS_DVBS2, + SYS_DVBH, + SYS_ISDBT, + SYS_ISDBS, + SYS_ISDBC, + SYS_ATSC, + SYS_ATSCMH, + SYS_DTMB, + SYS_CMMB, + SYS_DAB, + SYS_DVBT2, + SYS_TURBO, + SYS_DVBC_ANNEX_C, + SYS_DVBC2, +} fe_delivery_system_t; + +/* backward compatibility */ +#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A +#define SYS_DMBTH SYS_DTMB /* DMB-TH is legacy name, use DTMB instead */ + +/* ATSC-MH */ + +enum atscmh_sccc_block_mode { + ATSCMH_SCCC_BLK_SEP = 0, + ATSCMH_SCCC_BLK_COMB = 1, + ATSCMH_SCCC_BLK_RES = 2, +}; + +enum atscmh_sccc_code_mode { + ATSCMH_SCCC_CODE_HLF = 0, + ATSCMH_SCCC_CODE_QTR = 1, + ATSCMH_SCCC_CODE_RES = 2, +}; + +enum atscmh_rs_frame_ensemble { + ATSCMH_RSFRAME_ENS_PRI = 0, + ATSCMH_RSFRAME_ENS_SEC = 1, +}; + +enum atscmh_rs_frame_mode { + ATSCMH_RSFRAME_PRI_ONLY = 0, + ATSCMH_RSFRAME_PRI_SEC = 1, + ATSCMH_RSFRAME_RES = 2, +}; + +enum atscmh_rs_code_mode { + ATSCMH_RSCODE_211_187 = 0, + ATSCMH_RSCODE_223_187 = 1, + ATSCMH_RSCODE_235_187 = 2, + ATSCMH_RSCODE_RES = 3, +}; + +#define NO_STREAM_ID_FILTER (~0U) +#define LNA_AUTO (~0U) + +struct dtv_cmds_h { + char *name; /* A display name for debugging purposes */ + + __u32 cmd; /* A unique ID */ + + /* Flags */ + __u32 set:1; /* Either a set or get property */ + __u32 buffer:1; /* Does this property use the buffer? */ + __u32 reserved:30; /* Align */ +}; + +/** + * Scale types for the quality parameters. + * @FE_SCALE_NOT_AVAILABLE: That QoS measure is not available. That + * could indicate a temporary or a permanent + * condition. + * @FE_SCALE_DECIBEL: The scale is measured in 0.0001 dB steps, typically + * used on signal measures. + * @FE_SCALE_RELATIVE: The scale is a relative percentual measure, + * ranging from 0 (0%) to 0xffff (100%). + * @FE_SCALE_COUNTER: The scale counts the occurrence of an event, like + * bit error, block error, lapsed time. + */ +enum fecap_scale_params { + FE_SCALE_NOT_AVAILABLE = 0, + FE_SCALE_DECIBEL, + FE_SCALE_RELATIVE, + FE_SCALE_COUNTER +}; + +/** + * struct dtv_stats - Used for reading a DTV status property + * + * @value: value of the measure. Should range from 0 to 0xffff; + * @scale: Filled with enum fecap_scale_params - the scale + * in usage for that parameter + * + * For most delivery systems, this will return a single value for each + * parameter. + * It should be noticed, however, that new OFDM delivery systems like + * ISDB can use different modulation types for each group of carriers. + * On such standards, up to 8 groups of statistics can be provided, one + * for each carrier group (called "layer" on ISDB). + * In order to be consistent with other delivery systems, the first + * value refers to the entire set of carriers ("global"). + * dtv_status:scale should use the value FE_SCALE_NOT_AVAILABLE when + * the value for the entire group of carriers or from one specific layer + * is not provided by the hardware. + * st.len should be filled with the latest filled status + 1. + * + * In other words, for ISDB, those values should be filled like: + * u.st.stat.svalue[0] = global statistics; + * u.st.stat.scale[0] = FE_SCALE_DECIBELS; + * u.st.stat.value[1] = layer A statistics; + * u.st.stat.scale[1] = FE_SCALE_NOT_AVAILABLE (if not available); + * u.st.stat.svalue[2] = layer B statistics; + * u.st.stat.scale[2] = FE_SCALE_DECIBELS; + * u.st.stat.svalue[3] = layer C statistics; + * u.st.stat.scale[3] = FE_SCALE_DECIBELS; + * u.st.len = 4; + */ +struct dtv_stats { + __u8 scale; /* enum fecap_scale_params type */ + union { + __u64 uvalue; /* for counters and relative scales */ + __s64 svalue; /* for 0.0001 dB measures */ + }; +} __attribute__ ((packed)); + + +#define MAX_DTV_STATS 4 + +struct dtv_fe_stats { + __u8 len; + struct dtv_stats stat[MAX_DTV_STATS]; +} __attribute__ ((packed)); + +struct dtv_property { + __u32 cmd; + __u32 reserved[3]; + union { + __u32 data; + struct dtv_fe_stats st; + struct { + __u8 data[32]; + __u32 len; + __u32 reserved1[3]; + void *reserved2; + } buffer; + } u; + int result; +} __attribute__ ((packed)); + +/* num of properties cannot exceed DTV_IOCTL_MAX_MSGS per ioctl */ +#define DTV_IOCTL_MAX_MSGS 64 + +struct dtv_properties { + __u32 num; + struct dtv_property *props; +}; + +#define FE_SET_PROPERTY _IOW('o', 82, struct dtv_properties) +#define FE_GET_PROPERTY _IOR('o', 83, struct dtv_properties) + + +/** + * When set, this flag will disable any zigzagging or other "normal" tuning + * behaviour. Additionally, there will be no automatic monitoring of the lock + * status, and hence no frontend events will be generated. If a frontend device + * is closed, this flag will be automatically turned off when the device is + * reopened read-write. + */ +#define FE_TUNE_MODE_ONESHOT 0x01 + + +#define FE_GET_INFO _IOR('o', 61, struct dvb_frontend_info) + +#define FE_DISEQC_RESET_OVERLOAD _IO('o', 62) +#define FE_DISEQC_SEND_MASTER_CMD _IOW('o', 63, struct dvb_diseqc_master_cmd) +#define FE_DISEQC_RECV_SLAVE_REPLY _IOR('o', 64, struct dvb_diseqc_slave_reply) +#define FE_DISEQC_SEND_BURST _IO('o', 65) /* fe_sec_mini_cmd_t */ + +#define FE_SET_TONE _IO('o', 66) /* fe_sec_tone_mode_t */ +#define FE_SET_VOLTAGE _IO('o', 67) /* fe_sec_voltage_t */ +#define FE_ENABLE_HIGH_LNB_VOLTAGE _IO('o', 68) /* int */ + +#define FE_READ_STATUS _IOR('o', 69, fe_status_t) +#define FE_READ_BER _IOR('o', 70, __u32) +#define FE_READ_SIGNAL_STRENGTH _IOR('o', 71, __u16) +#define FE_READ_SNR _IOR('o', 72, __u16) +#define FE_READ_UNCORRECTED_BLOCKS _IOR('o', 73, __u32) + +#define FE_SET_FRONTEND _IOW('o', 76, struct dvb_frontend_parameters) +#define FE_GET_FRONTEND _IOR('o', 77, struct dvb_frontend_parameters) +#define FE_SET_FRONTEND_TUNE_MODE _IO('o', 81) /* unsigned int */ +#define FE_GET_EVENT _IOR('o', 78, struct dvb_frontend_event) + +#define FE_DISHNETWORK_SEND_LEGACY_CMD _IO('o', 80) /* unsigned int */ + +#endif /*_DVBFRONTEND_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/mod.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/mod.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/mod.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/mod.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,23 @@ +#ifndef _UAPI_DVBMOD_H_ +#define _UAPI_DVBMOD_H_ + +#include +#include "frontend.h" + +struct dvb_mod_params { + __u32 base_frequency; + __u32 attenuator; +}; + +struct dvb_mod_channel_params { + enum fe_modulation modulation; + + __u32 rate_increment; + +}; + + +#define DVB_MOD_SET _IOW('o', 208, struct dvb_mod_params) +#define DVB_MOD_CHANNEL_SET _IOW('o', 209, struct dvb_mod_channel_params) + +#endif /*_UAPI_DVBMOD_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/net.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/net.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/net.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/net.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,52 @@ +/* + * net.h + * + * Copyright (C) 2000 Marcus Metzler + * & Ralph Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVBNET_H_ +#define _DVBNET_H_ + +#include + +struct dvb_net_if { + __u16 pid; + __u16 if_num; + __u8 feedtype; +#define DVB_NET_FEEDTYPE_MPE 0 /* multi protocol encapsulation */ +#define DVB_NET_FEEDTYPE_ULE 1 /* ultra lightweight encapsulation */ +}; + + +#define NET_ADD_IF _IOWR('o', 52, struct dvb_net_if) +#define NET_REMOVE_IF _IO('o', 53) +#define NET_GET_IF _IOWR('o', 54, struct dvb_net_if) + + +/* binary compatibility cruft: */ +struct __dvb_net_if_old { + __u16 pid; + __u16 if_num; +}; +#define __NET_ADD_IF_OLD _IOWR('o', 52, struct __dvb_net_if_old) +#define __NET_GET_IF_OLD _IOWR('o', 54, struct __dvb_net_if_old) + + +#endif /*_DVBNET_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ns.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ns.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ns.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/ns.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,68 @@ +#ifndef _UAPI_DVBNS_H_ +#define _UAPI_DVBNS_H_ + +#include + +struct dvb_ns_params { + __u8 smac[6]; + __u8 dmac[6]; + __u8 sip[16]; + __u8 dip[16]; + __u16 sport; + __u16 dport; + __u16 sport2; + __u16 dport2; + __u8 ssrc[8]; + __u8 flags; + __u8 qos; + __u16 vlan; + __u8 ttl; +}; + +#define DVB_NS_IPV6 1 +#define DVB_NS_RTP 2 +#define DVB_NS_RTCP 4 +#define DVB_NS_RTP_TO 8 + +struct dvb_ns_rtcp { + __u8 *msg; + __u16 len; +}; + +struct dvb_ns_packet { + __u8 *buf; + __u8 count; +}; + +struct dvb_nsd_ts { + __u16 pid; + __u16 num; + __u16 input; + __u16 timeout; + __u16 len; + __u8 *ts; + __u8 mode; + __u8 table; + + __u8 filter_mask; + __u8 section; + __u16 section_id; +}; + +#define NS_SET_NET _IOW('o', 192, struct dvb_ns_params) +#define NS_START _IO('o', 193) +#define NS_STOP _IO('o', 194) +#define NS_SET_PID _IOW('o', 195, __u16) +#define NS_SET_PIDS _IOW('o', 196, __u8 *) +#define NS_SET_RTCP_MSG _IOW('o', 197, struct dvb_ns_rtcp) + +#define NSD_START_GET_TS _IOWR('o', 198, struct dvb_nsd_ts) +#define NSD_STOP_GET_TS _IOWR('o', 199, struct dvb_nsd_ts) +#define NSD_CANCEL_GET_TS _IO('o', 200) +#define NSD_POLL_GET_TS _IOWR('o', 201, struct dvb_nsd_ts) + +#define NS_SET_PACKETS _IOW('o', 202, struct dvb_ns_packet) +#define NS_INSERT_PACKETS _IOW('o', 203, __u8) +#define NS_SET_CI _IOW('o', 204, __u8) + +#endif /*_UAPI_DVBNS_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/osd.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/osd.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/osd.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/osd.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,144 @@ +/* + * osd.h + * + * Copyright (C) 2001 Ralph Metzler + * & Marcus Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Lesser Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVBOSD_H_ +#define _DVBOSD_H_ + +#include + +typedef enum { + // All functions return -2 on "not open" + OSD_Close=1, // () + // Disables OSD and releases the buffers + // returns 0 on success + OSD_Open, // (x0,y0,x1,y1,BitPerPixel[2/4/8](color&0x0F),mix[0..15](color&0xF0)) + // Opens OSD with this size and bit depth + // returns 0 on success, -1 on DRAM allocation error, -2 on "already open" + OSD_Show, // () + // enables OSD mode + // returns 0 on success + OSD_Hide, // () + // disables OSD mode + // returns 0 on success + OSD_Clear, // () + // Sets all pixel to color 0 + // returns 0 on success + OSD_Fill, // (color) + // Sets all pixel to color + // returns 0 on success + OSD_SetColor, // (color,R{x0},G{y0},B{x1},opacity{y1}) + // set palette entry to , and apply + // R,G,B: 0..255 + // R=Red, G=Green, B=Blue + // opacity=0: pixel opacity 0% (only video pixel shows) + // opacity=1..254: pixel opacity as specified in header + // opacity=255: pixel opacity 100% (only OSD pixel shows) + // returns 0 on success, -1 on error + OSD_SetPalette, // (firstcolor{color},lastcolor{x0},data) + // Set a number of entries in the palette + // sets the entries "firstcolor" through "lastcolor" from the array "data" + // data has 4 byte for each color: + // R,G,B, and a opacity value: 0->transparent, 1..254->mix, 255->pixel + OSD_SetTrans, // (transparency{color}) + // Sets transparency of mixed pixel (0..15) + // returns 0 on success + OSD_SetPixel, // (x0,y0,color) + // sets pixel , to color number + // returns 0 on success, -1 on error + OSD_GetPixel, // (x0,y0) + // returns color number of pixel ,, or -1 + OSD_SetRow, // (x0,y0,x1,data) + // fills pixels x0,y through x1,y with the content of data[] + // returns 0 on success, -1 on clipping all pixel (no pixel drawn) + OSD_SetBlock, // (x0,y0,x1,y1,increment{color},data) + // fills pixels x0,y0 through x1,y1 with the content of data[] + // inc contains the width of one line in the data block, + // inc<=0 uses blockwidth as linewidth + // returns 0 on success, -1 on clipping all pixel + OSD_FillRow, // (x0,y0,x1,color) + // fills pixels x0,y through x1,y with the color + // returns 0 on success, -1 on clipping all pixel + OSD_FillBlock, // (x0,y0,x1,y1,color) + // fills pixels x0,y0 through x1,y1 with the color + // returns 0 on success, -1 on clipping all pixel + OSD_Line, // (x0,y0,x1,y1,color) + // draw a line from x0,y0 to x1,y1 with the color + // returns 0 on success + OSD_Query, // (x0,y0,x1,y1,xasp{color}}), yasp=11 + // fills parameters with the picture dimensions and the pixel aspect ratio + // returns 0 on success + OSD_Test, // () + // draws a test picture. for debugging purposes only + // returns 0 on success +// TODO: remove "test" in final version + OSD_Text, // (x0,y0,size,color,text) + OSD_SetWindow, // (x0) set window with number 0 + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _DVBVERSION_H_ +#define _DVBVERSION_H_ + +#define DVB_API_VERSION 5 +#define DVB_API_VERSION_MINOR 10 + +#endif /*_DVBVERSION_H_*/ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/video.h dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/video.h --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/video.h 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/include/linux/dvb/video.h 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,274 @@ +/* + * video.h + * + * Copyright (C) 2000 Marcus Metzler + * & Ralph Metzler + * for convergence integrated media GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#ifndef _UAPI_DVBVIDEO_H_ +#define _UAPI_DVBVIDEO_H_ + +#include +#ifndef __KERNEL__ +#include +#include +#endif + +typedef enum { + VIDEO_FORMAT_4_3, /* Select 4:3 format */ + VIDEO_FORMAT_16_9, /* Select 16:9 format. */ + VIDEO_FORMAT_221_1 /* 2.21:1 */ +} video_format_t; + + +typedef enum { + VIDEO_SYSTEM_PAL, + VIDEO_SYSTEM_NTSC, + VIDEO_SYSTEM_PALN, + VIDEO_SYSTEM_PALNc, + VIDEO_SYSTEM_PALM, + VIDEO_SYSTEM_NTSC60, + VIDEO_SYSTEM_PAL60, + VIDEO_SYSTEM_PALM60 +} video_system_t; + + +typedef enum { + VIDEO_PAN_SCAN, /* use pan and scan format */ + VIDEO_LETTER_BOX, /* use letterbox format */ + VIDEO_CENTER_CUT_OUT /* use center cut out format */ +} video_displayformat_t; + +typedef struct { + int w; + int h; + video_format_t aspect_ratio; +} video_size_t; + +typedef enum { + VIDEO_SOURCE_DEMUX, /* Select the demux as the main source */ + VIDEO_SOURCE_MEMORY /* If this source is selected, the stream + comes from the user through the write + system call */ +} video_stream_source_t; + + +typedef enum { + VIDEO_STOPPED, /* Video is stopped */ + VIDEO_PLAYING, /* Video is currently playing */ + VIDEO_FREEZED /* Video is freezed */ +} video_play_state_t; + + +/* Decoder commands */ +#define VIDEO_CMD_PLAY (0) +#define VIDEO_CMD_STOP (1) +#define VIDEO_CMD_FREEZE (2) +#define VIDEO_CMD_CONTINUE (3) + +/* Flags for VIDEO_CMD_FREEZE */ +#define VIDEO_CMD_FREEZE_TO_BLACK (1 << 0) + +/* Flags for VIDEO_CMD_STOP */ +#define VIDEO_CMD_STOP_TO_BLACK (1 << 0) +#define VIDEO_CMD_STOP_IMMEDIATELY (1 << 1) + +/* Play input formats: */ +/* The decoder has no special format requirements */ +#define VIDEO_PLAY_FMT_NONE (0) +/* The decoder requires full GOPs */ +#define VIDEO_PLAY_FMT_GOP (1) + +/* The structure must be zeroed before use by the application + This ensures it can be extended safely in the future. */ +struct video_command { + __u32 cmd; + __u32 flags; + union { + struct { + __u64 pts; + } stop; + + struct { + /* 0 or 1000 specifies normal speed, + 1 specifies forward single stepping, + -1 specifies backward single stepping, + >1: playback at speed/1000 of the normal speed, + <-1: reverse playback at (-speed/1000) of the normal speed. */ + __s32 speed; + __u32 format; + } play; + + struct { + __u32 data[16]; + } raw; + }; +}; + +/* FIELD_UNKNOWN can be used if the hardware does not know whether + the Vsync is for an odd, even or progressive (i.e. non-interlaced) + field. */ +#define VIDEO_VSYNC_FIELD_UNKNOWN (0) +#define VIDEO_VSYNC_FIELD_ODD (1) +#define VIDEO_VSYNC_FIELD_EVEN (2) +#define VIDEO_VSYNC_FIELD_PROGRESSIVE (3) + +struct video_event { + __s32 type; +#define VIDEO_EVENT_SIZE_CHANGED 1 +#define VIDEO_EVENT_FRAME_RATE_CHANGED 2 +#define VIDEO_EVENT_DECODER_STOPPED 3 +#define VIDEO_EVENT_VSYNC 4 + __kernel_time_t timestamp; + union { + video_size_t size; + unsigned int frame_rate; /* in frames per 1000sec */ + unsigned char vsync_field; /* unknown/odd/even/progressive */ + } u; +}; + + +struct video_status { + int video_blank; /* blank video on freeze? */ + video_play_state_t play_state; /* current state of playback */ + video_stream_source_t stream_source; /* current source (demux/memory) */ + video_format_t video_format; /* current aspect ratio of stream*/ + video_displayformat_t display_format;/* selected cropping mode */ +}; + + +struct video_still_picture { + char __user *iFrame; /* pointer to a single iframe in memory */ + __s32 size; +}; + + +typedef +struct video_highlight { + int active; /* 1=show highlight, 0=hide highlight */ + __u8 contrast1; /* 7- 4 Pattern pixel contrast */ + /* 3- 0 Background pixel contrast */ + __u8 contrast2; /* 7- 4 Emphasis pixel-2 contrast */ + /* 3- 0 Emphasis pixel-1 contrast */ + __u8 color1; /* 7- 4 Pattern pixel color */ + /* 3- 0 Background pixel color */ + __u8 color2; /* 7- 4 Emphasis pixel-2 color */ + /* 3- 0 Emphasis pixel-1 color */ + __u32 ypos; /* 23-22 auto action mode */ + /* 21-12 start y */ + /* 9- 0 end y */ + __u32 xpos; /* 23-22 button color number */ + /* 21-12 start x */ + /* 9- 0 end x */ +} video_highlight_t; + + +typedef struct video_spu { + int active; + int stream_id; +} video_spu_t; + + +typedef struct video_spu_palette { /* SPU Palette information */ + int length; + __u8 __user *palette; +} video_spu_palette_t; + + +typedef struct video_navi_pack { + int length; /* 0 ... 1024 */ + __u8 data[1024]; +} video_navi_pack_t; + + +typedef __u16 video_attributes_t; +/* bits: descr. */ +/* 15-14 Video compression mode (0=MPEG-1, 1=MPEG-2) */ +/* 13-12 TV system (0=525/60, 1=625/50) */ +/* 11-10 Aspect ratio (0=4:3, 3=16:9) */ +/* 9- 8 permitted display mode on 4:3 monitor (0=both, 1=only pan-sca */ +/* 7 line 21-1 data present in GOP (1=yes, 0=no) */ +/* 6 line 21-2 data present in GOP (1=yes, 0=no) */ +/* 5- 3 source resolution (0=720x480/576, 1=704x480/576, 2=352x480/57 */ +/* 2 source letterboxed (1=yes, 0=no) */ +/* 0 film/camera mode (0=camera, 1=film (625/50 only)) */ + + +/* bit definitions for capabilities: */ +/* can the hardware decode MPEG1 and/or MPEG2? */ +#define VIDEO_CAP_MPEG1 1 +#define VIDEO_CAP_MPEG2 2 +/* can you send a system and/or program stream to video device? + (you still have to open the video and the audio device but only + send the stream to the video device) */ +#define VIDEO_CAP_SYS 4 +#define VIDEO_CAP_PROG 8 +/* can the driver also handle SPU, NAVI and CSS encoded data? + (CSS API is not present yet) */ +#define VIDEO_CAP_SPU 16 +#define VIDEO_CAP_NAVI 32 +#define VIDEO_CAP_CSS 64 + + +#define VIDEO_STOP _IO('o', 21) +#define VIDEO_PLAY _IO('o', 22) +#define VIDEO_FREEZE _IO('o', 23) +#define VIDEO_CONTINUE _IO('o', 24) +#define VIDEO_SELECT_SOURCE _IO('o', 25) +#define VIDEO_SET_BLANK _IO('o', 26) +#define VIDEO_GET_STATUS _IOR('o', 27, struct video_status) +#define VIDEO_GET_EVENT _IOR('o', 28, struct video_event) +#define VIDEO_SET_DISPLAY_FORMAT _IO('o', 29) +#define VIDEO_STILLPICTURE _IOW('o', 30, struct video_still_picture) +#define VIDEO_FAST_FORWARD _IO('o', 31) +#define VIDEO_SLOWMOTION _IO('o', 32) +#define VIDEO_GET_CAPABILITIES _IOR('o', 33, unsigned int) +#define VIDEO_CLEAR_BUFFER _IO('o', 34) +#define VIDEO_SET_ID _IO('o', 35) +#define VIDEO_SET_STREAMTYPE _IO('o', 36) +#define VIDEO_SET_FORMAT _IO('o', 37) +#define VIDEO_SET_SYSTEM _IO('o', 38) +#define VIDEO_SET_HIGHLIGHT _IOW('o', 39, video_highlight_t) +#define VIDEO_SET_SPU _IOW('o', 50, video_spu_t) +#define VIDEO_SET_SPU_PALETTE _IOW('o', 51, video_spu_palette_t) +#define VIDEO_GET_NAVI _IOR('o', 52, video_navi_pack_t) +#define VIDEO_SET_ATTRIBUTES _IO('o', 53) +#define VIDEO_GET_SIZE _IOR('o', 55, video_size_t) +#define VIDEO_GET_FRAME_RATE _IOR('o', 56, unsigned int) + +/** + * VIDEO_GET_PTS + * + * Read the 33 bit presentation time stamp as defined + * in ITU T-REC-H.222.0 / ISO/IEC 13818-1. + * + * The PTS should belong to the currently played + * frame if possible, but may also be a value close to it + * like the PTS of the last decoded frame or the last PTS + * extracted by the PES parser. + */ +#define VIDEO_GET_PTS _IOR('o', 57, __u64) + +/* Read the number of displayed frames since the decoder was started */ +#define VIDEO_GET_FRAME_COUNT _IOR('o', 58, __u64) + +#define VIDEO_COMMAND _IOWR('o', 59, struct video_command) +#define VIDEO_TRY_COMMAND _IOWR('o', 60, struct video_command) + +#endif /* _UAPI_DVBVIDEO_H_ */ diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/dbvals.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/dbvals.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/dbvals.diff 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/dbvals.diff 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,13 @@ +diff --git a/frontends/Makefile b/frontends/Makefile +index 5e00ccf..e1a05ef 100644 +--- a/frontends/Makefile ++++ b/frontends/Makefile +@@ -10,7 +10,7 @@ EXTRA_CFLAGS += -DCONFIG_DVB_STV0367DD + #EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212 + EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212DD + EXTRA_CFLAGS += -DCONFIG_DVB_CXD2843 +-EXTRA_CFLAGS += -DDBVALS ++#EXTRA_CFLAGS += -DDBVALS + NOSTDINC_FLAGS += -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core + + drxk-objs := drxk_hard.o diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/ddbridge.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/ddbridge.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/ddbridge.diff 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/ddbridge.diff 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,37 @@ +diff -r 2cc595391006 a/ddbridge/ddbridge-core.c +--- a/ddbridge/ddbridge-core.c Tue Nov 05 08:03:36 2013 +0100 ++++ b/ddbridge/ddbridge-core.c Tue Nov 05 09:18:10 2013 +0100 +@@ -889,16 +889,19 @@ + return status; + } + +-#ifdef CONFIG_DVB_DRXK ++#if IS_ENABLED(CONFIG_DVB_DRXK) + static int demod_attach_drxk(struct ddb_input *input) + { + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; +- +- fe = dvb->fe = dvb_attach(drxk_attach, +- i2c, 0x29 + (input->nr&1), +- &dvb->fe2); ++ struct drxk_config config; ++ ++ memset(&config, 0, sizeof(config)); ++ config.adr = 0x29 + (input->nr & 1); ++ config.microcode_name = "drxk_a3.mc"; ++ ++ fe = dvb->fe = dvb_attach(drxk_attach, &config, i2c); + if (!fe) { + printk(KERN_ERR "No DRXK found!\n"); + return -ENODEV; +@@ -1442,7 +1445,7 @@ + if (tuner_attach_stv6110(input, 1) < 0) + return -ENODEV; + break; +-#ifdef CONFIG_DVB_DRXK ++#if IS_ENABLED(CONFIG_DVB_DRXK) + case DDB_TUNER_DVBCT_TR: + if (demod_attach_drxk(input) < 0) + return -ENODEV; diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk.diff 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk.diff 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,31774 @@ +diff --git a/frontends/drxk.h b/frontends/drxk.h +index 7d43cbb..9d64e4f 100644 +--- a/frontends/drxk.h ++++ b/frontends/drxk.h +@@ -1,10 +1,57 @@ +-#ifndef _DRXK_H_ +-#define _DRXK_H_ +- +-#include +-#include +- +-extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, +- u8 adr, +- struct dvb_frontend **fe_t); +-#endif ++#ifndef _DRXK_H_ ++#define _DRXK_H_ ++ ++#include ++#include ++ ++/** ++ * struct drxk_config - Configure the initial parameters for DRX-K ++ * ++ * @adr: I2C Address of the DRX-K ++ * @parallel_ts: True means that the device uses parallel TS, ++ * Serial otherwise. ++ * @dynamic_clk: True means that the clock will be dynamically ++ * adjusted. Static clock otherwise. ++ * @enable_merr_cfg: Enable SIO_PDR_PERR_CFG/SIO_PDR_MVAL_CFG. ++ * @single_master: Device is on the single master mode ++ * @no_i2c_bridge: Don't switch the I2C bridge to talk with tuner ++ * @antenna_gpio: GPIO bit used to control the antenna ++ * @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1 ++ * means that 1=DVBC, 0 = DVBT. Zero means the opposite. ++ * @mpeg_out_clk_strength: DRXK Mpeg output clock drive strength. ++ * @microcode_name: Name of the firmware file with the microcode ++ * ++ * On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is ++ * UIO-3. ++ */ ++struct drxk_config { ++ u8 adr; ++ bool single_master; ++ bool no_i2c_bridge; ++ bool parallel_ts; ++ bool dynamic_clk; ++ bool enable_merr_cfg; ++ ++ bool antenna_dvbt; ++ u16 antenna_gpio; ++ ++ u8 mpeg_out_clk_strength; ++ int chunk_size; ++ ++ const char *microcode_name; ++}; ++ ++#if defined(CONFIG_DVB_DRXK) || (defined(CONFIG_DVB_DRXK_MODULE) \ ++ && defined(MODULE)) ++extern struct dvb_frontend *drxk_attach(const struct drxk_config *config, ++ struct i2c_adapter *i2c); ++#else ++static inline struct dvb_frontend *drxk_attach(const struct drxk_config *config, ++ struct i2c_adapter *i2c) ++{ ++ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); ++ return NULL; ++} ++#endif ++ ++#endif +diff --git a/frontends/drxk_hard.c b/frontends/drxk_hard.c +index 53cb65b..60b868f 100644 +--- a/frontends/drxk_hard.c ++++ b/frontends/drxk_hard.c +@@ -1,5097 +1,6457 @@ +-/* +- * drxk_hard: DRX-K DVB-C/T demodulator driver +- * +- * Copyright (C) 2010-2011 Digital Devices GmbH +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 only, as published by the Free Software Foundation. +- * +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +- * 02110-1301, USA +- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "dvb_frontend.h" +-#include "drxk.h" +-#include "drxk_hard.h" +- +-static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); +-static int PowerDownQAM(struct drxk_state *state); +-static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +-static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode); +-static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, +- s32 tunerFreqOffset); +-static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +-static int DVBTStart(struct drxk_state *state); +-static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, +- s32 tunerFreqOffset); +-static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); +-static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); +-static int SwitchAntennaToQAM(struct drxk_state *state); +-static int SwitchAntennaToDVBT(struct drxk_state *state); +- +-static bool IsDVBT(struct drxk_state *state) +-{ +- return state->m_OperationMode == OM_DVBT; +-} +- +-static bool IsQAM(struct drxk_state *state) +-{ +- return state->m_OperationMode == OM_QAM_ITU_A || +- state->m_OperationMode == OM_QAM_ITU_B || +- state->m_OperationMode == OM_QAM_ITU_C; +-} +- +-bool IsA1WithPatchCode(struct drxk_state *state) +-{ +- return state->m_DRXK_A1_PATCH_CODE; +-} +- +-bool IsA1WithRomCode(struct drxk_state *state) +-{ +- return state->m_DRXK_A1_ROM_CODE; +-} +- +-#define NOA1ROM 0 +- +-#ifndef CHK_ERROR +- #define CHK_ERROR(s) if ((status = s) < 0) break +-#endif +- +-#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) +-#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) +- +-#define DEFAULT_MER_83 165 +-#define DEFAULT_MER_93 250 +- +-#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +-#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) +-#endif +- +-#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +-#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) +-#endif +- +-#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH +-#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06) +-#endif +- +-#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 +-#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 +- +-#ifndef DRXK_KI_RAGC_ATV +-#define DRXK_KI_RAGC_ATV 4 +-#endif +-#ifndef DRXK_KI_IAGC_ATV +-#define DRXK_KI_IAGC_ATV 6 +-#endif +-#ifndef DRXK_KI_DAGC_ATV +-#define DRXK_KI_DAGC_ATV 7 +-#endif +- +-#ifndef DRXK_KI_RAGC_QAM +-#define DRXK_KI_RAGC_QAM 3 +-#endif +-#ifndef DRXK_KI_IAGC_QAM +-#define DRXK_KI_IAGC_QAM 4 +-#endif +-#ifndef DRXK_KI_DAGC_QAM +-#define DRXK_KI_DAGC_QAM 7 +-#endif +-#ifndef DRXK_KI_RAGC_DVBT +-#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) +-#endif +-#ifndef DRXK_KI_IAGC_DVBT +-#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) +-#endif +-#ifndef DRXK_KI_DAGC_DVBT +-#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) +-#endif +- +-#ifndef DRXK_AGC_DAC_OFFSET +-#define DRXK_AGC_DAC_OFFSET (0x800) +-#endif +- +-#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ +-#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) +-#endif +- +-#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ +-#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) +-#endif +- +-#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ +-#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) +-#endif +- +-#ifndef DRXK_QAM_SYMBOLRATE_MAX +-#define DRXK_QAM_SYMBOLRATE_MAX (7233000) +-#endif +- +-#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 +-#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 +-#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 +-#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 +-#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 +-#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 +-#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 +-#define DRXK_BL_ROM_OFFSET_UCODE 0 +- +-#define DRXK_BLC_TIMEOUT 100 +- +-#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 +-#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 +- +-#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 +- +-#ifndef DRXK_OFDM_NE_NOTCH_WIDTH +-#define DRXK_OFDM_NE_NOTCH_WIDTH (4) +-#endif +- +-#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) +-#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) +-#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) +-#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) +-#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) +- +-static inline u32 MulDiv32(u32 a, u32 b, u32 c) +-{ +- u64 tmp64; +- +- tmp64 = (u64)a * (u64)b; +- do_div(tmp64, c); +- +- return (u32) tmp64; +-} +- +-inline u32 Frac28a(u32 a, u32 c) +-{ +- int i = 0; +- u32 Q1 = 0; +- u32 R0 = 0; +- +- R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ +- Q1 = a / c; /* integer part, only the 4 least significant bits +- will be visible in the result */ +- +- /* division using radix 16, 7 nibbles in the result */ +- for (i = 0; i < 7; i++) { +- Q1 = (Q1 << 4) | (R0 / c); +- R0 = (R0 % c) << 4; +- } +- /* rounding */ +- if ((R0 >> 3) >= c) +- Q1++; +- +- return Q1; +-} +- +-static u32 Log10Times100(u32 x) +-{ +- static const u8 scale = 15; +- static const u8 indexWidth = 5; +- u8 i = 0; +- u32 y = 0; +- u32 d = 0; +- u32 k = 0; +- u32 r = 0; +- /* +- log2lut[n] = (1< 0; k--) { +- if (x & (((u32)1) << scale)) +- break; +- x <<= 1; +- } +- } else { +- for (k = scale; k < 31 ; k++) { +- if ((x & (((u32)(-1)) << (scale+1))) == 0) +- break; +- x >>= 1; +- } +- } +- /* +- Now x has binary point between bit[scale] and bit[scale-1] +- and 1.0 <= x < 2.0 */ +- +- /* correction for divison: log(x) = log(x/y)+log(y) */ +- y = k * ((((u32)1) << scale) * 200); +- +- /* remove integer part */ +- x &= ((((u32)1) << scale)-1); +- /* get index */ +- i = (u8) (x >> (scale - indexWidth)); +- /* compute delta (x - a) */ +- d = x & ((((u32)1) << (scale - indexWidth)) - 1); +- /* compute log, multiplication (d* (..)) must be within range ! */ +- y += log2lut[i] + +- ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); +- /* Conver to log10() */ +- y /= 108853; /* (log2(10) << scale) */ +- r = (y >> 1); +- /* rounding */ +- if (y & ((u32)1)) +- r++; +- return (r); +-} +- +-/****************************************************************************/ +-/* I2C **********************************************************************/ +-/****************************************************************************/ +- +-static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) +-{ +- struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, +- .buf = val, .len = 1 }}; +- return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +-} +- +-static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +-{ +- struct i2c_msg msg = +- {.addr = adr, .flags = 0, .buf = data, .len = len}; +- +- if (i2c_transfer(adap, &msg, 1) != 1) { +- printk("i2c_write error\n"); +- return -1; +- } +- return 0; +-} +- +-static int i2c_read(struct i2c_adapter *adap, +- u8 adr, u8 *msg, int len, u8 *answ, int alen) +-{ +- struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, +- .buf = msg, .len = len}, +- { .addr = adr, .flags = I2C_M_RD, +- .buf = answ, .len = alen } }; +- if (i2c_transfer(adap, msgs, 2) != 2) { +- printk("i2c_read error\n"); +- return -1; +- } +- return 0; +-} +- +-static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) +-{ +- u8 adr=state->demod_address, mm1[4], mm2[2], len; +-#ifdef I2C_LONG_ADR +- flags |= 0xC0; +-#endif +- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { +- mm1[0] = (((reg << 1) & 0xFF) | 0x01); +- mm1[1] = ((reg >> 16) & 0xFF); +- mm1[2] = ((reg >> 24) & 0xFF) | flags; +- mm1[3] = ((reg >> 7) & 0xFF); +- len = 4; +- } else { +- mm1[0] = ((reg << 1) & 0xFF); +- mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); +- len = 2; +- } +- if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) +- return -1; +- if (data) +- *data = mm2[0] | (mm2[1] << 8); +- return 0; +-} +- +-static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) +-{ +- return Read16(state, reg, data, 0); +-} +- +-static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) +-{ +- u8 adr = state->demod_address, mm1[4], mm2[4], len; +-#ifdef I2C_LONG_ADR +- flags |= 0xC0; +-#endif +- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { +- mm1[0] = (((reg << 1) & 0xFF) | 0x01); +- mm1[1] = ((reg >> 16) & 0xFF); +- mm1[2] = ((reg >> 24) & 0xFF) | flags; +- mm1[3] = ((reg >> 7) & 0xFF); +- len = 4; +- } else { +- mm1[0] = ((reg << 1) & 0xFF); +- mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); +- len = 2; +- } +- if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) +- return -1; +- if (data) +- *data = mm2[0] | (mm2[1] << 8) | +- (mm2[2] << 16) | (mm2[3] << 24); +- return 0; +-} +- +-static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) +-{ +- u8 adr = state->demod_address, mm[6], len; +-#ifdef I2C_LONG_ADR +- flags |= 0xC0; +-#endif +- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { +- mm[0] = (((reg << 1) & 0xFF) | 0x01); +- mm[1] = ((reg >> 16) & 0xFF); +- mm[2] = ((reg >> 24) & 0xFF) | flags; +- mm[3] = ((reg >> 7) & 0xFF); +- len = 4; +- } else { +- mm[0] = ((reg << 1) & 0xFF); +- mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); +- len = 2; +- } +- mm[len] = data & 0xff; +- mm[len+1] = (data >>8) & 0xff; +- if (i2c_write(state->i2c, adr, mm, len + 2) < 0) +- return -1; +- return 0; +-} +- +-static int Write16_0(struct drxk_state *state, u32 reg, u16 data) +-{ +- return Write16(state, reg, data, 0); +-} +- +-static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) +-{ +- u8 adr = state->demod_address, mm[8], len; +-#ifdef I2C_LONG_ADR +- flags |= 0xC0; +-#endif +- if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { +- mm[0] = (((reg << 1) & 0xFF) | 0x01); +- mm[1] = ((reg >> 16) & 0xFF); +- mm[2] = ((reg >> 24) & 0xFF) | flags; +- mm[3] = ((reg >> 7) & 0xFF); +- len = 4; +- } else { +- mm[0] = ((reg << 1) & 0xFF); +- mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); +- len = 2; +- } +- mm[len] = data & 0xff; +- mm[len+1] = (data >> 8) & 0xff; +- mm[len+2] = (data >> 16) & 0xff; +- mm[len+3] = (data >> 24) & 0xff; +- if (i2c_write(state->i2c, adr, mm, len+4) < 0) +- return -1; +- return 0; +-} +- +-static int WriteBlock(struct drxk_state *state, u32 Address, +- const int BlockSize, const u8 pBlock[], u8 Flags) +-{ +- int status = 0, BlkSize = BlockSize; +-#ifdef I2C_LONG_ADR +- Flags |= 0xC0; +-#endif +- while (BlkSize > 0) { +- int Chunk = BlkSize > state->m_ChunkSize ? +- state->m_ChunkSize : BlkSize ; +- u8 *AdrBuf = &state->Chunk[0]; +- u32 AdrLength = 0; +- +- if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { +- AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); +- AdrBuf[1] = ((Address >> 16) & 0xFF); +- AdrBuf[2] = ((Address >> 24) & 0xFF); +- AdrBuf[3] = ((Address >> 7) & 0xFF); +- AdrBuf[2] |= Flags; +- AdrLength = 4; +- if (Chunk == state->m_ChunkSize) +- Chunk -= 2; +- } else { +- AdrBuf[0] = ((Address << 1) & 0xFF); +- AdrBuf[1] = (((Address >> 16) & 0x0F) | +- ((Address >> 18) & 0xF0)); +- AdrLength = 2; +- } +- memcpy(&state->Chunk[AdrLength], pBlock, Chunk); +- status = i2c_write(state->i2c, state->demod_address, +- &state->Chunk[0], Chunk+AdrLength); +- if (status<0) { +- printk("I2C Write error\n"); +- break; +- } +- pBlock += Chunk; +- Address += (Chunk >> 1); +- BlkSize -= Chunk; +- } +- return status; +-} +- +-#ifndef DRXK_MAX_RETRIES_POWERUP +-#define DRXK_MAX_RETRIES_POWERUP 20 +-#endif +- +-int PowerUpDevice(struct drxk_state *state) +-{ +- int status; +- u8 data = 0; +- u16 retryCount = 0; +- +- status = i2c_read1(state->i2c, state->demod_address, &data); +- if (status<0) +- do { +- data = 0; +- if (i2c_write(state->i2c, +- state->demod_address, &data, 1) < 0) +- printk("powerup failed\n"); +- msleep(10); +- retryCount++ ; +- } while (i2c_read1(state->i2c, +- state->demod_address, &data) < 0 && +- (retryCount < DRXK_MAX_RETRIES_POWERUP)); +- if (retryCount >= DRXK_MAX_RETRIES_POWERUP) +- return -1; +- do { +- /* Make sure all clk domains are active */ +- CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, +- SIO_CC_PWD_MODE_LEVEL_NONE)); +- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, +- SIO_CC_UPDATE_KEY)); +- /* Enable pll lock tests */ +- CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); +- state->m_currentPowerMode = DRX_POWER_UP; +- } while (0); +- return status; +-} +- +- +-static int init_state(struct drxk_state *state) +-{ +- u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; +- u32 ulVSBIfAgcOutputLevel = 0; +- u32 ulVSBIfAgcMinLevel = 0; +- u32 ulVSBIfAgcMaxLevel = 0x7FFF; +- u32 ulVSBIfAgcSpeed = 3; +- +- u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; +- u32 ulVSBRfAgcOutputLevel = 0; +- u32 ulVSBRfAgcMinLevel = 0; +- u32 ulVSBRfAgcMaxLevel = 0x7FFF; +- u32 ulVSBRfAgcSpeed = 3; +- u32 ulVSBRfAgcTop = 9500; +- u32 ulVSBRfAgcCutOffCurrent = 4000; +- +- u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; +- u32 ulATVIfAgcOutputLevel = 0; +- u32 ulATVIfAgcMinLevel = 0; +- u32 ulATVIfAgcMaxLevel = 0; +- u32 ulATVIfAgcSpeed = 3; +- +- u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; +- u32 ulATVRfAgcOutputLevel = 0; +- u32 ulATVRfAgcMinLevel = 0; +- u32 ulATVRfAgcMaxLevel = 0; +- u32 ulATVRfAgcTop = 9500; +- u32 ulATVRfAgcCutOffCurrent = 4000; +- u32 ulATVRfAgcSpeed = 3; +- +- u32 ulQual83 = DEFAULT_MER_83; +- u32 ulQual93 = DEFAULT_MER_93; +- +- u32 ulDVBTStaticTSClock = 1; +- u32 ulDVBCStaticTSClock = 1; +- +- u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; +- u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; +- +- /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ +- /* io_pad_cfg_mode output mode is drive always */ +- /* io_pad_cfg_drive is set to power 2 (23 mA) */ +- u32 ulGPIOCfg = 0x0113; +- u32 ulGPIO = 0; +- u32 ulSerialMode = 1; +- u32 ulInvertTSClock = 0; +- u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; +- u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; +- u32 ulDVBTBitrate = 50000000; +- u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; +- +- u32 ulInsertRSByte = 0; +- +- u32 ulRfMirror = 1; +- u32 ulPowerDown = 0; +- +- u32 ulAntennaDVBT = 1; +- u32 ulAntennaDVBC = 0; +- u32 ulAntennaSwitchDVBTDVBC = 0; +- +- state->m_hasLNA = false; +- state->m_hasDVBT= false; +- state->m_hasDVBC= false; +- state->m_hasATV= false; +- state->m_hasOOB = false; +- state->m_hasAudio = false; +- +- state->m_ChunkSize = 124; +- +- state->m_oscClockFreq = 0; +- state->m_smartAntInverted = false; +- state->m_bPDownOpenBridge = false; +- +- /* real system clock frequency in kHz */ +- state->m_sysClockFreq = 151875; +- /* Timing div, 250ns/Psys */ +- /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ +- state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * +- HI_I2C_DELAY) / 1000; +- /* Clipping */ +- if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) +- state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; +- state->m_HICfgWakeUpKey = (state->demod_address << 1); +- /* port/bridge/power down ctrl */ +- state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; +- +- state->m_bPowerDown = (ulPowerDown != 0); +- +- state->m_DRXK_A1_PATCH_CODE = false; +- state->m_DRXK_A1_ROM_CODE = false; +- state->m_DRXK_A2_ROM_CODE = false; +- state->m_DRXK_A3_ROM_CODE = false; +- state->m_DRXK_A2_PATCH_CODE = false; +- state->m_DRXK_A3_PATCH_CODE = false; +- +- /* Init AGC and PGA parameters */ +- /* VSB IF */ +- state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); +- state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); +- state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); +- state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); +- state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); +- state->m_vsbPgaCfg = 140; +- +- /* VSB RF */ +- state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); +- state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); +- state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); +- state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); +- state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); +- state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); +- state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); +- state->m_vsbPreSawCfg.reference = 0x07; +- state->m_vsbPreSawCfg.usePreSaw = true; +- +- state->m_Quality83percent = DEFAULT_MER_83; +- state->m_Quality93percent = DEFAULT_MER_93; +- if (ulQual93 <= 500 && ulQual83 < ulQual93) { +- state->m_Quality83percent = ulQual83; +- state->m_Quality93percent = ulQual93; +- } +- +- /* ATV IF */ +- state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); +- state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); +- state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); +- state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); +- state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); +- +- /* ATV RF */ +- state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); +- state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); +- state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); +- state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); +- state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); +- state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); +- state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); +- state->m_atvPreSawCfg.reference = 0x04; +- state->m_atvPreSawCfg.usePreSaw = true; +- +- +- /* DVBT RF */ +- state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; +- state->m_dvbtRfAgcCfg.outputLevel = 0; +- state->m_dvbtRfAgcCfg.minOutputLevel = 0; +- state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; +- state->m_dvbtRfAgcCfg.top = 0x2100; +- state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; +- state->m_dvbtRfAgcCfg.speed = 1; +- +- +- /* DVBT IF */ +- state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; +- state->m_dvbtIfAgcCfg.outputLevel = 0; +- state->m_dvbtIfAgcCfg.minOutputLevel = 0; +- state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; +- state->m_dvbtIfAgcCfg.top = 13424; +- state->m_dvbtIfAgcCfg.cutOffCurrent = 0; +- state->m_dvbtIfAgcCfg.speed = 3; +- state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; +- state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; +- // state->m_dvbtPgaCfg = 140; +- +- state->m_dvbtPreSawCfg.reference = 4; +- state->m_dvbtPreSawCfg.usePreSaw = false; +- +- /* QAM RF */ +- state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; +- state->m_qamRfAgcCfg.outputLevel = 0; +- state->m_qamRfAgcCfg.minOutputLevel = 6023; +- state->m_qamRfAgcCfg.maxOutputLevel = 27000; +- state->m_qamRfAgcCfg.top = 0x2380; +- state->m_qamRfAgcCfg.cutOffCurrent = 4000; +- state->m_qamRfAgcCfg.speed = 3; +- +- /* QAM IF */ +- state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; +- state->m_qamIfAgcCfg.outputLevel = 0; +- state->m_qamIfAgcCfg.minOutputLevel = 0; +- state->m_qamIfAgcCfg.maxOutputLevel = 9000; +- state->m_qamIfAgcCfg.top = 0x0511; +- state->m_qamIfAgcCfg.cutOffCurrent = 0; +- state->m_qamIfAgcCfg.speed = 3; +- state->m_qamIfAgcCfg.IngainTgtMax = 5119; +- state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; +- +- state->m_qamPgaCfg = 140; +- state->m_qamPreSawCfg.reference = 4; +- state->m_qamPreSawCfg.usePreSaw = false; +- +- state->m_OperationMode = OM_NONE; +- state->m_DrxkState = DRXK_UNINITIALIZED; +- +- /* MPEG output configuration */ +- state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ +- state->m_insertRSByte = false; /* If TRUE; insert RS byte */ +- state->m_enableParallel = true; /* If TRUE; +- parallel out otherwise serial */ +- state->m_invertDATA = false; /* If TRUE; invert DATA signals */ +- state->m_invertERR = false; /* If TRUE; invert ERR signal */ +- state->m_invertSTR = false; /* If TRUE; invert STR signals */ +- state->m_invertVAL = false; /* If TRUE; invert VAL signals */ +- state->m_invertCLK = +- (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ +- state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); +- state->m_DVBCStaticCLK = +- (ulDVBCStaticTSClock != 0); +- /* If TRUE; static MPEG clockrate will be used; +- otherwise clockrate will adapt to the bitrate of the TS */ +- +- state->m_DVBTBitrate = ulDVBTBitrate; +- state->m_DVBCBitrate = ulDVBCBitrate; +- +- state->m_TSDataStrength = (ulTSDataStrength & 0x07); +- state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); +- +- /* Maximum bitrate in b/s in case static clockrate is selected */ +- state->m_mpegTsStaticBitrate = 19392658; +- state->m_disableTEIhandling = false; +- +- if (ulInsertRSByte) +- state->m_insertRSByte = true; +- +- state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; +- if (ulMpegLockTimeOut < 10000) +- state->m_MpegLockTimeOut = ulMpegLockTimeOut; +- state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; +- if (ulDemodLockTimeOut < 10000) +- state->m_DemodLockTimeOut = ulDemodLockTimeOut; +- +- // QAM defaults +- state->m_Constellation = DRX_CONSTELLATION_AUTO; +- state->m_qamInterleaveMode = DRXK_QAM_I12_J17; +- state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/ +- state->m_fecRsPrescale = 1; +- +- state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; +- state->m_agcFastClipCtrlDelay = 0; +- +- state->m_GPIOCfg = (ulGPIOCfg); +- state->m_GPIO = (ulGPIO == 0 ? 0 : 1); +- +- state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1); +- state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1); +- state->m_AntennaSwitchDVBTDVBC = +- (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1); +- +- state->m_bPowerDown = false; +- state->m_currentPowerMode = DRX_POWER_DOWN; +- +- state->m_enableParallel = (ulSerialMode == 0); +- +- state->m_rfmirror = (ulRfMirror == 0); +- state->m_IfAgcPol = false; +- return 0; +-} +- +-static int DRXX_Open(struct drxk_state *state) +-{ +- int status = 0; +- u32 jtag = 0; +- u16 bid = 0; +- u16 key = 0; +- +- do { +- /* stop lock indicator process */ +- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, +- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); +- /* Check device id */ +- CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, +- SIO_TOP_COMM_KEY_KEY)); +- CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); +- CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); +- } while(0); +- return status; +-} +- +-static int GetDeviceCapabilities(struct drxk_state *state) +-{ +- u16 sioPdrOhwCfg = 0; +- u32 sioTopJtagidLo = 0; +- int status; +- +- do { +- /* driver 0.9.0 */ +- /* stop lock indicator process */ +- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, +- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); +- +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); +- CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); +- +- switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { +- case 0: +- /* ignore (bypass ?) */ +- break; +- case 1: +- /* 27 MHz */ +- state->m_oscClockFreq = 27000; +- break; +- case 2: +- /* 20.25 MHz */ +- state->m_oscClockFreq = 20250; +- break; +- case 3: +- /* 4 MHz */ +- state->m_oscClockFreq = 20250; +- break; +- default: +- return -1; +- } +- /* +- Determine device capabilities +- Based on pinning v14 +- */ +- CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, +- &sioTopJtagidLo, 0)); +- /* driver 0.9.0 */ +- switch((sioTopJtagidLo >> 29) & 0xF) { +- case 0: +- state->m_deviceSpin = DRXK_SPIN_A1; +- break; +- case 2: +- state->m_deviceSpin = DRXK_SPIN_A2; +- break; +- case 3: +- state->m_deviceSpin = DRXK_SPIN_A3; +- break; +- default: +- state->m_deviceSpin = DRXK_SPIN_UNKNOWN; +- status = -1; +- break; +- } +- switch ((sioTopJtagidLo>>12)&0xFF) { +- case 0x13: +- /* typeId = DRX3913K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = false; +- state->m_hasAudio = false; +- state->m_hasDVBT = true; +- state->m_hasDVBC = true; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = false; +- state->m_hasGPIO1 = false; +- state->m_hasIRQN = false; +- break; +- case 0x15: +- /* typeId = DRX3915K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = true; +- state->m_hasAudio = false; +- state->m_hasDVBT = true; +- state->m_hasDVBC = false; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = true; +- state->m_hasGPIO1 = true; +- state->m_hasIRQN = false; +- break; +- case 0x16: +- /* typeId = DRX3916K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = true; +- state->m_hasAudio = false; +- state->m_hasDVBT = true; +- state->m_hasDVBC = false; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = true; +- state->m_hasGPIO1 = true; +- state->m_hasIRQN = false; +- break; +- case 0x18: +- /* typeId = DRX3918K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = true; +- state->m_hasAudio = true; +- state->m_hasDVBT = true; +- state->m_hasDVBC = false; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = true; +- state->m_hasGPIO1 = true; +- state->m_hasIRQN = false; +- break; +- case 0x21: +- /* typeId = DRX3921K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = true; +- state->m_hasAudio = true; +- state->m_hasDVBT = true; +- state->m_hasDVBC = true; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = true; +- state->m_hasGPIO1 = true; +- state->m_hasIRQN = false; +- break; +- case 0x23: +- /* typeId = DRX3923K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = true; +- state->m_hasAudio = true; +- state->m_hasDVBT = true; +- state->m_hasDVBC = true; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = true; +- state->m_hasGPIO1 = true; +- state->m_hasIRQN = false; +- break; +- case 0x25: +- /* typeId = DRX3925K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = true; +- state->m_hasAudio = true; +- state->m_hasDVBT = true; +- state->m_hasDVBC = true; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = true; +- state->m_hasGPIO1 = true; +- state->m_hasIRQN = false; +- break; +- case 0x26: +- /* typeId = DRX3926K_TYPE_ID */ +- state->m_hasLNA = false; +- state->m_hasOOB = false; +- state->m_hasATV = true; +- state->m_hasAudio = false; +- state->m_hasDVBT = true; +- state->m_hasDVBC = true; +- state->m_hasSAWSW = true; +- state->m_hasGPIO2 = true; +- state->m_hasGPIO1 = true; +- state->m_hasIRQN = false; +- break; +- default: +- printk("DeviceID not supported = %02x\n", +- ((sioTopJtagidLo>>12)&0xFF)); +- status = -1; +- break; +- } +- } while(0); +- return status; +-} +- +-static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) +-{ +- int status; +- bool powerdown_cmd; +- +- //printk("%s\n", __FUNCTION__); +- +- /* Write command */ +- status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); +- if (status < 0) +- return status; +- if (cmd == SIO_HI_RA_RAM_CMD_RESET) +- msleep(1); +- +- powerdown_cmd = +- (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && +- ((state->m_HICfgCtrl) & +- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == +- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); +- if (powerdown_cmd == false) { +- /* Wait until command rdy */ +- u32 retryCount = 0; +- u16 waitCmd; +- +- do { +- msleep(1); +- retryCount += 1; +- status = Read16(state, SIO_HI_RA_RAM_CMD__A, +- &waitCmd, 0); +- } while ((status < 0) && +- (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0)); +- +- if (status == 0) +- status = Read16(state, SIO_HI_RA_RAM_RES__A, +- pResult, 0); +- } +- return status; +-} +- +-static int HI_CfgCommand(struct drxk_state *state) +-{ +- int status; +- +- mutex_lock(&state->mutex); +- do { +- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A, +- state->m_HICfgTimeout)); +- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A, +- state->m_HICfgCtrl)); +- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A, +- state->m_HICfgWakeUpKey)); +- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A, +- state->m_HICfgBridgeDelay)); +- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A, +- state->m_HICfgTimingDiv)); +- CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A, +- SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); +- CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); +- +- state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; +- } while(0); +- mutex_unlock(&state->mutex); +- return status; +-} +- +-static int InitHI(struct drxk_state *state) +-{ +- state->m_HICfgWakeUpKey = (state->demod_address<<1); +- state->m_HICfgTimeout = 0x96FF; +- /* port/bridge/power down ctrl */ +- state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; +- return HI_CfgCommand(state); +-} +- +-static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) +-{ +- int status = -1; +- u16 sioPdrMclkCfg = 0; +- u16 sioPdrMdxCfg = 0; +- +- do { +- /* stop lock indicator process */ +- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, +- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); +- +- /* MPEG TS pad configuration */ +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); +- +- if (mpegEnable == false) { +- /* Set MPEG TS pads to inputmode */ +- CHK_ERROR(Write16_0(state, +- SIO_PDR_MSTRT_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, +- SIO_PDR_MERR_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, +- SIO_PDR_MCLK_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, +- SIO_PDR_MVAL_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000)); +- } else { +- /* Enable MPEG output */ +- sioPdrMdxCfg = +- ((state->m_TSDataStrength << +- SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); +- sioPdrMclkCfg = ((state->m_TSClockkStrength << +- SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); +- +- CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, +- sioPdrMdxCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, +- 0x0000)); // Disable +- CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, +- 0x0000)); // Disable +- if (state->m_enableParallel == true) { +- /* paralel -> enable MD1 to MD7 */ +- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, +- sioPdrMdxCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, +- sioPdrMdxCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, +- sioPdrMdxCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, +- sioPdrMdxCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, +- sioPdrMdxCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, +- sioPdrMdxCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, +- sioPdrMdxCfg)); +- } else { +- sioPdrMdxCfg = ((state->m_TSDataStrength << +- SIO_PDR_MD0_CFG_DRIVE__B) | +- 0x0003); +- /* serial -> disable MD1 to MD7 */ +- CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, +- 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, +- 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, +- 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, +- 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, +- 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, +- 0x0000)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, +- 0x0000)); +- } +- CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, +- sioPdrMclkCfg)); +- CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, +- sioPdrMdxCfg)); +- } +- /* Enable MB output over MPEG pads and ctl input */ +- CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); +- /* Write nomagic word to enable pdr reg write */ +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); +- } while(0); +- return status; +-} +- +-static int MPEGTSDisable(struct drxk_state *state) +-{ +- return MPEGTSConfigurePins(state, false); +-} +- +-static int BLChainCmd(struct drxk_state *state, +- u16 romOffset, u16 nrOfElements, u32 timeOut) +-{ +- u16 blStatus = 0; +- int status; +- unsigned long end; +- +- mutex_lock(&state->mutex); +- do { +- CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, +- SIO_BL_MODE_CHAIN)); +- CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, +- romOffset)); +- CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, +- nrOfElements)); +- CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, +- SIO_BL_ENABLE_ON)); +- end=jiffies+msecs_to_jiffies(timeOut); +- +- do { +- msleep(1); +- CHK_ERROR(Read16(state, SIO_BL_STATUS__A, +- &blStatus, 0)); +- } while ((blStatus == 0x1) && +- ((time_is_after_jiffies(end)))); +- if (blStatus == 0x1) { +- printk("SIO not ready\n"); +- mutex_unlock(&state->mutex); +- return -1; +- } +- } while(0); +- mutex_unlock(&state->mutex); +- return status; +-} +- +- +-static int DownloadMicrocode(struct drxk_state *state, +- const u8 pMCImage[], +- u32 Length) +-{ +- const u8 *pSrc = pMCImage; +- u16 Flags; +- u16 Drain; +- u32 Address; +- u16 nBlocks; +- u16 BlockSize; +- u16 BlockCRC; +- u32 offset = 0; +- u32 i; +- int status; +- +- /* down the drain (we don care about MAGIC_WORD) */ +- Drain = (pSrc[0] << 8) | pSrc[1]; +- pSrc += sizeof(u16); offset += sizeof(u16); +- nBlocks = (pSrc[0] << 8) | pSrc[1]; +- pSrc += sizeof(u16); offset += sizeof(u16); +- +- for (i = 0; i < nBlocks; i += 1) { +- Address = (pSrc[0] << 24) | (pSrc[1] << 16) | +- (pSrc[2] << 8) | pSrc[3]; +- pSrc += sizeof(u32); offset += sizeof(u32); +- +- BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); +- pSrc += sizeof(u16); offset += sizeof(u16); +- +- Flags = (pSrc[0] << 8) | pSrc[1]; +- pSrc += sizeof(u16); offset += sizeof(u16); +- +- BlockCRC = (pSrc[0] << 8) | pSrc[1]; +- pSrc += sizeof(u16); offset += sizeof(u16); +- status = WriteBlock(state, Address, BlockSize, pSrc, 0); +- if (status<0) +- break; +- pSrc += BlockSize; +- offset += BlockSize; +- } +- return status; +-} +- +-static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) +-{ +- int status; +- u16 data = 0; +- u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; +- u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; +- unsigned long end; +- +- if (enable == false) { +- desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; +- desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; +- } +- +- status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); +- +- if (data == desiredStatus) { +- /* tokenring already has correct status */ +- return status; +- } +- /* Disable/enable dvbt tokenring bridge */ +- status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); +- +- end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); +- do +- CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); +- while ((data != desiredStatus) && +- ((time_is_after_jiffies(end)))); +- if (data != desiredStatus) { +- printk("SIO not ready\n"); +- return -1; +- } +- return status; +-} +- +-static int MPEGTSStop(struct drxk_state *state) +-{ +- int status = 0; +- u16 fecOcSncMode = 0; +- u16 fecOcIprMode = 0; +- +- do { +- /* Gracefull shutdown (byte boundaries) */ +- CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); +- fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; +- CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); +- +- /* Suppress MCLK during absence of data */ +- CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); +- fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; +- CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode)); +- } while (0); +- return status; +-} +- +-static int scu_command(struct drxk_state *state, +- u16 cmd, u8 parameterLen, +- u16 * parameter, u8 resultLen, u16 * result) +-{ +-#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 +-#error DRXK register mapping no longer compatible with this routine! +-#endif +- u16 curCmd = 0; +- int status; +- unsigned long end; +- +- if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || +- ((resultLen > 0) && (result == NULL))) +- return -1; +- +- mutex_lock(&state->mutex); +- do { +- /* assume that the command register is ready +- since it is checked afterwards */ +- u8 buffer[34]; +- int cnt = 0, ii; +- +- for (ii=parameterLen-1; ii >= 0; ii -= 1) { +- buffer[cnt++] = (parameter[ii] & 0xFF); +- buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); +- } +- buffer[cnt++] = (cmd & 0xFF); +- buffer[cnt++] = ((cmd >> 8) & 0xFF); +- +- WriteBlock(state, SCU_RAM_PARAM_0__A - +- (parameterLen-1), cnt, buffer, 0x00); +- /* Wait until SCU has processed command */ +- end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME); +- do { +- msleep(1); +- CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd)); +- } while (! (curCmd == DRX_SCU_READY) && +- (time_is_after_jiffies(end))); +- if (curCmd != DRX_SCU_READY) { +- printk("SCU not ready\n"); +- mutex_unlock(&state->mutex); +- return -1; +- } +- /* read results */ +- if ((resultLen > 0) && (result != NULL)) { +- s16 err; +- int ii; +- +- for(ii=resultLen-1; ii >= 0; ii -= 1) { +- CHK_ERROR(Read16_0(state, +- SCU_RAM_PARAM_0__A - ii, +- &result[ii])); +- } +- +- /* Check if an error was reported by SCU */ +- err = (s16)result[0]; +- +- /* check a few fixed error codes */ +- if (err == SCU_RESULT_UNKSTD) { +- printk("SCU_RESULT_UNKSTD\n"); +- mutex_unlock(&state->mutex); +- return -1; +- } else if (err == SCU_RESULT_UNKCMD) { +- printk("SCU_RESULT_UNKCMD\n"); +- mutex_unlock(&state->mutex); +- return -1; +- } +- /* here it is assumed that negative means error, +- and positive no error */ +- else if (err < 0) { +- printk("%s ERROR\n", __FUNCTION__); +- mutex_unlock(&state->mutex); +- return -1; +- } +- } +- } while(0); +- mutex_unlock(&state->mutex); +- if (status<0) +- { +- printk("%s: status = %d\n", __FUNCTION__, status); +- } +- +- return status; +-} +- +-static int SetIqmAf(struct drxk_state *state, bool active) +-{ +- u16 data = 0; +- int status; +- +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active)); +- //printk("%s\n", __FUNCTION__); +- +- do +- { +- /* Configure IQM */ +- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));; +- if (!active) { +- data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY +- | IQM_AF_STDBY_STDBY_AMP_STANDBY +- | IQM_AF_STDBY_STDBY_PD_STANDBY +- | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY +- | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY +- ); +- // break; +- //default: +- // break; +- //} +- } else /* active */ { +- data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) +- & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) +- & (~IQM_AF_STDBY_STDBY_PD_STANDBY) +- & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) +- & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) +- ); +- // break; +- //default: +- // break; +- //} +- } +- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); +- }while(0); +- return status; +-} +- +-static int CtrlPowerMode(struct drxk_state *state, +- pDRXPowerMode_t mode) +-{ +- int status = 0; +- u16 sioCcPwdMode = 0; +- +- //printk("%s\n", __FUNCTION__); +- /* Check arguments */ +- if (mode == NULL) +- return -1; +- +- switch (*mode) { +- case DRX_POWER_UP: +- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; +- break; +- case DRXK_POWER_DOWN_OFDM: +- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; +- break; +- case DRXK_POWER_DOWN_CORE: +- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; +- break; +- case DRXK_POWER_DOWN_PLL: +- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; +- break; +- case DRX_POWER_DOWN: +- sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; +- break; +- default: +- /* Unknow sleep mode */ +- return -1; +- break; +- } +- +- /* If already in requested power mode, do nothing */ +- if (state->m_currentPowerMode == *mode) +- return 0; +- +- /* For next steps make sure to start from DRX_POWER_UP mode */ +- if (state->m_currentPowerMode != DRX_POWER_UP) +- { +- do { +- CHK_ERROR(PowerUpDevice(state)); +- CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); +- } while(0); +- } +- +- if (*mode == DRX_POWER_UP) { +- /* Restore analog & pin configuartion */ +- } else { +- /* Power down to requested mode */ +- /* Backup some register settings */ +- /* Set pins with possible pull-ups connected +- to them in input mode */ +- /* Analog power down */ +- /* ADC power down */ +- /* Power down device */ +- /* stop all comm_exec */ +- /* Stop and power down previous standard */ +- do { +- switch (state->m_OperationMode) { +- case OM_DVBT: +- CHK_ERROR(MPEGTSStop(state)); +- CHK_ERROR(PowerDownDVBT(state, false)); +- break; +- case OM_QAM_ITU_A: +- case OM_QAM_ITU_C: +- CHK_ERROR(MPEGTSStop(state)); +- CHK_ERROR(PowerDownQAM(state)); +- break; +- default: +- break; +- } +- CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); +- CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, +- sioCcPwdMode)); +- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, +- SIO_CC_UPDATE_KEY)); +- +- if (*mode != DRXK_POWER_DOWN_OFDM) { +- state->m_HICfgCtrl |= +- SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; +- CHK_ERROR(HI_CfgCommand(state)); +- } +- } while(0); +- } +- state->m_currentPowerMode = *mode; +- return (status); +-} +- +-static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) +-{ +- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; +- u16 cmdResult = 0; +- u16 data = 0; +- int status; +- +- do { +- CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); +- if (data == SCU_COMM_EXEC_ACTIVE) { +- /* Send OFDM stop command */ +- CHK_ERROR(scu_command(state, +- SCU_RAM_COMMAND_STANDARD_OFDM | +- SCU_RAM_COMMAND_CMD_DEMOD_STOP, +- 0, NULL, 1, &cmdResult)); +- /* Send OFDM reset command */ +- CHK_ERROR(scu_command(state, +- SCU_RAM_COMMAND_STANDARD_OFDM | +- SCU_RAM_COMMAND_CMD_DEMOD_RESET, +- 0, NULL, 1, &cmdResult)); +- } +- +- /* Reset datapath for OFDM, processors first */ +- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, +- OFDM_SC_COMM_EXEC_STOP)); +- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, +- OFDM_LC_COMM_EXEC_STOP)); +- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, +- IQM_COMM_EXEC_B_STOP)); +- +- /* powerdown AFE */ +- CHK_ERROR(SetIqmAf(state,false)); +- +- /* powerdown to OFDM mode */ +- if (setPowerMode) { +- CHK_ERROR(CtrlPowerMode(state,&powerMode)); +- } +- } while(0); +- return status; +-} +- +-static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode) +-{ +- int status = 0; +- +- /* +- Stop and power down previous standard +- TODO investigate total power down instead of partial +- power down depending on "previous" standard. +- */ +- do { +- /* disable HW lock indicator */ +- CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A, +- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); +- +- if (state->m_OperationMode != oMode) { +- switch (state->m_OperationMode) { +- // OM_NONE was added for start up +- case OM_NONE: +- break; +- case OM_DVBT: +- CHK_ERROR(MPEGTSStop(state)); +- CHK_ERROR(PowerDownDVBT(state,true)); +- state->m_OperationMode = OM_NONE; +- break; +- case OM_QAM_ITU_B: +- status = -1; +- break; +- case OM_QAM_ITU_A: /* fallthrough */ +- case OM_QAM_ITU_C: +- CHK_ERROR(MPEGTSStop(state)); +- CHK_ERROR(PowerDownQAM(state)); +- state->m_OperationMode = OM_NONE; +- break; +- default: +- status = -1; +- } +- CHK_ERROR(status); +- +- /* +- Power up new standard +- */ +- switch (oMode) +- { +- case OM_DVBT: +- state->m_OperationMode = oMode; +- CHK_ERROR(SetDVBTStandard(state, oMode)); +- break; +- case OM_QAM_ITU_B: +- status = -1; +- break; +- case OM_QAM_ITU_A: /* fallthrough */ +- case OM_QAM_ITU_C: +- state->m_OperationMode = oMode; +- CHK_ERROR(SetQAMStandard(state,oMode)); +- break; +- default: +- status = -1; +- } +- } +- CHK_ERROR(status); +- } while(0); +- return 0; +-} +- +-static int Start(struct drxk_state *state, s32 offsetFreq, +- s32 IntermediateFrequency) +-{ +- int status; +- +- do { +- u16 IFreqkHz; +- s32 OffsetkHz = offsetFreq / 1000; +- +- if (state->m_DrxkState != DRXK_STOPPED && +- state->m_DrxkState != DRXK_DTV_STARTED) { +- status = -1; +- break; +- } +- state->m_bMirrorFreqSpect = +-#ifndef USE_API3 +- (state->props.inversion == INVERSION_ON); +-#else +- (state->param.inversion == INVERSION_ON); +-#endif +- if (IntermediateFrequency < 0) { +- state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; +- IntermediateFrequency = -IntermediateFrequency; +- } +- +- switch(state->m_OperationMode) { +- case OM_QAM_ITU_A: +- case OM_QAM_ITU_C: +- IFreqkHz = (IntermediateFrequency / 1000); +- CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz)); +- state->m_DrxkState = DRXK_DTV_STARTED; +- break; +- case OM_DVBT: +- IFreqkHz = (IntermediateFrequency / 1000); +- CHK_ERROR(MPEGTSStop(state)); +- CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz)); +- CHK_ERROR(DVBTStart(state)); +- state->m_DrxkState = DRXK_DTV_STARTED; +- break; +- default: +- break; +- } +- } while(0); +- return status; +-} +- +-static int ShutDown(struct drxk_state *state) +-{ +- MPEGTSStop(state); +- return 0; +-} +- +-static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time) +-{ +- int status; +- +- if (pLockStatus == NULL) +- return -1; +- +- *pLockStatus = NOT_LOCKED; +- +- /* define the SCU command code */ +- switch (state->m_OperationMode) { +- case OM_QAM_ITU_A: +- case OM_QAM_ITU_B: +- case OM_QAM_ITU_C: +- status = GetQAMLockStatus(state, pLockStatus); +- break; +- case OM_DVBT: +- status = GetDVBTLockStatus(state, pLockStatus); +- break; +- default: +- break; +- } +- return status; +-} +- +-static int MPEGTSStart(struct drxk_state *state) +-{ +- int status = 0; +- +- u16 fecOcSncMode = 0; +- +- do { +- /* Allow OC to sync again */ +- CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); +- fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; +- CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); +- CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); +- } while (0); +- return status; +-} +- +-static int MPEGTSDtoInit(struct drxk_state *state) +-{ +- int status = -1; +- +- do { +- /* Rate integration settings */ +- CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); +- CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); +- CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); +- CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); +- CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); +- CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); +- CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); +- CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); +- +- /* Additional configuration */ +- CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); +- CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); +- CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); +- } while (0); +- return status; +-} +- +-static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode) +-{ +- int status = -1; +- +- u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ +- u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ +- u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ +- u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ +- u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ +- u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ +- u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ +- u16 fecOcTmdMode = 0; +- u16 fecOcTmdIntUpdRate = 0; +- u32 maxBitRate = 0; +- bool staticCLK = false; +- +- do { +- /* Check insertion of the Reed-Solomon parity bytes */ +- CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); +- CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, +- &fecOcRegIprMode)); +- fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); +- fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); +- if (state->m_insertRSByte == true) { +- /* enable parity symbol forward */ +- fecOcRegMode |= FEC_OC_MODE_PARITY__M; +- /* MVAL disable during parity bytes */ +- fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; +- /* TS burst length to 204 */ +- fecOcDtoBurstLen = 204 ; +- } +- +- /* Check serial or parrallel output */ +- fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); +- if (state->m_enableParallel == false) { +- /* MPEG data output is serial -> set ipr_mode[0] */ +- fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; +- } +- +- switch (oMode) { +- case OM_DVBT: +- maxBitRate = state->m_DVBTBitrate; +- fecOcTmdMode = 3; +- fecOcRcnCtlRate = 0xC00000; +- staticCLK = state->m_DVBTStaticCLK; +- break; +- case OM_QAM_ITU_A: /* fallthrough */ +- case OM_QAM_ITU_C: +- fecOcTmdMode = 0x0004; +- fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ +- maxBitRate = state->m_DVBCBitrate; +- staticCLK = state->m_DVBCStaticCLK; +- break; +- default: +- status = -1; +- } /* switch (standard) */ +- CHK_ERROR(status); +- +- /* Configure DTO's */ +- if (staticCLK ) { +- u32 bitRate = 0; +- +- /* Rational DTO for MCLK source (static MCLK rate), +- Dynamic DTO for optimal grouping +- (avoid intra-packet gaps), +- DTO offset enable to sync TS burst with MSTRT */ +- fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | +- FEC_OC_DTO_MODE_OFFSET_ENABLE__M); +- fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | +- FEC_OC_FCT_MODE_VIRT_ENA__M); +- +- /* Check user defined bitrate */ +- bitRate = maxBitRate; +- if (bitRate > 75900000UL) +- { /* max is 75.9 Mb/s */ +- bitRate = 75900000UL; +- } +- /* Rational DTO period: +- dto_period = (Fsys / bitrate) - 2 +- +- Result should be floored, +- to make sure >= requested bitrate +- */ +- fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) +- * 1000) / bitRate); +- if (fecOcDtoPeriod <= 2) +- fecOcDtoPeriod = 0; +- else +- fecOcDtoPeriod -= 2; +- fecOcTmdIntUpdRate = 8; +- } else { +- /* (commonAttr->staticCLK == false) => dynamic mode */ +- fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; +- fecOcFctMode = FEC_OC_FCT_MODE__PRE; +- fecOcTmdIntUpdRate = 5; +- } +- +- /* Write appropriate registers with requested configuration */ +- CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, +- fecOcDtoBurstLen)); +- CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, +- fecOcDtoPeriod)); +- CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, +- fecOcDtoMode)); +- CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, +- fecOcFctMode)); +- CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, +- fecOcRegMode)); +- CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, +- fecOcRegIprMode)); +- +- /* Rate integration settings */ +- CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, +- fecOcRcnCtlRate ,0)); +- CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, +- fecOcTmdIntUpdRate)); +- CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, +- fecOcTmdMode)); +- } while (0); +- return status; +-} +- +-static int MPEGTSConfigurePolarity(struct drxk_state *state) +-{ +- int status; +- u16 fecOcRegIprInvert = 0; +- +- /* Data mask for the output data byte */ +- u16 InvertDataMask = +- FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | +- FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | +- FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | +- FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; +- +- /* Control selective inversion of output bits */ +- fecOcRegIprInvert &= (~(InvertDataMask)); +- if (state->m_invertDATA == true) +- fecOcRegIprInvert |= InvertDataMask; +- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); +- if (state->m_invertERR == true) +- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; +- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); +- if (state->m_invertSTR == true) +- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; +- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); +- if (state->m_invertVAL == true) +- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; +- fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); +- if (state->m_invertCLK == true) +- fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; +- status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); +- return status; +-} +- +-#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 +- +-static int SetAgcRf(struct drxk_state *state, +- struct SCfgAgc *pAgcCfg, bool isDTV) +-{ +- int status = 0; +- struct SCfgAgc *pIfAgcSettings; +- +- if (pAgcCfg == NULL) +- return -1; +- +- do { +- u16 data = 0; +- +- switch (pAgcCfg->ctrlMode) { +- case DRXK_AGC_CTRL_AUTO: +- +- /* Enable RF AGC DAC */ +- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); +- data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; +- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); +- +- CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, +- &data, 0)); +- +- /* Enable SCU RF AGC loop */ +- data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; +- +- /* Polarity */ +- if (state->m_RfAgcPol) +- data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; +- else +- data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_CONFIG__A, data)); +- +- /* Set speed (using complementary reduction value) */ +- CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, +- &data, 0)); +- +- data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; +- data |= (~(pAgcCfg->speed << +- SCU_RAM_AGC_KI_RED_RAGC_RED__B) +- & SCU_RAM_AGC_KI_RED_RAGC_RED__M); +- +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_KI_RED__A, data)); +- +- if (IsDVBT(state)) +- pIfAgcSettings = &state->m_dvbtIfAgcCfg; +- else if (IsQAM(state)) +- pIfAgcSettings = &state->m_qamIfAgcCfg; +- else +- pIfAgcSettings = &state->m_atvIfAgcCfg; +- if (pIfAgcSettings == NULL) +- return -1; +- +- /* Set TOP, only if IF-AGC is in AUTO mode */ +- if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, +- pAgcCfg->top)); +- +- /* Cut-Off current */ +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_RF_IACCU_HI_CO__A, +- pAgcCfg->cutOffCurrent)); +- +- /* Max. output level */ +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, +- pAgcCfg->maxOutputLevel)); +- +- break; +- +- case DRXK_AGC_CTRL_USER: +- /* Enable RF AGC DAC */ +- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); +- data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; +- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); +- +- /* Disable SCU RF AGC loop */ +- CHK_ERROR(Read16_0(state, +- SCU_RAM_AGC_CONFIG__A, &data)); +- data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; +- if (state->m_RfAgcPol) +- data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; +- else +- data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, +- data)); +- +- /* SCU c.o.c. to 0, enabling full control range */ +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, +- 0)); +- +- /* Write value to output pin */ +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, +- pAgcCfg->outputLevel)); +- break; +- +- case DRXK_AGC_CTRL_OFF: +- /* Disable RF AGC DAC */ +- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); +- data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; +- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); +- +- /* Disable SCU RF AGC loop */ +- CHK_ERROR(Read16_0(state, +- SCU_RAM_AGC_CONFIG__A, &data)); +- data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_CONFIG__A, data)); +- break; +- +- default: +- return -1; +- +- } /* switch (agcsettings->ctrlMode) */ +- } while(0); +- return status; +-} +- +-#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 +- +-static int SetAgcIf (struct drxk_state *state, +- struct SCfgAgc *pAgcCfg, bool isDTV) +-{ +- u16 data = 0; +- int status = 0; +- struct SCfgAgc *pRfAgcSettings; +- +- do { +- switch (pAgcCfg->ctrlMode) { +- case DRXK_AGC_CTRL_AUTO: +- +- /* Enable IF AGC DAC */ +- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); +- data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; +- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); +- +- CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, +- &data)); +- +- /* Enable SCU IF AGC loop */ +- data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; +- +- /* Polarity */ +- if (state->m_IfAgcPol) +- data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; +- else +- data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_CONFIG__A, data)); +- +- /* Set speed (using complementary reduction value) */ +- CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, +- &data)); +- data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; +- data |= (~(pAgcCfg->speed << +- SCU_RAM_AGC_KI_RED_IAGC_RED__B) +- & SCU_RAM_AGC_KI_RED_IAGC_RED__M); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A , +- data)); +- +- if (IsQAM(state)) +- pRfAgcSettings = &state->m_qamRfAgcCfg; +- else +- pRfAgcSettings = &state->m_atvRfAgcCfg; +- if (pRfAgcSettings == NULL) +- return -1; +- /* Restore TOP */ +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, +- pRfAgcSettings->top)); +- break; +- +- case DRXK_AGC_CTRL_USER: +- +- /* Enable IF AGC DAC */ +- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); +- data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; +- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); +- +- CHK_ERROR(Read16_0(state, +- SCU_RAM_AGC_CONFIG__A, &data)); +- +- /* Disable SCU IF AGC loop */ +- data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; +- +- /* Polarity */ +- if (state->m_IfAgcPol) +- data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; +- else +- data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_CONFIG__A, data)); +- +- /* Write value to output pin */ +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, +- pAgcCfg->outputLevel)); +- break; +- +- case DRXK_AGC_CTRL_OFF: +- +- /* Disable If AGC DAC */ +- CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); +- data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; +- CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); +- +- /* Disable SCU IF AGC loop */ +- CHK_ERROR(Read16_0(state, +- SCU_RAM_AGC_CONFIG__A, &data)); +- data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; +- CHK_ERROR(Write16_0(state, +- SCU_RAM_AGC_CONFIG__A, data)); +- break; +- } /* switch (agcSettingsIf->ctrlMode) */ +- +- /* always set the top to support +- configurations without if-loop */ +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, +- pAgcCfg->top)); +- +- +- } while(0); +- return status; +-} +- +-static int ReadIFAgc(struct drxk_state *state, u32 *pValue) +-{ +- u16 agcDacLvl; +- int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); +- +- *pValue = 0; +- +- if (status==0) { +- u16 Level = 0; +- if (agcDacLvl > DRXK_AGC_DAC_OFFSET) +- Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; +- if (Level < 14000) +- *pValue = (14000 - Level) / 4 ; +- else +- *pValue = 0; +- } +- return status; +-} +- +-static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +-{ +- int status = 0; +- +- do { +- /* MER calculation */ +- u16 qamSlErrPower = 0; /* accum. error between +- raw and sliced symbols */ +- u32 qamSlSigPower = 0; /* used for MER, depends of +- QAM constellation */ +- u32 qamSlMer = 0; /* QAM MER */ +- +- /* get the register value needed for MER */ +- CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower)); +- +-#ifndef USE_API3 +- switch(state->props.modulation) { +-#else +- switch(state->param.u.qam.modulation) { +-#endif +- case QAM_16: +- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; +- break; +- case QAM_32: +- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; +- break; +- case QAM_64: +- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; +- break; +- case QAM_128: +- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; +- break; +- default: +- case QAM_256: +- qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; +- break; +- } +- +- if (qamSlErrPower > 0) { +- qamSlMer = Log10Times100(qamSlSigPower) - +- Log10Times100((u32) qamSlErrPower); +- } +- *pSignalToNoise = qamSlMer; +- } while(0); +- return status; +-} +- +-static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +-{ +- int status = 0; +- +- u16 regData = 0; +- u32 EqRegTdSqrErrI = 0; +- u32 EqRegTdSqrErrQ = 0; +- u16 EqRegTdSqrErrExp = 0; +- u16 EqRegTdTpsPwrOfs = 0; +- u16 EqRegTdReqSmbCnt = 0; +- u32 tpsCnt = 0; +- u32 SqrErrIQ = 0; +- u32 a = 0; +- u32 b = 0; +- u32 c = 0; +- u32 iMER = 0; +- u16 transmissionParams = 0; +- +- do { +- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, +- &EqRegTdTpsPwrOfs)); +- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, +- &EqRegTdReqSmbCnt)); +- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, +- &EqRegTdSqrErrExp)); +- CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, +- ®Data)); +- /* Extend SQR_ERR_I operational range */ +- EqRegTdSqrErrI = (u32) regData; +- if ((EqRegTdSqrErrExp > 11) && +- (EqRegTdSqrErrI < 0x00000FFFUL)) { +- EqRegTdSqrErrI += 0x00010000UL; +- } +- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A, +- ®Data)); +- /* Extend SQR_ERR_Q operational range */ +- EqRegTdSqrErrQ = (u32)regData; +- if ((EqRegTdSqrErrExp > 11) && +- (EqRegTdSqrErrQ < 0x00000FFFUL)) +- EqRegTdSqrErrQ += 0x00010000UL; +- +- CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A, +- &transmissionParams)); +- +- /* Check input data for MER */ +- +- /* MER calculation (in 0.1 dB) without math.h */ +- if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) +- iMER = 0; +- else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { +- /* No error at all, this must be the HW reset value +- * Apparently no first measurement yet +- * Set MER to 0.0 */ +- iMER = 0; +- } else { +- SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << +- EqRegTdSqrErrExp; +- if ((transmissionParams & +- OFDM_SC_RA_RAM_OP_PARAM_MODE__M) +- == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) +- tpsCnt = 17; +- else +- tpsCnt = 68; +- +- /* IMER = 100 * log10 (x) +- where x = (EqRegTdTpsPwrOfs^2 * +- EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ +- +- => IMER = a + b -c +- where a = 100 * log10 (EqRegTdTpsPwrOfs^2) +- b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) +- c = 100 * log10 (SqrErrIQ) +- */ +- +- /* log(x) x = 9bits * 9bits->18 bits */ +- a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs); +- /* log(x) x = 16bits * 7bits->23 bits */ +- b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt); +- /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ +- c = Log10Times100(SqrErrIQ); +- +- iMER = a + b; +- /* No negative MER, clip to zero */ +- if (iMER > c) +- iMER -= c; +- else +- iMER = 0; +- } +- *pSignalToNoise = iMER; +- } while(0); +- +- return status; +-} +- +-static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +-{ +- *pSignalToNoise = 0; +- switch(state->m_OperationMode) { +- case OM_DVBT: +- return GetDVBTSignalToNoise(state, pSignalToNoise); +- case OM_QAM_ITU_A: +- case OM_QAM_ITU_C: +- return GetQAMSignalToNoise(state, pSignalToNoise); +- default: +- break; +- } +- return 0; +-} +- +-#if 0 +-static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) +-{ +- /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ +- int status = 0; +- +- static s32 QE_SN[] = +- { +- 51, // QPSK 1/2 +- 69, // QPSK 2/3 +- 79, // QPSK 3/4 +- 89, // QPSK 5/6 +- 97, // QPSK 7/8 +- 108, // 16-QAM 1/2 +- 131, // 16-QAM 2/3 +- 146, // 16-QAM 3/4 +- 156, // 16-QAM 5/6 +- 160, // 16-QAM 7/8 +- 165, // 64-QAM 1/2 +- 187, // 64-QAM 2/3 +- 202, // 64-QAM 3/4 +- 216, // 64-QAM 5/6 +- 225, // 64-QAM 7/8 +- }; +- +- *pQuality = 0; +- +- do { +- s32 SignalToNoise = 0; +- u16 Constellation = 0; +- u16 CodeRate = 0; +- u32 SignalToNoiseRel; +- u32 BERQuality; +- +- CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise)); +- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A, +- &Constellation)); +- Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; +- +- CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A, +- &CodeRate)); +- CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; +- +- if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || +- CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) +- break; +- SignalToNoiseRel = SignalToNoise - +- QE_SN[Constellation * 5 + CodeRate]; +- BERQuality = 100; +- +- if (SignalToNoiseRel < -70) *pQuality = 0; +- else if (SignalToNoiseRel < 30) +- *pQuality = ((SignalToNoiseRel + 70) * +- BERQuality) / 100; +- else +- *pQuality = BERQuality; +- } while(0); +- return 0; +-}; +- +-static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) +-{ +- int status = 0; +- *pQuality = 0; +- +- do { +- u32 SignalToNoise = 0; +- u32 BERQuality = 100; +- u32 SignalToNoiseRel = 0; +- +- CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); +- +-#ifndef USE_API3 +- switch(state->props.modulation) { +-#else +- switch(state->param.u.qam.modulation) { +-#endif +- case QAM_16: +- SignalToNoiseRel = SignalToNoise - 200; +- break; +- case QAM_32: +- SignalToNoiseRel = SignalToNoise - 230; +- break; /* Not in NorDig */ +- case QAM_64: +- SignalToNoiseRel = SignalToNoise - 260; +- break; +- case QAM_128: +- SignalToNoiseRel = SignalToNoise - 290; +- break; +- default: +- case QAM_256: +- SignalToNoiseRel = SignalToNoise - 320; +- break; +- } +- +- if (SignalToNoiseRel < -70) +- *pQuality = 0; +- else if (SignalToNoiseRel < 30) +- *pQuality = ((SignalToNoiseRel + 70) * +- BERQuality) / 100; +- else +- *pQuality = BERQuality; +- } while(0); +- +- return status; +-} +- +-static int GetQuality(struct drxk_state *state, s32 *pQuality) +-{ +- switch(state->m_OperationMode) { +- case OM_DVBT: +- return GetDVBTQuality(state, pQuality); +- case OM_QAM_ITU_A: +- return GetDVBCQuality(state, pQuality); +- default: +- break; +- } +- +- return 0; +-} +-#endif +- +-/* Free data ram in SIO HI */ +-#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +-#define SIO_HI_RA_RAM_USR_END__A 0x420060 +- +-#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +-#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +-#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +-#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE +- +-#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) +-#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) +-#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) +- +-static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) +-{ +- int status; +- +- if (state->m_DrxkState == DRXK_UNINITIALIZED) +- return -1; +- if (state->m_DrxkState == DRXK_POWERED_DOWN) +- return -1; +- +- do { +- CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, +- SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); +- if (bEnableBridge) { +- CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, +- SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); +- } else { +- CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, +- SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); +- } +- +- CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0)); +- } while(0); +- return status; +-} +- +-static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg) +-{ +- int status; +- +- if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M)) +- return -1; +- +- status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); +- return status; +-} +- +-static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, +- u16 romOffset, u16 nrOfElements, u32 timeOut) +-{ +- u16 blStatus = 0; +- u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF); +- u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF); +- int status ; +- unsigned long end; +- +- mutex_lock(&state->mutex); +- do { +- CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); +- CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); +- CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); +- CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); +- CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements)); +- CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); +- +- end=jiffies+msecs_to_jiffies(timeOut); +- do { +- CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus)); +- } while ((blStatus == 0x1) && +- time_is_after_jiffies(end)); +- if (blStatus == 0x1) { +- printk("SIO not ready\n"); +- mutex_unlock(&state->mutex); +- return -1; +- } +- } while(0); +- mutex_unlock(&state->mutex); +- return status; +- +-} +- +-static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) +-{ +- u16 data = 0; +- int status; +- +- do { +- /* Start measurement */ +- CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, +- IQM_AF_COMM_EXEC_ACTIVE)); +- CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1)); +- +- *count = 0; +- CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data)); +- if (data == 127) +- *count = *count+1; +- CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data)); +- if (data == 127) +- *count = *count+1; +- CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data)); +- if (data == 127) +- *count = *count+1; +- } while(0); +- return status; +-} +- +-static int ADCSynchronization(struct drxk_state *state) +-{ +- u16 count = 0; +- int status; +- +- do { +- CHK_ERROR(ADCSyncMeasurement(state, &count)); +- +- if (count==1) { +- /* Try sampling on a diffrent edge */ +- u16 clkNeg = 0; +- +- CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg)); +- if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == +- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { +- clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); +- clkNeg |= +- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; +- } else { +- clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); +- clkNeg |= +- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; +- } +- CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg)); +- CHK_ERROR(ADCSyncMeasurement(state, &count)); +- } +- +- if (count < 2) +- status = -1; +- } while (0); +- return status; +-} +- +-static int SetFrequencyShifter(struct drxk_state *state, +- u16 intermediateFreqkHz, +- s32 tunerFreqOffset, +- bool isDTV) +-{ +- bool selectPosImage = false; +- u32 rfFreqResidual = tunerFreqOffset; +- u32 fmFrequencyShift = 0; +- bool tunerMirror = !state->m_bMirrorFreqSpect; +- u32 adcFreq; +- bool adcFlip; +- int status; +- u32 ifFreqActual; +- u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3); +- u32 frequencyShift; +- bool imageToSelect; +- +- /* +- Program frequency shifter +- No need to account for mirroring on RF +- */ +- if (isDTV) { +- if ((state->m_OperationMode == OM_QAM_ITU_A) || +- (state->m_OperationMode == OM_QAM_ITU_C) || +- (state->m_OperationMode == OM_DVBT)) +- selectPosImage = true; +- else +- selectPosImage = false; +- } +- if (tunerMirror) +- /* tuner doesn't mirror */ +- ifFreqActual = intermediateFreqkHz + +- rfFreqResidual + fmFrequencyShift; +- else +- /* tuner mirrors */ +- ifFreqActual = intermediateFreqkHz - +- rfFreqResidual - fmFrequencyShift; +- if (ifFreqActual > samplingFrequency / 2) { +- /* adc mirrors */ +- adcFreq = samplingFrequency - ifFreqActual; +- adcFlip = true; +- } else { +- /* adc doesn't mirror */ +- adcFreq = ifFreqActual; +- adcFlip = false; +- } +- +- frequencyShift = adcFreq; +- imageToSelect = state->m_rfmirror ^ tunerMirror ^ +- adcFlip ^ selectPosImage; +- state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency); +- +- if (imageToSelect) +- state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; +- +- /* Program frequency shifter with tuner offset compensation */ +- /* frequencyShift += tunerFreqOffset; TODO */ +- status = Write32(state, IQM_FS_RATE_OFS_LO__A , +- state->m_IqmFsRateOfs, 0); +- return status; +-} +- +-static int InitAGC(struct drxk_state *state, bool isDTV) +-{ +- u16 ingainTgt = 0; +- u16 ingainTgtMin = 0; +- u16 ingainTgtMax = 0; +- u16 clpCyclen = 0; +- u16 clpSumMin = 0; +- u16 clpDirTo = 0; +- u16 snsSumMin = 0; +- u16 snsSumMax = 0; +- u16 clpSumMax = 0; +- u16 snsDirTo = 0; +- u16 kiInnergainMin = 0; +- u16 ifIaccuHiTgt = 0; +- u16 ifIaccuHiTgtMin = 0; +- u16 ifIaccuHiTgtMax = 0; +- u16 data = 0; +- u16 fastClpCtrlDelay = 0; +- u16 clpCtrlMode = 0; +- int status = 0; +- +- do { +- /* Common settings */ +- snsSumMax = 1023; +- ifIaccuHiTgtMin = 2047; +- clpCyclen = 500; +- clpSumMax = 1023; +- +- if (IsQAM(state)) { +- /* Standard specific settings */ +- clpSumMin = 8; +- clpDirTo = (u16) - 9; +- clpCtrlMode = 0; +- snsSumMin = 8; +- snsDirTo = (u16) - 9; +- kiInnergainMin = (u16) - 1030; +- } else +- status = -1; +- CHK_ERROR((status)); +- if (IsQAM(state)) { +- ifIaccuHiTgtMax = 0x2380; +- ifIaccuHiTgt = 0x2380; +- ingainTgtMin = 0x0511; +- ingainTgt = 0x0511; +- ingainTgtMax = 5119; +- fastClpCtrlDelay = +- state->m_qamIfAgcCfg.FastClipCtrlDelay; +- } else { +- ifIaccuHiTgtMax = 0x1200; +- ifIaccuHiTgt = 0x1200; +- ingainTgtMin = 13424; +- ingainTgt = 13424; +- ingainTgtMax = 30000; +- fastClpCtrlDelay = +- state->m_dvbtIfAgcCfg.FastClipCtrlDelay; +- } +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, +- fastClpCtrlDelay)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, +- clpCtrlMode)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, +- ingainTgt)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, +- ingainTgtMin)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, +- ingainTgtMax)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, +- ifIaccuHiTgtMin)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, +- ifIaccuHiTgtMax)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, +- clpSumMax)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, +- snsSumMax)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, +- kiInnergainMin)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, +- ifIaccuHiTgt)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, +- clpCyclen)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, +- 1023)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, +- (u16) -1023)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, +- 50)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, +- 20)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, +- clpSumMin)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, +- snsSumMin)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, +- clpDirTo)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, +- snsDirTo)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); +- +- /* Initialize inner-loop KI gain factors */ +- CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); +- if (IsQAM(state)) { +- data = 0x0657; +- data &= ~SCU_RAM_AGC_KI_RF__M; +- data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); +- data &= ~SCU_RAM_AGC_KI_IF__M; +- data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); +- } +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); +- } while(0); +- return status; +-} +- +-static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr) +-{ +- int status; +- +- do { +- if (packetErr == NULL) { +- CHK_ERROR(Write16_0(state, +- SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, +- 0)); +- } else { +- CHK_ERROR(Read16_0(state, +- SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, +- packetErr)); +- } +- } while (0); +- return status; +-} +- +-static int DVBTScCommand(struct drxk_state *state, +- u16 cmd, u16 subcmd, +- u16 param0, u16 param1, u16 param2, +- u16 param3, u16 param4) +-{ +- u16 curCmd = 0; +- u16 errCode = 0; +- u16 retryCnt = 0; +- u16 scExec = 0; +- int status; +- +- status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); +- if (scExec != 1) { +- /* SC is not running */ +- return -1; +- } +- +- /* Wait until sc is ready to receive command */ +- retryCnt =0; +- do { +- msleep(1); +- status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); +- retryCnt++; +- } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); +- if (retryCnt >= DRXK_MAX_RETRIES) +- return -1; +- /* Write sub-command */ +- switch (cmd) { +- /* All commands using sub-cmd */ +- case OFDM_SC_RA_RAM_CMD_PROC_START: +- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: +- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: +- status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); +- break; +- default: +- /* Do nothing */ +- break; +- } /* switch (cmd->cmd) */ +- +- /* Write needed parameters and the command */ +- switch (cmd) { +- /* All commands using 5 parameters */ +- /* All commands using 4 parameters */ +- /* All commands using 3 parameters */ +- /* All commands using 2 parameters */ +- case OFDM_SC_RA_RAM_CMD_PROC_START: +- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: +- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: +- status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); +- /* All commands using 1 parameters */ +- case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: +- case OFDM_SC_RA_RAM_CMD_USER_IO: +- status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); +- /* All commands using 0 parameters */ +- case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: +- case OFDM_SC_RA_RAM_CMD_NULL: +- /* Write command */ +- status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); +- break; +- default: +- /* Unknown command */ +- return -EINVAL; +- } /* switch (cmd->cmd) */ +- +- /* Wait until sc is ready processing command */ +- retryCnt = 0; +- do{ +- msleep(1); +- status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); +- retryCnt++; +- } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); +- if (retryCnt >= DRXK_MAX_RETRIES) +- return -1; +- +- /* Check for illegal cmd */ +- status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); +- if (errCode == 0xFFFF) +- { +- /* illegal command */ +- return -EINVAL; +- } +- +- /* Retreive results parameters from SC */ +- switch (cmd) { +- /* All commands yielding 5 results */ +- /* All commands yielding 4 results */ +- /* All commands yielding 3 results */ +- /* All commands yielding 2 results */ +- /* All commands yielding 1 result */ +- case OFDM_SC_RA_RAM_CMD_USER_IO: +- case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: +- status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); +- /* All commands yielding 0 results */ +- case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: +- case OFDM_SC_RA_RAM_CMD_SET_TIMER: +- case OFDM_SC_RA_RAM_CMD_PROC_START: +- case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: +- case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: +- case OFDM_SC_RA_RAM_CMD_NULL: +- break; +- default: +- /* Unknown command */ +- return -EINVAL; +- break; +- } /* switch (cmd->cmd) */ +- return status; +-} +- +-static int PowerUpDVBT (struct drxk_state *state) +-{ +- DRXPowerMode_t powerMode = DRX_POWER_UP; +- int status; +- +- do { +- CHK_ERROR(CtrlPowerMode(state, &powerMode)); +- } while (0); +- return status; +-} +- +-static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled) +-{ +- int status; +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- if (*enabled == true) +- { +- status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); +- } +- else +- { +- status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); +- } +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- +- return status; +-} +- #define DEFAULT_FR_THRES_8K 4000 +-static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled) +-{ +- +- int status; +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- +- if (*enabled == true) +- { +- /* write mask to 1 */ +- status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, +- DEFAULT_FR_THRES_8K); +- } +- else +- { +- /* write mask to 0 */ +- status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); +- } +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- +- return status; +-} +- +-static int DVBTCtrlSetEchoThreshold (struct drxk_state *state, +- struct DRXKCfgDvbtEchoThres_t* echoThres) +-{ +- u16 data = 0; +- int status; +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- +- do { +- CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); +- +- switch (echoThres->fftMode) +- { +- case DRX_FFTMODE_2K: +- data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M; +- data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) & +- (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); +- break; +- case DRX_FFTMODE_8K: +- data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M; +- data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & +- (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); +- break; +- default: +- return -1; +- break; +- } +- +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); +- } while (0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); +- } +- +- return status; +-} +- +-static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, +- enum DRXKCfgDvbtSqiSpeed* speed) +-{ +- int status; +- +- switch (*speed) { +- case DRXK_DVBT_SQI_SPEED_FAST: +- case DRXK_DVBT_SQI_SPEED_MEDIUM: +- case DRXK_DVBT_SQI_SPEED_SLOW: +- break; +- default: +- return -EINVAL; +- } +- status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, +- (u16) *speed); +- return status; +-} +- +-/*============================================================================*/ +- +-/** +-* \brief Activate DVBT specific presets +-* \param demod instance of demodulator. +-* \return DRXStatus_t. +-* +-* Called in DVBTSetStandard +-* +-*/ +-static int DVBTActivatePresets (struct drxk_state *state) +-{ +- int status; +- +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- +- struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K}; +- struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K}; +- +- do { +- bool setincenable = false; +- bool setfrenable = true; +- CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable)); +- CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable)); +- CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); +- CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, +- state->m_dvbtIfAgcCfg.IngainTgtMax)); +- } while (0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- +- return status; +-} +-/*============================================================================*/ +- +-/** +-* \brief Initialize channelswitch-independent settings for DVBT. +-* \param demod instance of demodulator. +-* \return DRXStatus_t. +-* +-* For ROM code channel filter taps are loaded from the bootloader. For microcode +-* the DVB-T taps from the drxk_filters.h are used. +-*/ +-static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode) +-{ +- u16 cmdResult = 0; +- u16 data = 0; +- int status; +- +- //printk("%s\n", __FUNCTION__); +- +- PowerUpDVBT(state); +- +- do { +- /* added antenna switch */ +- SwitchAntennaToDVBT(state); +- /* send OFDM reset command */ +- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); +- +- /* send OFDM setenv command */ +- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult)); +- +- /* reset datapath for OFDM, processors first */ +- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); +- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); +- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP )); +- +- /* IQM setup */ +- /* synchronize on ofdstate->m_festart */ +- CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); +- /* window size for clipping ADC detection */ +- CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); +- /* window size for for sense pre-SAW detection */ +- CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); +- /* sense threshold for sense pre-SAW detection */ +- CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); +- CHK_ERROR(SetIqmAf(state,true)); +- +- CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); +- +- /* Impulse noise cruncher setup */ +- CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ +- CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ +- CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ +- +- CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); +- CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ +- CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ +- CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); +- CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); +- +- /* virtual clipping threshold for clipping ADC detection */ +- CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); +- CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ +- +- CHK_ERROR(BLChainCmd(state, +- DRXK_BL_ROM_OFFSET_TAPS_DVBT, +- DRXK_BLCC_NR_ELEMENTS_TAPS, +- DRXK_BLC_TIMEOUT)); +- +- CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ +- CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); +- /* enable power measurement interrupt */ +- CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); +- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); +- +- /* IQM will not be reset from here, sync ADC and update/init AGC */ +- CHK_ERROR(ADCSynchronization(state)); +- CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); +- +- /* Halt SCU to enable safe non-atomic accesses */ +- CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); +- +- CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ; +- CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true)); +- +- /* Set Noise Estimation notch width and enable DC fix */ +- CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data)); +- data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data)); +- +- /* Activate SCU to enable SCU commands */ +- CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); +- +- if (!state->m_DRXK_A3_ROM_CODE) +- { +- /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ +- CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, +- state->m_dvbtIfAgcCfg.FastClipCtrlDelay)); +- } +- +- /* OFDM_SC setup */ +-#ifdef COMPILE_FOR_NONRT +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); +-#endif +- +- /* FEC setup */ +- CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ +- +- +-#ifdef COMPILE_FOR_NONRT +- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400)); +-#else +- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000)); +-#endif +- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001)); +- +- /* Setup MPEG bus */ +- CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT)); +- /* Set DVBT Presets */ +- CHK_ERROR (DVBTActivatePresets (state)); +- +- } while (0); +- +- if (status<0) +- { +- printk("%s status - %08x\n",__FUNCTION__,status); +- } +- +- return status; +-} +- +-/*============================================================================*/ +-/** +-* \brief Start dvbt demodulating for channel. +-* \param demod instance of demodulator. +-* \return DRXStatus_t. +-*/ +-static int DVBTStart(struct drxk_state *state) +-{ +- u16 param1; +- +- int status; +-// DRXKOfdmScCmd_t scCmd; +- +- //printk("%s\n",__FUNCTION__); +- /* Start correct processes to get in lock */ +- /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ +- do { +- param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; +- CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0)); +- /* Start FEC OC */ +- CHK_ERROR(MPEGTSStart(state)); +- CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); +- } while (0); +- return (status); +-} +- +- +-/*============================================================================*/ +- +-/** +-* \brief Set up dvbt demodulator for channel. +-* \param demod instance of demodulator. +-* \return DRXStatus_t. +-* // original DVBTSetChannel() +-*/ +-static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +-{ +- u16 cmdResult = 0; +- u16 transmissionParams = 0; +- u16 operationMode = 0; +- u32 iqmRcRateOfs = 0; +- u32 bandwidth = 0; +- u16 param1; +- int status; +- +- //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset); +- do { +- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | +- SCU_RAM_COMMAND_CMD_DEMOD_STOP, +- 0,NULL,1,&cmdResult)); +- +- /* Halt SCU to enable safe non-atomic accesses */ +- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); +- +- /* Stop processors */ +- CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); +- CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); +- +- /* Mandatory fix, always stop CP, required to set spl offset back to +- hardware default (is set to 0 by ucode during pilot detection */ +- CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP)); +- +- /*== Write channel settings to device =====================================*/ +- +- /* mode */ +-#ifndef USE_API3 +- switch(state->props.transmission_mode) { +-#else +- switch(state->param.u.ofdm.transmission_mode) { +-#endif +- case TRANSMISSION_MODE_AUTO: +- default: +- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; +- /* fall through , try first guess DRX_FFTMODE_8K */ +- case TRANSMISSION_MODE_8K: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; +- break; +- case TRANSMISSION_MODE_2K: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; +- break; +- } +- +- /* guard */ +-#ifndef USE_API3 +- switch(state->props.guard_interval) { +-#else +- switch(state->param.u.ofdm.guard_interval) { +-#endif +- default: +- case GUARD_INTERVAL_AUTO: +- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; +- /* fall through , try first guess DRX_GUARD_1DIV4 */ +- case GUARD_INTERVAL_1_4: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; +- break; +- case GUARD_INTERVAL_1_32: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; +- break; +- case GUARD_INTERVAL_1_16: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; +- break; +- case GUARD_INTERVAL_1_8: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; +- break; +- } +- +- /* hierarchy */ +-#ifndef USE_API3 +- switch(state->props.hierarchy) { +-#else +- switch(state->param.u.ofdm.hierarchy_information) { +-#endif +- case HIERARCHY_AUTO: +- case HIERARCHY_NONE: +- default: +- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; +- /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ +- // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; +- //break; +- case HIERARCHY_1: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; +- break; +- case HIERARCHY_2: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; +- break; +- case HIERARCHY_4: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; +- break; +- } +- +- +- /* constellation */ +-#ifndef USE_API3 +- switch(state->props.modulation) { +-#else +- switch(state->param.u.ofdm.constellation) { +-#endif +- case QAM_AUTO: +- default: +- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; +- /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ +- case QAM_64: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; +- break; +- case QPSK: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; +- break; +- case QAM_16: +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; +- break; +- } +-#if 0 +- // No hierachical channels support in BDA +- /* Priority (only for hierarchical channels) */ +- switch (channel->priority) { +- case DRX_PRIORITY_LOW : +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; +- WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO); +- break; +- case DRX_PRIORITY_HIGH : +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; +- WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); +- break; +- case DRX_PRIORITY_UNKNOWN : /* fall through */ +- default: +- return (DRX_STS_INVALID_ARG); +- break; +- } +-#else +- // Set Priorty high +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; +- CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); +-#endif +- +- /* coderate */ +-#ifndef USE_API3 +- switch(state->props.code_rate_HP) { +-#else +- switch(state->param.u.ofdm.code_rate_HP) { +-#endif +- case FEC_AUTO: +- default: +- operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; +- /* fall through , try first guess DRX_CODERATE_2DIV3 */ +- case FEC_2_3 : +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; +- break; +- case FEC_1_2 : +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; +- break; +- case FEC_3_4 : +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; +- break; +- case FEC_5_6 : +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; +- break; +- case FEC_7_8 : +- transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; +- break; +- } +- +- /* SAW filter selection: normaly not necesarry, but if wanted +- the application can select a SAW filter via the driver by using UIOs */ +- /* First determine real bandwidth (Hz) */ +- /* Also set delay for impulse noise cruncher */ +- /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed +- by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC +- functions */ +-#ifndef USE_API3 +- switch(state->props.bandwidth_hz) { +-#else +- switch(state->param.u.ofdm.bandwidth) { +-#endif +-#ifndef USE_API3 +- case 0: +- case 8000000: +-#else +- case BANDWIDTH_AUTO: +- case BANDWIDTH_8_MHZ: +-#endif +- bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052)); +- /* cochannel protection for PAL 8 MHz */ +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); +- break; +-#ifndef USE_API3 +- case 7000000: +-#else +- case BANDWIDTH_7_MHZ: +-#endif +- bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491)); +- /* cochannel protection for PAL 7 MHz */ +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); +- break; +-#ifndef USE_API3 +- case 6000000: +-#else +- case BANDWIDTH_6_MHZ: +-#endif +- bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073)); +- /* cochannel protection for NTSC 6 MHz */ +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14)); +- CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); +- break; +- } +- +- if (iqmRcRateOfs == 0) +- { +- /* Now compute IQM_RC_RATE_OFS +- (((SysFreq/BandWidth)/2)/2) -1) * 2^23) +- => +- ((SysFreq / BandWidth) * (2^21)) - (2^23) +- */ +- /* (SysFreq / BandWidth) * (2^28) */ +- /* assert (MAX(sysClk)/MIN(bandwidth) < 16) +- => assert(MAX(sysClk) < 16*MIN(bandwidth)) +- => assert(109714272 > 48000000) = true so Frac 28 can be used */ +- iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth); +- /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ +- if ((iqmRcRateOfs & 0x7fL) >= 0x40) +- { +- iqmRcRateOfs += 0x80L; +- } +- iqmRcRateOfs = iqmRcRateOfs >> 7 ; +- /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ +- iqmRcRateOfs = iqmRcRateOfs - (1<<23); +- } +- +- iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<m_DRXK_A3_ROM_CODE) +- CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed)); +- +- } while(0); +- if (status<0) { +- //printk("%s status - %08x\n",__FUNCTION__,status); +- } +- +- return status; +-} +- +- +-/*============================================================================*/ +- +-/** +-* \brief Retreive lock status . +-* \param demod Pointer to demodulator instance. +-* \param lockStat Pointer to lock status structure. +-* \return DRXStatus_t. +-* +-*/ +-static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) +-{ +- int status; +- const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | +- OFDM_SC_RA_RAM_LOCK_FEC__M ); +- const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); +- const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ; +- +- u16 ScRaRamLock = 0; +- u16 ScCommExec = 0; +- +- /* driver 0.9.0 */ +- /* Check if SC is running */ +- status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); +- if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) +- { +- /* SC not active; return DRX_NOT_LOCKED */ +- *pLockStatus = NOT_LOCKED; +- return status; +- } +- +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- +- status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); +- +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock)); +- +- if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { +- *pLockStatus = MPEG_LOCK; +- } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) { +- *pLockStatus = FEC_LOCK; +- } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) { +- *pLockStatus = DEMOD_LOCK; +- } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) { +- *pLockStatus = NEVER_LOCK; +- } else { +- *pLockStatus = NOT_LOCKED; +- } +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- +- return status; +-} +- +-static int PowerUpQAM (struct drxk_state *state) +-{ +- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; +- +- +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- do +- { +- CHK_ERROR(CtrlPowerMode(state, &powerMode)); +- +- }while(0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); +- } +- return status; +-} +- +- +-/// Power Down QAM +-static int PowerDownQAM(struct drxk_state *state) +-{ +- u16 data = 0; +- u16 cmdResult; +- +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- do +- { +- CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); +- if (data == SCU_COMM_EXEC_ACTIVE) +- { +- /* +- STOP demodulator +- QAM and HW blocks +- */ +- /* stop all comstate->m_exec */ +- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); +- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult)); +- } +- /* powerdown AFE */ +- CHK_ERROR(SetIqmAf(state, false)); +- } +- while(0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- return status; +-} +-/*============================================================================*/ +- +-/** +-* \brief Setup of the QAM Measurement intervals for signal quality +-* \param demod instance of demod. +-* \param constellation current constellation. +-* \return DRXStatus_t. +-* +-* NOTE: +-* Take into account that for certain settings the errorcounters can overflow. +-* The implementation does not check this. +-* +-*/ +-static int SetQAMMeasurement(struct drxk_state *state, +- enum EDrxkConstellation constellation, +- u32 symbolRate) +-{ +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode)); +- +- u32 fecBitsDesired = 0; /* BER accounting period */ +- u32 fecRsPeriodTotal = 0; /* Total period */ +- u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ +- u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ +- int status = 0; +- +- fecRsPrescale = 1; +- +- do { +- +- /* fecBitsDesired = symbolRate [kHz] * +- FrameLenght [ms] * +- (constellation + 1) * +- SyncLoss (== 1) * +- ViterbiLoss (==1) +- */ +- switch (constellation) +- { +- case DRX_CONSTELLATION_QAM16: +- fecBitsDesired = 4 * symbolRate; +- break; +- case DRX_CONSTELLATION_QAM32: +- fecBitsDesired = 5 * symbolRate; +- break; +- case DRX_CONSTELLATION_QAM64: +- fecBitsDesired = 6 * symbolRate; +- break; +- case DRX_CONSTELLATION_QAM128: +- fecBitsDesired = 7 * symbolRate; +- break; +- case DRX_CONSTELLATION_QAM256: +- fecBitsDesired = 8 * symbolRate; +- break; +- default: +- status = -EINVAL; +- } +- CHK_ERROR(status); +- +- fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ +- fecBitsDesired *= 500; /* meas. period [ms] */ +- +- /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ +- /* fecRsPeriodTotal = fecBitsDesired / 1632 */ +- fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/ +- +- /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ +- fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); +- if (fecRsPrescale == 0) { +- /* Divide by zero (though impossible) */ +- status = -1; +- } +- CHK_ERROR(status); +- fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) / +- fecRsPrescale; +- +- /* write corresponding registers */ +- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod)); +- CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale)); +- CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); +- +- } while (0); +- +- if (status<0) { +- printk("%s: status - %08x\n",__FUNCTION__,status); +- } +- return status; +-} +- +-static int SetQAM16 (struct drxk_state *state) +-{ +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- do +- { +- /* QAM Equalizer Setup */ +- /* Equalizer */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); +- /* Decision Feedback Equalizer */ +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); +- +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); +- +- /* QAM Slicer Settings */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16)); +- +- /* QAM Loop Controller Coeficients */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); +- +- +- /* QAM State Machine (FSM) Thresholds */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); +- +- +- /* QAM FSM Tracking Parameters */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127)); +- }while(0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- return status; +-} +- +-/*============================================================================*/ +- +-/** +-* \brief QAM32 specific setup +-* \param demod instance of demod. +-* \return DRXStatus_t. +-*/ +-static int SetQAM32 (struct drxk_state *state) +-{ +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- do +- { +- /* QAM Equalizer Setup */ +- /* Equalizer */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); +- +- /* Decision Feedback Equalizer */ +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); +- +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); +- +- /* QAM Slicer Settings */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32)); +- +- +- /* QAM Loop Controller Coeficients */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); +- +- +- /* QAM State Machine (FSM) Thresholds */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); +- +- +- /* QAM FSM Tracking Parameters */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86)); +- }while(0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- return status; +-} +- +-/*============================================================================*/ +- +-/** +-* \brief QAM64 specific setup +-* \param demod instance of demod. +-* \return DRXStatus_t. +-*/ +-static int SetQAM64 (struct drxk_state *state) +-{ +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- do +- { +- /* QAM Equalizer Setup */ +- /* Equalizer */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); +- +- /* Decision Feedback Equalizer */ +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); +- +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); +- +- /* QAM Slicer Settings */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64)); +- +- +- /* QAM Loop Controller Coeficients */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); +- +- +- /* QAM State Machine (FSM) Thresholds */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); +- +- +- /* QAM FSM Tracking Parameters */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80)); +- }while(0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- return status; +-} +- +-/*============================================================================*/ +- +-/** +-* \brief QAM128 specific setup +-* \param demod: instance of demod. +-* \return DRXStatus_t. +-*/ +-static int SetQAM128(struct drxk_state *state) +-{ +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- do +- { +- /* QAM Equalizer Setup */ +- /* Equalizer */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); +- +- /* Decision Feedback Equalizer */ +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); +- +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); +- +- +- /* QAM Slicer Settings */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128)); +- +- +- /* QAM Loop Controller Coeficients */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); +- +- +- /* QAM State Machine (FSM) Thresholds */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); +- +- /* QAM FSM Tracking Parameters */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23)); +- }while(0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- return status; +-} +- +-/*============================================================================*/ +- +-/** +-* \brief QAM256 specific setup +-* \param demod: instance of demod. +-* \return DRXStatus_t. +-*/ +-static int SetQAM256(struct drxk_state *state) +-{ +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- do +- { +- /* QAM Equalizer Setup */ +- /* Equalizer */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); +- +- /* Decision Feedback Equalizer */ +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); +- CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); +- +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); +- +- /* QAM Slicer Settings */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256)); +- +- +- /* QAM Loop Controller Coeficients */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); +- +- +- /* QAM State Machine (FSM) Thresholds */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); +- +- +- /* QAM FSM Tracking Parameters */ +- +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0)); +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8)); +- }while(0); +- +- if (status<0) +- { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- } +- return status; +-} +- +- +-/*============================================================================*/ +-/** +-* \brief Reset QAM block. +-* \param demod: instance of demod. +-* \param channel: pointer to channel data. +-* \return DRXStatus_t. +-*/ +-static int QAMResetQAM(struct drxk_state *state) +-{ +- int status; +- u16 cmdResult; +- +- //printk("%s\n", __FUNCTION__); +- do +- { +- /* Stop QAM comstate->m_exec */ +- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); +- +- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); +- } while (0); +- +- /* All done, all OK */ +- return status; +-} +- +-/*============================================================================*/ +- +-/** +-* \brief Set QAM symbolrate. +-* \param demod: instance of demod. +-* \param channel: pointer to channel data. +-* \return DRXStatus_t. +-*/ +-static int QAMSetSymbolrate(struct drxk_state *state) +-{ +- u32 adcFrequency = 0; +- u32 symbFreq = 0; +- u32 iqmRcRate = 0; +- u16 ratesel = 0; +- u32 lcSymbRate = 0; +- int status; +- u32 srate = +-#ifndef USE_API3 +- state->props.symbol_rate; +-#else +- state->param.u.qam.symbol_rate; +-#endif +- +- do +- { +- /* Select & calculate correct IQM rate */ +- adcFrequency = (state->m_sysClockFreq * 1000) / 3; +- ratesel = 0; +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate)); +- //printk("SR %d\n", state->param.u.qam.symbol_rate); +- if (srate <= 1188750) +- { +- ratesel = 3; +- } +- else if (srate <= 2377500) +- { +- ratesel = 2; +- } +- else if (srate <= 4755000) +- { +- ratesel = 1; +- } +- CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel)); +- +- /* +- IqmRcRate = ((Fadc / (symbolrate * (4<> 7) - +- (1 << 23); +- CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0)); +- state->m_iqmRcRate = iqmRcRate; +- /* +- LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) +- */ +- symbFreq = srate; +- if (adcFrequency == 0) +- { +- /* Divide by zero */ +- return -1; +- } +- lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + +- (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16); +- if (lcSymbRate > 511) +- { +- lcSymbRate = 511; +- } +- CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate)); +- } while (0); +- +- return status; +-} +- +-/*============================================================================*/ +- +-/** +-* \brief Get QAM lock status. +-* \param demod: instance of demod. +-* \param channel: pointer to channel data. +-* \return DRXStatus_t. +-*/ +- +-static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) +-{ +- int status; +- u16 Result[2] = {0,0}; +- +- status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result); +- if (status<0) +- { +- printk("%s status = %08x\n",__FUNCTION__,status); +- } +- if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) +- { +- /* 0x0000 NOT LOCKED */ +- *pLockStatus = NOT_LOCKED; +- } +- else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) +- { +- /* 0x4000 DEMOD LOCKED */ +- *pLockStatus = DEMOD_LOCK; +- } +- else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) +- { +- /* 0x8000 DEMOD + FEC LOCKED (system lock) */ +- *pLockStatus = MPEG_LOCK; +- } +- else +- { +- /* 0xC000 NEVER LOCKED */ +- /* (system will never be able to lock to the signal) */ +- /* TODO: check this, intermediate & standard specific lock states are not +- taken into account here */ +- *pLockStatus = NEVER_LOCK; +- } +- return status; +-} +- +-#define QAM_MIRROR__M 0x03 +-#define QAM_MIRROR_NORMAL 0x00 +-#define QAM_MIRRORED 0x01 +-#define QAM_MIRROR_AUTO_ON 0x02 +-#define QAM_LOCKRANGE__M 0x10 +-#define QAM_LOCKRANGE_NORMAL 0x10 +- +-static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +-{ +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- int status = 0; +- u8 parameterLen; +- u16 setEnvParameters[5]; +- u16 setParamParameters[4]={0,0,0,0}; +- u16 cmdResult; +- +- //printk("%s\n", __FUNCTION__); +- +- do { +- /* +- STEP 1: reset demodulator +- resets FEC DI and FEC RS +- resets QAM block +- resets SCU variables +- */ +- CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP)); +- CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP)); +- CHK_ERROR(QAMResetQAM(state)); +- +- /* +- STEP 2: configure demodulator +- -set env +- -set params; resets IQM,QAM,FEC HW; initializes some SCU variables +- */ +- CHK_ERROR(QAMSetSymbolrate(state)); +- +- /* Env parameters */ +- setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ +- if (state->m_OperationMode == OM_QAM_ITU_C) +- { +- setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ +- } +- setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); +-// check for LOCKRANGE Extented +- // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; +- parameterLen = 4; +- +- /* Set params */ +-#ifndef USE_API3 +- switch(state->props.modulation) +-#else +- switch(state->param.u.qam.modulation) +-#endif +- { +- case QAM_256: +- state->m_Constellation = DRX_CONSTELLATION_QAM256; +- break; +- case QAM_AUTO: +- case QAM_64: +- state->m_Constellation = DRX_CONSTELLATION_QAM64; +- break; +- case QAM_16: +- state->m_Constellation = DRX_CONSTELLATION_QAM16; +- break; +- case QAM_32: +- state->m_Constellation = DRX_CONSTELLATION_QAM32; +- break; +- case QAM_128: +- state->m_Constellation = DRX_CONSTELLATION_QAM128; +- break; +- default: +- status = -EINVAL; +- break; +- } +- CHK_ERROR(status); +- setParamParameters[0] = state->m_Constellation; /* constellation */ +- setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ +- +- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult)); +- +- +- /* STEP 3: enable the system in a mode where the ADC provides valid signal +- setup constellation independent registers */ +-// CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); +- CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true)); +- +- /* Setup BER measurement */ +- CHK_ERROR(SetQAMMeasurement (state, +- state->m_Constellation, +-#ifndef USE_API3 +- state->props.symbol_rate)); +-#else +- state->param.u.qam.symbol_rate)); +-#endif +- +- /* Reset default values */ +- CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE)); +- CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); +- +- /* Reset default LC values */ +- CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); +- +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); +- CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); +- +- /* Mirroring, QAM-block starting point not inverted */ +- CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS)); +- +- /* Halt SCU to enable safe non-atomic accesses */ +- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); +- +- /* STEP 4: constellation specific setup */ +-#ifndef USE_API3 +- switch (state->props.modulation) +-#else +- switch (state->param.u.qam.modulation) +-#endif +- { +- case QAM_16: +- CHK_ERROR(SetQAM16(state)); +- break; +- case QAM_32: +- CHK_ERROR(SetQAM32(state)); +- break; +- case QAM_AUTO: +- case QAM_64: +- CHK_ERROR(SetQAM64(state)); +- break; +- case QAM_128: +- CHK_ERROR(SetQAM128(state)); +- break; +- case QAM_256: +- //printk("SETQAM256\n"); +- CHK_ERROR(SetQAM256(state)); +- break; +- default: +- return -1; +- break; +- } /* switch */ +- /* Activate SCU to enable SCU commands */ +- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); +- +- +- /* Re-configure MPEG output, requires knowledge of channel bitrate */ +-// extAttr->currentChannel.constellation = channel->constellation; +-// extAttr->currentChannel.symbolrate = channel->symbolrate; +- CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); +- +- /* Start processes */ +- CHK_ERROR(MPEGTSStart(state)); +- CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); +- CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); +- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); +- +- /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ +- CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | +- SCU_RAM_COMMAND_CMD_DEMOD_START,0, +- NULL,1,&cmdResult)); +- +- /* update global DRXK data container */ +-//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; +- +- /* All done, all OK */ +- } while(0); +- +- if (status<0) { +- printk("%s %d\n", __FUNCTION__, status); +- } +- return status; +-} +- +-static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode) +-{ +-#ifdef DRXK_QAM_TAPS +-#define DRXK_QAMA_TAPS_SELECT +-#include "drxk_filters.h" +-#undef DRXK_QAMA_TAPS_SELECT +-#else +- int status; +-#endif +- +- //printk("%s\n", __FUNCTION__); +- do +- { +- /* added antenna switch */ +- SwitchAntennaToQAM(state); +- +- /* Ensure correct power-up mode */ +- CHK_ERROR(PowerUpQAM(state)); +- /* Reset QAM block */ +- CHK_ERROR(QAMResetQAM(state)); +- +- /* Setup IQM */ +- +- CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); +- CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); +- +- /* Upload IQM Channel Filter settings by +- boot loader from ROM table */ +- switch (oMode) +- { +- case OM_QAM_ITU_A: +- CHK_ERROR(BLChainCmd(state, +- DRXK_BL_ROM_OFFSET_TAPS_ITU_A, +- DRXK_BLCC_NR_ELEMENTS_TAPS, +- DRXK_BLC_TIMEOUT)); +- break; +- case OM_QAM_ITU_C: +- CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, +- DRXK_BL_ROM_OFFSET_TAPS_ITU_C, +- DRXK_BLDC_NR_ELEMENTS_TAPS, +- DRXK_BLC_TIMEOUT)); +- CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, +- DRXK_BL_ROM_OFFSET_TAPS_ITU_C, +- DRXK_BLDC_NR_ELEMENTS_TAPS, +- DRXK_BLC_TIMEOUT)); +- break; +- default: +- status=-EINVAL; +- } +- CHK_ERROR (status); +- +- CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, +- (1 << IQM_CF_OUT_ENA_QAM__B))); +- CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); +- CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, +- ((1 << IQM_CF_MIDTAP_RE__B) | +- (1 << IQM_CF_MIDTAP_IM__B)))); +- +- CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); +- CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); +- CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); +- CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); +- CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); +- +- CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); +- CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); +- CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); +- CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); +- +- /* IQM Impulse Noise Processing Unit */ +- CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); +- CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); +- CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); +- CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); +- CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); +- CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); +- CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); +- +- /* turn on IQMAF. Must be done before setAgc**() */ +- CHK_ERROR(SetIqmAf(state, true)); +- CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); +- +- /* IQM will not be reset from here, sync ADC and update/init AGC */ +- CHK_ERROR(ADCSynchronization (state)); +- +- /* Set the FSM step period */ +- CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); +- +- /* Halt SCU to enable safe non-atomic accesses */ +- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); +- +- /* No more resets of the IQM, current standard correctly set => +- now AGCs can be configured. */ +- +- CHK_ERROR(InitAGC(state,true)); +- CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); +- +- /* Configure AGC's */ +- CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); +- CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true)); +- +- /* Activate SCU to enable SCU commands */ +- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); +- } while (0); +- return status; +-} +- +-static int WriteGPIO(struct drxk_state *state) +-{ +- int status; +- u16 value = 0; +- +- do { +- /* stop lock indicator process */ +- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, +- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); +- +- /* Write magic word to enable pdr reg write */ +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, +- SIO_TOP_COMM_KEY_KEY)); +- +- if (state->m_hasSAWSW) { +- /* write to io pad configuration register - output mode */ +- CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, +- state->m_GPIOCfg)); +- +- /* use corresponding bit in io data output registar */ +- CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value)); +- if (state->m_GPIO == 0) { +- value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ +- } else { +- value |= 0x8000; /* write one to 15th bit - 1st UIO */ +- } +- /* write back to io data output register */ +- CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value)); +- +- } +- /* Write magic word to disable pdr reg write */ +- CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); +- } while (0); +- return status; +-} +- +-static int SwitchAntennaToQAM(struct drxk_state *state) +-{ +- int status = -1; +- +- if (state->m_AntennaSwitchDVBTDVBC != 0) { +- if (state->m_GPIO != state->m_AntennaDVBC) { +- state->m_GPIO = state->m_AntennaDVBC; +- status = WriteGPIO(state); +- } +- } +- return status; +-} +- +-static int SwitchAntennaToDVBT(struct drxk_state *state) +-{ +- int status = -1; +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); +- if (state->m_AntennaSwitchDVBTDVBC != 0) { +- if (state->m_GPIO != state->m_AntennaDVBT) { +- state->m_GPIO = state->m_AntennaDVBT; +- status = WriteGPIO(state); +- } +- } +- return status; +-} +- +- +-static int PowerDownDevice(struct drxk_state *state) +-{ +- /* Power down to requested mode */ +- /* Backup some register settings */ +- /* Set pins with possible pull-ups connected to them in input mode */ +- /* Analog power down */ +- /* ADC power down */ +- /* Power down device */ +- int status; +- do { +- if (state->m_bPDownOpenBridge) { +- // Open I2C bridge before power down of DRXK +- CHK_ERROR(ConfigureI2CBridge(state, true)); +- } +- // driver 0.9.0 +- CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); +- +- CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK)); +- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY)); +- state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; +- CHK_ERROR(HI_CfgCommand(state)); +- } +- while(0); +- +- if (status<0) { +- //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); +- return -1; +- } +- return 0; +-} +- +-static int load_microcode(struct drxk_state *state, char *mc_name) +-{ +- const struct firmware *fw = NULL; +- int err=0; +- +- err = request_firmware(&fw, mc_name, state->i2c->dev.parent); +- if (err < 0) { +- printk(KERN_ERR +- ": Could not load firmware file %s.\n", mc_name); +- printk(KERN_INFO +- ": Copy %s to your hotplug directory!\n", mc_name); +- return err; +- } +- err=DownloadMicrocode(state, fw->data, fw->size); +- release_firmware(fw); +- return err; +-} +- +-static int init_drxk(struct drxk_state *state) +-{ +- int status; +- DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; +- u16 driverVersion; +- +- //printk("init_drxk\n"); +- if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { +- do { +- CHK_ERROR(PowerUpDevice(state)); +- CHK_ERROR (DRXX_Open(state)); +- /* Soft reset of OFDM-, sys- and osc-clockdomain */ +- CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, +- SIO_CC_SOFT_RST_OFDM__M | +- SIO_CC_SOFT_RST_SYS__M | +- SIO_CC_SOFT_RST_OSC__M)); +- CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); +- /* TODO is this needed, if yes how much delay in worst case scenario */ +- msleep(1); +- state->m_DRXK_A3_PATCH_CODE = true; +- CHK_ERROR(GetDeviceCapabilities(state)); +- +- /* Bridge delay, uses oscilator clock */ +- /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ +- /* SDA brdige delay */ +- state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000; +- /* Clipping */ +- if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) +- { +- state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; +- } +- /* SCL bridge delay, same as SDA for now */ +- state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; +- +- CHK_ERROR(InitHI(state)); +- /* disable various processes */ +-#if NOA1ROM +- if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) ) +-#endif +- { +- CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); +- } +- +- /* disable MPEG port */ +- CHK_ERROR(MPEGTSDisable(state)); +- +- /* Stop AUD and SCU */ +- CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP)); +- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP)); +- +- /* enable token-ring bus through OFDM block for possible ucode upload */ +- CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); +- +- /* include boot loader section */ +- CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE)); +- CHK_ERROR(BLChainCmd(state, 0, 6, 100)); +- +-#if 0 +- if (state->m_DRXK_A3_PATCH_CODE) +- CHK_ERROR(DownloadMicrocode(state, +- DRXK_A3_microcode, +- DRXK_A3_microcode_length)); +-#else +- load_microcode(state, "drxk_a3.mc"); +-#endif +-#if NOA1ROM +- if (state->m_DRXK_A2_PATCH_CODE) +- CHK_ERROR(DownloadMicrocode(state, +- DRXK_A2_microcode, +- DRXK_A2_microcode_length)); +-#endif +- /* disable token-ring bus through OFDM block for possible ucode upload */ +- CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); +- +- /* Run SCU for a little while to initialize microcode version numbers */ +- CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); +- CHK_ERROR (DRXX_Open(state)); +- // added for test +- msleep(30); +- +- powerMode = DRXK_POWER_DOWN_OFDM; +- CHK_ERROR(CtrlPowerMode(state, &powerMode)); +- +- /* Stamp driver version number in SCU data RAM in BCD code +- Done to enable field application engineers to retreive drxdriver version +- via I2C from SCU RAM. +- Not using SCU command interface for SCU register access since no +- microcode may be present. +- */ +- driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) + +- (((DRXK_VERSION_MAJOR/10) % 10) << 8) + +- ((DRXK_VERSION_MAJOR%10) << 4) + +- (DRXK_VERSION_MINOR%10); +- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion )); +- driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) + +- (((DRXK_VERSION_PATCH/100) % 10) << 8) + +- (((DRXK_VERSION_PATCH/10) % 10) << 4) + +- (DRXK_VERSION_PATCH%10); +- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion )); +- +- printk("DRXK driver version:%d.%d.%d\n", +- DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH); +- +- /* Dirty fix of default values for ROM/PATCH microcode +- Dirty because this fix makes it impossible to setup suitable values +- before calling DRX_Open. This solution requires changes to RF AGC speed +- to be done via the CTRL function after calling DRX_Open */ +- +- // m_dvbtRfAgcCfg.speed=3; +- +- /* Reset driver debug flags to 0 */ +- CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0)); +- /* driver 0.9.0 */ +- /* Setup FEC OC: +- NOTE: No more full FEC resets allowed afterwards!! */ +- CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP)); +- // MPEGTS functions are still the same +- CHK_ERROR(MPEGTSDtoInit(state)); +- CHK_ERROR(MPEGTSStop(state)); +- CHK_ERROR(MPEGTSConfigurePolarity(state)); +- CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput)); +- // added: configure GPIO +- CHK_ERROR(WriteGPIO(state)); +- +- state->m_DrxkState = DRXK_STOPPED; +- +- if (state->m_bPowerDown) { +- CHK_ERROR(PowerDownDevice(state)); +- state->m_DrxkState = DRXK_POWERED_DOWN; +- } +- else +- state->m_DrxkState = DRXK_STOPPED; +- } while(0); +- //printk("%s=%d\n", __FUNCTION__, status); +- } +- else +- { +- //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n")); +- } +- +- return 0; +-} +- +-static void drxk_c_release(struct dvb_frontend* fe) +-{ +- struct drxk_state *state=fe->demodulator_priv; +- printk("%s\n", __FUNCTION__); +- kfree(state); +-} +- +-static int drxk_c_init (struct dvb_frontend *fe) +-{ +- struct drxk_state *state=fe->demodulator_priv; +- +- if (mutex_trylock(&state->ctlock)==0) +- return -EBUSY; +- SetOperationMode(state, OM_QAM_ITU_A); +- return 0; +-} +- +-static int drxk_c_sleep(struct dvb_frontend* fe) +-{ +- struct drxk_state *state=fe->demodulator_priv; +- +- ShutDown(state); +- mutex_unlock(&state->ctlock); +- return 0; +-} +- +-static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable) +-{ +- struct drxk_state *state = fe->demodulator_priv; +- +- //printk("drxk_gate %d\n", enable); +- return ConfigureI2CBridge(state, enable ? true : false); +-} +- +-#ifndef USE_API3 +-static int drxk_set_parameters (struct dvb_frontend *fe) +-#else +-static int drxk_set_parameters (struct dvb_frontend *fe, +- struct dvb_frontend_parameters *p) +-#endif +-{ +-#ifndef USE_API3 +- struct dtv_frontend_properties *p = &fe->dtv_property_cache; +- u32 delsys = p->delivery_system, old_delsys; +-#endif +- struct drxk_state *state = fe->demodulator_priv; +- u32 IF; +- +- //printk("%s\n", __FUNCTION__); +- +- if (fe->ops.i2c_gate_ctrl) +- fe->ops.i2c_gate_ctrl(fe, 1); +- if (fe->ops.tuner_ops.set_params) +-#ifndef USE_API3 +- fe->ops.tuner_ops.set_params(fe); +-#else +- fe->ops.tuner_ops.set_params(fe, p); +-#endif +- if (fe->ops.i2c_gate_ctrl) +- fe->ops.i2c_gate_ctrl(fe, 0); +-#ifndef USE_API3 +-#else +- state->param=*p; +-#endif +- fe->ops.tuner_ops.get_if_frequency(fe, &IF); /* WTF is a frequency frequency? */ +- Start(state, 0, IF); +- +- //printk("%s IF=%d done\n", __FUNCTION__, IF); +- return 0; +-} +- +-static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +-{ +- //struct drxk_state *state = fe->demodulator_priv; +- //printk("%s\n", __FUNCTION__); +- return 0; +-} +- +-static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) +-{ +- struct drxk_state *state = fe->demodulator_priv; +- u32 stat; +- +- *status=0; +- GetLockStatus(state, &stat, 0); +- if (stat==MPEG_LOCK) +- *status|=0x1f; +- if (stat==FEC_LOCK) +- *status|=0x0f; +- if (stat==DEMOD_LOCK) +- *status|=0x07; +- return 0; +-} +- +-static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) +-{ +- //struct drxk_state *state = fe->demodulator_priv; +- *ber=0; +- return 0; +-} +- +-static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +-{ +- struct drxk_state *state = fe->demodulator_priv; +- u32 val; +- +- ReadIFAgc(state, &val); +- *strength = val & 0xffff;; +- return 0; +-} +- +-static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) +-{ +- struct drxk_state *state = fe->demodulator_priv; +- s32 snr2; +- +- GetSignalToNoise(state, &snr2); +- *snr = snr2&0xffff; +- return 0; +-} +- +-static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +-{ +- struct drxk_state *state = fe->demodulator_priv; +- u16 err; +- +- DVBTQAMGetAccPktErr(state, &err); +- *ucblocks = (u32) err; +- return 0; +-} +- +-static int drxk_c_get_tune_settings(struct dvb_frontend *fe, +- struct dvb_frontend_tune_settings *sets) +-{ +- sets->min_delay_ms=3000; +- sets->max_drift=0; +- sets->step_size=0; +- return 0; +-} +- +-static void drxk_t_release(struct dvb_frontend* fe) +-{ +- //struct drxk_state *state=fe->demodulator_priv; +- //printk("%s\n", __FUNCTION__); +- //kfree(state); +-} +- +-static int drxk_t_init (struct dvb_frontend *fe) +-{ +- struct drxk_state *state=fe->demodulator_priv; +- if (mutex_trylock(&state->ctlock)==0) +- return -EBUSY; +- //printk("%s\n", __FUNCTION__); +- SetOperationMode(state, OM_DVBT); +- //printk("%s done\n", __FUNCTION__); +- return 0; +-} +- +-static int drxk_t_sleep(struct dvb_frontend* fe) +-{ +- struct drxk_state *state=fe->demodulator_priv; +- mutex_unlock(&state->ctlock); +- return 0; +-} +- +-static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +-{ +- //struct drxk_state *state = fe->demodulator_priv; +- //printk("%s\n", __FUNCTION__); +- return 0; +-} +- +-static struct dvb_frontend_ops drxk_c_ops = { +- .info = { +- .name = "DRXK DVB-C", +- .type = FE_QAM, +- .frequency_stepsize = 62500, +- .frequency_min = 47000000, +- .frequency_max = 862000000, +- .symbol_rate_min = 870000, +- .symbol_rate_max = 11700000, +- .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | +- FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO +- }, +- .release = drxk_c_release, +- .init = drxk_c_init, +- .sleep = drxk_c_sleep, +- .i2c_gate_ctrl = drxk_gate_ctrl, +- +- .set_frontend = drxk_set_parameters, +- .get_frontend = drxk_c_get_frontend, +- .get_tune_settings = drxk_c_get_tune_settings, +- +- .read_status = drxk_read_status, +- .read_ber = drxk_read_ber, +- .read_signal_strength = drxk_read_signal_strength, +- .read_snr = drxk_read_snr, +- .read_ucblocks = drxk_read_ucblocks, +-}; +- +-static struct dvb_frontend_ops drxk_t_ops = { +- .info = { +- .name = "DRXK DVB-T", +- .type = FE_OFDM, +- .frequency_min = 47125000, +- .frequency_max = 865000000, +- .frequency_stepsize = 166667, +- .frequency_tolerance = 0, +- .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | +- FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | +- FE_CAN_FEC_AUTO | +- FE_CAN_QAM_16 | FE_CAN_QAM_64 | +- FE_CAN_QAM_AUTO | +- FE_CAN_TRANSMISSION_MODE_AUTO | +- FE_CAN_GUARD_INTERVAL_AUTO | +- FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | +- FE_CAN_MUTE_TS +- }, +- .release = drxk_t_release, +- .init = drxk_t_init, +- .sleep = drxk_t_sleep, +- .i2c_gate_ctrl = drxk_gate_ctrl, +- +- .set_frontend = drxk_set_parameters, +- .get_frontend = drxk_t_get_frontend, +- +- .read_status = drxk_read_status, +- .read_ber = drxk_read_ber, +- .read_signal_strength = drxk_read_signal_strength, +- .read_snr = drxk_read_snr, +- .read_ucblocks = drxk_read_ucblocks, +-}; +- +-struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, +- struct dvb_frontend **fe_t) +-{ +- struct drxk_state *state = NULL; +- +- state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL); +- if (!state) +- return NULL; +- +- state->i2c=i2c; +- state->demod_address=adr; +- +- mutex_init(&state->mutex); +- mutex_init(&state->ctlock); +- +- memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops)); +- memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops)); +- state->c_frontend.demodulator_priv=state; +- state->t_frontend.demodulator_priv=state; +- +- init_state(state); +- if (init_drxk(state)<0) +- goto error; +- *fe_t = &state->t_frontend; +- return &state->c_frontend; +- +-error: +- printk("drxk: not found\n"); +- kfree(state); +- return NULL; +-} +- +-MODULE_DESCRIPTION("DRX-K driver"); +-MODULE_AUTHOR("Ralph Metzler"); +-MODULE_LICENSE("GPL"); +- +-EXPORT_SYMBOL(drxk_attach); ++/* ++ * drxk_hard: DRX-K DVB-C/T demodulator driver ++ * ++ * Copyright (C) 2010-2011 Digital Devices GmbH ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 only, as published by the Free Software Foundation. ++ * ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA ++ * 02110-1301, USA ++ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dvb_frontend.h" ++#include "drxk.h" ++#include "drxk_hard.h" ++ ++static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); ++static int PowerDownQAM(struct drxk_state *state); ++static int SetDVBTStandard(struct drxk_state *state, ++ enum OperationMode oMode); ++static int SetQAMStandard(struct drxk_state *state, ++ enum OperationMode oMode); ++static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, ++ s32 tunerFreqOffset); ++static int SetDVBTStandard(struct drxk_state *state, ++ enum OperationMode oMode); ++static int DVBTStart(struct drxk_state *state); ++static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, ++ s32 tunerFreqOffset); ++static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); ++static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); ++static int SwitchAntennaToQAM(struct drxk_state *state); ++static int SwitchAntennaToDVBT(struct drxk_state *state); ++ ++static bool IsDVBT(struct drxk_state *state) ++{ ++ return state->m_OperationMode == OM_DVBT; ++} ++ ++static bool IsQAM(struct drxk_state *state) ++{ ++ return state->m_OperationMode == OM_QAM_ITU_A || ++ state->m_OperationMode == OM_QAM_ITU_B || ++ state->m_OperationMode == OM_QAM_ITU_C; ++} ++ ++bool IsA1WithPatchCode(struct drxk_state *state) ++{ ++ return state->m_DRXK_A1_PATCH_CODE; ++} ++ ++bool IsA1WithRomCode(struct drxk_state *state) ++{ ++ return state->m_DRXK_A1_ROM_CODE; ++} ++ ++#define NOA1ROM 0 ++ ++#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) ++#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) ++ ++#define DEFAULT_MER_83 165 ++#define DEFAULT_MER_93 250 ++ ++#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH ++#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) ++#endif ++ ++#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH ++#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) ++#endif ++ ++#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 ++#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 ++ ++#ifndef DRXK_KI_RAGC_ATV ++#define DRXK_KI_RAGC_ATV 4 ++#endif ++#ifndef DRXK_KI_IAGC_ATV ++#define DRXK_KI_IAGC_ATV 6 ++#endif ++#ifndef DRXK_KI_DAGC_ATV ++#define DRXK_KI_DAGC_ATV 7 ++#endif ++ ++#ifndef DRXK_KI_RAGC_QAM ++#define DRXK_KI_RAGC_QAM 3 ++#endif ++#ifndef DRXK_KI_IAGC_QAM ++#define DRXK_KI_IAGC_QAM 4 ++#endif ++#ifndef DRXK_KI_DAGC_QAM ++#define DRXK_KI_DAGC_QAM 7 ++#endif ++#ifndef DRXK_KI_RAGC_DVBT ++#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) ++#endif ++#ifndef DRXK_KI_IAGC_DVBT ++#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) ++#endif ++#ifndef DRXK_KI_DAGC_DVBT ++#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) ++#endif ++ ++#ifndef DRXK_AGC_DAC_OFFSET ++#define DRXK_AGC_DAC_OFFSET (0x800) ++#endif ++ ++#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ ++#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) ++#endif ++ ++#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ ++#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) ++#endif ++ ++#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ ++#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) ++#endif ++ ++#ifndef DRXK_QAM_SYMBOLRATE_MAX ++#define DRXK_QAM_SYMBOLRATE_MAX (7233000) ++#endif ++ ++#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 ++#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 ++#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 ++#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 ++#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 ++#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 ++#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 ++#define DRXK_BL_ROM_OFFSET_UCODE 0 ++ ++#define DRXK_BLC_TIMEOUT 100 ++ ++#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 ++#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 ++ ++#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 ++ ++#ifndef DRXK_OFDM_NE_NOTCH_WIDTH ++#define DRXK_OFDM_NE_NOTCH_WIDTH (4) ++#endif ++ ++#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) ++#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) ++#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) ++#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) ++#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) ++ ++static unsigned int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "enable debug messages"); ++ ++#define dprintk(level, fmt, arg...) do { \ ++if (debug >= level) \ ++ printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \ ++} while (0) ++ ++ ++static inline u32 MulDiv32(u32 a, u32 b, u32 c) ++{ ++ u64 tmp64; ++ ++ tmp64 = (u64) a * (u64) b; ++ do_div(tmp64, c); ++ ++ return (u32) tmp64; ++} ++ ++inline u32 Frac28a(u32 a, u32 c) ++{ ++ int i = 0; ++ u32 Q1 = 0; ++ u32 R0 = 0; ++ ++ R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ ++ Q1 = a / c; /* integer part, only the 4 least significant bits ++ will be visible in the result */ ++ ++ /* division using radix 16, 7 nibbles in the result */ ++ for (i = 0; i < 7; i++) { ++ Q1 = (Q1 << 4) | (R0 / c); ++ R0 = (R0 % c) << 4; ++ } ++ /* rounding */ ++ if ((R0 >> 3) >= c) ++ Q1++; ++ ++ return Q1; ++} ++ ++static u32 Log10Times100(u32 x) ++{ ++ static const u8 scale = 15; ++ static const u8 indexWidth = 5; ++ u8 i = 0; ++ u32 y = 0; ++ u32 d = 0; ++ u32 k = 0; ++ u32 r = 0; ++ /* ++ log2lut[n] = (1< 0; k--) { ++ if (x & (((u32) 1) << scale)) ++ break; ++ x <<= 1; ++ } ++ } else { ++ for (k = scale; k < 31; k++) { ++ if ((x & (((u32) (-1)) << (scale + 1))) == 0) ++ break; ++ x >>= 1; ++ } ++ } ++ /* ++ Now x has binary point between bit[scale] and bit[scale-1] ++ and 1.0 <= x < 2.0 */ ++ ++ /* correction for divison: log(x) = log(x/y)+log(y) */ ++ y = k * ((((u32) 1) << scale) * 200); ++ ++ /* remove integer part */ ++ x &= ((((u32) 1) << scale) - 1); ++ /* get index */ ++ i = (u8) (x >> (scale - indexWidth)); ++ /* compute delta (x - a) */ ++ d = x & ((((u32) 1) << (scale - indexWidth)) - 1); ++ /* compute log, multiplication (d* (..)) must be within range ! */ ++ y += log2lut[i] + ++ ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); ++ /* Conver to log10() */ ++ y /= 108853; /* (log2(10) << scale) */ ++ r = (y >> 1); ++ /* rounding */ ++ if (y & ((u32) 1)) ++ r++; ++ return r; ++} ++ ++/****************************************************************************/ ++/* I2C **********************************************************************/ ++/****************************************************************************/ ++ ++static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) ++{ ++ struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, ++ .buf = val, .len = 1} ++ }; ++ ++ return i2c_transfer(adapter, msgs, 1); ++} ++ ++static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) ++{ ++ int status; ++ struct i2c_msg msg = { ++ .addr = adr, .flags = 0, .buf = data, .len = len }; ++ ++ dprintk(3, ":"); ++ if (debug > 2) { ++ int i; ++ for (i = 0; i < len; i++) ++ printk(KERN_CONT " %02x", data[i]); ++ printk(KERN_CONT "\n"); ++ } ++ status = i2c_transfer(adap, &msg, 1); ++ if (status >= 0 && status != 1) ++ status = -EIO; ++ ++ if (status < 0) ++ printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr); ++ ++ return status; ++} ++ ++static int i2c_read(struct i2c_adapter *adap, ++ u8 adr, u8 *msg, int len, u8 *answ, int alen) ++{ ++ int status; ++ struct i2c_msg msgs[2] = { ++ {.addr = adr, .flags = 0, ++ .buf = msg, .len = len}, ++ {.addr = adr, .flags = I2C_M_RD, ++ .buf = answ, .len = alen} ++ }; ++ ++ status = i2c_transfer(adap, msgs, 2); ++ if (status != 2) { ++ if (debug > 2) ++ printk(KERN_CONT ": ERROR!\n"); ++ if (status >= 0) ++ status = -EIO; ++ ++ printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr); ++ return status; ++ } ++ if (debug > 2) { ++ int i; ++ dprintk(2, ": read from"); ++ for (i = 0; i < len; i++) ++ printk(KERN_CONT " %02x", msg[i]); ++ printk(KERN_CONT ", value = "); ++ for (i = 0; i < alen; i++) ++ printk(KERN_CONT " %02x", answ[i]); ++ printk(KERN_CONT "\n"); ++ } ++ return 0; ++} ++ ++static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) ++{ ++ int status; ++ u8 adr = state->demod_address, mm1[4], mm2[2], len; ++ ++ if (state->single_master) ++ flags |= 0xC0; ++ ++ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { ++ mm1[0] = (((reg << 1) & 0xFF) | 0x01); ++ mm1[1] = ((reg >> 16) & 0xFF); ++ mm1[2] = ((reg >> 24) & 0xFF) | flags; ++ mm1[3] = ((reg >> 7) & 0xFF); ++ len = 4; ++ } else { ++ mm1[0] = ((reg << 1) & 0xFF); ++ mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); ++ len = 2; ++ } ++ dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); ++ status = i2c_read(state->i2c, adr, mm1, len, mm2, 2); ++ if (status < 0) ++ return status; ++ if (data) ++ *data = mm2[0] | (mm2[1] << 8); ++ ++ return 0; ++} ++ ++static int read16(struct drxk_state *state, u32 reg, u16 *data) ++{ ++ return read16_flags(state, reg, data, 0); ++} ++ ++static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) ++{ ++ int status; ++ u8 adr = state->demod_address, mm1[4], mm2[4], len; ++ ++ if (state->single_master) ++ flags |= 0xC0; ++ ++ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { ++ mm1[0] = (((reg << 1) & 0xFF) | 0x01); ++ mm1[1] = ((reg >> 16) & 0xFF); ++ mm1[2] = ((reg >> 24) & 0xFF) | flags; ++ mm1[3] = ((reg >> 7) & 0xFF); ++ len = 4; ++ } else { ++ mm1[0] = ((reg << 1) & 0xFF); ++ mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); ++ len = 2; ++ } ++ dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); ++ status = i2c_read(state->i2c, adr, mm1, len, mm2, 4); ++ if (status < 0) ++ return status; ++ if (data) ++ *data = mm2[0] | (mm2[1] << 8) | ++ (mm2[2] << 16) | (mm2[3] << 24); ++ ++ return 0; ++} ++ ++static int read32(struct drxk_state *state, u32 reg, u32 *data) ++{ ++ return read32_flags(state, reg, data, 0); ++} ++ ++static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) ++{ ++ u8 adr = state->demod_address, mm[6], len; ++ ++ if (state->single_master) ++ flags |= 0xC0; ++ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { ++ mm[0] = (((reg << 1) & 0xFF) | 0x01); ++ mm[1] = ((reg >> 16) & 0xFF); ++ mm[2] = ((reg >> 24) & 0xFF) | flags; ++ mm[3] = ((reg >> 7) & 0xFF); ++ len = 4; ++ } else { ++ mm[0] = ((reg << 1) & 0xFF); ++ mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); ++ len = 2; ++ } ++ mm[len] = data & 0xff; ++ mm[len + 1] = (data >> 8) & 0xff; ++ ++ dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); ++ return i2c_write(state->i2c, adr, mm, len + 2); ++} ++ ++static int write16(struct drxk_state *state, u32 reg, u16 data) ++{ ++ return write16_flags(state, reg, data, 0); ++} ++ ++static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) ++{ ++ u8 adr = state->demod_address, mm[8], len; ++ ++ if (state->single_master) ++ flags |= 0xC0; ++ if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { ++ mm[0] = (((reg << 1) & 0xFF) | 0x01); ++ mm[1] = ((reg >> 16) & 0xFF); ++ mm[2] = ((reg >> 24) & 0xFF) | flags; ++ mm[3] = ((reg >> 7) & 0xFF); ++ len = 4; ++ } else { ++ mm[0] = ((reg << 1) & 0xFF); ++ mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); ++ len = 2; ++ } ++ mm[len] = data & 0xff; ++ mm[len + 1] = (data >> 8) & 0xff; ++ mm[len + 2] = (data >> 16) & 0xff; ++ mm[len + 3] = (data >> 24) & 0xff; ++ dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); ++ ++ return i2c_write(state->i2c, adr, mm, len + 4); ++} ++ ++static int write32(struct drxk_state *state, u32 reg, u32 data) ++{ ++ return write32_flags(state, reg, data, 0); ++} ++ ++static int write_block(struct drxk_state *state, u32 Address, ++ const int BlockSize, const u8 pBlock[]) ++{ ++ int status = 0, BlkSize = BlockSize; ++ u8 Flags = 0; ++ ++ if (state->single_master) ++ Flags |= 0xC0; ++ ++ while (BlkSize > 0) { ++ int Chunk = BlkSize > state->m_ChunkSize ? ++ state->m_ChunkSize : BlkSize; ++ u8 *AdrBuf = &state->Chunk[0]; ++ u32 AdrLength = 0; ++ ++ if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { ++ AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); ++ AdrBuf[1] = ((Address >> 16) & 0xFF); ++ AdrBuf[2] = ((Address >> 24) & 0xFF); ++ AdrBuf[3] = ((Address >> 7) & 0xFF); ++ AdrBuf[2] |= Flags; ++ AdrLength = 4; ++ if (Chunk == state->m_ChunkSize) ++ Chunk -= 2; ++ } else { ++ AdrBuf[0] = ((Address << 1) & 0xFF); ++ AdrBuf[1] = (((Address >> 16) & 0x0F) | ++ ((Address >> 18) & 0xF0)); ++ AdrLength = 2; ++ } ++ memcpy(&state->Chunk[AdrLength], pBlock, Chunk); ++ dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags); ++ if (debug > 1) { ++ int i; ++ if (pBlock) ++ for (i = 0; i < Chunk; i++) ++ printk(KERN_CONT " %02x", pBlock[i]); ++ printk(KERN_CONT "\n"); ++ } ++ status = i2c_write(state->i2c, state->demod_address, ++ &state->Chunk[0], Chunk + AdrLength); ++ if (status < 0) { ++ printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n", ++ __func__, Address); ++ break; ++ } ++ pBlock += Chunk; ++ Address += (Chunk >> 1); ++ BlkSize -= Chunk; ++ } ++ return status; ++} ++ ++#ifndef DRXK_MAX_RETRIES_POWERUP ++#define DRXK_MAX_RETRIES_POWERUP 20 ++#endif ++ ++int PowerUpDevice(struct drxk_state *state) ++{ ++ int status; ++ u8 data = 0; ++ u16 retryCount = 0; ++ ++ dprintk(1, "\n"); ++ ++ status = i2c_read1(state->i2c, state->demod_address, &data); ++ if (status < 0) { ++ do { ++ data = 0; ++ status = i2c_write(state->i2c, state->demod_address, ++ &data, 1); ++ msleep(10); ++ retryCount++; ++ if (status < 0) ++ continue; ++ status = i2c_read1(state->i2c, state->demod_address, ++ &data); ++ } while (status < 0 && ++ (retryCount < DRXK_MAX_RETRIES_POWERUP)); ++ if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP) ++ goto error; ++ } ++ ++ /* Make sure all clk domains are active */ ++ status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); ++ if (status < 0) ++ goto error; ++ /* Enable pll lock tests */ ++ status = write16(state, SIO_CC_PLL_LOCK__A, 1); ++ if (status < 0) ++ goto error; ++ ++ state->m_currentPowerMode = DRX_POWER_UP; ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++ ++static int init_state(struct drxk_state *state) ++{ ++ /* ++ * FIXME: most (all?) of the values bellow should be moved into ++ * struct drxk_config, as they are probably board-specific ++ */ ++ u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; ++ u32 ulVSBIfAgcOutputLevel = 0; ++ u32 ulVSBIfAgcMinLevel = 0; ++ u32 ulVSBIfAgcMaxLevel = 0x7FFF; ++ u32 ulVSBIfAgcSpeed = 3; ++ ++ u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; ++ u32 ulVSBRfAgcOutputLevel = 0; ++ u32 ulVSBRfAgcMinLevel = 0; ++ u32 ulVSBRfAgcMaxLevel = 0x7FFF; ++ u32 ulVSBRfAgcSpeed = 3; ++ u32 ulVSBRfAgcTop = 9500; ++ u32 ulVSBRfAgcCutOffCurrent = 4000; ++ ++ u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; ++ u32 ulATVIfAgcOutputLevel = 0; ++ u32 ulATVIfAgcMinLevel = 0; ++ u32 ulATVIfAgcMaxLevel = 0; ++ u32 ulATVIfAgcSpeed = 3; ++ ++ u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; ++ u32 ulATVRfAgcOutputLevel = 0; ++ u32 ulATVRfAgcMinLevel = 0; ++ u32 ulATVRfAgcMaxLevel = 0; ++ u32 ulATVRfAgcTop = 9500; ++ u32 ulATVRfAgcCutOffCurrent = 4000; ++ u32 ulATVRfAgcSpeed = 3; ++ ++ u32 ulQual83 = DEFAULT_MER_83; ++ u32 ulQual93 = DEFAULT_MER_93; ++ ++ u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; ++ u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; ++ ++ /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ ++ /* io_pad_cfg_mode output mode is drive always */ ++ /* io_pad_cfg_drive is set to power 2 (23 mA) */ ++ u32 ulGPIOCfg = 0x0113; ++ u32 ulInvertTSClock = 0; ++ u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; ++ u32 ulDVBTBitrate = 50000000; ++ u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; ++ ++ u32 ulInsertRSByte = 0; ++ ++ u32 ulRfMirror = 1; ++ u32 ulPowerDown = 0; ++ ++ dprintk(1, "\n"); ++ ++ state->m_hasLNA = false; ++ state->m_hasDVBT = false; ++ state->m_hasDVBC = false; ++ state->m_hasATV = false; ++ state->m_hasOOB = false; ++ state->m_hasAudio = false; ++ ++ if (!state->m_ChunkSize) ++ state->m_ChunkSize = 124; ++ ++ state->m_oscClockFreq = 0; ++ state->m_smartAntInverted = false; ++ state->m_bPDownOpenBridge = false; ++ ++ /* real system clock frequency in kHz */ ++ state->m_sysClockFreq = 151875; ++ /* Timing div, 250ns/Psys */ ++ /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ ++ state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * ++ HI_I2C_DELAY) / 1000; ++ /* Clipping */ ++ if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) ++ state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; ++ state->m_HICfgWakeUpKey = (state->demod_address << 1); ++ /* port/bridge/power down ctrl */ ++ state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; ++ ++ state->m_bPowerDown = (ulPowerDown != 0); ++ ++ state->m_DRXK_A1_PATCH_CODE = false; ++ state->m_DRXK_A1_ROM_CODE = false; ++ state->m_DRXK_A2_ROM_CODE = false; ++ state->m_DRXK_A3_ROM_CODE = false; ++ state->m_DRXK_A2_PATCH_CODE = false; ++ state->m_DRXK_A3_PATCH_CODE = false; ++ ++ /* Init AGC and PGA parameters */ ++ /* VSB IF */ ++ state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); ++ state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); ++ state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); ++ state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); ++ state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); ++ state->m_vsbPgaCfg = 140; ++ ++ /* VSB RF */ ++ state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); ++ state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); ++ state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); ++ state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); ++ state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); ++ state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); ++ state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); ++ state->m_vsbPreSawCfg.reference = 0x07; ++ state->m_vsbPreSawCfg.usePreSaw = true; ++ ++ state->m_Quality83percent = DEFAULT_MER_83; ++ state->m_Quality93percent = DEFAULT_MER_93; ++ if (ulQual93 <= 500 && ulQual83 < ulQual93) { ++ state->m_Quality83percent = ulQual83; ++ state->m_Quality93percent = ulQual93; ++ } ++ ++ /* ATV IF */ ++ state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); ++ state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); ++ state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); ++ state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); ++ state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); ++ ++ /* ATV RF */ ++ state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); ++ state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); ++ state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); ++ state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); ++ state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); ++ state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); ++ state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); ++ state->m_atvPreSawCfg.reference = 0x04; ++ state->m_atvPreSawCfg.usePreSaw = true; ++ ++ ++ /* DVBT RF */ ++ state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; ++ state->m_dvbtRfAgcCfg.outputLevel = 0; ++ state->m_dvbtRfAgcCfg.minOutputLevel = 0; ++ state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; ++ state->m_dvbtRfAgcCfg.top = 0x2100; ++ state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; ++ state->m_dvbtRfAgcCfg.speed = 1; ++ ++ ++ /* DVBT IF */ ++ state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; ++ state->m_dvbtIfAgcCfg.outputLevel = 0; ++ state->m_dvbtIfAgcCfg.minOutputLevel = 0; ++ state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; ++ state->m_dvbtIfAgcCfg.top = 13424; ++ state->m_dvbtIfAgcCfg.cutOffCurrent = 0; ++ state->m_dvbtIfAgcCfg.speed = 3; ++ state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; ++ state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; ++ /* state->m_dvbtPgaCfg = 140; */ ++ ++ state->m_dvbtPreSawCfg.reference = 4; ++ state->m_dvbtPreSawCfg.usePreSaw = false; ++ ++ /* QAM RF */ ++ state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; ++ state->m_qamRfAgcCfg.outputLevel = 0; ++ state->m_qamRfAgcCfg.minOutputLevel = 6023; ++ state->m_qamRfAgcCfg.maxOutputLevel = 27000; ++ state->m_qamRfAgcCfg.top = 0x2380; ++ state->m_qamRfAgcCfg.cutOffCurrent = 4000; ++ state->m_qamRfAgcCfg.speed = 3; ++ ++ /* QAM IF */ ++ state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; ++ state->m_qamIfAgcCfg.outputLevel = 0; ++ state->m_qamIfAgcCfg.minOutputLevel = 0; ++ state->m_qamIfAgcCfg.maxOutputLevel = 9000; ++ state->m_qamIfAgcCfg.top = 0x0511; ++ state->m_qamIfAgcCfg.cutOffCurrent = 0; ++ state->m_qamIfAgcCfg.speed = 3; ++ state->m_qamIfAgcCfg.IngainTgtMax = 5119; ++ state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; ++ ++ state->m_qamPgaCfg = 140; ++ state->m_qamPreSawCfg.reference = 4; ++ state->m_qamPreSawCfg.usePreSaw = false; ++ ++ state->m_OperationMode = OM_NONE; ++ state->m_DrxkState = DRXK_UNINITIALIZED; ++ ++ /* MPEG output configuration */ ++ state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ ++ state->m_insertRSByte = false; /* If TRUE; insert RS byte */ ++ state->m_invertDATA = false; /* If TRUE; invert DATA signals */ ++ state->m_invertERR = false; /* If TRUE; invert ERR signal */ ++ state->m_invertSTR = false; /* If TRUE; invert STR signals */ ++ state->m_invertVAL = false; /* If TRUE; invert VAL signals */ ++ state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ ++ ++ /* If TRUE; static MPEG clockrate will be used; ++ otherwise clockrate will adapt to the bitrate of the TS */ ++ ++ state->m_DVBTBitrate = ulDVBTBitrate; ++ state->m_DVBCBitrate = ulDVBCBitrate; ++ ++ state->m_TSDataStrength = (ulTSDataStrength & 0x07); ++ ++ /* Maximum bitrate in b/s in case static clockrate is selected */ ++ state->m_mpegTsStaticBitrate = 19392658; ++ state->m_disableTEIhandling = false; ++ ++ if (ulInsertRSByte) ++ state->m_insertRSByte = true; ++ ++ state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; ++ if (ulMpegLockTimeOut < 10000) ++ state->m_MpegLockTimeOut = ulMpegLockTimeOut; ++ state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; ++ if (ulDemodLockTimeOut < 10000) ++ state->m_DemodLockTimeOut = ulDemodLockTimeOut; ++ ++ /* QAM defaults */ ++ state->m_Constellation = DRX_CONSTELLATION_AUTO; ++ state->m_qamInterleaveMode = DRXK_QAM_I12_J17; ++ state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */ ++ state->m_fecRsPrescale = 1; ++ ++ state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; ++ state->m_agcFastClipCtrlDelay = 0; ++ ++ state->m_GPIOCfg = (ulGPIOCfg); ++ ++ state->m_bPowerDown = false; ++ state->m_currentPowerMode = DRX_POWER_DOWN; ++ ++ state->m_rfmirror = (ulRfMirror == 0); ++ state->m_IfAgcPol = false; ++ return 0; ++} ++ ++static int DRXX_Open(struct drxk_state *state) ++{ ++ int status = 0; ++ u32 jtag = 0; ++ u16 bid = 0; ++ u16 key = 0; ++ ++ dprintk(1, "\n"); ++ /* stop lock indicator process */ ++ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); ++ if (status < 0) ++ goto error; ++ /* Check device id */ ++ status = read16(state, SIO_TOP_COMM_KEY__A, &key); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); ++ if (status < 0) ++ goto error; ++ status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); ++ if (status < 0) ++ goto error; ++ status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_TOP_COMM_KEY__A, key); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int GetDeviceCapabilities(struct drxk_state *state) ++{ ++ u16 sioPdrOhwCfg = 0; ++ u32 sioTopJtagidLo = 0; ++ int status; ++ const char *spin = ""; ++ ++ dprintk(1, "\n"); ++ ++ /* driver 0.9.0 */ ++ /* stop lock indicator process */ ++ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); ++ if (status < 0) ++ goto error; ++ status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); ++ if (status < 0) ++ goto error; ++ ++ switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { ++ case 0: ++ /* ignore (bypass ?) */ ++ break; ++ case 1: ++ /* 27 MHz */ ++ state->m_oscClockFreq = 27000; ++ break; ++ case 2: ++ /* 20.25 MHz */ ++ state->m_oscClockFreq = 20250; ++ break; ++ case 3: ++ /* 4 MHz */ ++ state->m_oscClockFreq = 20250; ++ break; ++ default: ++ printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n"); ++ return -EINVAL; ++ } ++ /* ++ Determine device capabilities ++ Based on pinning v14 ++ */ ++ status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); ++ if (status < 0) ++ goto error; ++ ++printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo); ++ ++ /* driver 0.9.0 */ ++ switch ((sioTopJtagidLo >> 29) & 0xF) { ++ case 0: ++ state->m_deviceSpin = DRXK_SPIN_A1; ++ spin = "A1"; ++ break; ++ case 2: ++ state->m_deviceSpin = DRXK_SPIN_A2; ++ spin = "A2"; ++ break; ++ case 3: ++ state->m_deviceSpin = DRXK_SPIN_A3; ++ spin = "A3"; ++ break; ++ default: ++ state->m_deviceSpin = DRXK_SPIN_UNKNOWN; ++ status = -EINVAL; ++ printk(KERN_ERR "drxk: Spin %d unknown\n", ++ (sioTopJtagidLo >> 29) & 0xF); ++ goto error2; ++ } ++ switch ((sioTopJtagidLo >> 12) & 0xFF) { ++ case 0x13: ++ /* typeId = DRX3913K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = false; ++ state->m_hasAudio = false; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = true; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = false; ++ state->m_hasGPIO1 = false; ++ state->m_hasIRQN = false; ++ break; ++ case 0x15: ++ /* typeId = DRX3915K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = true; ++ state->m_hasAudio = false; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = false; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = true; ++ state->m_hasGPIO1 = true; ++ state->m_hasIRQN = false; ++ break; ++ case 0x16: ++ /* typeId = DRX3916K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = true; ++ state->m_hasAudio = false; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = false; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = true; ++ state->m_hasGPIO1 = true; ++ state->m_hasIRQN = false; ++ break; ++ case 0x18: ++ /* typeId = DRX3918K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = true; ++ state->m_hasAudio = true; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = false; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = true; ++ state->m_hasGPIO1 = true; ++ state->m_hasIRQN = false; ++ break; ++ case 0x21: ++ /* typeId = DRX3921K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = true; ++ state->m_hasAudio = true; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = true; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = true; ++ state->m_hasGPIO1 = true; ++ state->m_hasIRQN = false; ++ break; ++ case 0x23: ++ /* typeId = DRX3923K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = true; ++ state->m_hasAudio = true; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = true; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = true; ++ state->m_hasGPIO1 = true; ++ state->m_hasIRQN = false; ++ break; ++ case 0x25: ++ /* typeId = DRX3925K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = true; ++ state->m_hasAudio = true; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = true; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = true; ++ state->m_hasGPIO1 = true; ++ state->m_hasIRQN = false; ++ break; ++ case 0x26: ++ /* typeId = DRX3926K_TYPE_ID */ ++ state->m_hasLNA = false; ++ state->m_hasOOB = false; ++ state->m_hasATV = true; ++ state->m_hasAudio = false; ++ state->m_hasDVBT = true; ++ state->m_hasDVBC = true; ++ state->m_hasSAWSW = true; ++ state->m_hasGPIO2 = true; ++ state->m_hasGPIO1 = true; ++ state->m_hasIRQN = false; ++ break; ++ default: ++ printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n", ++ ((sioTopJtagidLo >> 12) & 0xFF)); ++ status = -EINVAL; ++ goto error2; ++ } ++ ++ printk(KERN_INFO ++ "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", ++ ((sioTopJtagidLo >> 12) & 0xFF), spin, ++ state->m_oscClockFreq / 1000, ++ state->m_oscClockFreq % 1000); ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++error2: ++ return status; ++} ++ ++static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) ++{ ++ int status; ++ bool powerdown_cmd; ++ ++ dprintk(1, "\n"); ++ ++ /* Write command */ ++ status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); ++ if (status < 0) ++ goto error; ++ if (cmd == SIO_HI_RA_RAM_CMD_RESET) ++ msleep(1); ++ ++ powerdown_cmd = ++ (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && ++ ((state->m_HICfgCtrl) & ++ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == ++ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); ++ if (powerdown_cmd == false) { ++ /* Wait until command rdy */ ++ u32 retryCount = 0; ++ u16 waitCmd; ++ ++ do { ++ msleep(1); ++ retryCount += 1; ++ status = read16(state, SIO_HI_RA_RAM_CMD__A, ++ &waitCmd); ++ } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES) ++ && (waitCmd != 0)); ++ if (status < 0) ++ goto error; ++ status = read16(state, SIO_HI_RA_RAM_RES__A, pResult); ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static int HI_CfgCommand(struct drxk_state *state) ++{ ++ int status; ++ ++ dprintk(1, "\n"); ++ ++ mutex_lock(&state->mutex); ++ ++ status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); ++ if (status < 0) ++ goto error; ++ status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); ++ if (status < 0) ++ goto error; ++ ++ state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; ++error: ++ mutex_unlock(&state->mutex); ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int InitHI(struct drxk_state *state) ++{ ++ dprintk(1, "\n"); ++ ++ state->m_HICfgWakeUpKey = (state->demod_address << 1); ++ state->m_HICfgTimeout = 0x96FF; ++ /* port/bridge/power down ctrl */ ++ state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; ++ ++ return HI_CfgCommand(state); ++} ++ ++static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) ++{ ++ int status = -1; ++ u16 sioPdrMclkCfg = 0; ++ u16 sioPdrMdxCfg = 0; ++ u16 err_cfg = 0; ++ ++ dprintk(1, ": mpeg %s, %s mode\n", ++ mpegEnable ? "enable" : "disable", ++ state->m_enableParallel ? "parallel" : "serial"); ++ ++ /* stop lock indicator process */ ++ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); ++ if (status < 0) ++ goto error; ++ ++ /* MPEG TS pad configuration */ ++ status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); ++ if (status < 0) ++ goto error; ++ ++ if (mpegEnable == false) { ++ /* Set MPEG TS pads to inputmode */ ++ status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ } else { ++ /* Enable MPEG output */ ++ sioPdrMdxCfg = ++ ((state->m_TSDataStrength << ++ SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); ++ sioPdrMclkCfg = ((state->m_TSClockkStrength << ++ SIO_PDR_MCLK_CFG_DRIVE__B) | ++ 0x0003); ++ ++ status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ ++ if (state->enable_merr_cfg) ++ err_cfg = sioPdrMdxCfg; ++ ++ status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); ++ if (status < 0) ++ goto error; ++ ++ if (state->m_enableParallel == true) { ++ /* paralel -> enable MD1 to MD7 */ ++ status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ } else { ++ sioPdrMdxCfg = ((state->m_TSDataStrength << ++ SIO_PDR_MD0_CFG_DRIVE__B) ++ | 0x0003); ++ /* serial -> disable MD1 to MD7 */ ++ status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ } ++ status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg); ++ if (status < 0) ++ goto error; ++ } ++ /* Enable MB output over MPEG pads and ctl input */ ++ status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); ++ if (status < 0) ++ goto error; ++ /* Write nomagic word to enable pdr reg write */ ++ status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int MPEGTSDisable(struct drxk_state *state) ++{ ++ dprintk(1, "\n"); ++ ++ return MPEGTSConfigurePins(state, false); ++} ++ ++static int BLChainCmd(struct drxk_state *state, ++ u16 romOffset, u16 nrOfElements, u32 timeOut) ++{ ++ u16 blStatus = 0; ++ int status; ++ unsigned long end; ++ ++ dprintk(1, "\n"); ++ mutex_lock(&state->mutex); ++ status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); ++ if (status < 0) ++ goto error; ++ ++ end = jiffies + msecs_to_jiffies(timeOut); ++ do { ++ msleep(1); ++ status = read16(state, SIO_BL_STATUS__A, &blStatus); ++ if (status < 0) ++ goto error; ++ } while ((blStatus == 0x1) && ++ ((time_is_after_jiffies(end)))); ++ ++ if (blStatus == 0x1) { ++ printk(KERN_ERR "drxk: SIO not ready\n"); ++ status = -EINVAL; ++ goto error2; ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++error2: ++ mutex_unlock(&state->mutex); ++ return status; ++} ++ ++ ++static int DownloadMicrocode(struct drxk_state *state, ++ const u8 pMCImage[], u32 Length) ++{ ++ const u8 *pSrc = pMCImage; ++ u32 Address; ++ u16 nBlocks; ++ u16 BlockSize; ++ u32 offset = 0; ++ u32 i; ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ ++ /* down the drain (we don't care about MAGIC_WORD) */ ++#if 0 ++ /* For future reference */ ++ Drain = (pSrc[0] << 8) | pSrc[1]; ++#endif ++ pSrc += sizeof(u16); ++ offset += sizeof(u16); ++ nBlocks = (pSrc[0] << 8) | pSrc[1]; ++ pSrc += sizeof(u16); ++ offset += sizeof(u16); ++ ++ for (i = 0; i < nBlocks; i += 1) { ++ Address = (pSrc[0] << 24) | (pSrc[1] << 16) | ++ (pSrc[2] << 8) | pSrc[3]; ++ pSrc += sizeof(u32); ++ offset += sizeof(u32); ++ ++ BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); ++ pSrc += sizeof(u16); ++ offset += sizeof(u16); ++ ++#if 0 ++ /* For future reference */ ++ Flags = (pSrc[0] << 8) | pSrc[1]; ++#endif ++ pSrc += sizeof(u16); ++ offset += sizeof(u16); ++ ++#if 0 ++ /* For future reference */ ++ BlockCRC = (pSrc[0] << 8) | pSrc[1]; ++#endif ++ pSrc += sizeof(u16); ++ offset += sizeof(u16); ++ ++ if (offset + BlockSize > Length) { ++ printk(KERN_ERR "drxk: Firmware is corrupted.\n"); ++ return -EINVAL; ++ } ++ ++ status = write_block(state, Address, BlockSize, pSrc); ++ if (status < 0) { ++ printk(KERN_ERR "drxk: Error %d while loading firmware\n", status); ++ break; ++ } ++ pSrc += BlockSize; ++ offset += BlockSize; ++ } ++ return status; ++} ++ ++static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) ++{ ++ int status; ++ u16 data = 0; ++ u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; ++ u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; ++ unsigned long end; ++ ++ dprintk(1, "\n"); ++ ++ if (enable == false) { ++ desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; ++ desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; ++ } ++ ++ status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); ++ if (status >= 0 && data == desiredStatus) { ++ /* tokenring already has correct status */ ++ return status; ++ } ++ /* Disable/enable dvbt tokenring bridge */ ++ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); ++ ++ end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); ++ do { ++ status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); ++ if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end)) ++ break; ++ msleep(1); ++ } while (1); ++ if (data != desiredStatus) { ++ printk(KERN_ERR "drxk: SIO not ready\n"); ++ return -EINVAL; ++ } ++ return status; ++} ++ ++static int MPEGTSStop(struct drxk_state *state) ++{ ++ int status = 0; ++ u16 fecOcSncMode = 0; ++ u16 fecOcIprMode = 0; ++ ++ dprintk(1, "\n"); ++ ++ /* Gracefull shutdown (byte boundaries) */ ++ status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); ++ if (status < 0) ++ goto error; ++ fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; ++ status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); ++ if (status < 0) ++ goto error; ++ ++ /* Suppress MCLK during absence of data */ ++ status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode); ++ if (status < 0) ++ goto error; ++ fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; ++ status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode); ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static int scu_command(struct drxk_state *state, ++ u16 cmd, u8 parameterLen, ++ u16 *parameter, u8 resultLen, u16 *result) ++{ ++#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 ++#error DRXK register mapping no longer compatible with this routine! ++#endif ++ u16 curCmd = 0; ++ int status = -EINVAL; ++ unsigned long end; ++ u8 buffer[34]; ++ int cnt = 0, ii; ++ const char *p; ++ char errname[30]; ++ ++ dprintk(1, "\n"); ++ ++ if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || ++ ((resultLen > 0) && (result == NULL))) { ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++ } ++ ++ mutex_lock(&state->mutex); ++ ++ /* assume that the command register is ready ++ since it is checked afterwards */ ++ for (ii = parameterLen - 1; ii >= 0; ii -= 1) { ++ buffer[cnt++] = (parameter[ii] & 0xFF); ++ buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); ++ } ++ buffer[cnt++] = (cmd & 0xFF); ++ buffer[cnt++] = ((cmd >> 8) & 0xFF); ++ ++ write_block(state, SCU_RAM_PARAM_0__A - ++ (parameterLen - 1), cnt, buffer); ++ /* Wait until SCU has processed command */ ++ end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); ++ do { ++ msleep(1); ++ status = read16(state, SCU_RAM_COMMAND__A, &curCmd); ++ if (status < 0) ++ goto error; ++ } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); ++ if (curCmd != DRX_SCU_READY) { ++ printk(KERN_ERR "drxk: SCU not ready\n"); ++ status = -EIO; ++ goto error2; ++ } ++ /* read results */ ++ if ((resultLen > 0) && (result != NULL)) { ++ s16 err; ++ int ii; ++ ++ for (ii = resultLen - 1; ii >= 0; ii -= 1) { ++ status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); ++ if (status < 0) ++ goto error; ++ } ++ ++ /* Check if an error was reported by SCU */ ++ err = (s16)result[0]; ++ if (err >= 0) ++ goto error; ++ ++ /* check for the known error codes */ ++ switch (err) { ++ case SCU_RESULT_UNKCMD: ++ p = "SCU_RESULT_UNKCMD"; ++ break; ++ case SCU_RESULT_UNKSTD: ++ p = "SCU_RESULT_UNKSTD"; ++ break; ++ case SCU_RESULT_SIZE: ++ p = "SCU_RESULT_SIZE"; ++ break; ++ case SCU_RESULT_INVPAR: ++ p = "SCU_RESULT_INVPAR"; ++ break; ++ default: /* Other negative values are errors */ ++ sprintf(errname, "ERROR: %d\n", err); ++ p = errname; ++ } ++ printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd); ++ print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt); ++ status = -EINVAL; ++ goto error2; ++ } ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++error2: ++ mutex_unlock(&state->mutex); ++ return status; ++} ++ ++static int SetIqmAf(struct drxk_state *state, bool active) ++{ ++ u16 data = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ ++ /* Configure IQM */ ++ status = read16(state, IQM_AF_STDBY__A, &data); ++ if (status < 0) ++ goto error; ++ ++ if (!active) { ++ data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY ++ | IQM_AF_STDBY_STDBY_AMP_STANDBY ++ | IQM_AF_STDBY_STDBY_PD_STANDBY ++ | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ++ | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY); ++ } else { ++ data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) ++ & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) ++ & (~IQM_AF_STDBY_STDBY_PD_STANDBY) ++ & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) ++ & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) ++ ); ++ } ++ status = write16(state, IQM_AF_STDBY__A, data); ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode) ++{ ++ int status = 0; ++ u16 sioCcPwdMode = 0; ++ ++ dprintk(1, "\n"); ++ ++ /* Check arguments */ ++ if (mode == NULL) ++ return -EINVAL; ++ ++ switch (*mode) { ++ case DRX_POWER_UP: ++ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; ++ break; ++ case DRXK_POWER_DOWN_OFDM: ++ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; ++ break; ++ case DRXK_POWER_DOWN_CORE: ++ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; ++ break; ++ case DRXK_POWER_DOWN_PLL: ++ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; ++ break; ++ case DRX_POWER_DOWN: ++ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; ++ break; ++ default: ++ /* Unknow sleep mode */ ++ return -EINVAL; ++ } ++ ++ /* If already in requested power mode, do nothing */ ++ if (state->m_currentPowerMode == *mode) ++ return 0; ++ ++ /* For next steps make sure to start from DRX_POWER_UP mode */ ++ if (state->m_currentPowerMode != DRX_POWER_UP) { ++ status = PowerUpDevice(state); ++ if (status < 0) ++ goto error; ++ status = DVBTEnableOFDMTokenRing(state, true); ++ if (status < 0) ++ goto error; ++ } ++ ++ if (*mode == DRX_POWER_UP) { ++ /* Restore analog & pin configuartion */ ++ } else { ++ /* Power down to requested mode */ ++ /* Backup some register settings */ ++ /* Set pins with possible pull-ups connected ++ to them in input mode */ ++ /* Analog power down */ ++ /* ADC power down */ ++ /* Power down device */ ++ /* stop all comm_exec */ ++ /* Stop and power down previous standard */ ++ switch (state->m_OperationMode) { ++ case OM_DVBT: ++ status = MPEGTSStop(state); ++ if (status < 0) ++ goto error; ++ status = PowerDownDVBT(state, false); ++ if (status < 0) ++ goto error; ++ break; ++ case OM_QAM_ITU_A: ++ case OM_QAM_ITU_C: ++ status = MPEGTSStop(state); ++ if (status < 0) ++ goto error; ++ status = PowerDownQAM(state); ++ if (status < 0) ++ goto error; ++ break; ++ default: ++ break; ++ } ++ status = DVBTEnableOFDMTokenRing(state, false); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); ++ if (status < 0) ++ goto error; ++ ++ if (*mode != DRXK_POWER_DOWN_OFDM) { ++ state->m_HICfgCtrl |= ++ SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; ++ status = HI_CfgCommand(state); ++ if (status < 0) ++ goto error; ++ } ++ } ++ state->m_currentPowerMode = *mode; ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) ++{ ++ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; ++ u16 cmdResult = 0; ++ u16 data = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ ++ status = read16(state, SCU_COMM_EXEC__A, &data); ++ if (status < 0) ++ goto error; ++ if (data == SCU_COMM_EXEC_ACTIVE) { ++ /* Send OFDM stop command */ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ /* Send OFDM reset command */ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ } ++ ++ /* Reset datapath for OFDM, processors first */ ++ status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); ++ if (status < 0) ++ goto error; ++ ++ /* powerdown AFE */ ++ status = SetIqmAf(state, false); ++ if (status < 0) ++ goto error; ++ ++ /* powerdown to OFDM mode */ ++ if (setPowerMode) { ++ status = CtrlPowerMode(state, &powerMode); ++ if (status < 0) ++ goto error; ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int SetOperationMode(struct drxk_state *state, ++ enum OperationMode oMode) ++{ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ /* ++ Stop and power down previous standard ++ TODO investigate total power down instead of partial ++ power down depending on "previous" standard. ++ */ ++ ++ /* disable HW lock indicator */ ++ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); ++ if (status < 0) ++ goto error; ++ ++ /* Device is already at the required mode */ ++ if (state->m_OperationMode == oMode) ++ return 0; ++ ++ switch (state->m_OperationMode) { ++ /* OM_NONE was added for start up */ ++ case OM_NONE: ++ break; ++ case OM_DVBT: ++ status = MPEGTSStop(state); ++ if (status < 0) ++ goto error; ++ status = PowerDownDVBT(state, true); ++ if (status < 0) ++ goto error; ++ state->m_OperationMode = OM_NONE; ++ break; ++ case OM_QAM_ITU_A: /* fallthrough */ ++ case OM_QAM_ITU_C: ++ status = MPEGTSStop(state); ++ if (status < 0) ++ goto error; ++ status = PowerDownQAM(state); ++ if (status < 0) ++ goto error; ++ state->m_OperationMode = OM_NONE; ++ break; ++ case OM_QAM_ITU_B: ++ default: ++ status = -EINVAL; ++ goto error; ++ } ++ ++ /* ++ Power up new standard ++ */ ++ switch (oMode) { ++ case OM_DVBT: ++ dprintk(1, ": DVB-T\n"); ++ state->m_OperationMode = oMode; ++ status = SetDVBTStandard(state, oMode); ++ if (status < 0) ++ goto error; ++ break; ++ case OM_QAM_ITU_A: /* fallthrough */ ++ case OM_QAM_ITU_C: ++ dprintk(1, ": DVB-C Annex %c\n", ++ (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C'); ++ state->m_OperationMode = oMode; ++ status = SetQAMStandard(state, oMode); ++ if (status < 0) ++ goto error; ++ break; ++ case OM_QAM_ITU_B: ++ default: ++ status = -EINVAL; ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int Start(struct drxk_state *state, s32 offsetFreq, ++ s32 IntermediateFrequency) ++{ ++ int status = -EINVAL; ++ ++ u16 IFreqkHz; ++ s32 OffsetkHz = offsetFreq / 1000; ++ ++ dprintk(1, "\n"); ++ if (state->m_DrxkState != DRXK_STOPPED && ++ state->m_DrxkState != DRXK_DTV_STARTED) ++ goto error; ++ ++ state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON); ++ ++ if (IntermediateFrequency < 0) { ++ state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; ++ IntermediateFrequency = -IntermediateFrequency; ++ } ++ ++ switch (state->m_OperationMode) { ++ case OM_QAM_ITU_A: ++ case OM_QAM_ITU_C: ++ IFreqkHz = (IntermediateFrequency / 1000); ++ status = SetQAM(state, IFreqkHz, OffsetkHz); ++ if (status < 0) ++ goto error; ++ state->m_DrxkState = DRXK_DTV_STARTED; ++ break; ++ case OM_DVBT: ++ IFreqkHz = (IntermediateFrequency / 1000); ++ status = MPEGTSStop(state); ++ if (status < 0) ++ goto error; ++ status = SetDVBT(state, IFreqkHz, OffsetkHz); ++ if (status < 0) ++ goto error; ++ status = DVBTStart(state); ++ if (status < 0) ++ goto error; ++ state->m_DrxkState = DRXK_DTV_STARTED; ++ break; ++ default: ++ break; ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int ShutDown(struct drxk_state *state) ++{ ++ dprintk(1, "\n"); ++ ++ MPEGTSStop(state); ++ return 0; ++} ++ ++static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, ++ u32 Time) ++{ ++ int status = -EINVAL; ++ ++ dprintk(1, "\n"); ++ ++ if (pLockStatus == NULL) ++ goto error; ++ ++ *pLockStatus = NOT_LOCKED; ++ ++ /* define the SCU command code */ ++ switch (state->m_OperationMode) { ++ case OM_QAM_ITU_A: ++ case OM_QAM_ITU_B: ++ case OM_QAM_ITU_C: ++ status = GetQAMLockStatus(state, pLockStatus); ++ break; ++ case OM_DVBT: ++ status = GetDVBTLockStatus(state, pLockStatus); ++ break; ++ default: ++ break; ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int MPEGTSStart(struct drxk_state *state) ++{ ++ int status; ++ ++ u16 fecOcSncMode = 0; ++ ++ /* Allow OC to sync again */ ++ status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); ++ if (status < 0) ++ goto error; ++ fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; ++ status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int MPEGTSDtoInit(struct drxk_state *state) ++{ ++ int status; ++ ++ dprintk(1, "\n"); ++ ++ /* Rate integration settings */ ++ status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); ++ if (status < 0) ++ goto error; ++ ++ /* Additional configuration */ ++ status = write16(state, FEC_OC_OCR_INVERT__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_SNC_LWM__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_SNC_HWM__A, 12); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static int MPEGTSDtoSetup(struct drxk_state *state, ++ enum OperationMode oMode) ++{ ++ int status; ++ ++ u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ ++ u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ ++ u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ ++ u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ ++ u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ ++ u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ ++ u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ ++ u16 fecOcTmdMode = 0; ++ u16 fecOcTmdIntUpdRate = 0; ++ u32 maxBitRate = 0; ++ bool staticCLK = false; ++ ++ dprintk(1, "\n"); ++ ++ /* Check insertion of the Reed-Solomon parity bytes */ ++ status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); ++ if (status < 0) ++ goto error; ++ status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); ++ if (status < 0) ++ goto error; ++ fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); ++ fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); ++ if (state->m_insertRSByte == true) { ++ /* enable parity symbol forward */ ++ fecOcRegMode |= FEC_OC_MODE_PARITY__M; ++ /* MVAL disable during parity bytes */ ++ fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; ++ /* TS burst length to 204 */ ++ fecOcDtoBurstLen = 204; ++ } ++ ++ /* Check serial or parrallel output */ ++ fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); ++ if (state->m_enableParallel == false) { ++ /* MPEG data output is serial -> set ipr_mode[0] */ ++ fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; ++ } ++ ++ switch (oMode) { ++ case OM_DVBT: ++ maxBitRate = state->m_DVBTBitrate; ++ fecOcTmdMode = 3; ++ fecOcRcnCtlRate = 0xC00000; ++ staticCLK = state->m_DVBTStaticCLK; ++ break; ++ case OM_QAM_ITU_A: /* fallthrough */ ++ case OM_QAM_ITU_C: ++ fecOcTmdMode = 0x0004; ++ fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ ++ maxBitRate = state->m_DVBCBitrate; ++ staticCLK = state->m_DVBCStaticCLK; ++ break; ++ default: ++ status = -EINVAL; ++ } /* switch (standard) */ ++ if (status < 0) ++ goto error; ++ ++ /* Configure DTO's */ ++ if (staticCLK) { ++ u32 bitRate = 0; ++ ++ /* Rational DTO for MCLK source (static MCLK rate), ++ Dynamic DTO for optimal grouping ++ (avoid intra-packet gaps), ++ DTO offset enable to sync TS burst with MSTRT */ ++ fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | ++ FEC_OC_DTO_MODE_OFFSET_ENABLE__M); ++ fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | ++ FEC_OC_FCT_MODE_VIRT_ENA__M); ++ ++ /* Check user defined bitrate */ ++ bitRate = maxBitRate; ++ if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */ ++ bitRate = 75900000UL; ++ } ++ /* Rational DTO period: ++ dto_period = (Fsys / bitrate) - 2 ++ ++ Result should be floored, ++ to make sure >= requested bitrate ++ */ ++ fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) ++ * 1000) / bitRate); ++ if (fecOcDtoPeriod <= 2) ++ fecOcDtoPeriod = 0; ++ else ++ fecOcDtoPeriod -= 2; ++ fecOcTmdIntUpdRate = 8; ++ } else { ++ /* (commonAttr->staticCLK == false) => dynamic mode */ ++ fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; ++ fecOcFctMode = FEC_OC_FCT_MODE__PRE; ++ fecOcTmdIntUpdRate = 5; ++ } ++ ++ /* Write appropriate registers with requested configuration */ ++ status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_MODE__A, fecOcRegMode); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); ++ if (status < 0) ++ goto error; ++ ++ /* Rate integration settings */ ++ status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int MPEGTSConfigurePolarity(struct drxk_state *state) ++{ ++ u16 fecOcRegIprInvert = 0; ++ ++ /* Data mask for the output data byte */ ++ u16 InvertDataMask = ++ FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | ++ FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | ++ FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | ++ FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; ++ ++ dprintk(1, "\n"); ++ ++ /* Control selective inversion of output bits */ ++ fecOcRegIprInvert &= (~(InvertDataMask)); ++ if (state->m_invertDATA == true) ++ fecOcRegIprInvert |= InvertDataMask; ++ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); ++ if (state->m_invertERR == true) ++ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; ++ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); ++ if (state->m_invertSTR == true) ++ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; ++ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); ++ if (state->m_invertVAL == true) ++ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; ++ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); ++ if (state->m_invertCLK == true) ++ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; ++ ++ return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); ++} ++ ++#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 ++ ++static int SetAgcRf(struct drxk_state *state, ++ struct SCfgAgc *pAgcCfg, bool isDTV) ++{ ++ int status = -EINVAL; ++ u16 data = 0; ++ struct SCfgAgc *pIfAgcSettings; ++ ++ dprintk(1, "\n"); ++ ++ if (pAgcCfg == NULL) ++ goto error; ++ ++ switch (pAgcCfg->ctrlMode) { ++ case DRXK_AGC_CTRL_AUTO: ++ /* Enable RF AGC DAC */ ++ status = read16(state, IQM_AF_STDBY__A, &data); ++ if (status < 0) ++ goto error; ++ data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; ++ status = write16(state, IQM_AF_STDBY__A, data); ++ if (status < 0) ++ goto error; ++ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); ++ if (status < 0) ++ goto error; ++ ++ /* Enable SCU RF AGC loop */ ++ data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; ++ ++ /* Polarity */ ++ if (state->m_RfAgcPol) ++ data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; ++ else ++ data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; ++ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* Set speed (using complementary reduction value) */ ++ status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); ++ if (status < 0) ++ goto error; ++ ++ data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; ++ data |= (~(pAgcCfg->speed << ++ SCU_RAM_AGC_KI_RED_RAGC_RED__B) ++ & SCU_RAM_AGC_KI_RED_RAGC_RED__M); ++ ++ status = write16(state, SCU_RAM_AGC_KI_RED__A, data); ++ if (status < 0) ++ goto error; ++ ++ if (IsDVBT(state)) ++ pIfAgcSettings = &state->m_dvbtIfAgcCfg; ++ else if (IsQAM(state)) ++ pIfAgcSettings = &state->m_qamIfAgcCfg; ++ else ++ pIfAgcSettings = &state->m_atvIfAgcCfg; ++ if (pIfAgcSettings == NULL) { ++ status = -EINVAL; ++ goto error; ++ } ++ ++ /* Set TOP, only if IF-AGC is in AUTO mode */ ++ if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top); ++ if (status < 0) ++ goto error; ++ ++ /* Cut-Off current */ ++ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent); ++ if (status < 0) ++ goto error; ++ ++ /* Max. output level */ ++ status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); ++ if (status < 0) ++ goto error; ++ ++ break; ++ ++ case DRXK_AGC_CTRL_USER: ++ /* Enable RF AGC DAC */ ++ status = read16(state, IQM_AF_STDBY__A, &data); ++ if (status < 0) ++ goto error; ++ data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; ++ status = write16(state, IQM_AF_STDBY__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* Disable SCU RF AGC loop */ ++ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); ++ if (status < 0) ++ goto error; ++ data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; ++ if (state->m_RfAgcPol) ++ data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; ++ else ++ data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; ++ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* SCU c.o.c. to 0, enabling full control range */ ++ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); ++ if (status < 0) ++ goto error; ++ ++ /* Write value to output pin */ ++ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); ++ if (status < 0) ++ goto error; ++ break; ++ ++ case DRXK_AGC_CTRL_OFF: ++ /* Disable RF AGC DAC */ ++ status = read16(state, IQM_AF_STDBY__A, &data); ++ if (status < 0) ++ goto error; ++ data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; ++ status = write16(state, IQM_AF_STDBY__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* Disable SCU RF AGC loop */ ++ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); ++ if (status < 0) ++ goto error; ++ data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; ++ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); ++ if (status < 0) ++ goto error; ++ break; ++ ++ default: ++ status = -EINVAL; ++ ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 ++ ++static int SetAgcIf(struct drxk_state *state, ++ struct SCfgAgc *pAgcCfg, bool isDTV) ++{ ++ u16 data = 0; ++ int status = 0; ++ struct SCfgAgc *pRfAgcSettings; ++ ++ dprintk(1, "\n"); ++ ++ switch (pAgcCfg->ctrlMode) { ++ case DRXK_AGC_CTRL_AUTO: ++ ++ /* Enable IF AGC DAC */ ++ status = read16(state, IQM_AF_STDBY__A, &data); ++ if (status < 0) ++ goto error; ++ data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; ++ status = write16(state, IQM_AF_STDBY__A, data); ++ if (status < 0) ++ goto error; ++ ++ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); ++ if (status < 0) ++ goto error; ++ ++ /* Enable SCU IF AGC loop */ ++ data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; ++ ++ /* Polarity */ ++ if (state->m_IfAgcPol) ++ data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; ++ else ++ data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; ++ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* Set speed (using complementary reduction value) */ ++ status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); ++ if (status < 0) ++ goto error; ++ data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; ++ data |= (~(pAgcCfg->speed << ++ SCU_RAM_AGC_KI_RED_IAGC_RED__B) ++ & SCU_RAM_AGC_KI_RED_IAGC_RED__M); ++ ++ status = write16(state, SCU_RAM_AGC_KI_RED__A, data); ++ if (status < 0) ++ goto error; ++ ++ if (IsQAM(state)) ++ pRfAgcSettings = &state->m_qamRfAgcCfg; ++ else ++ pRfAgcSettings = &state->m_atvRfAgcCfg; ++ if (pRfAgcSettings == NULL) ++ return -1; ++ /* Restore TOP */ ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); ++ if (status < 0) ++ goto error; ++ break; ++ ++ case DRXK_AGC_CTRL_USER: ++ ++ /* Enable IF AGC DAC */ ++ status = read16(state, IQM_AF_STDBY__A, &data); ++ if (status < 0) ++ goto error; ++ data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; ++ status = write16(state, IQM_AF_STDBY__A, data); ++ if (status < 0) ++ goto error; ++ ++ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); ++ if (status < 0) ++ goto error; ++ ++ /* Disable SCU IF AGC loop */ ++ data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; ++ ++ /* Polarity */ ++ if (state->m_IfAgcPol) ++ data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; ++ else ++ data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; ++ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* Write value to output pin */ ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); ++ if (status < 0) ++ goto error; ++ break; ++ ++ case DRXK_AGC_CTRL_OFF: ++ ++ /* Disable If AGC DAC */ ++ status = read16(state, IQM_AF_STDBY__A, &data); ++ if (status < 0) ++ goto error; ++ data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; ++ status = write16(state, IQM_AF_STDBY__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* Disable SCU IF AGC loop */ ++ status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); ++ if (status < 0) ++ goto error; ++ data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; ++ status = write16(state, SCU_RAM_AGC_CONFIG__A, data); ++ if (status < 0) ++ goto error; ++ break; ++ } /* switch (agcSettingsIf->ctrlMode) */ ++ ++ /* always set the top to support ++ configurations without if-loop */ ++ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int ReadIFAgc(struct drxk_state *state, u32 *pValue) ++{ ++ u16 agcDacLvl; ++ int status; ++ u16 Level = 0; ++ ++ dprintk(1, "\n"); ++ ++ status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl); ++ if (status < 0) { ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++ } ++ ++ *pValue = 0; ++ ++ if (agcDacLvl > DRXK_AGC_DAC_OFFSET) ++ Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; ++ if (Level < 14000) ++ *pValue = (14000 - Level) / 4; ++ else ++ *pValue = 0; ++ ++ return status; ++} ++ ++static int GetQAMSignalToNoise(struct drxk_state *state, ++ s32 *pSignalToNoise) ++{ ++ int status = 0; ++ u16 qamSlErrPower = 0; /* accum. error between ++ raw and sliced symbols */ ++ u32 qamSlSigPower = 0; /* used for MER, depends of ++ QAM modulation */ ++ u32 qamSlMer = 0; /* QAM MER */ ++ ++ dprintk(1, "\n"); ++ ++ /* MER calculation */ ++ ++ /* get the register value needed for MER */ ++ status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower); ++ if (status < 0) { ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return -EINVAL; ++ } ++ ++ switch (state->props.modulation) { ++ case QAM_16: ++ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; ++ break; ++ case QAM_32: ++ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; ++ break; ++ case QAM_64: ++ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; ++ break; ++ case QAM_128: ++ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; ++ break; ++ default: ++ case QAM_256: ++ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; ++ break; ++ } ++ ++ if (qamSlErrPower > 0) { ++ qamSlMer = Log10Times100(qamSlSigPower) - ++ Log10Times100((u32) qamSlErrPower); ++ } ++ *pSignalToNoise = qamSlMer; ++ ++ return status; ++} ++ ++static int GetDVBTSignalToNoise(struct drxk_state *state, ++ s32 *pSignalToNoise) ++{ ++ int status; ++ u16 regData = 0; ++ u32 EqRegTdSqrErrI = 0; ++ u32 EqRegTdSqrErrQ = 0; ++ u16 EqRegTdSqrErrExp = 0; ++ u16 EqRegTdTpsPwrOfs = 0; ++ u16 EqRegTdReqSmbCnt = 0; ++ u32 tpsCnt = 0; ++ u32 SqrErrIQ = 0; ++ u32 a = 0; ++ u32 b = 0; ++ u32 c = 0; ++ u32 iMER = 0; ++ u16 transmissionParams = 0; ++ ++ dprintk(1, "\n"); ++ ++ status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); ++ if (status < 0) ++ goto error; ++ status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); ++ if (status < 0) ++ goto error; ++ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); ++ if (status < 0) ++ goto error; ++ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data); ++ if (status < 0) ++ goto error; ++ /* Extend SQR_ERR_I operational range */ ++ EqRegTdSqrErrI = (u32) regData; ++ if ((EqRegTdSqrErrExp > 11) && ++ (EqRegTdSqrErrI < 0x00000FFFUL)) { ++ EqRegTdSqrErrI += 0x00010000UL; ++ } ++ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data); ++ if (status < 0) ++ goto error; ++ /* Extend SQR_ERR_Q operational range */ ++ EqRegTdSqrErrQ = (u32) regData; ++ if ((EqRegTdSqrErrExp > 11) && ++ (EqRegTdSqrErrQ < 0x00000FFFUL)) ++ EqRegTdSqrErrQ += 0x00010000UL; ++ ++ status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); ++ if (status < 0) ++ goto error; ++ ++ /* Check input data for MER */ ++ ++ /* MER calculation (in 0.1 dB) without math.h */ ++ if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) ++ iMER = 0; ++ else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { ++ /* No error at all, this must be the HW reset value ++ * Apparently no first measurement yet ++ * Set MER to 0.0 */ ++ iMER = 0; ++ } else { ++ SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << ++ EqRegTdSqrErrExp; ++ if ((transmissionParams & ++ OFDM_SC_RA_RAM_OP_PARAM_MODE__M) ++ == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) ++ tpsCnt = 17; ++ else ++ tpsCnt = 68; ++ ++ /* IMER = 100 * log10 (x) ++ where x = (EqRegTdTpsPwrOfs^2 * ++ EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ ++ ++ => IMER = a + b -c ++ where a = 100 * log10 (EqRegTdTpsPwrOfs^2) ++ b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) ++ c = 100 * log10 (SqrErrIQ) ++ */ ++ ++ /* log(x) x = 9bits * 9bits->18 bits */ ++ a = Log10Times100(EqRegTdTpsPwrOfs * ++ EqRegTdTpsPwrOfs); ++ /* log(x) x = 16bits * 7bits->23 bits */ ++ b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt); ++ /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ ++ c = Log10Times100(SqrErrIQ); ++ ++ iMER = a + b; ++ /* No negative MER, clip to zero */ ++ if (iMER > c) ++ iMER -= c; ++ else ++ iMER = 0; ++ } ++ *pSignalToNoise = iMER; ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) ++{ ++ dprintk(1, "\n"); ++ ++ *pSignalToNoise = 0; ++ switch (state->m_OperationMode) { ++ case OM_DVBT: ++ return GetDVBTSignalToNoise(state, pSignalToNoise); ++ case OM_QAM_ITU_A: ++ case OM_QAM_ITU_C: ++ return GetQAMSignalToNoise(state, pSignalToNoise); ++ default: ++ break; ++ } ++ return 0; ++} ++ ++#if 0 ++static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) ++{ ++ /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ ++ static s32 QE_SN[] = { ++ 51, /* QPSK 1/2 */ ++ 69, /* QPSK 2/3 */ ++ 79, /* QPSK 3/4 */ ++ 89, /* QPSK 5/6 */ ++ 97, /* QPSK 7/8 */ ++ 108, /* 16-QAM 1/2 */ ++ 131, /* 16-QAM 2/3 */ ++ 146, /* 16-QAM 3/4 */ ++ 156, /* 16-QAM 5/6 */ ++ 160, /* 16-QAM 7/8 */ ++ 165, /* 64-QAM 1/2 */ ++ 187, /* 64-QAM 2/3 */ ++ 202, /* 64-QAM 3/4 */ ++ 216, /* 64-QAM 5/6 */ ++ 225, /* 64-QAM 7/8 */ ++ }; ++ ++ *pQuality = 0; ++ ++ do { ++ s32 SignalToNoise = 0; ++ u16 Constellation = 0; ++ u16 CodeRate = 0; ++ u32 SignalToNoiseRel; ++ u32 BERQuality; ++ ++ status = GetDVBTSignalToNoise(state, &SignalToNoise); ++ if (status < 0) ++ break; ++ status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation); ++ if (status < 0) ++ break; ++ Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; ++ ++ status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate); ++ if (status < 0) ++ break; ++ CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; ++ ++ if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || ++ CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) ++ break; ++ SignalToNoiseRel = SignalToNoise - ++ QE_SN[Constellation * 5 + CodeRate]; ++ BERQuality = 100; ++ ++ if (SignalToNoiseRel < -70) ++ *pQuality = 0; ++ else if (SignalToNoiseRel < 30) ++ *pQuality = ((SignalToNoiseRel + 70) * ++ BERQuality) / 100; ++ else ++ *pQuality = BERQuality; ++ } while (0); ++ return 0; ++}; ++ ++static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) ++{ ++ int status = 0; ++ *pQuality = 0; ++ ++ dprintk(1, "\n"); ++ ++ do { ++ u32 SignalToNoise = 0; ++ u32 BERQuality = 100; ++ u32 SignalToNoiseRel = 0; ++ ++ status = GetQAMSignalToNoise(state, &SignalToNoise); ++ if (status < 0) ++ break; ++ ++ switch (state->props.modulation) { ++ case QAM_16: ++ SignalToNoiseRel = SignalToNoise - 200; ++ break; ++ case QAM_32: ++ SignalToNoiseRel = SignalToNoise - 230; ++ break; /* Not in NorDig */ ++ case QAM_64: ++ SignalToNoiseRel = SignalToNoise - 260; ++ break; ++ case QAM_128: ++ SignalToNoiseRel = SignalToNoise - 290; ++ break; ++ default: ++ case QAM_256: ++ SignalToNoiseRel = SignalToNoise - 320; ++ break; ++ } ++ ++ if (SignalToNoiseRel < -70) ++ *pQuality = 0; ++ else if (SignalToNoiseRel < 30) ++ *pQuality = ((SignalToNoiseRel + 70) * ++ BERQuality) / 100; ++ else ++ *pQuality = BERQuality; ++ } while (0); ++ ++ return status; ++} ++ ++static int GetQuality(struct drxk_state *state, s32 *pQuality) ++{ ++ dprintk(1, "\n"); ++ ++ switch (state->m_OperationMode) { ++ case OM_DVBT: ++ return GetDVBTQuality(state, pQuality); ++ case OM_QAM_ITU_A: ++ return GetDVBCQuality(state, pQuality); ++ default: ++ break; ++ } ++ ++ return 0; ++} ++#endif ++ ++/* Free data ram in SIO HI */ ++#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 ++#define SIO_HI_RA_RAM_USR_END__A 0x420060 ++ ++#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) ++#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) ++#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ ++#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE ++ ++#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) ++#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) ++#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) ++ ++static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) ++{ ++ int status = -EINVAL; ++ ++ dprintk(1, "\n"); ++ ++ if (state->m_DrxkState == DRXK_UNINITIALIZED) ++ goto error; ++ if (state->m_DrxkState == DRXK_POWERED_DOWN) ++ goto error; ++ ++ if (state->no_i2c_bridge) ++ return 0; ++ ++ status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); ++ if (status < 0) ++ goto error; ++ if (bEnableBridge) { ++ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); ++ if (status < 0) ++ goto error; ++ } else { ++ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); ++ if (status < 0) ++ goto error; ++ } ++ ++ status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0); ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int SetPreSaw(struct drxk_state *state, ++ struct SCfgPreSaw *pPreSawCfg) ++{ ++ int status = -EINVAL; ++ ++ dprintk(1, "\n"); ++ ++ if ((pPreSawCfg == NULL) ++ || (pPreSawCfg->reference > IQM_AF_PDREF__M)) ++ goto error; ++ ++ status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, ++ u16 romOffset, u16 nrOfElements, u32 timeOut) ++{ ++ u16 blStatus = 0; ++ u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF); ++ u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF); ++ int status; ++ unsigned long end; ++ ++ dprintk(1, "\n"); ++ ++ mutex_lock(&state->mutex); ++ status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_TGT_HDR__A, blockbank); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_TGT_ADDR__A, offset); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); ++ if (status < 0) ++ goto error; ++ ++ end = jiffies + msecs_to_jiffies(timeOut); ++ do { ++ status = read16(state, SIO_BL_STATUS__A, &blStatus); ++ if (status < 0) ++ goto error; ++ } while ((blStatus == 0x1) && time_is_after_jiffies(end)); ++ if (blStatus == 0x1) { ++ printk(KERN_ERR "drxk: SIO not ready\n"); ++ status = -EINVAL; ++ goto error2; ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++error2: ++ mutex_unlock(&state->mutex); ++ return status; ++ ++} ++ ++static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) ++{ ++ u16 data = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ ++ /* Start measurement */ ++ status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_START_LOCK__A, 1); ++ if (status < 0) ++ goto error; ++ ++ *count = 0; ++ status = read16(state, IQM_AF_PHASE0__A, &data); ++ if (status < 0) ++ goto error; ++ if (data == 127) ++ *count = *count + 1; ++ status = read16(state, IQM_AF_PHASE1__A, &data); ++ if (status < 0) ++ goto error; ++ if (data == 127) ++ *count = *count + 1; ++ status = read16(state, IQM_AF_PHASE2__A, &data); ++ if (status < 0) ++ goto error; ++ if (data == 127) ++ *count = *count + 1; ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int ADCSynchronization(struct drxk_state *state) ++{ ++ u16 count = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ ++ status = ADCSyncMeasurement(state, &count); ++ if (status < 0) ++ goto error; ++ ++ if (count == 1) { ++ /* Try sampling on a diffrent edge */ ++ u16 clkNeg = 0; ++ ++ status = read16(state, IQM_AF_CLKNEG__A, &clkNeg); ++ if (status < 0) ++ goto error; ++ if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == ++ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { ++ clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); ++ clkNeg |= ++ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; ++ } else { ++ clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); ++ clkNeg |= ++ IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; ++ } ++ status = write16(state, IQM_AF_CLKNEG__A, clkNeg); ++ if (status < 0) ++ goto error; ++ status = ADCSyncMeasurement(state, &count); ++ if (status < 0) ++ goto error; ++ } ++ ++ if (count < 2) ++ status = -EINVAL; ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int SetFrequencyShifter(struct drxk_state *state, ++ u16 intermediateFreqkHz, ++ s32 tunerFreqOffset, bool isDTV) ++{ ++ bool selectPosImage = false; ++ u32 rfFreqResidual = tunerFreqOffset; ++ u32 fmFrequencyShift = 0; ++ bool tunerMirror = !state->m_bMirrorFreqSpect; ++ u32 adcFreq; ++ bool adcFlip; ++ int status; ++ u32 ifFreqActual; ++ u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3); ++ u32 frequencyShift; ++ bool imageToSelect; ++ ++ dprintk(1, "\n"); ++ ++ /* ++ Program frequency shifter ++ No need to account for mirroring on RF ++ */ ++ if (isDTV) { ++ if ((state->m_OperationMode == OM_QAM_ITU_A) || ++ (state->m_OperationMode == OM_QAM_ITU_C) || ++ (state->m_OperationMode == OM_DVBT)) ++ selectPosImage = true; ++ else ++ selectPosImage = false; ++ } ++ if (tunerMirror) ++ /* tuner doesn't mirror */ ++ ifFreqActual = intermediateFreqkHz + ++ rfFreqResidual + fmFrequencyShift; ++ else ++ /* tuner mirrors */ ++ ifFreqActual = intermediateFreqkHz - ++ rfFreqResidual - fmFrequencyShift; ++ if (ifFreqActual > samplingFrequency / 2) { ++ /* adc mirrors */ ++ adcFreq = samplingFrequency - ifFreqActual; ++ adcFlip = true; ++ } else { ++ /* adc doesn't mirror */ ++ adcFreq = ifFreqActual; ++ adcFlip = false; ++ } ++ ++ frequencyShift = adcFreq; ++ imageToSelect = state->m_rfmirror ^ tunerMirror ^ ++ adcFlip ^ selectPosImage; ++ state->m_IqmFsRateOfs = ++ Frac28a((frequencyShift), samplingFrequency); ++ ++ if (imageToSelect) ++ state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; ++ ++ /* Program frequency shifter with tuner offset compensation */ ++ /* frequencyShift += tunerFreqOffset; TODO */ ++ status = write32(state, IQM_FS_RATE_OFS_LO__A, ++ state->m_IqmFsRateOfs); ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int InitAGC(struct drxk_state *state, bool isDTV) ++{ ++ u16 ingainTgt = 0; ++ u16 ingainTgtMin = 0; ++ u16 ingainTgtMax = 0; ++ u16 clpCyclen = 0; ++ u16 clpSumMin = 0; ++ u16 clpDirTo = 0; ++ u16 snsSumMin = 0; ++ u16 snsSumMax = 0; ++ u16 clpSumMax = 0; ++ u16 snsDirTo = 0; ++ u16 kiInnergainMin = 0; ++ u16 ifIaccuHiTgt = 0; ++ u16 ifIaccuHiTgtMin = 0; ++ u16 ifIaccuHiTgtMax = 0; ++ u16 data = 0; ++ u16 fastClpCtrlDelay = 0; ++ u16 clpCtrlMode = 0; ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ ++ /* Common settings */ ++ snsSumMax = 1023; ++ ifIaccuHiTgtMin = 2047; ++ clpCyclen = 500; ++ clpSumMax = 1023; ++ ++ /* AGCInit() not available for DVBT; init done in microcode */ ++ if (!IsQAM(state)) { ++ printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode); ++ return -EINVAL; ++ } ++ ++ /* FIXME: Analog TV AGC require different settings */ ++ ++ /* Standard specific settings */ ++ clpSumMin = 8; ++ clpDirTo = (u16) -9; ++ clpCtrlMode = 0; ++ snsSumMin = 8; ++ snsDirTo = (u16) -9; ++ kiInnergainMin = (u16) -1030; ++ ifIaccuHiTgtMax = 0x2380; ++ ifIaccuHiTgt = 0x2380; ++ ingainTgtMin = 0x0511; ++ ingainTgt = 0x0511; ++ ingainTgtMax = 5119; ++ fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay; ++ ++ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); ++ if (status < 0) ++ goto error; ++ ++ /* Initialize inner-loop KI gain factors */ ++ status = read16(state, SCU_RAM_AGC_KI__A, &data); ++ if (status < 0) ++ goto error; ++ ++ data = 0x0657; ++ data &= ~SCU_RAM_AGC_KI_RF__M; ++ data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); ++ data &= ~SCU_RAM_AGC_KI_IF__M; ++ data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); ++ ++ status = write16(state, SCU_RAM_AGC_KI__A, data); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr) ++{ ++ int status; ++ ++ dprintk(1, "\n"); ++ if (packetErr == NULL) ++ status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); ++ else ++ status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int DVBTScCommand(struct drxk_state *state, ++ u16 cmd, u16 subcmd, ++ u16 param0, u16 param1, u16 param2, ++ u16 param3, u16 param4) ++{ ++ u16 curCmd = 0; ++ u16 errCode = 0; ++ u16 retryCnt = 0; ++ u16 scExec = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec); ++ if (scExec != 1) { ++ /* SC is not running */ ++ status = -EINVAL; ++ } ++ if (status < 0) ++ goto error; ++ ++ /* Wait until sc is ready to receive command */ ++ retryCnt = 0; ++ do { ++ msleep(1); ++ status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); ++ retryCnt++; ++ } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); ++ if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) ++ goto error; ++ ++ /* Write sub-command */ ++ switch (cmd) { ++ /* All commands using sub-cmd */ ++ case OFDM_SC_RA_RAM_CMD_PROC_START: ++ case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: ++ case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: ++ status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); ++ if (status < 0) ++ goto error; ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ ++ /* Write needed parameters and the command */ ++ switch (cmd) { ++ /* All commands using 5 parameters */ ++ /* All commands using 4 parameters */ ++ /* All commands using 3 parameters */ ++ /* All commands using 2 parameters */ ++ case OFDM_SC_RA_RAM_CMD_PROC_START: ++ case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: ++ case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: ++ status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); ++ /* All commands using 1 parameters */ ++ case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: ++ case OFDM_SC_RA_RAM_CMD_USER_IO: ++ status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); ++ /* All commands using 0 parameters */ ++ case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: ++ case OFDM_SC_RA_RAM_CMD_NULL: ++ /* Write command */ ++ status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); ++ break; ++ default: ++ /* Unknown command */ ++ status = -EINVAL; ++ } ++ if (status < 0) ++ goto error; ++ ++ /* Wait until sc is ready processing command */ ++ retryCnt = 0; ++ do { ++ msleep(1); ++ status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); ++ retryCnt++; ++ } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); ++ if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) ++ goto error; ++ ++ /* Check for illegal cmd */ ++ status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); ++ if (errCode == 0xFFFF) { ++ /* illegal command */ ++ status = -EINVAL; ++ } ++ if (status < 0) ++ goto error; ++ ++ /* Retreive results parameters from SC */ ++ switch (cmd) { ++ /* All commands yielding 5 results */ ++ /* All commands yielding 4 results */ ++ /* All commands yielding 3 results */ ++ /* All commands yielding 2 results */ ++ /* All commands yielding 1 result */ ++ case OFDM_SC_RA_RAM_CMD_USER_IO: ++ case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: ++ status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); ++ /* All commands yielding 0 results */ ++ case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: ++ case OFDM_SC_RA_RAM_CMD_SET_TIMER: ++ case OFDM_SC_RA_RAM_CMD_PROC_START: ++ case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: ++ case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: ++ case OFDM_SC_RA_RAM_CMD_NULL: ++ break; ++ default: ++ /* Unknown command */ ++ status = -EINVAL; ++ break; ++ } /* switch (cmd->cmd) */ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int PowerUpDVBT(struct drxk_state *state) ++{ ++ enum DRXPowerMode powerMode = DRX_POWER_UP; ++ int status; ++ ++ dprintk(1, "\n"); ++ status = CtrlPowerMode(state, &powerMode); ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled) ++{ ++ int status; ++ ++ dprintk(1, "\n"); ++ if (*enabled == true) ++ status = write16(state, IQM_CF_BYPASSDET__A, 0); ++ else ++ status = write16(state, IQM_CF_BYPASSDET__A, 1); ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++#define DEFAULT_FR_THRES_8K 4000 ++static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled) ++{ ++ ++ int status; ++ ++ dprintk(1, "\n"); ++ if (*enabled == true) { ++ /* write mask to 1 */ ++ status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, ++ DEFAULT_FR_THRES_8K); ++ } else { ++ /* write mask to 0 */ ++ status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); ++ } ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static int DVBTCtrlSetEchoThreshold(struct drxk_state *state, ++ struct DRXKCfgDvbtEchoThres_t *echoThres) ++{ ++ u16 data = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); ++ if (status < 0) ++ goto error; ++ ++ switch (echoThres->fftMode) { ++ case DRX_FFTMODE_2K: ++ data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; ++ data |= ((echoThres->threshold << ++ OFDM_SC_RA_RAM_ECHO_THRES_2K__B) ++ & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); ++ break; ++ case DRX_FFTMODE_8K: ++ data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; ++ data |= ((echoThres->threshold << ++ OFDM_SC_RA_RAM_ECHO_THRES_8K__B) ++ & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, ++ enum DRXKCfgDvbtSqiSpeed *speed) ++{ ++ int status = -EINVAL; ++ ++ dprintk(1, "\n"); ++ ++ switch (*speed) { ++ case DRXK_DVBT_SQI_SPEED_FAST: ++ case DRXK_DVBT_SQI_SPEED_MEDIUM: ++ case DRXK_DVBT_SQI_SPEED_SLOW: ++ break; ++ default: ++ goto error; ++ } ++ status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, ++ (u16) *speed); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief Activate DVBT specific presets ++* \param demod instance of demodulator. ++* \return DRXStatus_t. ++* ++* Called in DVBTSetStandard ++* ++*/ ++static int DVBTActivatePresets(struct drxk_state *state) ++{ ++ int status; ++ bool setincenable = false; ++ bool setfrenable = true; ++ ++ struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K }; ++ struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K }; ++ ++ dprintk(1, "\n"); ++ status = DVBTCtrlSetIncEnable(state, &setincenable); ++ if (status < 0) ++ goto error; ++ status = DVBTCtrlSetFrEnable(state, &setfrenable); ++ if (status < 0) ++ goto error; ++ status = DVBTCtrlSetEchoThreshold(state, &echoThres2k); ++ if (status < 0) ++ goto error; ++ status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief Initialize channelswitch-independent settings for DVBT. ++* \param demod instance of demodulator. ++* \return DRXStatus_t. ++* ++* For ROM code channel filter taps are loaded from the bootloader. For microcode ++* the DVB-T taps from the drxk_filters.h are used. ++*/ ++static int SetDVBTStandard(struct drxk_state *state, ++ enum OperationMode oMode) ++{ ++ u16 cmdResult = 0; ++ u16 data = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ ++ PowerUpDVBT(state); ++ /* added antenna switch */ ++ SwitchAntennaToDVBT(state); ++ /* send OFDM reset command */ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ ++ /* send OFDM setenv command */ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ ++ /* reset datapath for OFDM, processors first */ ++ status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); ++ if (status < 0) ++ goto error; ++ ++ /* IQM setup */ ++ /* synchronize on ofdstate->m_festart */ ++ status = write16(state, IQM_AF_UPD_SEL__A, 1); ++ if (status < 0) ++ goto error; ++ /* window size for clipping ADC detection */ ++ status = write16(state, IQM_AF_CLP_LEN__A, 0); ++ if (status < 0) ++ goto error; ++ /* window size for for sense pre-SAW detection */ ++ status = write16(state, IQM_AF_SNS_LEN__A, 0); ++ if (status < 0) ++ goto error; ++ /* sense threshold for sense pre-SAW detection */ ++ status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); ++ if (status < 0) ++ goto error; ++ status = SetIqmAf(state, true); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, IQM_AF_AGC_RF__A, 0); ++ if (status < 0) ++ goto error; ++ ++ /* Impulse noise cruncher setup */ ++ status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, IQM_RC_STRETCH__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_SCALE__A, 1600); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_SCALE_SH__A, 0); ++ if (status < 0) ++ goto error; ++ ++ /* virtual clipping threshold for clipping ADC detection */ ++ status = write16(state, IQM_AF_CLP_TH__A, 448); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ ++ if (status < 0) ++ goto error; ++ ++ status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); ++ if (status < 0) ++ goto error; ++ /* enable power measurement interrupt */ ++ status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); ++ if (status < 0) ++ goto error; ++ ++ /* IQM will not be reset from here, sync ADC and update/init AGC */ ++ status = ADCSynchronization(state); ++ if (status < 0) ++ goto error; ++ status = SetPreSaw(state, &state->m_dvbtPreSawCfg); ++ if (status < 0) ++ goto error; ++ ++ /* Halt SCU to enable safe non-atomic accesses */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); ++ if (status < 0) ++ goto error; ++ ++ status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true); ++ if (status < 0) ++ goto error; ++ status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true); ++ if (status < 0) ++ goto error; ++ ++ /* Set Noise Estimation notch width and enable DC fix */ ++ status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); ++ if (status < 0) ++ goto error; ++ data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; ++ status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); ++ if (status < 0) ++ goto error; ++ ++ /* Activate SCU to enable SCU commands */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ ++ if (!state->m_DRXK_A3_ROM_CODE) { ++ /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ ++ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay); ++ if (status < 0) ++ goto error; ++ } ++ ++ /* OFDM_SC setup */ ++#ifdef COMPILE_FOR_NONRT ++ status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); ++ if (status < 0) ++ goto error; ++#endif ++ ++ /* FEC setup */ ++ status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ ++ if (status < 0) ++ goto error; ++ ++ ++#ifdef COMPILE_FOR_NONRT ++ status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); ++ if (status < 0) ++ goto error; ++#else ++ status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); ++ if (status < 0) ++ goto error; ++#endif ++ status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); ++ if (status < 0) ++ goto error; ++ ++ /* Setup MPEG bus */ ++ status = MPEGTSDtoSetup(state, OM_DVBT); ++ if (status < 0) ++ goto error; ++ /* Set DVBT Presets */ ++ status = DVBTActivatePresets(state); ++ if (status < 0) ++ goto error; ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++/*============================================================================*/ ++/** ++* \brief Start dvbt demodulating for channel. ++* \param demod instance of demodulator. ++* \return DRXStatus_t. ++*/ ++static int DVBTStart(struct drxk_state *state) ++{ ++ u16 param1; ++ int status; ++ /* DRXKOfdmScCmd_t scCmd; */ ++ ++ dprintk(1, "\n"); ++ /* Start correct processes to get in lock */ ++ /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ ++ param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; ++ status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0); ++ if (status < 0) ++ goto error; ++ /* Start FEC OC */ ++ status = MPEGTSStart(state); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++ ++/*============================================================================*/ ++ ++/** ++* \brief Set up dvbt demodulator for channel. ++* \param demod instance of demodulator. ++* \return DRXStatus_t. ++* // original DVBTSetChannel() ++*/ ++static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, ++ s32 tunerFreqOffset) ++{ ++ u16 cmdResult = 0; ++ u16 transmissionParams = 0; ++ u16 operationMode = 0; ++ u32 iqmRcRateOfs = 0; ++ u32 bandwidth = 0; ++ u16 param1; ++ int status; ++ ++ dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset); ++ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ ++ /* Halt SCU to enable safe non-atomic accesses */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); ++ if (status < 0) ++ goto error; ++ ++ /* Stop processors */ ++ status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ ++ /* Mandatory fix, always stop CP, required to set spl offset back to ++ hardware default (is set to 0 by ucode during pilot detection */ ++ status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ ++ /*== Write channel settings to device =====================================*/ ++ ++ /* mode */ ++ switch (state->props.transmission_mode) { ++ case TRANSMISSION_MODE_AUTO: ++ default: ++ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; ++ /* fall through , try first guess DRX_FFTMODE_8K */ ++ case TRANSMISSION_MODE_8K: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; ++ break; ++ case TRANSMISSION_MODE_2K: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; ++ break; ++ } ++ ++ /* guard */ ++ switch (state->props.guard_interval) { ++ default: ++ case GUARD_INTERVAL_AUTO: ++ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; ++ /* fall through , try first guess DRX_GUARD_1DIV4 */ ++ case GUARD_INTERVAL_1_4: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; ++ break; ++ case GUARD_INTERVAL_1_32: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; ++ break; ++ case GUARD_INTERVAL_1_16: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; ++ break; ++ case GUARD_INTERVAL_1_8: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; ++ break; ++ } ++ ++ /* hierarchy */ ++ switch (state->props.hierarchy) { ++ case HIERARCHY_AUTO: ++ case HIERARCHY_NONE: ++ default: ++ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; ++ /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ ++ /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ ++ /* break; */ ++ case HIERARCHY_1: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; ++ break; ++ case HIERARCHY_2: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; ++ break; ++ case HIERARCHY_4: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; ++ break; ++ } ++ ++ ++ /* modulation */ ++ switch (state->props.modulation) { ++ case QAM_AUTO: ++ default: ++ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; ++ /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ ++ case QAM_64: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; ++ break; ++ case QPSK: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; ++ break; ++ case QAM_16: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; ++ break; ++ } ++#if 0 ++ /* No hierachical channels support in BDA */ ++ /* Priority (only for hierarchical channels) */ ++ switch (channel->priority) { ++ case DRX_PRIORITY_LOW: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; ++ WR16(devAddr, OFDM_EC_SB_PRIOR__A, ++ OFDM_EC_SB_PRIOR_LO); ++ break; ++ case DRX_PRIORITY_HIGH: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; ++ WR16(devAddr, OFDM_EC_SB_PRIOR__A, ++ OFDM_EC_SB_PRIOR_HI)); ++ break; ++ case DRX_PRIORITY_UNKNOWN: /* fall through */ ++ default: ++ status = -EINVAL; ++ goto error; ++ } ++#else ++ /* Set Priorty high */ ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; ++ status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); ++ if (status < 0) ++ goto error; ++#endif ++ ++ /* coderate */ ++ switch (state->props.code_rate_HP) { ++ case FEC_AUTO: ++ default: ++ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; ++ /* fall through , try first guess DRX_CODERATE_2DIV3 */ ++ case FEC_2_3: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; ++ break; ++ case FEC_1_2: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; ++ break; ++ case FEC_3_4: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; ++ break; ++ case FEC_5_6: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; ++ break; ++ case FEC_7_8: ++ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; ++ break; ++ } ++ ++ /* SAW filter selection: normaly not necesarry, but if wanted ++ the application can select a SAW filter via the driver by using UIOs */ ++ /* First determine real bandwidth (Hz) */ ++ /* Also set delay for impulse noise cruncher */ ++ /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed ++ by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC ++ functions */ ++ switch (state->props.bandwidth_hz) { ++ case 0: ++ state->props.bandwidth_hz = 8000000; ++ /* fall though */ ++ case 8000000: ++ bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; ++ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); ++ if (status < 0) ++ goto error; ++ /* cochannel protection for PAL 8 MHz */ ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); ++ if (status < 0) ++ goto error; ++ break; ++ case 7000000: ++ bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; ++ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); ++ if (status < 0) ++ goto error; ++ /* cochannel protection for PAL 7 MHz */ ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); ++ if (status < 0) ++ goto error; ++ break; ++ case 6000000: ++ bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; ++ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); ++ if (status < 0) ++ goto error; ++ /* cochannel protection for NTSC 6 MHz */ ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); ++ if (status < 0) ++ goto error; ++ break; ++ default: ++ status = -EINVAL; ++ goto error; ++ } ++ ++ if (iqmRcRateOfs == 0) { ++ /* Now compute IQM_RC_RATE_OFS ++ (((SysFreq/BandWidth)/2)/2) -1) * 2^23) ++ => ++ ((SysFreq / BandWidth) * (2^21)) - (2^23) ++ */ ++ /* (SysFreq / BandWidth) * (2^28) */ ++ /* assert (MAX(sysClk)/MIN(bandwidth) < 16) ++ => assert(MAX(sysClk) < 16*MIN(bandwidth)) ++ => assert(109714272 > 48000000) = true so Frac 28 can be used */ ++ iqmRcRateOfs = Frac28a((u32) ++ ((state->m_sysClockFreq * ++ 1000) / 3), bandwidth); ++ /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ ++ if ((iqmRcRateOfs & 0x7fL) >= 0x40) ++ iqmRcRateOfs += 0x80L; ++ iqmRcRateOfs = iqmRcRateOfs >> 7; ++ /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ ++ iqmRcRateOfs = iqmRcRateOfs - (1 << 23); ++ } ++ ++ iqmRcRateOfs &= ++ ((((u32) IQM_RC_RATE_OFS_HI__M) << ++ IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); ++ status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs); ++ if (status < 0) ++ goto error; ++ ++ /* Bandwidth setting done */ ++ ++#if 0 ++ status = DVBTSetFrequencyShift(demod, channel, tunerOffset); ++ if (status < 0) ++ goto error; ++#endif ++ status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); ++ if (status < 0) ++ goto error; ++ ++ /*== Start SC, write channel settings to SC ===============================*/ ++ ++ /* Activate SCU to enable SCU commands */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ ++ /* Enable SC after setting all other parameters */ ++ status = write16(state, OFDM_SC_COMM_STATE__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, OFDM_SC_COMM_EXEC__A, 1); ++ if (status < 0) ++ goto error; ++ ++ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ ++ /* Write SC parameter registers, set all AUTO flags in operation mode */ ++ param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | ++ OFDM_SC_RA_RAM_OP_AUTO_GUARD__M | ++ OFDM_SC_RA_RAM_OP_AUTO_CONST__M | ++ OFDM_SC_RA_RAM_OP_AUTO_HIER__M | ++ OFDM_SC_RA_RAM_OP_AUTO_RATE__M); ++ status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, ++ 0, transmissionParams, param1, 0, 0, 0); ++ if (status < 0) ++ goto error; ++ ++ if (!state->m_DRXK_A3_ROM_CODE) ++ status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++ ++/*============================================================================*/ ++ ++/** ++* \brief Retreive lock status . ++* \param demod Pointer to demodulator instance. ++* \param lockStat Pointer to lock status structure. ++* \return DRXStatus_t. ++* ++*/ ++static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) ++{ ++ int status; ++ const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | ++ OFDM_SC_RA_RAM_LOCK_FEC__M); ++ const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); ++ const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; ++ ++ u16 ScRaRamLock = 0; ++ u16 ScCommExec = 0; ++ ++ dprintk(1, "\n"); ++ ++ *pLockStatus = NOT_LOCKED; ++ /* driver 0.9.0 */ ++ /* Check if SC is running */ ++ status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); ++ if (status < 0) ++ goto end; ++ if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) ++ goto end; ++ ++ status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); ++ if (status < 0) ++ goto end; ++ ++ if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) ++ *pLockStatus = MPEG_LOCK; ++ else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) ++ *pLockStatus = FEC_LOCK; ++ else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) ++ *pLockStatus = DEMOD_LOCK; ++ else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) ++ *pLockStatus = NEVER_LOCK; ++end: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static int PowerUpQAM(struct drxk_state *state) ++{ ++ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; ++ int status; ++ ++ dprintk(1, "\n"); ++ status = CtrlPowerMode(state, &powerMode); ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++ ++/** Power Down QAM */ ++static int PowerDownQAM(struct drxk_state *state) ++{ ++ u16 data = 0; ++ u16 cmdResult; ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ status = read16(state, SCU_COMM_EXEC__A, &data); ++ if (status < 0) ++ goto error; ++ if (data == SCU_COMM_EXEC_ACTIVE) { ++ /* ++ STOP demodulator ++ QAM and HW blocks ++ */ ++ /* stop all comstate->m_exec */ ++ status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ } ++ /* powerdown AFE */ ++ status = SetIqmAf(state, false); ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief Setup of the QAM Measurement intervals for signal quality ++* \param demod instance of demod. ++* \param modulation current modulation. ++* \return DRXStatus_t. ++* ++* NOTE: ++* Take into account that for certain settings the errorcounters can overflow. ++* The implementation does not check this. ++* ++*/ ++static int SetQAMMeasurement(struct drxk_state *state, ++ enum EDrxkConstellation modulation, ++ u32 symbolRate) ++{ ++ u32 fecBitsDesired = 0; /* BER accounting period */ ++ u32 fecRsPeriodTotal = 0; /* Total period */ ++ u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ ++ u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ ++ fecRsPrescale = 1; ++ /* fecBitsDesired = symbolRate [kHz] * ++ FrameLenght [ms] * ++ (modulation + 1) * ++ SyncLoss (== 1) * ++ ViterbiLoss (==1) ++ */ ++ switch (modulation) { ++ case DRX_CONSTELLATION_QAM16: ++ fecBitsDesired = 4 * symbolRate; ++ break; ++ case DRX_CONSTELLATION_QAM32: ++ fecBitsDesired = 5 * symbolRate; ++ break; ++ case DRX_CONSTELLATION_QAM64: ++ fecBitsDesired = 6 * symbolRate; ++ break; ++ case DRX_CONSTELLATION_QAM128: ++ fecBitsDesired = 7 * symbolRate; ++ break; ++ case DRX_CONSTELLATION_QAM256: ++ fecBitsDesired = 8 * symbolRate; ++ break; ++ default: ++ status = -EINVAL; ++ } ++ if (status < 0) ++ goto error; ++ ++ fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ ++ fecBitsDesired *= 500; /* meas. period [ms] */ ++ ++ /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ ++ /* fecRsPeriodTotal = fecBitsDesired / 1632 */ ++ fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */ ++ ++ /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ ++ fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); ++ if (fecRsPrescale == 0) { ++ /* Divide by zero (though impossible) */ ++ status = -EINVAL; ++ if (status < 0) ++ goto error; ++ } ++ fecRsPeriod = ++ ((u16) fecRsPeriodTotal + ++ (fecRsPrescale >> 1)) / fecRsPrescale; ++ ++ /* write corresponding registers */ ++ status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int SetQAM16(struct drxk_state *state) ++{ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ /* QAM Equalizer Setup */ ++ /* Equalizer */ ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); ++ if (status < 0) ++ goto error; ++ /* Decision Feedback Equalizer */ ++ status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, QAM_SY_SYNC_HWM__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_AWM__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_LWM__A, 3); ++ if (status < 0) ++ goto error; ++ ++ /* QAM Slicer Settings */ ++ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); ++ if (status < 0) ++ goto error; ++ ++ /* QAM Loop Controller Coeficients */ ++ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM State Machine (FSM) Thresholds */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM FSM Tracking Parameters */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); ++ if (status < 0) ++ goto error; ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief QAM32 specific setup ++* \param demod instance of demod. ++* \return DRXStatus_t. ++*/ ++static int SetQAM32(struct drxk_state *state) ++{ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ ++ /* QAM Equalizer Setup */ ++ /* Equalizer */ ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); ++ if (status < 0) ++ goto error; ++ ++ /* Decision Feedback Equalizer */ ++ status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, QAM_SY_SYNC_HWM__A, 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_AWM__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_LWM__A, 3); ++ if (status < 0) ++ goto error; ++ ++ /* QAM Slicer Settings */ ++ ++ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM Loop Controller Coeficients */ ++ ++ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM State Machine (FSM) Thresholds */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM FSM Tracking Parameters */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief QAM64 specific setup ++* \param demod instance of demod. ++* \return DRXStatus_t. ++*/ ++static int SetQAM64(struct drxk_state *state) ++{ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ /* QAM Equalizer Setup */ ++ /* Equalizer */ ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); ++ if (status < 0) ++ goto error; ++ ++ /* Decision Feedback Equalizer */ ++ status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, QAM_SY_SYNC_HWM__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_AWM__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_LWM__A, 3); ++ if (status < 0) ++ goto error; ++ ++ /* QAM Slicer Settings */ ++ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM Loop Controller Coeficients */ ++ ++ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM State Machine (FSM) Thresholds */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM FSM Tracking Parameters */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief QAM128 specific setup ++* \param demod: instance of demod. ++* \return DRXStatus_t. ++*/ ++static int SetQAM128(struct drxk_state *state) ++{ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ /* QAM Equalizer Setup */ ++ /* Equalizer */ ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); ++ if (status < 0) ++ goto error; ++ ++ /* Decision Feedback Equalizer */ ++ status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, QAM_SY_SYNC_HWM__A, 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_AWM__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_LWM__A, 3); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM Slicer Settings */ ++ ++ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM Loop Controller Coeficients */ ++ ++ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM State Machine (FSM) Thresholds */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); ++ if (status < 0) ++ goto error; ++ ++ /* QAM FSM Tracking Parameters */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief QAM256 specific setup ++* \param demod: instance of demod. ++* \return DRXStatus_t. ++*/ ++static int SetQAM256(struct drxk_state *state) ++{ ++ int status = 0; ++ ++ dprintk(1, "\n"); ++ /* QAM Equalizer Setup */ ++ /* Equalizer */ ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); ++ if (status < 0) ++ goto error; ++ ++ /* Decision Feedback Equalizer */ ++ status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, QAM_SY_SYNC_HWM__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_AWM__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_SYNC_LWM__A, 3); ++ if (status < 0) ++ goto error; ++ ++ /* QAM Slicer Settings */ ++ ++ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM Loop Controller Coeficients */ ++ ++ status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM State Machine (FSM) Thresholds */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); ++ if (status < 0) ++ goto error; ++ ++ ++ /* QAM FSM Tracking Parameters */ ++ ++ status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++ ++/*============================================================================*/ ++/** ++* \brief Reset QAM block. ++* \param demod: instance of demod. ++* \param channel: pointer to channel data. ++* \return DRXStatus_t. ++*/ ++static int QAMResetQAM(struct drxk_state *state) ++{ ++ int status; ++ u16 cmdResult; ++ ++ dprintk(1, "\n"); ++ /* Stop QAM comstate->m_exec */ ++ status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief Set QAM symbolrate. ++* \param demod: instance of demod. ++* \param channel: pointer to channel data. ++* \return DRXStatus_t. ++*/ ++static int QAMSetSymbolrate(struct drxk_state *state) ++{ ++ u32 adcFrequency = 0; ++ u32 symbFreq = 0; ++ u32 iqmRcRate = 0; ++ u16 ratesel = 0; ++ u32 lcSymbRate = 0; ++ int status; ++ ++ dprintk(1, "\n"); ++ /* Select & calculate correct IQM rate */ ++ adcFrequency = (state->m_sysClockFreq * 1000) / 3; ++ ratesel = 0; ++ /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ ++ if (state->props.symbol_rate <= 1188750) ++ ratesel = 3; ++ else if (state->props.symbol_rate <= 2377500) ++ ratesel = 2; ++ else if (state->props.symbol_rate <= 4755000) ++ ratesel = 1; ++ status = write16(state, IQM_FD_RATESEL__A, ratesel); ++ if (status < 0) ++ goto error; ++ ++ /* ++ IqmRcRate = ((Fadc / (symbolrate * (4<props.symbol_rate * (1 << ratesel); ++ if (symbFreq == 0) { ++ /* Divide by zero */ ++ status = -EINVAL; ++ goto error; ++ } ++ iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + ++ (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - ++ (1 << 23); ++ status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate); ++ if (status < 0) ++ goto error; ++ state->m_iqmRcRate = iqmRcRate; ++ /* ++ LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) ++ */ ++ symbFreq = state->props.symbol_rate; ++ if (adcFrequency == 0) { ++ /* Divide by zero */ ++ status = -EINVAL; ++ goto error; ++ } ++ lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + ++ (Frac28a((symbFreq % adcFrequency), adcFrequency) >> ++ 16); ++ if (lcSymbRate > 511) ++ lcSymbRate = 511; ++ status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++/*============================================================================*/ ++ ++/** ++* \brief Get QAM lock status. ++* \param demod: instance of demod. ++* \param channel: pointer to channel data. ++* \return DRXStatus_t. ++*/ ++ ++static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) ++{ ++ int status; ++ u16 Result[2] = { 0, 0 }; ++ ++ dprintk(1, "\n"); ++ *pLockStatus = NOT_LOCKED; ++ status = scu_command(state, ++ SCU_RAM_COMMAND_STANDARD_QAM | ++ SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, ++ Result); ++ if (status < 0) ++ printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status); ++ ++ if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { ++ /* 0x0000 NOT LOCKED */ ++ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { ++ /* 0x4000 DEMOD LOCKED */ ++ *pLockStatus = DEMOD_LOCK; ++ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { ++ /* 0x8000 DEMOD + FEC LOCKED (system lock) */ ++ *pLockStatus = MPEG_LOCK; ++ } else { ++ /* 0xC000 NEVER LOCKED */ ++ /* (system will never be able to lock to the signal) */ ++ /* TODO: check this, intermediate & standard specific lock states are not ++ taken into account here */ ++ *pLockStatus = NEVER_LOCK; ++ } ++ return status; ++} ++ ++#define QAM_MIRROR__M 0x03 ++#define QAM_MIRROR_NORMAL 0x00 ++#define QAM_MIRRORED 0x01 ++#define QAM_MIRROR_AUTO_ON 0x02 ++#define QAM_LOCKRANGE__M 0x10 ++#define QAM_LOCKRANGE_NORMAL 0x10 ++ ++static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, ++ s32 tunerFreqOffset) ++{ ++ int status; ++ u16 setParamParameters[4] = { 0, 0, 0, 0 }; ++ u16 cmdResult; ++ ++ dprintk(1, "\n"); ++ /* ++ * STEP 1: reset demodulator ++ * resets FEC DI and FEC RS ++ * resets QAM block ++ * resets SCU variables ++ */ ++ status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = QAMResetQAM(state); ++ if (status < 0) ++ goto error; ++ ++ /* ++ * STEP 2: configure demodulator ++ * -set params; resets IQM,QAM,FEC HW; initializes some ++ * SCU variables ++ */ ++ status = QAMSetSymbolrate(state); ++ if (status < 0) ++ goto error; ++ ++ /* Set params */ ++ switch (state->props.modulation) { ++ case QAM_256: ++ state->m_Constellation = DRX_CONSTELLATION_QAM256; ++ break; ++ case QAM_AUTO: ++ case QAM_64: ++ state->m_Constellation = DRX_CONSTELLATION_QAM64; ++ break; ++ case QAM_16: ++ state->m_Constellation = DRX_CONSTELLATION_QAM16; ++ break; ++ case QAM_32: ++ state->m_Constellation = DRX_CONSTELLATION_QAM32; ++ break; ++ case QAM_128: ++ state->m_Constellation = DRX_CONSTELLATION_QAM128; ++ break; ++ default: ++ status = -EINVAL; ++ break; ++ } ++ if (status < 0) ++ goto error; ++ setParamParameters[0] = state->m_Constellation; /* modulation */ ++ setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ ++ if (state->m_OperationMode == OM_QAM_ITU_C) ++ setParamParameters[2] = QAM_TOP_ANNEX_C; ++ else ++ setParamParameters[2] = QAM_TOP_ANNEX_A; ++ setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); ++ /* Env parameters */ ++ /* check for LOCKRANGE Extented */ ++ /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */ ++ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult); ++ if (status < 0) { ++ /* Fall-back to the simpler call */ ++ if (state->m_OperationMode == OM_QAM_ITU_C) ++ setParamParameters[0] = QAM_TOP_ANNEX_C; ++ else ++ setParamParameters[0] = QAM_TOP_ANNEX_A; ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ ++ setParamParameters[0] = state->m_Constellation; /* modulation */ ++ setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult); ++ } ++ if (status < 0) ++ goto error; ++ ++ /* ++ * STEP 3: enable the system in a mode where the ADC provides valid ++ * signal setup modulation independent registers ++ */ ++#if 0 ++ status = SetFrequency(channel, tunerFreqOffset)); ++ if (status < 0) ++ goto error; ++#endif ++ status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); ++ if (status < 0) ++ goto error; ++ ++ /* Setup BER measurement */ ++ status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate); ++ if (status < 0) ++ goto error; ++ ++ /* Reset default values */ ++ status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); ++ if (status < 0) ++ goto error; ++ ++ /* Reset default LC values */ ++ status = write16(state, QAM_LC_RATE_LIMIT__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_LPF_FACTORP__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_LPF_FACTORI__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_MODE__A, 7); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, QAM_LC_QUAL_TAB0__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB1__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB2__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB3__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB4__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB5__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB6__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB8__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB9__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB10__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB12__A, 2); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB15__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB16__A, 3); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB20__A, 4); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_LC_QUAL_TAB25__A, 4); ++ if (status < 0) ++ goto error; ++ ++ /* Mirroring, QAM-block starting point not inverted */ ++ status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); ++ if (status < 0) ++ goto error; ++ ++ /* Halt SCU to enable safe non-atomic accesses */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); ++ if (status < 0) ++ goto error; ++ ++ /* STEP 4: modulation specific setup */ ++ switch (state->props.modulation) { ++ case QAM_16: ++ status = SetQAM16(state); ++ break; ++ case QAM_32: ++ status = SetQAM32(state); ++ break; ++ case QAM_AUTO: ++ case QAM_64: ++ status = SetQAM64(state); ++ break; ++ case QAM_128: ++ status = SetQAM128(state); ++ break; ++ case QAM_256: ++ status = SetQAM256(state); ++ break; ++ default: ++ status = -EINVAL; ++ break; ++ } ++ if (status < 0) ++ goto error; ++ ++ /* Activate SCU to enable SCU commands */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ ++ /* Re-configure MPEG output, requires knowledge of channel bitrate */ ++ /* extAttr->currentChannel.modulation = channel->modulation; */ ++ /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ ++ status = MPEGTSDtoSetup(state, state->m_OperationMode); ++ if (status < 0) ++ goto error; ++ ++ /* Start processes */ ++ status = MPEGTSStart(state); ++ if (status < 0) ++ goto error; ++ status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); ++ if (status < 0) ++ goto error; ++ ++ /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ ++ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); ++ if (status < 0) ++ goto error; ++ ++ /* update global DRXK data container */ ++/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ ++ ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int SetQAMStandard(struct drxk_state *state, ++ enum OperationMode oMode) ++{ ++ int status; ++#ifdef DRXK_QAM_TAPS ++#define DRXK_QAMA_TAPS_SELECT ++#include "drxk_filters.h" ++#undef DRXK_QAMA_TAPS_SELECT ++#endif ++ ++ dprintk(1, "\n"); ++ ++ /* added antenna switch */ ++ SwitchAntennaToQAM(state); ++ ++ /* Ensure correct power-up mode */ ++ status = PowerUpQAM(state); ++ if (status < 0) ++ goto error; ++ /* Reset QAM block */ ++ status = QAMResetQAM(state); ++ if (status < 0) ++ goto error; ++ ++ /* Setup IQM */ ++ ++ status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); ++ if (status < 0) ++ goto error; ++ ++ /* Upload IQM Channel Filter settings by ++ boot loader from ROM table */ ++ switch (oMode) { ++ case OM_QAM_ITU_A: ++ status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); ++ break; ++ case OM_QAM_ITU_C: ++ status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); ++ if (status < 0) ++ goto error; ++ status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); ++ break; ++ default: ++ status = -EINVAL; ++ } ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_SYMMETRIC__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, IQM_RC_STRETCH__A, 21); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_CLP_LEN__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_CLP_TH__A, 448); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_SNS_LEN__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, IQM_FS_ADJ_SEL__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_RC_ADJ_SEL__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_ADJ_SEL__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_UPD_SEL__A, 0); ++ if (status < 0) ++ goto error; ++ ++ /* IQM Impulse Noise Processing Unit */ ++ status = write16(state, IQM_CF_CLP_VAL__A, 500); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_DATATH__A, 1000); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_BYPASSDET__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_DET_LCT__A, 0); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_WND_LEN__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_CF_PKDTH__A, 1); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_INC_BYPASS__A, 1); ++ if (status < 0) ++ goto error; ++ ++ /* turn on IQMAF. Must be done before setAgc**() */ ++ status = SetIqmAf(state, true); ++ if (status < 0) ++ goto error; ++ status = write16(state, IQM_AF_START_LOCK__A, 0x01); ++ if (status < 0) ++ goto error; ++ ++ /* IQM will not be reset from here, sync ADC and update/init AGC */ ++ status = ADCSynchronization(state); ++ if (status < 0) ++ goto error; ++ ++ /* Set the FSM step period */ ++ status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); ++ if (status < 0) ++ goto error; ++ ++ /* Halt SCU to enable safe non-atomic accesses */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); ++ if (status < 0) ++ goto error; ++ ++ /* No more resets of the IQM, current standard correctly set => ++ now AGCs can be configured. */ ++ ++ status = InitAGC(state, true); ++ if (status < 0) ++ goto error; ++ status = SetPreSaw(state, &(state->m_qamPreSawCfg)); ++ if (status < 0) ++ goto error; ++ ++ /* Configure AGC's */ ++ status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true); ++ if (status < 0) ++ goto error; ++ status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true); ++ if (status < 0) ++ goto error; ++ ++ /* Activate SCU to enable SCU commands */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int WriteGPIO(struct drxk_state *state) ++{ ++ int status; ++ u16 value = 0; ++ ++ dprintk(1, "\n"); ++ /* stop lock indicator process */ ++ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); ++ if (status < 0) ++ goto error; ++ ++ /* Write magic word to enable pdr reg write */ ++ status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); ++ if (status < 0) ++ goto error; ++ ++ if (state->m_hasSAWSW) { ++ if (state->UIO_mask & 0x0001) { /* UIO-1 */ ++ /* write to io pad configuration register - output mode */ ++ status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); ++ if (status < 0) ++ goto error; ++ ++ /* use corresponding bit in io data output registar */ ++ status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); ++ if (status < 0) ++ goto error; ++ if ((state->m_GPIO & 0x0001) == 0) ++ value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ ++ else ++ value |= 0x8000; /* write one to 15th bit - 1st UIO */ ++ /* write back to io data output register */ ++ status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); ++ if (status < 0) ++ goto error; ++ } ++ if (state->UIO_mask & 0x0002) { /* UIO-2 */ ++ /* write to io pad configuration register - output mode */ ++ status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg); ++ if (status < 0) ++ goto error; ++ ++ /* use corresponding bit in io data output registar */ ++ status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); ++ if (status < 0) ++ goto error; ++ if ((state->m_GPIO & 0x0002) == 0) ++ value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ ++ else ++ value |= 0x4000; /* write one to 14th bit - 2st UIO */ ++ /* write back to io data output register */ ++ status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); ++ if (status < 0) ++ goto error; ++ } ++ if (state->UIO_mask & 0x0004) { /* UIO-3 */ ++ /* write to io pad configuration register - output mode */ ++ status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg); ++ if (status < 0) ++ goto error; ++ ++ /* use corresponding bit in io data output registar */ ++ status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); ++ if (status < 0) ++ goto error; ++ if ((state->m_GPIO & 0x0004) == 0) ++ value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ ++ else ++ value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ ++ /* write back to io data output register */ ++ status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); ++ if (status < 0) ++ goto error; ++ } ++ } ++ /* Write magic word to disable pdr reg write */ ++ status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int SwitchAntennaToQAM(struct drxk_state *state) ++{ ++ int status = 0; ++ bool gpio_state; ++ ++ dprintk(1, "\n"); ++ ++ if (!state->antenna_gpio) ++ return 0; ++ ++ gpio_state = state->m_GPIO & state->antenna_gpio; ++ ++ if (state->antenna_dvbt ^ gpio_state) { ++ /* Antenna is on DVB-T mode. Switch */ ++ if (state->antenna_dvbt) ++ state->m_GPIO &= ~state->antenna_gpio; ++ else ++ state->m_GPIO |= state->antenna_gpio; ++ status = WriteGPIO(state); ++ } ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++static int SwitchAntennaToDVBT(struct drxk_state *state) ++{ ++ int status = 0; ++ bool gpio_state; ++ ++ dprintk(1, "\n"); ++ ++ if (!state->antenna_gpio) ++ return 0; ++ ++ gpio_state = state->m_GPIO & state->antenna_gpio; ++ ++ if (!(state->antenna_dvbt ^ gpio_state)) { ++ /* Antenna is on DVB-C mode. Switch */ ++ if (state->antenna_dvbt) ++ state->m_GPIO |= state->antenna_gpio; ++ else ++ state->m_GPIO &= ~state->antenna_gpio; ++ status = WriteGPIO(state); ++ } ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ return status; ++} ++ ++ ++static int PowerDownDevice(struct drxk_state *state) ++{ ++ /* Power down to requested mode */ ++ /* Backup some register settings */ ++ /* Set pins with possible pull-ups connected to them in input mode */ ++ /* Analog power down */ ++ /* ADC power down */ ++ /* Power down device */ ++ int status; ++ ++ dprintk(1, "\n"); ++ if (state->m_bPDownOpenBridge) { ++ /* Open I2C bridge before power down of DRXK */ ++ status = ConfigureI2CBridge(state, true); ++ if (status < 0) ++ goto error; ++ } ++ /* driver 0.9.0 */ ++ status = DVBTEnableOFDMTokenRing(state, false); ++ if (status < 0) ++ goto error; ++ ++ status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); ++ if (status < 0) ++ goto error; ++ state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; ++ status = HI_CfgCommand(state); ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static int load_microcode(struct drxk_state *state, const char *mc_name) ++{ ++ const struct firmware *fw = NULL; ++ int err = 0; ++ ++ dprintk(1, "\n"); ++ ++ err = request_firmware(&fw, mc_name, state->i2c->dev.parent); ++ if (err < 0) { ++ printk(KERN_ERR ++ "drxk: Could not load firmware file %s.\n", mc_name); ++ printk(KERN_INFO ++ "drxk: Copy %s to your hotplug directory!\n", mc_name); ++ return err; ++ } ++ err = DownloadMicrocode(state, fw->data, fw->size); ++ release_firmware(fw); ++ return err; ++} ++ ++static int init_drxk(struct drxk_state *state) ++{ ++ int status = 0; ++ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; ++ u16 driverVersion; ++ ++ dprintk(1, "\n"); ++ if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { ++ status = PowerUpDevice(state); ++ if (status < 0) ++ goto error; ++ status = DRXX_Open(state); ++ if (status < 0) ++ goto error; ++ /* Soft reset of OFDM-, sys- and osc-clockdomain */ ++ status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M); ++ if (status < 0) ++ goto error; ++ status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); ++ if (status < 0) ++ goto error; ++ /* TODO is this needed, if yes how much delay in worst case scenario */ ++ msleep(1); ++ state->m_DRXK_A3_PATCH_CODE = true; ++ status = GetDeviceCapabilities(state); ++ if (status < 0) ++ goto error; ++ ++ /* Bridge delay, uses oscilator clock */ ++ /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ ++ /* SDA brdige delay */ ++ state->m_HICfgBridgeDelay = ++ (u16) ((state->m_oscClockFreq / 1000) * ++ HI_I2C_BRIDGE_DELAY) / 1000; ++ /* Clipping */ ++ if (state->m_HICfgBridgeDelay > ++ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { ++ state->m_HICfgBridgeDelay = ++ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; ++ } ++ /* SCL bridge delay, same as SDA for now */ ++ state->m_HICfgBridgeDelay += ++ state->m_HICfgBridgeDelay << ++ SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; ++ ++ status = InitHI(state); ++ if (status < 0) ++ goto error; ++ /* disable various processes */ ++#if NOA1ROM ++ if (!(state->m_DRXK_A1_ROM_CODE) ++ && !(state->m_DRXK_A2_ROM_CODE)) ++#endif ++ { ++ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); ++ if (status < 0) ++ goto error; ++ } ++ ++ /* disable MPEG port */ ++ status = MPEGTSDisable(state); ++ if (status < 0) ++ goto error; ++ ++ /* Stop AUD and SCU */ ++ status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ ++ /* enable token-ring bus through OFDM block for possible ucode upload */ ++ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON); ++ if (status < 0) ++ goto error; ++ ++ /* include boot loader section */ ++ status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ status = BLChainCmd(state, 0, 6, 100); ++ if (status < 0) ++ goto error; ++ ++ if (state->microcode_name) ++ load_microcode(state, state->microcode_name); ++ ++ /* disable token-ring bus through OFDM block for possible ucode upload */ ++ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); ++ if (status < 0) ++ goto error; ++ ++ /* Run SCU for a little while to initialize microcode version numbers */ ++ status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); ++ if (status < 0) ++ goto error; ++ status = DRXX_Open(state); ++ if (status < 0) ++ goto error; ++ /* added for test */ ++ msleep(30); ++ ++ powerMode = DRXK_POWER_DOWN_OFDM; ++ status = CtrlPowerMode(state, &powerMode); ++ if (status < 0) ++ goto error; ++ ++ /* Stamp driver version number in SCU data RAM in BCD code ++ Done to enable field application engineers to retreive drxdriver version ++ via I2C from SCU RAM. ++ Not using SCU command interface for SCU register access since no ++ microcode may be present. ++ */ ++ driverVersion = ++ (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + ++ (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + ++ ((DRXK_VERSION_MAJOR % 10) << 4) + ++ (DRXK_VERSION_MINOR % 10); ++ status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion); ++ if (status < 0) ++ goto error; ++ driverVersion = ++ (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + ++ (((DRXK_VERSION_PATCH / 100) % 10) << 8) + ++ (((DRXK_VERSION_PATCH / 10) % 10) << 4) + ++ (DRXK_VERSION_PATCH % 10); ++ status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion); ++ if (status < 0) ++ goto error; ++ ++ printk(KERN_INFO "DRXK driver version %d.%d.%d\n", ++ DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, ++ DRXK_VERSION_PATCH); ++ ++ /* Dirty fix of default values for ROM/PATCH microcode ++ Dirty because this fix makes it impossible to setup suitable values ++ before calling DRX_Open. This solution requires changes to RF AGC speed ++ to be done via the CTRL function after calling DRX_Open */ ++ ++ /* m_dvbtRfAgcCfg.speed = 3; */ ++ ++ /* Reset driver debug flags to 0 */ ++ status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); ++ if (status < 0) ++ goto error; ++ /* driver 0.9.0 */ ++ /* Setup FEC OC: ++ NOTE: No more full FEC resets allowed afterwards!! */ ++ status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); ++ if (status < 0) ++ goto error; ++ /* MPEGTS functions are still the same */ ++ status = MPEGTSDtoInit(state); ++ if (status < 0) ++ goto error; ++ status = MPEGTSStop(state); ++ if (status < 0) ++ goto error; ++ status = MPEGTSConfigurePolarity(state); ++ if (status < 0) ++ goto error; ++ status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput); ++ if (status < 0) ++ goto error; ++ /* added: configure GPIO */ ++ status = WriteGPIO(state); ++ if (status < 0) ++ goto error; ++ ++ state->m_DrxkState = DRXK_STOPPED; ++ ++ if (state->m_bPowerDown) { ++ status = PowerDownDevice(state); ++ if (status < 0) ++ goto error; ++ state->m_DrxkState = DRXK_POWERED_DOWN; ++ } else ++ state->m_DrxkState = DRXK_STOPPED; ++ } ++error: ++ if (status < 0) ++ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); ++ ++ return status; ++} ++ ++static void drxk_release(struct dvb_frontend *fe) ++{ ++ struct drxk_state *state = fe->demodulator_priv; ++ ++ dprintk(1, "\n"); ++ kfree(state); ++} ++ ++static int drxk_sleep(struct dvb_frontend *fe) ++{ ++ struct drxk_state *state = fe->demodulator_priv; ++ ++ dprintk(1, "\n"); ++ ShutDown(state); ++ return 0; ++} ++ ++static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) ++{ ++ struct drxk_state *state = fe->demodulator_priv; ++ ++ dprintk(1, "%s\n", enable ? "enable" : "disable"); ++ return ConfigureI2CBridge(state, enable ? true : false); ++} ++ ++static int drxk_set_parameters(struct dvb_frontend *fe) ++{ ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ u32 delsys = p->delivery_system, old_delsys; ++ struct drxk_state *state = fe->demodulator_priv; ++ u32 IF; ++ ++ dprintk(1, "\n"); ++ ++ if (!fe->ops.tuner_ops.get_if_frequency) { ++ printk(KERN_ERR ++ "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); ++ return -EINVAL; ++ } ++ ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ if (fe->ops.tuner_ops.set_params) ++ fe->ops.tuner_ops.set_params(fe); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ ++ old_delsys = state->props.delivery_system; ++ state->props = *p; ++ ++ if (old_delsys != delsys) { ++ ShutDown(state); ++ switch (delsys) { ++ case SYS_DVBC_ANNEX_A: ++ case SYS_DVBC_ANNEX_C: ++ if (!state->m_hasDVBC) ++ return -EINVAL; ++ state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; ++ if (state->m_itut_annex_c) ++ SetOperationMode(state, OM_QAM_ITU_C); ++ else ++ SetOperationMode(state, OM_QAM_ITU_A); ++ break; ++ case SYS_DVBT: ++ if (!state->m_hasDVBT) ++ return -EINVAL; ++ SetOperationMode(state, OM_DVBT); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ fe->ops.tuner_ops.get_if_frequency(fe, &IF); ++ Start(state, 0, IF); ++ ++ /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ ++ ++ return 0; ++} ++ ++static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) ++{ ++ struct drxk_state *state = fe->demodulator_priv; ++ u32 stat; ++ ++ dprintk(1, "\n"); ++ *status = 0; ++ GetLockStatus(state, &stat, 0); ++ if (stat == MPEG_LOCK) ++ *status |= 0x1f; ++ if (stat == FEC_LOCK) ++ *status |= 0x0f; ++ if (stat == DEMOD_LOCK) ++ *status |= 0x07; ++ return 0; ++} ++ ++static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) ++{ ++ dprintk(1, "\n"); ++ ++ *ber = 0; ++ return 0; ++} ++ ++static int drxk_read_signal_strength(struct dvb_frontend *fe, ++ u16 *strength) ++{ ++ struct drxk_state *state = fe->demodulator_priv; ++ u32 val = 0; ++ ++ dprintk(1, "\n"); ++ ReadIFAgc(state, &val); ++ *strength = val & 0xffff; ++ return 0; ++} ++ ++static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) ++{ ++ struct drxk_state *state = fe->demodulator_priv; ++ s32 snr2; ++ ++ dprintk(1, "\n"); ++ GetSignalToNoise(state, &snr2); ++ *snr = snr2 & 0xffff; ++ return 0; ++} ++ ++static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) ++{ ++ struct drxk_state *state = fe->demodulator_priv; ++ u16 err; ++ ++ dprintk(1, "\n"); ++ DVBTQAMGetAccPktErr(state, &err); ++ *ucblocks = (u32) err; ++ return 0; ++} ++ ++static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings ++ *sets) ++{ ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ ++ dprintk(1, "\n"); ++ switch (p->delivery_system) { ++ case SYS_DVBC_ANNEX_A: ++ case SYS_DVBC_ANNEX_C: ++ case SYS_DVBT: ++ sets->min_delay_ms = 3000; ++ sets->max_drift = 0; ++ sets->step_size = 0; ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static struct dvb_frontend_ops drxk_ops = { ++ /* .delsys will be filled dynamically */ ++ .info = { ++ .name = "DRXK", ++ .frequency_min = 47000000, ++ .frequency_max = 865000000, ++ /* For DVB-C */ ++ .symbol_rate_min = 870000, ++ .symbol_rate_max = 11700000, ++ /* For DVB-T */ ++ .frequency_stepsize = 166667, ++ ++ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | ++ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | ++ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | ++ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS | ++ FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | ++ FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO ++ }, ++ ++ .release = drxk_release, ++ .sleep = drxk_sleep, ++ .i2c_gate_ctrl = drxk_gate_ctrl, ++ ++ .set_frontend = drxk_set_parameters, ++ .get_tune_settings = drxk_get_tune_settings, ++ ++ .read_status = drxk_read_status, ++ .read_ber = drxk_read_ber, ++ .read_signal_strength = drxk_read_signal_strength, ++ .read_snr = drxk_read_snr, ++ .read_ucblocks = drxk_read_ucblocks, ++}; ++ ++struct dvb_frontend *drxk_attach(const struct drxk_config *config, ++ struct i2c_adapter *i2c) ++{ ++ int n; ++ ++ struct drxk_state *state = NULL; ++ u8 adr = config->adr; ++ ++ dprintk(1, "\n"); ++ state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ ++ state->i2c = i2c; ++ state->demod_address = adr; ++ state->single_master = config->single_master; ++ state->microcode_name = config->microcode_name; ++ state->no_i2c_bridge = config->no_i2c_bridge; ++ state->antenna_gpio = config->antenna_gpio; ++ state->antenna_dvbt = config->antenna_dvbt; ++ state->m_ChunkSize = config->chunk_size; ++ state->enable_merr_cfg = config->enable_merr_cfg; ++ ++ if (config->dynamic_clk) { ++ state->m_DVBTStaticCLK = 0; ++ state->m_DVBCStaticCLK = 0; ++ } else { ++ state->m_DVBTStaticCLK = 1; ++ state->m_DVBCStaticCLK = 1; ++ } ++ ++ ++ if (config->mpeg_out_clk_strength) ++ state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07; ++ else ++ state->m_TSClockkStrength = 0x06; ++ ++ if (config->parallel_ts) ++ state->m_enableParallel = true; ++ else ++ state->m_enableParallel = false; ++ ++ /* NOTE: as more UIO bits will be used, add them to the mask */ ++ state->UIO_mask = config->antenna_gpio; ++ ++ /* Default gpio to DVB-C */ ++ if (!state->antenna_dvbt && state->antenna_gpio) ++ state->m_GPIO |= state->antenna_gpio; ++ else ++ state->m_GPIO &= ~state->antenna_gpio; ++ ++ mutex_init(&state->mutex); ++ ++ memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); ++ state->frontend.demodulator_priv = state; ++ ++ init_state(state); ++ if (init_drxk(state) < 0) ++ goto error; ++ ++ /* Initialize the supported delivery systems */ ++ n = 0; ++ if (state->m_hasDVBC) { ++ state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; ++ state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; ++ strlcat(state->frontend.ops.info.name, " DVB-C", ++ sizeof(state->frontend.ops.info.name)); ++ } ++ if (state->m_hasDVBT) { ++ state->frontend.ops.delsys[n++] = SYS_DVBT; ++ strlcat(state->frontend.ops.info.name, " DVB-T", ++ sizeof(state->frontend.ops.info.name)); ++ } ++ ++ printk(KERN_INFO "drxk: frontend initialized.\n"); ++ return &state->frontend; ++ ++error: ++ printk(KERN_ERR "drxk: not found\n"); ++ kfree(state); ++ return NULL; ++} ++EXPORT_SYMBOL(drxk_attach); ++ ++MODULE_DESCRIPTION("DRX-K driver"); ++MODULE_AUTHOR("Ralph Metzler"); ++MODULE_LICENSE("GPL"); +diff --git a/frontends/drxk_hard.h b/frontends/drxk_hard.h +index 78e8e7a..4bbf841 100644 +--- a/frontends/drxk_hard.h ++++ b/frontends/drxk_hard.h +@@ -1,343 +1,349 @@ +-#include "drxk_map.h" +- +-#define DRXK_VERSION_MAJOR 0 +-#define DRXK_VERSION_MINOR 9 +-#define DRXK_VERSION_PATCH 4300 +- +-#define HI_I2C_DELAY 42 +-#define HI_I2C_BRIDGE_DELAY 350 +-#define DRXK_MAX_RETRIES 100 +- +-#define DRIVER_4400 1 +- +-#define DRXX_JTAGID 0x039210D9 +-#define DRXX_J_JTAGID 0x239310D9 +-#define DRXX_K_JTAGID 0x039210D9 +- +-#define DRX_UNKNOWN 254 +-#define DRX_AUTO 255 +- +-#define DRX_SCU_READY 0 +-#define DRXK_MAX_WAITTIME (200) +-#define SCU_RESULT_OK 0 +-#define SCU_RESULT_UNKSTD -2 +-#define SCU_RESULT_UNKCMD -1 +- +-#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT +-#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) +-#endif +- +-#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ +-#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ +-#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ +-#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ +-#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ +-#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ +-#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ +-#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ +- +-#define IQM_CF_OUT_ENA_OFDM__M 0x4 +-#define IQM_FS_ADJ_SEL_B_QAM 0x1 +-#define IQM_FS_ADJ_SEL_B_OFF 0x0 +-#define IQM_FS_ADJ_SEL_B_VSB 0x2 +-#define IQM_RC_ADJ_SEL_B_OFF 0x0 +-#define IQM_RC_ADJ_SEL_B_QAM 0x1 +-#define IQM_RC_ADJ_SEL_B_VSB 0x2 +- +-enum OperationMode { +- OM_NONE, +- OM_QAM_ITU_A, +- OM_QAM_ITU_B, +- OM_QAM_ITU_C, +- OM_DVBT +-}; +- +-typedef enum { +- DRX_POWER_UP = 0, +- DRX_POWER_MODE_1, +- DRX_POWER_MODE_2, +- DRX_POWER_MODE_3, +- DRX_POWER_MODE_4, +- DRX_POWER_MODE_5, +- DRX_POWER_MODE_6, +- DRX_POWER_MODE_7, +- DRX_POWER_MODE_8, +- +- DRX_POWER_MODE_9, +- DRX_POWER_MODE_10, +- DRX_POWER_MODE_11, +- DRX_POWER_MODE_12, +- DRX_POWER_MODE_13, +- DRX_POWER_MODE_14, +- DRX_POWER_MODE_15, +- DRX_POWER_MODE_16, +- DRX_POWER_DOWN = 255 +-}DRXPowerMode_t, *pDRXPowerMode_t; +- +- +-/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ +-#ifndef DRXK_POWER_DOWN_OFDM +-#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 +-#endif +- +-/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ +-#ifndef DRXK_POWER_DOWN_CORE +-#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 +-#endif +- +-/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ +-#ifndef DRXK_POWER_DOWN_PLL +-#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 +-#endif +- +- +-enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; +-enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; +-enum EDrxkCoefArrayIndex { +- DRXK_COEF_IDX_MN = 0, +- DRXK_COEF_IDX_FM , +- DRXK_COEF_IDX_L , +- DRXK_COEF_IDX_LP , +- DRXK_COEF_IDX_BG , +- DRXK_COEF_IDX_DK , +- DRXK_COEF_IDX_I , +- DRXK_COEF_IDX_MAX +-}; +-enum EDrxkSifAttenuation { +- DRXK_SIF_ATTENUATION_0DB, +- DRXK_SIF_ATTENUATION_3DB, +- DRXK_SIF_ATTENUATION_6DB, +- DRXK_SIF_ATTENUATION_9DB +-}; +-enum EDrxkConstellation { +- DRX_CONSTELLATION_BPSK = 0, +- DRX_CONSTELLATION_QPSK, +- DRX_CONSTELLATION_PSK8, +- DRX_CONSTELLATION_QAM16, +- DRX_CONSTELLATION_QAM32, +- DRX_CONSTELLATION_QAM64, +- DRX_CONSTELLATION_QAM128, +- DRX_CONSTELLATION_QAM256, +- DRX_CONSTELLATION_QAM512, +- DRX_CONSTELLATION_QAM1024, +- DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, +- DRX_CONSTELLATION_AUTO = DRX_AUTO +-}; +-enum EDrxkInterleaveMode { +- DRXK_QAM_I12_J17 = 16, +- DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN +-}; +-enum { +- DRXK_SPIN_A1 = 0, +- DRXK_SPIN_A2, +- DRXK_SPIN_A3, +- DRXK_SPIN_UNKNOWN +-}; +- +-enum DRXKCfgDvbtSqiSpeed { +- DRXK_DVBT_SQI_SPEED_FAST = 0, +- DRXK_DVBT_SQI_SPEED_MEDIUM, +- DRXK_DVBT_SQI_SPEED_SLOW, +- DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +-} ; +- +-enum DRXFftmode_t { +- DRX_FFTMODE_2K = 0, +- DRX_FFTMODE_4K, +- DRX_FFTMODE_8K, +- DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, +- DRX_FFTMODE_AUTO = DRX_AUTO +-}; +- +-enum DRXMPEGStrWidth_t { +- DRX_MPEG_STR_WIDTH_1, +- DRX_MPEG_STR_WIDTH_8 +-}; +- +-enum DRXQamLockRange_t { +- DRX_QAM_LOCKRANGE_NORMAL, +- DRX_QAM_LOCKRANGE_EXTENDED +-}; +- +-struct DRXKCfgDvbtEchoThres_t { +- u16 threshold; +- enum DRXFftmode_t fftMode; +-} ; +- +-struct SCfgAgc +-{ +- enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ +- u16 outputLevel; /* range dependent on AGC */ +- u16 minOutputLevel; /* range dependent on AGC */ +- u16 maxOutputLevel; /* range dependent on AGC */ +- u16 speed; /* range dependent on AGC */ +- u16 top; /* rf-agc take over point */ +- u16 cutOffCurrent; /* rf-agc is accelerated if output current +- is below cut-off current */ +- u16 IngainTgtMax; +- u16 FastClipCtrlDelay; +-}; +- +-struct SCfgPreSaw +-{ +- u16 reference; /* pre SAW reference value, range 0 .. 31 */ +- bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ +-}; +- +-struct DRXKOfdmScCmd_t +-{ +- u16 cmd; /**< Command number */ +- u16 subcmd; /**< Sub-command parameter*/ +- u16 param0; /**< General purpous param */ +- u16 param1; /**< General purpous param */ +- u16 param2; /**< General purpous param */ +- u16 param3; /**< General purpous param */ +- u16 param4; /**< General purpous param */ +-}; +- +-struct drxk_state { +- struct dvb_frontend c_frontend; +- struct dvb_frontend t_frontend; +-#ifndef USE_API3 +- struct dtv_frontend_properties props; +-#else +- struct dvb_frontend_parameters param; +-#endif +- struct device *dev; +- +- struct i2c_adapter *i2c; +- u8 demod_address; +- void *priv; +- +- struct mutex mutex; +- struct mutex ctlock; +- +- u32 m_Instance; ///< Channel 1,2,3 or 4 +- +- int m_ChunkSize; +- u8 Chunk[256]; +- +- bool m_hasLNA; +- bool m_hasDVBT; +- bool m_hasDVBC; +- bool m_hasAudio; +- bool m_hasATV; +- bool m_hasOOB; +- bool m_hasSAWSW; /**< TRUE if mat_tx is available */ +- bool m_hasGPIO1; /**< TRUE if mat_rx is available */ +- bool m_hasGPIO2; /**< TRUE if GPIO is available */ +- bool m_hasIRQN; /**< TRUE if IRQN is available */ +- u16 m_oscClockFreq; +- u16 m_HICfgTimingDiv; +- u16 m_HICfgBridgeDelay; +- u16 m_HICfgWakeUpKey; +- u16 m_HICfgTimeout; +- u16 m_HICfgCtrl; +- s32 m_sysClockFreq ; ///< system clock frequency in kHz +- +- enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started) +- enum OperationMode m_OperationMode; ///< digital standards +- struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC +- struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC +- u16 m_vsbPgaCfg; ///< settings for VSB PGA +- struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense +- s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication +- s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication +- bool m_smartAntInverted; +- bool m_bDebugEnableBridge; +- bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed +- bool m_bPowerDown; ///< Power down when not used +- +- u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint) +- +- bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ +- bool m_insertRSByte; /**< If TRUE, insert RS byte */ +- bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ +- bool m_invertDATA; /**< If TRUE, invert DATA signals */ +- bool m_invertERR; /**< If TRUE, invert ERR signal */ +- bool m_invertSTR; /**< If TRUE, invert STR signals */ +- bool m_invertVAL; /**< If TRUE, invert VAL signals */ +- bool m_invertCLK; /**< If TRUE, invert CLK signals */ +- bool m_DVBCStaticCLK; +- bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will +- be used, otherwise clockrate will +- adapt to the bitrate of the TS */ +- u32 m_DVBTBitrate; +- u32 m_DVBCBitrate; +- +- u8 m_TSDataStrength; +- u8 m_TSClockkStrength; +- +- enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/ +- u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case +- static clockrate is selected */ +- +- //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start +- s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) +- s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) +- +- bool m_disableTEIhandling; +- +- bool m_RfAgcPol; +- bool m_IfAgcPol; +- +- struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC +- struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC +- struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense +- bool m_phaseCorrectionBypass; +- s16 m_atvTopVidPeak; +- u16 m_atvTopNoiseTh; +- enum EDrxkSifAttenuation m_sifAttenuation; +- bool m_enableCVBSOutput; +- bool m_enableSIFOutput; +- bool m_bMirrorFreqSpect; +- enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel +- u32 m_CurrSymbolRate; ///< Current QAM symbol rate +- struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC +- struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC +- u16 m_qamPgaCfg; ///< settings for QAM PGA +- struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense +- enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode +- u16 m_fecRsPlen; +- u16 m_fecRsPrescale; +- +- enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; +- +- u16 m_GPIO; +- u16 m_GPIOCfg; +- +- struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC +- struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC +- struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense +- +- u16 m_agcFastClipCtrlDelay; +- bool m_adcCompPassed; +- u16 m_adcCompCoef[64]; +- u16 m_adcState; +- +- u8 *m_microcode; +- int m_microcode_length; +- bool m_DRXK_A1_PATCH_CODE; +- bool m_DRXK_A1_ROM_CODE; +- bool m_DRXK_A2_ROM_CODE; +- bool m_DRXK_A3_ROM_CODE; +- bool m_DRXK_A2_PATCH_CODE; +- bool m_DRXK_A3_PATCH_CODE; +- +- bool m_rfmirror; +- u8 m_deviceSpin; +- u32 m_iqmRcRate; +- +- u16 m_AntennaDVBC; +- u16 m_AntennaDVBT; +- u16 m_AntennaSwitchDVBTDVBC; +- +- DRXPowerMode_t m_currentPowerMode; +-}; +- +-#define NEVER_LOCK 0 +-#define NOT_LOCKED 1 +-#define DEMOD_LOCK 2 +-#define FEC_LOCK 3 +-#define MPEG_LOCK 4 +- ++#include "drxk_map.h" ++ ++#define DRXK_VERSION_MAJOR 0 ++#define DRXK_VERSION_MINOR 9 ++#define DRXK_VERSION_PATCH 4300 ++ ++#define HI_I2C_DELAY 42 ++#define HI_I2C_BRIDGE_DELAY 350 ++#define DRXK_MAX_RETRIES 100 ++ ++#define DRIVER_4400 1 ++ ++#define DRXX_JTAGID 0x039210D9 ++#define DRXX_J_JTAGID 0x239310D9 ++#define DRXX_K_JTAGID 0x039210D9 ++ ++#define DRX_UNKNOWN 254 ++#define DRX_AUTO 255 ++ ++#define DRX_SCU_READY 0 ++#define DRXK_MAX_WAITTIME (200) ++#define SCU_RESULT_OK 0 ++#define SCU_RESULT_SIZE -4 ++#define SCU_RESULT_INVPAR -3 ++#define SCU_RESULT_UNKSTD -2 ++#define SCU_RESULT_UNKCMD -1 ++ ++#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT ++#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) ++#endif ++ ++#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ ++#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ ++#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ ++#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ ++#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ ++#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ ++#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ ++#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ ++ ++#define IQM_CF_OUT_ENA_OFDM__M 0x4 ++#define IQM_FS_ADJ_SEL_B_QAM 0x1 ++#define IQM_FS_ADJ_SEL_B_OFF 0x0 ++#define IQM_FS_ADJ_SEL_B_VSB 0x2 ++#define IQM_RC_ADJ_SEL_B_OFF 0x0 ++#define IQM_RC_ADJ_SEL_B_QAM 0x1 ++#define IQM_RC_ADJ_SEL_B_VSB 0x2 ++ ++enum OperationMode { ++ OM_NONE, ++ OM_QAM_ITU_A, ++ OM_QAM_ITU_B, ++ OM_QAM_ITU_C, ++ OM_DVBT ++}; ++ ++enum DRXPowerMode { ++ DRX_POWER_UP = 0, ++ DRX_POWER_MODE_1, ++ DRX_POWER_MODE_2, ++ DRX_POWER_MODE_3, ++ DRX_POWER_MODE_4, ++ DRX_POWER_MODE_5, ++ DRX_POWER_MODE_6, ++ DRX_POWER_MODE_7, ++ DRX_POWER_MODE_8, ++ ++ DRX_POWER_MODE_9, ++ DRX_POWER_MODE_10, ++ DRX_POWER_MODE_11, ++ DRX_POWER_MODE_12, ++ DRX_POWER_MODE_13, ++ DRX_POWER_MODE_14, ++ DRX_POWER_MODE_15, ++ DRX_POWER_MODE_16, ++ DRX_POWER_DOWN = 255 ++}; ++ ++ ++/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ ++#ifndef DRXK_POWER_DOWN_OFDM ++#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 ++#endif ++ ++/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ ++#ifndef DRXK_POWER_DOWN_CORE ++#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 ++#endif ++ ++/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ ++#ifndef DRXK_POWER_DOWN_PLL ++#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 ++#endif ++ ++ ++enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; ++enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; ++enum EDrxkCoefArrayIndex { ++ DRXK_COEF_IDX_MN = 0, ++ DRXK_COEF_IDX_FM , ++ DRXK_COEF_IDX_L , ++ DRXK_COEF_IDX_LP , ++ DRXK_COEF_IDX_BG , ++ DRXK_COEF_IDX_DK , ++ DRXK_COEF_IDX_I , ++ DRXK_COEF_IDX_MAX ++}; ++enum EDrxkSifAttenuation { ++ DRXK_SIF_ATTENUATION_0DB, ++ DRXK_SIF_ATTENUATION_3DB, ++ DRXK_SIF_ATTENUATION_6DB, ++ DRXK_SIF_ATTENUATION_9DB ++}; ++enum EDrxkConstellation { ++ DRX_CONSTELLATION_BPSK = 0, ++ DRX_CONSTELLATION_QPSK, ++ DRX_CONSTELLATION_PSK8, ++ DRX_CONSTELLATION_QAM16, ++ DRX_CONSTELLATION_QAM32, ++ DRX_CONSTELLATION_QAM64, ++ DRX_CONSTELLATION_QAM128, ++ DRX_CONSTELLATION_QAM256, ++ DRX_CONSTELLATION_QAM512, ++ DRX_CONSTELLATION_QAM1024, ++ DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, ++ DRX_CONSTELLATION_AUTO = DRX_AUTO ++}; ++enum EDrxkInterleaveMode { ++ DRXK_QAM_I12_J17 = 16, ++ DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN ++}; ++enum { ++ DRXK_SPIN_A1 = 0, ++ DRXK_SPIN_A2, ++ DRXK_SPIN_A3, ++ DRXK_SPIN_UNKNOWN ++}; ++ ++enum DRXKCfgDvbtSqiSpeed { ++ DRXK_DVBT_SQI_SPEED_FAST = 0, ++ DRXK_DVBT_SQI_SPEED_MEDIUM, ++ DRXK_DVBT_SQI_SPEED_SLOW, ++ DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN ++} ; ++ ++enum DRXFftmode_t { ++ DRX_FFTMODE_2K = 0, ++ DRX_FFTMODE_4K, ++ DRX_FFTMODE_8K, ++ DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, ++ DRX_FFTMODE_AUTO = DRX_AUTO ++}; ++ ++enum DRXMPEGStrWidth_t { ++ DRX_MPEG_STR_WIDTH_1, ++ DRX_MPEG_STR_WIDTH_8 ++}; ++ ++enum DRXQamLockRange_t { ++ DRX_QAM_LOCKRANGE_NORMAL, ++ DRX_QAM_LOCKRANGE_EXTENDED ++}; ++ ++struct DRXKCfgDvbtEchoThres_t { ++ u16 threshold; ++ enum DRXFftmode_t fftMode; ++} ; ++ ++struct SCfgAgc { ++ enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ ++ u16 outputLevel; /* range dependent on AGC */ ++ u16 minOutputLevel; /* range dependent on AGC */ ++ u16 maxOutputLevel; /* range dependent on AGC */ ++ u16 speed; /* range dependent on AGC */ ++ u16 top; /* rf-agc take over point */ ++ u16 cutOffCurrent; /* rf-agc is accelerated if output current ++ is below cut-off current */ ++ u16 IngainTgtMax; ++ u16 FastClipCtrlDelay; ++}; ++ ++struct SCfgPreSaw { ++ u16 reference; /* pre SAW reference value, range 0 .. 31 */ ++ bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ ++}; ++ ++struct DRXKOfdmScCmd_t { ++ u16 cmd; /**< Command number */ ++ u16 subcmd; /**< Sub-command parameter*/ ++ u16 param0; /**< General purpous param */ ++ u16 param1; /**< General purpous param */ ++ u16 param2; /**< General purpous param */ ++ u16 param3; /**< General purpous param */ ++ u16 param4; /**< General purpous param */ ++}; ++ ++struct drxk_state { ++ struct dvb_frontend frontend; ++ struct dtv_frontend_properties props; ++ struct device *dev; ++ ++ struct i2c_adapter *i2c; ++ u8 demod_address; ++ void *priv; ++ ++ struct mutex mutex; ++ ++ u32 m_Instance; /**< Channel 1,2,3 or 4 */ ++ ++ int m_ChunkSize; ++ u8 Chunk[256]; ++ ++ bool m_hasLNA; ++ bool m_hasDVBT; ++ bool m_hasDVBC; ++ bool m_hasAudio; ++ bool m_hasATV; ++ bool m_hasOOB; ++ bool m_hasSAWSW; /**< TRUE if mat_tx is available */ ++ bool m_hasGPIO1; /**< TRUE if mat_rx is available */ ++ bool m_hasGPIO2; /**< TRUE if GPIO is available */ ++ bool m_hasIRQN; /**< TRUE if IRQN is available */ ++ u16 m_oscClockFreq; ++ u16 m_HICfgTimingDiv; ++ u16 m_HICfgBridgeDelay; ++ u16 m_HICfgWakeUpKey; ++ u16 m_HICfgTimeout; ++ u16 m_HICfgCtrl; ++ s32 m_sysClockFreq; /**< system clock frequency in kHz */ ++ ++ enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */ ++ enum OperationMode m_OperationMode; /**< digital standards */ ++ struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */ ++ struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */ ++ u16 m_vsbPgaCfg; /**< settings for VSB PGA */ ++ struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */ ++ s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */ ++ s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */ ++ bool m_smartAntInverted; ++ bool m_bDebugEnableBridge; ++ bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */ ++ bool m_bPowerDown; /**< Power down when not used */ ++ ++ u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */ ++ ++ bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ ++ bool m_insertRSByte; /**< If TRUE, insert RS byte */ ++ bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ ++ bool m_invertDATA; /**< If TRUE, invert DATA signals */ ++ bool m_invertERR; /**< If TRUE, invert ERR signal */ ++ bool m_invertSTR; /**< If TRUE, invert STR signals */ ++ bool m_invertVAL; /**< If TRUE, invert VAL signals */ ++ bool m_invertCLK; /**< If TRUE, invert CLK signals */ ++ bool m_DVBCStaticCLK; ++ bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will ++ be used, otherwise clockrate will ++ adapt to the bitrate of the TS */ ++ u32 m_DVBTBitrate; ++ u32 m_DVBCBitrate; ++ ++ u8 m_TSDataStrength; ++ u8 m_TSClockkStrength; ++ ++ bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */ ++ ++ enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */ ++ u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case ++ static clockrate is selected */ ++ ++ /* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */ ++ s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ ++ s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ ++ ++ bool m_disableTEIhandling; ++ ++ bool m_RfAgcPol; ++ bool m_IfAgcPol; ++ ++ struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */ ++ struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */ ++ struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */ ++ bool m_phaseCorrectionBypass; ++ s16 m_atvTopVidPeak; ++ u16 m_atvTopNoiseTh; ++ enum EDrxkSifAttenuation m_sifAttenuation; ++ bool m_enableCVBSOutput; ++ bool m_enableSIFOutput; ++ bool m_bMirrorFreqSpect; ++ enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */ ++ u32 m_CurrSymbolRate; /**< Current QAM symbol rate */ ++ struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */ ++ struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */ ++ u16 m_qamPgaCfg; /**< settings for QAM PGA */ ++ struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */ ++ enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */ ++ u16 m_fecRsPlen; ++ u16 m_fecRsPrescale; ++ ++ enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; ++ ++ u16 m_GPIO; ++ u16 m_GPIOCfg; ++ ++ struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */ ++ struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */ ++ struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */ ++ ++ u16 m_agcFastClipCtrlDelay; ++ bool m_adcCompPassed; ++ u16 m_adcCompCoef[64]; ++ u16 m_adcState; ++ ++ u8 *m_microcode; ++ int m_microcode_length; ++ bool m_DRXK_A1_PATCH_CODE; ++ bool m_DRXK_A1_ROM_CODE; ++ bool m_DRXK_A2_ROM_CODE; ++ bool m_DRXK_A3_ROM_CODE; ++ bool m_DRXK_A2_PATCH_CODE; ++ bool m_DRXK_A3_PATCH_CODE; ++ ++ bool m_rfmirror; ++ u8 m_deviceSpin; ++ u32 m_iqmRcRate; ++ ++ enum DRXPowerMode m_currentPowerMode; ++ ++ /* ++ * Configurable parameters at the driver. They stores the values found ++ * at struct drxk_config. ++ */ ++ ++ u16 UIO_mask; /* Bits used by UIO */ ++ ++ bool enable_merr_cfg; ++ bool single_master; ++ bool no_i2c_bridge; ++ bool antenna_dvbt; ++ u16 antenna_gpio; ++ ++ const char *microcode_name; ++}; ++ ++#define NEVER_LOCK 0 ++#define NOT_LOCKED 1 ++#define DEMOD_LOCK 2 ++#define FEC_LOCK 3 ++#define MPEG_LOCK 4 ++ +diff --git a/frontends/drxk_map.h b/frontends/drxk_map.h +index 02895aa..23e16c1 100644 +--- a/frontends/drxk_map.h ++++ b/frontends/drxk_map.h +@@ -1,16438 +1,451 @@ +-#ifndef __DRXK_MAP__H__ +-#define __DRXK_MAP__H__ 1 +- +-#define AUD_COMM_EXEC__A 0x1000000 +-#define AUD_COMM_EXEC__W 2 +-#define AUD_COMM_EXEC__M 0x3 +-#define AUD_COMM_EXEC__PRE 0x0 +-#define AUD_COMM_EXEC_STOP 0x0 +- +-#define FEC_COMM_EXEC__A 0x1C00000 +-#define FEC_COMM_EXEC__W 2 +-#define FEC_COMM_EXEC__M 0x3 +-#define FEC_COMM_EXEC__PRE 0x0 +-#define FEC_COMM_EXEC_STOP 0x0 +-#define FEC_COMM_EXEC_ACTIVE 0x1 +-#define FEC_COMM_EXEC_HOLD 0x2 +- +-#define FEC_COMM_MB__A 0x1C00002 +-#define FEC_COMM_MB__W 16 +-#define FEC_COMM_MB__M 0xFFFF +-#define FEC_COMM_MB__PRE 0x0 +-#define FEC_COMM_INT_REQ__A 0x1C00003 +-#define FEC_COMM_INT_REQ__W 16 +-#define FEC_COMM_INT_REQ__M 0xFFFF +-#define FEC_COMM_INT_REQ__PRE 0x0 +-#define FEC_COMM_INT_REQ_OC_REQ__B 0 +-#define FEC_COMM_INT_REQ_OC_REQ__W 1 +-#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +-#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +-#define FEC_COMM_INT_REQ_RS_REQ__B 1 +-#define FEC_COMM_INT_REQ_RS_REQ__W 1 +-#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +-#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +-#define FEC_COMM_INT_REQ_DI_REQ__B 2 +-#define FEC_COMM_INT_REQ_DI_REQ__W 1 +-#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +-#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 +- +-#define FEC_COMM_INT_STA__A 0x1C00005 +-#define FEC_COMM_INT_STA__W 16 +-#define FEC_COMM_INT_STA__M 0xFFFF +-#define FEC_COMM_INT_STA__PRE 0x0 +-#define FEC_COMM_INT_MSK__A 0x1C00006 +-#define FEC_COMM_INT_MSK__W 16 +-#define FEC_COMM_INT_MSK__M 0xFFFF +-#define FEC_COMM_INT_MSK__PRE 0x0 +-#define FEC_COMM_INT_STM__A 0x1C00007 +-#define FEC_COMM_INT_STM__W 16 +-#define FEC_COMM_INT_STM__M 0xFFFF +-#define FEC_COMM_INT_STM__PRE 0x0 +- +- +- +-#define FEC_TOP_COMM_EXEC__A 0x1C10000 +-#define FEC_TOP_COMM_EXEC__W 2 +-#define FEC_TOP_COMM_EXEC__M 0x3 +-#define FEC_TOP_COMM_EXEC__PRE 0x0 +-#define FEC_TOP_COMM_EXEC_STOP 0x0 +-#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +-#define FEC_TOP_COMM_EXEC_HOLD 0x2 +- +-#define FEC_TOP_ANNEX__A 0x1C10010 +-#define FEC_TOP_ANNEX__W 2 +-#define FEC_TOP_ANNEX__M 0x3 +-#define FEC_TOP_ANNEX__PRE 0x0 +-#define FEC_TOP_ANNEX_A 0x0 +-#define FEC_TOP_ANNEX_B 0x1 +-#define FEC_TOP_ANNEX_C 0x2 +-#define FEC_TOP_ANNEX_D 0x3 +- +- +- +-#define FEC_DI_COMM_EXEC__A 0x1C20000 +-#define FEC_DI_COMM_EXEC__W 2 +-#define FEC_DI_COMM_EXEC__M 0x3 +-#define FEC_DI_COMM_EXEC__PRE 0x0 +-#define FEC_DI_COMM_EXEC_STOP 0x0 +-#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +-#define FEC_DI_COMM_EXEC_HOLD 0x2 +- +-#define FEC_DI_COMM_MB__A 0x1C20002 +-#define FEC_DI_COMM_MB__W 2 +-#define FEC_DI_COMM_MB__M 0x3 +-#define FEC_DI_COMM_MB__PRE 0x0 +-#define FEC_DI_COMM_MB_CTL__B 0 +-#define FEC_DI_COMM_MB_CTL__W 1 +-#define FEC_DI_COMM_MB_CTL__M 0x1 +-#define FEC_DI_COMM_MB_CTL__PRE 0x0 +-#define FEC_DI_COMM_MB_CTL_OFF 0x0 +-#define FEC_DI_COMM_MB_CTL_ON 0x1 +-#define FEC_DI_COMM_MB_OBS__B 1 +-#define FEC_DI_COMM_MB_OBS__W 1 +-#define FEC_DI_COMM_MB_OBS__M 0x2 +-#define FEC_DI_COMM_MB_OBS__PRE 0x0 +-#define FEC_DI_COMM_MB_OBS_OFF 0x0 +-#define FEC_DI_COMM_MB_OBS_ON 0x2 +- +-#define FEC_DI_COMM_INT_REQ__A 0x1C20003 +-#define FEC_DI_COMM_INT_REQ__W 1 +-#define FEC_DI_COMM_INT_REQ__M 0x1 +-#define FEC_DI_COMM_INT_REQ__PRE 0x0 +-#define FEC_DI_COMM_INT_STA__A 0x1C20005 +-#define FEC_DI_COMM_INT_STA__W 2 +-#define FEC_DI_COMM_INT_STA__M 0x3 +-#define FEC_DI_COMM_INT_STA__PRE 0x0 +- +-#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +-#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +-#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +-#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 +- +-#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +-#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +-#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +-#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 +- +-#define FEC_DI_COMM_INT_MSK__A 0x1C20006 +-#define FEC_DI_COMM_INT_MSK__W 2 +-#define FEC_DI_COMM_INT_MSK__M 0x3 +-#define FEC_DI_COMM_INT_MSK__PRE 0x0 +-#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +-#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +-#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +-#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +-#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +-#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +-#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +-#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 +- +-#define FEC_DI_COMM_INT_STM__A 0x1C20007 +-#define FEC_DI_COMM_INT_STM__W 2 +-#define FEC_DI_COMM_INT_STM__M 0x3 +-#define FEC_DI_COMM_INT_STM__PRE 0x0 +-#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +-#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +-#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +-#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +-#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +-#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +-#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +-#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 +- +- +-#define FEC_DI_STATUS__A 0x1C20010 +-#define FEC_DI_STATUS__W 1 +-#define FEC_DI_STATUS__M 0x1 +-#define FEC_DI_STATUS__PRE 0x0 +-#define FEC_DI_MODE__A 0x1C20011 +-#define FEC_DI_MODE__W 3 +-#define FEC_DI_MODE__M 0x7 +-#define FEC_DI_MODE__PRE 0x0 +- +-#define FEC_DI_MODE_NO_SYNC__B 0 +-#define FEC_DI_MODE_NO_SYNC__W 1 +-#define FEC_DI_MODE_NO_SYNC__M 0x1 +-#define FEC_DI_MODE_NO_SYNC__PRE 0x0 +- +-#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +-#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +-#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +-#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 +- +-#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +-#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +-#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +-#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 +- +- +-#define FEC_DI_CONTROL_WORD__A 0x1C20012 +-#define FEC_DI_CONTROL_WORD__W 4 +-#define FEC_DI_CONTROL_WORD__M 0xF +-#define FEC_DI_CONTROL_WORD__PRE 0x0 +- +-#define FEC_DI_RESTART__A 0x1C20013 +-#define FEC_DI_RESTART__W 1 +-#define FEC_DI_RESTART__M 0x1 +-#define FEC_DI_RESTART__PRE 0x0 +- +-#define FEC_DI_TIMEOUT_LO__A 0x1C20014 +-#define FEC_DI_TIMEOUT_LO__W 16 +-#define FEC_DI_TIMEOUT_LO__M 0xFFFF +-#define FEC_DI_TIMEOUT_LO__PRE 0x0 +- +-#define FEC_DI_TIMEOUT_HI__A 0x1C20015 +-#define FEC_DI_TIMEOUT_HI__W 8 +-#define FEC_DI_TIMEOUT_HI__M 0xFF +-#define FEC_DI_TIMEOUT_HI__PRE 0xA +- +-#define FEC_DI_INPUT_CTL__A 0x1C20016 +-#define FEC_DI_INPUT_CTL__W 1 +-#define FEC_DI_INPUT_CTL__M 0x1 +-#define FEC_DI_INPUT_CTL__PRE 0x0 +- +- +- +-#define FEC_RS_COMM_EXEC__A 0x1C30000 +-#define FEC_RS_COMM_EXEC__W 2 +-#define FEC_RS_COMM_EXEC__M 0x3 +-#define FEC_RS_COMM_EXEC__PRE 0x0 +-#define FEC_RS_COMM_EXEC_STOP 0x0 +-#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +-#define FEC_RS_COMM_EXEC_HOLD 0x2 +- +-#define FEC_RS_COMM_MB__A 0x1C30002 +-#define FEC_RS_COMM_MB__W 2 +-#define FEC_RS_COMM_MB__M 0x3 +-#define FEC_RS_COMM_MB__PRE 0x0 +-#define FEC_RS_COMM_MB_CTL__B 0 +-#define FEC_RS_COMM_MB_CTL__W 1 +-#define FEC_RS_COMM_MB_CTL__M 0x1 +-#define FEC_RS_COMM_MB_CTL__PRE 0x0 +-#define FEC_RS_COMM_MB_CTL_OFF 0x0 +-#define FEC_RS_COMM_MB_CTL_ON 0x1 +-#define FEC_RS_COMM_MB_OBS__B 1 +-#define FEC_RS_COMM_MB_OBS__W 1 +-#define FEC_RS_COMM_MB_OBS__M 0x2 +-#define FEC_RS_COMM_MB_OBS__PRE 0x0 +-#define FEC_RS_COMM_MB_OBS_OFF 0x0 +-#define FEC_RS_COMM_MB_OBS_ON 0x2 +- +-#define FEC_RS_COMM_INT_REQ__A 0x1C30003 +-#define FEC_RS_COMM_INT_REQ__W 1 +-#define FEC_RS_COMM_INT_REQ__M 0x1 +-#define FEC_RS_COMM_INT_REQ__PRE 0x0 +-#define FEC_RS_COMM_INT_STA__A 0x1C30005 +-#define FEC_RS_COMM_INT_STA__W 2 +-#define FEC_RS_COMM_INT_STA__M 0x3 +-#define FEC_RS_COMM_INT_STA__PRE 0x0 +- +-#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +-#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +-#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +-#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 +- +-#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +-#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +-#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +-#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 +- +-#define FEC_RS_COMM_INT_MSK__A 0x1C30006 +-#define FEC_RS_COMM_INT_MSK__W 2 +-#define FEC_RS_COMM_INT_MSK__M 0x3 +-#define FEC_RS_COMM_INT_MSK__PRE 0x0 +-#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +-#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +-#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +-#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +-#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +-#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +-#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +-#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 +- +-#define FEC_RS_COMM_INT_STM__A 0x1C30007 +-#define FEC_RS_COMM_INT_STM__W 2 +-#define FEC_RS_COMM_INT_STM__M 0x3 +-#define FEC_RS_COMM_INT_STM__PRE 0x0 +-#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +-#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +-#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +-#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +-#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +-#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +-#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +-#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 +- +-#define FEC_RS_STATUS__A 0x1C30010 +-#define FEC_RS_STATUS__W 1 +-#define FEC_RS_STATUS__M 0x1 +-#define FEC_RS_STATUS__PRE 0x0 +-#define FEC_RS_MODE__A 0x1C30011 +-#define FEC_RS_MODE__W 1 +-#define FEC_RS_MODE__M 0x1 +-#define FEC_RS_MODE__PRE 0x0 +- +-#define FEC_RS_MODE_BYPASS__B 0 +-#define FEC_RS_MODE_BYPASS__W 1 +-#define FEC_RS_MODE_BYPASS__M 0x1 +-#define FEC_RS_MODE_BYPASS__PRE 0x0 +- +-#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +-#define FEC_RS_MEASUREMENT_PERIOD__W 16 +-#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +-#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993 +- +-#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +-#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +-#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +-#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993 +- +-#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +-#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +-#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +-#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 +- +-#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +-#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +-#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +-#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 +- +-#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 +-#define FEC_RS_NR_BIT_ERRORS__W 16 +-#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +-#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF +- +-#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +-#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +-#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +-#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF +- +-#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +-#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +-#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +-#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 +- +-#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015 +-#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +-#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +-#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF +- +-#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +-#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +-#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +-#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF +- +-#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +-#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +-#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +-#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 +- +-#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016 +-#define FEC_RS_NR_PACKET_ERRORS__W 16 +-#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +-#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF +- +-#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +-#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +-#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +-#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF +- +-#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +-#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +-#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +-#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 +- +-#define FEC_RS_NR_FAILURES__A 0x1C30017 +-#define FEC_RS_NR_FAILURES__W 16 +-#define FEC_RS_NR_FAILURES__M 0xFFFF +-#define FEC_RS_NR_FAILURES__PRE 0x0 +- +-#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +-#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +-#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +-#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 +- +-#define FEC_RS_NR_FAILURES_EXP__B 12 +-#define FEC_RS_NR_FAILURES_EXP__W 4 +-#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +-#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 +- +- +- +-#define FEC_OC_COMM_EXEC__A 0x1C40000 +-#define FEC_OC_COMM_EXEC__W 2 +-#define FEC_OC_COMM_EXEC__M 0x3 +-#define FEC_OC_COMM_EXEC__PRE 0x0 +-#define FEC_OC_COMM_EXEC_STOP 0x0 +-#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +-#define FEC_OC_COMM_EXEC_HOLD 0x2 +- +-#define FEC_OC_COMM_MB__A 0x1C40002 +-#define FEC_OC_COMM_MB__W 2 +-#define FEC_OC_COMM_MB__M 0x3 +-#define FEC_OC_COMM_MB__PRE 0x0 +-#define FEC_OC_COMM_MB_CTL__B 0 +-#define FEC_OC_COMM_MB_CTL__W 1 +-#define FEC_OC_COMM_MB_CTL__M 0x1 +-#define FEC_OC_COMM_MB_CTL__PRE 0x0 +-#define FEC_OC_COMM_MB_CTL_OFF 0x0 +-#define FEC_OC_COMM_MB_CTL_ON 0x1 +-#define FEC_OC_COMM_MB_OBS__B 1 +-#define FEC_OC_COMM_MB_OBS__W 1 +-#define FEC_OC_COMM_MB_OBS__M 0x2 +-#define FEC_OC_COMM_MB_OBS__PRE 0x0 +-#define FEC_OC_COMM_MB_OBS_OFF 0x0 +-#define FEC_OC_COMM_MB_OBS_ON 0x2 +- +-#define FEC_OC_COMM_INT_REQ__A 0x1C40003 +-#define FEC_OC_COMM_INT_REQ__W 1 +-#define FEC_OC_COMM_INT_REQ__M 0x1 +-#define FEC_OC_COMM_INT_REQ__PRE 0x0 +-#define FEC_OC_COMM_INT_STA__A 0x1C40005 +-#define FEC_OC_COMM_INT_STA__W 8 +-#define FEC_OC_COMM_INT_STA__M 0xFF +-#define FEC_OC_COMM_INT_STA__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +-#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +-#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +-#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +-#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +-#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +-#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +-#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +-#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +-#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +-#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +-#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +-#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +-#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +-#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +-#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +-#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +-#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +-#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +-#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +-#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +-#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +-#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +-#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +-#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 +- +-#define FEC_OC_COMM_INT_MSK__A 0x1C40006 +-#define FEC_OC_COMM_INT_MSK__W 8 +-#define FEC_OC_COMM_INT_MSK__M 0xFF +-#define FEC_OC_COMM_INT_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +-#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +-#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +-#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +-#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +-#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +-#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +-#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +-#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +-#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +-#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +-#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +-#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +-#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +-#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +-#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +-#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +-#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 +- +-#define FEC_OC_COMM_INT_STM__A 0x1C40007 +-#define FEC_OC_COMM_INT_STM__W 8 +-#define FEC_OC_COMM_INT_STM__M 0xFF +-#define FEC_OC_COMM_INT_STM__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +-#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +-#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +-#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +-#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +-#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +-#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +-#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +-#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +-#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +-#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +-#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +-#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +-#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +-#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +-#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +-#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +-#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +-#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 +- +-#define FEC_OC_STATUS__A 0x1C40010 +-#define FEC_OC_STATUS__W 5 +-#define FEC_OC_STATUS__M 0x1F +-#define FEC_OC_STATUS__PRE 0x0 +- +-#define FEC_OC_STATUS_DPR_STATUS__B 0 +-#define FEC_OC_STATUS_DPR_STATUS__W 1 +-#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +-#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 +- +-#define FEC_OC_STATUS_SNC_STATUS__B 1 +-#define FEC_OC_STATUS_SNC_STATUS__W 2 +-#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +-#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 +-#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0 +-#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2 +-#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4 +- +-#define FEC_OC_STATUS_FIFO_FULL__B 3 +-#define FEC_OC_STATUS_FIFO_FULL__W 1 +-#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +-#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 +- +-#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +-#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +-#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +-#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 +- +-#define FEC_OC_MODE__A 0x1C40011 +-#define FEC_OC_MODE__W 4 +-#define FEC_OC_MODE__M 0xF +-#define FEC_OC_MODE__PRE 0x0 +- +-#define FEC_OC_MODE_PARITY__B 0 +-#define FEC_OC_MODE_PARITY__W 1 +-#define FEC_OC_MODE_PARITY__M 0x1 +-#define FEC_OC_MODE_PARITY__PRE 0x0 +- +-#define FEC_OC_MODE_TRANSPARENT__B 1 +-#define FEC_OC_MODE_TRANSPARENT__W 1 +-#define FEC_OC_MODE_TRANSPARENT__M 0x2 +-#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 +- +-#define FEC_OC_MODE_CLEAR__B 2 +-#define FEC_OC_MODE_CLEAR__W 1 +-#define FEC_OC_MODE_CLEAR__M 0x4 +-#define FEC_OC_MODE_CLEAR__PRE 0x0 +- +-#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +-#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +-#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +-#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 +- +-#define FEC_OC_DPR_MODE__A 0x1C40012 +-#define FEC_OC_DPR_MODE__W 2 +-#define FEC_OC_DPR_MODE__M 0x3 +-#define FEC_OC_DPR_MODE__PRE 0x0 +- +-#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +-#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +-#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +-#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 +- +-#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +-#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +-#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +-#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 +- +- +-#define FEC_OC_DPR_UNLOCK__A 0x1C40013 +-#define FEC_OC_DPR_UNLOCK__W 1 +-#define FEC_OC_DPR_UNLOCK__M 0x1 +-#define FEC_OC_DPR_UNLOCK__PRE 0x0 +-#define FEC_OC_DTO_MODE__A 0x1C40014 +-#define FEC_OC_DTO_MODE__W 3 +-#define FEC_OC_DTO_MODE__M 0x7 +-#define FEC_OC_DTO_MODE__PRE 0x0 +- +-#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +-#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +-#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +-#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 +- +-#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +-#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +-#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +-#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 +- +-#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +-#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +-#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +-#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 +- +- +-#define FEC_OC_DTO_PERIOD__A 0x1C40015 +-#define FEC_OC_DTO_PERIOD__W 8 +-#define FEC_OC_DTO_PERIOD__M 0xFF +-#define FEC_OC_DTO_PERIOD__PRE 0x0 +-#define FEC_OC_DTO_RATE_LO__A 0x1C40016 +-#define FEC_OC_DTO_RATE_LO__W 16 +-#define FEC_OC_DTO_RATE_LO__M 0xFFFF +-#define FEC_OC_DTO_RATE_LO__PRE 0x0 +- +-#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +-#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +-#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +-#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 +- +-#define FEC_OC_DTO_RATE_HI__A 0x1C40017 +-#define FEC_OC_DTO_RATE_HI__W 10 +-#define FEC_OC_DTO_RATE_HI__M 0x3FF +-#define FEC_OC_DTO_RATE_HI__PRE 0xC0 +- +-#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +-#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +-#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +-#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 +- +-#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 +-#define FEC_OC_DTO_BURST_LEN__W 8 +-#define FEC_OC_DTO_BURST_LEN__M 0xFF +-#define FEC_OC_DTO_BURST_LEN__PRE 0xBC +- +-#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +-#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +-#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +-#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC +- +-#define FEC_OC_FCT_MODE__A 0x1C4001A +-#define FEC_OC_FCT_MODE__W 2 +-#define FEC_OC_FCT_MODE__M 0x3 +-#define FEC_OC_FCT_MODE__PRE 0x0 +- +-#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +-#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +-#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +-#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 +- +-#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +-#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +-#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +-#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 +- +-#define FEC_OC_FCT_USAGE__A 0x1C4001B +-#define FEC_OC_FCT_USAGE__W 3 +-#define FEC_OC_FCT_USAGE__M 0x7 +-#define FEC_OC_FCT_USAGE__PRE 0x7 +- +-#define FEC_OC_FCT_USAGE_USAGE__B 0 +-#define FEC_OC_FCT_USAGE_USAGE__W 3 +-#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +-#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7 +- +-#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C +-#define FEC_OC_FCT_OCCUPATION__W 12 +-#define FEC_OC_FCT_OCCUPATION__M 0xFFF +-#define FEC_OC_FCT_OCCUPATION__PRE 0x0 +- +-#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +-#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +-#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +-#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 +- +-#define FEC_OC_TMD_MODE__A 0x1C4001E +-#define FEC_OC_TMD_MODE__W 3 +-#define FEC_OC_TMD_MODE__M 0x7 +-#define FEC_OC_TMD_MODE__PRE 0x4 +- +-#define FEC_OC_TMD_MODE_MODE__B 0 +-#define FEC_OC_TMD_MODE_MODE__W 3 +-#define FEC_OC_TMD_MODE_MODE__M 0x7 +-#define FEC_OC_TMD_MODE_MODE__PRE 0x4 +- +-#define FEC_OC_TMD_COUNT__A 0x1C4001F +-#define FEC_OC_TMD_COUNT__W 10 +-#define FEC_OC_TMD_COUNT__M 0x3FF +-#define FEC_OC_TMD_COUNT__PRE 0x1F4 +- +-#define FEC_OC_TMD_COUNT_COUNT__B 0 +-#define FEC_OC_TMD_COUNT_COUNT__W 10 +-#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +-#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 +- +-#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 +-#define FEC_OC_TMD_HI_MARGIN__W 11 +-#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +-#define FEC_OC_TMD_HI_MARGIN__PRE 0x500 +- +-#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +-#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +-#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +-#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500 +- +-#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 +-#define FEC_OC_TMD_LO_MARGIN__W 11 +-#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +-#define FEC_OC_TMD_LO_MARGIN__PRE 0x300 +- +-#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +-#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +-#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +-#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300 +- +-#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022 +-#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +-#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +-#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 +- +-#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +-#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +-#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +-#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 +- +-#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 +-#define FEC_OC_TMD_INT_UPD_RATE__W 4 +-#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +-#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 +- +-#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +-#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +-#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +-#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 +- +-#define FEC_OC_AVR_PARM_A__A 0x1C40026 +-#define FEC_OC_AVR_PARM_A__W 4 +-#define FEC_OC_AVR_PARM_A__M 0xF +-#define FEC_OC_AVR_PARM_A__PRE 0x6 +- +-#define FEC_OC_AVR_PARM_A_PARM__B 0 +-#define FEC_OC_AVR_PARM_A_PARM__W 4 +-#define FEC_OC_AVR_PARM_A_PARM__M 0xF +-#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 +- +-#define FEC_OC_AVR_PARM_B__A 0x1C40027 +-#define FEC_OC_AVR_PARM_B__W 4 +-#define FEC_OC_AVR_PARM_B__M 0xF +-#define FEC_OC_AVR_PARM_B__PRE 0x4 +- +-#define FEC_OC_AVR_PARM_B_PARM__B 0 +-#define FEC_OC_AVR_PARM_B_PARM__W 4 +-#define FEC_OC_AVR_PARM_B_PARM__M 0xF +-#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 +- +-#define FEC_OC_AVR_AVG_LO__A 0x1C40028 +-#define FEC_OC_AVR_AVG_LO__W 16 +-#define FEC_OC_AVR_AVG_LO__M 0xFFFF +-#define FEC_OC_AVR_AVG_LO__PRE 0x0 +- +-#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +-#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +-#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +-#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 +- +-#define FEC_OC_AVR_AVG_HI__A 0x1C40029 +-#define FEC_OC_AVR_AVG_HI__W 6 +-#define FEC_OC_AVR_AVG_HI__M 0x3F +-#define FEC_OC_AVR_AVG_HI__PRE 0x0 +- +-#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +-#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +-#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +-#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 +- +-#define FEC_OC_RCN_MODE__A 0x1C4002C +-#define FEC_OC_RCN_MODE__W 5 +-#define FEC_OC_RCN_MODE__M 0x1F +-#define FEC_OC_RCN_MODE__PRE 0x1F +- +-#define FEC_OC_RCN_MODE_MODE__B 0 +-#define FEC_OC_RCN_MODE_MODE__W 5 +-#define FEC_OC_RCN_MODE_MODE__M 0x1F +-#define FEC_OC_RCN_MODE_MODE__PRE 0x1F +- +-#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D +-#define FEC_OC_RCN_OCC_SETTLE__W 11 +-#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +-#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400 +- +-#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +-#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +-#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +-#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400 +- +-#define FEC_OC_RCN_GAIN__A 0x1C4002E +-#define FEC_OC_RCN_GAIN__W 4 +-#define FEC_OC_RCN_GAIN__M 0xF +-#define FEC_OC_RCN_GAIN__PRE 0xC +- +-#define FEC_OC_RCN_GAIN_GAIN__B 0 +-#define FEC_OC_RCN_GAIN_GAIN__W 4 +-#define FEC_OC_RCN_GAIN_GAIN__M 0xF +-#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC +- +-#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 +-#define FEC_OC_RCN_CTL_RATE_LO__W 16 +-#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +-#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 +- +-#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +-#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +-#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +-#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 +- +-#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031 +-#define FEC_OC_RCN_CTL_RATE_HI__W 8 +-#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +-#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 +- +-#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +-#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +-#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +-#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 +- +-#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 +-#define FEC_OC_RCN_CTL_STEP_LO__W 16 +-#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +-#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 +- +-#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +-#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +-#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +-#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 +- +-#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 +-#define FEC_OC_RCN_CTL_STEP_HI__W 8 +-#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +-#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 +- +-#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +-#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +-#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +-#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 +- +-#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034 +-#define FEC_OC_RCN_DTO_OFS_LO__W 16 +-#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +-#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 +- +-#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +-#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +-#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +-#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 +- +-#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035 +-#define FEC_OC_RCN_DTO_OFS_HI__W 8 +-#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +-#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 +- +-#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +-#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +-#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +-#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 +- +-#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036 +-#define FEC_OC_RCN_DTO_RATE_LO__W 16 +-#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +-#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 +- +-#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +-#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +-#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +-#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 +- +-#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037 +-#define FEC_OC_RCN_DTO_RATE_HI__W 8 +-#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +-#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 +- +-#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +-#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +-#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +-#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 +- +-#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038 +-#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +-#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +-#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 +- +-#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +-#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +-#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +-#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 +- +-#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039 +-#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +-#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +-#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 +- +-#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +-#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +-#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +-#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 +- +-#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A +-#define FEC_OC_RCN_DYN_RATE_LO__W 16 +-#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +-#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 +- +-#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +-#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +-#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +-#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 +- +-#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B +-#define FEC_OC_RCN_DYN_RATE_HI__W 8 +-#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +-#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 +- +-#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +-#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +-#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +-#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 +- +-#define FEC_OC_SNC_MODE__A 0x1C40040 +-#define FEC_OC_SNC_MODE__W 5 +-#define FEC_OC_SNC_MODE__M 0x1F +-#define FEC_OC_SNC_MODE__PRE 0x0 +- +-#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +-#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +-#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +-#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 +- +-#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +-#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +-#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +-#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 +- +-#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +-#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +-#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +-#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 +- +-#define FEC_OC_SNC_MODE_SHUTDOWN__B 4 +-#define FEC_OC_SNC_MODE_SHUTDOWN__W 1 +-#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +-#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0 +- +-#define FEC_OC_SNC_LWM__A 0x1C40041 +-#define FEC_OC_SNC_LWM__W 4 +-#define FEC_OC_SNC_LWM__M 0xF +-#define FEC_OC_SNC_LWM__PRE 0x3 +- +-#define FEC_OC_SNC_LWM_MARK__B 0 +-#define FEC_OC_SNC_LWM_MARK__W 4 +-#define FEC_OC_SNC_LWM_MARK__M 0xF +-#define FEC_OC_SNC_LWM_MARK__PRE 0x3 +- +-#define FEC_OC_SNC_HWM__A 0x1C40042 +-#define FEC_OC_SNC_HWM__W 4 +-#define FEC_OC_SNC_HWM__M 0xF +-#define FEC_OC_SNC_HWM__PRE 0x5 +- +-#define FEC_OC_SNC_HWM_MARK__B 0 +-#define FEC_OC_SNC_HWM_MARK__W 4 +-#define FEC_OC_SNC_HWM_MARK__M 0xF +-#define FEC_OC_SNC_HWM_MARK__PRE 0x5 +- +-#define FEC_OC_SNC_UNLOCK__A 0x1C40043 +-#define FEC_OC_SNC_UNLOCK__W 1 +-#define FEC_OC_SNC_UNLOCK__M 0x1 +-#define FEC_OC_SNC_UNLOCK__PRE 0x0 +- +-#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +-#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +-#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +-#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 +- +-#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044 +-#define FEC_OC_SNC_LOCK_COUNT__W 12 +-#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +-#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 +- +-#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +-#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +-#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +-#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 +- +-#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045 +-#define FEC_OC_SNC_FAIL_COUNT__W 12 +-#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +-#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 +- +-#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +-#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +-#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +-#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 +- +-#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 +-#define FEC_OC_SNC_FAIL_PERIOD__W 16 +-#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +-#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 +- +-#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +-#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +-#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +-#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 +- +-#define FEC_OC_EMS_MODE__A 0x1C40047 +-#define FEC_OC_EMS_MODE__W 2 +-#define FEC_OC_EMS_MODE__M 0x3 +-#define FEC_OC_EMS_MODE__PRE 0x0 +- +-#define FEC_OC_EMS_MODE_MODE__B 0 +-#define FEC_OC_EMS_MODE_MODE__W 2 +-#define FEC_OC_EMS_MODE_MODE__M 0x3 +-#define FEC_OC_EMS_MODE_MODE__PRE 0x0 +- +-#define FEC_OC_IPR_MODE__A 0x1C40048 +-#define FEC_OC_IPR_MODE__W 12 +-#define FEC_OC_IPR_MODE__M 0xFFF +-#define FEC_OC_IPR_MODE__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_SERIAL__B 0 +-#define FEC_OC_IPR_MODE_SERIAL__W 1 +-#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +-#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +-#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +-#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +-#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +-#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +-#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +-#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +-#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +-#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +-#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +-#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +-#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +-#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +-#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +-#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +-#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +-#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +-#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +-#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +-#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +-#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +-#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +-#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +-#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +-#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +-#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +-#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +-#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +-#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +-#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +-#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 +- +-#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +-#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +-#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +-#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT__A 0x1C40049 +-#define FEC_OC_IPR_INVERT__W 12 +-#define FEC_OC_IPR_INVERT__M 0xFFF +-#define FEC_OC_IPR_INVERT__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD0__B 0 +-#define FEC_OC_IPR_INVERT_MD0__W 1 +-#define FEC_OC_IPR_INVERT_MD0__M 0x1 +-#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD1__B 1 +-#define FEC_OC_IPR_INVERT_MD1__W 1 +-#define FEC_OC_IPR_INVERT_MD1__M 0x2 +-#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD2__B 2 +-#define FEC_OC_IPR_INVERT_MD2__W 1 +-#define FEC_OC_IPR_INVERT_MD2__M 0x4 +-#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD3__B 3 +-#define FEC_OC_IPR_INVERT_MD3__W 1 +-#define FEC_OC_IPR_INVERT_MD3__M 0x8 +-#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD4__B 4 +-#define FEC_OC_IPR_INVERT_MD4__W 1 +-#define FEC_OC_IPR_INVERT_MD4__M 0x10 +-#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD5__B 5 +-#define FEC_OC_IPR_INVERT_MD5__W 1 +-#define FEC_OC_IPR_INVERT_MD5__M 0x20 +-#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD6__B 6 +-#define FEC_OC_IPR_INVERT_MD6__W 1 +-#define FEC_OC_IPR_INVERT_MD6__M 0x40 +-#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MD7__B 7 +-#define FEC_OC_IPR_INVERT_MD7__W 1 +-#define FEC_OC_IPR_INVERT_MD7__M 0x80 +-#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MERR__B 8 +-#define FEC_OC_IPR_INVERT_MERR__W 1 +-#define FEC_OC_IPR_INVERT_MERR__M 0x100 +-#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MSTRT__B 9 +-#define FEC_OC_IPR_INVERT_MSTRT__W 1 +-#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +-#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MVAL__B 10 +-#define FEC_OC_IPR_INVERT_MVAL__W 1 +-#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +-#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 +- +-#define FEC_OC_IPR_INVERT_MCLK__B 11 +-#define FEC_OC_IPR_INVERT_MCLK__W 1 +-#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +-#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 +- +-#define FEC_OC_OCR_MODE__A 0x1C40050 +-#define FEC_OC_OCR_MODE__W 4 +-#define FEC_OC_OCR_MODE__M 0xF +-#define FEC_OC_OCR_MODE__PRE 0x0 +- +-#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +-#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +-#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +-#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 +- +-#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +-#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +-#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +-#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 +- +-#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +-#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +-#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +-#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 +- +-#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +-#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +-#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +-#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 +- +-#define FEC_OC_OCR_RATE__A 0x1C40051 +-#define FEC_OC_OCR_RATE__W 4 +-#define FEC_OC_OCR_RATE__M 0xF +-#define FEC_OC_OCR_RATE__PRE 0x0 +- +-#define FEC_OC_OCR_RATE_RATE__B 0 +-#define FEC_OC_OCR_RATE_RATE__W 4 +-#define FEC_OC_OCR_RATE_RATE__M 0xF +-#define FEC_OC_OCR_RATE_RATE__PRE 0x0 +- +-#define FEC_OC_OCR_INVERT__A 0x1C40052 +-#define FEC_OC_OCR_INVERT__W 12 +-#define FEC_OC_OCR_INVERT__M 0xFFF +-#define FEC_OC_OCR_INVERT__PRE 0x800 +- +-#define FEC_OC_OCR_INVERT_INVERT__B 0 +-#define FEC_OC_OCR_INVERT_INVERT__W 12 +-#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +-#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 +- +-#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053 +-#define FEC_OC_OCR_GRAB_COUNT__W 16 +-#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +-#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +-#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +-#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +-#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054 +-#define FEC_OC_OCR_GRAB_SYNC__W 8 +-#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +-#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +-#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +-#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +-#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +-#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +-#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +-#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +-#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +-#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +-#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055 +-#define FEC_OC_OCR_GRAB_RD0__W 10 +-#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +-#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +-#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056 +-#define FEC_OC_OCR_GRAB_RD1__W 10 +-#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +-#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +-#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057 +-#define FEC_OC_OCR_GRAB_RD2__W 10 +-#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +-#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +-#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058 +-#define FEC_OC_OCR_GRAB_RD3__W 10 +-#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +-#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +-#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059 +-#define FEC_OC_OCR_GRAB_RD4__W 10 +-#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +-#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +-#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A +-#define FEC_OC_OCR_GRAB_RD5__W 10 +-#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 +- +-#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +-#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +-#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +-#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 +- +- +- +-#define FEC_DI_RAM__A 0x1C50000 +- +- +- +-#define FEC_RS_RAM__A 0x1C60000 +- +- +- +-#define FEC_OC_RAM__A 0x1C70000 +- +- +- +- +- +-#define IQM_COMM_EXEC__A 0x1800000 +-#define IQM_COMM_EXEC__W 2 +-#define IQM_COMM_EXEC__M 0x3 +-#define IQM_COMM_EXEC__PRE 0x0 +-#define IQM_COMM_EXEC_B__B 0 +-#define IQM_COMM_EXEC_B__W 2 +-#define IQM_COMM_EXEC_B__M 0x3 +-#define IQM_COMM_EXEC_B__PRE 0x0 +-#define IQM_COMM_EXEC_B_STOP 0x0 +-#define IQM_COMM_EXEC_B_ACTIVE 0x1 +-#define IQM_COMM_EXEC_B_HOLD 0x2 +- +-#define IQM_COMM_MB__A 0x1800002 +-#define IQM_COMM_MB__W 16 +-#define IQM_COMM_MB__M 0xFFFF +-#define IQM_COMM_MB__PRE 0x0 +-#define IQM_COMM_MB_B__B 0 +-#define IQM_COMM_MB_B__W 16 +-#define IQM_COMM_MB_B__M 0xFFFF +-#define IQM_COMM_MB_B__PRE 0x0 +- +-#define IQM_COMM_INT_REQ__A 0x1800003 +-#define IQM_COMM_INT_REQ__W 3 +-#define IQM_COMM_INT_REQ__M 0x7 +-#define IQM_COMM_INT_REQ__PRE 0x0 +- +-#define IQM_COMM_INT_REQ_AF_REQ__B 0 +-#define IQM_COMM_INT_REQ_AF_REQ__W 1 +-#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +-#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 +- +-#define IQM_COMM_INT_REQ_CF_REQ__B 1 +-#define IQM_COMM_INT_REQ_CF_REQ__W 1 +-#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +-#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 +- +-#define IQM_COMM_INT_REQ_CW_REQ__B 2 +-#define IQM_COMM_INT_REQ_CW_REQ__W 1 +-#define IQM_COMM_INT_REQ_CW_REQ__M 0x4 +-#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0 +- +-#define IQM_COMM_INT_STA__A 0x1800005 +-#define IQM_COMM_INT_STA__W 16 +-#define IQM_COMM_INT_STA__M 0xFFFF +-#define IQM_COMM_INT_STA__PRE 0x0 +-#define IQM_COMM_INT_STA_B__B 0 +-#define IQM_COMM_INT_STA_B__W 16 +-#define IQM_COMM_INT_STA_B__M 0xFFFF +-#define IQM_COMM_INT_STA_B__PRE 0x0 +- +-#define IQM_COMM_INT_MSK__A 0x1800006 +-#define IQM_COMM_INT_MSK__W 16 +-#define IQM_COMM_INT_MSK__M 0xFFFF +-#define IQM_COMM_INT_MSK__PRE 0x0 +-#define IQM_COMM_INT_MSK_B__B 0 +-#define IQM_COMM_INT_MSK_B__W 16 +-#define IQM_COMM_INT_MSK_B__M 0xFFFF +-#define IQM_COMM_INT_MSK_B__PRE 0x0 +- +-#define IQM_COMM_INT_STM__A 0x1800007 +-#define IQM_COMM_INT_STM__W 16 +-#define IQM_COMM_INT_STM__M 0xFFFF +-#define IQM_COMM_INT_STM__PRE 0x0 +-#define IQM_COMM_INT_STM_B__B 0 +-#define IQM_COMM_INT_STM_B__W 16 +-#define IQM_COMM_INT_STM_B__M 0xFFFF +-#define IQM_COMM_INT_STM_B__PRE 0x0 +- +- +- +-#define IQM_FS_COMM_EXEC__A 0x1820000 +-#define IQM_FS_COMM_EXEC__W 2 +-#define IQM_FS_COMM_EXEC__M 0x3 +-#define IQM_FS_COMM_EXEC__PRE 0x0 +-#define IQM_FS_COMM_EXEC_STOP 0x0 +-#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +-#define IQM_FS_COMM_EXEC_HOLD 0x2 +- +-#define IQM_FS_COMM_MB__A 0x1820002 +-#define IQM_FS_COMM_MB__W 4 +-#define IQM_FS_COMM_MB__M 0xF +-#define IQM_FS_COMM_MB__PRE 0x0 +-#define IQM_FS_COMM_MB_CTL__B 0 +-#define IQM_FS_COMM_MB_CTL__W 1 +-#define IQM_FS_COMM_MB_CTL__M 0x1 +-#define IQM_FS_COMM_MB_CTL__PRE 0x0 +-#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +-#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +-#define IQM_FS_COMM_MB_OBS__B 1 +-#define IQM_FS_COMM_MB_OBS__W 1 +-#define IQM_FS_COMM_MB_OBS__M 0x2 +-#define IQM_FS_COMM_MB_OBS__PRE 0x0 +-#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +-#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 +-#define IQM_FS_COMM_MB_CTL_MUX__B 2 +-#define IQM_FS_COMM_MB_CTL_MUX__W 1 +-#define IQM_FS_COMM_MB_CTL_MUX__M 0x4 +-#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0 +-#define IQM_FS_COMM_MB_OBS_MUX__B 3 +-#define IQM_FS_COMM_MB_OBS_MUX__W 1 +-#define IQM_FS_COMM_MB_OBS_MUX__M 0x8 +-#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0 +- +-#define IQM_FS_RATE_OFS_LO__A 0x1820010 +-#define IQM_FS_RATE_OFS_LO__W 16 +-#define IQM_FS_RATE_OFS_LO__M 0xFFFF +-#define IQM_FS_RATE_OFS_LO__PRE 0x0 +-#define IQM_FS_RATE_OFS_LO_B__B 0 +-#define IQM_FS_RATE_OFS_LO_B__W 16 +-#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF +-#define IQM_FS_RATE_OFS_LO_B__PRE 0x0 +- +-#define IQM_FS_RATE_OFS_HI__A 0x1820011 +-#define IQM_FS_RATE_OFS_HI__W 12 +-#define IQM_FS_RATE_OFS_HI__M 0xFFF +-#define IQM_FS_RATE_OFS_HI__PRE 0x0 +-#define IQM_FS_RATE_OFS_HI_B__B 0 +-#define IQM_FS_RATE_OFS_HI_B__W 12 +-#define IQM_FS_RATE_OFS_HI_B__M 0xFFF +-#define IQM_FS_RATE_OFS_HI_B__PRE 0x0 +- +-#define IQM_FS_RATE_LO__A 0x1820012 +-#define IQM_FS_RATE_LO__W 16 +-#define IQM_FS_RATE_LO__M 0xFFFF +-#define IQM_FS_RATE_LO__PRE 0x0 +-#define IQM_FS_RATE_LO_B__B 0 +-#define IQM_FS_RATE_LO_B__W 16 +-#define IQM_FS_RATE_LO_B__M 0xFFFF +-#define IQM_FS_RATE_LO_B__PRE 0x0 +- +-#define IQM_FS_RATE_HI__A 0x1820013 +-#define IQM_FS_RATE_HI__W 12 +-#define IQM_FS_RATE_HI__M 0xFFF +-#define IQM_FS_RATE_HI__PRE 0x0 +-#define IQM_FS_RATE_HI_B__B 0 +-#define IQM_FS_RATE_HI_B__W 12 +-#define IQM_FS_RATE_HI_B__M 0xFFF +-#define IQM_FS_RATE_HI_B__PRE 0x0 +- +-#define IQM_FS_ADJ_SEL__A 0x1820014 +-#define IQM_FS_ADJ_SEL__W 2 +-#define IQM_FS_ADJ_SEL__M 0x3 +-#define IQM_FS_ADJ_SEL__PRE 0x0 +- +-#define IQM_FS_ADJ_SEL_B__B 0 +-#define IQM_FS_ADJ_SEL_B__W 2 +-#define IQM_FS_ADJ_SEL_B__M 0x3 +-#define IQM_FS_ADJ_SEL_B__PRE 0x0 +-#define IQM_FS_ADJ_SEL_B_OFF 0x0 +-#define IQM_FS_ADJ_SEL_B_QAM 0x1 +-#define IQM_FS_ADJ_SEL_B_VSB 0x2 +- +- +- +-#define IQM_FD_COMM_EXEC__A 0x1830000 +-#define IQM_FD_COMM_EXEC__W 2 +-#define IQM_FD_COMM_EXEC__M 0x3 +-#define IQM_FD_COMM_EXEC__PRE 0x0 +-#define IQM_FD_COMM_EXEC_STOP 0x0 +-#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +-#define IQM_FD_COMM_EXEC_HOLD 0x2 +- +-#define IQM_FD_COMM_MB__A 0x1830002 +-#define IQM_FD_COMM_MB__W 2 +-#define IQM_FD_COMM_MB__M 0x3 +-#define IQM_FD_COMM_MB__PRE 0x0 +-#define IQM_FD_COMM_MB_CTL__B 0 +-#define IQM_FD_COMM_MB_CTL__W 1 +-#define IQM_FD_COMM_MB_CTL__M 0x1 +-#define IQM_FD_COMM_MB_CTL__PRE 0x0 +-#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +-#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +-#define IQM_FD_COMM_MB_OBS__B 1 +-#define IQM_FD_COMM_MB_OBS__W 1 +-#define IQM_FD_COMM_MB_OBS__M 0x2 +-#define IQM_FD_COMM_MB_OBS__PRE 0x0 +-#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +-#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 +- +-#define IQM_FD_RATESEL__A 0x1830010 +-#define IQM_FD_RATESEL__W 2 +-#define IQM_FD_RATESEL__M 0x3 +-#define IQM_FD_RATESEL__PRE 0x0 +-#define IQM_FD_RATESEL_B__B 0 +-#define IQM_FD_RATESEL_B__W 2 +-#define IQM_FD_RATESEL_B__M 0x3 +-#define IQM_FD_RATESEL_B__PRE 0x0 +-#define IQM_FD_RATESEL_B_DS0 0x0 +-#define IQM_FD_RATESEL_B_DS1 0x1 +-#define IQM_FD_RATESEL_B_DS2 0x2 +-#define IQM_FD_RATESEL_B_DS3 0x3 +- +- +- +-#define IQM_RC_COMM_EXEC__A 0x1840000 +-#define IQM_RC_COMM_EXEC__W 2 +-#define IQM_RC_COMM_EXEC__M 0x3 +-#define IQM_RC_COMM_EXEC__PRE 0x0 +-#define IQM_RC_COMM_EXEC_STOP 0x0 +-#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +-#define IQM_RC_COMM_EXEC_HOLD 0x2 +- +-#define IQM_RC_COMM_MB__A 0x1840002 +-#define IQM_RC_COMM_MB__W 2 +-#define IQM_RC_COMM_MB__M 0x3 +-#define IQM_RC_COMM_MB__PRE 0x0 +-#define IQM_RC_COMM_MB_CTL__B 0 +-#define IQM_RC_COMM_MB_CTL__W 1 +-#define IQM_RC_COMM_MB_CTL__M 0x1 +-#define IQM_RC_COMM_MB_CTL__PRE 0x0 +-#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +-#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +-#define IQM_RC_COMM_MB_OBS__B 1 +-#define IQM_RC_COMM_MB_OBS__W 1 +-#define IQM_RC_COMM_MB_OBS__M 0x2 +-#define IQM_RC_COMM_MB_OBS__PRE 0x0 +-#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +-#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 +- +-#define IQM_RC_RATE_OFS_LO__A 0x1840010 +-#define IQM_RC_RATE_OFS_LO__W 16 +-#define IQM_RC_RATE_OFS_LO__M 0xFFFF +-#define IQM_RC_RATE_OFS_LO__PRE 0x0 +-#define IQM_RC_RATE_OFS_LO_B__B 0 +-#define IQM_RC_RATE_OFS_LO_B__W 16 +-#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF +-#define IQM_RC_RATE_OFS_LO_B__PRE 0x0 +- +-#define IQM_RC_RATE_OFS_HI__A 0x1840011 +-#define IQM_RC_RATE_OFS_HI__W 8 +-#define IQM_RC_RATE_OFS_HI__M 0xFF +-#define IQM_RC_RATE_OFS_HI__PRE 0x0 +-#define IQM_RC_RATE_OFS_HI_B__B 0 +-#define IQM_RC_RATE_OFS_HI_B__W 8 +-#define IQM_RC_RATE_OFS_HI_B__M 0xFF +-#define IQM_RC_RATE_OFS_HI_B__PRE 0x0 +- +-#define IQM_RC_RATE_LO__A 0x1840012 +-#define IQM_RC_RATE_LO__W 16 +-#define IQM_RC_RATE_LO__M 0xFFFF +-#define IQM_RC_RATE_LO__PRE 0x0 +-#define IQM_RC_RATE_LO_B__B 0 +-#define IQM_RC_RATE_LO_B__W 16 +-#define IQM_RC_RATE_LO_B__M 0xFFFF +-#define IQM_RC_RATE_LO_B__PRE 0x0 +- +-#define IQM_RC_RATE_HI__A 0x1840013 +-#define IQM_RC_RATE_HI__W 8 +-#define IQM_RC_RATE_HI__M 0xFF +-#define IQM_RC_RATE_HI__PRE 0x0 +-#define IQM_RC_RATE_HI_B__B 0 +-#define IQM_RC_RATE_HI_B__W 8 +-#define IQM_RC_RATE_HI_B__M 0xFF +-#define IQM_RC_RATE_HI_B__PRE 0x0 +- +-#define IQM_RC_ADJ_SEL__A 0x1840014 +-#define IQM_RC_ADJ_SEL__W 2 +-#define IQM_RC_ADJ_SEL__M 0x3 +-#define IQM_RC_ADJ_SEL__PRE 0x0 +- +-#define IQM_RC_ADJ_SEL_B__B 0 +-#define IQM_RC_ADJ_SEL_B__W 2 +-#define IQM_RC_ADJ_SEL_B__M 0x3 +-#define IQM_RC_ADJ_SEL_B__PRE 0x0 +-#define IQM_RC_ADJ_SEL_B_OFF 0x0 +-#define IQM_RC_ADJ_SEL_B_QAM 0x1 +-#define IQM_RC_ADJ_SEL_B_VSB 0x2 +- +-#define IQM_RC_CROUT_ENA__A 0x1840015 +-#define IQM_RC_CROUT_ENA__W 1 +-#define IQM_RC_CROUT_ENA__M 0x1 +-#define IQM_RC_CROUT_ENA__PRE 0x0 +- +-#define IQM_RC_CROUT_ENA_ENA__B 0 +-#define IQM_RC_CROUT_ENA_ENA__W 1 +-#define IQM_RC_CROUT_ENA_ENA__M 0x1 +-#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 +- +-#define IQM_RC_STRETCH__A 0x1840016 +-#define IQM_RC_STRETCH__W 5 +-#define IQM_RC_STRETCH__M 0x1F +-#define IQM_RC_STRETCH__PRE 0x0 +- +-#define IQM_RC_STRETCH_B__B 0 +-#define IQM_RC_STRETCH_B__W 5 +-#define IQM_RC_STRETCH_B__M 0x1F +-#define IQM_RC_STRETCH_B__PRE 0x0 +- +- +- +-#define IQM_RT_COMM_EXEC__A 0x1850000 +-#define IQM_RT_COMM_EXEC__W 2 +-#define IQM_RT_COMM_EXEC__M 0x3 +-#define IQM_RT_COMM_EXEC__PRE 0x0 +-#define IQM_RT_COMM_EXEC_STOP 0x0 +-#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +-#define IQM_RT_COMM_EXEC_HOLD 0x2 +- +-#define IQM_RT_COMM_MB__A 0x1850002 +-#define IQM_RT_COMM_MB__W 2 +-#define IQM_RT_COMM_MB__M 0x3 +-#define IQM_RT_COMM_MB__PRE 0x0 +-#define IQM_RT_COMM_MB_CTL__B 0 +-#define IQM_RT_COMM_MB_CTL__W 1 +-#define IQM_RT_COMM_MB_CTL__M 0x1 +-#define IQM_RT_COMM_MB_CTL__PRE 0x0 +-#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +-#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +-#define IQM_RT_COMM_MB_OBS__B 1 +-#define IQM_RT_COMM_MB_OBS__W 1 +-#define IQM_RT_COMM_MB_OBS__M 0x2 +-#define IQM_RT_COMM_MB_OBS__PRE 0x0 +-#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +-#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 +- +-#define IQM_RT_ACTIVE__A 0x1850010 +-#define IQM_RT_ACTIVE__W 2 +-#define IQM_RT_ACTIVE__M 0x3 +-#define IQM_RT_ACTIVE__PRE 0x0 +- +-#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +-#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +-#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +-#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +-#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +-#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 +- +-#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +-#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +-#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +-#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +-#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +-#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 +- +- +-#define IQM_RT_LO_INCR__A 0x1850011 +-#define IQM_RT_LO_INCR__W 12 +-#define IQM_RT_LO_INCR__M 0xFFF +-#define IQM_RT_LO_INCR__PRE 0x588 +-#define IQM_RT_LO_INCR_FM 0x0 +-#define IQM_RT_LO_INCR_MN 0x588 +- +-#define IQM_RT_ROT_BP__A 0x1850012 +-#define IQM_RT_ROT_BP__W 3 +-#define IQM_RT_ROT_BP__M 0x7 +-#define IQM_RT_ROT_BP__PRE 0x0 +- +-#define IQM_RT_ROT_BP_ROT_OFF__B 0 +-#define IQM_RT_ROT_BP_ROT_OFF__W 1 +-#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +-#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +-#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +-#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 +- +-#define IQM_RT_ROT_BP_ROT_BPF__B 1 +-#define IQM_RT_ROT_BP_ROT_BPF__W 1 +-#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +-#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 +- +-#define IQM_RT_ROT_BP_MIX_BP__B 2 +-#define IQM_RT_ROT_BP_MIX_BP__W 1 +-#define IQM_RT_ROT_BP_MIX_BP__M 0x4 +-#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0 +- +- +-#define IQM_RT_LP_BP__A 0x1850013 +-#define IQM_RT_LP_BP__W 1 +-#define IQM_RT_LP_BP__M 0x1 +-#define IQM_RT_LP_BP__PRE 0x0 +- +-#define IQM_RT_DELAY__A 0x1850014 +-#define IQM_RT_DELAY__W 7 +-#define IQM_RT_DELAY__M 0x7F +-#define IQM_RT_DELAY__PRE 0x45 +- +- +- +-#define IQM_CF_COMM_EXEC__A 0x1860000 +-#define IQM_CF_COMM_EXEC__W 2 +-#define IQM_CF_COMM_EXEC__M 0x3 +-#define IQM_CF_COMM_EXEC__PRE 0x0 +-#define IQM_CF_COMM_EXEC_STOP 0x0 +-#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +-#define IQM_CF_COMM_EXEC_HOLD 0x2 +- +-#define IQM_CF_COMM_MB__A 0x1860002 +-#define IQM_CF_COMM_MB__W 2 +-#define IQM_CF_COMM_MB__M 0x3 +-#define IQM_CF_COMM_MB__PRE 0x0 +-#define IQM_CF_COMM_MB_CTL__B 0 +-#define IQM_CF_COMM_MB_CTL__W 1 +-#define IQM_CF_COMM_MB_CTL__M 0x1 +-#define IQM_CF_COMM_MB_CTL__PRE 0x0 +-#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +-#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +-#define IQM_CF_COMM_MB_OBS__B 1 +-#define IQM_CF_COMM_MB_OBS__W 1 +-#define IQM_CF_COMM_MB_OBS__M 0x2 +-#define IQM_CF_COMM_MB_OBS__PRE 0x0 +-#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +-#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 +- +-#define IQM_CF_COMM_INT_REQ__A 0x1860003 +-#define IQM_CF_COMM_INT_REQ__W 1 +-#define IQM_CF_COMM_INT_REQ__M 0x1 +-#define IQM_CF_COMM_INT_REQ__PRE 0x0 +-#define IQM_CF_COMM_INT_STA__A 0x1860005 +-#define IQM_CF_COMM_INT_STA__W 2 +-#define IQM_CF_COMM_INT_STA__M 0x3 +-#define IQM_CF_COMM_INT_STA__PRE 0x0 +-#define IQM_CF_COMM_INT_STA_PM__B 0 +-#define IQM_CF_COMM_INT_STA_PM__W 1 +-#define IQM_CF_COMM_INT_STA_PM__M 0x1 +-#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 +-#define IQM_CF_COMM_INT_STA_INC__B 1 +-#define IQM_CF_COMM_INT_STA_INC__W 1 +-#define IQM_CF_COMM_INT_STA_INC__M 0x2 +-#define IQM_CF_COMM_INT_STA_INC__PRE 0x0 +- +-#define IQM_CF_COMM_INT_MSK__A 0x1860006 +-#define IQM_CF_COMM_INT_MSK__W 2 +-#define IQM_CF_COMM_INT_MSK__M 0x3 +-#define IQM_CF_COMM_INT_MSK__PRE 0x0 +-#define IQM_CF_COMM_INT_MSK_PM__B 0 +-#define IQM_CF_COMM_INT_MSK_PM__W 1 +-#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +-#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 +-#define IQM_CF_COMM_INT_MSK_INC__B 1 +-#define IQM_CF_COMM_INT_MSK_INC__W 1 +-#define IQM_CF_COMM_INT_MSK_INC__M 0x2 +-#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0 +- +-#define IQM_CF_COMM_INT_STM__A 0x1860007 +-#define IQM_CF_COMM_INT_STM__W 2 +-#define IQM_CF_COMM_INT_STM__M 0x3 +-#define IQM_CF_COMM_INT_STM__PRE 0x0 +-#define IQM_CF_COMM_INT_STM_PM__B 0 +-#define IQM_CF_COMM_INT_STM_PM__W 1 +-#define IQM_CF_COMM_INT_STM_PM__M 0x1 +-#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 +-#define IQM_CF_COMM_INT_STM_INC__B 1 +-#define IQM_CF_COMM_INT_STM_INC__W 1 +-#define IQM_CF_COMM_INT_STM_INC__M 0x2 +-#define IQM_CF_COMM_INT_STM_INC__PRE 0x0 +- +-#define IQM_CF_SYMMETRIC__A 0x1860010 +-#define IQM_CF_SYMMETRIC__W 2 +-#define IQM_CF_SYMMETRIC__M 0x3 +-#define IQM_CF_SYMMETRIC__PRE 0x0 +- +-#define IQM_CF_SYMMETRIC_RE__B 0 +-#define IQM_CF_SYMMETRIC_RE__W 1 +-#define IQM_CF_SYMMETRIC_RE__M 0x1 +-#define IQM_CF_SYMMETRIC_RE__PRE 0x0 +- +-#define IQM_CF_SYMMETRIC_IM__B 1 +-#define IQM_CF_SYMMETRIC_IM__W 1 +-#define IQM_CF_SYMMETRIC_IM__M 0x2 +-#define IQM_CF_SYMMETRIC_IM__PRE 0x0 +- +-#define IQM_CF_MIDTAP__A 0x1860011 +-#define IQM_CF_MIDTAP__W 3 +-#define IQM_CF_MIDTAP__M 0x7 +-#define IQM_CF_MIDTAP__PRE 0x3 +- +-#define IQM_CF_MIDTAP_RE__B 0 +-#define IQM_CF_MIDTAP_RE__W 1 +-#define IQM_CF_MIDTAP_RE__M 0x1 +-#define IQM_CF_MIDTAP_RE__PRE 0x1 +- +-#define IQM_CF_MIDTAP_IM__B 1 +-#define IQM_CF_MIDTAP_IM__W 1 +-#define IQM_CF_MIDTAP_IM__M 0x2 +-#define IQM_CF_MIDTAP_IM__PRE 0x2 +- +-#define IQM_CF_MIDTAP_SCALE__B 2 +-#define IQM_CF_MIDTAP_SCALE__W 1 +-#define IQM_CF_MIDTAP_SCALE__M 0x4 +-#define IQM_CF_MIDTAP_SCALE__PRE 0x0 +- +-#define IQM_CF_OUT_ENA__A 0x1860012 +-#define IQM_CF_OUT_ENA__W 3 +-#define IQM_CF_OUT_ENA__M 0x7 +-#define IQM_CF_OUT_ENA__PRE 0x0 +- +-#define IQM_CF_OUT_ENA_ATV__B 0 +-#define IQM_CF_OUT_ENA_ATV__W 1 +-#define IQM_CF_OUT_ENA_ATV__M 0x1 +-#define IQM_CF_OUT_ENA_ATV__PRE 0x0 +- +-#define IQM_CF_OUT_ENA_QAM__B 1 +-#define IQM_CF_OUT_ENA_QAM__W 1 +-#define IQM_CF_OUT_ENA_QAM__M 0x2 +-#define IQM_CF_OUT_ENA_QAM__PRE 0x0 +- +-#define IQM_CF_OUT_ENA_OFDM__B 2 +-#define IQM_CF_OUT_ENA_OFDM__W 1 +-#define IQM_CF_OUT_ENA_OFDM__M 0x4 +-#define IQM_CF_OUT_ENA_OFDM__PRE 0x0 +- +-#define IQM_CF_ADJ_SEL__A 0x1860013 +-#define IQM_CF_ADJ_SEL__W 2 +-#define IQM_CF_ADJ_SEL__M 0x3 +-#define IQM_CF_ADJ_SEL__PRE 0x0 +- +-#define IQM_CF_ADJ_SEL_B__B 0 +-#define IQM_CF_ADJ_SEL_B__W 2 +-#define IQM_CF_ADJ_SEL_B__M 0x3 +-#define IQM_CF_ADJ_SEL_B__PRE 0x0 +- +-#define IQM_CF_SCALE__A 0x1860014 +-#define IQM_CF_SCALE__W 14 +-#define IQM_CF_SCALE__M 0x3FFF +-#define IQM_CF_SCALE__PRE 0x400 +-#define IQM_CF_SCALE_B__B 0 +-#define IQM_CF_SCALE_B__W 14 +-#define IQM_CF_SCALE_B__M 0x3FFF +-#define IQM_CF_SCALE_B__PRE 0x400 +- +-#define IQM_CF_SCALE_SH__A 0x1860015 +-#define IQM_CF_SCALE_SH__W 2 +-#define IQM_CF_SCALE_SH__M 0x3 +-#define IQM_CF_SCALE_SH__PRE 0x0 +- +-#define IQM_CF_SCALE_SH_B__B 0 +-#define IQM_CF_SCALE_SH_B__W 2 +-#define IQM_CF_SCALE_SH_B__M 0x3 +-#define IQM_CF_SCALE_SH_B__PRE 0x0 +- +-#define IQM_CF_AMP__A 0x1860016 +-#define IQM_CF_AMP__W 14 +-#define IQM_CF_AMP__M 0x3FFF +-#define IQM_CF_AMP__PRE 0x0 +- +-#define IQM_CF_AMP_B__B 0 +-#define IQM_CF_AMP_B__W 14 +-#define IQM_CF_AMP_B__M 0x3FFF +-#define IQM_CF_AMP_B__PRE 0x0 +- +-#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +-#define IQM_CF_POW_MEAS_LEN__W 3 +-#define IQM_CF_POW_MEAS_LEN__M 0x7 +-#define IQM_CF_POW_MEAS_LEN__PRE 0x2 +- +-#define IQM_CF_POW_MEAS_LEN_B__B 0 +-#define IQM_CF_POW_MEAS_LEN_B__W 3 +-#define IQM_CF_POW_MEAS_LEN_B__M 0x7 +-#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2 +- +-#define IQM_CF_POW__A 0x1860018 +-#define IQM_CF_POW__W 16 +-#define IQM_CF_POW__M 0xFFFF +-#define IQM_CF_POW__PRE 0x2 +-#define IQM_CF_POW_B__B 0 +-#define IQM_CF_POW_B__W 16 +-#define IQM_CF_POW_B__M 0xFFFF +-#define IQM_CF_POW_B__PRE 0x2 +- +-#define IQM_CF_DS_ENA__A 0x1860019 +-#define IQM_CF_DS_ENA__W 3 +-#define IQM_CF_DS_ENA__M 0x7 +-#define IQM_CF_DS_ENA__PRE 0x4 +- +-#define IQM_CF_DS_ENA_ATV__B 0 +-#define IQM_CF_DS_ENA_ATV__W 1 +-#define IQM_CF_DS_ENA_ATV__M 0x1 +-#define IQM_CF_DS_ENA_ATV__PRE 0x0 +- +-#define IQM_CF_DS_ENA_QAM__B 1 +-#define IQM_CF_DS_ENA_QAM__W 1 +-#define IQM_CF_DS_ENA_QAM__M 0x2 +-#define IQM_CF_DS_ENA_QAM__PRE 0x0 +- +-#define IQM_CF_DS_ENA_VSB__B 2 +-#define IQM_CF_DS_ENA_VSB__W 1 +-#define IQM_CF_DS_ENA_VSB__M 0x4 +-#define IQM_CF_DS_ENA_VSB__PRE 0x4 +- +- +-#define IQM_CF_POW_UPD__A 0x186001A +-#define IQM_CF_POW_UPD__W 1 +-#define IQM_CF_POW_UPD__M 0x1 +-#define IQM_CF_POW_UPD__PRE 0x0 +-#define IQM_CF_TAP_RE0__A 0x1860020 +-#define IQM_CF_TAP_RE0__W 7 +-#define IQM_CF_TAP_RE0__M 0x7F +-#define IQM_CF_TAP_RE0__PRE 0x2 +-#define IQM_CF_TAP_RE0_B__B 0 +-#define IQM_CF_TAP_RE0_B__W 7 +-#define IQM_CF_TAP_RE0_B__M 0x7F +-#define IQM_CF_TAP_RE0_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE1__A 0x1860021 +-#define IQM_CF_TAP_RE1__W 7 +-#define IQM_CF_TAP_RE1__M 0x7F +-#define IQM_CF_TAP_RE1__PRE 0x2 +-#define IQM_CF_TAP_RE1_B__B 0 +-#define IQM_CF_TAP_RE1_B__W 7 +-#define IQM_CF_TAP_RE1_B__M 0x7F +-#define IQM_CF_TAP_RE1_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE2__A 0x1860022 +-#define IQM_CF_TAP_RE2__W 7 +-#define IQM_CF_TAP_RE2__M 0x7F +-#define IQM_CF_TAP_RE2__PRE 0x2 +-#define IQM_CF_TAP_RE2_B__B 0 +-#define IQM_CF_TAP_RE2_B__W 7 +-#define IQM_CF_TAP_RE2_B__M 0x7F +-#define IQM_CF_TAP_RE2_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE3__A 0x1860023 +-#define IQM_CF_TAP_RE3__W 7 +-#define IQM_CF_TAP_RE3__M 0x7F +-#define IQM_CF_TAP_RE3__PRE 0x2 +-#define IQM_CF_TAP_RE3_B__B 0 +-#define IQM_CF_TAP_RE3_B__W 7 +-#define IQM_CF_TAP_RE3_B__M 0x7F +-#define IQM_CF_TAP_RE3_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE4__A 0x1860024 +-#define IQM_CF_TAP_RE4__W 7 +-#define IQM_CF_TAP_RE4__M 0x7F +-#define IQM_CF_TAP_RE4__PRE 0x2 +-#define IQM_CF_TAP_RE4_B__B 0 +-#define IQM_CF_TAP_RE4_B__W 7 +-#define IQM_CF_TAP_RE4_B__M 0x7F +-#define IQM_CF_TAP_RE4_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE5__A 0x1860025 +-#define IQM_CF_TAP_RE5__W 7 +-#define IQM_CF_TAP_RE5__M 0x7F +-#define IQM_CF_TAP_RE5__PRE 0x2 +-#define IQM_CF_TAP_RE5_B__B 0 +-#define IQM_CF_TAP_RE5_B__W 7 +-#define IQM_CF_TAP_RE5_B__M 0x7F +-#define IQM_CF_TAP_RE5_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE6__A 0x1860026 +-#define IQM_CF_TAP_RE6__W 7 +-#define IQM_CF_TAP_RE6__M 0x7F +-#define IQM_CF_TAP_RE6__PRE 0x2 +-#define IQM_CF_TAP_RE6_B__B 0 +-#define IQM_CF_TAP_RE6_B__W 7 +-#define IQM_CF_TAP_RE6_B__M 0x7F +-#define IQM_CF_TAP_RE6_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE7__A 0x1860027 +-#define IQM_CF_TAP_RE7__W 9 +-#define IQM_CF_TAP_RE7__M 0x1FF +-#define IQM_CF_TAP_RE7__PRE 0x2 +-#define IQM_CF_TAP_RE7_B__B 0 +-#define IQM_CF_TAP_RE7_B__W 9 +-#define IQM_CF_TAP_RE7_B__M 0x1FF +-#define IQM_CF_TAP_RE7_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE8__A 0x1860028 +-#define IQM_CF_TAP_RE8__W 9 +-#define IQM_CF_TAP_RE8__M 0x1FF +-#define IQM_CF_TAP_RE8__PRE 0x2 +-#define IQM_CF_TAP_RE8_B__B 0 +-#define IQM_CF_TAP_RE8_B__W 9 +-#define IQM_CF_TAP_RE8_B__M 0x1FF +-#define IQM_CF_TAP_RE8_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE9__A 0x1860029 +-#define IQM_CF_TAP_RE9__W 9 +-#define IQM_CF_TAP_RE9__M 0x1FF +-#define IQM_CF_TAP_RE9__PRE 0x2 +-#define IQM_CF_TAP_RE9_B__B 0 +-#define IQM_CF_TAP_RE9_B__W 9 +-#define IQM_CF_TAP_RE9_B__M 0x1FF +-#define IQM_CF_TAP_RE9_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE10__A 0x186002A +-#define IQM_CF_TAP_RE10__W 9 +-#define IQM_CF_TAP_RE10__M 0x1FF +-#define IQM_CF_TAP_RE10__PRE 0x2 +-#define IQM_CF_TAP_RE10_B__B 0 +-#define IQM_CF_TAP_RE10_B__W 9 +-#define IQM_CF_TAP_RE10_B__M 0x1FF +-#define IQM_CF_TAP_RE10_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE11__A 0x186002B +-#define IQM_CF_TAP_RE11__W 9 +-#define IQM_CF_TAP_RE11__M 0x1FF +-#define IQM_CF_TAP_RE11__PRE 0x2 +-#define IQM_CF_TAP_RE11_B__B 0 +-#define IQM_CF_TAP_RE11_B__W 9 +-#define IQM_CF_TAP_RE11_B__M 0x1FF +-#define IQM_CF_TAP_RE11_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE12__A 0x186002C +-#define IQM_CF_TAP_RE12__W 9 +-#define IQM_CF_TAP_RE12__M 0x1FF +-#define IQM_CF_TAP_RE12__PRE 0x2 +-#define IQM_CF_TAP_RE12_B__B 0 +-#define IQM_CF_TAP_RE12_B__W 9 +-#define IQM_CF_TAP_RE12_B__M 0x1FF +-#define IQM_CF_TAP_RE12_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE13__A 0x186002D +-#define IQM_CF_TAP_RE13__W 9 +-#define IQM_CF_TAP_RE13__M 0x1FF +-#define IQM_CF_TAP_RE13__PRE 0x2 +-#define IQM_CF_TAP_RE13_B__B 0 +-#define IQM_CF_TAP_RE13_B__W 9 +-#define IQM_CF_TAP_RE13_B__M 0x1FF +-#define IQM_CF_TAP_RE13_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE14__A 0x186002E +-#define IQM_CF_TAP_RE14__W 9 +-#define IQM_CF_TAP_RE14__M 0x1FF +-#define IQM_CF_TAP_RE14__PRE 0x2 +-#define IQM_CF_TAP_RE14_B__B 0 +-#define IQM_CF_TAP_RE14_B__W 9 +-#define IQM_CF_TAP_RE14_B__M 0x1FF +-#define IQM_CF_TAP_RE14_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE15__A 0x186002F +-#define IQM_CF_TAP_RE15__W 9 +-#define IQM_CF_TAP_RE15__M 0x1FF +-#define IQM_CF_TAP_RE15__PRE 0x2 +-#define IQM_CF_TAP_RE15_B__B 0 +-#define IQM_CF_TAP_RE15_B__W 9 +-#define IQM_CF_TAP_RE15_B__M 0x1FF +-#define IQM_CF_TAP_RE15_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE16__A 0x1860030 +-#define IQM_CF_TAP_RE16__W 9 +-#define IQM_CF_TAP_RE16__M 0x1FF +-#define IQM_CF_TAP_RE16__PRE 0x2 +-#define IQM_CF_TAP_RE16_B__B 0 +-#define IQM_CF_TAP_RE16_B__W 9 +-#define IQM_CF_TAP_RE16_B__M 0x1FF +-#define IQM_CF_TAP_RE16_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE17__A 0x1860031 +-#define IQM_CF_TAP_RE17__W 9 +-#define IQM_CF_TAP_RE17__M 0x1FF +-#define IQM_CF_TAP_RE17__PRE 0x2 +-#define IQM_CF_TAP_RE17_B__B 0 +-#define IQM_CF_TAP_RE17_B__W 9 +-#define IQM_CF_TAP_RE17_B__M 0x1FF +-#define IQM_CF_TAP_RE17_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE18__A 0x1860032 +-#define IQM_CF_TAP_RE18__W 9 +-#define IQM_CF_TAP_RE18__M 0x1FF +-#define IQM_CF_TAP_RE18__PRE 0x2 +-#define IQM_CF_TAP_RE18_B__B 0 +-#define IQM_CF_TAP_RE18_B__W 9 +-#define IQM_CF_TAP_RE18_B__M 0x1FF +-#define IQM_CF_TAP_RE18_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE19__A 0x1860033 +-#define IQM_CF_TAP_RE19__W 9 +-#define IQM_CF_TAP_RE19__M 0x1FF +-#define IQM_CF_TAP_RE19__PRE 0x2 +-#define IQM_CF_TAP_RE19_B__B 0 +-#define IQM_CF_TAP_RE19_B__W 9 +-#define IQM_CF_TAP_RE19_B__M 0x1FF +-#define IQM_CF_TAP_RE19_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE20__A 0x1860034 +-#define IQM_CF_TAP_RE20__W 9 +-#define IQM_CF_TAP_RE20__M 0x1FF +-#define IQM_CF_TAP_RE20__PRE 0x2 +-#define IQM_CF_TAP_RE20_B__B 0 +-#define IQM_CF_TAP_RE20_B__W 9 +-#define IQM_CF_TAP_RE20_B__M 0x1FF +-#define IQM_CF_TAP_RE20_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE21__A 0x1860035 +-#define IQM_CF_TAP_RE21__W 11 +-#define IQM_CF_TAP_RE21__M 0x7FF +-#define IQM_CF_TAP_RE21__PRE 0x2 +-#define IQM_CF_TAP_RE21_B__B 0 +-#define IQM_CF_TAP_RE21_B__W 11 +-#define IQM_CF_TAP_RE21_B__M 0x7FF +-#define IQM_CF_TAP_RE21_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE22__A 0x1860036 +-#define IQM_CF_TAP_RE22__W 11 +-#define IQM_CF_TAP_RE22__M 0x7FF +-#define IQM_CF_TAP_RE22__PRE 0x2 +-#define IQM_CF_TAP_RE22_B__B 0 +-#define IQM_CF_TAP_RE22_B__W 11 +-#define IQM_CF_TAP_RE22_B__M 0x7FF +-#define IQM_CF_TAP_RE22_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE23__A 0x1860037 +-#define IQM_CF_TAP_RE23__W 11 +-#define IQM_CF_TAP_RE23__M 0x7FF +-#define IQM_CF_TAP_RE23__PRE 0x2 +-#define IQM_CF_TAP_RE23_B__B 0 +-#define IQM_CF_TAP_RE23_B__W 11 +-#define IQM_CF_TAP_RE23_B__M 0x7FF +-#define IQM_CF_TAP_RE23_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE24__A 0x1860038 +-#define IQM_CF_TAP_RE24__W 11 +-#define IQM_CF_TAP_RE24__M 0x7FF +-#define IQM_CF_TAP_RE24__PRE 0x2 +-#define IQM_CF_TAP_RE24_B__B 0 +-#define IQM_CF_TAP_RE24_B__W 11 +-#define IQM_CF_TAP_RE24_B__M 0x7FF +-#define IQM_CF_TAP_RE24_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE25__A 0x1860039 +-#define IQM_CF_TAP_RE25__W 11 +-#define IQM_CF_TAP_RE25__M 0x7FF +-#define IQM_CF_TAP_RE25__PRE 0x2 +-#define IQM_CF_TAP_RE25_B__B 0 +-#define IQM_CF_TAP_RE25_B__W 11 +-#define IQM_CF_TAP_RE25_B__M 0x7FF +-#define IQM_CF_TAP_RE25_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE26__A 0x186003A +-#define IQM_CF_TAP_RE26__W 11 +-#define IQM_CF_TAP_RE26__M 0x7FF +-#define IQM_CF_TAP_RE26__PRE 0x2 +-#define IQM_CF_TAP_RE26_B__B 0 +-#define IQM_CF_TAP_RE26_B__W 11 +-#define IQM_CF_TAP_RE26_B__M 0x7FF +-#define IQM_CF_TAP_RE26_B__PRE 0x2 +- +-#define IQM_CF_TAP_RE27__A 0x186003B +-#define IQM_CF_TAP_RE27__W 11 +-#define IQM_CF_TAP_RE27__M 0x7FF +-#define IQM_CF_TAP_RE27__PRE 0x2 +-#define IQM_CF_TAP_RE27_B__B 0 +-#define IQM_CF_TAP_RE27_B__W 11 +-#define IQM_CF_TAP_RE27_B__M 0x7FF +-#define IQM_CF_TAP_RE27_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM0__A 0x1860040 +-#define IQM_CF_TAP_IM0__W 7 +-#define IQM_CF_TAP_IM0__M 0x7F +-#define IQM_CF_TAP_IM0__PRE 0x2 +-#define IQM_CF_TAP_IM0_B__B 0 +-#define IQM_CF_TAP_IM0_B__W 7 +-#define IQM_CF_TAP_IM0_B__M 0x7F +-#define IQM_CF_TAP_IM0_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM1__A 0x1860041 +-#define IQM_CF_TAP_IM1__W 7 +-#define IQM_CF_TAP_IM1__M 0x7F +-#define IQM_CF_TAP_IM1__PRE 0x2 +-#define IQM_CF_TAP_IM1_B__B 0 +-#define IQM_CF_TAP_IM1_B__W 7 +-#define IQM_CF_TAP_IM1_B__M 0x7F +-#define IQM_CF_TAP_IM1_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM2__A 0x1860042 +-#define IQM_CF_TAP_IM2__W 7 +-#define IQM_CF_TAP_IM2__M 0x7F +-#define IQM_CF_TAP_IM2__PRE 0x2 +-#define IQM_CF_TAP_IM2_B__B 0 +-#define IQM_CF_TAP_IM2_B__W 7 +-#define IQM_CF_TAP_IM2_B__M 0x7F +-#define IQM_CF_TAP_IM2_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM3__A 0x1860043 +-#define IQM_CF_TAP_IM3__W 7 +-#define IQM_CF_TAP_IM3__M 0x7F +-#define IQM_CF_TAP_IM3__PRE 0x2 +-#define IQM_CF_TAP_IM3_B__B 0 +-#define IQM_CF_TAP_IM3_B__W 7 +-#define IQM_CF_TAP_IM3_B__M 0x7F +-#define IQM_CF_TAP_IM3_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM4__A 0x1860044 +-#define IQM_CF_TAP_IM4__W 7 +-#define IQM_CF_TAP_IM4__M 0x7F +-#define IQM_CF_TAP_IM4__PRE 0x2 +-#define IQM_CF_TAP_IM4_B__B 0 +-#define IQM_CF_TAP_IM4_B__W 7 +-#define IQM_CF_TAP_IM4_B__M 0x7F +-#define IQM_CF_TAP_IM4_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM5__A 0x1860045 +-#define IQM_CF_TAP_IM5__W 7 +-#define IQM_CF_TAP_IM5__M 0x7F +-#define IQM_CF_TAP_IM5__PRE 0x2 +-#define IQM_CF_TAP_IM5_B__B 0 +-#define IQM_CF_TAP_IM5_B__W 7 +-#define IQM_CF_TAP_IM5_B__M 0x7F +-#define IQM_CF_TAP_IM5_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM6__A 0x1860046 +-#define IQM_CF_TAP_IM6__W 7 +-#define IQM_CF_TAP_IM6__M 0x7F +-#define IQM_CF_TAP_IM6__PRE 0x2 +-#define IQM_CF_TAP_IM6_B__B 0 +-#define IQM_CF_TAP_IM6_B__W 7 +-#define IQM_CF_TAP_IM6_B__M 0x7F +-#define IQM_CF_TAP_IM6_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM7__A 0x1860047 +-#define IQM_CF_TAP_IM7__W 9 +-#define IQM_CF_TAP_IM7__M 0x1FF +-#define IQM_CF_TAP_IM7__PRE 0x2 +-#define IQM_CF_TAP_IM7_B__B 0 +-#define IQM_CF_TAP_IM7_B__W 9 +-#define IQM_CF_TAP_IM7_B__M 0x1FF +-#define IQM_CF_TAP_IM7_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM8__A 0x1860048 +-#define IQM_CF_TAP_IM8__W 9 +-#define IQM_CF_TAP_IM8__M 0x1FF +-#define IQM_CF_TAP_IM8__PRE 0x2 +-#define IQM_CF_TAP_IM8_B__B 0 +-#define IQM_CF_TAP_IM8_B__W 9 +-#define IQM_CF_TAP_IM8_B__M 0x1FF +-#define IQM_CF_TAP_IM8_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM9__A 0x1860049 +-#define IQM_CF_TAP_IM9__W 9 +-#define IQM_CF_TAP_IM9__M 0x1FF +-#define IQM_CF_TAP_IM9__PRE 0x2 +-#define IQM_CF_TAP_IM9_B__B 0 +-#define IQM_CF_TAP_IM9_B__W 9 +-#define IQM_CF_TAP_IM9_B__M 0x1FF +-#define IQM_CF_TAP_IM9_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM10__A 0x186004A +-#define IQM_CF_TAP_IM10__W 9 +-#define IQM_CF_TAP_IM10__M 0x1FF +-#define IQM_CF_TAP_IM10__PRE 0x2 +-#define IQM_CF_TAP_IM10_B__B 0 +-#define IQM_CF_TAP_IM10_B__W 9 +-#define IQM_CF_TAP_IM10_B__M 0x1FF +-#define IQM_CF_TAP_IM10_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM11__A 0x186004B +-#define IQM_CF_TAP_IM11__W 9 +-#define IQM_CF_TAP_IM11__M 0x1FF +-#define IQM_CF_TAP_IM11__PRE 0x2 +-#define IQM_CF_TAP_IM11_B__B 0 +-#define IQM_CF_TAP_IM11_B__W 9 +-#define IQM_CF_TAP_IM11_B__M 0x1FF +-#define IQM_CF_TAP_IM11_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM12__A 0x186004C +-#define IQM_CF_TAP_IM12__W 9 +-#define IQM_CF_TAP_IM12__M 0x1FF +-#define IQM_CF_TAP_IM12__PRE 0x2 +-#define IQM_CF_TAP_IM12_B__B 0 +-#define IQM_CF_TAP_IM12_B__W 9 +-#define IQM_CF_TAP_IM12_B__M 0x1FF +-#define IQM_CF_TAP_IM12_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM13__A 0x186004D +-#define IQM_CF_TAP_IM13__W 9 +-#define IQM_CF_TAP_IM13__M 0x1FF +-#define IQM_CF_TAP_IM13__PRE 0x2 +-#define IQM_CF_TAP_IM13_B__B 0 +-#define IQM_CF_TAP_IM13_B__W 9 +-#define IQM_CF_TAP_IM13_B__M 0x1FF +-#define IQM_CF_TAP_IM13_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM14__A 0x186004E +-#define IQM_CF_TAP_IM14__W 9 +-#define IQM_CF_TAP_IM14__M 0x1FF +-#define IQM_CF_TAP_IM14__PRE 0x2 +-#define IQM_CF_TAP_IM14_B__B 0 +-#define IQM_CF_TAP_IM14_B__W 9 +-#define IQM_CF_TAP_IM14_B__M 0x1FF +-#define IQM_CF_TAP_IM14_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM15__A 0x186004F +-#define IQM_CF_TAP_IM15__W 9 +-#define IQM_CF_TAP_IM15__M 0x1FF +-#define IQM_CF_TAP_IM15__PRE 0x2 +-#define IQM_CF_TAP_IM15_B__B 0 +-#define IQM_CF_TAP_IM15_B__W 9 +-#define IQM_CF_TAP_IM15_B__M 0x1FF +-#define IQM_CF_TAP_IM15_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM16__A 0x1860050 +-#define IQM_CF_TAP_IM16__W 9 +-#define IQM_CF_TAP_IM16__M 0x1FF +-#define IQM_CF_TAP_IM16__PRE 0x2 +-#define IQM_CF_TAP_IM16_B__B 0 +-#define IQM_CF_TAP_IM16_B__W 9 +-#define IQM_CF_TAP_IM16_B__M 0x1FF +-#define IQM_CF_TAP_IM16_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM17__A 0x1860051 +-#define IQM_CF_TAP_IM17__W 9 +-#define IQM_CF_TAP_IM17__M 0x1FF +-#define IQM_CF_TAP_IM17__PRE 0x2 +-#define IQM_CF_TAP_IM17_B__B 0 +-#define IQM_CF_TAP_IM17_B__W 9 +-#define IQM_CF_TAP_IM17_B__M 0x1FF +-#define IQM_CF_TAP_IM17_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM18__A 0x1860052 +-#define IQM_CF_TAP_IM18__W 9 +-#define IQM_CF_TAP_IM18__M 0x1FF +-#define IQM_CF_TAP_IM18__PRE 0x2 +-#define IQM_CF_TAP_IM18_B__B 0 +-#define IQM_CF_TAP_IM18_B__W 9 +-#define IQM_CF_TAP_IM18_B__M 0x1FF +-#define IQM_CF_TAP_IM18_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM19__A 0x1860053 +-#define IQM_CF_TAP_IM19__W 9 +-#define IQM_CF_TAP_IM19__M 0x1FF +-#define IQM_CF_TAP_IM19__PRE 0x2 +-#define IQM_CF_TAP_IM19_B__B 0 +-#define IQM_CF_TAP_IM19_B__W 9 +-#define IQM_CF_TAP_IM19_B__M 0x1FF +-#define IQM_CF_TAP_IM19_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM20__A 0x1860054 +-#define IQM_CF_TAP_IM20__W 9 +-#define IQM_CF_TAP_IM20__M 0x1FF +-#define IQM_CF_TAP_IM20__PRE 0x2 +-#define IQM_CF_TAP_IM20_B__B 0 +-#define IQM_CF_TAP_IM20_B__W 9 +-#define IQM_CF_TAP_IM20_B__M 0x1FF +-#define IQM_CF_TAP_IM20_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM21__A 0x1860055 +-#define IQM_CF_TAP_IM21__W 11 +-#define IQM_CF_TAP_IM21__M 0x7FF +-#define IQM_CF_TAP_IM21__PRE 0x2 +-#define IQM_CF_TAP_IM21_B__B 0 +-#define IQM_CF_TAP_IM21_B__W 11 +-#define IQM_CF_TAP_IM21_B__M 0x7FF +-#define IQM_CF_TAP_IM21_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM22__A 0x1860056 +-#define IQM_CF_TAP_IM22__W 11 +-#define IQM_CF_TAP_IM22__M 0x7FF +-#define IQM_CF_TAP_IM22__PRE 0x2 +-#define IQM_CF_TAP_IM22_B__B 0 +-#define IQM_CF_TAP_IM22_B__W 11 +-#define IQM_CF_TAP_IM22_B__M 0x7FF +-#define IQM_CF_TAP_IM22_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM23__A 0x1860057 +-#define IQM_CF_TAP_IM23__W 11 +-#define IQM_CF_TAP_IM23__M 0x7FF +-#define IQM_CF_TAP_IM23__PRE 0x2 +-#define IQM_CF_TAP_IM23_B__B 0 +-#define IQM_CF_TAP_IM23_B__W 11 +-#define IQM_CF_TAP_IM23_B__M 0x7FF +-#define IQM_CF_TAP_IM23_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM24__A 0x1860058 +-#define IQM_CF_TAP_IM24__W 11 +-#define IQM_CF_TAP_IM24__M 0x7FF +-#define IQM_CF_TAP_IM24__PRE 0x2 +-#define IQM_CF_TAP_IM24_B__B 0 +-#define IQM_CF_TAP_IM24_B__W 11 +-#define IQM_CF_TAP_IM24_B__M 0x7FF +-#define IQM_CF_TAP_IM24_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM25__A 0x1860059 +-#define IQM_CF_TAP_IM25__W 11 +-#define IQM_CF_TAP_IM25__M 0x7FF +-#define IQM_CF_TAP_IM25__PRE 0x2 +-#define IQM_CF_TAP_IM25_B__B 0 +-#define IQM_CF_TAP_IM25_B__W 11 +-#define IQM_CF_TAP_IM25_B__M 0x7FF +-#define IQM_CF_TAP_IM25_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM26__A 0x186005A +-#define IQM_CF_TAP_IM26__W 11 +-#define IQM_CF_TAP_IM26__M 0x7FF +-#define IQM_CF_TAP_IM26__PRE 0x2 +-#define IQM_CF_TAP_IM26_B__B 0 +-#define IQM_CF_TAP_IM26_B__W 11 +-#define IQM_CF_TAP_IM26_B__M 0x7FF +-#define IQM_CF_TAP_IM26_B__PRE 0x2 +- +-#define IQM_CF_TAP_IM27__A 0x186005B +-#define IQM_CF_TAP_IM27__W 11 +-#define IQM_CF_TAP_IM27__M 0x7FF +-#define IQM_CF_TAP_IM27__PRE 0x2 +-#define IQM_CF_TAP_IM27_B__B 0 +-#define IQM_CF_TAP_IM27_B__W 11 +-#define IQM_CF_TAP_IM27_B__M 0x7FF +-#define IQM_CF_TAP_IM27_B__PRE 0x2 +- +- +-#define IQM_CF_CLP_VAL__A 0x1860060 +-#define IQM_CF_CLP_VAL__W 9 +-#define IQM_CF_CLP_VAL__M 0x1FF +-#define IQM_CF_CLP_VAL__PRE 0x3C +- +-#define IQM_CF_DATATH__A 0x1860061 +-#define IQM_CF_DATATH__W 10 +-#define IQM_CF_DATATH__M 0x3FF +-#define IQM_CF_DATATH__PRE 0x180 +- +-#define IQM_CF_PKDTH__A 0x1860062 +-#define IQM_CF_PKDTH__W 5 +-#define IQM_CF_PKDTH__M 0x1F +-#define IQM_CF_PKDTH__PRE 0x1 +- +-#define IQM_CF_WND_LEN__A 0x1860063 +-#define IQM_CF_WND_LEN__W 4 +-#define IQM_CF_WND_LEN__M 0xF +-#define IQM_CF_WND_LEN__PRE 0x1 +- +-#define IQM_CF_DET_LCT__A 0x1860064 +-#define IQM_CF_DET_LCT__W 1 +-#define IQM_CF_DET_LCT__M 0x1 +-#define IQM_CF_DET_LCT__PRE 0x1 +- +-#define IQM_CF_SNS_LEN__A 0x1860065 +-#define IQM_CF_SNS_LEN__W 16 +-#define IQM_CF_SNS_LEN__M 0xFFFF +-#define IQM_CF_SNS_LEN__PRE 0x0 +- +-#define IQM_CF_SNS_SENSE__A 0x1860066 +-#define IQM_CF_SNS_SENSE__W 16 +-#define IQM_CF_SNS_SENSE__M 0xFFFF +-#define IQM_CF_SNS_SENSE__PRE 0x0 +- +-#define IQM_CF_BYPASSDET__A 0x1860067 +-#define IQM_CF_BYPASSDET__W 1 +-#define IQM_CF_BYPASSDET__M 0x1 +-#define IQM_CF_BYPASSDET__PRE 0x0 +- +-#define IQM_CF_UPD_ENA__A 0x1860068 +-#define IQM_CF_UPD_ENA__W 1 +-#define IQM_CF_UPD_ENA__M 0x1 +-#define IQM_CF_UPD_ENA__PRE 0x0 +-#define IQM_CF_UPD_ENA_DISABLE 0x0 +-#define IQM_CF_UPD_ENA_ENABLE 0x1 +- +- +- +-#define IQM_AF_COMM_EXEC__A 0x1870000 +-#define IQM_AF_COMM_EXEC__W 2 +-#define IQM_AF_COMM_EXEC__M 0x3 +-#define IQM_AF_COMM_EXEC__PRE 0x0 +-#define IQM_AF_COMM_EXEC_STOP 0x0 +-#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +-#define IQM_AF_COMM_EXEC_HOLD 0x2 +- +-#define IQM_AF_COMM_MB__A 0x1870002 +-#define IQM_AF_COMM_MB__W 8 +-#define IQM_AF_COMM_MB__M 0xFF +-#define IQM_AF_COMM_MB__PRE 0x0 +-#define IQM_AF_COMM_MB_CTL__B 0 +-#define IQM_AF_COMM_MB_CTL__W 1 +-#define IQM_AF_COMM_MB_CTL__M 0x1 +-#define IQM_AF_COMM_MB_CTL__PRE 0x0 +-#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +-#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +-#define IQM_AF_COMM_MB_OBS__B 1 +-#define IQM_AF_COMM_MB_OBS__W 1 +-#define IQM_AF_COMM_MB_OBS__M 0x2 +-#define IQM_AF_COMM_MB_OBS__PRE 0x0 +-#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +-#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +-#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +-#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +-#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +-#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +-#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +-#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +-#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +-#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +-#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +-#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14 +-#define IQM_AF_COMM_MB_MUX_OBS__B 5 +-#define IQM_AF_COMM_MB_MUX_OBS__W 3 +-#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +-#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +-#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +-#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +-#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +-#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +-#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 +-#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0 +- +-#define IQM_AF_COMM_INT_REQ__A 0x1870003 +-#define IQM_AF_COMM_INT_REQ__W 1 +-#define IQM_AF_COMM_INT_REQ__M 0x1 +-#define IQM_AF_COMM_INT_REQ__PRE 0x0 +-#define IQM_AF_COMM_INT_STA__A 0x1870005 +-#define IQM_AF_COMM_INT_STA__W 3 +-#define IQM_AF_COMM_INT_STA__M 0x7 +-#define IQM_AF_COMM_INT_STA__PRE 0x0 +-#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +-#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +-#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +-#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +-#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +-#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +-#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +-#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 +-#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2 +-#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1 +-#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4 +-#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0 +- +-#define IQM_AF_COMM_INT_MSK__A 0x1870006 +-#define IQM_AF_COMM_INT_MSK__W 3 +-#define IQM_AF_COMM_INT_MSK__M 0x7 +-#define IQM_AF_COMM_INT_MSK__PRE 0x0 +-#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +-#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +-#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +-#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +-#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +-#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +-#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +-#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 +-#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2 +-#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1 +-#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4 +-#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0 +- +-#define IQM_AF_COMM_INT_STM__A 0x1870007 +-#define IQM_AF_COMM_INT_STM__W 3 +-#define IQM_AF_COMM_INT_STM__M 0x7 +-#define IQM_AF_COMM_INT_STM__PRE 0x0 +-#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +-#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +-#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +-#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +-#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +-#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +-#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +-#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 +-#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2 +-#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1 +-#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4 +-#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0 +- +- +-#define IQM_AF_FDB_SEL__A 0x1870010 +-#define IQM_AF_FDB_SEL__W 2 +-#define IQM_AF_FDB_SEL__M 0x3 +-#define IQM_AF_FDB_SEL__PRE 0x0 +-#define IQM_AF_CLKNEG__A 0x1870012 +-#define IQM_AF_CLKNEG__W 2 +-#define IQM_AF_CLKNEG__M 0x3 +-#define IQM_AF_CLKNEG__PRE 0x0 +- +-#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +-#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +-#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +-#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +-#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +-#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 +- +-#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +-#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +-#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +-#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +-#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +-#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 +- +- +-#define IQM_AF_MON_IN_MUX__A 0x1870013 +-#define IQM_AF_MON_IN_MUX__W 2 +-#define IQM_AF_MON_IN_MUX__M 0x3 +-#define IQM_AF_MON_IN_MUX__PRE 0x0 +- +-#define IQM_AF_MON_IN5__A 0x1870014 +-#define IQM_AF_MON_IN5__W 10 +-#define IQM_AF_MON_IN5__M 0x3FF +-#define IQM_AF_MON_IN5__PRE 0x0 +- +-#define IQM_AF_MON_IN4__A 0x1870015 +-#define IQM_AF_MON_IN4__W 10 +-#define IQM_AF_MON_IN4__M 0x3FF +-#define IQM_AF_MON_IN4__PRE 0x0 +- +-#define IQM_AF_MON_IN3__A 0x1870016 +-#define IQM_AF_MON_IN3__W 10 +-#define IQM_AF_MON_IN3__M 0x3FF +-#define IQM_AF_MON_IN3__PRE 0x0 +- +-#define IQM_AF_MON_IN2__A 0x1870017 +-#define IQM_AF_MON_IN2__W 10 +-#define IQM_AF_MON_IN2__M 0x3FF +-#define IQM_AF_MON_IN2__PRE 0x0 +- +-#define IQM_AF_MON_IN1__A 0x1870018 +-#define IQM_AF_MON_IN1__W 10 +-#define IQM_AF_MON_IN1__M 0x3FF +-#define IQM_AF_MON_IN1__PRE 0x0 +- +-#define IQM_AF_MON_IN0__A 0x1870019 +-#define IQM_AF_MON_IN0__W 10 +-#define IQM_AF_MON_IN0__M 0x3FF +-#define IQM_AF_MON_IN0__PRE 0x0 +- +-#define IQM_AF_MON_IN_VAL__A 0x187001A +-#define IQM_AF_MON_IN_VAL__W 1 +-#define IQM_AF_MON_IN_VAL__M 0x1 +-#define IQM_AF_MON_IN_VAL__PRE 0x0 +- +-#define IQM_AF_START_LOCK__A 0x187001B +-#define IQM_AF_START_LOCK__W 1 +-#define IQM_AF_START_LOCK__M 0x1 +-#define IQM_AF_START_LOCK__PRE 0x0 +- +-#define IQM_AF_PHASE0__A 0x187001C +-#define IQM_AF_PHASE0__W 7 +-#define IQM_AF_PHASE0__M 0x7F +-#define IQM_AF_PHASE0__PRE 0x0 +- +-#define IQM_AF_PHASE1__A 0x187001D +-#define IQM_AF_PHASE1__W 7 +-#define IQM_AF_PHASE1__M 0x7F +-#define IQM_AF_PHASE1__PRE 0x0 +- +-#define IQM_AF_PHASE2__A 0x187001E +-#define IQM_AF_PHASE2__W 7 +-#define IQM_AF_PHASE2__M 0x7F +-#define IQM_AF_PHASE2__PRE 0x0 +- +-#define IQM_AF_SCU_PHASE__A 0x187001F +-#define IQM_AF_SCU_PHASE__W 2 +-#define IQM_AF_SCU_PHASE__M 0x3 +-#define IQM_AF_SCU_PHASE__PRE 0x0 +- +-#define IQM_AF_SYNC_SEL__A 0x1870020 +-#define IQM_AF_SYNC_SEL__W 2 +-#define IQM_AF_SYNC_SEL__M 0x3 +-#define IQM_AF_SYNC_SEL__PRE 0x0 +-#define IQM_AF_ADC_CONF__A 0x1870021 +-#define IQM_AF_ADC_CONF__W 4 +-#define IQM_AF_ADC_CONF__M 0xF +-#define IQM_AF_ADC_CONF__PRE 0x0 +- +-#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +-#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +-#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +-#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +-#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +-#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 +- +-#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +-#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +-#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +-#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +-#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +-#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 +- +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 +- +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +-#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 +- +- +-#define IQM_AF_CLP_CLIP__A 0x1870022 +-#define IQM_AF_CLP_CLIP__W 16 +-#define IQM_AF_CLP_CLIP__M 0xFFFF +-#define IQM_AF_CLP_CLIP__PRE 0x0 +- +-#define IQM_AF_CLP_LEN__A 0x1870023 +-#define IQM_AF_CLP_LEN__W 16 +-#define IQM_AF_CLP_LEN__M 0xFFFF +-#define IQM_AF_CLP_LEN__PRE 0x0 +- +-#define IQM_AF_CLP_TH__A 0x1870024 +-#define IQM_AF_CLP_TH__W 9 +-#define IQM_AF_CLP_TH__M 0x1FF +-#define IQM_AF_CLP_TH__PRE 0x0 +- +-#define IQM_AF_DCF_BYPASS__A 0x1870025 +-#define IQM_AF_DCF_BYPASS__W 1 +-#define IQM_AF_DCF_BYPASS__M 0x1 +-#define IQM_AF_DCF_BYPASS__PRE 0x0 +-#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +-#define IQM_AF_DCF_BYPASS_BYPASS 0x1 +- +- +-#define IQM_AF_SNS_LEN__A 0x1870026 +-#define IQM_AF_SNS_LEN__W 16 +-#define IQM_AF_SNS_LEN__M 0xFFFF +-#define IQM_AF_SNS_LEN__PRE 0x0 +- +-#define IQM_AF_SNS_SENSE__A 0x1870027 +-#define IQM_AF_SNS_SENSE__W 16 +-#define IQM_AF_SNS_SENSE__M 0xFFFF +-#define IQM_AF_SNS_SENSE__PRE 0x0 +- +-#define IQM_AF_AGC_IF__A 0x1870028 +-#define IQM_AF_AGC_IF__W 15 +-#define IQM_AF_AGC_IF__M 0x7FFF +-#define IQM_AF_AGC_IF__PRE 0x0 +- +-#define IQM_AF_AGC_RF__A 0x1870029 +-#define IQM_AF_AGC_RF__W 15 +-#define IQM_AF_AGC_RF__M 0x7FFF +-#define IQM_AF_AGC_RF__PRE 0x0 +- +-#define IQM_AF_PDREF__A 0x187002B +-#define IQM_AF_PDREF__W 5 +-#define IQM_AF_PDREF__M 0x1F +-#define IQM_AF_PDREF__PRE 0x0 +-#define IQM_AF_STDBY__A 0x187002C +-#define IQM_AF_STDBY__W 6 +-#define IQM_AF_STDBY__M 0x3F +-#define IQM_AF_STDBY__PRE 0x3E +- +-#define IQM_AF_STDBY_STDBY_BIAS__B 0 +-#define IQM_AF_STDBY_STDBY_BIAS__W 1 +-#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +-#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +-#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +-#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 +- +-#define IQM_AF_STDBY_STDBY_ADC__B 1 +-#define IQM_AF_STDBY_STDBY_ADC__W 1 +-#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +-#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2 +-#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0 +-#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 +- +-#define IQM_AF_STDBY_STDBY_AMP__B 2 +-#define IQM_AF_STDBY_STDBY_AMP__W 1 +-#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +-#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4 +-#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0 +-#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 +- +-#define IQM_AF_STDBY_STDBY_PD__B 3 +-#define IQM_AF_STDBY_STDBY_PD__W 1 +-#define IQM_AF_STDBY_STDBY_PD__M 0x8 +-#define IQM_AF_STDBY_STDBY_PD__PRE 0x8 +-#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0 +-#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 +- +-#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +-#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +-#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +-#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10 +-#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0 +-#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 +- +-#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +-#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +-#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +-#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20 +-#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0 +-#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 +- +- +-#define IQM_AF_AMUX__A 0x187002D +-#define IQM_AF_AMUX__W 1 +-#define IQM_AF_AMUX__M 0x1 +-#define IQM_AF_AMUX__PRE 0x0 +-#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +-#define IQM_AF_AMUX_SIGNAL2ADC 0x1 +- +- +-#define IQM_AF_TST_AFEMAIN__A 0x187002E +-#define IQM_AF_TST_AFEMAIN__W 8 +-#define IQM_AF_TST_AFEMAIN__M 0xFF +-#define IQM_AF_TST_AFEMAIN__PRE 0x0 +- +-#define IQM_AF_UPD_SEL__A 0x187002F +-#define IQM_AF_UPD_SEL__W 1 +-#define IQM_AF_UPD_SEL__M 0x1 +-#define IQM_AF_UPD_SEL__PRE 0x0 +- +-#define IQM_AF_INC_DATATH__A 0x1870030 +-#define IQM_AF_INC_DATATH__W 9 +-#define IQM_AF_INC_DATATH__M 0x1FF +-#define IQM_AF_INC_DATATH__PRE 0x180 +- +-#define IQM_AF_INC_PKDTH__A 0x1870031 +-#define IQM_AF_INC_PKDTH__W 5 +-#define IQM_AF_INC_PKDTH__M 0x1F +-#define IQM_AF_INC_PKDTH__PRE 0x3 +- +-#define IQM_AF_INC_WND_LEN__A 0x1870032 +-#define IQM_AF_INC_WND_LEN__W 4 +-#define IQM_AF_INC_WND_LEN__M 0xF +-#define IQM_AF_INC_WND_LEN__PRE 0xA +- +-#define IQM_AF_INC_DLY__A 0x1870033 +-#define IQM_AF_INC_DLY__W 7 +-#define IQM_AF_INC_DLY__M 0x7F +-#define IQM_AF_INC_DLY__PRE 0x14 +- +-#define IQM_AF_INC_LCT__A 0x1870034 +-#define IQM_AF_INC_LCT__W 1 +-#define IQM_AF_INC_LCT__M 0x1 +-#define IQM_AF_INC_LCT__PRE 0x1 +- +-#define IQM_AF_INC_CLP_VAL__A 0x1870035 +-#define IQM_AF_INC_CLP_VAL__W 9 +-#define IQM_AF_INC_CLP_VAL__M 0x1FF +-#define IQM_AF_INC_CLP_VAL__PRE 0x3C +- +-#define IQM_AF_INC_BYPASS__A 0x1870036 +-#define IQM_AF_INC_BYPASS__W 1 +-#define IQM_AF_INC_BYPASS__M 0x1 +-#define IQM_AF_INC_BYPASS__PRE 0x1 +- +-#define IQM_AF_INC_MODE_SEL__A 0x1870037 +-#define IQM_AF_INC_MODE_SEL__W 2 +-#define IQM_AF_INC_MODE_SEL__M 0x3 +-#define IQM_AF_INC_MODE_SEL__PRE 0x1 +- +-#define IQM_AF_INC_A_DLY__A 0x1870038 +-#define IQM_AF_INC_A_DLY__W 6 +-#define IQM_AF_INC_A_DLY__M 0x3F +-#define IQM_AF_INC_A_DLY__PRE 0xF +- +-#define IQM_AF_ISNS_LEN__A 0x1870039 +-#define IQM_AF_ISNS_LEN__W 16 +-#define IQM_AF_ISNS_LEN__M 0xFFFF +-#define IQM_AF_ISNS_LEN__PRE 0x0 +- +-#define IQM_AF_ISNS_SENSE__A 0x187003A +-#define IQM_AF_ISNS_SENSE__W 16 +-#define IQM_AF_ISNS_SENSE__M 0xFFFF +-#define IQM_AF_ISNS_SENSE__PRE 0x0 +-#define IQM_AF_CMP_STATE__A 0x187003B +-#define IQM_AF_CMP_STATE__W 7 +-#define IQM_AF_CMP_STATE__M 0x7F +-#define IQM_AF_CMP_STATE__PRE 0x0 +- +-#define IQM_AF_CMP_STATE_STATE__B 0 +-#define IQM_AF_CMP_STATE_STATE__W 2 +-#define IQM_AF_CMP_STATE_STATE__M 0x3 +-#define IQM_AF_CMP_STATE_STATE__PRE 0x0 +- +-#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2 +-#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1 +-#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4 +-#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0 +- +-#define IQM_AF_CMP_STATE_FILTERGAIN__B 3 +-#define IQM_AF_CMP_STATE_FILTERGAIN__W 2 +-#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18 +-#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0 +-#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0 +-#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8 +-#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10 +-#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18 +- +-#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5 +-#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1 +-#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20 +-#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0 +- +-#define IQM_AF_CMP_STATE_SEG64__B 6 +-#define IQM_AF_CMP_STATE_SEG64__W 1 +-#define IQM_AF_CMP_STATE_SEG64__M 0x40 +-#define IQM_AF_CMP_STATE_SEG64__PRE 0x0 +-#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0 +-#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40 +- +- +-#define IQM_AF_CMP_DC_OUT__A 0x187003C +-#define IQM_AF_CMP_DC_OUT__W 12 +-#define IQM_AF_CMP_DC_OUT__M 0xFFF +-#define IQM_AF_CMP_DC_OUT__PRE 0x0 +-#define IQM_AF_CMP_DC_IN__A 0x187003D +-#define IQM_AF_CMP_DC_IN__W 13 +-#define IQM_AF_CMP_DC_IN__M 0x1FFF +-#define IQM_AF_CMP_DC_IN__PRE 0x0 +- +-#define IQM_AF_CMP_DC_IN_DC__B 0 +-#define IQM_AF_CMP_DC_IN_DC__W 12 +-#define IQM_AF_CMP_DC_IN_DC__M 0xFFF +-#define IQM_AF_CMP_DC_IN_DC__PRE 0x0 +-#define IQM_AF_CMP_DC_IN_DC_EN__B 12 +-#define IQM_AF_CMP_DC_IN_DC_EN__W 1 +-#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000 +-#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0 +-#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0 +-#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000 +- +- +-#define IQM_AF_CMP_AMP__A 0x187003E +-#define IQM_AF_CMP_AMP__W 10 +-#define IQM_AF_CMP_AMP__M 0x3FF +-#define IQM_AF_CMP_AMP__PRE 0x0 +-#define IQM_AF_CMP_DN_AVG__A 0x187003F +-#define IQM_AF_CMP_DN_AVG__W 8 +-#define IQM_AF_CMP_DN_AVG__M 0xFF +-#define IQM_AF_CMP_DN_AVG__PRE 0x0 +- +-#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0 +-#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8 +-#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF +-#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0 +- +- +-#define IQM_AF_CMP_ACTIVE__A 0x1870040 +-#define IQM_AF_CMP_ACTIVE__W 1 +-#define IQM_AF_CMP_ACTIVE__M 0x1 +-#define IQM_AF_CMP_ACTIVE__PRE 0x0 +-#define IQM_AF_CMP_MEM0__A 0x1870080 +-#define IQM_AF_CMP_MEM0__W 13 +-#define IQM_AF_CMP_MEM0__M 0x1FFF +-#define IQM_AF_CMP_MEM0__PRE 0x0 +- +-#define IQM_AF_CMP_MEM0_COEF__B 0 +-#define IQM_AF_CMP_MEM0_COEF__W 13 +-#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM0_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM1__A 0x1870081 +-#define IQM_AF_CMP_MEM1__W 13 +-#define IQM_AF_CMP_MEM1__M 0x1FFF +-#define IQM_AF_CMP_MEM1__PRE 0x0 +- +-#define IQM_AF_CMP_MEM1_COEF__B 0 +-#define IQM_AF_CMP_MEM1_COEF__W 13 +-#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM1_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM2__A 0x1870082 +-#define IQM_AF_CMP_MEM2__W 13 +-#define IQM_AF_CMP_MEM2__M 0x1FFF +-#define IQM_AF_CMP_MEM2__PRE 0x0 +- +-#define IQM_AF_CMP_MEM2_COEF__B 0 +-#define IQM_AF_CMP_MEM2_COEF__W 13 +-#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM2_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM3__A 0x1870083 +-#define IQM_AF_CMP_MEM3__W 13 +-#define IQM_AF_CMP_MEM3__M 0x1FFF +-#define IQM_AF_CMP_MEM3__PRE 0x0 +- +-#define IQM_AF_CMP_MEM3_COEF__B 0 +-#define IQM_AF_CMP_MEM3_COEF__W 13 +-#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM3_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM4__A 0x1870084 +-#define IQM_AF_CMP_MEM4__W 13 +-#define IQM_AF_CMP_MEM4__M 0x1FFF +-#define IQM_AF_CMP_MEM4__PRE 0x0 +- +-#define IQM_AF_CMP_MEM4_COEF__B 0 +-#define IQM_AF_CMP_MEM4_COEF__W 13 +-#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM4_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM5__A 0x1870085 +-#define IQM_AF_CMP_MEM5__W 13 +-#define IQM_AF_CMP_MEM5__M 0x1FFF +-#define IQM_AF_CMP_MEM5__PRE 0x0 +- +-#define IQM_AF_CMP_MEM5_COEF__B 0 +-#define IQM_AF_CMP_MEM5_COEF__W 13 +-#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM5_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM6__A 0x1870086 +-#define IQM_AF_CMP_MEM6__W 13 +-#define IQM_AF_CMP_MEM6__M 0x1FFF +-#define IQM_AF_CMP_MEM6__PRE 0x0 +- +-#define IQM_AF_CMP_MEM6_COEF__B 0 +-#define IQM_AF_CMP_MEM6_COEF__W 13 +-#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM6_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM7__A 0x1870087 +-#define IQM_AF_CMP_MEM7__W 13 +-#define IQM_AF_CMP_MEM7__M 0x1FFF +-#define IQM_AF_CMP_MEM7__PRE 0x0 +- +-#define IQM_AF_CMP_MEM7_COEF__B 0 +-#define IQM_AF_CMP_MEM7_COEF__W 13 +-#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM7_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM8__A 0x1870088 +-#define IQM_AF_CMP_MEM8__W 13 +-#define IQM_AF_CMP_MEM8__M 0x1FFF +-#define IQM_AF_CMP_MEM8__PRE 0x0 +- +-#define IQM_AF_CMP_MEM8_COEF__B 0 +-#define IQM_AF_CMP_MEM8_COEF__W 13 +-#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM8_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM9__A 0x1870089 +-#define IQM_AF_CMP_MEM9__W 13 +-#define IQM_AF_CMP_MEM9__M 0x1FFF +-#define IQM_AF_CMP_MEM9__PRE 0x0 +- +-#define IQM_AF_CMP_MEM9_COEF__B 0 +-#define IQM_AF_CMP_MEM9_COEF__W 13 +-#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM9_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM10__A 0x187008A +-#define IQM_AF_CMP_MEM10__W 13 +-#define IQM_AF_CMP_MEM10__M 0x1FFF +-#define IQM_AF_CMP_MEM10__PRE 0x0 +- +-#define IQM_AF_CMP_MEM10_COEF__B 0 +-#define IQM_AF_CMP_MEM10_COEF__W 13 +-#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM10_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM11__A 0x187008B +-#define IQM_AF_CMP_MEM11__W 13 +-#define IQM_AF_CMP_MEM11__M 0x1FFF +-#define IQM_AF_CMP_MEM11__PRE 0x0 +- +-#define IQM_AF_CMP_MEM11_COEF__B 0 +-#define IQM_AF_CMP_MEM11_COEF__W 13 +-#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM11_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM12__A 0x187008C +-#define IQM_AF_CMP_MEM12__W 13 +-#define IQM_AF_CMP_MEM12__M 0x1FFF +-#define IQM_AF_CMP_MEM12__PRE 0x0 +- +-#define IQM_AF_CMP_MEM12_COEF__B 0 +-#define IQM_AF_CMP_MEM12_COEF__W 13 +-#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM12_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM13__A 0x187008D +-#define IQM_AF_CMP_MEM13__W 13 +-#define IQM_AF_CMP_MEM13__M 0x1FFF +-#define IQM_AF_CMP_MEM13__PRE 0x0 +- +-#define IQM_AF_CMP_MEM13_COEF__B 0 +-#define IQM_AF_CMP_MEM13_COEF__W 13 +-#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM13_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM14__A 0x187008E +-#define IQM_AF_CMP_MEM14__W 13 +-#define IQM_AF_CMP_MEM14__M 0x1FFF +-#define IQM_AF_CMP_MEM14__PRE 0x0 +- +-#define IQM_AF_CMP_MEM14_COEF__B 0 +-#define IQM_AF_CMP_MEM14_COEF__W 13 +-#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM14_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM15__A 0x187008F +-#define IQM_AF_CMP_MEM15__W 13 +-#define IQM_AF_CMP_MEM15__M 0x1FFF +-#define IQM_AF_CMP_MEM15__PRE 0x0 +- +-#define IQM_AF_CMP_MEM15_COEF__B 0 +-#define IQM_AF_CMP_MEM15_COEF__W 13 +-#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM15_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM16__A 0x1870090 +-#define IQM_AF_CMP_MEM16__W 13 +-#define IQM_AF_CMP_MEM16__M 0x1FFF +-#define IQM_AF_CMP_MEM16__PRE 0x0 +- +-#define IQM_AF_CMP_MEM16_COEF__B 0 +-#define IQM_AF_CMP_MEM16_COEF__W 13 +-#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM16_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM17__A 0x1870091 +-#define IQM_AF_CMP_MEM17__W 13 +-#define IQM_AF_CMP_MEM17__M 0x1FFF +-#define IQM_AF_CMP_MEM17__PRE 0x0 +- +-#define IQM_AF_CMP_MEM17_COEF__B 0 +-#define IQM_AF_CMP_MEM17_COEF__W 13 +-#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM17_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM18__A 0x1870092 +-#define IQM_AF_CMP_MEM18__W 13 +-#define IQM_AF_CMP_MEM18__M 0x1FFF +-#define IQM_AF_CMP_MEM18__PRE 0x0 +- +-#define IQM_AF_CMP_MEM18_COEF__B 0 +-#define IQM_AF_CMP_MEM18_COEF__W 13 +-#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM18_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM19__A 0x1870093 +-#define IQM_AF_CMP_MEM19__W 13 +-#define IQM_AF_CMP_MEM19__M 0x1FFF +-#define IQM_AF_CMP_MEM19__PRE 0x0 +- +-#define IQM_AF_CMP_MEM19_COEF__B 0 +-#define IQM_AF_CMP_MEM19_COEF__W 13 +-#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM19_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM20__A 0x1870094 +-#define IQM_AF_CMP_MEM20__W 13 +-#define IQM_AF_CMP_MEM20__M 0x1FFF +-#define IQM_AF_CMP_MEM20__PRE 0x0 +- +-#define IQM_AF_CMP_MEM20_COEF__B 0 +-#define IQM_AF_CMP_MEM20_COEF__W 13 +-#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM20_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM21__A 0x1870095 +-#define IQM_AF_CMP_MEM21__W 13 +-#define IQM_AF_CMP_MEM21__M 0x1FFF +-#define IQM_AF_CMP_MEM21__PRE 0x0 +- +-#define IQM_AF_CMP_MEM21_COEF__B 0 +-#define IQM_AF_CMP_MEM21_COEF__W 13 +-#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM21_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM22__A 0x1870096 +-#define IQM_AF_CMP_MEM22__W 13 +-#define IQM_AF_CMP_MEM22__M 0x1FFF +-#define IQM_AF_CMP_MEM22__PRE 0x0 +- +-#define IQM_AF_CMP_MEM22_COEF__B 0 +-#define IQM_AF_CMP_MEM22_COEF__W 13 +-#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM22_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM23__A 0x1870097 +-#define IQM_AF_CMP_MEM23__W 13 +-#define IQM_AF_CMP_MEM23__M 0x1FFF +-#define IQM_AF_CMP_MEM23__PRE 0x0 +- +-#define IQM_AF_CMP_MEM23_COEF__B 0 +-#define IQM_AF_CMP_MEM23_COEF__W 13 +-#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM23_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM24__A 0x1870098 +-#define IQM_AF_CMP_MEM24__W 13 +-#define IQM_AF_CMP_MEM24__M 0x1FFF +-#define IQM_AF_CMP_MEM24__PRE 0x0 +- +-#define IQM_AF_CMP_MEM24_COEF__B 0 +-#define IQM_AF_CMP_MEM24_COEF__W 13 +-#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM24_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM25__A 0x1870099 +-#define IQM_AF_CMP_MEM25__W 13 +-#define IQM_AF_CMP_MEM25__M 0x1FFF +-#define IQM_AF_CMP_MEM25__PRE 0x0 +- +-#define IQM_AF_CMP_MEM25_COEF__B 0 +-#define IQM_AF_CMP_MEM25_COEF__W 13 +-#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM25_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM26__A 0x187009A +-#define IQM_AF_CMP_MEM26__W 13 +-#define IQM_AF_CMP_MEM26__M 0x1FFF +-#define IQM_AF_CMP_MEM26__PRE 0x0 +- +-#define IQM_AF_CMP_MEM26_COEF__B 0 +-#define IQM_AF_CMP_MEM26_COEF__W 13 +-#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM26_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM27__A 0x187009B +-#define IQM_AF_CMP_MEM27__W 13 +-#define IQM_AF_CMP_MEM27__M 0x1FFF +-#define IQM_AF_CMP_MEM27__PRE 0x0 +- +-#define IQM_AF_CMP_MEM27_COEF__B 0 +-#define IQM_AF_CMP_MEM27_COEF__W 13 +-#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM27_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM28__A 0x187009C +-#define IQM_AF_CMP_MEM28__W 13 +-#define IQM_AF_CMP_MEM28__M 0x1FFF +-#define IQM_AF_CMP_MEM28__PRE 0x0 +- +-#define IQM_AF_CMP_MEM28_COEF__B 0 +-#define IQM_AF_CMP_MEM28_COEF__W 13 +-#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM28_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM29__A 0x187009D +-#define IQM_AF_CMP_MEM29__W 13 +-#define IQM_AF_CMP_MEM29__M 0x1FFF +-#define IQM_AF_CMP_MEM29__PRE 0x0 +- +-#define IQM_AF_CMP_MEM29_COEF__B 0 +-#define IQM_AF_CMP_MEM29_COEF__W 13 +-#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM29_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM30__A 0x187009E +-#define IQM_AF_CMP_MEM30__W 13 +-#define IQM_AF_CMP_MEM30__M 0x1FFF +-#define IQM_AF_CMP_MEM30__PRE 0x0 +- +-#define IQM_AF_CMP_MEM30_COEF__B 0 +-#define IQM_AF_CMP_MEM30_COEF__W 13 +-#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM30_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM31__A 0x187009F +-#define IQM_AF_CMP_MEM31__W 13 +-#define IQM_AF_CMP_MEM31__M 0x1FFF +-#define IQM_AF_CMP_MEM31__PRE 0x0 +- +-#define IQM_AF_CMP_MEM31_COEF__B 0 +-#define IQM_AF_CMP_MEM31_COEF__W 13 +-#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM31_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM32__A 0x18700A0 +-#define IQM_AF_CMP_MEM32__W 13 +-#define IQM_AF_CMP_MEM32__M 0x1FFF +-#define IQM_AF_CMP_MEM32__PRE 0x0 +- +-#define IQM_AF_CMP_MEM32_COEF__B 0 +-#define IQM_AF_CMP_MEM32_COEF__W 13 +-#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM32_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM33__A 0x18700A1 +-#define IQM_AF_CMP_MEM33__W 13 +-#define IQM_AF_CMP_MEM33__M 0x1FFF +-#define IQM_AF_CMP_MEM33__PRE 0x0 +- +-#define IQM_AF_CMP_MEM33_COEF__B 0 +-#define IQM_AF_CMP_MEM33_COEF__W 13 +-#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM33_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM34__A 0x18700A2 +-#define IQM_AF_CMP_MEM34__W 13 +-#define IQM_AF_CMP_MEM34__M 0x1FFF +-#define IQM_AF_CMP_MEM34__PRE 0x0 +- +-#define IQM_AF_CMP_MEM34_COEF__B 0 +-#define IQM_AF_CMP_MEM34_COEF__W 13 +-#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM34_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM35__A 0x18700A3 +-#define IQM_AF_CMP_MEM35__W 13 +-#define IQM_AF_CMP_MEM35__M 0x1FFF +-#define IQM_AF_CMP_MEM35__PRE 0x0 +- +-#define IQM_AF_CMP_MEM35_COEF__B 0 +-#define IQM_AF_CMP_MEM35_COEF__W 13 +-#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM35_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM36__A 0x18700A4 +-#define IQM_AF_CMP_MEM36__W 13 +-#define IQM_AF_CMP_MEM36__M 0x1FFF +-#define IQM_AF_CMP_MEM36__PRE 0x0 +- +-#define IQM_AF_CMP_MEM36_COEF__B 0 +-#define IQM_AF_CMP_MEM36_COEF__W 13 +-#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM36_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM37__A 0x18700A5 +-#define IQM_AF_CMP_MEM37__W 13 +-#define IQM_AF_CMP_MEM37__M 0x1FFF +-#define IQM_AF_CMP_MEM37__PRE 0x0 +- +-#define IQM_AF_CMP_MEM37_COEF__B 0 +-#define IQM_AF_CMP_MEM37_COEF__W 13 +-#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM37_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM38__A 0x18700A6 +-#define IQM_AF_CMP_MEM38__W 13 +-#define IQM_AF_CMP_MEM38__M 0x1FFF +-#define IQM_AF_CMP_MEM38__PRE 0x0 +- +-#define IQM_AF_CMP_MEM38_COEF__B 0 +-#define IQM_AF_CMP_MEM38_COEF__W 13 +-#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM38_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM39__A 0x18700A7 +-#define IQM_AF_CMP_MEM39__W 13 +-#define IQM_AF_CMP_MEM39__M 0x1FFF +-#define IQM_AF_CMP_MEM39__PRE 0x0 +- +-#define IQM_AF_CMP_MEM39_COEF__B 0 +-#define IQM_AF_CMP_MEM39_COEF__W 13 +-#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM39_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM40__A 0x18700A8 +-#define IQM_AF_CMP_MEM40__W 13 +-#define IQM_AF_CMP_MEM40__M 0x1FFF +-#define IQM_AF_CMP_MEM40__PRE 0x0 +- +-#define IQM_AF_CMP_MEM40_COEF__B 0 +-#define IQM_AF_CMP_MEM40_COEF__W 13 +-#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM40_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM41__A 0x18700A9 +-#define IQM_AF_CMP_MEM41__W 13 +-#define IQM_AF_CMP_MEM41__M 0x1FFF +-#define IQM_AF_CMP_MEM41__PRE 0x0 +- +-#define IQM_AF_CMP_MEM41_COEF__B 0 +-#define IQM_AF_CMP_MEM41_COEF__W 13 +-#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM41_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM42__A 0x18700AA +-#define IQM_AF_CMP_MEM42__W 13 +-#define IQM_AF_CMP_MEM42__M 0x1FFF +-#define IQM_AF_CMP_MEM42__PRE 0x0 +- +-#define IQM_AF_CMP_MEM42_COEF__B 0 +-#define IQM_AF_CMP_MEM42_COEF__W 13 +-#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM42_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM43__A 0x18700AB +-#define IQM_AF_CMP_MEM43__W 13 +-#define IQM_AF_CMP_MEM43__M 0x1FFF +-#define IQM_AF_CMP_MEM43__PRE 0x0 +- +-#define IQM_AF_CMP_MEM43_COEF__B 0 +-#define IQM_AF_CMP_MEM43_COEF__W 13 +-#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM43_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM44__A 0x18700AC +-#define IQM_AF_CMP_MEM44__W 13 +-#define IQM_AF_CMP_MEM44__M 0x1FFF +-#define IQM_AF_CMP_MEM44__PRE 0x0 +- +-#define IQM_AF_CMP_MEM44_COEF__B 0 +-#define IQM_AF_CMP_MEM44_COEF__W 13 +-#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM44_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM45__A 0x18700AD +-#define IQM_AF_CMP_MEM45__W 13 +-#define IQM_AF_CMP_MEM45__M 0x1FFF +-#define IQM_AF_CMP_MEM45__PRE 0x0 +- +-#define IQM_AF_CMP_MEM45_COEF__B 0 +-#define IQM_AF_CMP_MEM45_COEF__W 13 +-#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM45_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM46__A 0x18700AE +-#define IQM_AF_CMP_MEM46__W 13 +-#define IQM_AF_CMP_MEM46__M 0x1FFF +-#define IQM_AF_CMP_MEM46__PRE 0x0 +- +-#define IQM_AF_CMP_MEM46_COEF__B 0 +-#define IQM_AF_CMP_MEM46_COEF__W 13 +-#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM46_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM47__A 0x18700AF +-#define IQM_AF_CMP_MEM47__W 13 +-#define IQM_AF_CMP_MEM47__M 0x1FFF +-#define IQM_AF_CMP_MEM47__PRE 0x0 +- +-#define IQM_AF_CMP_MEM47_COEF__B 0 +-#define IQM_AF_CMP_MEM47_COEF__W 13 +-#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM47_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM48__A 0x18700B0 +-#define IQM_AF_CMP_MEM48__W 13 +-#define IQM_AF_CMP_MEM48__M 0x1FFF +-#define IQM_AF_CMP_MEM48__PRE 0x0 +- +-#define IQM_AF_CMP_MEM48_COEF__B 0 +-#define IQM_AF_CMP_MEM48_COEF__W 13 +-#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM48_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM49__A 0x18700B1 +-#define IQM_AF_CMP_MEM49__W 13 +-#define IQM_AF_CMP_MEM49__M 0x1FFF +-#define IQM_AF_CMP_MEM49__PRE 0x0 +- +-#define IQM_AF_CMP_MEM49_COEF__B 0 +-#define IQM_AF_CMP_MEM49_COEF__W 13 +-#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM49_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM50__A 0x18700B2 +-#define IQM_AF_CMP_MEM50__W 13 +-#define IQM_AF_CMP_MEM50__M 0x1FFF +-#define IQM_AF_CMP_MEM50__PRE 0x0 +- +-#define IQM_AF_CMP_MEM50_COEF__B 0 +-#define IQM_AF_CMP_MEM50_COEF__W 13 +-#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM50_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM51__A 0x18700B3 +-#define IQM_AF_CMP_MEM51__W 13 +-#define IQM_AF_CMP_MEM51__M 0x1FFF +-#define IQM_AF_CMP_MEM51__PRE 0x0 +- +-#define IQM_AF_CMP_MEM51_COEF__B 0 +-#define IQM_AF_CMP_MEM51_COEF__W 13 +-#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM51_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM52__A 0x18700B4 +-#define IQM_AF_CMP_MEM52__W 13 +-#define IQM_AF_CMP_MEM52__M 0x1FFF +-#define IQM_AF_CMP_MEM52__PRE 0x0 +- +-#define IQM_AF_CMP_MEM52_COEF__B 0 +-#define IQM_AF_CMP_MEM52_COEF__W 13 +-#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM52_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM53__A 0x18700B5 +-#define IQM_AF_CMP_MEM53__W 13 +-#define IQM_AF_CMP_MEM53__M 0x1FFF +-#define IQM_AF_CMP_MEM53__PRE 0x0 +- +-#define IQM_AF_CMP_MEM53_COEF__B 0 +-#define IQM_AF_CMP_MEM53_COEF__W 13 +-#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM53_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM54__A 0x18700B6 +-#define IQM_AF_CMP_MEM54__W 13 +-#define IQM_AF_CMP_MEM54__M 0x1FFF +-#define IQM_AF_CMP_MEM54__PRE 0x0 +- +-#define IQM_AF_CMP_MEM54_COEF__B 0 +-#define IQM_AF_CMP_MEM54_COEF__W 13 +-#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM54_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM55__A 0x18700B7 +-#define IQM_AF_CMP_MEM55__W 13 +-#define IQM_AF_CMP_MEM55__M 0x1FFF +-#define IQM_AF_CMP_MEM55__PRE 0x0 +- +-#define IQM_AF_CMP_MEM55_COEF__B 0 +-#define IQM_AF_CMP_MEM55_COEF__W 13 +-#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM55_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM56__A 0x18700B8 +-#define IQM_AF_CMP_MEM56__W 13 +-#define IQM_AF_CMP_MEM56__M 0x1FFF +-#define IQM_AF_CMP_MEM56__PRE 0x0 +- +-#define IQM_AF_CMP_MEM56_COEF__B 0 +-#define IQM_AF_CMP_MEM56_COEF__W 13 +-#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM56_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM57__A 0x18700B9 +-#define IQM_AF_CMP_MEM57__W 13 +-#define IQM_AF_CMP_MEM57__M 0x1FFF +-#define IQM_AF_CMP_MEM57__PRE 0x0 +- +-#define IQM_AF_CMP_MEM57_COEF__B 0 +-#define IQM_AF_CMP_MEM57_COEF__W 13 +-#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM57_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM58__A 0x18700BA +-#define IQM_AF_CMP_MEM58__W 13 +-#define IQM_AF_CMP_MEM58__M 0x1FFF +-#define IQM_AF_CMP_MEM58__PRE 0x0 +- +-#define IQM_AF_CMP_MEM58_COEF__B 0 +-#define IQM_AF_CMP_MEM58_COEF__W 13 +-#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM58_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM59__A 0x18700BB +-#define IQM_AF_CMP_MEM59__W 13 +-#define IQM_AF_CMP_MEM59__M 0x1FFF +-#define IQM_AF_CMP_MEM59__PRE 0x0 +- +-#define IQM_AF_CMP_MEM59_COEF__B 0 +-#define IQM_AF_CMP_MEM59_COEF__W 13 +-#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM59_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM60__A 0x18700BC +-#define IQM_AF_CMP_MEM60__W 13 +-#define IQM_AF_CMP_MEM60__M 0x1FFF +-#define IQM_AF_CMP_MEM60__PRE 0x0 +- +-#define IQM_AF_CMP_MEM60_COEF__B 0 +-#define IQM_AF_CMP_MEM60_COEF__W 13 +-#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM60_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM61__A 0x18700BD +-#define IQM_AF_CMP_MEM61__W 13 +-#define IQM_AF_CMP_MEM61__M 0x1FFF +-#define IQM_AF_CMP_MEM61__PRE 0x0 +- +-#define IQM_AF_CMP_MEM61_COEF__B 0 +-#define IQM_AF_CMP_MEM61_COEF__W 13 +-#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM61_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM62__A 0x18700BE +-#define IQM_AF_CMP_MEM62__W 13 +-#define IQM_AF_CMP_MEM62__M 0x1FFF +-#define IQM_AF_CMP_MEM62__PRE 0x0 +- +-#define IQM_AF_CMP_MEM62_COEF__B 0 +-#define IQM_AF_CMP_MEM62_COEF__W 13 +-#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM62_COEF__PRE 0x0 +- +-#define IQM_AF_CMP_MEM63__A 0x18700BF +-#define IQM_AF_CMP_MEM63__W 13 +-#define IQM_AF_CMP_MEM63__M 0x1FFF +-#define IQM_AF_CMP_MEM63__PRE 0x0 +- +-#define IQM_AF_CMP_MEM63_COEF__B 0 +-#define IQM_AF_CMP_MEM63_COEF__W 13 +-#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF +-#define IQM_AF_CMP_MEM63_COEF__PRE 0x0 +- +- +- +-#define IQM_RT_RAM__A 0x1880000 +- +-#define IQM_RT_RAM_DLY__B 0 +-#define IQM_RT_RAM_DLY__W 13 +-#define IQM_RT_RAM_DLY__M 0x1FFF +-#define IQM_RT_RAM_DLY__PRE 0x0 +- +- +- +- +- +-#define OFDM_CE_COMM_EXEC__A 0x2C00000 +-#define OFDM_CE_COMM_EXEC__W 3 +-#define OFDM_CE_COMM_EXEC__M 0x7 +-#define OFDM_CE_COMM_EXEC__PRE 0x0 +-#define OFDM_CE_COMM_EXEC_STOP 0x0 +-#define OFDM_CE_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_CE_COMM_EXEC_HOLD 0x2 +-#define OFDM_CE_COMM_EXEC_STEP 0x3 +-#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4 +-#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6 +- +-#define OFDM_CE_COMM_STATE__A 0x2C00001 +-#define OFDM_CE_COMM_STATE__W 16 +-#define OFDM_CE_COMM_STATE__M 0xFFFF +-#define OFDM_CE_COMM_STATE__PRE 0x0 +-#define OFDM_CE_COMM_MB__A 0x2C00002 +-#define OFDM_CE_COMM_MB__W 16 +-#define OFDM_CE_COMM_MB__M 0xFFFF +-#define OFDM_CE_COMM_MB__PRE 0x0 +-#define OFDM_CE_COMM_INT_REQ__A 0x2C00004 +-#define OFDM_CE_COMM_INT_REQ__W 16 +-#define OFDM_CE_COMM_INT_REQ__M 0xFFFF +-#define OFDM_CE_COMM_INT_REQ__PRE 0x0 +-#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2 +-#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1 +-#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4 +-#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0 +- +-#define OFDM_CE_COMM_INT_STA__A 0x2C00005 +-#define OFDM_CE_COMM_INT_STA__W 16 +-#define OFDM_CE_COMM_INT_STA__M 0xFFFF +-#define OFDM_CE_COMM_INT_STA__PRE 0x0 +-#define OFDM_CE_COMM_INT_MSK__A 0x2C00006 +-#define OFDM_CE_COMM_INT_MSK__W 16 +-#define OFDM_CE_COMM_INT_MSK__M 0xFFFF +-#define OFDM_CE_COMM_INT_MSK__PRE 0x0 +-#define OFDM_CE_COMM_INT_STM__A 0x2C00007 +-#define OFDM_CE_COMM_INT_STM__W 16 +-#define OFDM_CE_COMM_INT_STM__M 0xFFFF +-#define OFDM_CE_COMM_INT_STM__PRE 0x0 +-#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0 +-#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16 +-#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF +-#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0 +- +- +- +-#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000 +-#define OFDM_CE_TOP_COMM_EXEC__W 3 +-#define OFDM_CE_TOP_COMM_EXEC__M 0x7 +-#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0 +-#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0 +-#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2 +-#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3 +- +-#define OFDM_CE_TOP_COMM_MB__A 0x2C10002 +-#define OFDM_CE_TOP_COMM_MB__W 4 +-#define OFDM_CE_TOP_COMM_MB__M 0xF +-#define OFDM_CE_TOP_COMM_MB__PRE 0x0 +-#define OFDM_CE_TOP_COMM_MB_CTL__B 0 +-#define OFDM_CE_TOP_COMM_MB_CTL__W 1 +-#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1 +-#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0 +-#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0 +-#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1 +-#define OFDM_CE_TOP_COMM_MB_OBS__B 1 +-#define OFDM_CE_TOP_COMM_MB_OBS__W 1 +-#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2 +-#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0 +-#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0 +-#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2 +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2 +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2 +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0 +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0 +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4 +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8 +-#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC +- +-#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004 +-#define OFDM_CE_TOP_COMM_INT_REQ__W 1 +-#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1 +-#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005 +-#define OFDM_CE_TOP_COMM_INT_STA__W 3 +-#define OFDM_CE_TOP_COMM_INT_STA__M 0x7 +-#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4 +-#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0 +- +-#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006 +-#define OFDM_CE_TOP_COMM_INT_MSK__W 3 +-#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7 +-#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4 +-#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0 +- +-#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007 +-#define OFDM_CE_TOP_COMM_INT_STM__W 3 +-#define OFDM_CE_TOP_COMM_INT_STM__M 0x7 +-#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4 +-#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0 +- +- +-#define OFDM_CE_TOP_MODE_2K__A 0x2C10010 +-#define OFDM_CE_TOP_MODE_2K__W 1 +-#define OFDM_CE_TOP_MODE_2K__M 0x1 +-#define OFDM_CE_TOP_MODE_2K__PRE 0x0 +- +-#define OFDM_CE_TOP_TAPSET__A 0x2C10011 +-#define OFDM_CE_TOP_TAPSET__W 4 +-#define OFDM_CE_TOP_TAPSET__M 0xF +-#define OFDM_CE_TOP_TAPSET__PRE 0x1 +-#define OFDM_CE_TOP_AVG_POW__A 0x2C10012 +-#define OFDM_CE_TOP_AVG_POW__W 8 +-#define OFDM_CE_TOP_AVG_POW__M 0xFF +-#define OFDM_CE_TOP_AVG_POW__PRE 0x65 +-#define OFDM_CE_TOP_MAX_POW__A 0x2C10013 +-#define OFDM_CE_TOP_MAX_POW__W 8 +-#define OFDM_CE_TOP_MAX_POW__M 0xFF +-#define OFDM_CE_TOP_MAX_POW__PRE 0x80 +-#define OFDM_CE_TOP_ATT__A 0x2C10014 +-#define OFDM_CE_TOP_ATT__W 8 +-#define OFDM_CE_TOP_ATT__M 0xFF +-#define OFDM_CE_TOP_ATT__PRE 0x70 +-#define OFDM_CE_TOP_NRED__A 0x2C10015 +-#define OFDM_CE_TOP_NRED__W 6 +-#define OFDM_CE_TOP_NRED__M 0x3F +-#define OFDM_CE_TOP_NRED__PRE 0x9 +- +-#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020 +-#define OFDM_CE_TOP_PU_SIGN__W 1 +-#define OFDM_CE_TOP_PU_SIGN__M 0x1 +-#define OFDM_CE_TOP_PU_SIGN__PRE 0x0 +- +-#define OFDM_CE_TOP_PU_MIX__A 0x2C10021 +-#define OFDM_CE_TOP_PU_MIX__W 1 +-#define OFDM_CE_TOP_PU_MIX__M 0x1 +-#define OFDM_CE_TOP_PU_MIX__PRE 0x0 +-#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030 +-#define OFDM_CE_TOP_PB_PILOT_REQ__W 15 +-#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF +-#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0 +-#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12 +-#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3 +-#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +-#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0 +-#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0 +-#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12 +-#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF +-#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0 +- +- +-#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031 +-#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1 +-#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1 +-#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0 +- +-#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032 +-#define OFDM_CE_TOP_PB_FREEZE__W 1 +-#define OFDM_CE_TOP_PB_FREEZE__M 0x1 +-#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0 +- +-#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038 +-#define OFDM_CE_TOP_PB_PILOT_EXP__W 4 +-#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF +-#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0 +- +-#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039 +-#define OFDM_CE_TOP_PB_PILOT_REAL__W 10 +-#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF +-#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0 +- +-#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A +-#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10 +-#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF +-#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0 +- +-#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B +-#define OFDM_CE_TOP_PB_SMBNR__W 5 +-#define OFDM_CE_TOP_PB_SMBNR__M 0x1F +-#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040 +-#define OFDM_CE_TOP_NE_PILOT_REQ__W 12 +-#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF +-#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 +-#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0 +- +- +-#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042 +-#define OFDM_CE_TOP_NE_PILOT_DATA__W 10 +-#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF +-#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0 +-#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043 +-#define OFDM_CE_TOP_NE_ERR_SELECT__W 5 +-#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F +-#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7 +- +-#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4 +-#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1 +-#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10 +-#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3 +-#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1 +-#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8 +-#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2 +-#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1 +-#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4 +-#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4 +- +-#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1 +-#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1 +-#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2 +-#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2 +- +-#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0 +-#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1 +-#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1 +-#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1 +- +- +-#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044 +-#define OFDM_CE_TOP_NE_TD_CAL__W 9 +-#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF +-#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8 +- +-#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045 +-#define OFDM_CE_TOP_NE_FD_CAL__W 9 +-#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF +-#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9 +- +-#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046 +-#define OFDM_CE_TOP_NE_MIXAVG__W 3 +-#define OFDM_CE_TOP_NE_MIXAVG__M 0x7 +-#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6 +- +-#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047 +-#define OFDM_CE_TOP_NE_NUPD_OFS__W 4 +-#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF +-#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4 +-#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048 +-#define OFDM_CE_TOP_NE_TD_POW__W 15 +-#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF +-#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10 +-#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5 +-#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00 +-#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0 +-#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10 +-#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF +-#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049 +-#define OFDM_CE_TOP_NE_FD_POW__W 15 +-#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF +-#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10 +-#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5 +-#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00 +-#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0 +-#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10 +-#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF +-#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0 +- +- +-#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A +-#define OFDM_CE_TOP_NE_NEXP_AVG__W 8 +-#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF +-#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B +-#define OFDM_CE_TOP_NE_OFFSET__W 9 +-#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF +-#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0 +- +-#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C +-#define OFDM_CE_TOP_NE_NUPD_TRH__W 5 +-#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F +-#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14 +- +-#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050 +-#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8 +-#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF +-#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051 +-#define OFDM_CE_TOP_PE_TIMESHIFT__W 14 +-#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF +-#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052 +-#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16 +-#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF +-#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053 +-#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16 +-#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF +-#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054 +-#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16 +-#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF +-#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055 +-#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16 +-#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF +-#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056 +-#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16 +-#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF +-#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057 +-#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16 +-#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF +-#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058 +-#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16 +-#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF +-#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059 +-#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16 +-#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF +-#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A +-#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5 +-#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F +-#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0 +- +-#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B +-#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5 +-#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F +-#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060 +-#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1 +-#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1 +-#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061 +-#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1 +-#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1 +-#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064 +-#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10 +-#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF +-#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100 +- +-#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065 +-#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1 +-#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1 +-#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066 +-#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5 +-#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F +-#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE +- +-#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067 +-#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10 +-#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF +-#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068 +-#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10 +-#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF +-#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069 +-#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1 +-#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1 +-#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A +-#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5 +-#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F +-#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA +- +-#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B +-#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10 +-#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF +-#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0 +-#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C +-#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15 +-#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF +-#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10 +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5 +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0 +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10 +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF +-#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15 +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF +-#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15 +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10 +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5 +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0 +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10 +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF +-#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15 +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10 +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5 +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0 +- +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0 +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10 +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF +-#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0 +- +- +-#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072 +-#define OFDM_CE_TOP_TI_SYM_CNT__W 6 +-#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F +-#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20 +- +-#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073 +-#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1 +-#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1 +-#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1 +- +-#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074 +-#define OFDM_CE_TOP_TI_SHIFT__W 2 +-#define OFDM_CE_TOP_TI_SHIFT__M 0x3 +-#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0 +- +-#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075 +-#define OFDM_CE_TOP_TI_SLOW__W 1 +-#define OFDM_CE_TOP_TI_SLOW__M 0x1 +-#define OFDM_CE_TOP_TI_SLOW__PRE 0x1 +- +-#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076 +-#define OFDM_CE_TOP_TI_MGAIN__W 8 +-#define OFDM_CE_TOP_TI_MGAIN__M 0xFF +-#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0 +- +-#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077 +-#define OFDM_CE_TOP_TI_ACCU1__W 8 +-#define OFDM_CE_TOP_TI_ACCU1__M 0xFF +-#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0 +- +-#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0 +-#define OFDM_CE_TOP_NI_PER_LEFT__W 5 +-#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F +-#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE +- +-#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1 +-#define OFDM_CE_TOP_NI_PER_RIGHT__W 5 +-#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F +-#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7 +- +-#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2 +-#define OFDM_CE_TOP_NI_POS_LR__W 9 +-#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF +-#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0 +- +-#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090 +-#define OFDM_CE_TOP_FI_SHT_INCR__W 9 +-#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF +-#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E +- +-#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091 +-#define OFDM_CE_TOP_FI_EXP_NORM__W 4 +-#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF +-#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC +- +-#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092 +-#define OFDM_CE_TOP_FI_SUPR_VAL__W 1 +-#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1 +-#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0 +- +-#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0 +-#define OFDM_CE_TOP_IR_INPUTSEL__W 1 +-#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1 +-#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0 +- +-#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1 +-#define OFDM_CE_TOP_IR_STARTPOS__W 8 +-#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF +-#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0 +- +-#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2 +-#define OFDM_CE_TOP_IR_NEXP_THRES__W 8 +-#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF +-#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF +- +-#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3 +-#define OFDM_CE_TOP_IR_LENGTH__W 4 +-#define OFDM_CE_TOP_IR_LENGTH__M 0xF +-#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9 +- +-#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4 +-#define OFDM_CE_TOP_IR_FREQ__W 11 +-#define OFDM_CE_TOP_IR_FREQ__M 0x7FF +-#define OFDM_CE_TOP_IR_FREQ__PRE 0x0 +- +-#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5 +-#define OFDM_CE_TOP_IR_FREQINC__W 11 +-#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF +-#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4 +- +-#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6 +-#define OFDM_CE_TOP_IR_KAISINC__W 15 +-#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF +-#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100 +- +-#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7 +-#define OFDM_CE_TOP_IR_CTL__W 3 +-#define OFDM_CE_TOP_IR_CTL__M 0x7 +-#define OFDM_CE_TOP_IR_CTL__PRE 0x0 +- +-#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8 +-#define OFDM_CE_TOP_IR_REAL__W 16 +-#define OFDM_CE_TOP_IR_REAL__M 0xFFFF +-#define OFDM_CE_TOP_IR_REAL__PRE 0x0 +- +-#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9 +-#define OFDM_CE_TOP_IR_IMAG__W 16 +-#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF +-#define OFDM_CE_TOP_IR_IMAG__PRE 0x0 +- +-#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA +-#define OFDM_CE_TOP_IR_INDEX__W 12 +-#define OFDM_CE_TOP_IR_INDEX__M 0xFFF +-#define OFDM_CE_TOP_IR_INDEX__PRE 0x0 +- +- +- +-#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000 +-#define OFDM_CE_FR_COMM_EXEC__W 3 +-#define OFDM_CE_FR_COMM_EXEC__M 0x7 +-#define OFDM_CE_FR_COMM_EXEC__PRE 0x0 +-#define OFDM_CE_FR_COMM_EXEC_STOP 0x0 +-#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2 +-#define OFDM_CE_FR_COMM_EXEC_STEP 0x3 +- +- +-#define OFDM_CE_FR_TREAL00__A 0x2C20010 +-#define OFDM_CE_FR_TREAL00__W 11 +-#define OFDM_CE_FR_TREAL00__M 0x7FF +-#define OFDM_CE_FR_TREAL00__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG00__A 0x2C20011 +-#define OFDM_CE_FR_TIMAG00__W 11 +-#define OFDM_CE_FR_TIMAG00__M 0x7FF +-#define OFDM_CE_FR_TIMAG00__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL01__A 0x2C20012 +-#define OFDM_CE_FR_TREAL01__W 11 +-#define OFDM_CE_FR_TREAL01__M 0x7FF +-#define OFDM_CE_FR_TREAL01__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG01__A 0x2C20013 +-#define OFDM_CE_FR_TIMAG01__W 11 +-#define OFDM_CE_FR_TIMAG01__M 0x7FF +-#define OFDM_CE_FR_TIMAG01__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL02__A 0x2C20014 +-#define OFDM_CE_FR_TREAL02__W 11 +-#define OFDM_CE_FR_TREAL02__M 0x7FF +-#define OFDM_CE_FR_TREAL02__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG02__A 0x2C20015 +-#define OFDM_CE_FR_TIMAG02__W 11 +-#define OFDM_CE_FR_TIMAG02__M 0x7FF +-#define OFDM_CE_FR_TIMAG02__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL03__A 0x2C20016 +-#define OFDM_CE_FR_TREAL03__W 11 +-#define OFDM_CE_FR_TREAL03__M 0x7FF +-#define OFDM_CE_FR_TREAL03__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG03__A 0x2C20017 +-#define OFDM_CE_FR_TIMAG03__W 11 +-#define OFDM_CE_FR_TIMAG03__M 0x7FF +-#define OFDM_CE_FR_TIMAG03__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL04__A 0x2C20018 +-#define OFDM_CE_FR_TREAL04__W 11 +-#define OFDM_CE_FR_TREAL04__M 0x7FF +-#define OFDM_CE_FR_TREAL04__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG04__A 0x2C20019 +-#define OFDM_CE_FR_TIMAG04__W 11 +-#define OFDM_CE_FR_TIMAG04__M 0x7FF +-#define OFDM_CE_FR_TIMAG04__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL05__A 0x2C2001A +-#define OFDM_CE_FR_TREAL05__W 11 +-#define OFDM_CE_FR_TREAL05__M 0x7FF +-#define OFDM_CE_FR_TREAL05__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG05__A 0x2C2001B +-#define OFDM_CE_FR_TIMAG05__W 11 +-#define OFDM_CE_FR_TIMAG05__M 0x7FF +-#define OFDM_CE_FR_TIMAG05__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL06__A 0x2C2001C +-#define OFDM_CE_FR_TREAL06__W 11 +-#define OFDM_CE_FR_TREAL06__M 0x7FF +-#define OFDM_CE_FR_TREAL06__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG06__A 0x2C2001D +-#define OFDM_CE_FR_TIMAG06__W 11 +-#define OFDM_CE_FR_TIMAG06__M 0x7FF +-#define OFDM_CE_FR_TIMAG06__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL07__A 0x2C2001E +-#define OFDM_CE_FR_TREAL07__W 11 +-#define OFDM_CE_FR_TREAL07__M 0x7FF +-#define OFDM_CE_FR_TREAL07__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG07__A 0x2C2001F +-#define OFDM_CE_FR_TIMAG07__W 11 +-#define OFDM_CE_FR_TIMAG07__M 0x7FF +-#define OFDM_CE_FR_TIMAG07__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL08__A 0x2C20020 +-#define OFDM_CE_FR_TREAL08__W 11 +-#define OFDM_CE_FR_TREAL08__M 0x7FF +-#define OFDM_CE_FR_TREAL08__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG08__A 0x2C20021 +-#define OFDM_CE_FR_TIMAG08__W 11 +-#define OFDM_CE_FR_TIMAG08__M 0x7FF +-#define OFDM_CE_FR_TIMAG08__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL09__A 0x2C20022 +-#define OFDM_CE_FR_TREAL09__W 11 +-#define OFDM_CE_FR_TREAL09__M 0x7FF +-#define OFDM_CE_FR_TREAL09__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG09__A 0x2C20023 +-#define OFDM_CE_FR_TIMAG09__W 11 +-#define OFDM_CE_FR_TIMAG09__M 0x7FF +-#define OFDM_CE_FR_TIMAG09__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL10__A 0x2C20024 +-#define OFDM_CE_FR_TREAL10__W 11 +-#define OFDM_CE_FR_TREAL10__M 0x7FF +-#define OFDM_CE_FR_TREAL10__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG10__A 0x2C20025 +-#define OFDM_CE_FR_TIMAG10__W 11 +-#define OFDM_CE_FR_TIMAG10__M 0x7FF +-#define OFDM_CE_FR_TIMAG10__PRE 0x0 +- +-#define OFDM_CE_FR_TREAL11__A 0x2C20026 +-#define OFDM_CE_FR_TREAL11__W 11 +-#define OFDM_CE_FR_TREAL11__M 0x7FF +-#define OFDM_CE_FR_TREAL11__PRE 0x52 +- +-#define OFDM_CE_FR_TIMAG11__A 0x2C20027 +-#define OFDM_CE_FR_TIMAG11__W 11 +-#define OFDM_CE_FR_TIMAG11__M 0x7FF +-#define OFDM_CE_FR_TIMAG11__PRE 0x0 +- +-#define OFDM_CE_FR_MID_TAP__A 0x2C20028 +-#define OFDM_CE_FR_MID_TAP__W 11 +-#define OFDM_CE_FR_MID_TAP__M 0x7FF +-#define OFDM_CE_FR_MID_TAP__PRE 0x51 +- +-#define OFDM_CE_FR_SQS_G00__A 0x2C20029 +-#define OFDM_CE_FR_SQS_G00__W 8 +-#define OFDM_CE_FR_SQS_G00__M 0xFF +-#define OFDM_CE_FR_SQS_G00__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G01__A 0x2C2002A +-#define OFDM_CE_FR_SQS_G01__W 8 +-#define OFDM_CE_FR_SQS_G01__M 0xFF +-#define OFDM_CE_FR_SQS_G01__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G02__A 0x2C2002B +-#define OFDM_CE_FR_SQS_G02__W 8 +-#define OFDM_CE_FR_SQS_G02__M 0xFF +-#define OFDM_CE_FR_SQS_G02__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G03__A 0x2C2002C +-#define OFDM_CE_FR_SQS_G03__W 8 +-#define OFDM_CE_FR_SQS_G03__M 0xFF +-#define OFDM_CE_FR_SQS_G03__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G04__A 0x2C2002D +-#define OFDM_CE_FR_SQS_G04__W 8 +-#define OFDM_CE_FR_SQS_G04__M 0xFF +-#define OFDM_CE_FR_SQS_G04__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G05__A 0x2C2002E +-#define OFDM_CE_FR_SQS_G05__W 8 +-#define OFDM_CE_FR_SQS_G05__M 0xFF +-#define OFDM_CE_FR_SQS_G05__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G06__A 0x2C2002F +-#define OFDM_CE_FR_SQS_G06__W 8 +-#define OFDM_CE_FR_SQS_G06__M 0xFF +-#define OFDM_CE_FR_SQS_G06__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G07__A 0x2C20030 +-#define OFDM_CE_FR_SQS_G07__W 8 +-#define OFDM_CE_FR_SQS_G07__M 0xFF +-#define OFDM_CE_FR_SQS_G07__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G08__A 0x2C20031 +-#define OFDM_CE_FR_SQS_G08__W 8 +-#define OFDM_CE_FR_SQS_G08__M 0xFF +-#define OFDM_CE_FR_SQS_G08__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G09__A 0x2C20032 +-#define OFDM_CE_FR_SQS_G09__W 8 +-#define OFDM_CE_FR_SQS_G09__M 0xFF +-#define OFDM_CE_FR_SQS_G09__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G10__A 0x2C20033 +-#define OFDM_CE_FR_SQS_G10__W 8 +-#define OFDM_CE_FR_SQS_G10__M 0xFF +-#define OFDM_CE_FR_SQS_G10__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G11__A 0x2C20034 +-#define OFDM_CE_FR_SQS_G11__W 8 +-#define OFDM_CE_FR_SQS_G11__M 0xFF +-#define OFDM_CE_FR_SQS_G11__PRE 0xB +- +-#define OFDM_CE_FR_SQS_G12__A 0x2C20035 +-#define OFDM_CE_FR_SQS_G12__W 8 +-#define OFDM_CE_FR_SQS_G12__M 0xFF +-#define OFDM_CE_FR_SQS_G12__PRE 0x5 +- +-#define OFDM_CE_FR_RIO_G00__A 0x2C20036 +-#define OFDM_CE_FR_RIO_G00__W 9 +-#define OFDM_CE_FR_RIO_G00__M 0x1FF +-#define OFDM_CE_FR_RIO_G00__PRE 0x1FF +- +-#define OFDM_CE_FR_RIO_G01__A 0x2C20037 +-#define OFDM_CE_FR_RIO_G01__W 9 +-#define OFDM_CE_FR_RIO_G01__M 0x1FF +-#define OFDM_CE_FR_RIO_G01__PRE 0x190 +- +-#define OFDM_CE_FR_RIO_G02__A 0x2C20038 +-#define OFDM_CE_FR_RIO_G02__W 9 +-#define OFDM_CE_FR_RIO_G02__M 0x1FF +-#define OFDM_CE_FR_RIO_G02__PRE 0x10B +- +-#define OFDM_CE_FR_RIO_G03__A 0x2C20039 +-#define OFDM_CE_FR_RIO_G03__W 9 +-#define OFDM_CE_FR_RIO_G03__M 0x1FF +-#define OFDM_CE_FR_RIO_G03__PRE 0xC8 +- +-#define OFDM_CE_FR_RIO_G04__A 0x2C2003A +-#define OFDM_CE_FR_RIO_G04__W 9 +-#define OFDM_CE_FR_RIO_G04__M 0x1FF +-#define OFDM_CE_FR_RIO_G04__PRE 0xA0 +- +-#define OFDM_CE_FR_RIO_G05__A 0x2C2003B +-#define OFDM_CE_FR_RIO_G05__W 9 +-#define OFDM_CE_FR_RIO_G05__M 0x1FF +-#define OFDM_CE_FR_RIO_G05__PRE 0x85 +- +-#define OFDM_CE_FR_RIO_G06__A 0x2C2003C +-#define OFDM_CE_FR_RIO_G06__W 9 +-#define OFDM_CE_FR_RIO_G06__M 0x1FF +-#define OFDM_CE_FR_RIO_G06__PRE 0x72 +- +-#define OFDM_CE_FR_RIO_G07__A 0x2C2003D +-#define OFDM_CE_FR_RIO_G07__W 9 +-#define OFDM_CE_FR_RIO_G07__M 0x1FF +-#define OFDM_CE_FR_RIO_G07__PRE 0x64 +- +-#define OFDM_CE_FR_RIO_G08__A 0x2C2003E +-#define OFDM_CE_FR_RIO_G08__W 9 +-#define OFDM_CE_FR_RIO_G08__M 0x1FF +-#define OFDM_CE_FR_RIO_G08__PRE 0x59 +- +-#define OFDM_CE_FR_RIO_G09__A 0x2C2003F +-#define OFDM_CE_FR_RIO_G09__W 9 +-#define OFDM_CE_FR_RIO_G09__M 0x1FF +-#define OFDM_CE_FR_RIO_G09__PRE 0x50 +- +-#define OFDM_CE_FR_RIO_G10__A 0x2C20040 +-#define OFDM_CE_FR_RIO_G10__W 9 +-#define OFDM_CE_FR_RIO_G10__M 0x1FF +-#define OFDM_CE_FR_RIO_G10__PRE 0x49 +-#define OFDM_CE_FR_MODE__A 0x2C20041 +-#define OFDM_CE_FR_MODE__W 9 +-#define OFDM_CE_FR_MODE__M 0x1FF +-#define OFDM_CE_FR_MODE__PRE 0xDE +- +-#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0 +-#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1 +-#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1 +-#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0 +- +-#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1 +-#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1 +-#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2 +-#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2 +- +-#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2 +-#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1 +-#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4 +-#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4 +- +-#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3 +-#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1 +-#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8 +-#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8 +- +-#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4 +-#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1 +-#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10 +-#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10 +- +-#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5 +-#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1 +-#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20 +-#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0 +- +-#define OFDM_CE_FR_MODE_MID_MODE__B 6 +-#define OFDM_CE_FR_MODE_MID_MODE__W 1 +-#define OFDM_CE_FR_MODE_MID_MODE__M 0x40 +-#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40 +- +-#define OFDM_CE_FR_MODE_NOISE_MODE__B 7 +-#define OFDM_CE_FR_MODE_NOISE_MODE__W 1 +-#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80 +-#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80 +- +-#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8 +-#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1 +-#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100 +-#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0 +- +- +-#define OFDM_CE_FR_SQS_TRH__A 0x2C20042 +-#define OFDM_CE_FR_SQS_TRH__W 8 +-#define OFDM_CE_FR_SQS_TRH__M 0xFF +-#define OFDM_CE_FR_SQS_TRH__PRE 0x80 +- +-#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043 +-#define OFDM_CE_FR_RIO_GAIN__W 3 +-#define OFDM_CE_FR_RIO_GAIN__M 0x7 +-#define OFDM_CE_FR_RIO_GAIN__PRE 0x7 +-#define OFDM_CE_FR_BYPASS__A 0x2C20044 +-#define OFDM_CE_FR_BYPASS__W 10 +-#define OFDM_CE_FR_BYPASS__M 0x3FF +-#define OFDM_CE_FR_BYPASS__PRE 0x13B +- +-#define OFDM_CE_FR_BYPASS_RUN_IN__B 0 +-#define OFDM_CE_FR_BYPASS_RUN_IN__W 4 +-#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF +-#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB +- +-#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4 +-#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5 +-#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 +-#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130 +- +-#define OFDM_CE_FR_BYPASS_TOTAL__B 9 +-#define OFDM_CE_FR_BYPASS_TOTAL__W 1 +-#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200 +-#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0 +- +- +-#define OFDM_CE_FR_PM_SET__A 0x2C20045 +-#define OFDM_CE_FR_PM_SET__W 4 +-#define OFDM_CE_FR_PM_SET__M 0xF +-#define OFDM_CE_FR_PM_SET__PRE 0xD +- +-#define OFDM_CE_FR_ERR_SH__A 0x2C20046 +-#define OFDM_CE_FR_ERR_SH__W 4 +-#define OFDM_CE_FR_ERR_SH__M 0xF +-#define OFDM_CE_FR_ERR_SH__PRE 0x4 +- +-#define OFDM_CE_FR_MAN_SH__A 0x2C20047 +-#define OFDM_CE_FR_MAN_SH__W 4 +-#define OFDM_CE_FR_MAN_SH__M 0xF +-#define OFDM_CE_FR_MAN_SH__PRE 0x7 +- +-#define OFDM_CE_FR_TAP_SH__A 0x2C20048 +-#define OFDM_CE_FR_TAP_SH__W 3 +-#define OFDM_CE_FR_TAP_SH__M 0x7 +-#define OFDM_CE_FR_TAP_SH__PRE 0x3 +- +-#define OFDM_CE_FR_CLIP__A 0x2C20049 +-#define OFDM_CE_FR_CLIP__W 9 +-#define OFDM_CE_FR_CLIP__M 0x1FF +-#define OFDM_CE_FR_CLIP__PRE 0x49 +- +-#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A +-#define OFDM_CE_FR_LEAK_UPD__W 3 +-#define OFDM_CE_FR_LEAK_UPD__M 0x7 +-#define OFDM_CE_FR_LEAK_UPD__PRE 0x0 +- +-#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B +-#define OFDM_CE_FR_LEAK_SH__W 3 +-#define OFDM_CE_FR_LEAK_SH__M 0x7 +-#define OFDM_CE_FR_LEAK_SH__PRE 0x1 +- +- +- +-#define OFDM_CE_NE_RAM__A 0x2C30000 +- +- +- +-#define OFDM_CE_PB_RAM__A 0x2C40000 +- +- +- +- +- +-#define OFDM_CP_COMM_EXEC__A 0x2800000 +-#define OFDM_CP_COMM_EXEC__W 3 +-#define OFDM_CP_COMM_EXEC__M 0x7 +-#define OFDM_CP_COMM_EXEC__PRE 0x0 +-#define OFDM_CP_COMM_EXEC_STOP 0x0 +-#define OFDM_CP_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_CP_COMM_EXEC_HOLD 0x2 +-#define OFDM_CP_COMM_EXEC_STEP 0x3 +-#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4 +-#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6 +- +-#define OFDM_CP_COMM_STATE__A 0x2800001 +-#define OFDM_CP_COMM_STATE__W 16 +-#define OFDM_CP_COMM_STATE__M 0xFFFF +-#define OFDM_CP_COMM_STATE__PRE 0x0 +-#define OFDM_CP_COMM_MB__A 0x2800002 +-#define OFDM_CP_COMM_MB__W 16 +-#define OFDM_CP_COMM_MB__M 0xFFFF +-#define OFDM_CP_COMM_MB__PRE 0x0 +-#define OFDM_CP_COMM_INT_REQ__A 0x2800004 +-#define OFDM_CP_COMM_INT_REQ__W 16 +-#define OFDM_CP_COMM_INT_REQ__M 0xFFFF +-#define OFDM_CP_COMM_INT_REQ__PRE 0x0 +-#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1 +-#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1 +-#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2 +-#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0 +- +-#define OFDM_CP_COMM_INT_STA__A 0x2800005 +-#define OFDM_CP_COMM_INT_STA__W 16 +-#define OFDM_CP_COMM_INT_STA__M 0xFFFF +-#define OFDM_CP_COMM_INT_STA__PRE 0x0 +-#define OFDM_CP_COMM_INT_MSK__A 0x2800006 +-#define OFDM_CP_COMM_INT_MSK__W 16 +-#define OFDM_CP_COMM_INT_MSK__M 0xFFFF +-#define OFDM_CP_COMM_INT_MSK__PRE 0x0 +-#define OFDM_CP_COMM_INT_STM__A 0x2800007 +-#define OFDM_CP_COMM_INT_STM__W 16 +-#define OFDM_CP_COMM_INT_STM__M 0xFFFF +-#define OFDM_CP_COMM_INT_STM__PRE 0x0 +-#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0 +-#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16 +-#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF +-#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0 +- +- +- +-#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000 +-#define OFDM_CP_TOP_COMM_EXEC__W 3 +-#define OFDM_CP_TOP_COMM_EXEC__M 0x7 +-#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0 +-#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0 +-#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2 +-#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3 +- +-#define OFDM_CP_TOP_COMM_MB__A 0x2810002 +-#define OFDM_CP_TOP_COMM_MB__W 3 +-#define OFDM_CP_TOP_COMM_MB__M 0x7 +-#define OFDM_CP_TOP_COMM_MB__PRE 0x0 +-#define OFDM_CP_TOP_COMM_MB_CTL__B 0 +-#define OFDM_CP_TOP_COMM_MB_CTL__W 1 +-#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1 +-#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0 +-#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0 +-#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1 +-#define OFDM_CP_TOP_COMM_MB_OBS__B 1 +-#define OFDM_CP_TOP_COMM_MB_OBS__W 1 +-#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2 +-#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0 +-#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0 +-#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2 +-#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2 +-#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1 +-#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4 +-#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0 +-#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0 +-#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4 +- +-#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004 +-#define OFDM_CP_TOP_COMM_INT_REQ__W 1 +-#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1 +-#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0 +-#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005 +-#define OFDM_CP_TOP_COMM_INT_STA__W 1 +-#define OFDM_CP_TOP_COMM_INT_STA__M 0x1 +-#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0 +-#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0 +-#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1 +-#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1 +-#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0 +- +-#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006 +-#define OFDM_CP_TOP_COMM_INT_MSK__W 1 +-#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1 +-#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0 +-#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0 +-#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1 +-#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1 +-#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0 +- +-#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007 +-#define OFDM_CP_TOP_COMM_INT_STM__W 1 +-#define OFDM_CP_TOP_COMM_INT_STM__M 0x1 +-#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0 +-#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0 +-#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1 +-#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1 +-#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0 +- +- +-#define OFDM_CP_TOP_MODE_2K__A 0x2810010 +-#define OFDM_CP_TOP_MODE_2K__W 1 +-#define OFDM_CP_TOP_MODE_2K__M 0x1 +-#define OFDM_CP_TOP_MODE_2K__PRE 0x0 +- +-#define OFDM_CP_TOP_INTERVAL__A 0x2810011 +-#define OFDM_CP_TOP_INTERVAL__W 4 +-#define OFDM_CP_TOP_INTERVAL__M 0xF +-#define OFDM_CP_TOP_INTERVAL__PRE 0x5 +-#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012 +-#define OFDM_CP_TOP_DETECT_ENA__W 2 +-#define OFDM_CP_TOP_DETECT_ENA__M 0x3 +-#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0 +- +-#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0 +-#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1 +-#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1 +-#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0 +- +-#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1 +-#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1 +-#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2 +-#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0 +- +-#define OFDM_CP_TOP_FIX__A 0x2810013 +-#define OFDM_CP_TOP_FIX__W 4 +-#define OFDM_CP_TOP_FIX__M 0xF +-#define OFDM_CP_TOP_FIX__PRE 0xF +- +-#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0 +-#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1 +-#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1 +-#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1 +-#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0 +-#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1 +- +-#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1 +-#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1 +-#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2 +-#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2 +-#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0 +-#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2 +- +-#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2 +-#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1 +-#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4 +-#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4 +-#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0 +-#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4 +- +-#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3 +-#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1 +-#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8 +-#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8 +-#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0 +-#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8 +- +-#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021 +-#define OFDM_CP_TOP_BR_SMB_NR__W 4 +-#define OFDM_CP_TOP_BR_SMB_NR__M 0xF +-#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0 +- +-#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0 +-#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2 +-#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3 +-#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0 +- +-#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2 +-#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1 +-#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4 +-#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0 +- +-#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3 +-#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1 +-#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8 +-#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0 +- +- +-#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022 +-#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2 +-#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3 +-#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0 +- +-#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023 +-#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4 +-#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF +-#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8 +- +-#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024 +-#define OFDM_CP_TOP_BR_STR_DEL__W 10 +-#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF +-#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA +- +-#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025 +-#define OFDM_CP_TOP_BR_EXP_ADJ__W 5 +-#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F +-#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10 +- +-#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030 +-#define OFDM_CP_TOP_RT_ANG_INC0__W 16 +-#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF +-#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031 +-#define OFDM_CP_TOP_RT_ANG_INC1__W 8 +-#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF +-#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032 +-#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5 +-#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F +-#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5 +- +-#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033 +-#define OFDM_CP_TOP_RT_DETECT_TRH__W 2 +-#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3 +-#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3 +- +-#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034 +-#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3 +-#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7 +-#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035 +-#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1 +-#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1 +-#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036 +-#define OFDM_CP_TOP_RT_SPD_MOD__W 2 +-#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3 +-#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037 +-#define OFDM_CP_TOP_RT_SPD_SMB__W 2 +-#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3 +-#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0 +-#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038 +-#define OFDM_CP_TOP_RT_CPD_MODE__W 3 +-#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7 +-#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0 +-#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2 +-#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3 +-#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2 +-#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1 +-#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4 +-#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0 +- +- +-#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039 +-#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3 +-#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7 +-#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A +-#define OFDM_CP_TOP_RT_CPD_BIN__W 5 +-#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F +-#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B +-#define OFDM_CP_TOP_RT_CPD_MAX__W 4 +-#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF +-#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0 +-#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C +-#define OFDM_CP_TOP_RT_SUPR_VAL__W 2 +-#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3 +-#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0 +-#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1 +-#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1 +-#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1 +-#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1 +-#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2 +-#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0 +- +- +-#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D +-#define OFDM_CP_TOP_RT_EXP_AVE__W 5 +-#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F +-#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0 +- +-#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E +-#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5 +-#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F +-#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3 +- +-#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040 +-#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8 +-#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF +-#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041 +-#define OFDM_CP_TOP_AC_AVER_POW__W 8 +-#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF +-#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F +- +-#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042 +-#define OFDM_CP_TOP_AC_MAX_POW__W 8 +-#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF +-#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A +- +-#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043 +-#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6 +-#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F +-#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31 +- +-#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044 +-#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5 +-#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F +-#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10 +- +-#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045 +-#define OFDM_CP_TOP_AC_GAIN_MAN__W 16 +-#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF +-#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046 +-#define OFDM_CP_TOP_AC_GAIN_EXP__W 5 +-#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F +-#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047 +-#define OFDM_CP_TOP_AC_AMP_MODE__W 2 +-#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3 +-#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2 +-#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0 +-#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1 +-#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2 +- +-#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048 +-#define OFDM_CP_TOP_AC_AMP_FIX__W 14 +-#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF +-#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0 +-#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10 +-#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF +-#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10 +-#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4 +-#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00 +-#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049 +-#define OFDM_CP_TOP_AC_AMP_READ__W 14 +-#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF +-#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0 +-#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10 +-#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF +-#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10 +-#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4 +-#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00 +-#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0 +- +- +-#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A +-#define OFDM_CP_TOP_AC_ANG_MODE__W 2 +-#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3 +-#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3 +-#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0 +-#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1 +-#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2 +-#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3 +- +- +-#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B +-#define OFDM_CP_TOP_AC_ANG_OFFS__W 16 +-#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF +-#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C +-#define OFDM_CP_TOP_AC_ANG_READ__W 16 +-#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF +-#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060 +-#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8 +-#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF +-#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061 +-#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8 +-#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF +-#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062 +-#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8 +-#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF +-#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0 +- +-#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063 +-#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8 +-#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF +-#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050 +-#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15 +-#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF +-#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0 +-#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051 +-#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5 +-#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F +-#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C +-#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1 +-#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0 +- +- +-#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052 +-#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15 +-#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF +-#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0 +-#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053 +-#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11 +-#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF +-#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C +-#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0 +- +-#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1 +-#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0 +- +- +- +-#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000 +- +- +- +-#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000 +- +- +- +-#define OFDM_CP_DL_0_RAM__A 0x2840000 +- +- +- +-#define OFDM_CP_DL_1_RAM__A 0x2850000 +- +- +- +-#define OFDM_CP_DL_2_RAM__A 0x2860000 +- +- +- +- +- +-#define OFDM_EC_COMM_EXEC__A 0x3400000 +-#define OFDM_EC_COMM_EXEC__W 3 +-#define OFDM_EC_COMM_EXEC__M 0x7 +-#define OFDM_EC_COMM_EXEC__PRE 0x0 +-#define OFDM_EC_COMM_EXEC_STOP 0x0 +-#define OFDM_EC_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_EC_COMM_EXEC_HOLD 0x2 +-#define OFDM_EC_COMM_EXEC_STEP 0x3 +-#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4 +-#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6 +- +-#define OFDM_EC_COMM_STATE__A 0x3400001 +-#define OFDM_EC_COMM_STATE__W 16 +-#define OFDM_EC_COMM_STATE__M 0xFFFF +-#define OFDM_EC_COMM_STATE__PRE 0x0 +-#define OFDM_EC_COMM_MB__A 0x3400002 +-#define OFDM_EC_COMM_MB__W 16 +-#define OFDM_EC_COMM_MB__M 0xFFFF +-#define OFDM_EC_COMM_MB__PRE 0x0 +-#define OFDM_EC_COMM_INT_REQ__A 0x3400004 +-#define OFDM_EC_COMM_INT_REQ__W 16 +-#define OFDM_EC_COMM_INT_REQ__M 0xFFFF +-#define OFDM_EC_COMM_INT_REQ__PRE 0x0 +-#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4 +-#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1 +-#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10 +-#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0 +-#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5 +-#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1 +-#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20 +-#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0 +- +-#define OFDM_EC_COMM_INT_STA__A 0x3400005 +-#define OFDM_EC_COMM_INT_STA__W 16 +-#define OFDM_EC_COMM_INT_STA__M 0xFFFF +-#define OFDM_EC_COMM_INT_STA__PRE 0x0 +-#define OFDM_EC_COMM_INT_MSK__A 0x3400006 +-#define OFDM_EC_COMM_INT_MSK__W 16 +-#define OFDM_EC_COMM_INT_MSK__M 0xFFFF +-#define OFDM_EC_COMM_INT_MSK__PRE 0x0 +-#define OFDM_EC_COMM_INT_STM__A 0x3400007 +-#define OFDM_EC_COMM_INT_STM__W 16 +-#define OFDM_EC_COMM_INT_STM__M 0xFFFF +-#define OFDM_EC_COMM_INT_STM__PRE 0x0 +-#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0 +-#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16 +-#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF +-#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0 +- +- +- +-#define OFDM_EC_SB_COMM_EXEC__A 0x3410000 +-#define OFDM_EC_SB_COMM_EXEC__W 3 +-#define OFDM_EC_SB_COMM_EXEC__M 0x7 +-#define OFDM_EC_SB_COMM_EXEC__PRE 0x0 +-#define OFDM_EC_SB_COMM_EXEC_STOP 0x0 +-#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2 +-#define OFDM_EC_SB_COMM_EXEC_STEP 0x3 +- +-#define OFDM_EC_SB_COMM_STATE__A 0x3410001 +-#define OFDM_EC_SB_COMM_STATE__W 4 +-#define OFDM_EC_SB_COMM_STATE__M 0xF +-#define OFDM_EC_SB_COMM_STATE__PRE 0x0 +-#define OFDM_EC_SB_COMM_MB__A 0x3410002 +-#define OFDM_EC_SB_COMM_MB__W 2 +-#define OFDM_EC_SB_COMM_MB__M 0x3 +-#define OFDM_EC_SB_COMM_MB__PRE 0x0 +-#define OFDM_EC_SB_COMM_MB_CTL__B 0 +-#define OFDM_EC_SB_COMM_MB_CTL__W 1 +-#define OFDM_EC_SB_COMM_MB_CTL__M 0x1 +-#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0 +-#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0 +-#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1 +-#define OFDM_EC_SB_COMM_MB_OBS__B 1 +-#define OFDM_EC_SB_COMM_MB_OBS__W 1 +-#define OFDM_EC_SB_COMM_MB_OBS__M 0x2 +-#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0 +-#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0 +-#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2 +- +- +-#define OFDM_EC_SB_TR_MODE__A 0x3410010 +-#define OFDM_EC_SB_TR_MODE__W 1 +-#define OFDM_EC_SB_TR_MODE__M 0x1 +-#define OFDM_EC_SB_TR_MODE__PRE 0x0 +-#define OFDM_EC_SB_TR_MODE_8K 0x0 +-#define OFDM_EC_SB_TR_MODE_2K 0x1 +- +- +-#define OFDM_EC_SB_CONST__A 0x3410011 +-#define OFDM_EC_SB_CONST__W 2 +-#define OFDM_EC_SB_CONST__M 0x3 +-#define OFDM_EC_SB_CONST__PRE 0x2 +-#define OFDM_EC_SB_CONST_QPSK 0x0 +-#define OFDM_EC_SB_CONST_16QAM 0x1 +-#define OFDM_EC_SB_CONST_64QAM 0x2 +- +- +-#define OFDM_EC_SB_ALPHA__A 0x3410012 +-#define OFDM_EC_SB_ALPHA__W 3 +-#define OFDM_EC_SB_ALPHA__M 0x7 +-#define OFDM_EC_SB_ALPHA__PRE 0x0 +-#define OFDM_EC_SB_ALPHA_NH 0x0 +-#define OFDM_EC_SB_ALPHA_H1 0x1 +-#define OFDM_EC_SB_ALPHA_H2 0x2 +-#define OFDM_EC_SB_ALPHA_H4 0x3 +- +- +-#define OFDM_EC_SB_PRIOR__A 0x3410013 +-#define OFDM_EC_SB_PRIOR__W 1 +-#define OFDM_EC_SB_PRIOR__M 0x1 +-#define OFDM_EC_SB_PRIOR__PRE 0x0 +-#define OFDM_EC_SB_PRIOR_HI 0x0 +-#define OFDM_EC_SB_PRIOR_LO 0x1 +- +- +-#define OFDM_EC_SB_CSI_HI__A 0x3410014 +-#define OFDM_EC_SB_CSI_HI__W 5 +-#define OFDM_EC_SB_CSI_HI__M 0x1F +-#define OFDM_EC_SB_CSI_HI__PRE 0x18 +-#define OFDM_EC_SB_CSI_HI_MAX 0x1F +-#define OFDM_EC_SB_CSI_HI_MIN 0x0 +-#define OFDM_EC_SB_CSI_HI_TAG 0x0 +- +- +-#define OFDM_EC_SB_CSI_LO__A 0x3410015 +-#define OFDM_EC_SB_CSI_LO__W 5 +-#define OFDM_EC_SB_CSI_LO__M 0x1F +-#define OFDM_EC_SB_CSI_LO__PRE 0xC +-#define OFDM_EC_SB_CSI_LO_MAX 0x1F +-#define OFDM_EC_SB_CSI_LO_MIN 0x0 +-#define OFDM_EC_SB_CSI_LO_TAG 0x0 +- +- +-#define OFDM_EC_SB_SMB_TGL__A 0x3410016 +-#define OFDM_EC_SB_SMB_TGL__W 1 +-#define OFDM_EC_SB_SMB_TGL__M 0x1 +-#define OFDM_EC_SB_SMB_TGL__PRE 0x1 +-#define OFDM_EC_SB_SMB_TGL_OFF 0x0 +-#define OFDM_EC_SB_SMB_TGL_ON 0x1 +- +- +-#define OFDM_EC_SB_SNR_HI__A 0x3410017 +-#define OFDM_EC_SB_SNR_HI__W 7 +-#define OFDM_EC_SB_SNR_HI__M 0x7F +-#define OFDM_EC_SB_SNR_HI__PRE 0x7F +-#define OFDM_EC_SB_SNR_HI_MAX 0x7F +-#define OFDM_EC_SB_SNR_HI_MIN 0x0 +-#define OFDM_EC_SB_SNR_HI_TAG 0x0 +- +- +-#define OFDM_EC_SB_SNR_MID__A 0x3410018 +-#define OFDM_EC_SB_SNR_MID__W 7 +-#define OFDM_EC_SB_SNR_MID__M 0x7F +-#define OFDM_EC_SB_SNR_MID__PRE 0x7F +-#define OFDM_EC_SB_SNR_MID_MAX 0x7F +-#define OFDM_EC_SB_SNR_MID_MIN 0x0 +-#define OFDM_EC_SB_SNR_MID_TAG 0x0 +- +- +-#define OFDM_EC_SB_SNR_LO__A 0x3410019 +-#define OFDM_EC_SB_SNR_LO__W 7 +-#define OFDM_EC_SB_SNR_LO__M 0x7F +-#define OFDM_EC_SB_SNR_LO__PRE 0x7F +-#define OFDM_EC_SB_SNR_LO_MAX 0x7F +-#define OFDM_EC_SB_SNR_LO_MIN 0x0 +-#define OFDM_EC_SB_SNR_LO_TAG 0x0 +- +- +-#define OFDM_EC_SB_SCALE_MSB__A 0x341001A +-#define OFDM_EC_SB_SCALE_MSB__W 6 +-#define OFDM_EC_SB_SCALE_MSB__M 0x3F +-#define OFDM_EC_SB_SCALE_MSB__PRE 0x30 +-#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F +- +- +-#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B +-#define OFDM_EC_SB_SCALE_BIT2__W 6 +-#define OFDM_EC_SB_SCALE_BIT2__M 0x3F +-#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC +-#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F +- +- +-#define OFDM_EC_SB_SCALE_LSB__A 0x341001C +-#define OFDM_EC_SB_SCALE_LSB__W 6 +-#define OFDM_EC_SB_SCALE_LSB__M 0x3F +-#define OFDM_EC_SB_SCALE_LSB__PRE 0x3 +-#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F +- +- +-#define OFDM_EC_SB_CSI_OFS0__A 0x341001D +-#define OFDM_EC_SB_CSI_OFS0__W 4 +-#define OFDM_EC_SB_CSI_OFS0__M 0xF +-#define OFDM_EC_SB_CSI_OFS0__PRE 0x1 +- +-#define OFDM_EC_SB_CSI_OFS1__A 0x341001E +-#define OFDM_EC_SB_CSI_OFS1__W 4 +-#define OFDM_EC_SB_CSI_OFS1__M 0xF +-#define OFDM_EC_SB_CSI_OFS1__PRE 0x1 +- +-#define OFDM_EC_SB_CSI_OFS2__A 0x341001F +-#define OFDM_EC_SB_CSI_OFS2__W 4 +-#define OFDM_EC_SB_CSI_OFS2__M 0xF +-#define OFDM_EC_SB_CSI_OFS2__PRE 0x1 +- +-#define OFDM_EC_SB_MAX0__A 0x3410020 +-#define OFDM_EC_SB_MAX0__W 6 +-#define OFDM_EC_SB_MAX0__M 0x3F +-#define OFDM_EC_SB_MAX0__PRE 0x3F +- +-#define OFDM_EC_SB_MAX1__A 0x3410021 +-#define OFDM_EC_SB_MAX1__W 6 +-#define OFDM_EC_SB_MAX1__M 0x3F +-#define OFDM_EC_SB_MAX1__PRE 0x3F +-#define OFDM_EC_SB_MAX1_INIT 0x3F +- +- +-#define OFDM_EC_SB_MAX2__A 0x3410022 +-#define OFDM_EC_SB_MAX2__W 6 +-#define OFDM_EC_SB_MAX2__M 0x3F +-#define OFDM_EC_SB_MAX2__PRE 0x3F +- +-#define OFDM_EC_SB_CSI_DIS__A 0x3410023 +-#define OFDM_EC_SB_CSI_DIS__W 1 +-#define OFDM_EC_SB_CSI_DIS__M 0x1 +-#define OFDM_EC_SB_CSI_DIS__PRE 0x0 +- +- +- +-#define OFDM_EC_VD_COMM_EXEC__A 0x3420000 +-#define OFDM_EC_VD_COMM_EXEC__W 3 +-#define OFDM_EC_VD_COMM_EXEC__M 0x7 +-#define OFDM_EC_VD_COMM_EXEC__PRE 0x0 +-#define OFDM_EC_VD_COMM_EXEC_STOP 0x0 +-#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2 +-#define OFDM_EC_VD_COMM_EXEC_STEP 0x3 +- +-#define OFDM_EC_VD_COMM_STATE__A 0x3420001 +-#define OFDM_EC_VD_COMM_STATE__W 4 +-#define OFDM_EC_VD_COMM_STATE__M 0xF +-#define OFDM_EC_VD_COMM_STATE__PRE 0x0 +-#define OFDM_EC_VD_COMM_MB__A 0x3420002 +-#define OFDM_EC_VD_COMM_MB__W 2 +-#define OFDM_EC_VD_COMM_MB__M 0x3 +-#define OFDM_EC_VD_COMM_MB__PRE 0x0 +-#define OFDM_EC_VD_COMM_MB_CTL__B 0 +-#define OFDM_EC_VD_COMM_MB_CTL__W 1 +-#define OFDM_EC_VD_COMM_MB_CTL__M 0x1 +-#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0 +-#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0 +-#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1 +-#define OFDM_EC_VD_COMM_MB_OBS__B 1 +-#define OFDM_EC_VD_COMM_MB_OBS__W 1 +-#define OFDM_EC_VD_COMM_MB_OBS__M 0x2 +-#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0 +-#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0 +-#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2 +- +-#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003 +-#define OFDM_EC_VD_COMM_INT_REQ__W 1 +-#define OFDM_EC_VD_COMM_INT_REQ__M 0x1 +-#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0 +-#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005 +-#define OFDM_EC_VD_COMM_INT_STA__W 1 +-#define OFDM_EC_VD_COMM_INT_STA__M 0x1 +-#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0 +-#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0 +-#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1 +-#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1 +-#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0 +- +-#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006 +-#define OFDM_EC_VD_COMM_INT_MSK__W 1 +-#define OFDM_EC_VD_COMM_INT_MSK__M 0x1 +-#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0 +-#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0 +-#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1 +-#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1 +-#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0 +- +-#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007 +-#define OFDM_EC_VD_COMM_INT_STM__W 1 +-#define OFDM_EC_VD_COMM_INT_STM__M 0x1 +-#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0 +-#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0 +-#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1 +-#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1 +-#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0 +- +- +-#define OFDM_EC_VD_FORCE__A 0x3420010 +-#define OFDM_EC_VD_FORCE__W 2 +-#define OFDM_EC_VD_FORCE__M 0x3 +-#define OFDM_EC_VD_FORCE__PRE 0x2 +-#define OFDM_EC_VD_FORCE_FREE 0x0 +-#define OFDM_EC_VD_FORCE_PROP 0x1 +-#define OFDM_EC_VD_FORCE_FORCED 0x2 +-#define OFDM_EC_VD_FORCE_FIXED 0x3 +- +- +-#define OFDM_EC_VD_SET_CODERATE__A 0x3420011 +-#define OFDM_EC_VD_SET_CODERATE__W 3 +-#define OFDM_EC_VD_SET_CODERATE__M 0x7 +-#define OFDM_EC_VD_SET_CODERATE__PRE 0x1 +-#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0 +-#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1 +-#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2 +-#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3 +-#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4 +- +- +-#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012 +-#define OFDM_EC_VD_REQ_SMB_CNT__W 16 +-#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF +-#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1 +- +-#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013 +-#define OFDM_EC_VD_REQ_BIT_CNT__W 16 +-#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF +-#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF +- +-#define OFDM_EC_VD_RLK_ENA__A 0x3420014 +-#define OFDM_EC_VD_RLK_ENA__W 1 +-#define OFDM_EC_VD_RLK_ENA__M 0x1 +-#define OFDM_EC_VD_RLK_ENA__PRE 0x1 +-#define OFDM_EC_VD_RLK_ENA_OFF 0x0 +-#define OFDM_EC_VD_RLK_ENA_ON 0x1 +- +- +-#define OFDM_EC_VD_VAL__A 0x3420015 +-#define OFDM_EC_VD_VAL__W 2 +-#define OFDM_EC_VD_VAL__M 0x3 +-#define OFDM_EC_VD_VAL__PRE 0x0 +-#define OFDM_EC_VD_VAL_CODE 0x1 +-#define OFDM_EC_VD_VAL_CNT 0x2 +- +- +-#define OFDM_EC_VD_GET_CODERATE__A 0x3420016 +-#define OFDM_EC_VD_GET_CODERATE__W 3 +-#define OFDM_EC_VD_GET_CODERATE__M 0x7 +-#define OFDM_EC_VD_GET_CODERATE__PRE 0x0 +-#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0 +-#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1 +-#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2 +-#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3 +-#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4 +- +- +-#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 +-#define OFDM_EC_VD_ERR_BIT_CNT__W 16 +-#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF +-#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF +- +-#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 +-#define OFDM_EC_VD_IN_BIT_CNT__W 16 +-#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF +-#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0 +- +-#define OFDM_EC_VD_STS__A 0x3420019 +-#define OFDM_EC_VD_STS__W 1 +-#define OFDM_EC_VD_STS__M 0x1 +-#define OFDM_EC_VD_STS__PRE 0x0 +-#define OFDM_EC_VD_STS_NO_LOCK 0x0 +-#define OFDM_EC_VD_STS_IN_LOCK 0x1 +- +- +-#define OFDM_EC_VD_RLK_CNT__A 0x342001A +-#define OFDM_EC_VD_RLK_CNT__W 16 +-#define OFDM_EC_VD_RLK_CNT__M 0xFFFF +-#define OFDM_EC_VD_RLK_CNT__PRE 0x0 +- +- +- +-#define OFDM_EC_SY_COMM_EXEC__A 0x3430000 +-#define OFDM_EC_SY_COMM_EXEC__W 2 +-#define OFDM_EC_SY_COMM_EXEC__M 0x3 +-#define OFDM_EC_SY_COMM_EXEC__PRE 0x0 +-#define OFDM_EC_SY_COMM_EXEC_STOP 0x0 +-#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2 +-#define OFDM_EC_SY_COMM_EXEC_STEP 0x3 +- +-#define OFDM_EC_SY_COMM_MB__A 0x3430002 +-#define OFDM_EC_SY_COMM_MB__W 2 +-#define OFDM_EC_SY_COMM_MB__M 0x3 +-#define OFDM_EC_SY_COMM_MB__PRE 0x0 +-#define OFDM_EC_SY_COMM_MB_CTL__B 0 +-#define OFDM_EC_SY_COMM_MB_CTL__W 1 +-#define OFDM_EC_SY_COMM_MB_CTL__M 0x1 +-#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0 +-#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0 +-#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1 +-#define OFDM_EC_SY_COMM_MB_OBS__B 1 +-#define OFDM_EC_SY_COMM_MB_OBS__W 1 +-#define OFDM_EC_SY_COMM_MB_OBS__M 0x2 +-#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0 +-#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0 +-#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2 +- +-#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003 +-#define OFDM_EC_SY_COMM_INT_REQ__W 1 +-#define OFDM_EC_SY_COMM_INT_REQ__M 0x1 +-#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0 +-#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005 +-#define OFDM_EC_SY_COMM_INT_STA__W 3 +-#define OFDM_EC_SY_COMM_INT_STA__M 0x7 +-#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0 +- +-#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0 +-#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1 +-#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1 +-#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 +- +-#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1 +-#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1 +-#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +-#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 +- +-#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +-#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +-#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +-#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 +- +-#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006 +-#define OFDM_EC_SY_COMM_INT_MSK__W 3 +-#define OFDM_EC_SY_COMM_INT_MSK__M 0x7 +-#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0 +-#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0 +-#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1 +-#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +-#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +-#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +-#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +-#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +-#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +-#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +-#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +-#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +-#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +- +-#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007 +-#define OFDM_EC_SY_COMM_INT_STM__W 3 +-#define OFDM_EC_SY_COMM_INT_STM__M 0x7 +-#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0 +-#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0 +-#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1 +-#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +-#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +-#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +-#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +-#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +-#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +-#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +-#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +-#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +-#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +- +-#define OFDM_EC_SY_STATUS__A 0x3430010 +-#define OFDM_EC_SY_STATUS__W 2 +-#define OFDM_EC_SY_STATUS__M 0x3 +-#define OFDM_EC_SY_STATUS__PRE 0x0 +-#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0 +-#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2 +-#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3 +-#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0 +-#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0 +-#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1 +-#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2 +- +- +-#define OFDM_EC_SY_TIMEOUT__A 0x3430011 +-#define OFDM_EC_SY_TIMEOUT__W 16 +-#define OFDM_EC_SY_TIMEOUT__M 0xFFFF +-#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98 +- +-#define OFDM_EC_SY_SYNC_LWM__A 0x3430012 +-#define OFDM_EC_SY_SYNC_LWM__W 4 +-#define OFDM_EC_SY_SYNC_LWM__M 0xF +-#define OFDM_EC_SY_SYNC_LWM__PRE 0x2 +- +-#define OFDM_EC_SY_SYNC_AWM__A 0x3430013 +-#define OFDM_EC_SY_SYNC_AWM__W 4 +-#define OFDM_EC_SY_SYNC_AWM__M 0xF +-#define OFDM_EC_SY_SYNC_AWM__PRE 0x3 +- +-#define OFDM_EC_SY_SYNC_HWM__A 0x3430014 +-#define OFDM_EC_SY_SYNC_HWM__W 4 +-#define OFDM_EC_SY_SYNC_HWM__M 0xF +-#define OFDM_EC_SY_SYNC_HWM__PRE 0x5 +- +-#define OFDM_EC_SY_UNLOCK__A 0x3430015 +-#define OFDM_EC_SY_UNLOCK__W 1 +-#define OFDM_EC_SY_UNLOCK__M 0x1 +-#define OFDM_EC_SY_UNLOCK__PRE 0x0 +- +- +- +-#define OFDM_EC_SB_BD0_RAM__A 0x3440000 +- +- +- +-#define OFDM_EC_SB_BD1_RAM__A 0x3450000 +- +- +- +-#define OFDM_EC_SB_SD_RAM__A 0x3460000 +- +- +- +-#define OFDM_EC_VD_RE_RAM__A 0x3470000 +- +- +- +-#define OFDM_EC_VD_TB0_RAM__A 0x3480000 +- +- +- +-#define OFDM_EC_VD_TB1_RAM__A 0x3490000 +- +- +- +-#define OFDM_EC_VD_TB2_RAM__A 0x34A0000 +- +- +- +-#define OFDM_EC_VD_TB3_RAM__A 0x34B0000 +- +- +- +- +- +-#define OFDM_EQ_COMM_EXEC__A 0x3000000 +-#define OFDM_EQ_COMM_EXEC__W 3 +-#define OFDM_EQ_COMM_EXEC__M 0x7 +-#define OFDM_EQ_COMM_EXEC__PRE 0x0 +-#define OFDM_EQ_COMM_EXEC_STOP 0x0 +-#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_EQ_COMM_EXEC_HOLD 0x2 +-#define OFDM_EQ_COMM_EXEC_STEP 0x3 +-#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4 +-#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6 +- +-#define OFDM_EQ_COMM_STATE__A 0x3000001 +-#define OFDM_EQ_COMM_STATE__W 16 +-#define OFDM_EQ_COMM_STATE__M 0xFFFF +-#define OFDM_EQ_COMM_STATE__PRE 0x0 +-#define OFDM_EQ_COMM_MB__A 0x3000002 +-#define OFDM_EQ_COMM_MB__W 16 +-#define OFDM_EQ_COMM_MB__M 0xFFFF +-#define OFDM_EQ_COMM_MB__PRE 0x0 +-#define OFDM_EQ_COMM_INT_REQ__A 0x3000004 +-#define OFDM_EQ_COMM_INT_REQ__W 16 +-#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF +-#define OFDM_EQ_COMM_INT_REQ__PRE 0x0 +-#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3 +-#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1 +-#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8 +-#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0 +- +-#define OFDM_EQ_COMM_INT_STA__A 0x3000005 +-#define OFDM_EQ_COMM_INT_STA__W 16 +-#define OFDM_EQ_COMM_INT_STA__M 0xFFFF +-#define OFDM_EQ_COMM_INT_STA__PRE 0x0 +-#define OFDM_EQ_COMM_INT_MSK__A 0x3000006 +-#define OFDM_EQ_COMM_INT_MSK__W 16 +-#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF +-#define OFDM_EQ_COMM_INT_MSK__PRE 0x0 +-#define OFDM_EQ_COMM_INT_STM__A 0x3000007 +-#define OFDM_EQ_COMM_INT_STM__W 16 +-#define OFDM_EQ_COMM_INT_STM__M 0xFFFF +-#define OFDM_EQ_COMM_INT_STM__PRE 0x0 +-#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0 +-#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16 +-#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF +-#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0 +- +- +- +-#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000 +-#define OFDM_EQ_TOP_COMM_EXEC__W 3 +-#define OFDM_EQ_TOP_COMM_EXEC__M 0x7 +-#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0 +-#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2 +-#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3 +- +-#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001 +-#define OFDM_EQ_TOP_COMM_STATE__W 4 +-#define OFDM_EQ_TOP_COMM_STATE__M 0xF +-#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_MB__A 0x3010002 +-#define OFDM_EQ_TOP_COMM_MB__W 6 +-#define OFDM_EQ_TOP_COMM_MB__M 0x3F +-#define OFDM_EQ_TOP_COMM_MB__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_MB_CTL__B 0 +-#define OFDM_EQ_TOP_COMM_MB_CTL__W 1 +-#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1 +-#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0 +-#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1 +-#define OFDM_EQ_TOP_COMM_MB_OBS__B 1 +-#define OFDM_EQ_TOP_COMM_MB_OBS__W 1 +-#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2 +-#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0 +-#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2 +-#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2 +-#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2 +-#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC +-#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0 +-#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4 +-#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20 +-#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30 +- +-#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004 +-#define OFDM_EQ_TOP_COMM_INT_REQ__W 1 +-#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1 +-#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005 +-#define OFDM_EQ_TOP_COMM_INT_STA__W 2 +-#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3 +-#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0 +-#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1 +-#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1 +-#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1 +-#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1 +-#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2 +-#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0 +- +-#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006 +-#define OFDM_EQ_TOP_COMM_INT_MSK__W 2 +-#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3 +-#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0 +-#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1 +-#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1 +-#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1 +-#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1 +-#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2 +-#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0 +- +-#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007 +-#define OFDM_EQ_TOP_COMM_INT_STM__W 2 +-#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3 +-#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0 +-#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1 +-#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1 +-#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0 +-#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1 +-#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1 +-#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2 +-#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0 +- +-#define OFDM_EQ_TOP_IS_MODE__A 0x3010014 +-#define OFDM_EQ_TOP_IS_MODE__W 4 +-#define OFDM_EQ_TOP_IS_MODE__M 0xF +-#define OFDM_EQ_TOP_IS_MODE__PRE 0x0 +- +-#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1 +-#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1 +-#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1 +- +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2 +- +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4 +- +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0 +-#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8 +- +- +-#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015 +-#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10 +-#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF +-#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114 +- +-#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016 +-#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5 +-#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F +-#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5 +- +-#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017 +-#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5 +-#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F +-#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10 +-#define OFDM_EQ_TOP_DV_MODE__A 0x301001E +-#define OFDM_EQ_TOP_DV_MODE__W 4 +-#define OFDM_EQ_TOP_DV_MODE__M 0xF +-#define OFDM_EQ_TOP_DV_MODE__PRE 0xF +- +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1 +- +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0 +-#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2 +- +-#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2 +-#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1 +-#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4 +-#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4 +-#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0 +-#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4 +- +-#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3 +-#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1 +-#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8 +-#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8 +-#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0 +-#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8 +- +- +-#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F +-#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16 +-#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF +-#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0 +-#define OFDM_EQ_TOP_SN_MODE__A 0x3010028 +-#define OFDM_EQ_TOP_SN_MODE__W 8 +-#define OFDM_EQ_TOP_SN_MODE__M 0xFF +-#define OFDM_EQ_TOP_SN_MODE__PRE 0x18 +- +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1 +- +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2 +- +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4 +- +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8 +- +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10 +- +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20 +- +-#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6 +-#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1 +-#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40 +-#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0 +-#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40 +- +-#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7 +-#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1 +-#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80 +-#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0 +-#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0 +-#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80 +- +- +-#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029 +-#define OFDM_EQ_TOP_SN_PFIX__W 8 +-#define OFDM_EQ_TOP_SN_PFIX__M 0xFF +-#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0 +- +-#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A +-#define OFDM_EQ_TOP_SN_CEGAIN__W 8 +-#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF +-#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30 +- +-#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B +-#define OFDM_EQ_TOP_SN_OFFSET__W 6 +-#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F +-#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39 +- +-#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C +-#define OFDM_EQ_TOP_SN_NULLIFY__W 6 +-#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F +-#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0 +-#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D +-#define OFDM_EQ_TOP_SN_SQUASH__W 10 +-#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF +-#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7 +- +-#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0 +-#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6 +-#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F +-#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7 +- +-#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6 +-#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4 +-#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0 +-#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0 +- +-#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032 +-#define OFDM_EQ_TOP_RC_SEL_CAR__W 8 +-#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF +-#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2 +-#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1 +-#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1 +-#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1 +- +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1 +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2 +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6 +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2 +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2 +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4 +-#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6 +- +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3 +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2 +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18 +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8 +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10 +-#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18 +- +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5 +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2 +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60 +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20 +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40 +-#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60 +- +-#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7 +-#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1 +-#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80 +-#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0 +-#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80 +- +-#define OFDM_EQ_TOP_RC_STS__A 0x3010033 +-#define OFDM_EQ_TOP_RC_STS__W 16 +-#define OFDM_EQ_TOP_RC_STS__M 0xFFFF +-#define OFDM_EQ_TOP_RC_STS__PRE 0x0 +- +-#define OFDM_EQ_TOP_RC_STS_DIFF__B 0 +-#define OFDM_EQ_TOP_RC_STS_DIFF__W 11 +-#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF +-#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0 +- +-#define OFDM_EQ_TOP_RC_STS_FIRST__B 11 +-#define OFDM_EQ_TOP_RC_STS_FIRST__W 1 +-#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800 +-#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0 +-#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0 +-#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800 +- +-#define OFDM_EQ_TOP_RC_STS_SELEC__B 12 +-#define OFDM_EQ_TOP_RC_STS_SELEC__W 1 +-#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000 +-#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0 +-#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0 +-#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000 +- +-#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13 +-#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1 +-#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000 +-#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0 +-#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0 +-#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000 +- +-#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14 +-#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1 +-#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000 +-#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0 +-#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0 +-#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000 +- +-#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15 +-#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1 +-#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000 +-#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0 +-#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0 +-#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000 +- +- +-#define OFDM_EQ_TOP_OT_CONST__A 0x3010046 +-#define OFDM_EQ_TOP_OT_CONST__W 2 +-#define OFDM_EQ_TOP_OT_CONST__M 0x3 +-#define OFDM_EQ_TOP_OT_CONST__PRE 0x2 +- +-#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047 +-#define OFDM_EQ_TOP_OT_ALPHA__W 2 +-#define OFDM_EQ_TOP_OT_ALPHA__M 0x3 +-#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0 +- +-#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048 +-#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5 +-#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F +-#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E +- +-#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049 +-#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5 +-#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F +-#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F +- +-#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A +-#define OFDM_EQ_TOP_OT_CSI_STEP__W 4 +-#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF +-#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5 +- +-#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B +-#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8 +-#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF +-#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5 +- +-#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C +-#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8 +-#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF +-#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B +- +-#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D +-#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7 +-#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F +-#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0 +- +-#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E +-#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7 +-#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F +-#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050 +-#define OFDM_EQ_TOP_TD_TPS_INIT__W 1 +-#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1 +-#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0 +-#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1 +- +- +-#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051 +-#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16 +-#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF +-#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE +-#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11 +- +- +-#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052 +-#define OFDM_EQ_TOP_TD_TPS_LEN__W 6 +-#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F +-#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17 +-#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F +- +- +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053 +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2 +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3 +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0 +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1 +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2 +-#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3 +- +- +-#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +-#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 +-#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +-#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 +-#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 +-#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 +- +- +-#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055 +-#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3 +-#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7 +-#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0 +-#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1 +-#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2 +-#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3 +- +- +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3 +-#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4 +- +- +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 +-#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 +- +- +-#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058 +-#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2 +-#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3 +-#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0 +-#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1 +-#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2 +-#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3 +- +- +-#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059 +-#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2 +-#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3 +-#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0 +-#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0 +-#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1 +- +- +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8 +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8 +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF +-#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C +-#define OFDM_EQ_TOP_TD_TPS_RSV__W 6 +-#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F +-#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D +-#define OFDM_EQ_TOP_TD_TPS_BCH__W 14 +-#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF +-#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E +-#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16 +-#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF +-#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F +-#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16 +-#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF +-#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 +-#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4 +-#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF +-#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0 +- +-#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 +-#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16 +-#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF +-#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200 +- +-#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 +-#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10 +-#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF +-#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F +- +- +- +- +- +-#define OFDM_FE_COMM_EXEC__A 0x2000000 +-#define OFDM_FE_COMM_EXEC__W 3 +-#define OFDM_FE_COMM_EXEC__M 0x7 +-#define OFDM_FE_COMM_EXEC__PRE 0x0 +-#define OFDM_FE_COMM_EXEC_STOP 0x0 +-#define OFDM_FE_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_FE_COMM_EXEC_HOLD 0x2 +-#define OFDM_FE_COMM_EXEC_STEP 0x3 +- +-#define OFDM_FE_COMM_STATE__A 0x2000001 +-#define OFDM_FE_COMM_STATE__W 16 +-#define OFDM_FE_COMM_STATE__M 0xFFFF +-#define OFDM_FE_COMM_STATE__PRE 0x0 +-#define OFDM_FE_COMM_MB__A 0x2000002 +-#define OFDM_FE_COMM_MB__W 16 +-#define OFDM_FE_COMM_MB__M 0xFFFF +-#define OFDM_FE_COMM_MB__PRE 0x0 +-#define OFDM_FE_COMM_INT_REQ__A 0x2000004 +-#define OFDM_FE_COMM_INT_REQ__W 16 +-#define OFDM_FE_COMM_INT_REQ__M 0xFFFF +-#define OFDM_FE_COMM_INT_REQ__PRE 0x0 +-#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0 +-#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1 +-#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1 +-#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0 +- +-#define OFDM_FE_COMM_INT_STA__A 0x2000005 +-#define OFDM_FE_COMM_INT_STA__W 16 +-#define OFDM_FE_COMM_INT_STA__M 0xFFFF +-#define OFDM_FE_COMM_INT_STA__PRE 0x0 +-#define OFDM_FE_COMM_INT_MSK__A 0x2000006 +-#define OFDM_FE_COMM_INT_MSK__W 16 +-#define OFDM_FE_COMM_INT_MSK__M 0xFFFF +-#define OFDM_FE_COMM_INT_MSK__PRE 0x0 +-#define OFDM_FE_COMM_INT_STM__A 0x2000007 +-#define OFDM_FE_COMM_INT_STM__W 16 +-#define OFDM_FE_COMM_INT_STM__M 0xFFFF +-#define OFDM_FE_COMM_INT_STM__PRE 0x0 +-#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0 +-#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16 +-#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF +-#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0 +- +- +- +-#define OFDM_FE_CU_COMM_EXEC__A 0x2010000 +-#define OFDM_FE_CU_COMM_EXEC__W 3 +-#define OFDM_FE_CU_COMM_EXEC__M 0x7 +-#define OFDM_FE_CU_COMM_EXEC__PRE 0x0 +-#define OFDM_FE_CU_COMM_EXEC_STOP 0x0 +-#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2 +-#define OFDM_FE_CU_COMM_EXEC_STEP 0x3 +- +-#define OFDM_FE_CU_COMM_STATE__A 0x2010001 +-#define OFDM_FE_CU_COMM_STATE__W 4 +-#define OFDM_FE_CU_COMM_STATE__M 0xF +-#define OFDM_FE_CU_COMM_STATE__PRE 0x0 +-#define OFDM_FE_CU_COMM_MB__A 0x2010002 +-#define OFDM_FE_CU_COMM_MB__W 2 +-#define OFDM_FE_CU_COMM_MB__M 0x3 +-#define OFDM_FE_CU_COMM_MB__PRE 0x0 +-#define OFDM_FE_CU_COMM_MB_CTL__B 0 +-#define OFDM_FE_CU_COMM_MB_CTL__W 1 +-#define OFDM_FE_CU_COMM_MB_CTL__M 0x1 +-#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0 +-#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0 +-#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1 +-#define OFDM_FE_CU_COMM_MB_OBS__B 1 +-#define OFDM_FE_CU_COMM_MB_OBS__W 1 +-#define OFDM_FE_CU_COMM_MB_OBS__M 0x2 +-#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0 +-#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0 +-#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2 +- +-#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004 +-#define OFDM_FE_CU_COMM_INT_REQ__W 1 +-#define OFDM_FE_CU_COMM_INT_REQ__M 0x1 +-#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005 +-#define OFDM_FE_CU_COMM_INT_STA__W 4 +-#define OFDM_FE_CU_COMM_INT_STA__M 0xF +-#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0 +-#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1 +-#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1 +-#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1 +-#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1 +-#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2 +-#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2 +-#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1 +-#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4 +-#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3 +-#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1 +-#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8 +-#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0 +- +-#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006 +-#define OFDM_FE_CU_COMM_INT_MSK__W 4 +-#define OFDM_FE_CU_COMM_INT_MSK__M 0xF +-#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0 +-#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1 +-#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1 +-#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1 +-#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1 +-#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2 +-#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2 +-#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1 +-#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4 +-#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3 +-#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1 +-#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8 +-#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0 +- +-#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007 +-#define OFDM_FE_CU_COMM_INT_STM__W 4 +-#define OFDM_FE_CU_COMM_INT_STM__M 0xF +-#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0 +-#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1 +-#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1 +-#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1 +-#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1 +-#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2 +-#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2 +-#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1 +-#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4 +-#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0 +-#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3 +-#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1 +-#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8 +-#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0 +- +-#define OFDM_FE_CU_MODE__A 0x2010010 +-#define OFDM_FE_CU_MODE__W 8 +-#define OFDM_FE_CU_MODE__M 0xFF +-#define OFDM_FE_CU_MODE__PRE 0x20 +- +-#define OFDM_FE_CU_MODE_FFT__B 0 +-#define OFDM_FE_CU_MODE_FFT__W 1 +-#define OFDM_FE_CU_MODE_FFT__M 0x1 +-#define OFDM_FE_CU_MODE_FFT__PRE 0x0 +-#define OFDM_FE_CU_MODE_FFT_M8K 0x0 +-#define OFDM_FE_CU_MODE_FFT_M2K 0x1 +- +-#define OFDM_FE_CU_MODE_COR__B 1 +-#define OFDM_FE_CU_MODE_COR__W 1 +-#define OFDM_FE_CU_MODE_COR__M 0x2 +-#define OFDM_FE_CU_MODE_COR__PRE 0x0 +-#define OFDM_FE_CU_MODE_COR_OFF 0x0 +-#define OFDM_FE_CU_MODE_COR_ON 0x2 +- +-#define OFDM_FE_CU_MODE_IFD__B 2 +-#define OFDM_FE_CU_MODE_IFD__W 1 +-#define OFDM_FE_CU_MODE_IFD__M 0x4 +-#define OFDM_FE_CU_MODE_IFD__PRE 0x0 +-#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0 +-#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4 +- +-#define OFDM_FE_CU_MODE_SEL__B 3 +-#define OFDM_FE_CU_MODE_SEL__W 1 +-#define OFDM_FE_CU_MODE_SEL__M 0x8 +-#define OFDM_FE_CU_MODE_SEL__PRE 0x0 +-#define OFDM_FE_CU_MODE_SEL_COR 0x0 +-#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8 +- +-#define OFDM_FE_CU_MODE_FES__B 4 +-#define OFDM_FE_CU_MODE_FES__W 1 +-#define OFDM_FE_CU_MODE_FES__M 0x10 +-#define OFDM_FE_CU_MODE_FES__PRE 0x0 +-#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0 +-#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10 +-#define OFDM_FE_CU_MODE_AVG__B 5 +-#define OFDM_FE_CU_MODE_AVG__W 1 +-#define OFDM_FE_CU_MODE_AVG__M 0x20 +-#define OFDM_FE_CU_MODE_AVG__PRE 0x20 +-#define OFDM_FE_CU_MODE_AVG_OFF 0x0 +-#define OFDM_FE_CU_MODE_AVG_ON 0x20 +-#define OFDM_FE_CU_MODE_SHF_ENA__B 6 +-#define OFDM_FE_CU_MODE_SHF_ENA__W 1 +-#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40 +-#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0 +-#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0 +-#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40 +-#define OFDM_FE_CU_MODE_SHF_DIR__B 7 +-#define OFDM_FE_CU_MODE_SHF_DIR__W 1 +-#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80 +-#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0 +-#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0 +-#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80 +- +- +-#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011 +-#define OFDM_FE_CU_FRM_CNT_RST__W 15 +-#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF +-#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF +- +-#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012 +-#define OFDM_FE_CU_FRM_CNT_STR__W 15 +-#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF +-#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E +- +-#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013 +-#define OFDM_FE_CU_FRM_SMP_CNT__W 15 +-#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF +-#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0 +- +-#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014 +-#define OFDM_FE_CU_FRM_SMB_CNT__W 16 +-#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF +-#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015 +-#define OFDM_FE_CU_CMP_MAX_DAT__W 12 +-#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF +-#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016 +-#define OFDM_FE_CU_CMP_MAX_ADR__W 10 +-#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF +-#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017 +-#define OFDM_FE_CU_CMP_MAX_RE__W 12 +-#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF +-#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018 +-#define OFDM_FE_CU_CMP_MAX_IM__W 12 +-#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF +-#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0 +- +-#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F +-#define OFDM_FE_CU_BUF_NFC_DEL__W 14 +-#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF +-#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0 +- +-#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020 +-#define OFDM_FE_CU_CTR_NFC_ICR__W 5 +-#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F +-#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1 +- +-#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021 +-#define OFDM_FE_CU_CTR_NFC_OCR__W 15 +-#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF +-#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8 +- +-#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022 +-#define OFDM_FE_CU_CTR_NFC_CNT__W 15 +-#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF +-#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0 +- +-#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023 +-#define OFDM_FE_CU_CTR_NFC_STS__W 3 +-#define OFDM_FE_CU_CTR_NFC_STS__M 0x7 +-#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0 +-#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0 +-#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1 +-#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2 +-#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4 +- +- +-#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024 +-#define OFDM_FE_CU_DIV_NFC_REA__W 14 +-#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF +-#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0 +- +-#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025 +-#define OFDM_FE_CU_DIV_NFC_IMA__W 14 +-#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF +-#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0 +- +-#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026 +-#define OFDM_FE_CU_FRM_CNT_UPD__W 15 +-#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF +-#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF +- +-#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027 +-#define OFDM_FE_CU_DIV_NFC_CLP__W 2 +-#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3 +-#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0 +-#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0 +-#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1 +-#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2 +-#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3 +- +- +-#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028 +-#define OFDM_FE_CU_CMP_MAX_32__W 12 +-#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF +-#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029 +-#define OFDM_FE_CU_CMP_MAX_16__W 12 +-#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF +-#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A +-#define OFDM_FE_CU_CMP_MAX_8__W 12 +-#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF +-#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B +-#define OFDM_FE_CU_CMP_MAX_4__W 12 +-#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF +-#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C +-#define OFDM_FE_CU_CMP_SUM_32_RE__W 14 +-#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D +-#define OFDM_FE_CU_CMP_SUM_32_IM__W 14 +-#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E +-#define OFDM_FE_CU_CMP_SUM_16_RE__W 14 +-#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F +-#define OFDM_FE_CU_CMP_SUM_16_IM__W 14 +-#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030 +-#define OFDM_FE_CU_CMP_SUM_8_RE__W 14 +-#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031 +-#define OFDM_FE_CU_CMP_SUM_8_IM__W 14 +-#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032 +-#define OFDM_FE_CU_CMP_SUM_4_RE__W 14 +-#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0 +- +-#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033 +-#define OFDM_FE_CU_CMP_SUM_4_IM__W 14 +-#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF +-#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0 +- +- +- +-#define OFDM_FE_CU_BUF_RAM__A 0x2020000 +- +- +- +-#define OFDM_FE_CU_CMP_RAM__A 0x2030000 +- +- +- +- +- +-#define OFDM_FT_COMM_EXEC__A 0x2400000 +-#define OFDM_FT_COMM_EXEC__W 3 +-#define OFDM_FT_COMM_EXEC__M 0x7 +-#define OFDM_FT_COMM_EXEC__PRE 0x0 +-#define OFDM_FT_COMM_EXEC_STOP 0x0 +-#define OFDM_FT_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_FT_COMM_EXEC_HOLD 0x2 +-#define OFDM_FT_COMM_EXEC_STEP 0x3 +-#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4 +-#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6 +- +-#define OFDM_FT_COMM_STATE__A 0x2400001 +-#define OFDM_FT_COMM_STATE__W 16 +-#define OFDM_FT_COMM_STATE__M 0xFFFF +-#define OFDM_FT_COMM_STATE__PRE 0x0 +-#define OFDM_FT_COMM_MB__A 0x2400002 +-#define OFDM_FT_COMM_MB__W 16 +-#define OFDM_FT_COMM_MB__M 0xFFFF +-#define OFDM_FT_COMM_MB__PRE 0x0 +- +- +- +-#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000 +-#define OFDM_FT_TOP_COMM_EXEC__W 3 +-#define OFDM_FT_TOP_COMM_EXEC__M 0x7 +-#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0 +-#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0 +-#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2 +-#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3 +- +-#define OFDM_FT_TOP_COMM_MB__A 0x2410002 +-#define OFDM_FT_TOP_COMM_MB__W 2 +-#define OFDM_FT_TOP_COMM_MB__M 0x3 +-#define OFDM_FT_TOP_COMM_MB__PRE 0x0 +-#define OFDM_FT_TOP_COMM_MB_CTL__B 0 +-#define OFDM_FT_TOP_COMM_MB_CTL__W 1 +-#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1 +-#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0 +-#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0 +-#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1 +-#define OFDM_FT_TOP_COMM_MB_OBS__B 1 +-#define OFDM_FT_TOP_COMM_MB_OBS__W 1 +-#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2 +-#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0 +-#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0 +-#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2 +- +- +-#define OFDM_FT_TOP_MODE_2K__A 0x2410010 +-#define OFDM_FT_TOP_MODE_2K__W 1 +-#define OFDM_FT_TOP_MODE_2K__M 0x1 +-#define OFDM_FT_TOP_MODE_2K__PRE 0x0 +-#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0 +-#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1 +- +- +-#define OFDM_FT_TOP_NORM_OFF__A 0x2410016 +-#define OFDM_FT_TOP_NORM_OFF__W 4 +-#define OFDM_FT_TOP_NORM_OFF__M 0xF +-#define OFDM_FT_TOP_NORM_OFF__PRE 0x2 +- +- +- +-#define OFDM_FT_0TO2_0_RAM__A 0x2420000 +- +- +- +-#define OFDM_FT_0TO2_1_RAM__A 0x2430000 +- +- +- +-#define OFDM_FT_0TO2_2_RAM__A 0x2440000 +- +- +- +-#define OFDM_FT_3TO7_0_RAM__A 0x2450000 +- +- +- +-#define OFDM_FT_3TO7_1_RAM__A 0x2460000 +- +- +- +- +- +-#define OFDM_LC_COMM_EXEC__A 0x3800000 +-#define OFDM_LC_COMM_EXEC__W 3 +-#define OFDM_LC_COMM_EXEC__M 0x7 +-#define OFDM_LC_COMM_EXEC__PRE 0x0 +-#define OFDM_LC_COMM_EXEC_STOP 0x0 +-#define OFDM_LC_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_LC_COMM_EXEC_HOLD 0x2 +-#define OFDM_LC_COMM_EXEC_STEP 0x3 +-#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4 +-#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6 +- +-#define OFDM_LC_COMM_STATE__A 0x3800001 +-#define OFDM_LC_COMM_STATE__W 16 +-#define OFDM_LC_COMM_STATE__M 0xFFFF +-#define OFDM_LC_COMM_STATE__PRE 0x0 +-#define OFDM_LC_COMM_MB__A 0x3800002 +-#define OFDM_LC_COMM_MB__W 16 +-#define OFDM_LC_COMM_MB__M 0xFFFF +-#define OFDM_LC_COMM_MB__PRE 0x0 +-#define OFDM_LC_COMM_INT_REQ__A 0x3800004 +-#define OFDM_LC_COMM_INT_REQ__W 16 +-#define OFDM_LC_COMM_INT_REQ__M 0xFFFF +-#define OFDM_LC_COMM_INT_REQ__PRE 0x0 +-#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6 +-#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1 +-#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40 +-#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0 +- +-#define OFDM_LC_COMM_INT_STA__A 0x3800005 +-#define OFDM_LC_COMM_INT_STA__W 16 +-#define OFDM_LC_COMM_INT_STA__M 0xFFFF +-#define OFDM_LC_COMM_INT_STA__PRE 0x0 +-#define OFDM_LC_COMM_INT_MSK__A 0x3800006 +-#define OFDM_LC_COMM_INT_MSK__W 16 +-#define OFDM_LC_COMM_INT_MSK__M 0xFFFF +-#define OFDM_LC_COMM_INT_MSK__PRE 0x0 +-#define OFDM_LC_COMM_INT_STM__A 0x3800007 +-#define OFDM_LC_COMM_INT_STM__W 16 +-#define OFDM_LC_COMM_INT_STM__M 0xFFFF +-#define OFDM_LC_COMM_INT_STM__PRE 0x0 +-#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0 +-#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16 +-#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF +-#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0 +- +- +- +-#define OFDM_LC_CT_COMM_EXEC__A 0x3810000 +-#define OFDM_LC_CT_COMM_EXEC__W 3 +-#define OFDM_LC_CT_COMM_EXEC__M 0x7 +-#define OFDM_LC_CT_COMM_EXEC__PRE 0x0 +-#define OFDM_LC_CT_COMM_EXEC_STOP 0x0 +-#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2 +-#define OFDM_LC_CT_COMM_EXEC_STEP 0x3 +- +- +-#define OFDM_LC_CT_COMM_STATE__A 0x3810001 +-#define OFDM_LC_CT_COMM_STATE__W 10 +-#define OFDM_LC_CT_COMM_STATE__M 0x3FF +-#define OFDM_LC_CT_COMM_STATE__PRE 0x0 +-#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004 +-#define OFDM_LC_CT_COMM_INT_REQ__W 1 +-#define OFDM_LC_CT_COMM_INT_REQ__M 0x1 +-#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0 +-#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005 +-#define OFDM_LC_CT_COMM_INT_STA__W 1 +-#define OFDM_LC_CT_COMM_INT_STA__M 0x1 +-#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0 +-#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0 +-#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1 +-#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1 +-#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0 +- +-#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006 +-#define OFDM_LC_CT_COMM_INT_MSK__W 1 +-#define OFDM_LC_CT_COMM_INT_MSK__M 0x1 +-#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0 +-#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0 +-#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1 +-#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1 +-#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 +- +-#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007 +-#define OFDM_LC_CT_COMM_INT_STM__W 1 +-#define OFDM_LC_CT_COMM_INT_STM__M 0x1 +-#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0 +-#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0 +-#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1 +-#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1 +-#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0 +- +- +-#define OFDM_LC_CT_CTL_STK_0__A 0x3810010 +-#define OFDM_LC_CT_CTL_STK_0__W 10 +-#define OFDM_LC_CT_CTL_STK_0__M 0x3FF +-#define OFDM_LC_CT_CTL_STK_0__PRE 0x0 +- +-#define OFDM_LC_CT_CTL_STK_1__A 0x3810011 +-#define OFDM_LC_CT_CTL_STK_1__W 10 +-#define OFDM_LC_CT_CTL_STK_1__M 0x3FF +-#define OFDM_LC_CT_CTL_STK_1__PRE 0x0 +- +-#define OFDM_LC_CT_CTL_STK_2__A 0x3810012 +-#define OFDM_LC_CT_CTL_STK_2__W 10 +-#define OFDM_LC_CT_CTL_STK_2__M 0x3FF +-#define OFDM_LC_CT_CTL_STK_2__PRE 0x0 +- +-#define OFDM_LC_CT_CTL_STK_3__A 0x3810013 +-#define OFDM_LC_CT_CTL_STK_3__W 10 +-#define OFDM_LC_CT_CTL_STK_3__M 0x3FF +-#define OFDM_LC_CT_CTL_STK_3__PRE 0x0 +- +-#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F +-#define OFDM_LC_CT_CTL_BPT_IDX__W 1 +-#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1 +-#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0 +- +-#define OFDM_LC_CT_CTL_BPT__A 0x3810020 +-#define OFDM_LC_CT_CTL_BPT__W 10 +-#define OFDM_LC_CT_CTL_BPT__M 0x3FF +-#define OFDM_LC_CT_CTL_BPT__PRE 0x0 +- +- +- +-#define OFDM_LC_RA_RAM__A 0x3820000 +- +- +- +- +-#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000 +-#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12 +-#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF +-#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0 +- +-#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001 +-#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12 +-#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF +-#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0 +- +-#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002 +-#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12 +-#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF +-#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0 +- +-#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004 +-#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12 +-#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF +-#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0 +- +-#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006 +-#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12 +-#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF +-#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0 +- +-#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007 +-#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12 +-#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF +-#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0 +- +- +- +- +- +- +- +-#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006 +-#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16 +-#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +-#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +-#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007 +-#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16 +-#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +-#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +-#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008 +-#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16 +-#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +-#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009 +-#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16 +-#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +-#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A +-#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16 +-#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF +-#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0 +-#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B +-#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16 +-#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +-#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0 +-#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C +-#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16 +-#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +-#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0 +-#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D +-#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16 +-#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +-#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0 +-#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E +-#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16 +-#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +-#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0 +-#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F +-#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16 +-#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +-#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010 +-#define OFDM_LC_RA_RAM_MODE_2K__W 16 +-#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF +-#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011 +-#define OFDM_LC_RA_RAM_MODE_GUARD__W 16 +-#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF +-#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0 +-#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1 +-#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2 +-#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3 +- +-#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012 +-#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16 +-#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF +-#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000 +-#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0 +- +-#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014 +-#define OFDM_LC_RA_RAM_RC_STS__W 16 +-#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF +-#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A +-#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +-#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B +-#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +-#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C +-#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16 +-#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF +-#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 +-#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D +-#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16 +-#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +-#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F +-#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +-#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020 +-#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +-#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021 +-#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +-#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022 +-#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16 +-#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +-#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0 +-#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023 +-#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16 +-#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +-#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0 +-#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024 +-#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16 +-#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025 +-#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16 +-#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +-#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0 +-#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026 +-#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16 +-#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +-#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0 +-#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027 +-#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16 +-#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF +-#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E +-#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16 +-#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF +-#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16 +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF +-#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0 +- +- +- +- +- +-#define OFDM_SC_COMM_EXEC__A 0x3C00000 +-#define OFDM_SC_COMM_EXEC__W 3 +-#define OFDM_SC_COMM_EXEC__M 0x7 +-#define OFDM_SC_COMM_EXEC__PRE 0x0 +-#define OFDM_SC_COMM_EXEC_STOP 0x0 +-#define OFDM_SC_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_SC_COMM_EXEC_HOLD 0x2 +-#define OFDM_SC_COMM_EXEC_STEP 0x3 +-#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4 +-#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6 +- +-#define OFDM_SC_COMM_STATE__A 0x3C00001 +-#define OFDM_SC_COMM_STATE__W 16 +-#define OFDM_SC_COMM_STATE__M 0xFFFF +-#define OFDM_SC_COMM_STATE__PRE 0x0 +-#define OFDM_SC_COMM_MB__A 0x3C00002 +-#define OFDM_SC_COMM_MB__W 16 +-#define OFDM_SC_COMM_MB__M 0xFFFF +-#define OFDM_SC_COMM_MB__PRE 0x0 +-#define OFDM_SC_COMM_INT_REQ__A 0x3C00004 +-#define OFDM_SC_COMM_INT_REQ__W 16 +-#define OFDM_SC_COMM_INT_REQ__M 0xFFFF +-#define OFDM_SC_COMM_INT_REQ__PRE 0x0 +-#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7 +-#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1 +-#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80 +-#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0 +- +-#define OFDM_SC_COMM_INT_STA__A 0x3C00005 +-#define OFDM_SC_COMM_INT_STA__W 16 +-#define OFDM_SC_COMM_INT_STA__M 0xFFFF +-#define OFDM_SC_COMM_INT_STA__PRE 0x0 +-#define OFDM_SC_COMM_INT_MSK__A 0x3C00006 +-#define OFDM_SC_COMM_INT_MSK__W 16 +-#define OFDM_SC_COMM_INT_MSK__M 0xFFFF +-#define OFDM_SC_COMM_INT_MSK__PRE 0x0 +-#define OFDM_SC_COMM_INT_STM__A 0x3C00007 +-#define OFDM_SC_COMM_INT_STM__W 16 +-#define OFDM_SC_COMM_INT_STM__M 0xFFFF +-#define OFDM_SC_COMM_INT_STM__PRE 0x0 +-#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0 +-#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16 +-#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF +-#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0 +- +- +- +-#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000 +-#define OFDM_SC_CT_COMM_EXEC__W 3 +-#define OFDM_SC_CT_COMM_EXEC__M 0x7 +-#define OFDM_SC_CT_COMM_EXEC__PRE 0x0 +-#define OFDM_SC_CT_COMM_EXEC_STOP 0x0 +-#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1 +-#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2 +-#define OFDM_SC_CT_COMM_EXEC_STEP 0x3 +- +- +-#define OFDM_SC_CT_COMM_STATE__A 0x3C10001 +-#define OFDM_SC_CT_COMM_STATE__W 10 +-#define OFDM_SC_CT_COMM_STATE__M 0x3FF +-#define OFDM_SC_CT_COMM_STATE__PRE 0x0 +-#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004 +-#define OFDM_SC_CT_COMM_INT_REQ__W 1 +-#define OFDM_SC_CT_COMM_INT_REQ__M 0x1 +-#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0 +-#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005 +-#define OFDM_SC_CT_COMM_INT_STA__W 1 +-#define OFDM_SC_CT_COMM_INT_STA__M 0x1 +-#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0 +-#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0 +-#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1 +-#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1 +-#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0 +- +-#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006 +-#define OFDM_SC_CT_COMM_INT_MSK__W 1 +-#define OFDM_SC_CT_COMM_INT_MSK__M 0x1 +-#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0 +-#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0 +-#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1 +-#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1 +-#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 +- +-#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007 +-#define OFDM_SC_CT_COMM_INT_STM__W 1 +-#define OFDM_SC_CT_COMM_INT_STM__M 0x1 +-#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0 +-#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0 +-#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1 +-#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1 +-#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0 +- +- +-#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010 +-#define OFDM_SC_CT_CTL_STK_0__W 10 +-#define OFDM_SC_CT_CTL_STK_0__M 0x3FF +-#define OFDM_SC_CT_CTL_STK_0__PRE 0x0 +- +-#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011 +-#define OFDM_SC_CT_CTL_STK_1__W 10 +-#define OFDM_SC_CT_CTL_STK_1__M 0x3FF +-#define OFDM_SC_CT_CTL_STK_1__PRE 0x0 +- +-#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012 +-#define OFDM_SC_CT_CTL_STK_2__W 10 +-#define OFDM_SC_CT_CTL_STK_2__M 0x3FF +-#define OFDM_SC_CT_CTL_STK_2__PRE 0x0 +- +-#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013 +-#define OFDM_SC_CT_CTL_STK_3__W 10 +-#define OFDM_SC_CT_CTL_STK_3__M 0x3FF +-#define OFDM_SC_CT_CTL_STK_3__PRE 0x0 +- +-#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F +-#define OFDM_SC_CT_CTL_BPT_IDX__W 1 +-#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1 +-#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0 +- +-#define OFDM_SC_CT_CTL_BPT__A 0x3C10020 +-#define OFDM_SC_CT_CTL_BPT__W 13 +-#define OFDM_SC_CT_CTL_BPT__M 0x1FFF +-#define OFDM_SC_CT_CTL_BPT__PRE 0x0 +- +- +- +-#define OFDM_SC_RA_RAM__A 0x3C20000 +- +- +- +- +-#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000 +-#define OFDM_SC_IF_RAM_TRP_RST_0__W 12 +-#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF +-#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0 +- +-#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001 +-#define OFDM_SC_IF_RAM_TRP_RST_1__W 12 +-#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF +-#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0 +- +-#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002 +-#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12 +-#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF +-#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0 +- +-#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004 +-#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12 +-#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF +-#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0 +- +-#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004 +-#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12 +-#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF +-#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0 +- +-#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005 +-#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12 +-#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF +-#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0 +- +-#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE +-#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12 +-#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF +-#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0 +- +-#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF +-#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12 +-#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF +-#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0 +- +- +- +- +- +- +- +-#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +-#define OFDM_SC_RA_RAM_PARAM0__W 16 +-#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +-#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +-#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +-#define OFDM_SC_RA_RAM_PARAM1__W 16 +-#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +-#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +-#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 +-#define OFDM_SC_RA_RAM_CMD_ADDR__W 16 +-#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF +-#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0 +-#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 +-#define OFDM_SC_RA_RAM_CMD__W 16 +-#define OFDM_SC_RA_RAM_CMD__M 0xFFFF +-#define OFDM_SC_RA_RAM_CMD__PRE 0x0 +-#define OFDM_SC_RA_RAM_CMD_NULL 0x0 +-#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +-#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +-#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +-#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +-#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +-#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 +-#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 +-#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +-#define OFDM_SC_RA_RAM_CMD_MAX 0x9 +-#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4 +- +-#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044 +-#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16 +-#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +-#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +-#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045 +-#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16 +-#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +-#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046 +-#define OFDM_SC_RA_RAM_SW_EVENT__W 14 +-#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF +-#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2 +-#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +-#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +-#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3 +-#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +-#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4 +-#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +-#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +-#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7 +-#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +-#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +-#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0 +-#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12 +-#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1 +-#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 +-#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0 +- +-#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047 +-#define OFDM_SC_RA_RAM_LOCKTRACK__W 16 +-#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF +-#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0 +-#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0 +-#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 +-#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1 +-#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +-#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3 +-#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4 +-#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5 +-#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6 +-#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7 +-#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8 +-#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9 +- +-#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 +-#define OFDM_SC_RA_RAM_OP_PARAM__W 13 +-#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF +-#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +-#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +-#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +-#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +-#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +-#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4 +-#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2 +-#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30 +-#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +-#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +-#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +-#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12 +-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1 +-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +-#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 +- +-#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049 +-#define OFDM_SC_RA_RAM_OP_AUTO__W 6 +-#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F +-#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F +-#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0 +-#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1 +-#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +-#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1 +-#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1 +-#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1 +-#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +-#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2 +-#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2 +-#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1 +-#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +-#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4 +-#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3 +-#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1 +-#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +-#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8 +-#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4 +-#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1 +-#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +-#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10 +-#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5 +-#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1 +-#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 +-#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0 +- +-#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A +-#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16 +-#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0 +-#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0 +-#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +-#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 +-#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 +- +-#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B +-#define OFDM_SC_RA_RAM_LOCK__W 4 +-#define OFDM_SC_RA_RAM_LOCK__M 0xF +-#define OFDM_SC_RA_RAM_LOCK__PRE 0x0 +-#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0 +-#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1 +-#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 +-#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0 +-#define OFDM_SC_RA_RAM_LOCK_FEC__B 1 +-#define OFDM_SC_RA_RAM_LOCK_FEC__W 1 +-#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 +-#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0 +-#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2 +-#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1 +-#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 +-#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0 +-#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3 +-#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1 +-#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 +-#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0 +- +-#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C +-#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F +-#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10 +-#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10 +- +-#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D +-#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16 +-#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +-#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80 +-#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E +-#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +-#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +-#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +-#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +-#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 +-#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 +-#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 +-#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 +-#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF +-#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 +-#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 +-#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 +-#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 +-#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 +- +-#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 +-#define OFDM_SC_RA_RAM_CONFIG__W 16 +-#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF +-#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14 +-#define OFDM_SC_RA_RAM_CONFIG_ID__B 0 +-#define OFDM_SC_RA_RAM_CONFIG_ID__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1 +-#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1 +-#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +-#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +-#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +-#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +-#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4 +-#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3 +-#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +-#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4 +-#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +-#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10 +-#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5 +-#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20 +-#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6 +-#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +-#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +-#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +-#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +-#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +-#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 +-#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11 +-#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 +-#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0 +-#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +-#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +-#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 +-#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0 +- +-#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054 +-#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 +-#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF +-#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 +-#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055 +-#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16 +-#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 +-#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056 +-#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16 +-#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057 +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058 +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16 +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 +-#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059 +-#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16 +-#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 +-#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A +-#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16 +-#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1 +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16 +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1 +-#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D +-#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16 +-#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF +-#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB +-#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E +-#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16 +-#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF +-#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 +-#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F +-#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16 +-#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +-#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE +-#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E +-#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16 +-#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1 +-#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F +-#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16 +-#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16 +-#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 +-#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C +-#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 +-#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 +-#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D +-#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 +-#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF +-#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C +-#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E +-#define OFDM_SC_RA_RAM_STATUS__W 16 +-#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF +-#define OFDM_SC_RA_RAM_STATUS__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F +-#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16 +-#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 +-#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080 +-#define OFDM_SC_RA_RAM_TIMER__W 16 +-#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF +-#define OFDM_SC_RA_RAM_TIMER__PRE 0x0 +-#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081 +-#define OFDM_SC_RA_RAM_FI_OFFSET__W 16 +-#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF +-#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382 +-#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082 +-#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16 +-#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18 +-#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D +-#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16 +-#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF +-#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640 +-#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E +-#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16 +-#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF +-#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0 +-#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F +-#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16 +-#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF +-#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF +-#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC +-#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2 +-#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16 +-#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF +-#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8 +-#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7 +-#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16 +-#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF +-#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230 +-#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8 +-#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16 +-#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF +-#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320 +-#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9 +-#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16 +-#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF +-#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400 +- +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16 +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3 +-#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC +-#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16 +-#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6 +-#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD +-#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16 +-#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28 +-#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE +-#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16 +-#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6 +-#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF +-#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16 +-#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF +-#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14 +-#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0 +-#define OFDM_SC_RA_RAM_IR_FREQ__W 16 +-#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +-#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 +-#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA +-#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +-#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +-#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB +-#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +-#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +-#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC +-#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +-#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +-#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 +-#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE +-#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16 +-#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 +-#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400 +- +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +-#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +-#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +-#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +-#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +-#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +-#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 +-#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7 +-#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16 +-#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF +-#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2 +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8 +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9 +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +-#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16 +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +-#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC +-#define OFDM_SC_RA_RAM_BAND__W 16 +-#define OFDM_SC_RA_RAM_BAND__M 0xFFFF +-#define OFDM_SC_RA_RAM_BAND__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF +-#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +-#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 +-#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0 +- +-#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED +-#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +-#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +-#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16 +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19 +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16 +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF +-#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B +-#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0 +-#define OFDM_SC_RA_RAM_REG_0__W 16 +-#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF +-#define OFDM_SC_RA_RAM_REG_0__PRE 0x0 +-#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1 +-#define OFDM_SC_RA_RAM_REG_1__W 16 +-#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF +-#define OFDM_SC_RA_RAM_REG_1__PRE 0x0 +-#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2 +-#define OFDM_SC_RA_RAM_BREAK__W 16 +-#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF +-#define OFDM_SC_RA_RAM_BREAK__PRE 0x0 +-#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3 +-#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16 +-#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF +-#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0 +-#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4 +-#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16 +-#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF +-#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F +-#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5 +-#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16 +-#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF +-#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F +-#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6 +-#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16 +-#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF +-#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1 +-#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7 +-#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 +-#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF +-#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF +-#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F +- +-#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9 +-#define OFDM_SC_RA_RAM_LC_CP__W 16 +-#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF +-#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1 +-#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA +-#define OFDM_SC_RA_RAM_LC_DIFF__W 16 +-#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF +-#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7 +-#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB +-#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16 +-#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58 +-#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC +-#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16 +-#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0 +- +-#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD +-#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16 +-#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF +-#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38 +-#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE +-#define OFDM_SC_RA_RAM_RELOCK__W 16 +-#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF +-#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0 +-#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF +-#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16 +-#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF +-#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148 +-#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +-#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149 +-#define OFDM_SC_RA_RAM_NF_PREPOST__W 16 +-#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A +-#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16 +-#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B +-#define OFDM_SC_RA_RAM_NF_START__W 16 +-#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_START__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C +-#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16 +-#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D +-#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16 +-#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F +-#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16 +-#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16 +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF +-#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +-#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16 +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0 +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16 +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF +-#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0 +- +- +- +- +- +-#define QAM_COMM_EXEC__A 0x1400000 +-#define QAM_COMM_EXEC__W 2 +-#define QAM_COMM_EXEC__M 0x3 +-#define QAM_COMM_EXEC__PRE 0x0 +-#define QAM_COMM_EXEC_STOP 0x0 +-#define QAM_COMM_EXEC_ACTIVE 0x1 +-#define QAM_COMM_EXEC_HOLD 0x2 +- +-#define QAM_COMM_MB__A 0x1400002 +-#define QAM_COMM_MB__W 16 +-#define QAM_COMM_MB__M 0xFFFF +-#define QAM_COMM_MB__PRE 0x0 +-#define QAM_COMM_INT_REQ__A 0x1400003 +-#define QAM_COMM_INT_REQ__W 16 +-#define QAM_COMM_INT_REQ__M 0xFFFF +-#define QAM_COMM_INT_REQ__PRE 0x0 +- +-#define QAM_COMM_INT_REQ_SL_REQ__B 0 +-#define QAM_COMM_INT_REQ_SL_REQ__W 1 +-#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +-#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 +- +-#define QAM_COMM_INT_REQ_LC_REQ__B 1 +-#define QAM_COMM_INT_REQ_LC_REQ__W 1 +-#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +-#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 +- +-#define QAM_COMM_INT_REQ_VD_REQ__B 2 +-#define QAM_COMM_INT_REQ_VD_REQ__W 1 +-#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +-#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 +- +-#define QAM_COMM_INT_REQ_SY_REQ__B 3 +-#define QAM_COMM_INT_REQ_SY_REQ__W 1 +-#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +-#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 +- +-#define QAM_COMM_INT_STA__A 0x1400005 +-#define QAM_COMM_INT_STA__W 16 +-#define QAM_COMM_INT_STA__M 0xFFFF +-#define QAM_COMM_INT_STA__PRE 0x0 +-#define QAM_COMM_INT_MSK__A 0x1400006 +-#define QAM_COMM_INT_MSK__W 16 +-#define QAM_COMM_INT_MSK__M 0xFFFF +-#define QAM_COMM_INT_MSK__PRE 0x0 +-#define QAM_COMM_INT_STM__A 0x1400007 +-#define QAM_COMM_INT_STM__W 16 +-#define QAM_COMM_INT_STM__M 0xFFFF +-#define QAM_COMM_INT_STM__PRE 0x0 +- +- +- +-#define QAM_TOP_COMM_EXEC__A 0x1410000 +-#define QAM_TOP_COMM_EXEC__W 2 +-#define QAM_TOP_COMM_EXEC__M 0x3 +-#define QAM_TOP_COMM_EXEC__PRE 0x0 +-#define QAM_TOP_COMM_EXEC_STOP 0x0 +-#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +-#define QAM_TOP_COMM_EXEC_HOLD 0x2 +- +- +-#define QAM_TOP_ANNEX__A 0x1410010 +-#define QAM_TOP_ANNEX__W 2 +-#define QAM_TOP_ANNEX__M 0x3 +-#define QAM_TOP_ANNEX__PRE 0x0 +-#define QAM_TOP_ANNEX_A 0x0 +-#define QAM_TOP_ANNEX_B 0x1 +-#define QAM_TOP_ANNEX_C 0x2 +-#define QAM_TOP_ANNEX_D 0x3 +- +- +-#define QAM_TOP_CONSTELLATION__A 0x1410011 +-#define QAM_TOP_CONSTELLATION__W 3 +-#define QAM_TOP_CONSTELLATION__M 0x7 +-#define QAM_TOP_CONSTELLATION__PRE 0x5 +-#define QAM_TOP_CONSTELLATION_NONE 0x0 +-#define QAM_TOP_CONSTELLATION_QPSK 0x1 +-#define QAM_TOP_CONSTELLATION_QAM8 0x2 +-#define QAM_TOP_CONSTELLATION_QAM16 0x3 +-#define QAM_TOP_CONSTELLATION_QAM32 0x4 +-#define QAM_TOP_CONSTELLATION_QAM64 0x5 +-#define QAM_TOP_CONSTELLATION_QAM128 0x6 +-#define QAM_TOP_CONSTELLATION_QAM256 0x7 +- +- +- +-#define QAM_FQ_COMM_EXEC__A 0x1420000 +-#define QAM_FQ_COMM_EXEC__W 2 +-#define QAM_FQ_COMM_EXEC__M 0x3 +-#define QAM_FQ_COMM_EXEC__PRE 0x0 +-#define QAM_FQ_COMM_EXEC_STOP 0x0 +-#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +-#define QAM_FQ_COMM_EXEC_HOLD 0x2 +- +-#define QAM_FQ_MODE__A 0x1420010 +-#define QAM_FQ_MODE__W 3 +-#define QAM_FQ_MODE__M 0x7 +-#define QAM_FQ_MODE__PRE 0x0 +- +-#define QAM_FQ_MODE_TAPRESET__B 0 +-#define QAM_FQ_MODE_TAPRESET__W 1 +-#define QAM_FQ_MODE_TAPRESET__M 0x1 +-#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +-#define QAM_FQ_MODE_TAPRESET_RST 0x1 +- +-#define QAM_FQ_MODE_TAPLMS__B 1 +-#define QAM_FQ_MODE_TAPLMS__W 1 +-#define QAM_FQ_MODE_TAPLMS__M 0x2 +-#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +-#define QAM_FQ_MODE_TAPLMS_UPD 0x2 +- +-#define QAM_FQ_MODE_TAPDRAIN__B 2 +-#define QAM_FQ_MODE_TAPDRAIN__W 1 +-#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +-#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +-#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 +- +- +-#define QAM_FQ_MU_FACTOR__A 0x1420011 +-#define QAM_FQ_MU_FACTOR__W 3 +-#define QAM_FQ_MU_FACTOR__M 0x7 +-#define QAM_FQ_MU_FACTOR__PRE 0x0 +- +-#define QAM_FQ_LA_FACTOR__A 0x1420012 +-#define QAM_FQ_LA_FACTOR__W 4 +-#define QAM_FQ_LA_FACTOR__M 0xF +-#define QAM_FQ_LA_FACTOR__PRE 0xC +-#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +-#define QAM_FQ_CENTTAP_IDX__W 5 +-#define QAM_FQ_CENTTAP_IDX__M 0x1F +-#define QAM_FQ_CENTTAP_IDX__PRE 0x13 +- +-#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +-#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +-#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +-#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 +- +-#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +-#define QAM_FQ_CENTTAP_VALUE__W 12 +-#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +-#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 +- +-#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +-#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +-#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +-#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 +- +-#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +-#define QAM_FQ_TAP_RE_EL0__W 12 +-#define QAM_FQ_TAP_RE_EL0__M 0xFFF +-#define QAM_FQ_TAP_RE_EL0__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +-#define QAM_FQ_TAP_IM_EL0__W 12 +-#define QAM_FQ_TAP_IM_EL0__M 0xFFF +-#define QAM_FQ_TAP_IM_EL0__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +-#define QAM_FQ_TAP_RE_EL1__W 12 +-#define QAM_FQ_TAP_RE_EL1__M 0xFFF +-#define QAM_FQ_TAP_RE_EL1__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +-#define QAM_FQ_TAP_IM_EL1__W 12 +-#define QAM_FQ_TAP_IM_EL1__M 0xFFF +-#define QAM_FQ_TAP_IM_EL1__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +-#define QAM_FQ_TAP_RE_EL2__W 12 +-#define QAM_FQ_TAP_RE_EL2__M 0xFFF +-#define QAM_FQ_TAP_RE_EL2__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +-#define QAM_FQ_TAP_IM_EL2__W 12 +-#define QAM_FQ_TAP_IM_EL2__M 0xFFF +-#define QAM_FQ_TAP_IM_EL2__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +-#define QAM_FQ_TAP_RE_EL3__W 12 +-#define QAM_FQ_TAP_RE_EL3__M 0xFFF +-#define QAM_FQ_TAP_RE_EL3__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +-#define QAM_FQ_TAP_IM_EL3__W 12 +-#define QAM_FQ_TAP_IM_EL3__M 0xFFF +-#define QAM_FQ_TAP_IM_EL3__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +-#define QAM_FQ_TAP_RE_EL4__W 12 +-#define QAM_FQ_TAP_RE_EL4__M 0xFFF +-#define QAM_FQ_TAP_RE_EL4__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +-#define QAM_FQ_TAP_IM_EL4__W 12 +-#define QAM_FQ_TAP_IM_EL4__M 0xFFF +-#define QAM_FQ_TAP_IM_EL4__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL5__A 0x142002A +-#define QAM_FQ_TAP_RE_EL5__W 12 +-#define QAM_FQ_TAP_RE_EL5__M 0xFFF +-#define QAM_FQ_TAP_RE_EL5__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL5__A 0x142002B +-#define QAM_FQ_TAP_IM_EL5__W 12 +-#define QAM_FQ_TAP_IM_EL5__M 0xFFF +-#define QAM_FQ_TAP_IM_EL5__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL6__A 0x142002C +-#define QAM_FQ_TAP_RE_EL6__W 12 +-#define QAM_FQ_TAP_RE_EL6__M 0xFFF +-#define QAM_FQ_TAP_RE_EL6__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL6__A 0x142002D +-#define QAM_FQ_TAP_IM_EL6__W 12 +-#define QAM_FQ_TAP_IM_EL6__M 0xFFF +-#define QAM_FQ_TAP_IM_EL6__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL7__A 0x142002E +-#define QAM_FQ_TAP_RE_EL7__W 12 +-#define QAM_FQ_TAP_RE_EL7__M 0xFFF +-#define QAM_FQ_TAP_RE_EL7__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL7__A 0x142002F +-#define QAM_FQ_TAP_IM_EL7__W 12 +-#define QAM_FQ_TAP_IM_EL7__M 0xFFF +-#define QAM_FQ_TAP_IM_EL7__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +-#define QAM_FQ_TAP_RE_EL8__W 12 +-#define QAM_FQ_TAP_RE_EL8__M 0xFFF +-#define QAM_FQ_TAP_RE_EL8__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +-#define QAM_FQ_TAP_IM_EL8__W 12 +-#define QAM_FQ_TAP_IM_EL8__M 0xFFF +-#define QAM_FQ_TAP_IM_EL8__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +-#define QAM_FQ_TAP_RE_EL9__W 12 +-#define QAM_FQ_TAP_RE_EL9__M 0xFFF +-#define QAM_FQ_TAP_RE_EL9__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +-#define QAM_FQ_TAP_IM_EL9__W 12 +-#define QAM_FQ_TAP_IM_EL9__M 0xFFF +-#define QAM_FQ_TAP_IM_EL9__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +-#define QAM_FQ_TAP_RE_EL10__W 12 +-#define QAM_FQ_TAP_RE_EL10__M 0xFFF +-#define QAM_FQ_TAP_RE_EL10__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +-#define QAM_FQ_TAP_IM_EL10__W 12 +-#define QAM_FQ_TAP_IM_EL10__M 0xFFF +-#define QAM_FQ_TAP_IM_EL10__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +-#define QAM_FQ_TAP_RE_EL11__W 12 +-#define QAM_FQ_TAP_RE_EL11__M 0xFFF +-#define QAM_FQ_TAP_RE_EL11__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +-#define QAM_FQ_TAP_IM_EL11__W 12 +-#define QAM_FQ_TAP_IM_EL11__M 0xFFF +-#define QAM_FQ_TAP_IM_EL11__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +-#define QAM_FQ_TAP_RE_EL12__W 12 +-#define QAM_FQ_TAP_RE_EL12__M 0xFFF +-#define QAM_FQ_TAP_RE_EL12__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +-#define QAM_FQ_TAP_IM_EL12__W 12 +-#define QAM_FQ_TAP_IM_EL12__M 0xFFF +-#define QAM_FQ_TAP_IM_EL12__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL13__A 0x142003A +-#define QAM_FQ_TAP_RE_EL13__W 12 +-#define QAM_FQ_TAP_RE_EL13__M 0xFFF +-#define QAM_FQ_TAP_RE_EL13__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL13__A 0x142003B +-#define QAM_FQ_TAP_IM_EL13__W 12 +-#define QAM_FQ_TAP_IM_EL13__M 0xFFF +-#define QAM_FQ_TAP_IM_EL13__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL14__A 0x142003C +-#define QAM_FQ_TAP_RE_EL14__W 12 +-#define QAM_FQ_TAP_RE_EL14__M 0xFFF +-#define QAM_FQ_TAP_RE_EL14__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL14__A 0x142003D +-#define QAM_FQ_TAP_IM_EL14__W 12 +-#define QAM_FQ_TAP_IM_EL14__M 0xFFF +-#define QAM_FQ_TAP_IM_EL14__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL15__A 0x142003E +-#define QAM_FQ_TAP_RE_EL15__W 12 +-#define QAM_FQ_TAP_RE_EL15__M 0xFFF +-#define QAM_FQ_TAP_RE_EL15__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL15__A 0x142003F +-#define QAM_FQ_TAP_IM_EL15__W 12 +-#define QAM_FQ_TAP_IM_EL15__M 0xFFF +-#define QAM_FQ_TAP_IM_EL15__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +-#define QAM_FQ_TAP_RE_EL16__W 12 +-#define QAM_FQ_TAP_RE_EL16__M 0xFFF +-#define QAM_FQ_TAP_RE_EL16__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +-#define QAM_FQ_TAP_IM_EL16__W 12 +-#define QAM_FQ_TAP_IM_EL16__M 0xFFF +-#define QAM_FQ_TAP_IM_EL16__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +-#define QAM_FQ_TAP_RE_EL17__W 12 +-#define QAM_FQ_TAP_RE_EL17__M 0xFFF +-#define QAM_FQ_TAP_RE_EL17__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +-#define QAM_FQ_TAP_IM_EL17__W 12 +-#define QAM_FQ_TAP_IM_EL17__M 0xFFF +-#define QAM_FQ_TAP_IM_EL17__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +-#define QAM_FQ_TAP_RE_EL18__W 12 +-#define QAM_FQ_TAP_RE_EL18__M 0xFFF +-#define QAM_FQ_TAP_RE_EL18__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +-#define QAM_FQ_TAP_IM_EL18__W 12 +-#define QAM_FQ_TAP_IM_EL18__M 0xFFF +-#define QAM_FQ_TAP_IM_EL18__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +-#define QAM_FQ_TAP_RE_EL19__W 12 +-#define QAM_FQ_TAP_RE_EL19__M 0xFFF +-#define QAM_FQ_TAP_RE_EL19__PRE 0x600 +- +-#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 +- +-#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +-#define QAM_FQ_TAP_IM_EL19__W 12 +-#define QAM_FQ_TAP_IM_EL19__M 0xFFF +-#define QAM_FQ_TAP_IM_EL19__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +-#define QAM_FQ_TAP_RE_EL20__W 12 +-#define QAM_FQ_TAP_RE_EL20__M 0xFFF +-#define QAM_FQ_TAP_RE_EL20__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +-#define QAM_FQ_TAP_IM_EL20__W 12 +-#define QAM_FQ_TAP_IM_EL20__M 0xFFF +-#define QAM_FQ_TAP_IM_EL20__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL21__A 0x142004A +-#define QAM_FQ_TAP_RE_EL21__W 12 +-#define QAM_FQ_TAP_RE_EL21__M 0xFFF +-#define QAM_FQ_TAP_RE_EL21__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL21__A 0x142004B +-#define QAM_FQ_TAP_IM_EL21__W 12 +-#define QAM_FQ_TAP_IM_EL21__M 0xFFF +-#define QAM_FQ_TAP_IM_EL21__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL22__A 0x142004C +-#define QAM_FQ_TAP_RE_EL22__W 12 +-#define QAM_FQ_TAP_RE_EL22__M 0xFFF +-#define QAM_FQ_TAP_RE_EL22__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL22__A 0x142004D +-#define QAM_FQ_TAP_IM_EL22__W 12 +-#define QAM_FQ_TAP_IM_EL22__M 0xFFF +-#define QAM_FQ_TAP_IM_EL22__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL23__A 0x142004E +-#define QAM_FQ_TAP_RE_EL23__W 12 +-#define QAM_FQ_TAP_RE_EL23__M 0xFFF +-#define QAM_FQ_TAP_RE_EL23__PRE 0x2 +- +-#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +-#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +-#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +-#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL23__A 0x142004F +-#define QAM_FQ_TAP_IM_EL23__W 12 +-#define QAM_FQ_TAP_IM_EL23__M 0xFFF +-#define QAM_FQ_TAP_IM_EL23__PRE 0x2 +- +-#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +-#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +-#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +-#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 +- +- +- +-#define QAM_SL_COMM_EXEC__A 0x1430000 +-#define QAM_SL_COMM_EXEC__W 2 +-#define QAM_SL_COMM_EXEC__M 0x3 +-#define QAM_SL_COMM_EXEC__PRE 0x0 +-#define QAM_SL_COMM_EXEC_STOP 0x0 +-#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +-#define QAM_SL_COMM_EXEC_HOLD 0x2 +- +-#define QAM_SL_COMM_MB__A 0x1430002 +-#define QAM_SL_COMM_MB__W 4 +-#define QAM_SL_COMM_MB__M 0xF +-#define QAM_SL_COMM_MB__PRE 0x0 +-#define QAM_SL_COMM_MB_CTL__B 0 +-#define QAM_SL_COMM_MB_CTL__W 1 +-#define QAM_SL_COMM_MB_CTL__M 0x1 +-#define QAM_SL_COMM_MB_CTL__PRE 0x0 +-#define QAM_SL_COMM_MB_CTL_OFF 0x0 +-#define QAM_SL_COMM_MB_CTL_ON 0x1 +-#define QAM_SL_COMM_MB_OBS__B 1 +-#define QAM_SL_COMM_MB_OBS__W 1 +-#define QAM_SL_COMM_MB_OBS__M 0x2 +-#define QAM_SL_COMM_MB_OBS__PRE 0x0 +-#define QAM_SL_COMM_MB_OBS_OFF 0x0 +-#define QAM_SL_COMM_MB_OBS_ON 0x2 +-#define QAM_SL_COMM_MB_MUX_OBS__B 2 +-#define QAM_SL_COMM_MB_MUX_OBS__W 2 +-#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +-#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +-#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +-#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +-#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +-#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC +- +-#define QAM_SL_COMM_INT_REQ__A 0x1430003 +-#define QAM_SL_COMM_INT_REQ__W 1 +-#define QAM_SL_COMM_INT_REQ__M 0x1 +-#define QAM_SL_COMM_INT_REQ__PRE 0x0 +-#define QAM_SL_COMM_INT_STA__A 0x1430005 +-#define QAM_SL_COMM_INT_STA__W 2 +-#define QAM_SL_COMM_INT_STA__M 0x3 +-#define QAM_SL_COMM_INT_STA__PRE 0x0 +- +-#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +-#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +-#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +-#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 +- +-#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +-#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +-#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +-#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 +- +-#define QAM_SL_COMM_INT_MSK__A 0x1430006 +-#define QAM_SL_COMM_INT_MSK__W 2 +-#define QAM_SL_COMM_INT_MSK__M 0x3 +-#define QAM_SL_COMM_INT_MSK__PRE 0x0 +-#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +-#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +-#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +-#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +-#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +-#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +-#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +-#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 +- +-#define QAM_SL_COMM_INT_STM__A 0x1430007 +-#define QAM_SL_COMM_INT_STM__W 2 +-#define QAM_SL_COMM_INT_STM__M 0x3 +-#define QAM_SL_COMM_INT_STM__PRE 0x0 +-#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +-#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +-#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +-#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +-#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +-#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +-#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +-#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 +- +-#define QAM_SL_MODE__A 0x1430010 +-#define QAM_SL_MODE__W 11 +-#define QAM_SL_MODE__M 0x7FF +-#define QAM_SL_MODE__PRE 0xA +- +-#define QAM_SL_MODE_SLICER4LC__B 0 +-#define QAM_SL_MODE_SLICER4LC__W 2 +-#define QAM_SL_MODE_SLICER4LC__M 0x3 +-#define QAM_SL_MODE_SLICER4LC__PRE 0x2 +-#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +-#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +-#define QAM_SL_MODE_SLICER4LC_RAD 0x2 +- +-#define QAM_SL_MODE_SLICER4DQ__B 2 +-#define QAM_SL_MODE_SLICER4DQ__W 2 +-#define QAM_SL_MODE_SLICER4DQ__M 0xC +-#define QAM_SL_MODE_SLICER4DQ__PRE 0x8 +-#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +-#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +-#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 +- +-#define QAM_SL_MODE_SLICER4VD__B 4 +-#define QAM_SL_MODE_SLICER4VD__W 2 +-#define QAM_SL_MODE_SLICER4VD__M 0x30 +-#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +-#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +-#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +-#define QAM_SL_MODE_SLICER4VD_RAD 0x20 +- +-#define QAM_SL_MODE_ROT_DIS__B 6 +-#define QAM_SL_MODE_ROT_DIS__W 1 +-#define QAM_SL_MODE_ROT_DIS__M 0x40 +-#define QAM_SL_MODE_ROT_DIS__PRE 0x0 +-#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0 +-#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40 +- +-#define QAM_SL_MODE_DQROT_DIS__B 7 +-#define QAM_SL_MODE_DQROT_DIS__W 1 +-#define QAM_SL_MODE_DQROT_DIS__M 0x80 +-#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 +-#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0 +-#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80 +- +-#define QAM_SL_MODE_DFE_DIS__B 8 +-#define QAM_SL_MODE_DFE_DIS__W 1 +-#define QAM_SL_MODE_DFE_DIS__M 0x100 +-#define QAM_SL_MODE_DFE_DIS__PRE 0x0 +-#define QAM_SL_MODE_DFE_DIS_DQ 0x0 +-#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100 +- +-#define QAM_SL_MODE_RADIUS_MIX__B 9 +-#define QAM_SL_MODE_RADIUS_MIX__W 1 +-#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +-#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 +-#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0 +-#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200 +- +-#define QAM_SL_MODE_TILT_COMP__B 10 +-#define QAM_SL_MODE_TILT_COMP__W 1 +-#define QAM_SL_MODE_TILT_COMP__M 0x400 +-#define QAM_SL_MODE_TILT_COMP__PRE 0x0 +-#define QAM_SL_MODE_TILT_COMP_OFF 0x0 +-#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400 +- +- +-#define QAM_SL_K_FACTOR__A 0x1430011 +-#define QAM_SL_K_FACTOR__W 4 +-#define QAM_SL_K_FACTOR__M 0xF +-#define QAM_SL_K_FACTOR__PRE 0xC +-#define QAM_SL_MEDIAN__A 0x1430012 +-#define QAM_SL_MEDIAN__W 14 +-#define QAM_SL_MEDIAN__M 0x3FFF +-#define QAM_SL_MEDIAN__PRE 0x2C86 +- +-#define QAM_SL_MEDIAN_LENGTH__B 0 +-#define QAM_SL_MEDIAN_LENGTH__W 2 +-#define QAM_SL_MEDIAN_LENGTH__M 0x3 +-#define QAM_SL_MEDIAN_LENGTH__PRE 0x2 +-#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0 +-#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1 +-#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2 +-#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3 +- +-#define QAM_SL_MEDIAN_CORRECT__B 2 +-#define QAM_SL_MEDIAN_CORRECT__W 4 +-#define QAM_SL_MEDIAN_CORRECT__M 0x3C +-#define QAM_SL_MEDIAN_CORRECT__PRE 0x4 +- +-#define QAM_SL_MEDIAN_TOLERANCE__B 6 +-#define QAM_SL_MEDIAN_TOLERANCE__W 7 +-#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +-#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80 +- +-#define QAM_SL_MEDIAN_FAST__B 13 +-#define QAM_SL_MEDIAN_FAST__W 1 +-#define QAM_SL_MEDIAN_FAST__M 0x2000 +-#define QAM_SL_MEDIAN_FAST__PRE 0x2000 +-#define QAM_SL_MEDIAN_FAST_AVER 0x0 +-#define QAM_SL_MEDIAN_FAST_LAST 0x2000 +- +- +-#define QAM_SL_ALPHA__A 0x1430013 +-#define QAM_SL_ALPHA__W 3 +-#define QAM_SL_ALPHA__M 0x7 +-#define QAM_SL_ALPHA__PRE 0x0 +- +-#define QAM_SL_PHASELIMIT__A 0x1430014 +-#define QAM_SL_PHASELIMIT__W 9 +-#define QAM_SL_PHASELIMIT__M 0x1FF +-#define QAM_SL_PHASELIMIT__PRE 0x0 +-#define QAM_SL_MTA_LENGTH__A 0x1430015 +-#define QAM_SL_MTA_LENGTH__W 2 +-#define QAM_SL_MTA_LENGTH__M 0x3 +-#define QAM_SL_MTA_LENGTH__PRE 0x1 +- +-#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +-#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +-#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +-#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 +- +-#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +-#define QAM_SL_MEDIAN_ERROR__W 10 +-#define QAM_SL_MEDIAN_ERROR__M 0x3FF +-#define QAM_SL_MEDIAN_ERROR__PRE 0x0 +- +-#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +-#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +-#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +-#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 +- +- +-#define QAM_SL_ERR_POWER__A 0x1430017 +-#define QAM_SL_ERR_POWER__W 16 +-#define QAM_SL_ERR_POWER__M 0xFFFF +-#define QAM_SL_ERR_POWER__PRE 0x0 +-#define QAM_SL_QUAL_QAM_4_0__A 0x1430018 +-#define QAM_SL_QUAL_QAM_4_0__W 3 +-#define QAM_SL_QUAL_QAM_4_0__M 0x7 +-#define QAM_SL_QUAL_QAM_4_0__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_4_0_Q0__B 0 +-#define QAM_SL_QUAL_QAM_4_0_Q0__W 3 +-#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_8_0__A 0x1430019 +-#define QAM_SL_QUAL_QAM_8_0__W 6 +-#define QAM_SL_QUAL_QAM_8_0__M 0x3F +-#define QAM_SL_QUAL_QAM_8_0__PRE 0xD +- +-#define QAM_SL_QUAL_QAM_8_0_Q0__B 0 +-#define QAM_SL_QUAL_QAM_8_0_Q0__W 3 +-#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_8_0_Q1__B 3 +-#define QAM_SL_QUAL_QAM_8_0_Q1__W 3 +-#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8 +- +-#define QAM_SL_QUAL_QAM_16_0__A 0x143001A +-#define QAM_SL_QUAL_QAM_16_0__W 3 +-#define QAM_SL_QUAL_QAM_16_0__M 0x7 +-#define QAM_SL_QUAL_QAM_16_0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_16_0_Q0__B 0 +-#define QAM_SL_QUAL_QAM_16_0_Q0__W 3 +-#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_16_1__A 0x143001B +-#define QAM_SL_QUAL_QAM_16_1__W 6 +-#define QAM_SL_QUAL_QAM_16_1__M 0x3F +-#define QAM_SL_QUAL_QAM_16_1__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_16_1_Q0__B 0 +-#define QAM_SL_QUAL_QAM_16_1_Q0__W 3 +-#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_16_1_Q1__B 3 +-#define QAM_SL_QUAL_QAM_16_1_Q1__W 3 +-#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_32_0__A 0x143001C +-#define QAM_SL_QUAL_QAM_32_0__W 3 +-#define QAM_SL_QUAL_QAM_32_0__M 0x7 +-#define QAM_SL_QUAL_QAM_32_0__PRE 0x4 +- +-#define QAM_SL_QUAL_QAM_32_0_Q0__B 0 +-#define QAM_SL_QUAL_QAM_32_0_Q0__W 3 +-#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4 +- +-#define QAM_SL_QUAL_QAM_32_1__A 0x143001D +-#define QAM_SL_QUAL_QAM_32_1__W 6 +-#define QAM_SL_QUAL_QAM_32_1__M 0x3F +-#define QAM_SL_QUAL_QAM_32_1__PRE 0x3 +- +-#define QAM_SL_QUAL_QAM_32_1_Q0__B 0 +-#define QAM_SL_QUAL_QAM_32_1_Q0__W 3 +-#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3 +- +-#define QAM_SL_QUAL_QAM_32_1_Q1__B 3 +-#define QAM_SL_QUAL_QAM_32_1_Q1__W 3 +-#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_32_2__A 0x143001E +-#define QAM_SL_QUAL_QAM_32_2__W 9 +-#define QAM_SL_QUAL_QAM_32_2__M 0x1FF +-#define QAM_SL_QUAL_QAM_32_2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_32_2_Q0__B 0 +-#define QAM_SL_QUAL_QAM_32_2_Q0__W 3 +-#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_32_2_Q1__B 3 +-#define QAM_SL_QUAL_QAM_32_2_Q1__W 3 +-#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_32_2_Q2__B 6 +-#define QAM_SL_QUAL_QAM_32_2_Q2__W 3 +-#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_64_0__A 0x143001F +-#define QAM_SL_QUAL_QAM_64_0__W 3 +-#define QAM_SL_QUAL_QAM_64_0__M 0x7 +-#define QAM_SL_QUAL_QAM_64_0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_64_0_Q0__B 0 +-#define QAM_SL_QUAL_QAM_64_0_Q0__W 3 +-#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_64_1__A 0x1430020 +-#define QAM_SL_QUAL_QAM_64_1__W 6 +-#define QAM_SL_QUAL_QAM_64_1__M 0x3F +-#define QAM_SL_QUAL_QAM_64_1__PRE 0x2 +- +-#define QAM_SL_QUAL_QAM_64_1_Q0__B 0 +-#define QAM_SL_QUAL_QAM_64_1_Q0__W 3 +-#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2 +- +-#define QAM_SL_QUAL_QAM_64_1_Q1__B 3 +-#define QAM_SL_QUAL_QAM_64_1_Q1__W 3 +-#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_64_2__A 0x1430021 +-#define QAM_SL_QUAL_QAM_64_2__W 9 +-#define QAM_SL_QUAL_QAM_64_2__M 0x1FF +-#define QAM_SL_QUAL_QAM_64_2__PRE 0x9 +- +-#define QAM_SL_QUAL_QAM_64_2_Q0__B 0 +-#define QAM_SL_QUAL_QAM_64_2_Q0__W 3 +-#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_64_2_Q1__B 3 +-#define QAM_SL_QUAL_QAM_64_2_Q1__W 3 +-#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8 +- +-#define QAM_SL_QUAL_QAM_64_2_Q2__B 6 +-#define QAM_SL_QUAL_QAM_64_2_Q2__W 3 +-#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_64_3__A 0x1430022 +-#define QAM_SL_QUAL_QAM_64_3__W 12 +-#define QAM_SL_QUAL_QAM_64_3__M 0xFFF +-#define QAM_SL_QUAL_QAM_64_3__PRE 0xD +- +-#define QAM_SL_QUAL_QAM_64_3_Q0__B 0 +-#define QAM_SL_QUAL_QAM_64_3_Q0__W 3 +-#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_64_3_Q1__B 3 +-#define QAM_SL_QUAL_QAM_64_3_Q1__W 3 +-#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8 +- +-#define QAM_SL_QUAL_QAM_64_3_Q2__B 6 +-#define QAM_SL_QUAL_QAM_64_3_Q2__W 3 +-#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_64_3_Q3__B 9 +-#define QAM_SL_QUAL_QAM_64_3_Q3__W 3 +-#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_0__A 0x1430023 +-#define QAM_SL_QUAL_QAM_128_0__W 3 +-#define QAM_SL_QUAL_QAM_128_0__M 0x7 +-#define QAM_SL_QUAL_QAM_128_0__PRE 0x4 +- +-#define QAM_SL_QUAL_QAM_128_0_Q0__B 0 +-#define QAM_SL_QUAL_QAM_128_0_Q0__W 3 +-#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4 +- +-#define QAM_SL_QUAL_QAM_128_1__A 0x1430024 +-#define QAM_SL_QUAL_QAM_128_1__W 6 +-#define QAM_SL_QUAL_QAM_128_1__M 0x3F +-#define QAM_SL_QUAL_QAM_128_1__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_128_1_Q0__B 0 +-#define QAM_SL_QUAL_QAM_128_1_Q0__W 3 +-#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_128_1_Q1__B 3 +-#define QAM_SL_QUAL_QAM_128_1_Q1__W 3 +-#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_2__A 0x1430025 +-#define QAM_SL_QUAL_QAM_128_2__W 9 +-#define QAM_SL_QUAL_QAM_128_2__M 0x1FF +-#define QAM_SL_QUAL_QAM_128_2__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_128_2_Q0__B 0 +-#define QAM_SL_QUAL_QAM_128_2_Q0__W 3 +-#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_128_2_Q1__B 3 +-#define QAM_SL_QUAL_QAM_128_2_Q1__W 3 +-#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_2_Q2__B 6 +-#define QAM_SL_QUAL_QAM_128_2_Q2__W 3 +-#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_3__A 0x1430026 +-#define QAM_SL_QUAL_QAM_128_3__W 12 +-#define QAM_SL_QUAL_QAM_128_3__M 0xFFF +-#define QAM_SL_QUAL_QAM_128_3__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_128_3_Q0__B 0 +-#define QAM_SL_QUAL_QAM_128_3_Q0__W 3 +-#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_128_3_Q1__B 3 +-#define QAM_SL_QUAL_QAM_128_3_Q1__W 3 +-#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_3_Q2__B 6 +-#define QAM_SL_QUAL_QAM_128_3_Q2__W 3 +-#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_3_Q3__B 9 +-#define QAM_SL_QUAL_QAM_128_3_Q3__W 3 +-#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_4__A 0x1430027 +-#define QAM_SL_QUAL_QAM_128_4__W 15 +-#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF +-#define QAM_SL_QUAL_QAM_128_4__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_4_Q0__B 0 +-#define QAM_SL_QUAL_QAM_128_4_Q0__W 3 +-#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_4_Q1__B 3 +-#define QAM_SL_QUAL_QAM_128_4_Q1__W 3 +-#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_4_Q2__B 6 +-#define QAM_SL_QUAL_QAM_128_4_Q2__W 3 +-#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_4_Q3__B 9 +-#define QAM_SL_QUAL_QAM_128_4_Q3__W 3 +-#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_4_Q4__B 12 +-#define QAM_SL_QUAL_QAM_128_4_Q4__W 3 +-#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000 +-#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_5__A 0x1430028 +-#define QAM_SL_QUAL_QAM_128_5__W 15 +-#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF +-#define QAM_SL_QUAL_QAM_128_5__PRE 0x90 +- +-#define QAM_SL_QUAL_QAM_128_5_Q0__B 0 +-#define QAM_SL_QUAL_QAM_128_5_Q0__W 3 +-#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_5_Q1__B 3 +-#define QAM_SL_QUAL_QAM_128_5_Q1__W 3 +-#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10 +- +-#define QAM_SL_QUAL_QAM_128_5_Q2__B 6 +-#define QAM_SL_QUAL_QAM_128_5_Q2__W 3 +-#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80 +- +-#define QAM_SL_QUAL_QAM_128_5_Q3__B 9 +-#define QAM_SL_QUAL_QAM_128_5_Q3__W 3 +-#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_5_Q4__B 12 +-#define QAM_SL_QUAL_QAM_128_5_Q4__W 3 +-#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000 +-#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029 +-#define QAM_SL_QUAL_QAM_128_5H__W 3 +-#define QAM_SL_QUAL_QAM_128_5H__M 0x7 +-#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0 +-#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3 +-#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7 +-#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_0__A 0x143002A +-#define QAM_SL_QUAL_QAM_256_0__W 3 +-#define QAM_SL_QUAL_QAM_256_0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_0__PRE 0x3 +- +-#define QAM_SL_QUAL_QAM_256_0_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_0_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3 +- +-#define QAM_SL_QUAL_QAM_256_1__A 0x143002B +-#define QAM_SL_QUAL_QAM_256_1__W 6 +-#define QAM_SL_QUAL_QAM_256_1__M 0x3F +-#define QAM_SL_QUAL_QAM_256_1__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_256_1_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_1_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_256_1_Q1__B 3 +-#define QAM_SL_QUAL_QAM_256_1_Q1__W 3 +-#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_2__A 0x143002C +-#define QAM_SL_QUAL_QAM_256_2__W 9 +-#define QAM_SL_QUAL_QAM_256_2__M 0x1FF +-#define QAM_SL_QUAL_QAM_256_2__PRE 0x9 +- +-#define QAM_SL_QUAL_QAM_256_2_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_2_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_256_2_Q1__B 3 +-#define QAM_SL_QUAL_QAM_256_2_Q1__W 3 +-#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8 +- +-#define QAM_SL_QUAL_QAM_256_2_Q2__B 6 +-#define QAM_SL_QUAL_QAM_256_2_Q2__W 3 +-#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_3__A 0x143002D +-#define QAM_SL_QUAL_QAM_256_3__W 12 +-#define QAM_SL_QUAL_QAM_256_3__M 0xFFF +-#define QAM_SL_QUAL_QAM_256_3__PRE 0x13 +- +-#define QAM_SL_QUAL_QAM_256_3_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_3_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3 +- +-#define QAM_SL_QUAL_QAM_256_3_Q1__B 3 +-#define QAM_SL_QUAL_QAM_256_3_Q1__W 3 +-#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10 +- +-#define QAM_SL_QUAL_QAM_256_3_Q2__B 6 +-#define QAM_SL_QUAL_QAM_256_3_Q2__W 3 +-#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_3_Q3__B 9 +-#define QAM_SL_QUAL_QAM_256_3_Q3__W 3 +-#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_4__A 0x143002E +-#define QAM_SL_QUAL_QAM_256_4__W 15 +-#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF +-#define QAM_SL_QUAL_QAM_256_4__PRE 0x49 +- +-#define QAM_SL_QUAL_QAM_256_4_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_4_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_256_4_Q1__B 3 +-#define QAM_SL_QUAL_QAM_256_4_Q1__W 3 +-#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8 +- +-#define QAM_SL_QUAL_QAM_256_4_Q2__B 6 +-#define QAM_SL_QUAL_QAM_256_4_Q2__W 3 +-#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40 +- +-#define QAM_SL_QUAL_QAM_256_4_Q3__B 9 +-#define QAM_SL_QUAL_QAM_256_4_Q3__W 3 +-#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_4_Q4__B 12 +-#define QAM_SL_QUAL_QAM_256_4_Q4__W 3 +-#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000 +-#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_5__A 0x143002F +-#define QAM_SL_QUAL_QAM_256_5__W 15 +-#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF +-#define QAM_SL_QUAL_QAM_256_5__PRE 0x59 +- +-#define QAM_SL_QUAL_QAM_256_5_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_5_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1 +- +-#define QAM_SL_QUAL_QAM_256_5_Q1__B 3 +-#define QAM_SL_QUAL_QAM_256_5_Q1__W 3 +-#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18 +- +-#define QAM_SL_QUAL_QAM_256_5_Q2__B 6 +-#define QAM_SL_QUAL_QAM_256_5_Q2__W 3 +-#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40 +- +-#define QAM_SL_QUAL_QAM_256_5_Q3__B 9 +-#define QAM_SL_QUAL_QAM_256_5_Q3__W 3 +-#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_5_Q4__B 12 +-#define QAM_SL_QUAL_QAM_256_5_Q4__W 3 +-#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000 +-#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030 +-#define QAM_SL_QUAL_QAM_256_5H__W 3 +-#define QAM_SL_QUAL_QAM_256_5H__M 0x7 +-#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0 +-#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3 +-#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7 +-#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_6__A 0x1430031 +-#define QAM_SL_QUAL_QAM_256_6__W 15 +-#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF +-#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A +- +-#define QAM_SL_QUAL_QAM_256_6_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_6_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2 +- +-#define QAM_SL_QUAL_QAM_256_6_Q1__B 3 +-#define QAM_SL_QUAL_QAM_256_6_Q1__W 3 +-#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18 +- +-#define QAM_SL_QUAL_QAM_256_6_Q2__B 6 +-#define QAM_SL_QUAL_QAM_256_6_Q2__W 3 +-#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_6_Q3__B 9 +-#define QAM_SL_QUAL_QAM_256_6_Q3__W 3 +-#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200 +- +-#define QAM_SL_QUAL_QAM_256_6_Q4__B 12 +-#define QAM_SL_QUAL_QAM_256_6_Q4__W 3 +-#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000 +-#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032 +-#define QAM_SL_QUAL_QAM_256_6H__W 6 +-#define QAM_SL_QUAL_QAM_256_6H__M 0x3F +-#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0 +-#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3 +-#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7 +-#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3 +-#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3 +-#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38 +-#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_7__A 0x1430033 +-#define QAM_SL_QUAL_QAM_256_7__W 15 +-#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF +-#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D +- +-#define QAM_SL_QUAL_QAM_256_7_Q0__B 0 +-#define QAM_SL_QUAL_QAM_256_7_Q0__W 3 +-#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7 +-#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5 +- +-#define QAM_SL_QUAL_QAM_256_7_Q1__B 3 +-#define QAM_SL_QUAL_QAM_256_7_Q1__W 3 +-#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38 +-#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18 +- +-#define QAM_SL_QUAL_QAM_256_7_Q2__B 6 +-#define QAM_SL_QUAL_QAM_256_7_Q2__W 3 +-#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0 +-#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80 +- +-#define QAM_SL_QUAL_QAM_256_7_Q3__B 9 +-#define QAM_SL_QUAL_QAM_256_7_Q3__W 3 +-#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00 +-#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200 +- +-#define QAM_SL_QUAL_QAM_256_7_Q4__B 12 +-#define QAM_SL_QUAL_QAM_256_7_Q4__W 3 +-#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000 +-#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034 +-#define QAM_SL_QUAL_QAM_256_7H__W 9 +-#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF +-#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0 +-#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3 +-#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7 +-#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3 +-#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3 +-#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38 +-#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0 +- +-#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6 +-#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3 +-#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0 +-#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0 +- +- +- +-#define QAM_DQ_COMM_EXEC__A 0x1440000 +-#define QAM_DQ_COMM_EXEC__W 2 +-#define QAM_DQ_COMM_EXEC__M 0x3 +-#define QAM_DQ_COMM_EXEC__PRE 0x0 +-#define QAM_DQ_COMM_EXEC_STOP 0x0 +-#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +-#define QAM_DQ_COMM_EXEC_HOLD 0x2 +- +-#define QAM_DQ_MODE__A 0x1440010 +-#define QAM_DQ_MODE__W 5 +-#define QAM_DQ_MODE__M 0x1F +-#define QAM_DQ_MODE__PRE 0x0 +- +-#define QAM_DQ_MODE_TAPRESET__B 0 +-#define QAM_DQ_MODE_TAPRESET__W 1 +-#define QAM_DQ_MODE_TAPRESET__M 0x1 +-#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +-#define QAM_DQ_MODE_TAPRESET_RST 0x1 +- +-#define QAM_DQ_MODE_TAPLMS__B 1 +-#define QAM_DQ_MODE_TAPLMS__W 1 +-#define QAM_DQ_MODE_TAPLMS__M 0x2 +-#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +-#define QAM_DQ_MODE_TAPLMS_UPD 0x2 +- +-#define QAM_DQ_MODE_TAPDRAIN__B 2 +-#define QAM_DQ_MODE_TAPDRAIN__W 1 +-#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +-#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +-#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 +- +-#define QAM_DQ_MODE_FB__B 3 +-#define QAM_DQ_MODE_FB__W 2 +-#define QAM_DQ_MODE_FB__M 0x18 +-#define QAM_DQ_MODE_FB__PRE 0x0 +-#define QAM_DQ_MODE_FB_CMA 0x0 +-#define QAM_DQ_MODE_FB_RADIUS 0x8 +-#define QAM_DQ_MODE_FB_DFB 0x10 +-#define QAM_DQ_MODE_FB_TRELLIS 0x18 +- +- +-#define QAM_DQ_MU_FACTOR__A 0x1440011 +-#define QAM_DQ_MU_FACTOR__W 3 +-#define QAM_DQ_MU_FACTOR__M 0x7 +-#define QAM_DQ_MU_FACTOR__PRE 0x0 +- +-#define QAM_DQ_LA_FACTOR__A 0x1440012 +-#define QAM_DQ_LA_FACTOR__W 4 +-#define QAM_DQ_LA_FACTOR__M 0xF +-#define QAM_DQ_LA_FACTOR__PRE 0xC +- +-#define QAM_DQ_CMA_RATIO__A 0x1440013 +-#define QAM_DQ_CMA_RATIO__W 14 +-#define QAM_DQ_CMA_RATIO__M 0x3FFF +-#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +-#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +-#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +-#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +-#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +-#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 +- +-#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +-#define QAM_DQ_QUAL_RADSEL__W 3 +-#define QAM_DQ_QUAL_RADSEL__M 0x7 +-#define QAM_DQ_QUAL_RADSEL__PRE 0x0 +- +-#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +-#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +-#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +-#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +-#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +-#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 +- +-#define QAM_DQ_QUAL_ENA__A 0x1440015 +-#define QAM_DQ_QUAL_ENA__W 1 +-#define QAM_DQ_QUAL_ENA__M 0x1 +-#define QAM_DQ_QUAL_ENA__PRE 0x0 +- +-#define QAM_DQ_QUAL_ENA_ENA__B 0 +-#define QAM_DQ_QUAL_ENA_ENA__W 1 +-#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +-#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +-#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 +- +-#define QAM_DQ_QUAL_FUN0__A 0x1440018 +-#define QAM_DQ_QUAL_FUN0__W 6 +-#define QAM_DQ_QUAL_FUN0__M 0x3F +-#define QAM_DQ_QUAL_FUN0__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN0_BIT__B 0 +-#define QAM_DQ_QUAL_FUN0_BIT__W 6 +-#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +-#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN1__A 0x1440019 +-#define QAM_DQ_QUAL_FUN1__W 6 +-#define QAM_DQ_QUAL_FUN1__M 0x3F +-#define QAM_DQ_QUAL_FUN1__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN1_BIT__B 0 +-#define QAM_DQ_QUAL_FUN1_BIT__W 6 +-#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +-#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN2__A 0x144001A +-#define QAM_DQ_QUAL_FUN2__W 6 +-#define QAM_DQ_QUAL_FUN2__M 0x3F +-#define QAM_DQ_QUAL_FUN2__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN2_BIT__B 0 +-#define QAM_DQ_QUAL_FUN2_BIT__W 6 +-#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +-#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN3__A 0x144001B +-#define QAM_DQ_QUAL_FUN3__W 6 +-#define QAM_DQ_QUAL_FUN3__M 0x3F +-#define QAM_DQ_QUAL_FUN3__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN3_BIT__B 0 +-#define QAM_DQ_QUAL_FUN3_BIT__W 6 +-#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +-#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 +- +-#define QAM_DQ_QUAL_FUN4__A 0x144001C +-#define QAM_DQ_QUAL_FUN4__W 6 +-#define QAM_DQ_QUAL_FUN4__M 0x3F +-#define QAM_DQ_QUAL_FUN4__PRE 0x6 +- +-#define QAM_DQ_QUAL_FUN4_BIT__B 0 +-#define QAM_DQ_QUAL_FUN4_BIT__W 6 +-#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +-#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 +- +-#define QAM_DQ_QUAL_FUN5__A 0x144001D +-#define QAM_DQ_QUAL_FUN5__W 6 +-#define QAM_DQ_QUAL_FUN5__M 0x3F +-#define QAM_DQ_QUAL_FUN5__PRE 0x6 +- +-#define QAM_DQ_QUAL_FUN5_BIT__B 0 +-#define QAM_DQ_QUAL_FUN5_BIT__W 6 +-#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +-#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 +- +-#define QAM_DQ_RAW_LIM__A 0x144001E +-#define QAM_DQ_RAW_LIM__W 5 +-#define QAM_DQ_RAW_LIM__M 0x1F +-#define QAM_DQ_RAW_LIM__PRE 0x1F +- +-#define QAM_DQ_RAW_LIM_BIT__B 0 +-#define QAM_DQ_RAW_LIM_BIT__W 5 +-#define QAM_DQ_RAW_LIM_BIT__M 0x1F +-#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F +- +-#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +-#define QAM_DQ_TAP_RE_EL0__W 12 +-#define QAM_DQ_TAP_RE_EL0__M 0xFFF +-#define QAM_DQ_TAP_RE_EL0__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +-#define QAM_DQ_TAP_IM_EL0__W 12 +-#define QAM_DQ_TAP_IM_EL0__M 0xFFF +-#define QAM_DQ_TAP_IM_EL0__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +-#define QAM_DQ_TAP_RE_EL1__W 12 +-#define QAM_DQ_TAP_RE_EL1__M 0xFFF +-#define QAM_DQ_TAP_RE_EL1__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +-#define QAM_DQ_TAP_IM_EL1__W 12 +-#define QAM_DQ_TAP_IM_EL1__M 0xFFF +-#define QAM_DQ_TAP_IM_EL1__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +-#define QAM_DQ_TAP_RE_EL2__W 12 +-#define QAM_DQ_TAP_RE_EL2__M 0xFFF +-#define QAM_DQ_TAP_RE_EL2__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +-#define QAM_DQ_TAP_IM_EL2__W 12 +-#define QAM_DQ_TAP_IM_EL2__M 0xFFF +-#define QAM_DQ_TAP_IM_EL2__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +-#define QAM_DQ_TAP_RE_EL3__W 12 +-#define QAM_DQ_TAP_RE_EL3__M 0xFFF +-#define QAM_DQ_TAP_RE_EL3__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +-#define QAM_DQ_TAP_IM_EL3__W 12 +-#define QAM_DQ_TAP_IM_EL3__M 0xFFF +-#define QAM_DQ_TAP_IM_EL3__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +-#define QAM_DQ_TAP_RE_EL4__W 12 +-#define QAM_DQ_TAP_RE_EL4__M 0xFFF +-#define QAM_DQ_TAP_RE_EL4__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +-#define QAM_DQ_TAP_IM_EL4__W 12 +-#define QAM_DQ_TAP_IM_EL4__M 0xFFF +-#define QAM_DQ_TAP_IM_EL4__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL5__A 0x144002A +-#define QAM_DQ_TAP_RE_EL5__W 12 +-#define QAM_DQ_TAP_RE_EL5__M 0xFFF +-#define QAM_DQ_TAP_RE_EL5__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL5__A 0x144002B +-#define QAM_DQ_TAP_IM_EL5__W 12 +-#define QAM_DQ_TAP_IM_EL5__M 0xFFF +-#define QAM_DQ_TAP_IM_EL5__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL6__A 0x144002C +-#define QAM_DQ_TAP_RE_EL6__W 12 +-#define QAM_DQ_TAP_RE_EL6__M 0xFFF +-#define QAM_DQ_TAP_RE_EL6__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL6__A 0x144002D +-#define QAM_DQ_TAP_IM_EL6__W 12 +-#define QAM_DQ_TAP_IM_EL6__M 0xFFF +-#define QAM_DQ_TAP_IM_EL6__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL7__A 0x144002E +-#define QAM_DQ_TAP_RE_EL7__W 12 +-#define QAM_DQ_TAP_RE_EL7__M 0xFFF +-#define QAM_DQ_TAP_RE_EL7__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL7__A 0x144002F +-#define QAM_DQ_TAP_IM_EL7__W 12 +-#define QAM_DQ_TAP_IM_EL7__M 0xFFF +-#define QAM_DQ_TAP_IM_EL7__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +-#define QAM_DQ_TAP_RE_EL8__W 12 +-#define QAM_DQ_TAP_RE_EL8__M 0xFFF +-#define QAM_DQ_TAP_RE_EL8__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +-#define QAM_DQ_TAP_IM_EL8__W 12 +-#define QAM_DQ_TAP_IM_EL8__M 0xFFF +-#define QAM_DQ_TAP_IM_EL8__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +-#define QAM_DQ_TAP_RE_EL9__W 12 +-#define QAM_DQ_TAP_RE_EL9__M 0xFFF +-#define QAM_DQ_TAP_RE_EL9__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +-#define QAM_DQ_TAP_IM_EL9__W 12 +-#define QAM_DQ_TAP_IM_EL9__M 0xFFF +-#define QAM_DQ_TAP_IM_EL9__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +-#define QAM_DQ_TAP_RE_EL10__W 12 +-#define QAM_DQ_TAP_RE_EL10__M 0xFFF +-#define QAM_DQ_TAP_RE_EL10__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +-#define QAM_DQ_TAP_IM_EL10__W 12 +-#define QAM_DQ_TAP_IM_EL10__M 0xFFF +-#define QAM_DQ_TAP_IM_EL10__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +-#define QAM_DQ_TAP_RE_EL11__W 12 +-#define QAM_DQ_TAP_RE_EL11__M 0xFFF +-#define QAM_DQ_TAP_RE_EL11__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +-#define QAM_DQ_TAP_IM_EL11__W 12 +-#define QAM_DQ_TAP_IM_EL11__M 0xFFF +-#define QAM_DQ_TAP_IM_EL11__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +-#define QAM_DQ_TAP_RE_EL12__W 12 +-#define QAM_DQ_TAP_RE_EL12__M 0xFFF +-#define QAM_DQ_TAP_RE_EL12__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +-#define QAM_DQ_TAP_IM_EL12__W 12 +-#define QAM_DQ_TAP_IM_EL12__M 0xFFF +-#define QAM_DQ_TAP_IM_EL12__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL13__A 0x144003A +-#define QAM_DQ_TAP_RE_EL13__W 12 +-#define QAM_DQ_TAP_RE_EL13__M 0xFFF +-#define QAM_DQ_TAP_RE_EL13__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL13__A 0x144003B +-#define QAM_DQ_TAP_IM_EL13__W 12 +-#define QAM_DQ_TAP_IM_EL13__M 0xFFF +-#define QAM_DQ_TAP_IM_EL13__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL14__A 0x144003C +-#define QAM_DQ_TAP_RE_EL14__W 12 +-#define QAM_DQ_TAP_RE_EL14__M 0xFFF +-#define QAM_DQ_TAP_RE_EL14__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL14__A 0x144003D +-#define QAM_DQ_TAP_IM_EL14__W 12 +-#define QAM_DQ_TAP_IM_EL14__M 0xFFF +-#define QAM_DQ_TAP_IM_EL14__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL15__A 0x144003E +-#define QAM_DQ_TAP_RE_EL15__W 12 +-#define QAM_DQ_TAP_RE_EL15__M 0xFFF +-#define QAM_DQ_TAP_RE_EL15__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL15__A 0x144003F +-#define QAM_DQ_TAP_IM_EL15__W 12 +-#define QAM_DQ_TAP_IM_EL15__M 0xFFF +-#define QAM_DQ_TAP_IM_EL15__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +-#define QAM_DQ_TAP_RE_EL16__W 12 +-#define QAM_DQ_TAP_RE_EL16__M 0xFFF +-#define QAM_DQ_TAP_RE_EL16__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +-#define QAM_DQ_TAP_IM_EL16__W 12 +-#define QAM_DQ_TAP_IM_EL16__M 0xFFF +-#define QAM_DQ_TAP_IM_EL16__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +-#define QAM_DQ_TAP_RE_EL17__W 12 +-#define QAM_DQ_TAP_RE_EL17__M 0xFFF +-#define QAM_DQ_TAP_RE_EL17__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +-#define QAM_DQ_TAP_IM_EL17__W 12 +-#define QAM_DQ_TAP_IM_EL17__M 0xFFF +-#define QAM_DQ_TAP_IM_EL17__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +-#define QAM_DQ_TAP_RE_EL18__W 12 +-#define QAM_DQ_TAP_RE_EL18__M 0xFFF +-#define QAM_DQ_TAP_RE_EL18__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +-#define QAM_DQ_TAP_IM_EL18__W 12 +-#define QAM_DQ_TAP_IM_EL18__M 0xFFF +-#define QAM_DQ_TAP_IM_EL18__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +-#define QAM_DQ_TAP_RE_EL19__W 12 +-#define QAM_DQ_TAP_RE_EL19__M 0xFFF +-#define QAM_DQ_TAP_RE_EL19__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +-#define QAM_DQ_TAP_IM_EL19__W 12 +-#define QAM_DQ_TAP_IM_EL19__M 0xFFF +-#define QAM_DQ_TAP_IM_EL19__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +-#define QAM_DQ_TAP_RE_EL20__W 12 +-#define QAM_DQ_TAP_RE_EL20__M 0xFFF +-#define QAM_DQ_TAP_RE_EL20__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +-#define QAM_DQ_TAP_IM_EL20__W 12 +-#define QAM_DQ_TAP_IM_EL20__M 0xFFF +-#define QAM_DQ_TAP_IM_EL20__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL21__A 0x144004A +-#define QAM_DQ_TAP_RE_EL21__W 12 +-#define QAM_DQ_TAP_RE_EL21__M 0xFFF +-#define QAM_DQ_TAP_RE_EL21__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL21__A 0x144004B +-#define QAM_DQ_TAP_IM_EL21__W 12 +-#define QAM_DQ_TAP_IM_EL21__M 0xFFF +-#define QAM_DQ_TAP_IM_EL21__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL22__A 0x144004C +-#define QAM_DQ_TAP_RE_EL22__W 12 +-#define QAM_DQ_TAP_RE_EL22__M 0xFFF +-#define QAM_DQ_TAP_RE_EL22__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL22__A 0x144004D +-#define QAM_DQ_TAP_IM_EL22__W 12 +-#define QAM_DQ_TAP_IM_EL22__M 0xFFF +-#define QAM_DQ_TAP_IM_EL22__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL23__A 0x144004E +-#define QAM_DQ_TAP_RE_EL23__W 12 +-#define QAM_DQ_TAP_RE_EL23__M 0xFFF +-#define QAM_DQ_TAP_RE_EL23__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL23__A 0x144004F +-#define QAM_DQ_TAP_IM_EL23__W 12 +-#define QAM_DQ_TAP_IM_EL23__M 0xFFF +-#define QAM_DQ_TAP_IM_EL23__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +-#define QAM_DQ_TAP_RE_EL24__W 12 +-#define QAM_DQ_TAP_RE_EL24__M 0xFFF +-#define QAM_DQ_TAP_RE_EL24__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +-#define QAM_DQ_TAP_IM_EL24__W 12 +-#define QAM_DQ_TAP_IM_EL24__M 0xFFF +-#define QAM_DQ_TAP_IM_EL24__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +-#define QAM_DQ_TAP_RE_EL25__W 12 +-#define QAM_DQ_TAP_RE_EL25__M 0xFFF +-#define QAM_DQ_TAP_RE_EL25__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +-#define QAM_DQ_TAP_IM_EL25__W 12 +-#define QAM_DQ_TAP_IM_EL25__M 0xFFF +-#define QAM_DQ_TAP_IM_EL25__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +-#define QAM_DQ_TAP_RE_EL26__W 12 +-#define QAM_DQ_TAP_RE_EL26__M 0xFFF +-#define QAM_DQ_TAP_RE_EL26__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +-#define QAM_DQ_TAP_IM_EL26__W 12 +-#define QAM_DQ_TAP_IM_EL26__M 0xFFF +-#define QAM_DQ_TAP_IM_EL26__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +-#define QAM_DQ_TAP_RE_EL27__W 12 +-#define QAM_DQ_TAP_RE_EL27__M 0xFFF +-#define QAM_DQ_TAP_RE_EL27__PRE 0x2 +- +-#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +-#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +-#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +-#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +-#define QAM_DQ_TAP_IM_EL27__W 12 +-#define QAM_DQ_TAP_IM_EL27__M 0xFFF +-#define QAM_DQ_TAP_IM_EL27__PRE 0x2 +- +-#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +-#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +-#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +-#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 +- +- +- +-#define QAM_LC_COMM_EXEC__A 0x1450000 +-#define QAM_LC_COMM_EXEC__W 2 +-#define QAM_LC_COMM_EXEC__M 0x3 +-#define QAM_LC_COMM_EXEC__PRE 0x0 +-#define QAM_LC_COMM_EXEC_STOP 0x0 +-#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +-#define QAM_LC_COMM_EXEC_HOLD 0x2 +- +-#define QAM_LC_COMM_MB__A 0x1450002 +-#define QAM_LC_COMM_MB__W 2 +-#define QAM_LC_COMM_MB__M 0x3 +-#define QAM_LC_COMM_MB__PRE 0x0 +-#define QAM_LC_COMM_MB_CTL__B 0 +-#define QAM_LC_COMM_MB_CTL__W 1 +-#define QAM_LC_COMM_MB_CTL__M 0x1 +-#define QAM_LC_COMM_MB_CTL__PRE 0x0 +-#define QAM_LC_COMM_MB_CTL_OFF 0x0 +-#define QAM_LC_COMM_MB_CTL_ON 0x1 +-#define QAM_LC_COMM_MB_OBS__B 1 +-#define QAM_LC_COMM_MB_OBS__W 1 +-#define QAM_LC_COMM_MB_OBS__M 0x2 +-#define QAM_LC_COMM_MB_OBS__PRE 0x0 +-#define QAM_LC_COMM_MB_OBS_OFF 0x0 +-#define QAM_LC_COMM_MB_OBS_ON 0x2 +- +-#define QAM_LC_COMM_INT_REQ__A 0x1450003 +-#define QAM_LC_COMM_INT_REQ__W 1 +-#define QAM_LC_COMM_INT_REQ__M 0x1 +-#define QAM_LC_COMM_INT_REQ__PRE 0x0 +-#define QAM_LC_COMM_INT_STA__A 0x1450005 +-#define QAM_LC_COMM_INT_STA__W 3 +-#define QAM_LC_COMM_INT_STA__M 0x7 +-#define QAM_LC_COMM_INT_STA__PRE 0x0 +- +-#define QAM_LC_COMM_INT_STA_READY__B 0 +-#define QAM_LC_COMM_INT_STA_READY__W 1 +-#define QAM_LC_COMM_INT_STA_READY__M 0x1 +-#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 +- +-#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +-#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +-#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +-#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 +- +-#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +-#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +-#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +-#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 +- +-#define QAM_LC_COMM_INT_MSK__A 0x1450006 +-#define QAM_LC_COMM_INT_MSK__W 3 +-#define QAM_LC_COMM_INT_MSK__M 0x7 +-#define QAM_LC_COMM_INT_MSK__PRE 0x0 +-#define QAM_LC_COMM_INT_MSK_READY__B 0 +-#define QAM_LC_COMM_INT_MSK_READY__W 1 +-#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +-#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +-#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +-#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +-#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +-#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +-#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +-#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +-#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +-#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 +- +-#define QAM_LC_COMM_INT_STM__A 0x1450007 +-#define QAM_LC_COMM_INT_STM__W 3 +-#define QAM_LC_COMM_INT_STM__M 0x7 +-#define QAM_LC_COMM_INT_STM__PRE 0x0 +-#define QAM_LC_COMM_INT_STM_READY__B 0 +-#define QAM_LC_COMM_INT_STM_READY__W 1 +-#define QAM_LC_COMM_INT_STM_READY__M 0x1 +-#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +-#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +-#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +-#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +-#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +-#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +-#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +-#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +-#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 +- +-#define QAM_LC_MODE__A 0x1450010 +-#define QAM_LC_MODE__W 4 +-#define QAM_LC_MODE__M 0xF +-#define QAM_LC_MODE__PRE 0xE +- +-#define QAM_LC_MODE_ENABLE_A__B 0 +-#define QAM_LC_MODE_ENABLE_A__W 1 +-#define QAM_LC_MODE_ENABLE_A__M 0x1 +-#define QAM_LC_MODE_ENABLE_A__PRE 0x0 +- +-#define QAM_LC_MODE_ENABLE_F__B 1 +-#define QAM_LC_MODE_ENABLE_F__W 1 +-#define QAM_LC_MODE_ENABLE_F__M 0x2 +-#define QAM_LC_MODE_ENABLE_F__PRE 0x2 +- +-#define QAM_LC_MODE_ENABLE_R__B 2 +-#define QAM_LC_MODE_ENABLE_R__W 1 +-#define QAM_LC_MODE_ENABLE_R__M 0x4 +-#define QAM_LC_MODE_ENABLE_R__PRE 0x4 +- +-#define QAM_LC_MODE_ENABLE_PQUAL__B 3 +-#define QAM_LC_MODE_ENABLE_PQUAL__W 1 +-#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8 +-#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8 +- +-#define QAM_LC_CA__A 0x1450011 +-#define QAM_LC_CA__W 6 +-#define QAM_LC_CA__M 0x3F +-#define QAM_LC_CA__PRE 0x28 +- +-#define QAM_LC_CA_COEF__B 0 +-#define QAM_LC_CA_COEF__W 6 +-#define QAM_LC_CA_COEF__M 0x3F +-#define QAM_LC_CA_COEF__PRE 0x28 +- +-#define QAM_LC_CF__A 0x1450012 +-#define QAM_LC_CF__W 8 +-#define QAM_LC_CF__M 0xFF +-#define QAM_LC_CF__PRE 0x30 +- +-#define QAM_LC_CF_COEF__B 0 +-#define QAM_LC_CF_COEF__W 8 +-#define QAM_LC_CF_COEF__M 0xFF +-#define QAM_LC_CF_COEF__PRE 0x30 +- +-#define QAM_LC_CF1__A 0x1450013 +-#define QAM_LC_CF1__W 8 +-#define QAM_LC_CF1__M 0xFF +-#define QAM_LC_CF1__PRE 0x14 +- +-#define QAM_LC_CF1_COEF__B 0 +-#define QAM_LC_CF1_COEF__W 8 +-#define QAM_LC_CF1_COEF__M 0xFF +-#define QAM_LC_CF1_COEF__PRE 0x14 +- +-#define QAM_LC_CP__A 0x1450014 +-#define QAM_LC_CP__W 8 +-#define QAM_LC_CP__M 0xFF +-#define QAM_LC_CP__PRE 0x64 +- +-#define QAM_LC_CP_COEF__B 0 +-#define QAM_LC_CP_COEF__W 8 +-#define QAM_LC_CP_COEF__M 0xFF +-#define QAM_LC_CP_COEF__PRE 0x64 +- +-#define QAM_LC_CI__A 0x1450015 +-#define QAM_LC_CI__W 8 +-#define QAM_LC_CI__M 0xFF +-#define QAM_LC_CI__PRE 0x32 +- +-#define QAM_LC_CI_COEF__B 0 +-#define QAM_LC_CI_COEF__W 8 +-#define QAM_LC_CI_COEF__M 0xFF +-#define QAM_LC_CI_COEF__PRE 0x32 +- +-#define QAM_LC_EP__A 0x1450016 +-#define QAM_LC_EP__W 6 +-#define QAM_LC_EP__M 0x3F +-#define QAM_LC_EP__PRE 0x0 +- +-#define QAM_LC_EP_COEF__B 0 +-#define QAM_LC_EP_COEF__W 6 +-#define QAM_LC_EP_COEF__M 0x3F +-#define QAM_LC_EP_COEF__PRE 0x0 +- +-#define QAM_LC_EI__A 0x1450017 +-#define QAM_LC_EI__W 6 +-#define QAM_LC_EI__M 0x3F +-#define QAM_LC_EI__PRE 0x0 +- +-#define QAM_LC_EI_COEF__B 0 +-#define QAM_LC_EI_COEF__W 6 +-#define QAM_LC_EI_COEF__M 0x3F +-#define QAM_LC_EI_COEF__PRE 0x0 +- +-#define QAM_LC_QUAL_TAB0__A 0x1450018 +-#define QAM_LC_QUAL_TAB0__W 5 +-#define QAM_LC_QUAL_TAB0__M 0x1F +-#define QAM_LC_QUAL_TAB0__PRE 0x0 +- +-#define QAM_LC_QUAL_TAB0_VALUE__B 0 +-#define QAM_LC_QUAL_TAB0_VALUE__W 5 +-#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 +- +-#define QAM_LC_QUAL_TAB1__A 0x1450019 +-#define QAM_LC_QUAL_TAB1__W 5 +-#define QAM_LC_QUAL_TAB1__M 0x1F +-#define QAM_LC_QUAL_TAB1__PRE 0x1 +- +-#define QAM_LC_QUAL_TAB1_VALUE__B 0 +-#define QAM_LC_QUAL_TAB1_VALUE__W 5 +-#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 +- +-#define QAM_LC_QUAL_TAB2__A 0x145001A +-#define QAM_LC_QUAL_TAB2__W 5 +-#define QAM_LC_QUAL_TAB2__M 0x1F +-#define QAM_LC_QUAL_TAB2__PRE 0x2 +- +-#define QAM_LC_QUAL_TAB2_VALUE__B 0 +-#define QAM_LC_QUAL_TAB2_VALUE__W 5 +-#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 +- +-#define QAM_LC_QUAL_TAB3__A 0x145001B +-#define QAM_LC_QUAL_TAB3__W 5 +-#define QAM_LC_QUAL_TAB3__M 0x1F +-#define QAM_LC_QUAL_TAB3__PRE 0x3 +- +-#define QAM_LC_QUAL_TAB3_VALUE__B 0 +-#define QAM_LC_QUAL_TAB3_VALUE__W 5 +-#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 +- +-#define QAM_LC_QUAL_TAB4__A 0x145001C +-#define QAM_LC_QUAL_TAB4__W 5 +-#define QAM_LC_QUAL_TAB4__M 0x1F +-#define QAM_LC_QUAL_TAB4__PRE 0x4 +- +-#define QAM_LC_QUAL_TAB4_VALUE__B 0 +-#define QAM_LC_QUAL_TAB4_VALUE__W 5 +-#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 +- +-#define QAM_LC_QUAL_TAB5__A 0x145001D +-#define QAM_LC_QUAL_TAB5__W 5 +-#define QAM_LC_QUAL_TAB5__M 0x1F +-#define QAM_LC_QUAL_TAB5__PRE 0x5 +- +-#define QAM_LC_QUAL_TAB5_VALUE__B 0 +-#define QAM_LC_QUAL_TAB5_VALUE__W 5 +-#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 +- +-#define QAM_LC_QUAL_TAB6__A 0x145001E +-#define QAM_LC_QUAL_TAB6__W 5 +-#define QAM_LC_QUAL_TAB6__M 0x1F +-#define QAM_LC_QUAL_TAB6__PRE 0x6 +- +-#define QAM_LC_QUAL_TAB6_VALUE__B 0 +-#define QAM_LC_QUAL_TAB6_VALUE__W 5 +-#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 +- +-#define QAM_LC_QUAL_TAB8__A 0x145001F +-#define QAM_LC_QUAL_TAB8__W 5 +-#define QAM_LC_QUAL_TAB8__M 0x1F +-#define QAM_LC_QUAL_TAB8__PRE 0x8 +- +-#define QAM_LC_QUAL_TAB8_VALUE__B 0 +-#define QAM_LC_QUAL_TAB8_VALUE__W 5 +-#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 +- +-#define QAM_LC_QUAL_TAB9__A 0x1450020 +-#define QAM_LC_QUAL_TAB9__W 5 +-#define QAM_LC_QUAL_TAB9__M 0x1F +-#define QAM_LC_QUAL_TAB9__PRE 0x9 +- +-#define QAM_LC_QUAL_TAB9_VALUE__B 0 +-#define QAM_LC_QUAL_TAB9_VALUE__W 5 +-#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 +- +-#define QAM_LC_QUAL_TAB10__A 0x1450021 +-#define QAM_LC_QUAL_TAB10__W 5 +-#define QAM_LC_QUAL_TAB10__M 0x1F +-#define QAM_LC_QUAL_TAB10__PRE 0xA +- +-#define QAM_LC_QUAL_TAB10_VALUE__B 0 +-#define QAM_LC_QUAL_TAB10_VALUE__W 5 +-#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA +- +-#define QAM_LC_QUAL_TAB12__A 0x1450022 +-#define QAM_LC_QUAL_TAB12__W 5 +-#define QAM_LC_QUAL_TAB12__M 0x1F +-#define QAM_LC_QUAL_TAB12__PRE 0xC +- +-#define QAM_LC_QUAL_TAB12_VALUE__B 0 +-#define QAM_LC_QUAL_TAB12_VALUE__W 5 +-#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC +- +-#define QAM_LC_QUAL_TAB15__A 0x1450023 +-#define QAM_LC_QUAL_TAB15__W 5 +-#define QAM_LC_QUAL_TAB15__M 0x1F +-#define QAM_LC_QUAL_TAB15__PRE 0xF +- +-#define QAM_LC_QUAL_TAB15_VALUE__B 0 +-#define QAM_LC_QUAL_TAB15_VALUE__W 5 +-#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF +- +-#define QAM_LC_QUAL_TAB16__A 0x1450024 +-#define QAM_LC_QUAL_TAB16__W 5 +-#define QAM_LC_QUAL_TAB16__M 0x1F +-#define QAM_LC_QUAL_TAB16__PRE 0x10 +- +-#define QAM_LC_QUAL_TAB16_VALUE__B 0 +-#define QAM_LC_QUAL_TAB16_VALUE__W 5 +-#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 +- +-#define QAM_LC_QUAL_TAB20__A 0x1450025 +-#define QAM_LC_QUAL_TAB20__W 5 +-#define QAM_LC_QUAL_TAB20__M 0x1F +-#define QAM_LC_QUAL_TAB20__PRE 0x14 +- +-#define QAM_LC_QUAL_TAB20_VALUE__B 0 +-#define QAM_LC_QUAL_TAB20_VALUE__W 5 +-#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 +- +-#define QAM_LC_QUAL_TAB25__A 0x1450026 +-#define QAM_LC_QUAL_TAB25__W 5 +-#define QAM_LC_QUAL_TAB25__M 0x1F +-#define QAM_LC_QUAL_TAB25__PRE 0x19 +- +-#define QAM_LC_QUAL_TAB25_VALUE__B 0 +-#define QAM_LC_QUAL_TAB25_VALUE__W 5 +-#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +-#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 +- +-#define QAM_LC_EQ_TIMING__A 0x1450027 +-#define QAM_LC_EQ_TIMING__W 10 +-#define QAM_LC_EQ_TIMING__M 0x3FF +-#define QAM_LC_EQ_TIMING__PRE 0x0 +- +-#define QAM_LC_EQ_TIMING_OFFS__B 0 +-#define QAM_LC_EQ_TIMING_OFFS__W 10 +-#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +-#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 +- +-#define QAM_LC_LPF_FACTORP__A 0x1450028 +-#define QAM_LC_LPF_FACTORP__W 3 +-#define QAM_LC_LPF_FACTORP__M 0x7 +-#define QAM_LC_LPF_FACTORP__PRE 0x3 +- +-#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +-#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +-#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +-#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 +- +-#define QAM_LC_LPF_FACTORI__A 0x1450029 +-#define QAM_LC_LPF_FACTORI__W 3 +-#define QAM_LC_LPF_FACTORI__M 0x7 +-#define QAM_LC_LPF_FACTORI__PRE 0x3 +- +-#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +-#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +-#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +-#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 +- +-#define QAM_LC_RATE_LIMIT__A 0x145002A +-#define QAM_LC_RATE_LIMIT__W 2 +-#define QAM_LC_RATE_LIMIT__M 0x3 +-#define QAM_LC_RATE_LIMIT__PRE 0x3 +- +-#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +-#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +-#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +-#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 +- +-#define QAM_LC_SYMBOL_FREQ__A 0x145002B +-#define QAM_LC_SYMBOL_FREQ__W 10 +-#define QAM_LC_SYMBOL_FREQ__M 0x3FF +-#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF +- +-#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +-#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +-#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +-#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF +- +-#define QAM_LC_MTA_LENGTH__A 0x145002C +-#define QAM_LC_MTA_LENGTH__W 2 +-#define QAM_LC_MTA_LENGTH__M 0x3 +-#define QAM_LC_MTA_LENGTH__PRE 0x2 +- +-#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +-#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +-#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +-#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 +- +-#define QAM_LC_AMP_ACCU__A 0x145002D +-#define QAM_LC_AMP_ACCU__W 14 +-#define QAM_LC_AMP_ACCU__M 0x3FFF +-#define QAM_LC_AMP_ACCU__PRE 0x600 +- +-#define QAM_LC_AMP_ACCU_ACCU__B 0 +-#define QAM_LC_AMP_ACCU_ACCU__W 14 +-#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +-#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 +- +-#define QAM_LC_FREQ_ACCU__A 0x145002E +-#define QAM_LC_FREQ_ACCU__W 10 +-#define QAM_LC_FREQ_ACCU__M 0x3FF +-#define QAM_LC_FREQ_ACCU__PRE 0x0 +- +-#define QAM_LC_FREQ_ACCU_ACCU__B 0 +-#define QAM_LC_FREQ_ACCU_ACCU__W 10 +-#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +-#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 +- +-#define QAM_LC_RATE_ACCU__A 0x145002F +-#define QAM_LC_RATE_ACCU__W 10 +-#define QAM_LC_RATE_ACCU__M 0x3FF +-#define QAM_LC_RATE_ACCU__PRE 0x0 +- +-#define QAM_LC_RATE_ACCU_ACCU__B 0 +-#define QAM_LC_RATE_ACCU_ACCU__W 10 +-#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +-#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 +- +-#define QAM_LC_AMPLITUDE__A 0x1450030 +-#define QAM_LC_AMPLITUDE__W 10 +-#define QAM_LC_AMPLITUDE__M 0x3FF +-#define QAM_LC_AMPLITUDE__PRE 0x0 +- +-#define QAM_LC_AMPLITUDE_SIZE__B 0 +-#define QAM_LC_AMPLITUDE_SIZE__W 10 +-#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +-#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 +- +-#define QAM_LC_RAD_ERROR__A 0x1450031 +-#define QAM_LC_RAD_ERROR__W 10 +-#define QAM_LC_RAD_ERROR__M 0x3FF +-#define QAM_LC_RAD_ERROR__PRE 0x0 +- +-#define QAM_LC_RAD_ERROR_SIZE__B 0 +-#define QAM_LC_RAD_ERROR_SIZE__W 10 +-#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +-#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 +- +-#define QAM_LC_FREQ_OFFS__A 0x1450032 +-#define QAM_LC_FREQ_OFFS__W 10 +-#define QAM_LC_FREQ_OFFS__M 0x3FF +-#define QAM_LC_FREQ_OFFS__PRE 0x0 +- +-#define QAM_LC_FREQ_OFFS_OFFS__B 0 +-#define QAM_LC_FREQ_OFFS_OFFS__W 10 +-#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +-#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 +- +-#define QAM_LC_PHASE_ERROR__A 0x1450033 +-#define QAM_LC_PHASE_ERROR__W 10 +-#define QAM_LC_PHASE_ERROR__M 0x3FF +-#define QAM_LC_PHASE_ERROR__PRE 0x0 +- +-#define QAM_LC_PHASE_ERROR_SIZE__B 0 +-#define QAM_LC_PHASE_ERROR_SIZE__W 10 +-#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +-#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 +- +- +- +-#define QAM_SY_COMM_EXEC__A 0x1470000 +-#define QAM_SY_COMM_EXEC__W 2 +-#define QAM_SY_COMM_EXEC__M 0x3 +-#define QAM_SY_COMM_EXEC__PRE 0x0 +-#define QAM_SY_COMM_EXEC_STOP 0x0 +-#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +-#define QAM_SY_COMM_EXEC_HOLD 0x2 +- +-#define QAM_SY_COMM_MB__A 0x1470002 +-#define QAM_SY_COMM_MB__W 4 +-#define QAM_SY_COMM_MB__M 0xF +-#define QAM_SY_COMM_MB__PRE 0x0 +-#define QAM_SY_COMM_MB_CTL__B 0 +-#define QAM_SY_COMM_MB_CTL__W 1 +-#define QAM_SY_COMM_MB_CTL__M 0x1 +-#define QAM_SY_COMM_MB_CTL__PRE 0x0 +-#define QAM_SY_COMM_MB_CTL_OFF 0x0 +-#define QAM_SY_COMM_MB_CTL_ON 0x1 +-#define QAM_SY_COMM_MB_OBS__B 1 +-#define QAM_SY_COMM_MB_OBS__W 1 +-#define QAM_SY_COMM_MB_OBS__M 0x2 +-#define QAM_SY_COMM_MB_OBS__PRE 0x0 +-#define QAM_SY_COMM_MB_OBS_OFF 0x0 +-#define QAM_SY_COMM_MB_OBS_ON 0x2 +-#define QAM_SY_COMM_MB_MUX_CTL__B 2 +-#define QAM_SY_COMM_MB_MUX_CTL__W 1 +-#define QAM_SY_COMM_MB_MUX_CTL__M 0x4 +-#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0 +-#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0 +-#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4 +-#define QAM_SY_COMM_MB_MUX_OBS__B 3 +-#define QAM_SY_COMM_MB_MUX_OBS__W 1 +-#define QAM_SY_COMM_MB_MUX_OBS__M 0x8 +-#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0 +-#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0 +-#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8 +- +-#define QAM_SY_COMM_INT_REQ__A 0x1470003 +-#define QAM_SY_COMM_INT_REQ__W 1 +-#define QAM_SY_COMM_INT_REQ__M 0x1 +-#define QAM_SY_COMM_INT_REQ__PRE 0x0 +-#define QAM_SY_COMM_INT_STA__A 0x1470005 +-#define QAM_SY_COMM_INT_STA__W 4 +-#define QAM_SY_COMM_INT_STA__M 0xF +-#define QAM_SY_COMM_INT_STA__PRE 0x0 +- +-#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +-#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +-#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +-#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 +- +-#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +-#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +-#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +-#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 +- +-#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +-#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +-#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +-#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 +- +-#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +-#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +-#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +-#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 +- +-#define QAM_SY_COMM_INT_MSK__A 0x1470006 +-#define QAM_SY_COMM_INT_MSK__W 4 +-#define QAM_SY_COMM_INT_MSK__M 0xF +-#define QAM_SY_COMM_INT_MSK__PRE 0x0 +-#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +-#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +-#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +-#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +-#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +-#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +-#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +-#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +-#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +-#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +-#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +-#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +-#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +-#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +-#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +-#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 +- +-#define QAM_SY_COMM_INT_STM__A 0x1470007 +-#define QAM_SY_COMM_INT_STM__W 4 +-#define QAM_SY_COMM_INT_STM__M 0xF +-#define QAM_SY_COMM_INT_STM__PRE 0x0 +-#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +-#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +-#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +-#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +-#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +-#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +-#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +-#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +-#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +-#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +-#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +-#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +-#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +-#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +-#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +-#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 +- +-#define QAM_SY_STATUS__A 0x1470010 +-#define QAM_SY_STATUS__W 2 +-#define QAM_SY_STATUS__M 0x3 +-#define QAM_SY_STATUS__PRE 0x0 +- +-#define QAM_SY_STATUS_SYNC_STATE__B 0 +-#define QAM_SY_STATUS_SYNC_STATE__W 2 +-#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +-#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 +- +- +-#define QAM_SY_TIMEOUT__A 0x1470011 +-#define QAM_SY_TIMEOUT__W 16 +-#define QAM_SY_TIMEOUT__M 0xFFFF +-#define QAM_SY_TIMEOUT__PRE 0x3A98 +- +-#define QAM_SY_SYNC_LWM__A 0x1470012 +-#define QAM_SY_SYNC_LWM__W 4 +-#define QAM_SY_SYNC_LWM__M 0xF +-#define QAM_SY_SYNC_LWM__PRE 0x2 +- +-#define QAM_SY_SYNC_AWM__A 0x1470013 +-#define QAM_SY_SYNC_AWM__W 4 +-#define QAM_SY_SYNC_AWM__M 0xF +-#define QAM_SY_SYNC_AWM__PRE 0x3 +- +-#define QAM_SY_SYNC_HWM__A 0x1470014 +-#define QAM_SY_SYNC_HWM__W 4 +-#define QAM_SY_SYNC_HWM__M 0xF +-#define QAM_SY_SYNC_HWM__PRE 0x5 +- +-#define QAM_SY_UNLOCK__A 0x1470015 +-#define QAM_SY_UNLOCK__W 1 +-#define QAM_SY_UNLOCK__M 0x1 +-#define QAM_SY_UNLOCK__PRE 0x0 +-#define QAM_SY_CONTROL_WORD__A 0x1470016 +-#define QAM_SY_CONTROL_WORD__W 4 +-#define QAM_SY_CONTROL_WORD__M 0xF +-#define QAM_SY_CONTROL_WORD__PRE 0x0 +- +-#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +-#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +-#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +-#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 +- +- +-#define QAM_SY_SP_INV__A 0x1470017 +-#define QAM_SY_SP_INV__W 1 +-#define QAM_SY_SP_INV__M 0x1 +-#define QAM_SY_SP_INV__PRE 0x0 +-#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 +-#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1 +- +- +- +-#define QAM_VD_ISS_RAM__A 0x1480000 +- +- +- +-#define QAM_VD_QSS_RAM__A 0x1490000 +- +- +- +-#define QAM_VD_SYM_RAM__A 0x14A0000 +- +- +- +- +- +-#define SCU_COMM_EXEC__A 0x800000 +-#define SCU_COMM_EXEC__W 2 +-#define SCU_COMM_EXEC__M 0x3 +-#define SCU_COMM_EXEC__PRE 0x0 +-#define SCU_COMM_EXEC_STOP 0x0 +-#define SCU_COMM_EXEC_ACTIVE 0x1 +-#define SCU_COMM_EXEC_HOLD 0x2 +- +-#define SCU_COMM_STATE__A 0x800001 +-#define SCU_COMM_STATE__W 16 +-#define SCU_COMM_STATE__M 0xFFFF +-#define SCU_COMM_STATE__PRE 0x0 +- +-#define SCU_COMM_STATE_COMM_STATE__B 0 +-#define SCU_COMM_STATE_COMM_STATE__W 16 +-#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +-#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 +- +- +- +-#define SCU_TOP_COMM_EXEC__A 0x810000 +-#define SCU_TOP_COMM_EXEC__W 2 +-#define SCU_TOP_COMM_EXEC__M 0x3 +-#define SCU_TOP_COMM_EXEC__PRE 0x0 +-#define SCU_TOP_COMM_EXEC_STOP 0x0 +-#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +-#define SCU_TOP_COMM_EXEC_HOLD 0x2 +- +- +-#define SCU_TOP_COMM_STATE__A 0x810001 +-#define SCU_TOP_COMM_STATE__W 16 +-#define SCU_TOP_COMM_STATE__M 0xFFFF +-#define SCU_TOP_COMM_STATE__PRE 0x0 +-#define SCU_TOP_MWAIT_CTR__A 0x810010 +-#define SCU_TOP_MWAIT_CTR__W 2 +-#define SCU_TOP_MWAIT_CTR__M 0x3 +-#define SCU_TOP_MWAIT_CTR__PRE 0x0 +- +-#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +-#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +-#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +-#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +-#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +-#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 +- +-#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +-#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +-#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +-#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +-#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +-#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 +- +- +- +-#define SCU_LOW_RAM__A 0x820000 +- +-#define SCU_LOW_RAM_LOW__B 0 +-#define SCU_LOW_RAM_LOW__W 16 +-#define SCU_LOW_RAM_LOW__M 0xFFFF +-#define SCU_LOW_RAM_LOW__PRE 0x0 +- +- +- +-#define SCU_HIGH_RAM__A 0x830000 +- +-#define SCU_HIGH_RAM_HIGH__B 0 +-#define SCU_HIGH_RAM_HIGH__W 16 +-#define SCU_HIGH_RAM_HIGH__M 0xFFFF +-#define SCU_HIGH_RAM_HIGH__PRE 0x0 +- +- +- +- +- +- +-#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF +-#define SCU_RAM_DRIVER_DEBUG__W 16 +-#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF +-#define SCU_RAM_DRIVER_DEBUG__PRE 0x0 +- +-#define SCU_RAM_SP__A 0x831EC0 +-#define SCU_RAM_SP__W 16 +-#define SCU_RAM_SP__M 0xFFFF +-#define SCU_RAM_SP__PRE 0x0 +- +-#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1 +-#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16 +-#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF +-#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0 +- +-#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2 +-#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16 +-#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF +-#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0 +- +-#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3 +-#define SCU_RAM_QAM_NO_ACQ_CNT__W 16 +-#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF +-#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 +-#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16 +-#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF +-#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0 +- +-#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5 +-#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +-#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +-#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000 +- +-#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6 +-#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +-#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +-#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 +-#define SCU_RAM_GPIO__A 0x831EC7 +-#define SCU_RAM_GPIO__W 2 +-#define SCU_RAM_GPIO__M 0x3 +-#define SCU_RAM_GPIO__PRE 0x0 +- +-#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +-#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +-#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +-#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +-#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +-#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 +- +-#define SCU_RAM_GPIO_VSYNC_IND__B 1 +-#define SCU_RAM_GPIO_VSYNC_IND__W 1 +-#define SCU_RAM_GPIO_VSYNC_IND__M 0x2 +-#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0 +-#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0 +-#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2 +- +-#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +-#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +-#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +-#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 +- +-#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 +- +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 +- +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +-#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 +- +- +-#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +-#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +-#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +-#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000 +- +-#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +-#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +-#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +-#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 +- +-#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +-#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +-#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +-#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 +- +-#define SCU_RAM_INHIBIT_1__A 0x831ECC +-#define SCU_RAM_INHIBIT_1__W 16 +-#define SCU_RAM_INHIBIT_1__M 0xFFFF +-#define SCU_RAM_INHIBIT_1__PRE 0x0 +- +-#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +-#define SCU_RAM_HTOL_BUF_0__W 16 +-#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +-#define SCU_RAM_HTOL_BUF_0__PRE 0x0 +- +-#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +-#define SCU_RAM_HTOL_BUF_1__W 16 +-#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +-#define SCU_RAM_HTOL_BUF_1__PRE 0x0 +- +-#define SCU_RAM_INHIBIT_2__A 0x831ECF +-#define SCU_RAM_INHIBIT_2__W 16 +-#define SCU_RAM_INHIBIT_2__M 0xFFFF +-#define SCU_RAM_INHIBIT_2__PRE 0x0 +- +-#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +-#define SCU_RAM_TR_SHORT_BUF_0__W 16 +-#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +-#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 +- +-#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +-#define SCU_RAM_TR_SHORT_BUF_1__W 16 +-#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +-#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +-#define SCU_RAM_TR_LONG_BUF_0__W 16 +-#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +-#define SCU_RAM_TR_LONG_BUF_1__W 16 +-#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +-#define SCU_RAM_TR_LONG_BUF_2__W 16 +-#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +-#define SCU_RAM_TR_LONG_BUF_3__W 16 +-#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +-#define SCU_RAM_TR_LONG_BUF_4__W 16 +-#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +-#define SCU_RAM_TR_LONG_BUF_5__W 16 +-#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +-#define SCU_RAM_TR_LONG_BUF_6__W 16 +-#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +-#define SCU_RAM_TR_LONG_BUF_7__W 16 +-#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +-#define SCU_RAM_TR_LONG_BUF_8__W 16 +-#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +-#define SCU_RAM_TR_LONG_BUF_9__W 16 +-#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +-#define SCU_RAM_TR_LONG_BUF_10__W 16 +-#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +-#define SCU_RAM_TR_LONG_BUF_11__W 16 +-#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +-#define SCU_RAM_TR_LONG_BUF_12__W 16 +-#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +-#define SCU_RAM_TR_LONG_BUF_13__W 16 +-#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +-#define SCU_RAM_TR_LONG_BUF_14__W 16 +-#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +-#define SCU_RAM_TR_LONG_BUF_15__W 16 +-#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +-#define SCU_RAM_TR_LONG_BUF_16__W 16 +-#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +-#define SCU_RAM_TR_LONG_BUF_17__W 16 +-#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +-#define SCU_RAM_TR_LONG_BUF_18__W 16 +-#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +-#define SCU_RAM_TR_LONG_BUF_19__W 16 +-#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +-#define SCU_RAM_TR_LONG_BUF_20__W 16 +-#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +-#define SCU_RAM_TR_LONG_BUF_21__W 16 +-#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +-#define SCU_RAM_TR_LONG_BUF_22__W 16 +-#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +-#define SCU_RAM_TR_LONG_BUF_23__W 16 +-#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +-#define SCU_RAM_TR_LONG_BUF_24__W 16 +-#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +-#define SCU_RAM_TR_LONG_BUF_25__W 16 +-#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +-#define SCU_RAM_TR_LONG_BUF_26__W 16 +-#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +-#define SCU_RAM_TR_LONG_BUF_27__W 16 +-#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +-#define SCU_RAM_TR_LONG_BUF_28__W 16 +-#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +-#define SCU_RAM_TR_LONG_BUF_29__W 16 +-#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +-#define SCU_RAM_TR_LONG_BUF_30__W 16 +-#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 +- +-#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +-#define SCU_RAM_TR_LONG_BUF_31__W 16 +-#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +-#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +-#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +-#define SCU_RAM_ATV_AMS_MAX__W 11 +-#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +-#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 +- +-#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +-#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +-#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +-#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 +- +-#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +-#define SCU_RAM_ATV_AMS_MIN__W 11 +-#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +-#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF +- +-#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +-#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +-#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +-#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF +- +-#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +-#define SCU_RAM_ATV_FIELD_CNT__W 9 +-#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +-#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +-#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +-#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +-#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +-#define SCU_RAM_ATV_AAGC_FAST__W 1 +-#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +-#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 +- +-#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +-#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +-#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +-#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +-#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +-#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 +- +-#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +-#define SCU_RAM_ATV_AAGC_LP2__W 16 +-#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +-#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 +- +-#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +-#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +-#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +-#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +-#define SCU_RAM_ATV_BP_LVL__W 11 +-#define SCU_RAM_ATV_BP_LVL__M 0x7FF +-#define SCU_RAM_ATV_BP_LVL__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +-#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +-#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +-#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +-#define SCU_RAM_ATV_BP_RELY__W 8 +-#define SCU_RAM_ATV_BP_RELY__M 0xFF +-#define SCU_RAM_ATV_BP_RELY__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +-#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +-#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +-#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +-#define SCU_RAM_ATV_BP_MTA__W 14 +-#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +-#define SCU_RAM_ATV_BP_MTA__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +-#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +-#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +-#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_REF__A 0x831EFA +-#define SCU_RAM_ATV_BP_REF__W 11 +-#define SCU_RAM_ATV_BP_REF__M 0x7FF +-#define SCU_RAM_ATV_BP_REF__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +-#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +-#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +-#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +-#define SCU_RAM_ATV_BP_REF_MIN__W 11 +-#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +-#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64 +- +-#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +-#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +-#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +-#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64 +- +-#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +-#define SCU_RAM_ATV_BP_REF_MAX__W 11 +-#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +-#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104 +- +-#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +-#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +-#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +-#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104 +- +-#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +-#define SCU_RAM_ATV_BP_CNT__W 8 +-#define SCU_RAM_ATV_BP_CNT__M 0xFF +-#define SCU_RAM_ATV_BP_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +-#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +-#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +-#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +-#define SCU_RAM_ATV_BP_XD_CNT__W 12 +-#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +-#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +-#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +-#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +-#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +-#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +-#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +-#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445 +- +-#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +-#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +-#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +-#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445 +- +-#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +-#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +-#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +-#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223 +- +-#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +-#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +-#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +-#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223 +- +- +-#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01 +-#define SCU_RAM_OFDM_AGC_POW_TGT__W 15 +-#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF +-#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848 +- +-#define SCU_RAM_OFDM_RSV_01__A 0x831F02 +-#define SCU_RAM_OFDM_RSV_01__W 16 +-#define SCU_RAM_OFDM_RSV_01__M 0xFFFF +-#define SCU_RAM_OFDM_RSV_01__PRE 0x0 +- +-#define SCU_RAM_OFDM_RSV_02__A 0x831F03 +-#define SCU_RAM_OFDM_RSV_02__W 16 +-#define SCU_RAM_OFDM_RSV_02__M 0xFFFF +-#define SCU_RAM_OFDM_RSV_02__PRE 0x0 +-#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04 +-#define SCU_RAM_FEC_PRE_RS_BER__W 16 +-#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF +-#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0 +- +-#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0 +-#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16 +-#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF +-#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0 +- +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16 +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0 +- +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0 +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16 +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF +-#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0 +- +-#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06 +-#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16 +-#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF +-#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0 +-#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16 +-#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF +-#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0 +- +-#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07 +-#define SCU_RAM_ATV_VSYNC_PERIOD__W 16 +-#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF +-#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0 +- +-#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0 +-#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16 +-#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF +-#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0 +- +-#define SCU_RAM_FREE_7944__A 0x831F08 +-#define SCU_RAM_FREE_7944__W 16 +-#define SCU_RAM_FREE_7944__M 0xFFFF +-#define SCU_RAM_FREE_7944__PRE 0x0 +- +-#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7945__A 0x831F09 +-#define SCU_RAM_FREE_7945__W 16 +-#define SCU_RAM_FREE_7945__M 0xFFFF +-#define SCU_RAM_FREE_7945__PRE 0x0 +- +-#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7946__A 0x831F0A +-#define SCU_RAM_FREE_7946__W 16 +-#define SCU_RAM_FREE_7946__M 0xFFFF +-#define SCU_RAM_FREE_7946__PRE 0x0 +- +-#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7947__A 0x831F0B +-#define SCU_RAM_FREE_7947__W 16 +-#define SCU_RAM_FREE_7947__M 0xFFFF +-#define SCU_RAM_FREE_7947__PRE 0x0 +- +-#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7948__A 0x831F0C +-#define SCU_RAM_FREE_7948__W 16 +-#define SCU_RAM_FREE_7948__M 0xFFFF +-#define SCU_RAM_FREE_7948__PRE 0x0 +- +-#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7949__A 0x831F0D +-#define SCU_RAM_FREE_7949__W 16 +-#define SCU_RAM_FREE_7949__M 0xFFFF +-#define SCU_RAM_FREE_7949__PRE 0x0 +- +-#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7950__A 0x831F0E +-#define SCU_RAM_FREE_7950__W 16 +-#define SCU_RAM_FREE_7950__M 0xFFFF +-#define SCU_RAM_FREE_7950__PRE 0x0 +- +-#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7951__A 0x831F0F +-#define SCU_RAM_FREE_7951__W 16 +-#define SCU_RAM_FREE_7951__M 0xFFFF +-#define SCU_RAM_FREE_7951__PRE 0x0 +- +-#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7952__A 0x831F10 +-#define SCU_RAM_FREE_7952__W 16 +-#define SCU_RAM_FREE_7952__M 0xFFFF +-#define SCU_RAM_FREE_7952__PRE 0x0 +- +-#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7953__A 0x831F11 +-#define SCU_RAM_FREE_7953__W 16 +-#define SCU_RAM_FREE_7953__M 0xFFFF +-#define SCU_RAM_FREE_7953__PRE 0x0 +- +-#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7954__A 0x831F12 +-#define SCU_RAM_FREE_7954__W 16 +-#define SCU_RAM_FREE_7954__M 0xFFFF +-#define SCU_RAM_FREE_7954__PRE 0x0 +- +-#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7955__A 0x831F13 +-#define SCU_RAM_FREE_7955__W 16 +-#define SCU_RAM_FREE_7955__M 0xFFFF +-#define SCU_RAM_FREE_7955__PRE 0x0 +- +-#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0 +- +- +-#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14 +-#define SCU_RAM_ADC_COMP_CONTROL__W 3 +-#define SCU_RAM_ADC_COMP_CONTROL__M 0x7 +-#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0 +-#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0 +-#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1 +-#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2 +-#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3 +- +- +-#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 +-#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +-#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +-#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32 +- +-#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16 +-#define SCU_RAM_AGC_KI_CYCCNT__W 16 +-#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +-#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 +- +-#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 +-#define SCU_RAM_AGC_KI_CYCLEN__W 16 +-#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +-#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4 +- +-#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 +-#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +-#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +-#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4 +- +-#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 +-#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +-#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +-#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF +- +-#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A +-#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +-#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +-#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01 +- +-#define SCU_RAM_AGC_RF_MAX__A 0x831F1B +-#define SCU_RAM_AGC_RF_MAX__W 15 +-#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +-#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF +-#define SCU_RAM_FREE_7964__A 0x831F1C +-#define SCU_RAM_FREE_7964__W 16 +-#define SCU_RAM_FREE_7964__M 0xFFFF +-#define SCU_RAM_FREE_7964__PRE 0x0 +- +-#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7965__A 0x831F1D +-#define SCU_RAM_FREE_7965__W 16 +-#define SCU_RAM_FREE_7965__M 0xFFFF +-#define SCU_RAM_FREE_7965__PRE 0x0 +- +-#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7966__A 0x831F1E +-#define SCU_RAM_FREE_7966__W 16 +-#define SCU_RAM_FREE_7966__M 0xFFFF +-#define SCU_RAM_FREE_7966__PRE 0x0 +- +-#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7967__A 0x831F1F +-#define SCU_RAM_FREE_7967__W 16 +-#define SCU_RAM_FREE_7967__M 0xFFFF +-#define SCU_RAM_FREE_7967__PRE 0x0 +- +-#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20 +-#define SCU_RAM_QAM_PARAM_MIRRORING__W 8 +-#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF +-#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0 +-#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1 +-#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1 +-#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0 +-#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0 +-#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1 +- +-#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1 +-#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1 +-#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2 +-#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0 +-#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0 +-#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2 +- +-#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2 +-#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1 +-#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4 +-#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0 +-#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0 +-#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4 +- +-#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21 +-#define SCU_RAM_QAM_PARAM_OPTIONS__W 8 +-#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF +-#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0 +-#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1 +-#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1 +-#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0 +-#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0 +-#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1 +- +-#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1 +-#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1 +-#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2 +-#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0 +-#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0 +-#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2 +- +-#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4 +-#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1 +-#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10 +-#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0 +-#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0 +-#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10 +- +-#define SCU_RAM_FREE_7970__A 0x831F22 +-#define SCU_RAM_FREE_7970__W 16 +-#define SCU_RAM_FREE_7970__M 0xFFFF +-#define SCU_RAM_FREE_7970__PRE 0x0 +- +-#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_FREE_7971__A 0x831F23 +-#define SCU_RAM_FREE_7971__W 16 +-#define SCU_RAM_FREE_7971__M 0xFFFF +-#define SCU_RAM_FREE_7971__PRE 0x0 +- +-#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0 +-#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16 +-#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF +-#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0 +- +-#define SCU_RAM_AGC_CONFIG__A 0x831F24 +-#define SCU_RAM_AGC_CONFIG__W 16 +-#define SCU_RAM_AGC_CONFIG__M 0xFFFF +-#define SCU_RAM_AGC_CONFIG__PRE 0x0 +- +-#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0 +-#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1 +-#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 +-#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0 +- +-#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1 +-#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1 +-#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 +-#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0 +- +-#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2 +-#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1 +-#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4 +-#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0 +- +-#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8 +-#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1 +-#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 +-#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0 +- +-#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9 +-#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1 +-#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 +-#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0 +- +-#define SCU_RAM_AGC_KI__A 0x831F25 +-#define SCU_RAM_AGC_KI__W 15 +-#define SCU_RAM_AGC_KI__M 0x7FFF +-#define SCU_RAM_AGC_KI__PRE 0x22A +- +-#define SCU_RAM_AGC_KI_DGAIN__B 0 +-#define SCU_RAM_AGC_KI_DGAIN__W 4 +-#define SCU_RAM_AGC_KI_DGAIN__M 0xF +-#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA +- +-#define SCU_RAM_AGC_KI_RF__B 4 +-#define SCU_RAM_AGC_KI_RF__W 4 +-#define SCU_RAM_AGC_KI_RF__M 0xF0 +-#define SCU_RAM_AGC_KI_RF__PRE 0x20 +- +-#define SCU_RAM_AGC_KI_IF__B 8 +-#define SCU_RAM_AGC_KI_IF__W 4 +-#define SCU_RAM_AGC_KI_IF__M 0xF00 +-#define SCU_RAM_AGC_KI_IF__PRE 0x200 +- +-#define SCU_RAM_AGC_KI_RED__A 0x831F26 +-#define SCU_RAM_AGC_KI_RED__W 6 +-#define SCU_RAM_AGC_KI_RED__M 0x3F +-#define SCU_RAM_AGC_KI_RED__PRE 0x0 +- +-#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +-#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +-#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +-#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 +- +-#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +-#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +-#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +-#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 +- +-#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +-#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +-#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +-#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 +- +- +-#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 +-#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +-#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +-#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 +- +-#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 +-#define SCU_RAM_AGC_KI_MINGAIN__W 16 +-#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +-#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000 +- +-#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 +-#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +-#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +-#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 +- +-#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A +-#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +-#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +-#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +-#define SCU_RAM_AGC_KI_MIN__A 0x831F2B +-#define SCU_RAM_AGC_KI_MIN__W 12 +-#define SCU_RAM_AGC_KI_MIN__M 0xFFF +-#define SCU_RAM_AGC_KI_MIN__PRE 0x111 +- +-#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +-#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +-#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +-#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1 +- +-#define SCU_RAM_AGC_KI_MIN_RF__B 4 +-#define SCU_RAM_AGC_KI_MIN_RF__W 4 +-#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +-#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10 +- +-#define SCU_RAM_AGC_KI_MIN_IF__B 8 +-#define SCU_RAM_AGC_KI_MIN_IF__W 4 +-#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +-#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100 +- +-#define SCU_RAM_AGC_KI_MAX__A 0x831F2C +-#define SCU_RAM_AGC_KI_MAX__W 12 +-#define SCU_RAM_AGC_KI_MAX__M 0xFFF +-#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF +- +-#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +-#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +-#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +-#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF +- +-#define SCU_RAM_AGC_KI_MAX_RF__B 4 +-#define SCU_RAM_AGC_KI_MAX_RF__W 4 +-#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +-#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0 +- +-#define SCU_RAM_AGC_KI_MAX_IF__B 8 +-#define SCU_RAM_AGC_KI_MAX_IF__W 4 +-#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +-#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00 +- +- +-#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D +-#define SCU_RAM_AGC_CLP_SUM__W 16 +-#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +-#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 +- +-#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E +-#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +-#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +-#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8 +- +-#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F +-#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +-#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +-#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400 +- +-#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 +-#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +-#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +-#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4 +- +-#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 +-#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +-#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +-#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 +- +-#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 +-#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +-#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +-#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC +- +-#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 +-#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +-#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +-#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 +- +-#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 +-#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +-#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +-#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1 +- +-#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 +-#define SCU_RAM_AGC_SNS_SUM__W 16 +-#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +-#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 +- +-#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 +-#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +-#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +-#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8 +- +-#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 +-#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +-#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +-#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400 +- +-#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 +-#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +-#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +-#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 +- +-#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 +-#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +-#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +-#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC +- +-#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A +-#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +-#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +-#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 +- +-#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B +-#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +-#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +-#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1 +- +-#define SCU_RAM_AGC_INGAIN__A 0x831F3C +-#define SCU_RAM_AGC_INGAIN__W 16 +-#define SCU_RAM_AGC_INGAIN__M 0xFFFF +-#define SCU_RAM_AGC_INGAIN__PRE 0x708 +- +-#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D +-#define SCU_RAM_AGC_INGAIN_TGT__W 15 +-#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +-#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708 +- +-#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +-#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +-#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +-#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708 +- +-#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +-#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +-#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +-#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF +- +-#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 +-#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +-#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +-#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 +- +-#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 +-#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +-#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +-#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 +- +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008 +- +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 +- +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +-#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C +- +-#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +-#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +-#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +-#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 +- +-#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 +-#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +-#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +-#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 +- +-#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 +-#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +-#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +-#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 +-#define SCU_RAM_ATV_STANDARD__A 0x831F48 +-#define SCU_RAM_ATV_STANDARD__W 12 +-#define SCU_RAM_ATV_STANDARD__M 0xFFF +-#define SCU_RAM_ATV_STANDARD__PRE 0x2 +- +-#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +-#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +-#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +-#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2 +-#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +-#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +-#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +-#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +-#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +-#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +-#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +-#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 +- +-#define SCU_RAM_ATV_DETECT__A 0x831F49 +-#define SCU_RAM_ATV_DETECT__W 1 +-#define SCU_RAM_ATV_DETECT__M 0x1 +-#define SCU_RAM_ATV_DETECT__PRE 0x0 +- +-#define SCU_RAM_ATV_DETECT_DETECT__B 0 +-#define SCU_RAM_ATV_DETECT_DETECT__W 1 +-#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +-#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +-#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 +-#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 +- +-#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +-#define SCU_RAM_ATV_DETECT_TH__W 8 +-#define SCU_RAM_ATV_DETECT_TH__M 0xFF +-#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F +- +-#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +-#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +-#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +-#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F +- +-#define SCU_RAM_ATV_LOCK__A 0x831F4B +-#define SCU_RAM_ATV_LOCK__W 2 +-#define SCU_RAM_ATV_LOCK__M 0x3 +-#define SCU_RAM_ATV_LOCK__PRE 0x0 +- +-#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +-#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +-#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +-#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +-#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +-#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 +- +-#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +-#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +-#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +-#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +-#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +-#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 +- +-#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +-#define SCU_RAM_ATV_CR_LOCK__W 11 +-#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +-#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 +- +-#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +-#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +-#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +-#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 +- +-#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +-#define SCU_RAM_ATV_AGC_MODE__W 8 +-#define SCU_RAM_ATV_AGC_MODE__M 0xFF +-#define SCU_RAM_ATV_AGC_MODE__PRE 0x50 +- +-#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +-#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +-#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +-#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +-#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +-#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 +- +-#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +-#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +-#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +-#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +-#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +-#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 +- +-#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +-#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +-#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +-#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10 +-#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +-#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +-#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 +- +-#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +-#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +-#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +-#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40 +-#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +-#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 +- +-#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +-#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +-#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +-#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +-#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +-#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 +- +- +-#define SCU_RAM_ATV_RSV_01__A 0x831F4E +-#define SCU_RAM_ATV_RSV_01__W 16 +-#define SCU_RAM_ATV_RSV_01__M 0xFFFF +-#define SCU_RAM_ATV_RSV_01__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_02__A 0x831F4F +-#define SCU_RAM_ATV_RSV_02__W 16 +-#define SCU_RAM_ATV_RSV_02__M 0xFFFF +-#define SCU_RAM_ATV_RSV_02__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_03__A 0x831F50 +-#define SCU_RAM_ATV_RSV_03__W 16 +-#define SCU_RAM_ATV_RSV_03__M 0xFFFF +-#define SCU_RAM_ATV_RSV_03__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_04__A 0x831F51 +-#define SCU_RAM_ATV_RSV_04__W 16 +-#define SCU_RAM_ATV_RSV_04__M 0xFFFF +-#define SCU_RAM_ATV_RSV_04__PRE 0x0 +-#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +-#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +-#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +-#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA +- +-#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +-#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +-#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +-#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA +- +-#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +-#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +-#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +-#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC +- +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +-#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A +- +-#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +-#define SCU_RAM_ATV_ACT_AMX__W 11 +-#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +-#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 +- +-#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +-#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +-#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +-#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 +- +-#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +-#define SCU_RAM_ATV_ACT_AMI__W 11 +-#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +-#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 +- +-#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +-#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +-#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +-#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 +- +-#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56 +-#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16 +-#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF +-#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0 +- +-#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0 +-#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16 +-#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF +-#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0 +- +-#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57 +-#define SCU_RAM_ATV_BPC_REF_CNT__W 16 +-#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF +-#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0 +- +-#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0 +-#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16 +-#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF +-#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0 +- +- +-#define SCU_RAM_ATV_RSV_07__A 0x831F58 +-#define SCU_RAM_ATV_RSV_07__W 16 +-#define SCU_RAM_ATV_RSV_07__M 0xFFFF +-#define SCU_RAM_ATV_RSV_07__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_08__A 0x831F59 +-#define SCU_RAM_ATV_RSV_08__W 16 +-#define SCU_RAM_ATV_RSV_08__M 0xFFFF +-#define SCU_RAM_ATV_RSV_08__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_09__A 0x831F5A +-#define SCU_RAM_ATV_RSV_09__W 16 +-#define SCU_RAM_ATV_RSV_09__M 0xFFFF +-#define SCU_RAM_ATV_RSV_09__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_10__A 0x831F5B +-#define SCU_RAM_ATV_RSV_10__W 16 +-#define SCU_RAM_ATV_RSV_10__M 0xFFFF +-#define SCU_RAM_ATV_RSV_10__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_11__A 0x831F5C +-#define SCU_RAM_ATV_RSV_11__W 16 +-#define SCU_RAM_ATV_RSV_11__M 0xFFFF +-#define SCU_RAM_ATV_RSV_11__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_12__A 0x831F5D +-#define SCU_RAM_ATV_RSV_12__W 16 +-#define SCU_RAM_ATV_RSV_12__M 0xFFFF +-#define SCU_RAM_ATV_RSV_12__PRE 0x0 +-#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +-#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +-#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +-#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000 +- +-#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +-#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +-#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +-#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000 +- +-#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +-#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +-#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +-#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 +- +-#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +-#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +-#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +-#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 +- +- +-#define SCU_RAM_ATV_RSV_13__A 0x831F60 +-#define SCU_RAM_ATV_RSV_13__W 16 +-#define SCU_RAM_ATV_RSV_13__M 0xFFFF +-#define SCU_RAM_ATV_RSV_13__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_14__A 0x831F61 +-#define SCU_RAM_ATV_RSV_14__W 16 +-#define SCU_RAM_ATV_RSV_14__M 0xFFFF +-#define SCU_RAM_ATV_RSV_14__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_15__A 0x831F62 +-#define SCU_RAM_ATV_RSV_15__W 16 +-#define SCU_RAM_ATV_RSV_15__M 0xFFFF +-#define SCU_RAM_ATV_RSV_15__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_16__A 0x831F63 +-#define SCU_RAM_ATV_RSV_16__W 16 +-#define SCU_RAM_ATV_RSV_16__M 0xFFFF +-#define SCU_RAM_ATV_RSV_16__PRE 0x0 +-#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +-#define SCU_RAM_ATV_AAGC_CNT__W 8 +-#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +-#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7 +- +-#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +-#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +-#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +-#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7 +- +-#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +-#define SCU_RAM_ATV_SIF_GAIN__W 11 +-#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +-#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80 +- +-#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +-#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +-#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +-#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80 +- +- +-#define SCU_RAM_ATV_RSV_17__A 0x831F66 +-#define SCU_RAM_ATV_RSV_17__W 16 +-#define SCU_RAM_ATV_RSV_17__M 0xFFFF +-#define SCU_RAM_ATV_RSV_17__PRE 0x0 +- +-#define SCU_RAM_ATV_RSV_18__A 0x831F67 +-#define SCU_RAM_ATV_RSV_18__W 16 +-#define SCU_RAM_ATV_RSV_18__M 0xFFFF +-#define SCU_RAM_ATV_RSV_18__PRE 0x0 +- +-#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +-#define SCU_RAM_ATV_RATE_OFS__W 12 +-#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +-#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 +- +-#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +-#define SCU_RAM_ATV_LO_INCR__W 12 +-#define SCU_RAM_ATV_LO_INCR__M 0xFFF +-#define SCU_RAM_ATV_LO_INCR__PRE 0x0 +- +-#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +-#define SCU_RAM_ATV_IIR_CRIT__W 12 +-#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +-#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 +- +-#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +-#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +-#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +-#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 +- +-#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +-#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +-#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +-#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 +- +-#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +-#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +-#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +-#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 +-#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +-#define SCU_RAM_ATV_MOD_CONTROL__W 12 +-#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +-#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 +- +-#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0 +-#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12 +-#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF +-#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0 +- +-#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +-#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +-#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +-#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667 +- +-#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0 +-#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12 +-#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +-#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667 +- +-#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +-#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +-#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +-#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337 +- +-#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0 +-#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12 +-#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF +-#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337 +- +-#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +-#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +-#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +-#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447 +- +-#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0 +-#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12 +-#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +-#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447 +- +-#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +-#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +-#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +-#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225 +- +-#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +-#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +-#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +-#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225 +- +-#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +-#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +-#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +-#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14 +- +-#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +-#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +-#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +-#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14 +-#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +-#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 +- +-#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +-#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +-#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +-#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1 +- +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1 +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +-#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 +- +-#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5 +- +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +-#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 +- +-#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +-#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1 +- +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +-#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF +- +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +-#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +-#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +-#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13 +- +-#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +-#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +-#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +-#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13 +- +-#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +-#define SCU_RAM_QAM_WR_RSV_0__W 16 +-#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 +- +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +-#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +-#define SCU_RAM_QAM_WR_RSV_5__W 16 +-#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +-#define SCU_RAM_QAM_WR_RSV_6__W 16 +-#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +-#define SCU_RAM_QAM_WR_RSV_7__W 16 +-#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +-#define SCU_RAM_QAM_WR_RSV_8__W 16 +-#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +-#define SCU_RAM_QAM_WR_RSV_9__W 16 +-#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +-#define SCU_RAM_QAM_WR_RSV_10__W 16 +-#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +-#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +-#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258 +- +-#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +-#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +-#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258 +-#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 +- +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +-#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +-#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +-#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +-#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 +- +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +-#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +-#define SCU_RAM_QAM_FSM_ATH__W 16 +-#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +-#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +-#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +-#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +-#define SCU_RAM_QAM_FSM_RTH__W 16 +-#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B +- +-#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +-#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +-#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B +-#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +-#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +-#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +-#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +-#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D +- +-#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +-#define SCU_RAM_QAM_FSM_FTH__W 16 +-#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C +- +-#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +-#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +-#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C +-#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +-#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +-#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +-#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +-#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 +- +-#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +-#define SCU_RAM_QAM_FSM_PTH__W 16 +-#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +-#define SCU_RAM_QAM_FSM_PTH__PRE 0x64 +- +-#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +-#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +-#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64 +-#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +-#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +-#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +-#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +-#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 +- +-#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +-#define SCU_RAM_QAM_FSM_MTH__W 16 +-#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +-#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E +- +-#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +-#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +-#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E +-#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +-#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +-#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +-#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +-#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 +- +-#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +-#define SCU_RAM_QAM_FSM_CTH__W 16 +-#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +-#define SCU_RAM_QAM_FSM_CTH__PRE 0x50 +- +-#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +-#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +-#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50 +-#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +-#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +-#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +-#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +-#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C +- +-#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +-#define SCU_RAM_QAM_FSM_QTH__W 16 +-#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +-#define SCU_RAM_QAM_FSM_QTH__PRE 0x96 +- +-#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +-#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +-#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96 +-#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +-#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +-#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +-#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +-#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 +- +-#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +-#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +-#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28 +- +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28 +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +-#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 +- +-#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +-#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +-#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF +- +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +-#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 +- +-#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +-#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +-#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +-#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4 +- +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4 +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +-#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 +- +-#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +-#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +-#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28 +- +-#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28 +- +-#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +-#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +-#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +-#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28 +- +-#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +-#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +-#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28 +- +-#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +-#define SCU_RAM_QAM_LC_CA_FINE__W 16 +-#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF +- +-#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF +- +-#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +-#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +-#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64 +- +-#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64 +- +-#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +-#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +-#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +-#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E +- +-#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +-#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +-#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E +- +-#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +-#define SCU_RAM_QAM_LC_CP_FINE__W 16 +-#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5 +- +-#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5 +- +-#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +-#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +-#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32 +- +-#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32 +- +-#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +-#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +-#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +-#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E +- +-#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +-#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +-#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E +- +-#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +-#define SCU_RAM_QAM_LC_CI_FINE__W 16 +-#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5 +- +-#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5 +- +-#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +-#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +-#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +-#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18 +- +-#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +-#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +-#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18 +- +-#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +-#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +-#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +-#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18 +- +-#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +-#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +-#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18 +- +-#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +-#define SCU_RAM_QAM_LC_EP_FINE__W 16 +-#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +-#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC +- +-#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +-#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +-#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC +- +-#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +-#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +-#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +-#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10 +- +-#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +-#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +-#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10 +- +-#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +-#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +-#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +-#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10 +- +-#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +-#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +-#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10 +- +-#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +-#define SCU_RAM_QAM_LC_EI_FINE__W 16 +-#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +-#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC +- +-#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +-#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +-#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC +- +-#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +-#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +-#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 +- +-#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 +- +-#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +-#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +-#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +-#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 +- +-#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +-#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +-#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 +- +-#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +-#define SCU_RAM_QAM_LC_CF_FINE__W 16 +-#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 +- +-#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 +- +-#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +-#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +-#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA +- +-#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA +- +-#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +-#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +-#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +-#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA +- +-#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +-#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +-#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA +- +-#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +-#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +-#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +-#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 +- +-#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +-#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +-#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +-#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 +- +-#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +-#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +-#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +-#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00 +- +-#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +-#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +-#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +-#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +-#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +-#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE +- +-#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +-#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A +- +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +-#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +-#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +-#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF +- +-#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +-#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +-#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +-#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +-#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D +- +-#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +-#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 +- +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +-#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 +- +-#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +-#define SCU_RAM_QAM_CTL_ENA__W 16 +-#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +-#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF +- +-#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +-#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +-#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +-#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1 +- +-#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +-#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +-#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +-#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2 +- +-#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +-#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +-#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +-#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4 +- +-#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +-#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +-#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +-#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8 +- +-#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +-#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +-#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +-#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10 +- +-#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +-#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +-#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +-#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20 +- +-#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +-#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +-#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +-#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40 +- +-#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +-#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +-#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +-#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80 +- +-#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +-#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +-#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +-#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100 +- +-#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +-#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +-#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +-#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200 +- +-#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +-#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +-#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +-#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400 +- +-#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +-#define SCU_RAM_QAM_WR_RSV_1__W 16 +-#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +-#define SCU_RAM_QAM_WR_RSV_2__W 16 +-#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +-#define SCU_RAM_QAM_WR_RSV_3__W 16 +-#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 +- +-#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +-#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +-#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +-#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 +- +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +-#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 +- +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1 +- +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +-#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE +- +-#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +-#define SCU_RAM_QAM_RD_RSV_4__W 16 +-#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_LOCKED__A 0x831FBA +-#define SCU_RAM_QAM_LOCKED__W 16 +-#define SCU_RAM_QAM_LOCKED__M 0xFFFF +-#define SCU_RAM_QAM_LOCKED__PRE 0x0 +- +-#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +-#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +-#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 +- +-#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +-#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +-#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +-#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +-#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +-#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +-#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +-#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +-#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +-#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +-#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +-#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +-#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +-#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +-#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +-#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +-#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +-#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +-#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +-#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +-#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +-#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +-#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +-#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +-#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 +- +-#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +-#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +-#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +-#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +-#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +-#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +-#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 +- +-#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +-#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +-#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +-#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +-#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +-#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +-#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 +- +-#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +-#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +-#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +-#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 +- +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 +- +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +-#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +-#define SCU_RAM_QAM_RD_RSV_5__W 16 +-#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +-#define SCU_RAM_QAM_RD_RSV_6__W 16 +-#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +-#define SCU_RAM_QAM_RD_RSV_7__W 16 +-#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +-#define SCU_RAM_QAM_RD_RSV_8__W 16 +-#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +-#define SCU_RAM_QAM_RD_RSV_9__W 16 +-#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +-#define SCU_RAM_QAM_RD_RSV_10__W 16 +-#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +-#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +-#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +-#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 +- +-#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +-#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +-#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +-#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +-#define SCU_RAM_QAM_FSM_STATE__W 4 +-#define SCU_RAM_QAM_FSM_STATE__M 0xF +-#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +-#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +-#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +-#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +-#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +-#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +-#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +-#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +-#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +-#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +-#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +-#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 +- +-#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +-#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +-#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +-#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +-#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000 +-#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0 +- +-#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +-#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +-#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46 +- +-#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +-#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +-#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46 +- +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E +- +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +-#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E +- +-#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +-#define SCU_RAM_QAM_ERR_STATE__W 4 +-#define SCU_RAM_QAM_ERR_STATE__M 0xF +-#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 +- +-#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +-#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +-#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +-#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +-#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +-#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +-#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +-#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +-#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +-#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +-#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +-#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 +- +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 +- +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +-#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 +- +-#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +-#define SCU_RAM_QAM_EQ_LOCK__W 1 +-#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +-#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 +- +-#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +-#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +-#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +-#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +-#define SCU_RAM_QAM_EQ_STATE__W 16 +-#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +-#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 +- +-#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +-#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +-#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +-#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +-#define SCU_RAM_QAM_RD_RSV_0__W 16 +-#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +-#define SCU_RAM_QAM_RD_RSV_1__W 16 +-#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +-#define SCU_RAM_QAM_RD_RSV_2__W 16 +-#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +-#define SCU_RAM_QAM_RD_RSV_3__W 16 +-#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 +- +-#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +-#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +-#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +-#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 +- +- +-#define SCU_RAM_FREE_8151__A 0x831FD7 +-#define SCU_RAM_FREE_8151__W 16 +-#define SCU_RAM_FREE_8151__M 0xFFFF +-#define SCU_RAM_FREE_8151__PRE 0x0 +- +-#define SCU_RAM_FREE_8152__A 0x831FD8 +-#define SCU_RAM_FREE_8152__W 16 +-#define SCU_RAM_FREE_8152__M 0xFFFF +-#define SCU_RAM_FREE_8152__PRE 0x0 +- +-#define SCU_RAM_FREE_8153__A 0x831FD9 +-#define SCU_RAM_FREE_8153__W 16 +-#define SCU_RAM_FREE_8153__M 0xFFFF +-#define SCU_RAM_FREE_8153__PRE 0x0 +- +-#define SCU_RAM_FREE_8154__A 0x831FDA +-#define SCU_RAM_FREE_8154__W 16 +-#define SCU_RAM_FREE_8154__M 0xFFFF +-#define SCU_RAM_FREE_8154__PRE 0x0 +- +-#define SCU_RAM_FREE_8155__A 0x831FDB +-#define SCU_RAM_FREE_8155__W 16 +-#define SCU_RAM_FREE_8155__M 0xFFFF +-#define SCU_RAM_FREE_8155__PRE 0x0 +- +-#define SCU_RAM_FREE_8156__A 0x831FDC +-#define SCU_RAM_FREE_8156__W 16 +-#define SCU_RAM_FREE_8156__M 0xFFFF +-#define SCU_RAM_FREE_8156__PRE 0x0 +- +-#define SCU_RAM_FREE_8157__A 0x831FDD +-#define SCU_RAM_FREE_8157__W 16 +-#define SCU_RAM_FREE_8157__M 0xFFFF +-#define SCU_RAM_FREE_8157__PRE 0x0 +- +-#define SCU_RAM_FREE_8158__A 0x831FDE +-#define SCU_RAM_FREE_8158__W 16 +-#define SCU_RAM_FREE_8158__M 0xFFFF +-#define SCU_RAM_FREE_8158__PRE 0x0 +- +-#define SCU_RAM_FREE_8159__A 0x831FDF +-#define SCU_RAM_FREE_8159__W 16 +-#define SCU_RAM_FREE_8159__M 0xFFFF +-#define SCU_RAM_FREE_8159__PRE 0x0 +- +-#define SCU_RAM_FREE_8160__A 0x831FE0 +-#define SCU_RAM_FREE_8160__W 16 +-#define SCU_RAM_FREE_8160__M 0xFFFF +-#define SCU_RAM_FREE_8160__PRE 0x0 +- +-#define SCU_RAM_FREE_8161__A 0x831FE1 +-#define SCU_RAM_FREE_8161__W 16 +-#define SCU_RAM_FREE_8161__M 0xFFFF +-#define SCU_RAM_FREE_8161__PRE 0x0 +- +-#define SCU_RAM_FREE_8162__A 0x831FE2 +-#define SCU_RAM_FREE_8162__W 16 +-#define SCU_RAM_FREE_8162__M 0xFFFF +-#define SCU_RAM_FREE_8162__PRE 0x0 +- +-#define SCU_RAM_FREE_8163__A 0x831FE3 +-#define SCU_RAM_FREE_8163__W 16 +-#define SCU_RAM_FREE_8163__M 0xFFFF +-#define SCU_RAM_FREE_8163__PRE 0x0 +- +-#define SCU_RAM_FREE_8164__A 0x831FE4 +-#define SCU_RAM_FREE_8164__W 16 +-#define SCU_RAM_FREE_8164__M 0xFFFF +-#define SCU_RAM_FREE_8164__PRE 0x0 +- +-#define SCU_RAM_FREE_8165__A 0x831FE5 +-#define SCU_RAM_FREE_8165__W 16 +-#define SCU_RAM_FREE_8165__M 0xFFFF +-#define SCU_RAM_FREE_8165__PRE 0x0 +- +-#define SCU_RAM_FREE_8166__A 0x831FE6 +-#define SCU_RAM_FREE_8166__W 16 +-#define SCU_RAM_FREE_8166__M 0xFFFF +-#define SCU_RAM_FREE_8166__PRE 0x0 +- +-#define SCU_RAM_FREE_8167__A 0x831FE7 +-#define SCU_RAM_FREE_8167__W 16 +-#define SCU_RAM_FREE_8167__M 0xFFFF +-#define SCU_RAM_FREE_8167__PRE 0x0 +- +-#define SCU_RAM_FREE_8168__A 0x831FE8 +-#define SCU_RAM_FREE_8168__W 16 +-#define SCU_RAM_FREE_8168__M 0xFFFF +-#define SCU_RAM_FREE_8168__PRE 0x0 +- +-#define SCU_RAM_FREE_8169__A 0x831FE9 +-#define SCU_RAM_FREE_8169__W 16 +-#define SCU_RAM_FREE_8169__M 0xFFFF +-#define SCU_RAM_FREE_8169__PRE 0x0 +- +-#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +-#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +-#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +-#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E +- +-#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +-#define SCU_RAM_DRIVER_VER_HI__W 16 +-#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +-#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 +- +-#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +-#define SCU_RAM_DRIVER_VER_LO__W 16 +-#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +-#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 +- +-#define SCU_RAM_PARAM_15__A 0x831FED +-#define SCU_RAM_PARAM_15__W 16 +-#define SCU_RAM_PARAM_15__M 0xFFFF +-#define SCU_RAM_PARAM_15__PRE 0x0 +- +-#define SCU_RAM_PARAM_14__A 0x831FEE +-#define SCU_RAM_PARAM_14__W 16 +-#define SCU_RAM_PARAM_14__M 0xFFFF +-#define SCU_RAM_PARAM_14__PRE 0x0 +- +-#define SCU_RAM_PARAM_13__A 0x831FEF +-#define SCU_RAM_PARAM_13__W 16 +-#define SCU_RAM_PARAM_13__M 0xFFFF +-#define SCU_RAM_PARAM_13__PRE 0x0 +- +-#define SCU_RAM_PARAM_12__A 0x831FF0 +-#define SCU_RAM_PARAM_12__W 16 +-#define SCU_RAM_PARAM_12__M 0xFFFF +-#define SCU_RAM_PARAM_12__PRE 0x0 +- +-#define SCU_RAM_PARAM_11__A 0x831FF1 +-#define SCU_RAM_PARAM_11__W 16 +-#define SCU_RAM_PARAM_11__M 0xFFFF +-#define SCU_RAM_PARAM_11__PRE 0x0 +- +-#define SCU_RAM_PARAM_10__A 0x831FF2 +-#define SCU_RAM_PARAM_10__W 16 +-#define SCU_RAM_PARAM_10__M 0xFFFF +-#define SCU_RAM_PARAM_10__PRE 0x0 +- +-#define SCU_RAM_PARAM_9__A 0x831FF3 +-#define SCU_RAM_PARAM_9__W 16 +-#define SCU_RAM_PARAM_9__M 0xFFFF +-#define SCU_RAM_PARAM_9__PRE 0x0 +- +-#define SCU_RAM_PARAM_8__A 0x831FF4 +-#define SCU_RAM_PARAM_8__W 16 +-#define SCU_RAM_PARAM_8__M 0xFFFF +-#define SCU_RAM_PARAM_8__PRE 0x0 +- +-#define SCU_RAM_PARAM_7__A 0x831FF5 +-#define SCU_RAM_PARAM_7__W 16 +-#define SCU_RAM_PARAM_7__M 0xFFFF +-#define SCU_RAM_PARAM_7__PRE 0x0 +- +-#define SCU_RAM_PARAM_6__A 0x831FF6 +-#define SCU_RAM_PARAM_6__W 16 +-#define SCU_RAM_PARAM_6__M 0xFFFF +-#define SCU_RAM_PARAM_6__PRE 0x0 +- +-#define SCU_RAM_PARAM_5__A 0x831FF7 +-#define SCU_RAM_PARAM_5__W 16 +-#define SCU_RAM_PARAM_5__M 0xFFFF +-#define SCU_RAM_PARAM_5__PRE 0x0 +- +-#define SCU_RAM_PARAM_4__A 0x831FF8 +-#define SCU_RAM_PARAM_4__W 16 +-#define SCU_RAM_PARAM_4__M 0xFFFF +-#define SCU_RAM_PARAM_4__PRE 0x0 +- +-#define SCU_RAM_PARAM_3__A 0x831FF9 +-#define SCU_RAM_PARAM_3__W 16 +-#define SCU_RAM_PARAM_3__M 0xFFFF +-#define SCU_RAM_PARAM_3__PRE 0x0 +- +-#define SCU_RAM_PARAM_2__A 0x831FFA +-#define SCU_RAM_PARAM_2__W 16 +-#define SCU_RAM_PARAM_2__M 0xFFFF +-#define SCU_RAM_PARAM_2__PRE 0x0 +- +-#define SCU_RAM_PARAM_1__A 0x831FFB +-#define SCU_RAM_PARAM_1__W 16 +-#define SCU_RAM_PARAM_1__M 0xFFFF +-#define SCU_RAM_PARAM_1__PRE 0x0 +-#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +-#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +-#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +-#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 +- +- +-#define SCU_RAM_PARAM_0__A 0x831FFC +-#define SCU_RAM_PARAM_0__W 16 +-#define SCU_RAM_PARAM_0__M 0xFFFF +-#define SCU_RAM_PARAM_0__PRE 0x0 +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +-#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +-#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +-#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +-#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +-#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +-#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +-#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +-#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +-#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +-#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC +- +- +-#define SCU_RAM_COMMAND__A 0x831FFD +-#define SCU_RAM_COMMAND__W 16 +-#define SCU_RAM_COMMAND__M 0xFFFF +-#define SCU_RAM_COMMAND__PRE 0x0 +-#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +-#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +-#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +-#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +-#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +-#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +-#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +-#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +-#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +-#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +-#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +-#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +-#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +-#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +-#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +-#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +-#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +-#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +-#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +-#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +-#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85 +-#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86 +-#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87 +-#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +-#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +-#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +-#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 +-#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1 +- +-#define SCU_RAM_COMMAND_STANDARD__B 8 +-#define SCU_RAM_COMMAND_STANDARD__W 8 +-#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +-#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +-#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +-#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +-#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +-#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +-#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +-#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 +- +-#define SCU_RAM_VERSION_HI__A 0x831FFE +-#define SCU_RAM_VERSION_HI__W 16 +-#define SCU_RAM_VERSION_HI__M 0xFFFF +-#define SCU_RAM_VERSION_HI__PRE 0x0 +- +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 +- +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 +- +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +-#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 +- +-#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +-#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +-#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +-#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 +- +-#define SCU_RAM_VERSION_LO__A 0x831FFF +-#define SCU_RAM_VERSION_LO__W 16 +-#define SCU_RAM_VERSION_LO__M 0xFFFF +-#define SCU_RAM_VERSION_LO__PRE 0x0 +- +-#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 +- +-#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 +- +-#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 +- +-#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +-#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +-#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 +- +- +- +- +- +-#define SIO_COMM_EXEC__A 0x400000 +-#define SIO_COMM_EXEC__W 2 +-#define SIO_COMM_EXEC__M 0x3 +-#define SIO_COMM_EXEC__PRE 0x0 +-#define SIO_COMM_EXEC_STOP 0x0 +-#define SIO_COMM_EXEC_ACTIVE 0x1 +-#define SIO_COMM_EXEC_HOLD 0x2 +- +-#define SIO_COMM_STATE__A 0x400001 +-#define SIO_COMM_STATE__W 16 +-#define SIO_COMM_STATE__M 0xFFFF +-#define SIO_COMM_STATE__PRE 0x0 +-#define SIO_COMM_MB__A 0x400002 +-#define SIO_COMM_MB__W 16 +-#define SIO_COMM_MB__M 0xFFFF +-#define SIO_COMM_MB__PRE 0x0 +-#define SIO_COMM_INT_REQ__A 0x400003 +-#define SIO_COMM_INT_REQ__W 16 +-#define SIO_COMM_INT_REQ__M 0xFFFF +-#define SIO_COMM_INT_REQ__PRE 0x0 +- +-#define SIO_COMM_INT_REQ_HI_REQ__B 0 +-#define SIO_COMM_INT_REQ_HI_REQ__W 1 +-#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +-#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 +- +-#define SIO_COMM_INT_REQ_SA_REQ__B 1 +-#define SIO_COMM_INT_REQ_SA_REQ__W 1 +-#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +-#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 +- +-#define SIO_COMM_INT_REQ_BL_REQ__B 2 +-#define SIO_COMM_INT_REQ_BL_REQ__W 1 +-#define SIO_COMM_INT_REQ_BL_REQ__M 0x4 +-#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0 +- +-#define SIO_COMM_INT_STA__A 0x400005 +-#define SIO_COMM_INT_STA__W 16 +-#define SIO_COMM_INT_STA__M 0xFFFF +-#define SIO_COMM_INT_STA__PRE 0x0 +-#define SIO_COMM_INT_MSK__A 0x400006 +-#define SIO_COMM_INT_MSK__W 16 +-#define SIO_COMM_INT_MSK__M 0xFFFF +-#define SIO_COMM_INT_MSK__PRE 0x0 +-#define SIO_COMM_INT_STM__A 0x400007 +-#define SIO_COMM_INT_STM__W 16 +-#define SIO_COMM_INT_STM__M 0xFFFF +-#define SIO_COMM_INT_STM__PRE 0x0 +- +- +- +-#define SIO_TOP_COMM_EXEC__A 0x410000 +-#define SIO_TOP_COMM_EXEC__W 2 +-#define SIO_TOP_COMM_EXEC__M 0x3 +-#define SIO_TOP_COMM_EXEC__PRE 0x0 +-#define SIO_TOP_COMM_EXEC_STOP 0x0 +-#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +-#define SIO_TOP_COMM_EXEC_HOLD 0x2 +- +- +-#define SIO_TOP_COMM_KEY__A 0x41000F +-#define SIO_TOP_COMM_KEY__W 16 +-#define SIO_TOP_COMM_KEY__M 0xFFFF +-#define SIO_TOP_COMM_KEY__PRE 0x0 +-#define SIO_TOP_COMM_KEY_KEY 0xFABA +- +- +-#define SIO_TOP_JTAGID_LO__A 0x410012 +-#define SIO_TOP_JTAGID_LO__W 16 +-#define SIO_TOP_JTAGID_LO__M 0xFFFF +-#define SIO_TOP_JTAGID_LO__PRE 0x0 +- +-#define SIO_TOP_JTAGID_HI__A 0x410013 +-#define SIO_TOP_JTAGID_HI__W 16 +-#define SIO_TOP_JTAGID_HI__M 0xFFFF +-#define SIO_TOP_JTAGID_HI__PRE 0x0 +- +- +- +- +-#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +-#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +-#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +-#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +-#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +-#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +-#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 +- +-#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +-#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +-#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +-#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +-#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +-#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +-#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +-#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +-#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +-#define SIO_HI_RA_RAM_S0_STATE__W 1 +-#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +-#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +-#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +-#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +-#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +-#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +-#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +-#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 +- +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 +- +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +-#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 +- +-#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +-#define SIO_HI_RA_RAM_S0_ADDR__W 16 +-#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +-#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +-#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +-#define SIO_HI_RA_RAM_S0_CRC__W 16 +-#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +-#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +-#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +-#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +-#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +-#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +-#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +-#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +-#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +-#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +-#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +-#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +-#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +-#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +-#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +-#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +-#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +-#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +-#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +-#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +-#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 +- +-#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +-#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +-#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +-#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +-#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +-#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +-#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +-#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +-#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +-#define SIO_HI_RA_RAM_S1_STATE__W 1 +-#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +-#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +-#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +-#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +-#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +-#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +-#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +-#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 +- +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 +- +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +-#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 +- +-#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +-#define SIO_HI_RA_RAM_S1_ADDR__W 16 +-#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +-#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +-#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +-#define SIO_HI_RA_RAM_S1_CRC__W 16 +-#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +-#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +-#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +-#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +-#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +-#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +-#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +-#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +-#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +-#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +-#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +-#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 +- +-#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +-#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +-#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +-#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +-#define SIO_HI_RA_RAM_SEMA__A 0x420030 +-#define SIO_HI_RA_RAM_SEMA__W 1 +-#define SIO_HI_RA_RAM_SEMA__M 0x1 +-#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +-#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +-#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 +- +-#define SIO_HI_RA_RAM_RES__A 0x420031 +-#define SIO_HI_RA_RAM_RES__W 3 +-#define SIO_HI_RA_RAM_RES__M 0x7 +-#define SIO_HI_RA_RAM_RES__PRE 0x0 +-#define SIO_HI_RA_RAM_RES_OK 0x0 +-#define SIO_HI_RA_RAM_RES_ERROR 0x1 +-#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +-#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +-#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +-#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 +- +-#define SIO_HI_RA_RAM_CMD__A 0x420032 +-#define SIO_HI_RA_RAM_CMD__W 4 +-#define SIO_HI_RA_RAM_CMD__M 0xF +-#define SIO_HI_RA_RAM_CMD__PRE 0x0 +-#define SIO_HI_RA_RAM_CMD_NULL 0x0 +-#define SIO_HI_RA_RAM_CMD_UIO 0x1 +-#define SIO_HI_RA_RAM_CMD_RESET 0x2 +-#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +-#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +-#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +-#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +-#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +-#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 +- +-#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +-#define SIO_HI_RA_RAM_PAR_1__W 16 +-#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +-#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +-#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 +- +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +-#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +-#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 +- +-#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +-#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +-#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +-#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +-#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +-#define SIO_HI_RA_RAM_PAR_2__W 16 +-#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +-#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +-#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +-#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +-#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +-#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 +- +-#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +-#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +-#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +-#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +-#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +-#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 +- +-#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +-#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +-#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +-#define SIO_HI_RA_RAM_PAR_3__W 16 +-#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +-#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +-#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F +- +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +-#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 +- +-#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +-#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +-#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +-#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +-#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +-#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +-#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +-#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +-#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +-#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 +- +-#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +-#define SIO_HI_RA_RAM_PAR_4__W 16 +-#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +-#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +-#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +-#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +-#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +-#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 +- +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +-#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +-#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +-#define SIO_HI_RA_RAM_PAR_5__W 16 +-#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +-#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +-#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 +- +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 +- +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 +- +-#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +-#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +-#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +-#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +-#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 +- +-#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +-#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +-#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +-#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +-#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +-#define SIO_HI_RA_RAM_PAR_6__W 16 +-#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +-#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +-#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +-#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +-#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 +- +-#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +-#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +-#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +-#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF +- +-#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +-#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +-#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +-#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 +- +- +-#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +-#define SIO_HI_RA_RAM_AB_TEMP__W 16 +-#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +-#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 +- +-#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +-#define SIO_HI_RA_RAM_I2C_CTL__W 16 +-#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +-#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +-#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +-#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +-#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +-#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +-#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +-#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +-#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +-#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +-#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +-#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +-#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +-#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +-#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +-#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +-#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +-#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +-#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +-#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +-#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +-#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +-#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 +- +- +-#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +-#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +-#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +-#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +-#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 +- +-#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +-#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +-#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +-#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 +- +- +- +-#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +-#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +-#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +-#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +-#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +-#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +-#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +-#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +-#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +-#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +-#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +-#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +-#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +-#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +-#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +-#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +-#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +-#define SIO_HI_IF_RAM_FUN_BASE__W 12 +-#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +-#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 +- +- +- +-#define SIO_HI_IF_COMM_EXEC__A 0x440000 +-#define SIO_HI_IF_COMM_EXEC__W 2 +-#define SIO_HI_IF_COMM_EXEC__M 0x3 +-#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +-#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +-#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +-#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +-#define SIO_HI_IF_COMM_EXEC_STEP 0x3 +- +- +-#define SIO_HI_IF_COMM_STATE__A 0x440001 +-#define SIO_HI_IF_COMM_STATE__W 10 +-#define SIO_HI_IF_COMM_STATE__M 0x3FF +-#define SIO_HI_IF_COMM_STATE__PRE 0x0 +-#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +-#define SIO_HI_IF_COMM_INT_REQ__W 1 +-#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +-#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +-#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +-#define SIO_HI_IF_COMM_INT_STA__W 1 +-#define SIO_HI_IF_COMM_INT_STA__M 0x1 +-#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +-#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +-#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +-#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +-#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 +- +-#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +-#define SIO_HI_IF_COMM_INT_MSK__W 1 +-#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +-#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +-#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +-#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +-#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +-#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 +- +-#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +-#define SIO_HI_IF_COMM_INT_STM__W 1 +-#define SIO_HI_IF_COMM_INT_STM__M 0x1 +-#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +-#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +-#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +-#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +-#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 +- +-#define SIO_HI_IF_STK_0__A 0x440010 +-#define SIO_HI_IF_STK_0__W 10 +-#define SIO_HI_IF_STK_0__M 0x3FF +-#define SIO_HI_IF_STK_0__PRE 0x2 +- +-#define SIO_HI_IF_STK_0_ADDR__B 0 +-#define SIO_HI_IF_STK_0_ADDR__W 10 +-#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +-#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 +- +-#define SIO_HI_IF_STK_1__A 0x440011 +-#define SIO_HI_IF_STK_1__W 10 +-#define SIO_HI_IF_STK_1__M 0x3FF +-#define SIO_HI_IF_STK_1__PRE 0x2 +-#define SIO_HI_IF_STK_1_ADDR__B 0 +-#define SIO_HI_IF_STK_1_ADDR__W 10 +-#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +-#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 +- +-#define SIO_HI_IF_STK_2__A 0x440012 +-#define SIO_HI_IF_STK_2__W 10 +-#define SIO_HI_IF_STK_2__M 0x3FF +-#define SIO_HI_IF_STK_2__PRE 0x2 +-#define SIO_HI_IF_STK_2_ADDR__B 0 +-#define SIO_HI_IF_STK_2_ADDR__W 10 +-#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +-#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 +- +-#define SIO_HI_IF_STK_3__A 0x440013 +-#define SIO_HI_IF_STK_3__W 10 +-#define SIO_HI_IF_STK_3__M 0x3FF +-#define SIO_HI_IF_STK_3__PRE 0x2 +- +-#define SIO_HI_IF_STK_3_ADDR__B 0 +-#define SIO_HI_IF_STK_3_ADDR__W 10 +-#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +-#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 +- +-#define SIO_HI_IF_BPT_IDX__A 0x44001F +-#define SIO_HI_IF_BPT_IDX__W 1 +-#define SIO_HI_IF_BPT_IDX__M 0x1 +-#define SIO_HI_IF_BPT_IDX__PRE 0x0 +- +-#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +-#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +-#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +-#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 +- +-#define SIO_HI_IF_BPT__A 0x440020 +-#define SIO_HI_IF_BPT__W 10 +-#define SIO_HI_IF_BPT__M 0x3FF +-#define SIO_HI_IF_BPT__PRE 0x2 +- +-#define SIO_HI_IF_BPT_ADDR__B 0 +-#define SIO_HI_IF_BPT_ADDR__W 10 +-#define SIO_HI_IF_BPT_ADDR__M 0x3FF +-#define SIO_HI_IF_BPT_ADDR__PRE 0x2 +- +- +- +-#define SIO_CC_COMM_EXEC__A 0x450000 +-#define SIO_CC_COMM_EXEC__W 2 +-#define SIO_CC_COMM_EXEC__M 0x3 +-#define SIO_CC_COMM_EXEC__PRE 0x0 +-#define SIO_CC_COMM_EXEC_STOP 0x0 +-#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +-#define SIO_CC_COMM_EXEC_HOLD 0x2 +- +-#define SIO_CC_PLL_MODE__A 0x450010 +-#define SIO_CC_PLL_MODE__W 6 +-#define SIO_CC_PLL_MODE__M 0x3F +-#define SIO_CC_PLL_MODE__PRE 0x0 +- +-#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +-#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +-#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +-#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +-#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +-#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +-#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +-#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 +- +-#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +-#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +-#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +-#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 +- +-#define SIO_CC_PLL_MODE_BYPASS__B 4 +-#define SIO_CC_PLL_MODE_BYPASS__W 2 +-#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +-#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +-#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +-#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +-#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 +- +- +-#define SIO_CC_PLL_TEST__A 0x450011 +-#define SIO_CC_PLL_TEST__W 8 +-#define SIO_CC_PLL_TEST__M 0xFF +-#define SIO_CC_PLL_TEST__PRE 0x0 +- +-#define SIO_CC_PLL_LOCK__A 0x450012 +-#define SIO_CC_PLL_LOCK__W 1 +-#define SIO_CC_PLL_LOCK__M 0x1 +-#define SIO_CC_PLL_LOCK__PRE 0x0 +-#define SIO_CC_CLK_TEST__A 0x450013 +-#define SIO_CC_CLK_TEST__W 8 +-#define SIO_CC_CLK_TEST__M 0xFF +-#define SIO_CC_CLK_TEST__PRE 0x0 +- +-#define SIO_CC_CLK_TEST_SEL1__B 0 +-#define SIO_CC_CLK_TEST_SEL1__W 3 +-#define SIO_CC_CLK_TEST_SEL1__M 0x7 +-#define SIO_CC_CLK_TEST_SEL1__PRE 0x0 +- +-#define SIO_CC_CLK_TEST_ENAB1__B 3 +-#define SIO_CC_CLK_TEST_ENAB1__W 1 +-#define SIO_CC_CLK_TEST_ENAB1__M 0x8 +-#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0 +- +-#define SIO_CC_CLK_TEST_SEL2__B 4 +-#define SIO_CC_CLK_TEST_SEL2__W 3 +-#define SIO_CC_CLK_TEST_SEL2__M 0x70 +-#define SIO_CC_CLK_TEST_SEL2__PRE 0x0 +- +-#define SIO_CC_CLK_TEST_ENAB2__B 7 +-#define SIO_CC_CLK_TEST_ENAB2__W 1 +-#define SIO_CC_CLK_TEST_ENAB2__M 0x80 +-#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0 +- +-#define SIO_CC_CLK_MODE__A 0x450014 +-#define SIO_CC_CLK_MODE__W 7 +-#define SIO_CC_CLK_MODE__M 0x7F +-#define SIO_CC_CLK_MODE__PRE 0x0 +- +-#define SIO_CC_CLK_MODE_DELAY__B 0 +-#define SIO_CC_CLK_MODE_DELAY__W 4 +-#define SIO_CC_CLK_MODE_DELAY__M 0xF +-#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 +- +-#define SIO_CC_CLK_MODE_INVERT__B 4 +-#define SIO_CC_CLK_MODE_INVERT__W 1 +-#define SIO_CC_CLK_MODE_INVERT__M 0x10 +-#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 +- +-#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5 +-#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1 +-#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20 +-#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0 +- +-#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6 +-#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1 +-#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40 +-#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0 +- +-#define SIO_CC_PWD_MODE__A 0x450015 +-#define SIO_CC_PWD_MODE__W 4 +-#define SIO_CC_PWD_MODE__M 0xF +-#define SIO_CC_PWD_MODE__PRE 0x0 +- +-#define SIO_CC_PWD_MODE_LEVEL__B 0 +-#define SIO_CC_PWD_MODE_LEVEL__W 3 +-#define SIO_CC_PWD_MODE_LEVEL__M 0x7 +-#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +-#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +-#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 +-#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +-#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 +-#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 +- +-#define SIO_CC_PWD_MODE_USE_LOCK__B 3 +-#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +-#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8 +-#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 +- +-#define SIO_CC_SOFT_RST__A 0x450016 +-#define SIO_CC_SOFT_RST__W 3 +-#define SIO_CC_SOFT_RST__M 0x7 +-#define SIO_CC_SOFT_RST__PRE 0x0 +- +-#define SIO_CC_SOFT_RST_OFDM__B 0 +-#define SIO_CC_SOFT_RST_OFDM__W 1 +-#define SIO_CC_SOFT_RST_OFDM__M 0x1 +-#define SIO_CC_SOFT_RST_OFDM__PRE 0x0 +- +-#define SIO_CC_SOFT_RST_SYS__B 1 +-#define SIO_CC_SOFT_RST_SYS__W 1 +-#define SIO_CC_SOFT_RST_SYS__M 0x2 +-#define SIO_CC_SOFT_RST_SYS__PRE 0x0 +- +-#define SIO_CC_SOFT_RST_OSC__B 2 +-#define SIO_CC_SOFT_RST_OSC__W 1 +-#define SIO_CC_SOFT_RST_OSC__M 0x4 +-#define SIO_CC_SOFT_RST_OSC__PRE 0x0 +- +- +-#define SIO_CC_UPDATE__A 0x450017 +-#define SIO_CC_UPDATE__W 16 +-#define SIO_CC_UPDATE__M 0xFFFF +-#define SIO_CC_UPDATE__PRE 0x0 +-#define SIO_CC_UPDATE_KEY 0xFABA +- +- +- +-#define SIO_SA_COMM_EXEC__A 0x460000 +-#define SIO_SA_COMM_EXEC__W 2 +-#define SIO_SA_COMM_EXEC__M 0x3 +-#define SIO_SA_COMM_EXEC__PRE 0x0 +-#define SIO_SA_COMM_EXEC_STOP 0x0 +-#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +-#define SIO_SA_COMM_EXEC_HOLD 0x2 +- +-#define SIO_SA_COMM_INT_REQ__A 0x460003 +-#define SIO_SA_COMM_INT_REQ__W 1 +-#define SIO_SA_COMM_INT_REQ__M 0x1 +-#define SIO_SA_COMM_INT_REQ__PRE 0x0 +-#define SIO_SA_COMM_INT_STA__A 0x460005 +-#define SIO_SA_COMM_INT_STA__W 4 +-#define SIO_SA_COMM_INT_STA__M 0xF +-#define SIO_SA_COMM_INT_STA__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +-#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +-#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +-#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +-#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +-#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +-#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +-#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +-#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +-#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +-#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +-#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +-#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 +- +-#define SIO_SA_COMM_INT_MSK__A 0x460006 +-#define SIO_SA_COMM_INT_MSK__W 4 +-#define SIO_SA_COMM_INT_MSK__M 0xF +-#define SIO_SA_COMM_INT_MSK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +-#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +-#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +-#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +-#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +-#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +-#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +-#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +-#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +-#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +-#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +-#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +-#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STM__A 0x460007 +-#define SIO_SA_COMM_INT_STM__W 4 +-#define SIO_SA_COMM_INT_STM__M 0xF +-#define SIO_SA_COMM_INT_STM__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +-#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +-#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +-#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +-#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +-#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +-#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +-#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +-#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +-#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 +- +-#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +-#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +-#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +-#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 +- +-#define SIO_SA_PRESCALER__A 0x460010 +-#define SIO_SA_PRESCALER__W 13 +-#define SIO_SA_PRESCALER__M 0x1FFF +-#define SIO_SA_PRESCALER__PRE 0x18B7 +-#define SIO_SA_TX_DATA0__A 0x460011 +-#define SIO_SA_TX_DATA0__W 16 +-#define SIO_SA_TX_DATA0__M 0xFFFF +-#define SIO_SA_TX_DATA0__PRE 0x0 +-#define SIO_SA_TX_DATA1__A 0x460012 +-#define SIO_SA_TX_DATA1__W 16 +-#define SIO_SA_TX_DATA1__M 0xFFFF +-#define SIO_SA_TX_DATA1__PRE 0x0 +-#define SIO_SA_TX_DATA2__A 0x460013 +-#define SIO_SA_TX_DATA2__W 16 +-#define SIO_SA_TX_DATA2__M 0xFFFF +-#define SIO_SA_TX_DATA2__PRE 0x0 +-#define SIO_SA_TX_DATA3__A 0x460014 +-#define SIO_SA_TX_DATA3__W 16 +-#define SIO_SA_TX_DATA3__M 0xFFFF +-#define SIO_SA_TX_DATA3__PRE 0x0 +-#define SIO_SA_TX_LENGTH__A 0x460015 +-#define SIO_SA_TX_LENGTH__W 6 +-#define SIO_SA_TX_LENGTH__M 0x3F +-#define SIO_SA_TX_LENGTH__PRE 0x0 +-#define SIO_SA_TX_COMMAND__A 0x460016 +-#define SIO_SA_TX_COMMAND__W 2 +-#define SIO_SA_TX_COMMAND__M 0x3 +-#define SIO_SA_TX_COMMAND__PRE 0x3 +- +-#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +-#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +-#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +-#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 +- +-#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +-#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +-#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +-#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 +- +-#define SIO_SA_TX_STATUS__A 0x460017 +-#define SIO_SA_TX_STATUS__W 2 +-#define SIO_SA_TX_STATUS__M 0x3 +-#define SIO_SA_TX_STATUS__PRE 0x0 +- +-#define SIO_SA_TX_STATUS_BUSY__B 0 +-#define SIO_SA_TX_STATUS_BUSY__W 1 +-#define SIO_SA_TX_STATUS_BUSY__M 0x1 +-#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 +- +-#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +-#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +-#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +-#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 +- +-#define SIO_SA_RX_DATA0__A 0x460018 +-#define SIO_SA_RX_DATA0__W 16 +-#define SIO_SA_RX_DATA0__M 0xFFFF +-#define SIO_SA_RX_DATA0__PRE 0x0 +-#define SIO_SA_RX_DATA1__A 0x460019 +-#define SIO_SA_RX_DATA1__W 16 +-#define SIO_SA_RX_DATA1__M 0xFFFF +-#define SIO_SA_RX_DATA1__PRE 0x0 +-#define SIO_SA_RX_LENGTH__A 0x46001A +-#define SIO_SA_RX_LENGTH__W 6 +-#define SIO_SA_RX_LENGTH__M 0x3F +-#define SIO_SA_RX_LENGTH__PRE 0x0 +-#define SIO_SA_RX_COMMAND__A 0x46001B +-#define SIO_SA_RX_COMMAND__W 1 +-#define SIO_SA_RX_COMMAND__M 0x1 +-#define SIO_SA_RX_COMMAND__PRE 0x1 +- +-#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +-#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +-#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +-#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 +- +-#define SIO_SA_RX_STATUS__A 0x46001C +-#define SIO_SA_RX_STATUS__W 2 +-#define SIO_SA_RX_STATUS__M 0x3 +-#define SIO_SA_RX_STATUS__PRE 0x0 +- +-#define SIO_SA_RX_STATUS_BUSY__B 0 +-#define SIO_SA_RX_STATUS_BUSY__W 1 +-#define SIO_SA_RX_STATUS_BUSY__M 0x1 +-#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 +- +-#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +-#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +-#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +-#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 +- +- +- +-#define SIO_OFDM_SH_COMM_EXEC__A 0x470000 +-#define SIO_OFDM_SH_COMM_EXEC__W 2 +-#define SIO_OFDM_SH_COMM_EXEC__M 0x3 +-#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0 +-#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0 +-#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1 +-#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2 +- +-#define SIO_OFDM_SH_COMM_MB__A 0x470002 +-#define SIO_OFDM_SH_COMM_MB__W 2 +-#define SIO_OFDM_SH_COMM_MB__M 0x3 +-#define SIO_OFDM_SH_COMM_MB__PRE 0x0 +-#define SIO_OFDM_SH_COMM_MB_CTL__B 0 +-#define SIO_OFDM_SH_COMM_MB_CTL__W 1 +-#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1 +-#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0 +-#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0 +-#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1 +-#define SIO_OFDM_SH_COMM_MB_OBS__B 1 +-#define SIO_OFDM_SH_COMM_MB_OBS__W 1 +-#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2 +-#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0 +-#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0 +-#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2 +- +-#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +-#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1 +-#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1 +-#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0 +-#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +-#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 +- +-#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0 +- +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1 +- +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0 +-#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2 +- +-#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 +-#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1 +-#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1 +-#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0 +-#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 +-#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 +- +-#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013 +-#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3 +-#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7 +-#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6 +-#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0 +-#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3 +-#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7 +-#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6 +- +- +- +-#define SIO_BL_COMM_EXEC__A 0x480000 +-#define SIO_BL_COMM_EXEC__W 2 +-#define SIO_BL_COMM_EXEC__M 0x3 +-#define SIO_BL_COMM_EXEC__PRE 0x0 +-#define SIO_BL_COMM_EXEC_STOP 0x0 +-#define SIO_BL_COMM_EXEC_ACTIVE 0x1 +-#define SIO_BL_COMM_EXEC_HOLD 0x2 +- +-#define SIO_BL_COMM_INT_REQ__A 0x480003 +-#define SIO_BL_COMM_INT_REQ__W 1 +-#define SIO_BL_COMM_INT_REQ__M 0x1 +-#define SIO_BL_COMM_INT_REQ__PRE 0x0 +-#define SIO_BL_COMM_INT_STA__A 0x480005 +-#define SIO_BL_COMM_INT_STA__W 1 +-#define SIO_BL_COMM_INT_STA__M 0x1 +-#define SIO_BL_COMM_INT_STA__PRE 0x0 +- +-#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0 +-#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1 +-#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1 +-#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0 +- +-#define SIO_BL_COMM_INT_MSK__A 0x480006 +-#define SIO_BL_COMM_INT_MSK__W 1 +-#define SIO_BL_COMM_INT_MSK__M 0x1 +-#define SIO_BL_COMM_INT_MSK__PRE 0x0 +- +-#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0 +-#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1 +-#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1 +-#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0 +- +-#define SIO_BL_COMM_INT_STM__A 0x480007 +-#define SIO_BL_COMM_INT_STM__W 1 +-#define SIO_BL_COMM_INT_STM__M 0x1 +-#define SIO_BL_COMM_INT_STM__PRE 0x0 +- +-#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0 +-#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1 +-#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1 +-#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0 +- +-#define SIO_BL_STATUS__A 0x480010 +-#define SIO_BL_STATUS__W 1 +-#define SIO_BL_STATUS__M 0x1 +-#define SIO_BL_STATUS__PRE 0x0 +-#define SIO_BL_MODE__A 0x480011 +-#define SIO_BL_MODE__W 1 +-#define SIO_BL_MODE__M 0x1 +-#define SIO_BL_MODE__PRE 0x1 +-#define SIO_BL_MODE_DIRECT 0x0 +-#define SIO_BL_MODE_CHAIN 0x1 +- +-#define SIO_BL_ENABLE__A 0x480012 +-#define SIO_BL_ENABLE__W 1 +-#define SIO_BL_ENABLE__M 0x1 +-#define SIO_BL_ENABLE__PRE 0x0 +-#define SIO_BL_ENABLE_OFF 0x0 +-#define SIO_BL_ENABLE_ON 0x1 +- +-#define SIO_BL_TGT_HDR__A 0x480014 +-#define SIO_BL_TGT_HDR__W 12 +-#define SIO_BL_TGT_HDR__M 0xFFF +-#define SIO_BL_TGT_HDR__PRE 0x0 +-#define SIO_BL_TGT_HDR_BANK__B 0 +-#define SIO_BL_TGT_HDR_BANK__W 6 +-#define SIO_BL_TGT_HDR_BANK__M 0x3F +-#define SIO_BL_TGT_HDR_BANK__PRE 0x0 +-#define SIO_BL_TGT_HDR_BLOCK__B 6 +-#define SIO_BL_TGT_HDR_BLOCK__W 6 +-#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0 +-#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0 +- +-#define SIO_BL_TGT_ADDR__A 0x480015 +-#define SIO_BL_TGT_ADDR__W 16 +-#define SIO_BL_TGT_ADDR__M 0xFFFF +-#define SIO_BL_TGT_ADDR__PRE 0x0 +-#define SIO_BL_SRC_ADDR__A 0x480016 +-#define SIO_BL_SRC_ADDR__W 16 +-#define SIO_BL_SRC_ADDR__M 0xFFFF +-#define SIO_BL_SRC_ADDR__PRE 0x0 +-#define SIO_BL_SRC_LEN__A 0x480017 +-#define SIO_BL_SRC_LEN__W 16 +-#define SIO_BL_SRC_LEN__M 0xFFFF +-#define SIO_BL_SRC_LEN__PRE 0x0 +- +-#define SIO_BL_CHAIN_ADDR__A 0x480018 +-#define SIO_BL_CHAIN_ADDR__W 16 +-#define SIO_BL_CHAIN_ADDR__M 0xFFFF +-#define SIO_BL_CHAIN_ADDR__PRE 0x0 +- +-#define SIO_BL_CHAIN_LEN__A 0x480019 +-#define SIO_BL_CHAIN_LEN__W 4 +-#define SIO_BL_CHAIN_LEN__M 0xF +-#define SIO_BL_CHAIN_LEN__PRE 0x2 +- +- +- +-#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000 +- +- +- +-#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000 +- +- +- +-#define SIO_BL_ROM__A 0x4E0000 +- +- +- +-#define SIO_PDR_COMM_EXEC__A 0x7F0000 +-#define SIO_PDR_COMM_EXEC__W 2 +-#define SIO_PDR_COMM_EXEC__M 0x3 +-#define SIO_PDR_COMM_EXEC__PRE 0x0 +-#define SIO_PDR_COMM_EXEC_STOP 0x0 +-#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +-#define SIO_PDR_COMM_EXEC_HOLD 0x2 +- +-#define SIO_PDR_MON_CFG__A 0x7F0010 +-#define SIO_PDR_MON_CFG__W 4 +-#define SIO_PDR_MON_CFG__M 0xF +-#define SIO_PDR_MON_CFG__PRE 0x0 +- +-#define SIO_PDR_MON_CFG_OSEL__B 0 +-#define SIO_PDR_MON_CFG_OSEL__W 1 +-#define SIO_PDR_MON_CFG_OSEL__M 0x1 +-#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 +- +-#define SIO_PDR_MON_CFG_IACT__B 1 +-#define SIO_PDR_MON_CFG_IACT__W 1 +-#define SIO_PDR_MON_CFG_IACT__M 0x2 +-#define SIO_PDR_MON_CFG_IACT__PRE 0x0 +- +-#define SIO_PDR_MON_CFG_ISEL__B 2 +-#define SIO_PDR_MON_CFG_ISEL__W 1 +-#define SIO_PDR_MON_CFG_ISEL__M 0x4 +-#define SIO_PDR_MON_CFG_ISEL__PRE 0x0 +- +-#define SIO_PDR_MON_CFG_INV_CLK__B 3 +-#define SIO_PDR_MON_CFG_INV_CLK__W 1 +-#define SIO_PDR_MON_CFG_INV_CLK__M 0x8 +-#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0 +- +-#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +-#define SIO_PDR_SMA_RX_SEL__W 4 +-#define SIO_PDR_SMA_RX_SEL__M 0xF +-#define SIO_PDR_SMA_RX_SEL__PRE 0x0 +- +-#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +-#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +-#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +-#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 +- +-#define SIO_PDR_SILENT__A 0x7F0013 +-#define SIO_PDR_SILENT__W 13 +-#define SIO_PDR_SILENT__M 0x1FFF +-#define SIO_PDR_SILENT__PRE 0x0 +- +-#define SIO_PDR_SILENT_I2S_WS__B 0 +-#define SIO_PDR_SILENT_I2S_WS__W 1 +-#define SIO_PDR_SILENT_I2S_WS__M 0x1 +-#define SIO_PDR_SILENT_I2S_WS__PRE 0x0 +- +-#define SIO_PDR_SILENT_I2S_DA__B 1 +-#define SIO_PDR_SILENT_I2S_DA__W 1 +-#define SIO_PDR_SILENT_I2S_DA__M 0x2 +-#define SIO_PDR_SILENT_I2S_DA__PRE 0x0 +- +-#define SIO_PDR_SILENT_I2S_CL__B 2 +-#define SIO_PDR_SILENT_I2S_CL__W 1 +-#define SIO_PDR_SILENT_I2S_CL__M 0x4 +-#define SIO_PDR_SILENT_I2S_CL__PRE 0x0 +- +-#define SIO_PDR_SILENT_I2C_SCL2__B 3 +-#define SIO_PDR_SILENT_I2C_SCL2__W 1 +-#define SIO_PDR_SILENT_I2C_SCL2__M 0x8 +-#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0 +- +-#define SIO_PDR_SILENT_I2C_SDA2__B 4 +-#define SIO_PDR_SILENT_I2C_SDA2__W 1 +-#define SIO_PDR_SILENT_I2C_SDA2__M 0x10 +-#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0 +- +-#define SIO_PDR_SILENT_SMA_TX__B 8 +-#define SIO_PDR_SILENT_SMA_TX__W 1 +-#define SIO_PDR_SILENT_SMA_TX__M 0x100 +-#define SIO_PDR_SILENT_SMA_TX__PRE 0x0 +- +-#define SIO_PDR_SILENT_SMA_RX__B 9 +-#define SIO_PDR_SILENT_SMA_RX__W 1 +-#define SIO_PDR_SILENT_SMA_RX__M 0x200 +-#define SIO_PDR_SILENT_SMA_RX__PRE 0x0 +- +-#define SIO_PDR_SILENT_GPIO__B 10 +-#define SIO_PDR_SILENT_GPIO__W 1 +-#define SIO_PDR_SILENT_GPIO__M 0x400 +-#define SIO_PDR_SILENT_GPIO__PRE 0x0 +- +-#define SIO_PDR_SILENT_VSYNC__B 11 +-#define SIO_PDR_SILENT_VSYNC__W 1 +-#define SIO_PDR_SILENT_VSYNC__M 0x800 +-#define SIO_PDR_SILENT_VSYNC__PRE 0x0 +- +-#define SIO_PDR_SILENT_IRQN__B 12 +-#define SIO_PDR_SILENT_IRQN__W 1 +-#define SIO_PDR_SILENT_IRQN__M 0x1000 +-#define SIO_PDR_SILENT_IRQN__PRE 0x0 +- +-#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +-#define SIO_PDR_UIO_IN_LO__W 16 +-#define SIO_PDR_UIO_IN_LO__M 0xFFFF +-#define SIO_PDR_UIO_IN_LO__PRE 0x0 +-#define SIO_PDR_UIO_IN_LO_DATA__B 0 +-#define SIO_PDR_UIO_IN_LO_DATA__W 16 +-#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +-#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 +- +-#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +-#define SIO_PDR_UIO_IN_HI__W 14 +-#define SIO_PDR_UIO_IN_HI__M 0x3FFF +-#define SIO_PDR_UIO_IN_HI__PRE 0x0 +-#define SIO_PDR_UIO_IN_HI_DATA__B 0 +-#define SIO_PDR_UIO_IN_HI_DATA__W 14 +-#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +-#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 +- +-#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +-#define SIO_PDR_UIO_OUT_LO__W 16 +-#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +-#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +-#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +-#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +-#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +-#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 +- +-#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +-#define SIO_PDR_UIO_OUT_HI__W 14 +-#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +-#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +-#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +-#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +-#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +-#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 +- +-#define SIO_PDR_PWM1_MODE__A 0x7F0018 +-#define SIO_PDR_PWM1_MODE__W 2 +-#define SIO_PDR_PWM1_MODE__M 0x3 +-#define SIO_PDR_PWM1_MODE__PRE 0x0 +-#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +-#define SIO_PDR_PWM1_PRESCALE__W 6 +-#define SIO_PDR_PWM1_PRESCALE__M 0x3F +-#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +-#define SIO_PDR_PWM1_VALUE__A 0x7F001A +-#define SIO_PDR_PWM1_VALUE__W 11 +-#define SIO_PDR_PWM1_VALUE__M 0x7FF +-#define SIO_PDR_PWM1_VALUE__PRE 0x0 +- +-#define SIO_PDR_IRQN_SEL__A 0x7F001B +-#define SIO_PDR_IRQN_SEL__W 4 +-#define SIO_PDR_IRQN_SEL__M 0xF +-#define SIO_PDR_IRQN_SEL__PRE 0x3 +-#define SIO_PDR_PWM2_MODE__A 0x7F001C +-#define SIO_PDR_PWM2_MODE__W 2 +-#define SIO_PDR_PWM2_MODE__M 0x3 +-#define SIO_PDR_PWM2_MODE__PRE 0x0 +-#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +-#define SIO_PDR_PWM2_PRESCALE__W 6 +-#define SIO_PDR_PWM2_PRESCALE__M 0x3F +-#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +-#define SIO_PDR_PWM2_VALUE__A 0x7F001E +-#define SIO_PDR_PWM2_VALUE__W 11 +-#define SIO_PDR_PWM2_VALUE__M 0x7FF +-#define SIO_PDR_PWM2_VALUE__PRE 0x0 +-#define SIO_PDR_OHW_CFG__A 0x7F001F +-#define SIO_PDR_OHW_CFG__W 7 +-#define SIO_PDR_OHW_CFG__M 0x7F +-#define SIO_PDR_OHW_CFG__PRE 0x0 +- +-#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +-#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +-#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +-#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 +- +-#define SIO_PDR_OHW_CFG_BYPASS__B 2 +-#define SIO_PDR_OHW_CFG_BYPASS__W 1 +-#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +-#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 +- +-#define SIO_PDR_OHW_CFG_ASEL__B 3 +-#define SIO_PDR_OHW_CFG_ASEL__W 3 +-#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +-#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 +- +-#define SIO_PDR_OHW_CFG_SPEED__B 6 +-#define SIO_PDR_OHW_CFG_SPEED__W 1 +-#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +-#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 +- +-#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +-#define SIO_PDR_I2S_WS_CFG__W 9 +-#define SIO_PDR_I2S_WS_CFG__M 0x1FF +-#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +-#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +-#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +-#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +-#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +-#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +-#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +-#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +-#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +-#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +-#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +-#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +-#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +-#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +-#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_GPIO_CFG__A 0x7F0021 +-#define SIO_PDR_GPIO_CFG__W 9 +-#define SIO_PDR_GPIO_CFG__M 0x1FF +-#define SIO_PDR_GPIO_CFG__PRE 0x10 +-#define SIO_PDR_GPIO_CFG_MODE__B 0 +-#define SIO_PDR_GPIO_CFG_MODE__W 3 +-#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +-#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +-#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +-#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +-#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +-#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_GPIO_CFG_KEEP__B 6 +-#define SIO_PDR_GPIO_CFG_KEEP__W 2 +-#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +-#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_GPIO_CFG_UIO__B 8 +-#define SIO_PDR_GPIO_CFG_UIO__W 1 +-#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +-#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +-#define SIO_PDR_MSTRT_CFG__W 9 +-#define SIO_PDR_MSTRT_CFG__M 0x1FF +-#define SIO_PDR_MSTRT_CFG__PRE 0x50 +-#define SIO_PDR_MSTRT_CFG_MODE__B 0 +-#define SIO_PDR_MSTRT_CFG_MODE__W 3 +-#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +-#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +-#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +-#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +-#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +-#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MSTRT_CFG_UIO__B 8 +-#define SIO_PDR_MSTRT_CFG_UIO__W 1 +-#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +-#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MERR_CFG__A 0x7F0026 +-#define SIO_PDR_MERR_CFG__W 9 +-#define SIO_PDR_MERR_CFG__M 0x1FF +-#define SIO_PDR_MERR_CFG__PRE 0x50 +-#define SIO_PDR_MERR_CFG_MODE__B 0 +-#define SIO_PDR_MERR_CFG_MODE__W 3 +-#define SIO_PDR_MERR_CFG_MODE__M 0x7 +-#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MERR_CFG_DRIVE__B 3 +-#define SIO_PDR_MERR_CFG_DRIVE__W 3 +-#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MERR_CFG_KEEP__B 6 +-#define SIO_PDR_MERR_CFG_KEEP__W 2 +-#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MERR_CFG_UIO__B 8 +-#define SIO_PDR_MERR_CFG_UIO__W 1 +-#define SIO_PDR_MERR_CFG_UIO__M 0x100 +-#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MCLK_CFG__A 0x7F0028 +-#define SIO_PDR_MCLK_CFG__W 9 +-#define SIO_PDR_MCLK_CFG__M 0x1FF +-#define SIO_PDR_MCLK_CFG__PRE 0x50 +-#define SIO_PDR_MCLK_CFG_MODE__B 0 +-#define SIO_PDR_MCLK_CFG_MODE__W 3 +-#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +-#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +-#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +-#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MCLK_CFG_KEEP__B 6 +-#define SIO_PDR_MCLK_CFG_KEEP__W 2 +-#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MCLK_CFG_UIO__B 8 +-#define SIO_PDR_MCLK_CFG_UIO__W 1 +-#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +-#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MVAL_CFG__A 0x7F0029 +-#define SIO_PDR_MVAL_CFG__W 9 +-#define SIO_PDR_MVAL_CFG__M 0x1FF +-#define SIO_PDR_MVAL_CFG__PRE 0x50 +-#define SIO_PDR_MVAL_CFG_MODE__B 0 +-#define SIO_PDR_MVAL_CFG_MODE__W 3 +-#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +-#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +-#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +-#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MVAL_CFG_KEEP__B 6 +-#define SIO_PDR_MVAL_CFG_KEEP__W 2 +-#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MVAL_CFG_UIO__B 8 +-#define SIO_PDR_MVAL_CFG_UIO__W 1 +-#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +-#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD0_CFG__A 0x7F002A +-#define SIO_PDR_MD0_CFG__W 9 +-#define SIO_PDR_MD0_CFG__M 0x1FF +-#define SIO_PDR_MD0_CFG__PRE 0x50 +-#define SIO_PDR_MD0_CFG_MODE__B 0 +-#define SIO_PDR_MD0_CFG_MODE__W 3 +-#define SIO_PDR_MD0_CFG_MODE__M 0x7 +-#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD0_CFG_DRIVE__B 3 +-#define SIO_PDR_MD0_CFG_DRIVE__W 3 +-#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD0_CFG_KEEP__B 6 +-#define SIO_PDR_MD0_CFG_KEEP__W 2 +-#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD0_CFG_UIO__B 8 +-#define SIO_PDR_MD0_CFG_UIO__W 1 +-#define SIO_PDR_MD0_CFG_UIO__M 0x100 +-#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD1_CFG__A 0x7F002B +-#define SIO_PDR_MD1_CFG__W 9 +-#define SIO_PDR_MD1_CFG__M 0x1FF +-#define SIO_PDR_MD1_CFG__PRE 0x50 +-#define SIO_PDR_MD1_CFG_MODE__B 0 +-#define SIO_PDR_MD1_CFG_MODE__W 3 +-#define SIO_PDR_MD1_CFG_MODE__M 0x7 +-#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD1_CFG_DRIVE__B 3 +-#define SIO_PDR_MD1_CFG_DRIVE__W 3 +-#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD1_CFG_KEEP__B 6 +-#define SIO_PDR_MD1_CFG_KEEP__W 2 +-#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD1_CFG_UIO__B 8 +-#define SIO_PDR_MD1_CFG_UIO__W 1 +-#define SIO_PDR_MD1_CFG_UIO__M 0x100 +-#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD2_CFG__A 0x7F002C +-#define SIO_PDR_MD2_CFG__W 9 +-#define SIO_PDR_MD2_CFG__M 0x1FF +-#define SIO_PDR_MD2_CFG__PRE 0x50 +-#define SIO_PDR_MD2_CFG_MODE__B 0 +-#define SIO_PDR_MD2_CFG_MODE__W 3 +-#define SIO_PDR_MD2_CFG_MODE__M 0x7 +-#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD2_CFG_DRIVE__B 3 +-#define SIO_PDR_MD2_CFG_DRIVE__W 3 +-#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD2_CFG_KEEP__B 6 +-#define SIO_PDR_MD2_CFG_KEEP__W 2 +-#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD2_CFG_UIO__B 8 +-#define SIO_PDR_MD2_CFG_UIO__W 1 +-#define SIO_PDR_MD2_CFG_UIO__M 0x100 +-#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD3_CFG__A 0x7F002D +-#define SIO_PDR_MD3_CFG__W 9 +-#define SIO_PDR_MD3_CFG__M 0x1FF +-#define SIO_PDR_MD3_CFG__PRE 0x50 +-#define SIO_PDR_MD3_CFG_MODE__B 0 +-#define SIO_PDR_MD3_CFG_MODE__W 3 +-#define SIO_PDR_MD3_CFG_MODE__M 0x7 +-#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD3_CFG_DRIVE__B 3 +-#define SIO_PDR_MD3_CFG_DRIVE__W 3 +-#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD3_CFG_KEEP__B 6 +-#define SIO_PDR_MD3_CFG_KEEP__W 2 +-#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD3_CFG_UIO__B 8 +-#define SIO_PDR_MD3_CFG_UIO__W 1 +-#define SIO_PDR_MD3_CFG_UIO__M 0x100 +-#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD4_CFG__A 0x7F002F +-#define SIO_PDR_MD4_CFG__W 9 +-#define SIO_PDR_MD4_CFG__M 0x1FF +-#define SIO_PDR_MD4_CFG__PRE 0x50 +-#define SIO_PDR_MD4_CFG_MODE__B 0 +-#define SIO_PDR_MD4_CFG_MODE__W 3 +-#define SIO_PDR_MD4_CFG_MODE__M 0x7 +-#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD4_CFG_DRIVE__B 3 +-#define SIO_PDR_MD4_CFG_DRIVE__W 3 +-#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD4_CFG_KEEP__B 6 +-#define SIO_PDR_MD4_CFG_KEEP__W 2 +-#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD4_CFG_UIO__B 8 +-#define SIO_PDR_MD4_CFG_UIO__W 1 +-#define SIO_PDR_MD4_CFG_UIO__M 0x100 +-#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD5_CFG__A 0x7F0030 +-#define SIO_PDR_MD5_CFG__W 9 +-#define SIO_PDR_MD5_CFG__M 0x1FF +-#define SIO_PDR_MD5_CFG__PRE 0x50 +-#define SIO_PDR_MD5_CFG_MODE__B 0 +-#define SIO_PDR_MD5_CFG_MODE__W 3 +-#define SIO_PDR_MD5_CFG_MODE__M 0x7 +-#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD5_CFG_DRIVE__B 3 +-#define SIO_PDR_MD5_CFG_DRIVE__W 3 +-#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD5_CFG_KEEP__B 6 +-#define SIO_PDR_MD5_CFG_KEEP__W 2 +-#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD5_CFG_UIO__B 8 +-#define SIO_PDR_MD5_CFG_UIO__W 1 +-#define SIO_PDR_MD5_CFG_UIO__M 0x100 +-#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD6_CFG__A 0x7F0031 +-#define SIO_PDR_MD6_CFG__W 9 +-#define SIO_PDR_MD6_CFG__M 0x1FF +-#define SIO_PDR_MD6_CFG__PRE 0x50 +-#define SIO_PDR_MD6_CFG_MODE__B 0 +-#define SIO_PDR_MD6_CFG_MODE__W 3 +-#define SIO_PDR_MD6_CFG_MODE__M 0x7 +-#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD6_CFG_DRIVE__B 3 +-#define SIO_PDR_MD6_CFG_DRIVE__W 3 +-#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD6_CFG_KEEP__B 6 +-#define SIO_PDR_MD6_CFG_KEEP__W 2 +-#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD6_CFG_UIO__B 8 +-#define SIO_PDR_MD6_CFG_UIO__W 1 +-#define SIO_PDR_MD6_CFG_UIO__M 0x100 +-#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_MD7_CFG__A 0x7F0032 +-#define SIO_PDR_MD7_CFG__W 9 +-#define SIO_PDR_MD7_CFG__M 0x1FF +-#define SIO_PDR_MD7_CFG__PRE 0x50 +-#define SIO_PDR_MD7_CFG_MODE__B 0 +-#define SIO_PDR_MD7_CFG_MODE__W 3 +-#define SIO_PDR_MD7_CFG_MODE__M 0x7 +-#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +-#define SIO_PDR_MD7_CFG_DRIVE__B 3 +-#define SIO_PDR_MD7_CFG_DRIVE__W 3 +-#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +-#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_MD7_CFG_KEEP__B 6 +-#define SIO_PDR_MD7_CFG_KEEP__W 2 +-#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +-#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +-#define SIO_PDR_MD7_CFG_UIO__B 8 +-#define SIO_PDR_MD7_CFG_UIO__W 1 +-#define SIO_PDR_MD7_CFG_UIO__M 0x100 +-#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +-#define SIO_PDR_I2C_SCL1_CFG__W 9 +-#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +-#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +-#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +-#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +-#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +-#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +-#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +-#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +-#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +-#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +-#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +-#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +-#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +-#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +-#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +-#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +-#define SIO_PDR_I2C_SDA1_CFG__W 9 +-#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +-#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +-#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +-#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +-#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +-#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +-#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +-#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +-#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +-#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +-#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +-#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +-#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +-#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +-#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +-#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +-#define SIO_PDR_VSYNC_CFG__W 9 +-#define SIO_PDR_VSYNC_CFG__M 0x1FF +-#define SIO_PDR_VSYNC_CFG__PRE 0x10 +-#define SIO_PDR_VSYNC_CFG_MODE__B 0 +-#define SIO_PDR_VSYNC_CFG_MODE__W 3 +-#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +-#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +-#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +-#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +-#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +-#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +-#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +-#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +-#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_VSYNC_CFG_UIO__B 8 +-#define SIO_PDR_VSYNC_CFG_UIO__W 1 +-#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +-#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +-#define SIO_PDR_SMA_RX_CFG__W 9 +-#define SIO_PDR_SMA_RX_CFG__M 0x1FF +-#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +-#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +-#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +-#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +-#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +-#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +-#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +-#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +-#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +-#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +-#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +-#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +-#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +-#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +-#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +-#define SIO_PDR_SMA_TX_CFG__W 9 +-#define SIO_PDR_SMA_TX_CFG__M 0x1FF +-#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +-#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +-#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +-#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +-#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +-#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +-#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +-#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +-#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +-#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +-#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +-#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +-#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +-#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +-#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +-#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +-#define SIO_PDR_I2C_SDA2_CFG__W 9 +-#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +-#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +-#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +-#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +-#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +-#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +-#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +-#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +-#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +-#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +-#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +-#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +-#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +-#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +-#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +-#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +-#define SIO_PDR_I2C_SCL2_CFG__W 9 +-#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +-#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +-#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +-#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +-#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +-#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +-#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +-#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +-#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +-#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +-#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +-#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +-#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +-#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +-#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +-#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +-#define SIO_PDR_I2S_CL_CFG__W 9 +-#define SIO_PDR_I2S_CL_CFG__M 0x1FF +-#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +-#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +-#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +-#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +-#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +-#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +-#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +-#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +-#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +-#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +-#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +-#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +-#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +-#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +-#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +-#define SIO_PDR_I2S_DA_CFG__W 9 +-#define SIO_PDR_I2S_DA_CFG__M 0x1FF +-#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +-#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +-#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +-#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +-#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +-#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +-#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +-#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +-#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +-#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +-#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +-#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +-#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +-#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +-#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +-#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +-#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 +- +-#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +-#define SIO_PDR_GPIO_GPIO_FNC__W 2 +-#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +-#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +-#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +-#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +-#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +-#define SIO_PDR_MERR_GPIO_FNC__W 2 +-#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +-#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +-#define SIO_PDR_MCLK_GPIO_FNC__W 2 +-#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +-#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +-#define SIO_PDR_MVAL_GPIO_FNC__W 2 +-#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +-#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +-#define SIO_PDR_MD0_GPIO_FNC__W 2 +-#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +-#define SIO_PDR_MD1_GPIO_FNC__W 2 +-#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +-#define SIO_PDR_MD2_GPIO_FNC__W 2 +-#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +-#define SIO_PDR_MD3_GPIO_FNC__W 2 +-#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +-#define SIO_PDR_MD4_GPIO_FNC__W 2 +-#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +-#define SIO_PDR_MD5_GPIO_FNC__W 2 +-#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +-#define SIO_PDR_MD6_GPIO_FNC__W 2 +-#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +-#define SIO_PDR_MD7_GPIO_FNC__W 2 +-#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +-#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +-#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +-#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +-#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 +- +-#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +-#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +-#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +-#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +-#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +-#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +-#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +-#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 +- +-#endif +- +- ++#define AUD_COMM_EXEC__A 0x1000000 ++#define AUD_COMM_EXEC_STOP 0x0 ++#define FEC_COMM_EXEC__A 0x1C00000 ++#define FEC_COMM_EXEC_STOP 0x0 ++#define FEC_COMM_EXEC_ACTIVE 0x1 ++#define FEC_DI_COMM_EXEC__A 0x1C20000 ++#define FEC_DI_COMM_EXEC_STOP 0x0 ++#define FEC_DI_INPUT_CTL__A 0x1C20016 ++#define FEC_RS_COMM_EXEC__A 0x1C30000 ++#define FEC_RS_COMM_EXEC_STOP 0x0 ++#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 ++#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 ++#define FEC_OC_MODE__A 0x1C40011 ++#define FEC_OC_MODE_PARITY__M 0x1 ++#define FEC_OC_DTO_MODE__A 0x1C40014 ++#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 ++#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 ++#define FEC_OC_DTO_PERIOD__A 0x1C40015 ++#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 ++#define FEC_OC_FCT_MODE__A 0x1C4001A ++#define FEC_OC_FCT_MODE__PRE 0x0 ++#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 ++#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 ++#define FEC_OC_TMD_MODE__A 0x1C4001E ++#define FEC_OC_TMD_COUNT__A 0x1C4001F ++#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 ++#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 ++#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 ++#define FEC_OC_AVR_PARM_A__A 0x1C40026 ++#define FEC_OC_AVR_PARM_B__A 0x1C40027 ++#define FEC_OC_RCN_GAIN__A 0x1C4002E ++#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 ++#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 ++#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 ++#define FEC_OC_SNC_MODE__A 0x1C40040 ++#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 ++#define FEC_OC_SNC_LWM__A 0x1C40041 ++#define FEC_OC_SNC_HWM__A 0x1C40042 ++#define FEC_OC_SNC_UNLOCK__A 0x1C40043 ++#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 ++#define FEC_OC_IPR_MODE__A 0x1C40048 ++#define FEC_OC_IPR_MODE_SERIAL__M 0x1 ++#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 ++#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 ++#define FEC_OC_IPR_INVERT__A 0x1C40049 ++#define FEC_OC_IPR_INVERT_MD0__M 0x1 ++#define FEC_OC_IPR_INVERT_MD1__M 0x2 ++#define FEC_OC_IPR_INVERT_MD2__M 0x4 ++#define FEC_OC_IPR_INVERT_MD3__M 0x8 ++#define FEC_OC_IPR_INVERT_MD4__M 0x10 ++#define FEC_OC_IPR_INVERT_MD5__M 0x20 ++#define FEC_OC_IPR_INVERT_MD6__M 0x40 ++#define FEC_OC_IPR_INVERT_MD7__M 0x80 ++#define FEC_OC_IPR_INVERT_MERR__M 0x100 ++#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 ++#define FEC_OC_IPR_INVERT_MVAL__M 0x400 ++#define FEC_OC_IPR_INVERT_MCLK__M 0x800 ++#define FEC_OC_OCR_INVERT__A 0x1C40052 ++#define IQM_COMM_EXEC__A 0x1800000 ++#define IQM_COMM_EXEC_B_STOP 0x0 ++#define IQM_COMM_EXEC_B_ACTIVE 0x1 ++#define IQM_FS_RATE_OFS_LO__A 0x1820010 ++#define IQM_FS_ADJ_SEL__A 0x1820014 ++#define IQM_FS_ADJ_SEL_B_OFF 0x0 ++#define IQM_FS_ADJ_SEL_B_QAM 0x1 ++#define IQM_FS_ADJ_SEL_B_VSB 0x2 ++#define IQM_FD_RATESEL__A 0x1830010 ++#define IQM_RC_RATE_OFS_LO__A 0x1840010 ++#define IQM_RC_RATE_OFS_LO__W 16 ++#define IQM_RC_RATE_OFS_LO__M 0xFFFF ++#define IQM_RC_RATE_OFS_HI__M 0xFF ++#define IQM_RC_ADJ_SEL__A 0x1840014 ++#define IQM_RC_ADJ_SEL_B_OFF 0x0 ++#define IQM_RC_ADJ_SEL_B_QAM 0x1 ++#define IQM_RC_ADJ_SEL_B_VSB 0x2 ++#define IQM_RC_STRETCH__A 0x1840016 ++#define IQM_CF_COMM_INT_MSK__A 0x1860006 ++#define IQM_CF_SYMMETRIC__A 0x1860010 ++#define IQM_CF_MIDTAP__A 0x1860011 ++#define IQM_CF_MIDTAP_RE__B 0 ++#define IQM_CF_MIDTAP_IM__B 1 ++#define IQM_CF_OUT_ENA__A 0x1860012 ++#define IQM_CF_OUT_ENA_QAM__B 1 ++#define IQM_CF_OUT_ENA_OFDM__M 0x4 ++#define IQM_CF_ADJ_SEL__A 0x1860013 ++#define IQM_CF_SCALE__A 0x1860014 ++#define IQM_CF_SCALE_SH__A 0x1860015 ++#define IQM_CF_SCALE_SH__PRE 0x0 ++#define IQM_CF_POW_MEAS_LEN__A 0x1860017 ++#define IQM_CF_DS_ENA__A 0x1860019 ++#define IQM_CF_TAP_RE0__A 0x1860020 ++#define IQM_CF_TAP_IM0__A 0x1860040 ++#define IQM_CF_CLP_VAL__A 0x1860060 ++#define IQM_CF_DATATH__A 0x1860061 ++#define IQM_CF_PKDTH__A 0x1860062 ++#define IQM_CF_WND_LEN__A 0x1860063 ++#define IQM_CF_DET_LCT__A 0x1860064 ++#define IQM_CF_BYPASSDET__A 0x1860067 ++#define IQM_AF_COMM_EXEC__A 0x1870000 ++#define IQM_AF_COMM_EXEC_ACTIVE 0x1 ++#define IQM_AF_CLKNEG__A 0x1870012 ++#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 ++#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 ++#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 ++#define IQM_AF_START_LOCK__A 0x187001B ++#define IQM_AF_PHASE0__A 0x187001C ++#define IQM_AF_PHASE1__A 0x187001D ++#define IQM_AF_PHASE2__A 0x187001E ++#define IQM_AF_CLP_LEN__A 0x1870023 ++#define IQM_AF_CLP_TH__A 0x1870024 ++#define IQM_AF_SNS_LEN__A 0x1870026 ++#define IQM_AF_AGC_IF__A 0x1870028 ++#define IQM_AF_AGC_RF__A 0x1870029 ++#define IQM_AF_PDREF__A 0x187002B ++#define IQM_AF_PDREF__M 0x1F ++#define IQM_AF_STDBY__A 0x187002C ++#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 ++#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 ++#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 ++#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 ++#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 ++#define IQM_AF_AMUX__A 0x187002D ++#define IQM_AF_AMUX_SIGNAL2ADC 0x1 ++#define IQM_AF_UPD_SEL__A 0x187002F ++#define IQM_AF_INC_LCT__A 0x1870034 ++#define IQM_AF_INC_BYPASS__A 0x1870036 ++#define OFDM_CP_COMM_EXEC__A 0x2800000 ++#define OFDM_CP_COMM_EXEC_STOP 0x0 ++#define OFDM_EC_SB_PRIOR__A 0x3410013 ++#define OFDM_EC_SB_PRIOR_HI 0x0 ++#define OFDM_EC_SB_PRIOR_LO 0x1 ++#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 ++#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 ++#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 ++#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 ++#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 ++#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 ++#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E ++#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F ++#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 ++#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 ++#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 ++#define OFDM_LC_COMM_EXEC__A 0x3800000 ++#define OFDM_LC_COMM_EXEC_STOP 0x0 ++#define OFDM_SC_COMM_EXEC__A 0x3C00000 ++#define OFDM_SC_COMM_EXEC_STOP 0x0 ++#define OFDM_SC_COMM_STATE__A 0x3C00001 ++#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 ++#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 ++#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 ++#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 ++#define OFDM_SC_RA_RAM_CMD_NULL 0x0 ++#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 ++#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 ++#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 ++#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 ++#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 ++#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 ++#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 ++#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 ++#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 ++#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 ++#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 ++#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 ++#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 ++#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 ++#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 ++#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 ++#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC ++#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 ++#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 ++#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 ++#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 ++#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 ++#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 ++#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 ++#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 ++#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 ++#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 ++#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 ++#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 ++#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 ++#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 ++#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 ++#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 ++#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 ++#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 ++#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 ++#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B ++#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 ++#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 ++#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 ++#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 ++#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D ++#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E ++#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F ++#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 ++#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF ++#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 ++#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 ++#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 ++#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 ++#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D ++#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 ++#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 ++#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 ++#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 ++#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 ++#define QAM_COMM_EXEC__A 0x1400000 ++#define QAM_COMM_EXEC_STOP 0x0 ++#define QAM_COMM_EXEC_ACTIVE 0x1 ++#define QAM_TOP_ANNEX_A 0x0 ++#define QAM_TOP_ANNEX_C 0x2 ++#define QAM_SL_ERR_POWER__A 0x1430017 ++#define QAM_DQ_QUAL_FUN0__A 0x1440018 ++#define QAM_DQ_QUAL_FUN1__A 0x1440019 ++#define QAM_DQ_QUAL_FUN2__A 0x144001A ++#define QAM_DQ_QUAL_FUN3__A 0x144001B ++#define QAM_DQ_QUAL_FUN4__A 0x144001C ++#define QAM_DQ_QUAL_FUN5__A 0x144001D ++#define QAM_LC_MODE__A 0x1450010 ++#define QAM_LC_QUAL_TAB0__A 0x1450018 ++#define QAM_LC_QUAL_TAB1__A 0x1450019 ++#define QAM_LC_QUAL_TAB2__A 0x145001A ++#define QAM_LC_QUAL_TAB3__A 0x145001B ++#define QAM_LC_QUAL_TAB4__A 0x145001C ++#define QAM_LC_QUAL_TAB5__A 0x145001D ++#define QAM_LC_QUAL_TAB6__A 0x145001E ++#define QAM_LC_QUAL_TAB8__A 0x145001F ++#define QAM_LC_QUAL_TAB9__A 0x1450020 ++#define QAM_LC_QUAL_TAB10__A 0x1450021 ++#define QAM_LC_QUAL_TAB12__A 0x1450022 ++#define QAM_LC_QUAL_TAB15__A 0x1450023 ++#define QAM_LC_QUAL_TAB16__A 0x1450024 ++#define QAM_LC_QUAL_TAB20__A 0x1450025 ++#define QAM_LC_QUAL_TAB25__A 0x1450026 ++#define QAM_LC_LPF_FACTORP__A 0x1450028 ++#define QAM_LC_LPF_FACTORI__A 0x1450029 ++#define QAM_LC_RATE_LIMIT__A 0x145002A ++#define QAM_LC_SYMBOL_FREQ__A 0x145002B ++#define QAM_SY_TIMEOUT__A 0x1470011 ++#define QAM_SY_TIMEOUT__PRE 0x3A98 ++#define QAM_SY_SYNC_LWM__A 0x1470012 ++#define QAM_SY_SYNC_AWM__A 0x1470013 ++#define QAM_SY_SYNC_HWM__A 0x1470014 ++#define QAM_SY_SP_INV__A 0x1470017 ++#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 ++#define SCU_COMM_EXEC__A 0x800000 ++#define SCU_COMM_EXEC_STOP 0x0 ++#define SCU_COMM_EXEC_ACTIVE 0x1 ++#define SCU_COMM_EXEC_HOLD 0x2 ++#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF ++#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 ++#define SCU_RAM_GPIO__A 0x831EC7 ++#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 ++#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 ++#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB ++#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 ++#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 ++#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 ++#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 ++#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 ++#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A ++#define SCU_RAM_AGC_RF_MAX__A 0x831F1B ++#define SCU_RAM_AGC_CONFIG__A 0x831F24 ++#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 ++#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 ++#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 ++#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 ++#define SCU_RAM_AGC_KI__A 0x831F25 ++#define SCU_RAM_AGC_KI_RF__B 4 ++#define SCU_RAM_AGC_KI_RF__M 0xF0 ++#define SCU_RAM_AGC_KI_IF__B 8 ++#define SCU_RAM_AGC_KI_IF__M 0xF00 ++#define SCU_RAM_AGC_KI_RED__A 0x831F26 ++#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 ++#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC ++#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 ++#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 ++#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 ++#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 ++#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 ++#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A ++#define SCU_RAM_AGC_KI_MIN__A 0x831F2B ++#define SCU_RAM_AGC_KI_MAX__A 0x831F2C ++#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D ++#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E ++#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F ++#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 ++#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 ++#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 ++#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 ++#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 ++#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 ++#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 ++#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 ++#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 ++#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 ++#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A ++#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B ++#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D ++#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E ++#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F ++#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 ++#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 ++#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 ++#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 ++#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 ++#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 ++#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 ++#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 ++#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 ++#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 ++#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 ++#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 ++#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 ++#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 ++#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A ++#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E ++#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F ++#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 ++#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 ++#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 ++#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 ++#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 ++#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 ++#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 ++#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 ++#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 ++#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A ++#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B ++#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C ++#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D ++#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E ++#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F ++#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 ++#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 ++#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 ++#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 ++#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 ++#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 ++#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 ++#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 ++#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 ++#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 ++#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA ++#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB ++#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC ++#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD ++#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE ++#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF ++#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 ++#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 ++#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 ++#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 ++#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 ++#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 ++#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA ++#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB ++#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC ++#define SCU_RAM_PARAM_15__A 0x831FED ++#define SCU_RAM_PARAM_0__A 0x831FFC ++#define SCU_RAM_COMMAND__A 0x831FFD ++#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 ++#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 ++#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 ++#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 ++#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 ++#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 ++#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 ++#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 ++#define SIO_TOP_COMM_KEY__A 0x41000F ++#define SIO_TOP_COMM_KEY_KEY 0xFABA ++#define SIO_TOP_JTAGID_LO__A 0x410012 ++#define SIO_HI_RA_RAM_RES__A 0x420031 ++#define SIO_HI_RA_RAM_CMD__A 0x420032 ++#define SIO_HI_RA_RAM_CMD_RESET 0x2 ++#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 ++#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 ++#define SIO_HI_RA_RAM_PAR_1__A 0x420033 ++#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 ++#define SIO_HI_RA_RAM_PAR_2__A 0x420034 ++#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F ++#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 ++#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 ++#define SIO_HI_RA_RAM_PAR_3__A 0x420035 ++#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F ++#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 ++#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 ++#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 ++#define SIO_HI_RA_RAM_PAR_4__A 0x420036 ++#define SIO_HI_RA_RAM_PAR_5__A 0x420037 ++#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 ++#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 ++#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 ++#define SIO_HI_RA_RAM_PAR_6__A 0x420038 ++#define SIO_CC_PLL_LOCK__A 0x450012 ++#define SIO_CC_PWD_MODE__A 0x450015 ++#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 ++#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 ++#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 ++#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 ++#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 ++#define SIO_CC_SOFT_RST__A 0x450016 ++#define SIO_CC_SOFT_RST_OFDM__M 0x1 ++#define SIO_CC_SOFT_RST_SYS__M 0x2 ++#define SIO_CC_SOFT_RST_OSC__M 0x4 ++#define SIO_CC_UPDATE__A 0x450017 ++#define SIO_CC_UPDATE_KEY 0xFABA ++#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 ++#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 ++#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 ++#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 ++#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 ++#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 ++#define SIO_BL_COMM_EXEC__A 0x480000 ++#define SIO_BL_COMM_EXEC_ACTIVE 0x1 ++#define SIO_BL_STATUS__A 0x480010 ++#define SIO_BL_MODE__A 0x480011 ++#define SIO_BL_MODE_DIRECT 0x0 ++#define SIO_BL_MODE_CHAIN 0x1 ++#define SIO_BL_ENABLE__A 0x480012 ++#define SIO_BL_ENABLE_ON 0x1 ++#define SIO_BL_TGT_HDR__A 0x480014 ++#define SIO_BL_TGT_ADDR__A 0x480015 ++#define SIO_BL_SRC_ADDR__A 0x480016 ++#define SIO_BL_SRC_LEN__A 0x480017 ++#define SIO_BL_CHAIN_ADDR__A 0x480018 ++#define SIO_BL_CHAIN_LEN__A 0x480019 ++#define SIO_PDR_MON_CFG__A 0x7F0010 ++#define SIO_PDR_UIO_IN_HI__A 0x7F0015 ++#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 ++#define SIO_PDR_OHW_CFG__A 0x7F001F ++#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 ++#define SIO_PDR_GPIO_CFG__A 0x7F0021 ++#define SIO_PDR_MSTRT_CFG__A 0x7F0025 ++#define SIO_PDR_MERR_CFG__A 0x7F0026 ++#define SIO_PDR_MCLK_CFG__A 0x7F0028 ++#define SIO_PDR_MCLK_CFG_DRIVE__B 3 ++#define SIO_PDR_MVAL_CFG__A 0x7F0029 ++#define SIO_PDR_MD0_CFG__A 0x7F002A ++#define SIO_PDR_MD0_CFG_DRIVE__B 3 ++#define SIO_PDR_MD1_CFG__A 0x7F002B ++#define SIO_PDR_MD2_CFG__A 0x7F002C ++#define SIO_PDR_MD3_CFG__A 0x7F002D ++#define SIO_PDR_MD4_CFG__A 0x7F002F ++#define SIO_PDR_MD5_CFG__A 0x7F0030 ++#define SIO_PDR_MD6_CFG__A 0x7F0031 ++#define SIO_PDR_MD7_CFG__A 0x7F0032 ++#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 ++#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +diff --git a/frontends/tda18271c2dd.c b/frontends/tda18271c2dd.c +index 5c098c7..ad7c72e 100644 +--- a/frontends/tda18271c2dd.c ++++ b/frontends/tda18271c2dd.c +@@ -1,1301 +1,1246 @@ +-/* +- * tda18271c2dd: Driver for the TDA18271C2 tuner +- * +- * Copyright (C) 2010 Digital Devices GmbH +- * +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License +- * version 2 only, as published by the Free Software Foundation. +- * +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +- * 02110-1301, USA +- * Or, point your browser to http://www.gnu.org/copyleft/gpl.html +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "dvb_frontend.h" +- +-struct SStandardParam { +- s32 m_IFFrequency; +- u32 m_BandWidth; +- u8 m_EP3_4_0; +- u8 m_EB22; +-}; +- +-struct SMap { +- u32 m_Frequency; +- u8 m_Param; +-}; +- +-struct SMapI { +- u32 m_Frequency; +- s32 m_Param; +-}; +- +-struct SMap2 { +- u32 m_Frequency; +- u8 m_Param1; +- u8 m_Param2; +-}; +- +-struct SRFBandMap { +- u32 m_RF_max; +- u32 m_RF1_Default; +- u32 m_RF2_Default; +- u32 m_RF3_Default; +-}; +- +-enum ERegister { +- ID = 0, +- TM, +- PL, +- EP1, EP2, EP3, EP4, EP5, +- CPD, CD1, CD2, CD3, +- MPD, MD1, MD2, MD3, +- EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10, +- EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20, +- EB21, EB22, EB23, +- NUM_REGS +-}; +- +-struct tda_state { +- struct i2c_adapter *i2c; +- u8 adr; +- +- u32 m_Frequency; +- u32 IF; +- +- u8 m_IFLevelAnalog; +- u8 m_IFLevelDigital; +- u8 m_IFLevelDVBC; +- u8 m_IFLevelDVBT; +- +- u8 m_EP4; +- u8 m_EP3_Standby; +- +- bool m_bMaster; +- +- s32 m_SettlingTime; +- +- u8 m_Regs[NUM_REGS]; +- +- /* Tracking filter settings for band 0..6 */ +- u32 m_RF1[7]; +- s32 m_RF_A1[7]; +- s32 m_RF_B1[7]; +- u32 m_RF2[7]; +- s32 m_RF_A2[7]; +- s32 m_RF_B2[7]; +- u32 m_RF3[7]; +- +- u8 m_TMValue_RFCal; /* Calibration temperatur */ +- +- bool m_bFMInput; /* true to use Pin 8 for FM Radio */ +- +-}; +- +-static int PowerScan(struct tda_state *state, +- u8 RFBand, u32 RF_in, +- u32 *pRF_Out, bool *pbcal); +- +-static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) +-{ +- struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, +- .buf = data, .len = len} }; +- return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +-} +- +-static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +-{ +- struct i2c_msg msg = {.addr = adr, .flags = 0, +- .buf = data, .len = len}; +- +- if (i2c_transfer(adap, &msg, 1) != 1) { +- printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr); +- return -1; +- } +- return 0; +-} +- +-static int WriteRegs(struct tda_state *state, +- u8 SubAddr, u8 *Regs, u16 nRegs) +-{ +- u8 data[nRegs+1]; +- +- data[0] = SubAddr; +- memcpy(data + 1, Regs, nRegs); +- return i2c_write(state->i2c, state->adr, data, nRegs+1); +-} +- +-static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) +-{ +- u8 msg[2] = {SubAddr, Reg}; +- +- return i2c_write(state->i2c, state->adr, msg, 2); +-} +- +-static int Read(struct tda_state *state, u8 * Regs) +-{ +- return i2c_readn(state->i2c, state->adr, Regs, 16); +-} +- +-static int ReadExtented(struct tda_state *state, u8 * Regs) +-{ +- return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS); +-} +- +-static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo) +-{ +- return WriteRegs(state, RegFrom, +- &state->m_Regs[RegFrom], RegTo-RegFrom+1); +-} +-static int UpdateReg(struct tda_state *state, u8 Reg) +-{ +- return WriteReg(state, Reg, state->m_Regs[Reg]); +-} +- +-#include "tda18271c2dd_maps.h" +- +-static void reset(struct tda_state *state) +-{ +- u32 ulIFLevelAnalog = 0; +- u32 ulIFLevelDigital = 2; +- u32 ulIFLevelDVBC = 7; +- u32 ulIFLevelDVBT = 6; +- u32 ulXTOut = 0; +- u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */ +- u32 ulSlave = 0; +- u32 ulFMInput = 0; +- u32 ulSettlingTime = 100; +- +- state->m_Frequency = 0; +- state->m_SettlingTime = 100; +- state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2; +- state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2; +- state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2; +- state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2; +- +- state->m_EP4 = 0x20; +- if (ulXTOut != 0) +- state->m_EP4 |= 0x40; +- +- state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F; +- state->m_bMaster = (ulSlave == 0); +- +- state->m_SettlingTime = ulSettlingTime; +- +- state->m_bFMInput = (ulFMInput == 2); +-} +- +-static bool SearchMap1(struct SMap Map[], +- u32 Frequency, u8 *pParam) +-{ +- int i = 0; +- +- while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency)) +- i += 1; +- if (Map[i].m_Frequency == 0) +- return false; +- *pParam = Map[i].m_Param; +- return true; +-} +- +-static bool SearchMap2(struct SMapI Map[], +- u32 Frequency, s32 *pParam) +-{ +- int i = 0; +- +- while ((Map[i].m_Frequency != 0) && +- (Frequency > Map[i].m_Frequency)) +- i += 1; +- if (Map[i].m_Frequency == 0) +- return false; +- *pParam = Map[i].m_Param; +- return true; +-} +- +-static bool SearchMap3(struct SMap2 Map[], u32 Frequency, +- u8 *pParam1, u8 *pParam2) +-{ +- int i = 0; +- +- while ((Map[i].m_Frequency != 0) && +- (Frequency > Map[i].m_Frequency)) +- i += 1; +- if (Map[i].m_Frequency == 0) +- return false; +- *pParam1 = Map[i].m_Param1; +- *pParam2 = Map[i].m_Param2; +- return true; +-} +- +-static bool SearchMap4(struct SRFBandMap Map[], +- u32 Frequency, u8 *pRFBand) +-{ +- int i = 0; +- +- while (i < 7 && (Frequency > Map[i].m_RF_max)) +- i += 1; +- if (i == 7) +- return false; +- *pRFBand = i; +- return true; +-} +- +-static int ThermometerRead(struct tda_state *state, u8 *pTM_Value) +-{ +- int status = 0; +- +- do { +- u8 Regs[16]; +- state->m_Regs[TM] |= 0x10; +- status = UpdateReg(state, TM); +- if (status < 0) +- break; +- status = Read(state, Regs); +- if (status < 0) +- break; +- if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) || +- ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) { +- state->m_Regs[TM] ^= 0x20; +- status = UpdateReg(state, TM); +- if (status < 0) +- break; +- msleep(10); +- status = Read(state, Regs); +- if (status < 0) +- break; +- } +- *pTM_Value = (Regs[TM] & 0x20) +- ? m_Thermometer_Map_2[Regs[TM] & 0x0F] +- : m_Thermometer_Map_1[Regs[TM] & 0x0F] ; +- state->m_Regs[TM] &= ~0x10; /* Thermometer off */ +- status = UpdateReg(state, TM); +- if (status < 0) +- break; +- state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */ +- status = UpdateReg(state, EP4); +- if (status < 0) +- break; +- } while (0); +- +- return status; +-} +- +-static int StandBy(struct tda_state *state) +-{ +- int status = 0; +- do { +- state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */ +- status = UpdateReg(state, EB12); +- if (status < 0) +- break; +- state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */ +- status = UpdateReg(state, EB18); +- if (status < 0) +- break; +- state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */ +- state->m_Regs[EP3] = state->m_EP3_Standby; +- status = UpdateReg(state, EP3); +- if (status < 0) +- break; +- state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */ +- status = UpdateRegs(state, EB21, EB23); +- if (status < 0) +- break; +- } while (0); +- return status; +-} +- +-static int CalcMainPLL(struct tda_state *state, u32 freq) +-{ +- +- u8 PostDiv; +- u8 Div; +- u64 OscFreq; +- u32 MainDiv; +- +- if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) +- return -EINVAL; +- +- OscFreq = (u64) freq * (u64) Div; +- OscFreq *= (u64) 16384; +- do_div(OscFreq, (u64)16000000); +- MainDiv = OscFreq; +- +- state->m_Regs[MPD] = PostDiv & 0x77; +- state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F); +- state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF); +- state->m_Regs[MD3] = (MainDiv & 0xFF); +- +- return UpdateRegs(state, MPD, MD3); +-} +- +-static int CalcCalPLL(struct tda_state *state, u32 freq) +-{ +- u8 PostDiv; +- u8 Div; +- u64 OscFreq; +- u32 CalDiv; +- +- if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div)) +- return -EINVAL; +- +- OscFreq = (u64)freq * (u64)Div; +- /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */ +- OscFreq *= (u64)16384; +- do_div(OscFreq, (u64)16000000); +- CalDiv = OscFreq; +- +- state->m_Regs[CPD] = PostDiv; +- state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF); +- state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF); +- state->m_Regs[CD3] = (CalDiv & 0xFF); +- +- return UpdateRegs(state, CPD, CD3); +-} +- +-static int CalibrateRF(struct tda_state *state, +- u8 RFBand, u32 freq, s32 *pCprog) +-{ +- int status = 0; +- u8 Regs[NUM_REGS]; +- do { +- u8 BP_Filter = 0; +- u8 GainTaper = 0; +- u8 RFC_K = 0; +- u8 RFC_M = 0; +- +- state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */ +- status = UpdateReg(state, EP4); +- if (status < 0) +- break; +- state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */ +- status = UpdateReg(state, EB18); +- if (status < 0) +- break; +- +- /* Switching off LT (as datasheet says) causes calibration on C1 to fail */ +- /* (Readout of Cprog is allways 255) */ +- if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */ +- state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */ +- +- if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) && +- SearchMap1(m_GainTaper_Map, freq, &GainTaper) && +- SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M))) +- return -EINVAL; +- +- state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter; +- state->m_Regs[EP2] = (RFBand << 5) | GainTaper; +- +- state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2); +- +- status = UpdateRegs(state, EP1, EP3); +- if (status < 0) +- break; +- status = UpdateReg(state, EB13); +- if (status < 0) +- break; +- +- state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */ +- status = UpdateReg(state, EB4); +- if (status < 0) +- break; +- +- state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */ +- status = UpdateReg(state, EB7); +- if (status < 0) +- break; +- +- state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */ +- status = UpdateReg(state, EB14); +- if (status < 0) +- break; +- +- state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */ +- status = UpdateReg(state, EB20); +- if (status < 0) +- break; +- +- state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */ +- status = UpdateRegs(state, EP4, EP5); +- if (status < 0) +- break; +- +- status = CalcCalPLL(state, freq); +- if (status < 0) +- break; +- status = CalcMainPLL(state, freq + 1000000); +- if (status < 0) +- break; +- +- msleep(5); +- status = UpdateReg(state, EP2); +- if (status < 0) +- break; +- status = UpdateReg(state, EP1); +- if (status < 0) +- break; +- status = UpdateReg(state, EP2); +- if (status < 0) +- break; +- status = UpdateReg(state, EP1); +- if (status < 0) +- break; +- +- state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */ +- status = UpdateReg(state, EB4); +- if (status < 0) +- break; +- +- state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */ +- status = UpdateReg(state, EB7); +- if (status < 0) +- break; +- msleep(10); +- +- state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */ +- status = UpdateReg(state, EB20); +- if (status < 0) +- break; +- msleep(60); +- +- state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */ +- state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */ +- state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */ +- status = UpdateReg(state, EB18); +- if (status < 0) +- break; +- status = UpdateRegs(state, EP3, EP4); +- if (status < 0) +- break; +- status = UpdateReg(state, EP1); +- if (status < 0) +- break; +- +- status = ReadExtented(state, Regs); +- if (status < 0) +- break; +- +- *pCprog = Regs[EB14]; +- +- } while (0); +- return status; +-} +- +-static int RFTrackingFiltersInit(struct tda_state *state, +- u8 RFBand) +-{ +- int status = 0; +- +- u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default; +- u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default; +- u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default; +- bool bcal = false; +- +- s32 Cprog_cal1 = 0; +- s32 Cprog_table1 = 0; +- s32 Cprog_cal2 = 0; +- s32 Cprog_table2 = 0; +- s32 Cprog_cal3 = 0; +- s32 Cprog_table3 = 0; +- +- state->m_RF_A1[RFBand] = 0; +- state->m_RF_B1[RFBand] = 0; +- state->m_RF_A2[RFBand] = 0; +- state->m_RF_B2[RFBand] = 0; +- +- do { +- status = PowerScan(state, RFBand, RF1, &RF1, &bcal); +- if (status < 0) +- break; +- if (bcal) { +- status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1); +- if (status < 0) +- break; +- } +- SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1); +- if (!bcal) +- Cprog_cal1 = Cprog_table1; +- state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1; +- /* state->m_RF_A1[RF_Band] = ???? */ +- +- if (RF2 == 0) +- break; +- +- status = PowerScan(state, RFBand, RF2, &RF2, &bcal); +- if (status < 0) +- break; +- if (bcal) { +- status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2); +- if (status < 0) +- break; +- } +- SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2); +- if (!bcal) +- Cprog_cal2 = Cprog_table2; +- +- state->m_RF_A1[RFBand] = +- (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) / +- ((s32)(RF2) - (s32)(RF1)); +- +- if (RF3 == 0) +- break; +- +- status = PowerScan(state, RFBand, RF3, &RF3, &bcal); +- if (status < 0) +- break; +- if (bcal) { +- status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3); +- if (status < 0) +- break; +- } +- SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3); +- if (!bcal) +- Cprog_cal3 = Cprog_table3; +- state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2)); +- state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2; +- +- } while (0); +- +- state->m_RF1[RFBand] = RF1; +- state->m_RF2[RFBand] = RF2; +- state->m_RF3[RFBand] = RF3; +- +-#if 0 +- printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__, +- RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2, +- state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3); +-#endif +- +- return status; +-} +- +-static int PowerScan(struct tda_state *state, +- u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal) +-{ +- int status = 0; +- do { +- u8 Gain_Taper = 0; +- s32 RFC_Cprog = 0; +- u8 CID_Target = 0; +- u8 CountLimit = 0; +- u32 freq_MainPLL; +- u8 Regs[NUM_REGS]; +- u8 CID_Gain; +- s32 Count = 0; +- int sign = 1; +- bool wait = false; +- +- if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) && +- SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) && +- SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) { +- +- printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__); +- return -EINVAL; +- } +- +- state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper; +- state->m_Regs[EB14] = (RFC_Cprog); +- status = UpdateReg(state, EP2); +- if (status < 0) +- break; +- status = UpdateReg(state, EB14); +- if (status < 0) +- break; +- +- freq_MainPLL = RF_in + 1000000; +- status = CalcMainPLL(state, freq_MainPLL); +- if (status < 0) +- break; +- msleep(5); +- state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */ +- status = UpdateReg(state, EP4); +- if (status < 0) +- break; +- status = UpdateReg(state, EP2); /* Launch power measurement */ +- if (status < 0) +- break; +- status = ReadExtented(state, Regs); +- if (status < 0) +- break; +- CID_Gain = Regs[EB10] & 0x3F; +- state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */ +- +- *pRF_Out = RF_in; +- +- while (CID_Gain < CID_Target) { +- freq_MainPLL = RF_in + sign * Count + 1000000; +- status = CalcMainPLL(state, freq_MainPLL); +- if (status < 0) +- break; +- msleep(wait ? 5 : 1); +- wait = false; +- status = UpdateReg(state, EP2); /* Launch power measurement */ +- if (status < 0) +- break; +- status = ReadExtented(state, Regs); +- if (status < 0) +- break; +- CID_Gain = Regs[EB10] & 0x3F; +- Count += 200000; +- +- if (Count < CountLimit * 100000) +- continue; +- if (sign < 0) +- break; +- +- sign = -sign; +- Count = 200000; +- wait = true; +- } +- status = status; +- if (status < 0) +- break; +- if (CID_Gain >= CID_Target) { +- *pbcal = true; +- *pRF_Out = freq_MainPLL - 1000000; +- } else +- *pbcal = false; +- } while (0); +- +- return status; +-} +- +-static int PowerScanInit(struct tda_state *state) +-{ +- int status = 0; +- do { +- state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12; +- state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */ +- status = UpdateRegs(state, EP3, EP4); +- if (status < 0) +- break; +- state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */ +- status = UpdateReg(state, EB18); +- if (status < 0) +- break; +- state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */ +- state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ +- status = UpdateRegs(state, EB21, EB23); +- if (status < 0) +- break; +- } while (0); +- return status; +-} +- +-static int CalcRFFilterCurve(struct tda_state *state) +-{ +- int status = 0; +- do { +- msleep(200); /* Temperature stabilisation */ +- status = PowerScanInit(state); +- if (status < 0) +- break; +- status = RFTrackingFiltersInit(state, 0); +- if (status < 0) +- break; +- status = RFTrackingFiltersInit(state, 1); +- if (status < 0) +- break; +- status = RFTrackingFiltersInit(state, 2); +- if (status < 0) +- break; +- status = RFTrackingFiltersInit(state, 3); +- if (status < 0) +- break; +- status = RFTrackingFiltersInit(state, 4); +- if (status < 0) +- break; +- status = RFTrackingFiltersInit(state, 5); +- if (status < 0) +- break; +- status = RFTrackingFiltersInit(state, 6); +- if (status < 0) +- break; +- status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */ +- if (status < 0) +- break; +- } while (0); +- +- return status; +-} +- +-static int FixedContentsI2CUpdate(struct tda_state *state) +-{ +- static u8 InitRegs[] = { +- 0x08, 0x80, 0xC6, +- 0xDF, 0x16, 0x60, 0x80, +- 0x80, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, +- 0xFC, 0x01, 0x84, 0x41, +- 0x01, 0x84, 0x40, 0x07, +- 0x00, 0x00, 0x96, 0x3F, +- 0xC1, 0x00, 0x8F, 0x00, +- 0x00, 0x8C, 0x00, 0x20, +- 0xB3, 0x48, 0xB0, +- }; +- int status = 0; +- memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1); +- do { +- status = UpdateRegs(state, TM, EB23); +- if (status < 0) +- break; +- +- /* AGC1 gain setup */ +- state->m_Regs[EB17] = 0x00; +- status = UpdateReg(state, EB17); +- if (status < 0) +- break; +- state->m_Regs[EB17] = 0x03; +- status = UpdateReg(state, EB17); +- if (status < 0) +- break; +- state->m_Regs[EB17] = 0x43; +- status = UpdateReg(state, EB17); +- if (status < 0) +- break; +- state->m_Regs[EB17] = 0x4C; +- status = UpdateReg(state, EB17); +- if (status < 0) +- break; +- +- /* IRC Cal Low band */ +- state->m_Regs[EP3] = 0x1F; +- state->m_Regs[EP4] = 0x66; +- state->m_Regs[EP5] = 0x81; +- state->m_Regs[CPD] = 0xCC; +- state->m_Regs[CD1] = 0x6C; +- state->m_Regs[CD2] = 0x00; +- state->m_Regs[CD3] = 0x00; +- state->m_Regs[MPD] = 0xC5; +- state->m_Regs[MD1] = 0x77; +- state->m_Regs[MD2] = 0x08; +- state->m_Regs[MD3] = 0x00; +- status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */ +- if (status < 0) +- break; +- +-#if 0 +- state->m_Regs[EB4] = 0x61; /* missing in sw */ +- status = UpdateReg(state, EB4); +- if (status < 0) +- break; +- msleep(1); +- state->m_Regs[EB4] = 0x41; +- status = UpdateReg(state, EB4); +- if (status < 0) +- break; +-#endif +- +- msleep(5); +- status = UpdateReg(state, EP1); +- if (status < 0) +- break; +- msleep(5); +- +- state->m_Regs[EP5] = 0x85; +- state->m_Regs[CPD] = 0xCB; +- state->m_Regs[CD1] = 0x66; +- state->m_Regs[CD2] = 0x70; +- status = UpdateRegs(state, EP3, CD3); +- if (status < 0) +- break; +- msleep(5); +- status = UpdateReg(state, EP2); +- if (status < 0) +- break; +- msleep(30); +- +- /* IRC Cal mid band */ +- state->m_Regs[EP5] = 0x82; +- state->m_Regs[CPD] = 0xA8; +- state->m_Regs[CD2] = 0x00; +- state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */ +- state->m_Regs[MD1] = 0x73; +- state->m_Regs[MD2] = 0x1A; +- status = UpdateRegs(state, EP3, MD3); +- if (status < 0) +- break; +- +- msleep(5); +- status = UpdateReg(state, EP1); +- if (status < 0) +- break; +- msleep(5); +- +- state->m_Regs[EP5] = 0x86; +- state->m_Regs[CPD] = 0xA8; +- state->m_Regs[CD1] = 0x66; +- state->m_Regs[CD2] = 0xA0; +- status = UpdateRegs(state, EP3, CD3); +- if (status < 0) +- break; +- msleep(5); +- status = UpdateReg(state, EP2); +- if (status < 0) +- break; +- msleep(30); +- +- /* IRC Cal high band */ +- state->m_Regs[EP5] = 0x83; +- state->m_Regs[CPD] = 0x98; +- state->m_Regs[CD1] = 0x65; +- state->m_Regs[CD2] = 0x00; +- state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */ +- state->m_Regs[MD1] = 0x71; +- state->m_Regs[MD2] = 0xCD; +- status = UpdateRegs(state, EP3, MD3); +- if (status < 0) +- break; +- msleep(5); +- status = UpdateReg(state, EP1); +- if (status < 0) +- break; +- msleep(5); +- state->m_Regs[EP5] = 0x87; +- state->m_Regs[CD1] = 0x65; +- state->m_Regs[CD2] = 0x50; +- status = UpdateRegs(state, EP3, CD3); +- if (status < 0) +- break; +- msleep(5); +- status = UpdateReg(state, EP2); +- if (status < 0) +- break; +- msleep(30); +- +- /* Back to normal */ +- state->m_Regs[EP4] = 0x64; +- status = UpdateReg(state, EP4); +- if (status < 0) +- break; +- status = UpdateReg(state, EP1); +- if (status < 0) +- break; +- +- } while (0); +- return status; +-} +- +-static int InitCal(struct tda_state *state) +-{ +- int status = 0; +- +- do { +- status = FixedContentsI2CUpdate(state); +- if (status < 0) +- break; +- status = CalcRFFilterCurve(state); +- if (status < 0) +- break; +- status = StandBy(state); +- if (status < 0) +- break; +- /* m_bInitDone = true; */ +- } while (0); +- return status; +-}; +- +-static int RFTrackingFiltersCorrection(struct tda_state *state, +- u32 Frequency) +-{ +- int status = 0; +- s32 Cprog_table; +- u8 RFBand; +- u8 dCoverdT; +- +- if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) || +- !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) || +- !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT)) +- +- return -EINVAL; +- +- do { +- u8 TMValue_Current; +- u32 RF1 = state->m_RF1[RFBand]; +- u32 RF2 = state->m_RF1[RFBand]; +- u32 RF3 = state->m_RF1[RFBand]; +- s32 RF_A1 = state->m_RF_A1[RFBand]; +- s32 RF_B1 = state->m_RF_B1[RFBand]; +- s32 RF_A2 = state->m_RF_A2[RFBand]; +- s32 RF_B2 = state->m_RF_B2[RFBand]; +- s32 Capprox = 0; +- int TComp; +- +- state->m_Regs[EP3] &= ~0xE0; /* Power up */ +- status = UpdateReg(state, EP3); +- if (status < 0) +- break; +- +- status = ThermometerRead(state, &TMValue_Current); +- if (status < 0) +- break; +- +- if (RF3 == 0 || Frequency < RF2) +- Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table; +- else +- Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table; +- +- TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000; +- +- Capprox += TComp; +- +- if (Capprox < 0) +- Capprox = 0; +- else if (Capprox > 255) +- Capprox = 255; +- +- +- /* TODO Temperature compensation. There is defenitely a scale factor */ +- /* missing in the datasheet, so leave it out for now. */ +- state->m_Regs[EB14] = Capprox; +- +- status = UpdateReg(state, EB14); +- if (status < 0) +- break; +- +- } while (0); +- return status; +-} +- +-static int ChannelConfiguration(struct tda_state *state, +- u32 Frequency, int Standard) +-{ +- +- s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency; +- int status = 0; +- +- u8 BP_Filter = 0; +- u8 RF_Band = 0; +- u8 GainTaper = 0; +- u8 IR_Meas = 0; +- +- state->IF = IntermediateFrequency; +- /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ +- /* get values from tables */ +- +- if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) && +- SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) && +- SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) && +- SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) { +- +- printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__); +- return -EINVAL; +- } +- +- do { +- state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0; +- state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */ +- +- /* m_EP4 default for XToutOn, CAL_Mode (0) */ +- state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog); +- /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */ +- if (Standard <= HF_AnalogMax) +- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog; +- else if (Standard <= HF_ATSC) +- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT; +- else if (Standard <= HF_DVBC) +- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC; +- else +- state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; +- +- if ((Standard == HF_FM_Radio) && state->m_bFMInput) +- state->m_Regs[EP4] |= 80; +- +- state->m_Regs[MPD] &= ~0x80; +- if (Standard > HF_AnalogMax) +- state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */ +- +- state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22; +- +- /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */ +- if (Standard == HF_FM_Radio) +- state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ +- else +- state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */ +- +- status = UpdateRegs(state, EB22, EB23); +- if (status < 0) +- break; +- +- state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */ +- state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas; +- state->m_Regs[EP2] = (RF_Band << 5) | GainTaper; +- +- state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) | +- (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */ +- /* AGC1_always_master = 0 */ +- /* AGC_firstn = 0 */ +- status = UpdateReg(state, EB1); +- if (status < 0) +- break; +- +- if (state->m_bMaster) { +- status = CalcMainPLL(state, Frequency + IntermediateFrequency); +- if (status < 0) +- break; +- status = UpdateRegs(state, TM, EP5); +- if (status < 0) +- break; +- state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */ +- status = UpdateReg(state, EB4); +- if (status < 0) +- break; +- msleep(1); +- state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ +- status = UpdateReg(state, EB4); +- if (status < 0) +- break; +- } else { +- u8 PostDiv = 0; +- u8 Div; +- status = CalcCalPLL(state, Frequency + IntermediateFrequency); +- if (status < 0) +- break; +- +- SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div); +- state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77); +- status = UpdateReg(state, MPD); +- if (status < 0) +- break; +- status = UpdateRegs(state, TM, EP5); +- if (status < 0) +- break; +- +- state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */ +- status = UpdateReg(state, EB7); +- if (status < 0) +- break; +- msleep(1); +- state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */ +- status = UpdateReg(state, EB7); +- if (status < 0) +- break; +- } +- msleep(20); +- if (Standard != HF_FM_Radio) +- state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */ +- status = UpdateReg(state, EP3); +- if (status < 0) +- break; +- +- } while (0); +- return status; +-} +- +-static int sleep(struct dvb_frontend *fe) +-{ +- struct tda_state *state = fe->tuner_priv; +- +- StandBy(state); +- return 0; +-} +- +-static int init(struct dvb_frontend *fe) +-{ +- return 0; +-} +- +-static int release(struct dvb_frontend *fe) +-{ +- kfree(fe->tuner_priv); +- fe->tuner_priv = NULL; +- return 0; +-} +- +-/* +- * As defined on EN 300 429 Annex A and on ITU-T J.83 annex A, the DVB-C +- * roll-off factor is 0.15. +- * According with the specs, the amount of the needed bandwith is given by: +- * Bw = Symbol_rate * (1 + 0.15) +- * As such, the maximum symbol rate supported by 6 MHz is +- * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds +- *NOTE: For ITU-T J.83 Annex C, the roll-off factor is 0.13. So: +- * max_symbol_rate = 6 MHz / 1.13 = 5309735 Baud +- * That means that an adjustment is needed for Japan, +- * but, as currently DRX-K is hardcoded to Annex A, let's stick +- * with 0.15 roll-off factor. +- */ +-#define MAX_SYMBOL_RATE_6MHz 5217391 +- +-#ifndef USE_API3 +-static int set_params(struct dvb_frontend *fe) +-#else +-static int set_params(struct dvb_frontend *fe, +- struct dvb_frontend_parameters *params) +-#endif +-{ +- struct tda_state *state = fe->tuner_priv; +- int status = 0; +- int Standard; +-#ifndef USE_API3 +- u32 bw = fe->dtv_property_cache.bandwidth_hz; +- u32 delsys = fe->dtv_property_cache.delivery_system; +- +- state->m_Frequency = fe->dtv_property_cache.frequency; +- +- switch (delsys) { +- case SYS_DVBT: +- case SYS_DVBT2: +- switch (bw) { +- case 6000000: +- Standard = HF_DVBT_6MHZ; +- break; +- case 7000000: +- Standard = HF_DVBT_7MHZ; +- break; +- case 8000000: +- Standard = HF_DVBT_8MHZ; +- break; +- default: +- return -EINVAL; +- } +- case SYS_DVBC_ANNEX_A: +- case SYS_DVBC_ANNEX_C: +- if (bw <= 6000000) +- Standard = HF_DVBC_6MHZ; +- else if (bw <= 7000000) +- Standard = HF_DVBC_7MHZ; +- else +- Standard = HF_DVBC_8MHZ; +- break; +- default: +- return -EINVAL; +- } +- do { +- status = RFTrackingFiltersCorrection(state, state->m_Frequency); +- if (status < 0) +- break; +- status = ChannelConfiguration(state, state->m_Frequency, +- Standard); +- if (status < 0) +- break; +- +- msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ +- } while (0); +-#else +- state->m_Frequency = params->frequency; +- +- if (fe->ops.info.type == FE_OFDM) +- switch (params->u.ofdm.bandwidth) { +- case BANDWIDTH_6_MHZ: +- Standard = HF_DVBT_6MHZ; +- break; +- case BANDWIDTH_7_MHZ: +- Standard = HF_DVBT_7MHZ; +- break; +- default: +- case BANDWIDTH_8_MHZ: +- Standard = HF_DVBT_8MHZ; +- break; +- } +- else if (fe->ops.info.type == FE_QAM) { +- if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) +- Standard = HF_DVBC_6MHZ; +- else +- Standard = HF_DVBC_8MHZ; +- } else +- return -EINVAL; +- do { +- status = RFTrackingFiltersCorrection(state, params->frequency); +- if (status < 0) +- break; +- status = ChannelConfiguration(state, params->frequency, Standard); +- if (status < 0) +- break; +- +- msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ +- } while (0); +-#endif +- return status; +-} +- +-#if 0 +-static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc) +-{ +- if (IFAgc < 500) { +- /* Scale this from 0 to 50000 */ +- *pSignalStrength = IFAgc * 100; +- } else { +- /* Scale range 500-1500 to 50000-80000 */ +- *pSignalStrength = 50000 + (IFAgc - 500) * 30; +- } +- +- return 0; +-} +-#endif +- +-static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency) +-{ +- struct tda_state *state = fe->tuner_priv; +- +- *frequency = state->IF; +- return 0; +-} +- +-static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +-{ +- /* struct tda_state *state = fe->tuner_priv; */ +- /* *bandwidth = priv->bandwidth; */ +- return 0; +-} +- +- +-static struct dvb_tuner_ops tuner_ops = { +- .info = { +- .name = "NXP TDA18271C2D", +- .frequency_min = 47125000, +- .frequency_max = 865000000, +- .frequency_step = 62500 +- }, +- .init = init, +- .sleep = sleep, +- .set_params = set_params, +- .release = release, +- .get_if_frequency = get_if_frequency, +- .get_bandwidth = get_bandwidth, +-}; +- +-struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, +- struct i2c_adapter *i2c, u8 adr) +-{ +- struct tda_state *state; +- +- state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); +- if (!state) +- return NULL; +- +- fe->tuner_priv = state; +- state->adr = adr; +- state->i2c = i2c; +- memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); +- reset(state); +- InitCal(state); +- +- return fe; +-} +-EXPORT_SYMBOL_GPL(tda18271c2dd_attach); +- +-MODULE_DESCRIPTION("TDA18271C2 driver"); +-MODULE_AUTHOR("DD"); +-MODULE_LICENSE("GPL"); ++/* ++ * tda18271c2dd: Driver for the TDA18271C2 tuner ++ * ++ * Copyright (C) 2010 Digital Devices GmbH ++ * ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 only, as published by the Free Software Foundation. ++ * ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA ++ * 02110-1301, USA ++ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dvb_frontend.h" ++ ++struct SStandardParam { ++ s32 m_IFFrequency; ++ u32 m_BandWidth; ++ u8 m_EP3_4_0; ++ u8 m_EB22; ++}; ++ ++struct SMap { ++ u32 m_Frequency; ++ u8 m_Param; ++}; ++ ++struct SMapI { ++ u32 m_Frequency; ++ s32 m_Param; ++}; ++ ++struct SMap2 { ++ u32 m_Frequency; ++ u8 m_Param1; ++ u8 m_Param2; ++}; ++ ++struct SRFBandMap { ++ u32 m_RF_max; ++ u32 m_RF1_Default; ++ u32 m_RF2_Default; ++ u32 m_RF3_Default; ++}; ++ ++enum ERegister { ++ ID = 0, ++ TM, ++ PL, ++ EP1, EP2, EP3, EP4, EP5, ++ CPD, CD1, CD2, CD3, ++ MPD, MD1, MD2, MD3, ++ EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10, ++ EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20, ++ EB21, EB22, EB23, ++ NUM_REGS ++}; ++ ++struct tda_state { ++ struct i2c_adapter *i2c; ++ u8 adr; ++ ++ u32 m_Frequency; ++ u32 IF; ++ ++ u8 m_IFLevelAnalog; ++ u8 m_IFLevelDigital; ++ u8 m_IFLevelDVBC; ++ u8 m_IFLevelDVBT; ++ ++ u8 m_EP4; ++ u8 m_EP3_Standby; ++ ++ bool m_bMaster; ++ ++ s32 m_SettlingTime; ++ ++ u8 m_Regs[NUM_REGS]; ++ ++ /* Tracking filter settings for band 0..6 */ ++ u32 m_RF1[7]; ++ s32 m_RF_A1[7]; ++ s32 m_RF_B1[7]; ++ u32 m_RF2[7]; ++ s32 m_RF_A2[7]; ++ s32 m_RF_B2[7]; ++ u32 m_RF3[7]; ++ ++ u8 m_TMValue_RFCal; /* Calibration temperatur */ ++ ++ bool m_bFMInput; /* true to use Pin 8 for FM Radio */ ++ ++}; ++ ++static int PowerScan(struct tda_state *state, ++ u8 RFBand, u32 RF_in, ++ u32 *pRF_Out, bool *pbcal); ++ ++static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) ++{ ++ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, ++ .buf = data, .len = len} }; ++ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; ++} ++ ++static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) ++{ ++ struct i2c_msg msg = {.addr = adr, .flags = 0, ++ .buf = data, .len = len}; ++ ++ if (i2c_transfer(adap, &msg, 1) != 1) { ++ printk(KERN_ERR "tda18271c2dd: i2c write error at addr %i\n", adr); ++ return -1; ++ } ++ return 0; ++} ++ ++static int WriteRegs(struct tda_state *state, ++ u8 SubAddr, u8 *Regs, u16 nRegs) ++{ ++ u8 data[nRegs+1]; ++ ++ data[0] = SubAddr; ++ memcpy(data + 1, Regs, nRegs); ++ return i2c_write(state->i2c, state->adr, data, nRegs+1); ++} ++ ++static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) ++{ ++ u8 msg[2] = {SubAddr, Reg}; ++ ++ return i2c_write(state->i2c, state->adr, msg, 2); ++} ++ ++static int Read(struct tda_state *state, u8 * Regs) ++{ ++ return i2c_readn(state->i2c, state->adr, Regs, 16); ++} ++ ++static int ReadExtented(struct tda_state *state, u8 * Regs) ++{ ++ return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS); ++} ++ ++static int UpdateRegs(struct tda_state *state, u8 RegFrom, u8 RegTo) ++{ ++ return WriteRegs(state, RegFrom, ++ &state->m_Regs[RegFrom], RegTo-RegFrom+1); ++} ++static int UpdateReg(struct tda_state *state, u8 Reg) ++{ ++ return WriteReg(state, Reg, state->m_Regs[Reg]); ++} ++ ++#include "tda18271c2dd_maps.h" ++ ++static void reset(struct tda_state *state) ++{ ++ u32 ulIFLevelAnalog = 0; ++ u32 ulIFLevelDigital = 2; ++ u32 ulIFLevelDVBC = 7; ++ u32 ulIFLevelDVBT = 6; ++ u32 ulXTOut = 0; ++ u32 ulStandbyMode = 0x06; /* Send in stdb, but leave osc on */ ++ u32 ulSlave = 0; ++ u32 ulFMInput = 0; ++ u32 ulSettlingTime = 100; ++ ++ state->m_Frequency = 0; ++ state->m_SettlingTime = 100; ++ state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2; ++ state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2; ++ state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2; ++ state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2; ++ ++ state->m_EP4 = 0x20; ++ if (ulXTOut != 0) ++ state->m_EP4 |= 0x40; ++ ++ state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F; ++ state->m_bMaster = (ulSlave == 0); ++ ++ state->m_SettlingTime = ulSettlingTime; ++ ++ state->m_bFMInput = (ulFMInput == 2); ++} ++ ++static bool SearchMap1(struct SMap Map[], ++ u32 Frequency, u8 *pParam) ++{ ++ int i = 0; ++ ++ while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency)) ++ i += 1; ++ if (Map[i].m_Frequency == 0) ++ return false; ++ *pParam = Map[i].m_Param; ++ return true; ++} ++ ++static bool SearchMap2(struct SMapI Map[], ++ u32 Frequency, s32 *pParam) ++{ ++ int i = 0; ++ ++ while ((Map[i].m_Frequency != 0) && ++ (Frequency > Map[i].m_Frequency)) ++ i += 1; ++ if (Map[i].m_Frequency == 0) ++ return false; ++ *pParam = Map[i].m_Param; ++ return true; ++} ++ ++static bool SearchMap3(struct SMap2 Map[], u32 Frequency, ++ u8 *pParam1, u8 *pParam2) ++{ ++ int i = 0; ++ ++ while ((Map[i].m_Frequency != 0) && ++ (Frequency > Map[i].m_Frequency)) ++ i += 1; ++ if (Map[i].m_Frequency == 0) ++ return false; ++ *pParam1 = Map[i].m_Param1; ++ *pParam2 = Map[i].m_Param2; ++ return true; ++} ++ ++static bool SearchMap4(struct SRFBandMap Map[], ++ u32 Frequency, u8 *pRFBand) ++{ ++ int i = 0; ++ ++ while (i < 7 && (Frequency > Map[i].m_RF_max)) ++ i += 1; ++ if (i == 7) ++ return false; ++ *pRFBand = i; ++ return true; ++} ++ ++static int ThermometerRead(struct tda_state *state, u8 *pTM_Value) ++{ ++ int status = 0; ++ ++ do { ++ u8 Regs[16]; ++ state->m_Regs[TM] |= 0x10; ++ status = UpdateReg(state, TM); ++ if (status < 0) ++ break; ++ status = Read(state, Regs); ++ if (status < 0) ++ break; ++ if (((Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20) || ++ ((Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00)) { ++ state->m_Regs[TM] ^= 0x20; ++ status = UpdateReg(state, TM); ++ if (status < 0) ++ break; ++ msleep(10); ++ status = Read(state, Regs); ++ if (status < 0) ++ break; ++ } ++ *pTM_Value = (Regs[TM] & 0x20) ++ ? m_Thermometer_Map_2[Regs[TM] & 0x0F] ++ : m_Thermometer_Map_1[Regs[TM] & 0x0F] ; ++ state->m_Regs[TM] &= ~0x10; /* Thermometer off */ ++ status = UpdateReg(state, TM); ++ if (status < 0) ++ break; ++ state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */ ++ status = UpdateReg(state, EP4); ++ if (status < 0) ++ break; ++ } while (0); ++ ++ return status; ++} ++ ++static int StandBy(struct tda_state *state) ++{ ++ int status = 0; ++ do { ++ state->m_Regs[EB12] &= ~0x20; /* PD_AGC1_Det = 0 */ ++ status = UpdateReg(state, EB12); ++ if (status < 0) ++ break; ++ state->m_Regs[EB18] &= ~0x83; /* AGC1_loop_off = 0, AGC1_Gain = 6 dB */ ++ status = UpdateReg(state, EB18); ++ if (status < 0) ++ break; ++ state->m_Regs[EB21] |= 0x03; /* AGC2_Gain = -6 dB */ ++ state->m_Regs[EP3] = state->m_EP3_Standby; ++ status = UpdateReg(state, EP3); ++ if (status < 0) ++ break; ++ state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LP_Fc[2] = 0 */ ++ status = UpdateRegs(state, EB21, EB23); ++ if (status < 0) ++ break; ++ } while (0); ++ return status; ++} ++ ++static int CalcMainPLL(struct tda_state *state, u32 freq) ++{ ++ ++ u8 PostDiv; ++ u8 Div; ++ u64 OscFreq; ++ u32 MainDiv; ++ ++ if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) ++ return -EINVAL; ++ ++ OscFreq = (u64) freq * (u64) Div; ++ OscFreq *= (u64) 16384; ++ do_div(OscFreq, (u64)16000000); ++ MainDiv = OscFreq; ++ ++ state->m_Regs[MPD] = PostDiv & 0x77; ++ state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F); ++ state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF); ++ state->m_Regs[MD3] = (MainDiv & 0xFF); ++ ++ return UpdateRegs(state, MPD, MD3); ++} ++ ++static int CalcCalPLL(struct tda_state *state, u32 freq) ++{ ++ u8 PostDiv; ++ u8 Div; ++ u64 OscFreq; ++ u32 CalDiv; ++ ++ if (!SearchMap3(m_Cal_PLL_Map, freq, &PostDiv, &Div)) ++ return -EINVAL; ++ ++ OscFreq = (u64)freq * (u64)Div; ++ /* CalDiv = u32( OscFreq * 16384 / 16000000 ); */ ++ OscFreq *= (u64)16384; ++ do_div(OscFreq, (u64)16000000); ++ CalDiv = OscFreq; ++ ++ state->m_Regs[CPD] = PostDiv; ++ state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF); ++ state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF); ++ state->m_Regs[CD3] = (CalDiv & 0xFF); ++ ++ return UpdateRegs(state, CPD, CD3); ++} ++ ++static int CalibrateRF(struct tda_state *state, ++ u8 RFBand, u32 freq, s32 *pCprog) ++{ ++ int status = 0; ++ u8 Regs[NUM_REGS]; ++ do { ++ u8 BP_Filter = 0; ++ u8 GainTaper = 0; ++ u8 RFC_K = 0; ++ u8 RFC_M = 0; ++ ++ state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */ ++ status = UpdateReg(state, EP4); ++ if (status < 0) ++ break; ++ state->m_Regs[EB18] |= 0x03; /* AGC1_Gain = 3 */ ++ status = UpdateReg(state, EB18); ++ if (status < 0) ++ break; ++ ++ /* Switching off LT (as datasheet says) causes calibration on C1 to fail */ ++ /* (Readout of Cprog is allways 255) */ ++ if (state->m_Regs[ID] != 0x83) /* C1: ID == 83, C2: ID == 84 */ ++ state->m_Regs[EP3] |= 0x40; /* SM_LT = 1 */ ++ ++ if (!(SearchMap1(m_BP_Filter_Map, freq, &BP_Filter) && ++ SearchMap1(m_GainTaper_Map, freq, &GainTaper) && ++ SearchMap3(m_KM_Map, freq, &RFC_K, &RFC_M))) ++ return -EINVAL; ++ ++ state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter; ++ state->m_Regs[EP2] = (RFBand << 5) | GainTaper; ++ ++ state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2); ++ ++ status = UpdateRegs(state, EP1, EP3); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EB13); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EB4] |= 0x20; /* LO_ForceSrce = 1 */ ++ status = UpdateReg(state, EB4); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EB7] |= 0x20; /* CAL_ForceSrce = 1 */ ++ status = UpdateReg(state, EB7); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EB14] = 0; /* RFC_Cprog = 0 */ ++ status = UpdateReg(state, EB14); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EB20] &= ~0x20; /* ForceLock = 0; */ ++ status = UpdateReg(state, EB20); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */ ++ status = UpdateRegs(state, EP4, EP5); ++ if (status < 0) ++ break; ++ ++ status = CalcCalPLL(state, freq); ++ if (status < 0) ++ break; ++ status = CalcMainPLL(state, freq + 1000000); ++ if (status < 0) ++ break; ++ ++ msleep(5); ++ status = UpdateReg(state, EP2); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EP1); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EP2); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EP1); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EB4] &= ~0x20; /* LO_ForceSrce = 0 */ ++ status = UpdateReg(state, EB4); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EB7] &= ~0x20; /* CAL_ForceSrce = 0 */ ++ status = UpdateReg(state, EB7); ++ if (status < 0) ++ break; ++ msleep(10); ++ ++ state->m_Regs[EB20] |= 0x20; /* ForceLock = 1; */ ++ status = UpdateReg(state, EB20); ++ if (status < 0) ++ break; ++ msleep(60); ++ ++ state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */ ++ state->m_Regs[EP3] &= ~0x40; /* SM_LT = 0 */ ++ state->m_Regs[EB18] &= ~0x03; /* AGC1_Gain = 0 */ ++ status = UpdateReg(state, EB18); ++ if (status < 0) ++ break; ++ status = UpdateRegs(state, EP3, EP4); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EP1); ++ if (status < 0) ++ break; ++ ++ status = ReadExtented(state, Regs); ++ if (status < 0) ++ break; ++ ++ *pCprog = Regs[EB14]; ++ ++ } while (0); ++ return status; ++} ++ ++static int RFTrackingFiltersInit(struct tda_state *state, ++ u8 RFBand) ++{ ++ int status = 0; ++ ++ u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default; ++ u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default; ++ u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default; ++ bool bcal = false; ++ ++ s32 Cprog_cal1 = 0; ++ s32 Cprog_table1 = 0; ++ s32 Cprog_cal2 = 0; ++ s32 Cprog_table2 = 0; ++ s32 Cprog_cal3 = 0; ++ s32 Cprog_table3 = 0; ++ ++ state->m_RF_A1[RFBand] = 0; ++ state->m_RF_B1[RFBand] = 0; ++ state->m_RF_A2[RFBand] = 0; ++ state->m_RF_B2[RFBand] = 0; ++ ++ do { ++ status = PowerScan(state, RFBand, RF1, &RF1, &bcal); ++ if (status < 0) ++ break; ++ if (bcal) { ++ status = CalibrateRF(state, RFBand, RF1, &Cprog_cal1); ++ if (status < 0) ++ break; ++ } ++ SearchMap2(m_RF_Cal_Map, RF1, &Cprog_table1); ++ if (!bcal) ++ Cprog_cal1 = Cprog_table1; ++ state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1; ++ /* state->m_RF_A1[RF_Band] = ???? */ ++ ++ if (RF2 == 0) ++ break; ++ ++ status = PowerScan(state, RFBand, RF2, &RF2, &bcal); ++ if (status < 0) ++ break; ++ if (bcal) { ++ status = CalibrateRF(state, RFBand, RF2, &Cprog_cal2); ++ if (status < 0) ++ break; ++ } ++ SearchMap2(m_RF_Cal_Map, RF2, &Cprog_table2); ++ if (!bcal) ++ Cprog_cal2 = Cprog_table2; ++ ++ state->m_RF_A1[RFBand] = ++ (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) / ++ ((s32)(RF2) - (s32)(RF1)); ++ ++ if (RF3 == 0) ++ break; ++ ++ status = PowerScan(state, RFBand, RF3, &RF3, &bcal); ++ if (status < 0) ++ break; ++ if (bcal) { ++ status = CalibrateRF(state, RFBand, RF3, &Cprog_cal3); ++ if (status < 0) ++ break; ++ } ++ SearchMap2(m_RF_Cal_Map, RF3, &Cprog_table3); ++ if (!bcal) ++ Cprog_cal3 = Cprog_table3; ++ state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3) - (s32)(RF2)); ++ state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2; ++ ++ } while (0); ++ ++ state->m_RF1[RFBand] = RF1; ++ state->m_RF2[RFBand] = RF2; ++ state->m_RF3[RFBand] = RF3; ++ ++#if 0 ++ printk(KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __func__, ++ RFBand, RF1, state->m_RF_A1[RFBand], state->m_RF_B1[RFBand], RF2, ++ state->m_RF_A2[RFBand], state->m_RF_B2[RFBand], RF3); ++#endif ++ ++ return status; ++} ++ ++static int PowerScan(struct tda_state *state, ++ u8 RFBand, u32 RF_in, u32 *pRF_Out, bool *pbcal) ++{ ++ int status = 0; ++ do { ++ u8 Gain_Taper = 0; ++ s32 RFC_Cprog = 0; ++ u8 CID_Target = 0; ++ u8 CountLimit = 0; ++ u32 freq_MainPLL; ++ u8 Regs[NUM_REGS]; ++ u8 CID_Gain; ++ s32 Count = 0; ++ int sign = 1; ++ bool wait = false; ++ ++ if (!(SearchMap2(m_RF_Cal_Map, RF_in, &RFC_Cprog) && ++ SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) && ++ SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) { ++ ++ printk(KERN_ERR "tda18271c2dd: %s Search map failed\n", __func__); ++ return -EINVAL; ++ } ++ ++ state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper; ++ state->m_Regs[EB14] = (RFC_Cprog); ++ status = UpdateReg(state, EP2); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EB14); ++ if (status < 0) ++ break; ++ ++ freq_MainPLL = RF_in + 1000000; ++ status = CalcMainPLL(state, freq_MainPLL); ++ if (status < 0) ++ break; ++ msleep(5); ++ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */ ++ status = UpdateReg(state, EP4); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EP2); /* Launch power measurement */ ++ if (status < 0) ++ break; ++ status = ReadExtented(state, Regs); ++ if (status < 0) ++ break; ++ CID_Gain = Regs[EB10] & 0x3F; ++ state->m_Regs[ID] = Regs[ID]; /* Chip version, (needed for C1 workarround in CalibrateRF) */ ++ ++ *pRF_Out = RF_in; ++ ++ while (CID_Gain < CID_Target) { ++ freq_MainPLL = RF_in + sign * Count + 1000000; ++ status = CalcMainPLL(state, freq_MainPLL); ++ if (status < 0) ++ break; ++ msleep(wait ? 5 : 1); ++ wait = false; ++ status = UpdateReg(state, EP2); /* Launch power measurement */ ++ if (status < 0) ++ break; ++ status = ReadExtented(state, Regs); ++ if (status < 0) ++ break; ++ CID_Gain = Regs[EB10] & 0x3F; ++ Count += 200000; ++ ++ if (Count < CountLimit * 100000) ++ continue; ++ if (sign < 0) ++ break; ++ ++ sign = -sign; ++ Count = 200000; ++ wait = true; ++ } ++ status = status; ++ if (status < 0) ++ break; ++ if (CID_Gain >= CID_Target) { ++ *pbcal = true; ++ *pRF_Out = freq_MainPLL - 1000000; ++ } else ++ *pbcal = false; ++ } while (0); ++ ++ return status; ++} ++ ++static int PowerScanInit(struct tda_state *state) ++{ ++ int status = 0; ++ do { ++ state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12; ++ state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */ ++ status = UpdateRegs(state, EP3, EP4); ++ if (status < 0) ++ break; ++ state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03); /* AGC 1 Gain = 0 */ ++ status = UpdateReg(state, EB18); ++ if (status < 0) ++ break; ++ state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03); /* AGC 2 Gain = 0 (Datasheet = 3) */ ++ state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06); /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ ++ status = UpdateRegs(state, EB21, EB23); ++ if (status < 0) ++ break; ++ } while (0); ++ return status; ++} ++ ++static int CalcRFFilterCurve(struct tda_state *state) ++{ ++ int status = 0; ++ do { ++ msleep(200); /* Temperature stabilisation */ ++ status = PowerScanInit(state); ++ if (status < 0) ++ break; ++ status = RFTrackingFiltersInit(state, 0); ++ if (status < 0) ++ break; ++ status = RFTrackingFiltersInit(state, 1); ++ if (status < 0) ++ break; ++ status = RFTrackingFiltersInit(state, 2); ++ if (status < 0) ++ break; ++ status = RFTrackingFiltersInit(state, 3); ++ if (status < 0) ++ break; ++ status = RFTrackingFiltersInit(state, 4); ++ if (status < 0) ++ break; ++ status = RFTrackingFiltersInit(state, 5); ++ if (status < 0) ++ break; ++ status = RFTrackingFiltersInit(state, 6); ++ if (status < 0) ++ break; ++ status = ThermometerRead(state, &state->m_TMValue_RFCal); /* also switches off Cal mode !!! */ ++ if (status < 0) ++ break; ++ } while (0); ++ ++ return status; ++} ++ ++static int FixedContentsI2CUpdate(struct tda_state *state) ++{ ++ static u8 InitRegs[] = { ++ 0x08, 0x80, 0xC6, ++ 0xDF, 0x16, 0x60, 0x80, ++ 0x80, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, ++ 0xFC, 0x01, 0x84, 0x41, ++ 0x01, 0x84, 0x40, 0x07, ++ 0x00, 0x00, 0x96, 0x3F, ++ 0xC1, 0x00, 0x8F, 0x00, ++ 0x00, 0x8C, 0x00, 0x20, ++ 0xB3, 0x48, 0xB0, ++ }; ++ int status = 0; ++ memcpy(&state->m_Regs[TM], InitRegs, EB23 - TM + 1); ++ do { ++ status = UpdateRegs(state, TM, EB23); ++ if (status < 0) ++ break; ++ ++ /* AGC1 gain setup */ ++ state->m_Regs[EB17] = 0x00; ++ status = UpdateReg(state, EB17); ++ if (status < 0) ++ break; ++ state->m_Regs[EB17] = 0x03; ++ status = UpdateReg(state, EB17); ++ if (status < 0) ++ break; ++ state->m_Regs[EB17] = 0x43; ++ status = UpdateReg(state, EB17); ++ if (status < 0) ++ break; ++ state->m_Regs[EB17] = 0x4C; ++ status = UpdateReg(state, EB17); ++ if (status < 0) ++ break; ++ ++ /* IRC Cal Low band */ ++ state->m_Regs[EP3] = 0x1F; ++ state->m_Regs[EP4] = 0x66; ++ state->m_Regs[EP5] = 0x81; ++ state->m_Regs[CPD] = 0xCC; ++ state->m_Regs[CD1] = 0x6C; ++ state->m_Regs[CD2] = 0x00; ++ state->m_Regs[CD3] = 0x00; ++ state->m_Regs[MPD] = 0xC5; ++ state->m_Regs[MD1] = 0x77; ++ state->m_Regs[MD2] = 0x08; ++ state->m_Regs[MD3] = 0x00; ++ status = UpdateRegs(state, EP2, MD3); /* diff between sw and datasheet (ep3-md3) */ ++ if (status < 0) ++ break; ++ ++#if 0 ++ state->m_Regs[EB4] = 0x61; /* missing in sw */ ++ status = UpdateReg(state, EB4); ++ if (status < 0) ++ break; ++ msleep(1); ++ state->m_Regs[EB4] = 0x41; ++ status = UpdateReg(state, EB4); ++ if (status < 0) ++ break; ++#endif ++ ++ msleep(5); ++ status = UpdateReg(state, EP1); ++ if (status < 0) ++ break; ++ msleep(5); ++ ++ state->m_Regs[EP5] = 0x85; ++ state->m_Regs[CPD] = 0xCB; ++ state->m_Regs[CD1] = 0x66; ++ state->m_Regs[CD2] = 0x70; ++ status = UpdateRegs(state, EP3, CD3); ++ if (status < 0) ++ break; ++ msleep(5); ++ status = UpdateReg(state, EP2); ++ if (status < 0) ++ break; ++ msleep(30); ++ ++ /* IRC Cal mid band */ ++ state->m_Regs[EP5] = 0x82; ++ state->m_Regs[CPD] = 0xA8; ++ state->m_Regs[CD2] = 0x00; ++ state->m_Regs[MPD] = 0xA1; /* Datasheet = 0xA9 */ ++ state->m_Regs[MD1] = 0x73; ++ state->m_Regs[MD2] = 0x1A; ++ status = UpdateRegs(state, EP3, MD3); ++ if (status < 0) ++ break; ++ ++ msleep(5); ++ status = UpdateReg(state, EP1); ++ if (status < 0) ++ break; ++ msleep(5); ++ ++ state->m_Regs[EP5] = 0x86; ++ state->m_Regs[CPD] = 0xA8; ++ state->m_Regs[CD1] = 0x66; ++ state->m_Regs[CD2] = 0xA0; ++ status = UpdateRegs(state, EP3, CD3); ++ if (status < 0) ++ break; ++ msleep(5); ++ status = UpdateReg(state, EP2); ++ if (status < 0) ++ break; ++ msleep(30); ++ ++ /* IRC Cal high band */ ++ state->m_Regs[EP5] = 0x83; ++ state->m_Regs[CPD] = 0x98; ++ state->m_Regs[CD1] = 0x65; ++ state->m_Regs[CD2] = 0x00; ++ state->m_Regs[MPD] = 0x91; /* Datasheet = 0x91 */ ++ state->m_Regs[MD1] = 0x71; ++ state->m_Regs[MD2] = 0xCD; ++ status = UpdateRegs(state, EP3, MD3); ++ if (status < 0) ++ break; ++ msleep(5); ++ status = UpdateReg(state, EP1); ++ if (status < 0) ++ break; ++ msleep(5); ++ state->m_Regs[EP5] = 0x87; ++ state->m_Regs[CD1] = 0x65; ++ state->m_Regs[CD2] = 0x50; ++ status = UpdateRegs(state, EP3, CD3); ++ if (status < 0) ++ break; ++ msleep(5); ++ status = UpdateReg(state, EP2); ++ if (status < 0) ++ break; ++ msleep(30); ++ ++ /* Back to normal */ ++ state->m_Regs[EP4] = 0x64; ++ status = UpdateReg(state, EP4); ++ if (status < 0) ++ break; ++ status = UpdateReg(state, EP1); ++ if (status < 0) ++ break; ++ ++ } while (0); ++ return status; ++} ++ ++static int InitCal(struct tda_state *state) ++{ ++ int status = 0; ++ ++ do { ++ status = FixedContentsI2CUpdate(state); ++ if (status < 0) ++ break; ++ status = CalcRFFilterCurve(state); ++ if (status < 0) ++ break; ++ status = StandBy(state); ++ if (status < 0) ++ break; ++ /* m_bInitDone = true; */ ++ } while (0); ++ return status; ++}; ++ ++static int RFTrackingFiltersCorrection(struct tda_state *state, ++ u32 Frequency) ++{ ++ int status = 0; ++ s32 Cprog_table; ++ u8 RFBand; ++ u8 dCoverdT; ++ ++ if (!SearchMap2(m_RF_Cal_Map, Frequency, &Cprog_table) || ++ !SearchMap4(m_RF_Band_Map, Frequency, &RFBand) || ++ !SearchMap1(m_RF_Cal_DC_Over_DT_Map, Frequency, &dCoverdT)) ++ ++ return -EINVAL; ++ ++ do { ++ u8 TMValue_Current; ++ u32 RF1 = state->m_RF1[RFBand]; ++ u32 RF2 = state->m_RF1[RFBand]; ++ u32 RF3 = state->m_RF1[RFBand]; ++ s32 RF_A1 = state->m_RF_A1[RFBand]; ++ s32 RF_B1 = state->m_RF_B1[RFBand]; ++ s32 RF_A2 = state->m_RF_A2[RFBand]; ++ s32 RF_B2 = state->m_RF_B2[RFBand]; ++ s32 Capprox = 0; ++ int TComp; ++ ++ state->m_Regs[EP3] &= ~0xE0; /* Power up */ ++ status = UpdateReg(state, EP3); ++ if (status < 0) ++ break; ++ ++ status = ThermometerRead(state, &TMValue_Current); ++ if (status < 0) ++ break; ++ ++ if (RF3 == 0 || Frequency < RF2) ++ Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table; ++ else ++ Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table; ++ ++ TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000; ++ ++ Capprox += TComp; ++ ++ if (Capprox < 0) ++ Capprox = 0; ++ else if (Capprox > 255) ++ Capprox = 255; ++ ++ ++ /* TODO Temperature compensation. There is defenitely a scale factor */ ++ /* missing in the datasheet, so leave it out for now. */ ++ state->m_Regs[EB14] = Capprox; ++ ++ status = UpdateReg(state, EB14); ++ if (status < 0) ++ break; ++ ++ } while (0); ++ return status; ++} ++ ++static int ChannelConfiguration(struct tda_state *state, ++ u32 Frequency, int Standard) ++{ ++ ++ s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency; ++ int status = 0; ++ ++ u8 BP_Filter = 0; ++ u8 RF_Band = 0; ++ u8 GainTaper = 0; ++ u8 IR_Meas = 0; ++ ++ state->IF = IntermediateFrequency; ++ /* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ ++ /* get values from tables */ ++ ++ if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) && ++ SearchMap1(m_GainTaper_Map, Frequency, &GainTaper) && ++ SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) && ++ SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) { ++ ++ printk(KERN_ERR "tda18271c2dd: %s SearchMap failed\n", __func__); ++ return -EINVAL; ++ } ++ ++ do { ++ state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0; ++ state->m_Regs[EP3] &= ~0x04; /* switch RFAGC to high speed mode */ ++ ++ /* m_EP4 default for XToutOn, CAL_Mode (0) */ ++ state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog); ++ /* state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; */ ++ if (Standard <= HF_AnalogMax) ++ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog; ++ else if (Standard <= HF_ATSC) ++ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT; ++ else if (Standard <= HF_DVBC) ++ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC; ++ else ++ state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; ++ ++ if ((Standard == HF_FM_Radio) && state->m_bFMInput) ++ state->m_Regs[EP4] |= 80; ++ ++ state->m_Regs[MPD] &= ~0x80; ++ if (Standard > HF_AnalogMax) ++ state->m_Regs[MPD] |= 0x80; /* Add IF_notch for digital */ ++ ++ state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22; ++ ++ /* Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM ) */ ++ if (Standard == HF_FM_Radio) ++ state->m_Regs[EB23] |= 0x06; /* ForceLP_Fc2_En = 1, LPFc[2] = 1 */ ++ else ++ state->m_Regs[EB23] &= ~0x06; /* ForceLP_Fc2_En = 0, LPFc[2] = 0 */ ++ ++ status = UpdateRegs(state, EB22, EB23); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; /* Dis_Power_level = 1, Filter */ ++ state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas; ++ state->m_Regs[EP2] = (RF_Band << 5) | GainTaper; ++ ++ state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) | ++ (state->m_bMaster ? 0x04 : 0x00); /* CALVCO_FortLOn = MS */ ++ /* AGC1_always_master = 0 */ ++ /* AGC_firstn = 0 */ ++ status = UpdateReg(state, EB1); ++ if (status < 0) ++ break; ++ ++ if (state->m_bMaster) { ++ status = CalcMainPLL(state, Frequency + IntermediateFrequency); ++ if (status < 0) ++ break; ++ status = UpdateRegs(state, TM, EP5); ++ if (status < 0) ++ break; ++ state->m_Regs[EB4] |= 0x20; /* LO_forceSrce = 1 */ ++ status = UpdateReg(state, EB4); ++ if (status < 0) ++ break; ++ msleep(1); ++ state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ ++ status = UpdateReg(state, EB4); ++ if (status < 0) ++ break; ++ } else { ++ u8 PostDiv = 0; ++ u8 Div; ++ status = CalcCalPLL(state, Frequency + IntermediateFrequency); ++ if (status < 0) ++ break; ++ ++ SearchMap3(m_Cal_PLL_Map, Frequency + IntermediateFrequency, &PostDiv, &Div); ++ state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77); ++ status = UpdateReg(state, MPD); ++ if (status < 0) ++ break; ++ status = UpdateRegs(state, TM, EP5); ++ if (status < 0) ++ break; ++ ++ state->m_Regs[EB7] |= 0x20; /* CAL_forceSrce = 1 */ ++ status = UpdateReg(state, EB7); ++ if (status < 0) ++ break; ++ msleep(1); ++ state->m_Regs[EB7] &= ~0x20; /* CAL_forceSrce = 0 */ ++ status = UpdateReg(state, EB7); ++ if (status < 0) ++ break; ++ } ++ msleep(20); ++ if (Standard != HF_FM_Radio) ++ state->m_Regs[EP3] |= 0x04; /* RFAGC to normal mode */ ++ status = UpdateReg(state, EP3); ++ if (status < 0) ++ break; ++ ++ } while (0); ++ return status; ++} ++ ++static int sleep(struct dvb_frontend *fe) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ ++ StandBy(state); ++ return 0; ++} ++ ++static int init(struct dvb_frontend *fe) ++{ ++ return 0; ++} ++ ++static int release(struct dvb_frontend *fe) ++{ ++ kfree(fe->tuner_priv); ++ fe->tuner_priv = NULL; ++ return 0; ++} ++ ++ ++static int set_params(struct dvb_frontend *fe) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ int status = 0; ++ int Standard; ++ u32 bw = fe->dtv_property_cache.bandwidth_hz; ++ u32 delsys = fe->dtv_property_cache.delivery_system; ++ ++ state->m_Frequency = fe->dtv_property_cache.frequency; ++ ++ switch (delsys) { ++ case SYS_DVBT: ++ case SYS_DVBT2: ++ switch (bw) { ++ case 6000000: ++ Standard = HF_DVBT_6MHZ; ++ break; ++ case 7000000: ++ Standard = HF_DVBT_7MHZ; ++ break; ++ case 8000000: ++ Standard = HF_DVBT_8MHZ; ++ break; ++ default: ++ return -EINVAL; ++ } ++ case SYS_DVBC_ANNEX_A: ++ case SYS_DVBC_ANNEX_C: ++ if (bw <= 6000000) ++ Standard = HF_DVBC_6MHZ; ++ else if (bw <= 7000000) ++ Standard = HF_DVBC_7MHZ; ++ else ++ Standard = HF_DVBC_8MHZ; ++ break; ++ default: ++ return -EINVAL; ++ } ++ do { ++ status = RFTrackingFiltersCorrection(state, state->m_Frequency); ++ if (status < 0) ++ break; ++ status = ChannelConfiguration(state, state->m_Frequency, ++ Standard); ++ if (status < 0) ++ break; ++ ++ msleep(state->m_SettlingTime); /* Allow AGC's to settle down */ ++ } while (0); ++ return status; ++} ++ ++#if 0 ++static int GetSignalStrength(s32 *pSignalStrength, u32 RFAgc, u32 IFAgc) ++{ ++ if (IFAgc < 500) { ++ /* Scale this from 0 to 50000 */ ++ *pSignalStrength = IFAgc * 100; ++ } else { ++ /* Scale range 500-1500 to 50000-80000 */ ++ *pSignalStrength = 50000 + (IFAgc - 500) * 30; ++ } ++ ++ return 0; ++} ++#endif ++ ++static int get_if_frequency(struct dvb_frontend *fe, u32 *frequency) ++{ ++ struct tda_state *state = fe->tuner_priv; ++ ++ *frequency = state->IF; ++ return 0; ++} ++ ++static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) ++{ ++ /* struct tda_state *state = fe->tuner_priv; */ ++ /* *bandwidth = priv->bandwidth; */ ++ return 0; ++} ++ ++ ++static struct dvb_tuner_ops tuner_ops = { ++ .info = { ++ .name = "NXP TDA18271C2D", ++ .frequency_min = 47125000, ++ .frequency_max = 865000000, ++ .frequency_step = 62500 ++ }, ++ .init = init, ++ .sleep = sleep, ++ .set_params = set_params, ++ .release = release, ++ .get_if_frequency = get_if_frequency, ++ .get_bandwidth = get_bandwidth, ++}; ++ ++struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, u8 adr) ++{ ++ struct tda_state *state; ++ ++ state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ ++ fe->tuner_priv = state; ++ state->adr = adr; ++ state->i2c = i2c; ++ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); ++ reset(state); ++ InitCal(state); ++ ++ return fe; ++} ++EXPORT_SYMBOL_GPL(tda18271c2dd_attach); ++ ++MODULE_DESCRIPTION("TDA18271C2 driver"); ++MODULE_AUTHOR("DD"); ++MODULE_LICENSE("GPL"); diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk_lockstatus_fix.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk_lockstatus_fix.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk_lockstatus_fix.diff 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/drxk_lockstatus_fix.diff 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,10 @@ +--- a/frontends/drxk_hard.c 2012-01-21 18:02:59.000000000 +0100 ++++ b/frontends/drxk_hard.c 2012-01-21 18:05:06.000000000 +0100 +@@ -1958,6 +1958,7 @@ static int GetLockStatus(struct drxk_sta + status = GetDVBTLockStatus(state, pLockStatus); + break; + default: ++ status = 0; + break; + } + error: diff -Nru dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/srcversion.diff dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/srcversion.diff --- dddvb-dkms-0.9.10.5yavdr0/dddvb-0.9.10.6yavdr0/patches/srcversion.diff 1970-01-01 00:00:00.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/dddvb-0.9.10.6yavdr0/patches/srcversion.diff 2013-11-12 21:18:00.000000000 +0000 @@ -0,0 +1,32 @@ +diff --git a/frontends/stv6110x.c b/frontends/stv6110x.c +index f36cab1..ed013d5 100644 +--- a/frontends/stv6110x.c ++++ b/frontends/stv6110x.c +@@ -36,6 +36,11 @@ static unsigned int verbose; + module_param(verbose, int, 0644); + MODULE_PARM_DESC(verbose, "Set Verbosity level"); + ++static int stv6110x_dummy_for_srcversion(void) ++{ ++ return 0; ++} ++ + static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data) + { + int ret; +diff --git a/frontends/lnbp21.c b/frontends/lnbp21.c +index 1343725..9098aee 100644 +--- a/frontends/lnbp21.c ++++ b/frontends/lnbp21.c +@@ -44,6 +44,11 @@ struct lnbp21 { + u8 i2c_addr; + }; + ++static int lnbp21_dummy_for_srcversion(void) ++{ ++ return 0; ++} ++ + static int lnbp21_set_voltage(struct dvb_frontend *fe, + fe_sec_voltage_t voltage) + { diff -Nru dddvb-dkms-0.9.10.5yavdr0/debian/changelog dddvb-dkms-0.9.10.6yavdr0/debian/changelog --- dddvb-dkms-0.9.10.5yavdr0/debian/changelog 2013-11-09 17:54:48.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/debian/changelog 2013-11-12 21:18:00.000000000 +0000 @@ -1,3 +1,9 @@ +dddvb-dkms (0.9.10.6yavdr0) precise; urgency=medium + + * stv090x: don't use DBVALS + + -- Lars Hanisch Tue, 12 Nov 2013 22:17:17 +0100 + dddvb-dkms (0.9.10.5yavdr0) precise; urgency=medium * add lnbp21 to srcversion.diff diff -Nru dddvb-dkms-0.9.10.5yavdr0/debian/prerm dddvb-dkms-0.9.10.6yavdr0/debian/prerm --- dddvb-dkms-0.9.10.5yavdr0/debian/prerm 2013-11-09 17:54:16.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/debian/prerm 2013-11-12 21:18:00.000000000 +0000 @@ -1,7 +1,7 @@ #!/bin/sh NAME=dddvb -VERSION=0.9.10.5yavdr0 +VERSION=0.9.10.6yavdr0 set -e diff -Nru dddvb-dkms-0.9.10.5yavdr0/debian/rules dddvb-dkms-0.9.10.6yavdr0/debian/rules --- dddvb-dkms-0.9.10.5yavdr0/debian/rules 2013-11-09 17:54:24.000000000 +0000 +++ dddvb-dkms-0.9.10.6yavdr0/debian/rules 2013-11-12 21:18:00.000000000 +0000 @@ -6,7 +6,7 @@ DEB_NAME=dddvb NAME=dddvb -VERSION=0.9.10.5yavdr0 +VERSION=0.9.10.6yavdr0 configure: configure-stamp configure-stamp: