Comment 140 for bug 160413

Hello everybody ....

So .... since it takes too long to get this fixed I tried to search in the RTL8168 datasheet ....

r8169.c contains the following ...

>static void rtl8169_asic_down(void __iomem *ioaddr)
>{
> RTL_W8(ChipCmd, 0x00);
> rtl8169_irq_mask_and_ack(ioaddr);
> RTL_R16(CPlusCmd);
>}

ChipCmd = 0x37

=============================================

rtl8168 datasheet contains the following ....

Command register - offset 0037h
---------------------------------
>bit 7-5 : -, -
Reserved

>bit 4 : RST, rw
Reset:Set this bit to 1 to force the RTL811B into a software reset state which disables the transmitter and receiver, reinitializes the FIFOs, and resets the system buffer pointer to the initial value (the start address of each descriptor group set in TNPDS, THPDS, and RDSAR registers). The values of IDR0-5, MAR0-7 and PCI configuration space will have no changes. This bit is 1 during the reset operation, and is self-cleared to 0 when the reset operation is complete.

>bit 3 : RE, rw
Receiver Enable

>bit 2 : TE, rw
Transmitter Enable

>bit 1-0 : -, -
Reserved

-----------

Therefore it looks like it simply disables the receiver, therefore the wake-up packets are ignored ...

Regards,
Jaromir.