distorm64 1.7.30-1 source package in Ubuntu


distorm64 (1.7.30-1) unstable; urgency=low

  * Initial release (closes: #652711).

 -- David Martínez Moreno <email address hidden>  Tue, 20 Dec 2011 00:49:32 -0800

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Uploaded by:
David Martínez Moreno on 2011-12-23
Uploaded to:
Original maintainer:
David Martínez Moreno
Low Urgency

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Series Pocket Published Component Section
Focal release on 2019-10-18 universe libs
Eoan release on 2019-04-18 universe libs
Disco release on 2018-10-30 universe libs
Cosmic release on 2018-05-01 universe libs
Bionic release on 2017-10-24 universe libs
Artful release on 2017-04-20 universe libs
Xenial release on 2015-10-22 universe libs
Trusty release on 2013-10-18 universe libs
Precise release on 2012-01-08 universe libs


File Size SHA-256 Checksum
distorm64_1.7.30-1.dsc 1.1 KiB d851915065907014ec470cdc3cf9ba627e088aaf2b0362dc10234196d0978a0a
distorm64_1.7.30.orig.tar.gz 112.9 KiB 98b218e5a436226c5fb30d3b27fcc435128b4e28557c44257ed2ba66bb1a9cf1
distorm64_1.7.30-1.debian.tar.gz 4.0 KiB 5c40d7bc71e52c5a32ab989994046bb9548ccdeef01ba3519a3b0325af2cc470

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Binary packages built by this source

libdistorm64-1: ultimate disassembler library for x86 code

 Distorm64 is a fast disassembler library for the x86-64 instruction set. Main
 features are:
  - It's really fast.
  - It supports multi-threading.
  - It supports AMD64, and all other 80x86 instruction sets.
  - It supports up to date instruction sets, such as VMX and SSE4.
  - It handles instruction prefixes in a serious manner.
  - Unused/extra prefixes are dropped (output as DB'ed).
  - Lock prefix works only on lockable instructions if the first operand is in
 the form of memory indirection.
  - REPn/z prefix works only on repeatable string instructions as well as I/O
  - Segment Override prefixes are possible where memory indirection address is
 being used (and specially treated with string and I/O instructions).
  - Some SSE2 instructions support pseudo opcodes (CMP family).
  - "Native" instructions, those which have the same mnemonic in different
 decoding modes, unless there's an operand size prefix, which then a suffix
 letter is concatenated to the mnemonic in order to indicate the operation size
 (instructions like: PUSHA, IRET, etc.).
  - XLAT instruction is treated specially when prefixed.
  - Drops invalid instructions when their operands are invalid.
  - Won't decode instructions which are longer than 15 bytes.
  - CR8 register is now accessible using the Lock prefix in 32 bits decoding
  - In 64-bit decoding mode the Segment Override prefixes CS, DS, ES and SS are

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