Comment 12 for bug 100114

Reading this extract from the HDA PRM in conjunction with azx_setup_controller() (note my ***...*** highlights) might suggest a problem with "...the hardware may still have pre-fetched descriptors that will not be flushed when the stream is restarted...":

4.6.6

After the RUN bit has been set, the buffer described by the BDL should not be changed by the
software. The hardware may pre-fetch and/or cache an arbitrary number of BDL Entries from the
list, so there is no way to ensure when or if any changes to the BDL list would be visible to the
hardware.
*** Even when the RUN bit has been cleared to pause the stream after it has been running,
the hardware may still have pre-fetched descriptors that will not be flushed when the stream is
restarted. Therefore, the software should only modify the BDL before the RUN bit has been set for
the first time after a Stream Reset. ***

 /* make sure the run bit is zero for SD */
 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
 /* reset stream */
 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
 udelay(3);
 timeout = 300;
 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
        --timeout)
  ;
 val &= ~SD_CTL_STREAM_RESET;
 azx_sd_writeb(azx_dev, SD_CTL, val);
 udelay(3);

 timeout = 300;
 /* waiting for hardware to report that the stream is out of reset */
 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
        --timeout);