Comment 4 for bug 2008745

As described in https://community.intel.com/t5/Blogs/Products-and-Solutions/HPC/Enabling-High-Bandwidth-Memory-for-HPC-and-AI-Applications-for/post/1335100,
for Intel Sapphire Rapids CPUs with HBM, it is possible to utilize the HBM as cache (so called "2LM mode"). It works in the way to create N fake NUMA domains in a size aligned the HBM so that HBM can act like direct-mapped L4 cache.

Since this is not really a "bug" (but is an officially proposed use case from Intel), it's not likely to provide a test case. But from HPE's testing of the test kernel from comment 2, there is improvement to performance on a Sapphire Rapids CPU with HBM.