verilator 3.820-2 source package in Ubuntu

Changelog

verilator (3.820-2) unstable; urgency=low

  * Cherry-picked Fix-PowerPC-runtime-error.patch from upstream VCS
    (Closes: #598256)
 -- ALEFHAHMEEMDAL ALEFLAMMEEMHAHMEEMWAWDALYEH (Ahmed El-Mahmoudy) <email address hidden>   Tue, 23 Aug 2011 13:15:42 +0200

Upload details

Uploaded by:
أحمد المحمودي (Ahmed El-Mahmoudy) on 2011-08-23
Uploaded to:
Oneiric
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Low Urgency

See full publishing history Publishing

Series Pocket Published Component Section

Downloads

File Size SHA-256 Checksum
verilator_3.820.orig.tar.gz 1.5 MiB 5e26bcbaf1f35e2d206073bbd42eeed4a7d088b24536275ff47ec310709c16d1
verilator_3.820-2.debian.tar.gz 8.5 KiB 5444aa537d1f1d47a468b4f73cda362121cc63ddb667235aa080ed6a3856cc23
verilator_3.820-2.dsc 1.6 KiB 91fc4a3e1011bb7902d448360465cf3947e44a932e7a451a6a39ed15a51502d7

Available diffs

View changes file

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.