verilator 3.855-1 source package in Ubuntu

Changelog

verilator (3.855-1) unstable; urgency=low


  * New upstream release.
  * Refreshed shebang.diff patch.
  * debian/copyright: update copyright years

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Mon, 27 Jan 2014 10:44:06 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2014-01-29
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Low Urgency

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Downloads

File Size SHA-256 Checksum
verilator_3.855-1.dsc 1.6 KiB 9e7b92336caf9d1a50cf94e397e8840bbc50f24ed3e5ad981055085c67553a39
verilator_3.855.orig.tar.gz 1.9 MiB adfded1d17fb7bb8d4188c299074014c993e3f91d6a5683be253ed096d3f1e9d
verilator_3.855-1.debian.tar.xz 6.8 KiB 44c666371bca9d2e39c02ba37f512609bb4427d505c7e4f6a711bc426f88459b

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.