verilator 3.914-2 source package in Ubuntu

Changelog

verilator (3.914-2) unstable; urgency=medium

  * fix_spelling.diff patch: remove a wrong fix

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Tue, 17 Oct 2017 05:05:20 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2017-10-17
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

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Series Pocket Published Component Section

Downloads

File Size SHA-256 Checksum
verilator_3.914-2.dsc 1.6 KiB c22572caa611246b46ed4ae45ef105d53240a4b90e2662fd997e579e676d2e19
verilator_3.914.orig.tar.gz 2.0 MiB 90058884e904ecc06cb0765399196b0016f6efb398c9cadb3122ab187b9bfb5f
verilator_3.914-2.debian.tar.xz 8.1 KiB 1b8d257e9c205cc6a964399471b4ffa5a633a78c2ec4e3f2111ae3aef4ca2ed5

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator