verilator 3.924-1 source package in Ubuntu

Changelog

verilator (3.924-1) unstable; urgency=medium

  [ Dima Kogan ]
  * Moved Vcs-... tags to point to salsa

  [ أحمد المحمودي (Ahmed El-Mahmoudy) ]
  * New upstream release
  * Refresh shebang.diff patch
  * Update standards version
  * Update copyright years
  * Remove autotools-dev from build deps
  * Bumped to compat level 11
  * Override dh_autoreconf to fix FTBFS

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Mon, 02 Jul 2018 14:08:42 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2018-07-02
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Cosmic release on 2018-07-02 universe electronics

Downloads

File Size SHA-256 Checksum
verilator_3.924-1.dsc 1.6 KiB a9450ca9c6990d56c53cb89ad338f9d74a938990b2ab6cd67c94d55452e8eb6a
verilator_3.924.orig.tar.gz 2.1 MiB 7dcb19711b8630ada59f0d3d7409faa9649e37bf4c53a0bbfcad32afb28b5975
verilator_3.924-1.debian.tar.xz 7.6 KiB bd12917f7385f488ba90953ce728acf1f42fc35e59823da13357fa9b41de241f

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator