verilator 4.016-3 source package in Ubuntu

Changelog

verilator (4.016-3) unstable; urgency=medium

  * Add system-flags.diff patch to honour system flags. (Closes: #931492)
    Thanks to Gianfranco Costamagna <email address hidden>

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 07 Jul 2019 02:53:30 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2019-07-09
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Eoan release on 2019-07-09 universe electronics

Downloads

File Size SHA-256 Checksum
verilator_4.016-3.dsc 1.6 KiB 2c9d3ceded6a79cf7df6617f73e9c007fcd99f611f10f0858be87e0a535cdc5f
verilator_4.016.orig.tar.gz 2.4 MiB 328a8f85c4fb0ecdabbf56e3c261485234dd1c28211e413101c533fdaea9d8a1
verilator_4.016-3.debian.tar.xz 9.7 KiB 52fe4499ff1931da846718f11c09a94095a6098fd628eb330f0149746db46dd6

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator