xc3sprog 0+svn795+dfsg-1 source package in Ubuntu

Changelog

xc3sprog (0+svn795+dfsg-1) unstable; urgency=medium

  * Initial release (Closes: #639956)
  * Enable CI for salsa
  * Fix copyright

 -- Ricardo Ribalda Delgado <email address hidden>  Mon, 14 Jan 2019 11:03:00 +0100

Upload details

Uploaded by:
Ricardo Ribalda Delgado on 2019-01-18
Uploaded to:
Sid
Original maintainer:
Ricardo Ribalda Delgado
Architectures:
any
Section:
misc
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Eoan release on 2019-04-18 universe misc
Disco release on 2019-01-19 universe misc

Downloads

File Size SHA-256 Checksum
xc3sprog_0+svn795+dfsg-1.dsc 1.9 KiB c3b21265a2ce1c57ea55a0d41ff0655cae0b6ecd6fa13269661dc4a88ac2641b
xc3sprog_0+svn795+dfsg.orig.tar.gz 247.1 KiB aacc9aa9601a199ea17a7d51df36da1e07462d39eee5c4e566b0c8ae58a8c027
xc3sprog_0+svn795+dfsg-1.debian.tar.xz 3.5 KiB f52a6d67b5e880b7c09073780c7e4ccf291d9d9da93a1218c8582cb6e46add75

No changes file available.

Binary packages built by this source

xc3sprog: JTAG flashing tool for FPGAs, CPLDs and EEPROMs

 xc3sprog is a suite of utilities for programming Xilinx FPGAs, CPLDs, and
 EEPROMs with the Xilinx Parallel Cable and other JTAG adapters under Linux.
 xc3sprog runs as a command-line application.
 .
 The main features include:
  - Reading a .BIT file from Xilinx design tools and programming it into an
    FPGA.
  - Reading a JEDEC file and programming it into a CPLD.
  - Programming a .BIT file into an on-board configuration PROM.
  - Programming a binary image into on-board SPI flash memory.
  - Reading the contents of a PROM chip back to a file.
  - Programming AVR microcontrollers.
 .
 The functionality of xc3sprog is similar to that of Xilinx IMPACT. There are
 also similarities with other free JTAG tools, such as UrJTAG. However,
 xc3sprog has a number of advantages:
 .
  - xc3sprog is free software.
  - It is a command-line tool.
  - It works on Linux without the need to install binary "cable-drivers".
    (Although some types of JTAG cables need to load firmware.)
  - It uses an optional configuration file to recognize new JTAG devices.
  - It contains programming algorithms for the supported devices, enabling
    the direct use of binary files (.BIT / JEDEC) from design tools (as opposed
    to intermediate SVF/STAPLE files).

xc3sprog-dbgsym: debug symbols for xc3sprog