yosys-plugin-ghdl 0.0~git20211127.09a32cd-2 source package in Ubuntu
Changelog
yosys-plugin-ghdl (0.0~git20211127.09a32cd-2) unstable; urgency=medium * Fix homepage link * Fix Vcs URLs * Add patch: Fix to block RAM handling -- Daniel Gröber <email address hidden> Thu, 15 Jun 2023 01:22:08 +0200
Upload details
- Uploaded by:
- Debian Electronics Team
- Uploaded to:
- Sid
- Original maintainer:
- Debian Electronics Team
- Architectures:
- any
- Section:
- misc
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section | |
|---|---|---|---|---|
| Mantic | release | universe | misc |
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| yosys-plugin-ghdl_0.0~git20211127.09a32cd-2.dsc | 2.2 KiB | dbea158909fae306846b0ebabefa013b3973ec552a6a12ce592eadb1db290095 |
| yosys-plugin-ghdl_0.0~git20211127.09a32cd.orig.tar.gz | 77.3 KiB | c224ca828487e774254ca85c1b70f32628447d2a1149099ce8876fe52937b6d4 |
| yosys-plugin-ghdl_0.0~git20211127.09a32cd-2.debian.tar.xz | 4.4 KiB | ae5605dc87d858426e0fc1969a529cd6675171fc768e743e4c020cee6b1c8e4c |
Available diffs
No changes file available.
Binary packages built by this source
- yosys-plugin-ghdl: VHDL to RTL synthesis plugin using GHDL
This yosys plugin allows running RTL synthesis from VHDL source code
instead of yosys' native Verilog.
.
This allows a full synthesis flow from VHDL to hardware for FPGAs where
the GHDL compiler is used to analyse the VHDL sources and yosys is used to
perform logic optimization, technology mapping and convertion to netlist
format.
- yosys-plugin-ghdl-dbgsym: debug symbols for yosys-plugin-ghdl
