Ubuntu
yosys package

yosys 0.23-6 source package in Ubuntu

Changelog

yosys (0.23-6) unstable; urgency=medium

  * Fix autotest error patch
  * Require berkeley-abc 1.01+20221019git70cb339+dfsg-3 to fix armhf

 -- Daniel Gröber <email address hidden>  Sat, 03 Dec 2022 23:15:20 +0100

Upload details

Uploaded by:
Debian Science Team
Uploaded to:
Sid
Original maintainer:
Debian Science Team
Architectures:
any all
Section:
misc
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Mantic release universe misc
Lunar release universe misc

Downloads

File Size SHA-256 Checksum
yosys_0.23-6.dsc 2.5 KiB 7ea97697e9838b880a111295424f24626fbee992623c5092d98c65505c56a535
yosys_0.23.orig.tar.gz 2.3 MiB ec982a9393b3217deecfbd3cf9a64109b85310a949e46a51cf2e07fba1071aeb
yosys_0.23-6.debian.tar.xz 17.6 KiB 024f699915338300764bb4f82fb2de764edeb1f383832c6f447e6056c909f089

Available diffs

No changes file available.

Binary packages built by this source

yosys: Framework for Verilog RTL synthesis

 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.

yosys-dbgsym: debug symbols for yosys
yosys-dev: Framework for Verilog RTL synthesis (development files)

 Yosys is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
 .
 This package contains the headers and programs needed to build yosys plugins.

yosys-doc: Documentation for Yosys

 Yosys is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
 .
 This package contains the manual.