Documentation for Yosys

 Yosys is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
 .
 This package contains the manual.