opensta binary package in Ubuntu Focal riscv64

 After synthesis, place and route of a digital circuit, it is necessary to
 verify the timing of the design. OpenSTA is a tool for doing exactly that. It
 has a Tcl interface for entering commands for analysing designs.
 .
 It typically takes as input a verilog netlist, a liberty file, and other
 parasitics information from the placed and routed design.

Source package