Binary package “opensta” in ubuntu mantic
Gate-level Static Timing Analyzer
After synthesis, place and route of a digital circuit, it is necessary to
verify the timing of the design. OpenSTA is a tool for doing exactly that. It
has a Tcl interface for entering commands for analysing designs.
.
It typically takes as input a verilog netlist, a liberty file, and other
parasitics information from the placed and routed design.
Published versions
- opensta 0~20191111gitc018cb2+dfsg-1build1 in amd64 (Release)
- opensta 0~20191111gitc018cb2+dfsg-1build1 in arm64 (Release)
- opensta 0~20191111gitc018cb2+dfsg-1build1 in armhf (Release)
- opensta 0~20191111gitc018cb2+dfsg-1build1 in ppc64el (Release)
- opensta 0~20191111gitc018cb2+dfsg-1build1 in riscv64 (Release)
- opensta 0~20191111gitc018cb2+dfsg-1build1 in s390x (Release)