yosys-plugin-ghdl binary package in Ubuntu Mantic arm64
This yosys plugin allows running RTL synthesis from VHDL source code
instead of yosys' native Verilog.
.
This allows a full synthesis flow from VHDL to hardware for FPGAs where
the GHDL compiler is used to analyse the VHDL sources and yosys is used to
perform logic optimization, technology mapping and convertion to netlist
format.
Publishing history
| Date | Status | Target | Component | Section | Priority | Phased updates | Version | ||
|---|---|---|---|---|---|---|---|---|---|
| 2023-06-15 09:14:13 UTC | Published | Ubuntu Mantic arm64 | release | universe | electronics | Optional | 0.0~git20211127.09a32cd-2 | ||
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| Deleted | Ubuntu Mantic arm64 | proposed | universe | electronics | Optional | 0.0~git20211127.09a32cd-2 | |||
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| 2023-06-15 09:14:14 UTC | Superseded | Ubuntu Mantic arm64 | release | universe | electronics | Optional | 0.0~git20211127.09a32cd-1 | ||
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| 2023-06-16 12:10:10 UTC | Deleted | Ubuntu Mantic arm64 | proposed | universe | electronics | Optional | 0.0~git20211127.09a32cd-1 | ||
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