Binary package “yosys-doc” in ubuntu noble
Framework for Verilog RTL synthesis (documentation)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
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Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
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This package contains the manual.
Source package
Published versions
- yosys-doc 0.23-6 in amd64 (Release)
- yosys-doc 0.33-5build2 in amd64 (Proposed)
- yosys-doc 0.33-5build2 in amd64 (Release)
- yosys-doc 0.23-6 in arm64 (Release)
- yosys-doc 0.33-5build2 in arm64 (Proposed)
- yosys-doc 0.33-5build2 in arm64 (Release)
- yosys-doc 0.23-6 in armhf (Release)
- yosys-doc 0.33-5build2 in armhf (Proposed)
- yosys-doc 0.33-5build2 in armhf (Release)
- yosys-doc 0.23-6 in i386 (Release)
- yosys-doc 0.33-5build2 in i386 (Proposed)
- yosys-doc 0.33-5build2 in i386 (Release)
- yosys-doc 0.23-6 in ppc64el (Release)
- yosys-doc 0.33-5build2 in ppc64el (Proposed)
- yosys-doc 0.33-5build2 in ppc64el (Release)
- yosys-doc 0.23-6 in riscv64 (Release)
- yosys-doc 0.33-5build2 in riscv64 (Proposed)
- yosys-doc 0.33-5build2 in riscv64 (Release)
- yosys-doc 0.23-6 in s390x (Release)
- yosys-doc 0.33-5build2 in s390x (Proposed)
- yosys-doc 0.33-5build2 in s390x (Release)