yosys binary package in Ubuntu Noble riscv64
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
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Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
Publishing history
| Date | Status | Target | Component | Section | Priority | Phased updates | Version | ||
|---|---|---|---|---|---|---|---|---|---|
| 2024-04-03 13:11:29 UTC | Published | Ubuntu Noble riscv64 | release | universe | electronics | Optional | 0.33-5build2 | ||
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| Deleted | Ubuntu Noble riscv64 | proposed | universe | electronics | Optional | 0.33-5build2 | |||
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| 2024-04-06 12:10:12 UTC | Deleted | Ubuntu Noble riscv64 | updates | universe | electronics | Optional | 0.33-5 | ||
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| 2024-04-03 13:24:57 UTC | Superseded | Ubuntu Noble riscv64 | release | universe | electronics | Optional | 0.33-5build1 | ||
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| 2024-04-04 18:10:15 UTC | Deleted | Ubuntu Noble riscv64 | proposed | universe | electronics | Optional | 0.33-5build1 | ||
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| 2024-03-16 09:41:02 UTC | Superseded | Ubuntu Noble riscv64 | proposed | universe | electronics | Optional | 0.33-5 | ||
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| 2024-03-29 03:56:46 UTC | Superseded | Ubuntu Noble riscv64 | release | universe | electronics | Optional | 0.23-6 | ||
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