[i915_bpo] Sync to 4.2-rc6

This bug is awaiting verification that the kernel in -proposed solves the problem. Please test the kernel and update this bug with the results. If the problem is solved, change the tag 'verification-needed-vivid' to 'verification-done-vivid'.

If verification is not done by 5 working days from today, this fix will be dropped from the source code, and this bug will be closed.

See https://wiki.ubuntu.com/Testing/EnableProposed for documentation how to enable and use -proposed. Thank you!

This bug was fixed in the package linux - 3.19.0-28.30

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linux (3.19.0-28.30) vivid; urgency=low

  [ Luis Henriques ]

  * Release Tracking Bug
    - LP: #1490606

  [ Gary Wang ]

  * SAUCE: i915_bpo: drm/i915: set CDCLK if DPLL0 enabled during resuming
    from S3
    - LP: #1490035

  [ Timo Aaltonen ]

  * Revert "SAUCE: i915_bpo: drm/i915/skl: DDI-E and DDI-A shares 4 lanes."
    - LP: #1490038

linux (3.19.0-27.29) vivid; urgency=low

  [ Brad Figg ]

  * Release Tracking Bug
    - LP: #1485113

  [ Adam Lee ]

  * SAUCE: serial: 8250_pci: Add support for Pericom PI7C9X795[1248]
    - LP: #1480142

  [ Arun Siluvery ]

  * SAUCE: i915_bpo: drm/i915/gen8: Add infrastructure to initialize WA
    batch buffers
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915/gen8: Re-order init pipe_control in lrc mode
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915/gen8: Add WaDisableCtxRestoreArbitration
    workaround
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915/gen8: Add
    WaFlushCoherentL3CacheLinesAtContextSwitch workaround
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915: Bail out early if WA batch is not available
    for given Gen
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch
    workaround
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915: Update
    WaFlushCoherentL3CacheLinesAtContextSwitch
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915: Enable WA batch buffers for Gen9
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915/gen9: Add WaDisableCtxRestoreArbitration
    workaround
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915: Update wa_ctx_emit() macro as per kernel
    coding guidelines
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915/gen9: Add
    WaFlushCoherentL3CacheLinesAtContextSwitch workaround
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915/gen9: Add
    WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915:skl: Add WaEnableGapsTsvCreditFix
    - LP: #1484486

  [ Chris Wilson ]

  * SAUCE: i915_bpo: drm/i915: Use two 32bit reads for select 64bit
    REG_READ ioctls
    - LP: #1484482
  * SAUCE: i915_bpo: drm/i915: Replace WARN inside I915_READ64_2x32 with
    retry loop
    - LP: #1484482
  * SAUCE: i915_bpo: drm/i915: Mark PIN_USER binding as GLOBAL_BIND without
    the aliasing ppgtt
    - LP: #1484482
  * SAUCE: i915_bpo: drm/i915: Declare the swizzling unknown for L-shaped
    configurations
    - LP: #1484482

  [ Damien Lespiau ]

  * SAUCE: i915_bpo: drm/i915/skl: Don't expose the top most plane on gen9
    display
    - LP: #1484486

  [ Daniel Vetter ]

  * SAUCE: i915_bpo: drm/i915: Fixup dp mst encoder selection
    - LP: #1484482

  [ David Weinehall ]

  * SAUCE: i915_bpo: drm/i915: Allow parsing of variable size child device
    entries from VBT
  * SAUCE: i915_bpo: drm/i915: Allow parsing of variable size child device
    entries from VBT, addendum v2
    - LP: #1484482

  [ Jani Nikula ]

  * SAUCE: i915_bpo: drm/i915/skl: WaIgnoreDDIAStrap is forever, always
    init DDI A
    - LP: #1484486
  * SAUCE: i915_bpo: drm/i915: reduce indent in i9xx_hpd_irq_handler
    - LP: #1484531
  * SAUCE: i915_bpo: drm/i91...