yosys 0.33-5 source package in Ubuntu
Changelog
yosys (0.33-5) unstable; urgency=medium * Fix pdflatex reproducibility -- Daniel Gröber <email address hidden> Sat, 23 Sep 2023 21:58:59 +0200
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- Uploaded by:
- Debian Science Team
- Uploaded to:
- Sid
- Original maintainer:
- Debian Science Team
- Architectures:
- any all
- Section:
- misc
- Urgency:
- Medium Urgency
See full publishing history Publishing
Series | Published | Component | Section |
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Downloads
File | Size | SHA-256 Checksum |
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yosys_0.33-5.dsc | 2.9 KiB | f15ab35d1453b9944fdd7fe3c17c40128816c7fc5649711304f38a03f878daef |
yosys_0.33.orig-abc.tar.gz | 5.9 MiB | 6559115f2bbf4f1aac86ae4edbae416e8c60b8998bb3ac552451f4283bf6a5a7 |
yosys_0.33.orig.tar.gz | 2.5 MiB | c240fa4fcc71c73b8989ab500f7bfa3109436fa1d7ba8d7e1028af4c42688f29 |
yosys_0.33-5.debian.tar.xz | 29.4 KiB | 268f618d6531f269f296c88fc6636301336e910a3508a997dd0b5434709ff597 |
No changes file available.
Binary packages built by this source
- yosys: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
- yosys-abc: Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic
circuits appearing in synchronous hardware designs. It combines scalable
logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
DAG-based technology mapping for look-up tables and standard cells, and
innovative algorithms for sequential synthesis and verification.
.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in
the yosys RTL synthesis framework.
- yosys-abc-dbgsym: debug symbols for yosys-abc
- yosys-dbgsym: debug symbols for yosys
- yosys-dev: Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the headers and programs needed to build yosys plugins.
- yosys-doc: Framework for Verilog RTL synthesis (documentation)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the manual.