pcb

pcb pcb-4.2.0

New feature release focusing on improvements to the DRC.

Milestone information

Project:
pcb
Series:
trunk
Version:
pcb-4.2.0
Released:
2019-02-01  
Registrant:
Bert Timmerman
Release registered:
2019-02-02
Active:
No. Drivers cannot target bugs and blueprints to this milestone.  

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Assigned to you:
No blueprints or bugs assigned to you.
Assignees:
3 Bert Timmerman, 13 Chad Parker, 1 Rob Spanton
Blueprints:
No blueprints are targeted to this milestone.
Bugs:
18 Fix Released

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Release notes 

Release notes for pcb-4.2.0

Dear Users,

This release introduces a file format change.

This is required by the improved routing style feature.

Kind regards,

The pcb development team.

Contributors
------------
The following authors contributed to this release:
- Charles Parker
- Rob Spanton
- Peter Clifton
- DJ Delorie
- Bert Timmerman

Please note that names are in no particular order and all e-mail
addresses have been removed for privacy.

User experience improvements
----------------------------
- Improved routing styles.
- Improved DRC testing.

Plugins
-------
- none

Exporters
---------
- Footprint attributes can now be added to the Bill of Materials [BOM]
  in a similar way as with gschem by defining attributes in a input
  file.
- XY output for Pick-and-Place now has proper values for non mm and mil
  units.

Footprints library
------------------
- none

Developer experience improvements
---------------------------------
- Batch has become the default UI (non-GUI) for 'make distcheck' in
  order to run regression tests without a GUI being in the way.
- Added regression tests.

Notes for packagers
-------------------
- For building packages with a GTK UI or a Lesstif UI, configure with
  the --with-gui=gtk or --with-gui=lesstif option (as usual).

Changed dependencies
--------------------
- none.

Changelog 

This release does not have a changelog.

0 blueprints and 18 bugs targeted

Bug report Importance Assignee Status
699234 #699234 DRC misses odd trace/poly clearance error 3 High Chad Parker  10 Fix Released
699245 #699245 DRC "minspace between pad and polygon" not triggerd! 4 Medium Chad Parker  10 Fix Released
699284 #699284 Draw w/auto drc during DRC causes crash 4 Medium Chad Parker  10 Fix Released
699445 #699445 Allow disabling of minimum overlap DRC checking 4 Medium Chad Parker  10 Fix Released
1229300 #1229300 DRC reports non-existent errors when using arcs for tracks 4 Medium Chad Parker  10 Fix Released
1394630 #1394630 locked object can be selected by the DRC operation 4 Medium Chad Parker  10 Fix Released
1744832 #1744832 Vias tented 4 Medium Chad Parker  10 Fix Released
1784755 #1784755 DRC Tests 4 Medium Chad Parker  10 Fix Released
1800707 #1800707 license check 4 Medium Bert Timmerman  10 Fix Released
1804564 #1804564 make check always builds and uses the gtkhid 4 Medium Chad Parker  10 Fix Released
1806044 #1806044 pick and place (xy) file export in dmil unit 4 Medium Bert Timmerman  10 Fix Released
1808656 #1808656 Tests that create new files may fail 4 Medium Chad Parker  10 Fix Released
1539882 #1539882 Cannot create a via with a copper annulus less than 0.0508mm 5 Low Rob Spanton  10 Fix Released
1800230 #1800230 Violating silk lines selected after running DRC 5 Low Chad Parker  10 Fix Released
1780674 #1780674 DRC HID 6 Wishlist Chad Parker  10 Fix Released
1808733 #1808733 [BOM HID] Attributes 6 Wishlist Bert Timmerman  10 Fix Released
1809332 #1809332 run_tests.sh enhancements 6 Wishlist Chad Parker  10 Fix Released
1364152 #1364152 PCB DRC incorrectly reports a clearance error 1 Undecided   10 Fix Released
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